STM32F769IDiscovery  1.00
uDANTE Audio Networking with STM32F7 DISCO board
stm32f769xx.h
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1 
52 #ifndef __STM32F769xx_H
53 #define __STM32F769xx_H
54 
55 #ifdef __cplusplus
56  extern "C" {
57 #endif /* __cplusplus */
58 
67 typedef enum
68 {
69 /****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/
70  NonMaskableInt_IRQn = -14,
71  MemoryManagement_IRQn = -12,
72  BusFault_IRQn = -11,
73  UsageFault_IRQn = -10,
74  SVCall_IRQn = -5,
75  DebugMonitor_IRQn = -4,
76  PendSV_IRQn = -2,
77  SysTick_IRQn = -1,
78 /****** STM32 specific Interrupt Numbers **********************************************************************/
79  WWDG_IRQn = 0,
80  PVD_IRQn = 1,
81  TAMP_STAMP_IRQn = 2,
82  RTC_WKUP_IRQn = 3,
83  FLASH_IRQn = 4,
84  RCC_IRQn = 5,
85  EXTI0_IRQn = 6,
86  EXTI1_IRQn = 7,
87  EXTI2_IRQn = 8,
88  EXTI3_IRQn = 9,
89  EXTI4_IRQn = 10,
90  DMA1_Stream0_IRQn = 11,
91  DMA1_Stream1_IRQn = 12,
92  DMA1_Stream2_IRQn = 13,
93  DMA1_Stream3_IRQn = 14,
94  DMA1_Stream4_IRQn = 15,
95  DMA1_Stream5_IRQn = 16,
96  DMA1_Stream6_IRQn = 17,
97  ADC_IRQn = 18,
98  CAN1_TX_IRQn = 19,
99  CAN1_RX0_IRQn = 20,
100  CAN1_RX1_IRQn = 21,
101  CAN1_SCE_IRQn = 22,
102  EXTI9_5_IRQn = 23,
103  TIM1_BRK_TIM9_IRQn = 24,
104  TIM1_UP_TIM10_IRQn = 25,
105  TIM1_TRG_COM_TIM11_IRQn = 26,
106  TIM1_CC_IRQn = 27,
107  TIM2_IRQn = 28,
108  TIM3_IRQn = 29,
109  TIM4_IRQn = 30,
110  I2C1_EV_IRQn = 31,
111  I2C1_ER_IRQn = 32,
112  I2C2_EV_IRQn = 33,
113  I2C2_ER_IRQn = 34,
114  SPI1_IRQn = 35,
115  SPI2_IRQn = 36,
116  USART1_IRQn = 37,
117  USART2_IRQn = 38,
118  USART3_IRQn = 39,
119  EXTI15_10_IRQn = 40,
120  RTC_Alarm_IRQn = 41,
121  OTG_FS_WKUP_IRQn = 42,
122  TIM8_BRK_TIM12_IRQn = 43,
123  TIM8_UP_TIM13_IRQn = 44,
124  TIM8_TRG_COM_TIM14_IRQn = 45,
125  TIM8_CC_IRQn = 46,
126  DMA1_Stream7_IRQn = 47,
127  FMC_IRQn = 48,
128  SDMMC1_IRQn = 49,
129  TIM5_IRQn = 50,
130  SPI3_IRQn = 51,
131  UART4_IRQn = 52,
132  UART5_IRQn = 53,
133  TIM6_DAC_IRQn = 54,
134  TIM7_IRQn = 55,
135  DMA2_Stream0_IRQn = 56,
136  DMA2_Stream1_IRQn = 57,
137  DMA2_Stream2_IRQn = 58,
138  DMA2_Stream3_IRQn = 59,
139  DMA2_Stream4_IRQn = 60,
140  ETH_IRQn = 61,
141  ETH_WKUP_IRQn = 62,
142  CAN2_TX_IRQn = 63,
143  CAN2_RX0_IRQn = 64,
144  CAN2_RX1_IRQn = 65,
145  CAN2_SCE_IRQn = 66,
146  OTG_FS_IRQn = 67,
147  DMA2_Stream5_IRQn = 68,
148  DMA2_Stream6_IRQn = 69,
149  DMA2_Stream7_IRQn = 70,
150  USART6_IRQn = 71,
151  I2C3_EV_IRQn = 72,
152  I2C3_ER_IRQn = 73,
153  OTG_HS_EP1_OUT_IRQn = 74,
154  OTG_HS_EP1_IN_IRQn = 75,
155  OTG_HS_WKUP_IRQn = 76,
156  OTG_HS_IRQn = 77,
157  DCMI_IRQn = 78,
158  RNG_IRQn = 80,
159  FPU_IRQn = 81,
160  UART7_IRQn = 82,
161  UART8_IRQn = 83,
162  SPI4_IRQn = 84,
163  SPI5_IRQn = 85,
164  SPI6_IRQn = 86,
165  SAI1_IRQn = 87,
166  LTDC_IRQn = 88,
167  LTDC_ER_IRQn = 89,
168  DMA2D_IRQn = 90,
169  SAI2_IRQn = 91,
170  QUADSPI_IRQn = 92,
171  LPTIM1_IRQn = 93,
172  CEC_IRQn = 94,
173  I2C4_EV_IRQn = 95,
174  I2C4_ER_IRQn = 96,
175  SPDIF_RX_IRQn = 97,
176  DSI_IRQn = 98,
177  DFSDM1_FLT0_IRQn = 99,
178  DFSDM1_FLT1_IRQn = 100,
179  DFSDM1_FLT2_IRQn = 101,
180  DFSDM1_FLT3_IRQn = 102,
181  SDMMC2_IRQn = 103,
182  CAN3_TX_IRQn = 104,
183  CAN3_RX0_IRQn = 105,
184  CAN3_RX1_IRQn = 106,
185  CAN3_SCE_IRQn = 107,
186  JPEG_IRQn = 108,
187  MDIOS_IRQn = 109
188 } IRQn_Type;
189 
197 #define __CM7_REV 0x0100U
198 #define __MPU_PRESENT 1
199 #define __NVIC_PRIO_BITS 4
200 #define __Vendor_SysTickConfig 0
201 #define __FPU_PRESENT 1
202 #define __ICACHE_PRESENT 1
203 #define __DCACHE_PRESENT 1
204 #include "core_cm7.h"
207 #include "system_stm32f7xx.h"
208 #include <stdint.h>
209 
218 typedef struct
219 {
220  __IO uint32_t SR;
221  __IO uint32_t CR1;
222  __IO uint32_t CR2;
223  __IO uint32_t SMPR1;
224  __IO uint32_t SMPR2;
225  __IO uint32_t JOFR1;
226  __IO uint32_t JOFR2;
227  __IO uint32_t JOFR3;
228  __IO uint32_t JOFR4;
229  __IO uint32_t HTR;
230  __IO uint32_t LTR;
231  __IO uint32_t SQR1;
232  __IO uint32_t SQR2;
233  __IO uint32_t SQR3;
234  __IO uint32_t JSQR;
235  __IO uint32_t JDR1;
236  __IO uint32_t JDR2;
237  __IO uint32_t JDR3;
238  __IO uint32_t JDR4;
239  __IO uint32_t DR;
240 } ADC_TypeDef;
241 
242 typedef struct
243 {
244  __IO uint32_t CSR;
245  __IO uint32_t CCR;
246  __IO uint32_t CDR;
248 } ADC_Common_TypeDef;
249 
250 
255 typedef struct
256 {
257  __IO uint32_t TIR;
258  __IO uint32_t TDTR;
259  __IO uint32_t TDLR;
260  __IO uint32_t TDHR;
261 } CAN_TxMailBox_TypeDef;
262 
267 typedef struct
268 {
269  __IO uint32_t RIR;
270  __IO uint32_t RDTR;
271  __IO uint32_t RDLR;
272  __IO uint32_t RDHR;
273 } CAN_FIFOMailBox_TypeDef;
274 
279 typedef struct
280 {
281  __IO uint32_t FR1;
282  __IO uint32_t FR2;
283 } CAN_FilterRegister_TypeDef;
284 
289 typedef struct
290 {
291  __IO uint32_t MCR;
292  __IO uint32_t MSR;
293  __IO uint32_t TSR;
294  __IO uint32_t RF0R;
295  __IO uint32_t RF1R;
296  __IO uint32_t IER;
297  __IO uint32_t ESR;
298  __IO uint32_t BTR;
299  uint32_t RESERVED0[88];
300  CAN_TxMailBox_TypeDef sTxMailBox[3];
301  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
302  uint32_t RESERVED1[12];
303  __IO uint32_t FMR;
304  __IO uint32_t FM1R;
305  uint32_t RESERVED2;
306  __IO uint32_t FS1R;
307  uint32_t RESERVED3;
308  __IO uint32_t FFA1R;
309  uint32_t RESERVED4;
310  __IO uint32_t FA1R;
311  uint32_t RESERVED5[8];
312  CAN_FilterRegister_TypeDef sFilterRegister[28];
313 } CAN_TypeDef;
314 
319 typedef struct
320 {
321  __IO uint32_t CR;
322  __IO uint32_t CFGR;
323  __IO uint32_t TXDR;
324  __IO uint32_t RXDR;
325  __IO uint32_t ISR;
326  __IO uint32_t IER;
327 }CEC_TypeDef;
328 
329 
334 typedef struct
335 {
336  __IO uint32_t DR;
337  __IO uint8_t IDR;
338  uint8_t RESERVED0;
339  uint16_t RESERVED1;
340  __IO uint32_t CR;
341  uint32_t RESERVED2;
342  __IO uint32_t INIT;
343  __IO uint32_t POL;
344 } CRC_TypeDef;
345 
350 typedef struct
351 {
352  __IO uint32_t CR;
353  __IO uint32_t SWTRIGR;
354  __IO uint32_t DHR12R1;
355  __IO uint32_t DHR12L1;
356  __IO uint32_t DHR8R1;
357  __IO uint32_t DHR12R2;
358  __IO uint32_t DHR12L2;
359  __IO uint32_t DHR8R2;
360  __IO uint32_t DHR12RD;
361  __IO uint32_t DHR12LD;
362  __IO uint32_t DHR8RD;
363  __IO uint32_t DOR1;
364  __IO uint32_t DOR2;
365  __IO uint32_t SR;
366 } DAC_TypeDef;
367 
371 typedef struct
372 {
373  __IO uint32_t FLTCR1;
374  __IO uint32_t FLTCR2;
375  __IO uint32_t FLTISR;
376  __IO uint32_t FLTICR;
377  __IO uint32_t FLTJCHGR;
378  __IO uint32_t FLTFCR;
379  __IO uint32_t FLTJDATAR;
380  __IO uint32_t FLTRDATAR;
381  __IO uint32_t FLTAWHTR;
382  __IO uint32_t FLTAWLTR;
383  __IO uint32_t FLTAWSR;
384  __IO uint32_t FLTAWCFR;
385  __IO uint32_t FLTEXMAX;
386  __IO uint32_t FLTEXMIN;
387  __IO uint32_t FLTCNVTIMR;
388 } DFSDM_Filter_TypeDef;
389 
393 typedef struct
394 {
395  __IO uint32_t CHCFGR1;
396  __IO uint32_t CHCFGR2;
397  __IO uint32_t CHAWSCDR;
399  __IO uint32_t CHWDATAR;
400  __IO uint32_t CHDATINR;
401 } DFSDM_Channel_TypeDef;
402 
407 typedef struct
408 {
409  __IO uint32_t IDCODE;
410  __IO uint32_t CR;
411  __IO uint32_t APB1FZ;
412  __IO uint32_t APB2FZ;
413 }DBGMCU_TypeDef;
414 
419 typedef struct
420 {
421  __IO uint32_t CR;
422  __IO uint32_t SR;
423  __IO uint32_t RISR;
424  __IO uint32_t IER;
425  __IO uint32_t MISR;
426  __IO uint32_t ICR;
427  __IO uint32_t ESCR;
428  __IO uint32_t ESUR;
429  __IO uint32_t CWSTRTR;
430  __IO uint32_t CWSIZER;
431  __IO uint32_t DR;
432 } DCMI_TypeDef;
433 
438 typedef struct
439 {
440  __IO uint32_t CR;
441  __IO uint32_t NDTR;
442  __IO uint32_t PAR;
443  __IO uint32_t M0AR;
444  __IO uint32_t M1AR;
445  __IO uint32_t FCR;
446 } DMA_Stream_TypeDef;
447 
448 typedef struct
449 {
450  __IO uint32_t LISR;
451  __IO uint32_t HISR;
452  __IO uint32_t LIFCR;
453  __IO uint32_t HIFCR;
454 } DMA_TypeDef;
455 
456 
461 typedef struct
462 {
463  __IO uint32_t CR;
464  __IO uint32_t ISR;
465  __IO uint32_t IFCR;
466  __IO uint32_t FGMAR;
467  __IO uint32_t FGOR;
468  __IO uint32_t BGMAR;
469  __IO uint32_t BGOR;
470  __IO uint32_t FGPFCCR;
471  __IO uint32_t FGCOLR;
472  __IO uint32_t BGPFCCR;
473  __IO uint32_t BGCOLR;
474  __IO uint32_t FGCMAR;
475  __IO uint32_t BGCMAR;
476  __IO uint32_t OPFCCR;
477  __IO uint32_t OCOLR;
478  __IO uint32_t OMAR;
479  __IO uint32_t OOR;
480  __IO uint32_t NLR;
481  __IO uint32_t LWR;
482  __IO uint32_t AMTCR;
483  uint32_t RESERVED[236];
484  __IO uint32_t FGCLUT[256];
485  __IO uint32_t BGCLUT[256];
486 } DMA2D_TypeDef;
487 
488 
493 typedef struct
494 {
495  __IO uint32_t MACCR;
496  __IO uint32_t MACFFR;
497  __IO uint32_t MACHTHR;
498  __IO uint32_t MACHTLR;
499  __IO uint32_t MACMIIAR;
500  __IO uint32_t MACMIIDR;
501  __IO uint32_t MACFCR;
502  __IO uint32_t MACVLANTR; /* 8 */
503  uint32_t RESERVED0[2];
504  __IO uint32_t MACRWUFFR; /* 11 */
505  __IO uint32_t MACPMTCSR;
506  uint32_t RESERVED1[2];
507  __IO uint32_t MACSR; /* 15 */
508  __IO uint32_t MACIMR;
509  __IO uint32_t MACA0HR;
510  __IO uint32_t MACA0LR;
511  __IO uint32_t MACA1HR;
512  __IO uint32_t MACA1LR;
513  __IO uint32_t MACA2HR;
514  __IO uint32_t MACA2LR;
515  __IO uint32_t MACA3HR;
516  __IO uint32_t MACA3LR; /* 24 */
517  uint32_t RESERVED2[40];
518  __IO uint32_t MMCCR; /* 65 */
519  __IO uint32_t MMCRIR;
520  __IO uint32_t MMCTIR;
521  __IO uint32_t MMCRIMR;
522  __IO uint32_t MMCTIMR; /* 69 */
523  uint32_t RESERVED3[14];
524  __IO uint32_t MMCTGFSCCR; /* 84 */
525  __IO uint32_t MMCTGFMSCCR;
526  uint32_t RESERVED4[5];
527  __IO uint32_t MMCTGFCR;
528  uint32_t RESERVED5[10];
529  __IO uint32_t MMCRFCECR;
530  __IO uint32_t MMCRFAECR;
531  uint32_t RESERVED6[10];
532  __IO uint32_t MMCRGUFCR;
533  uint32_t RESERVED7[334];
534  __IO uint32_t PTPTSCR;
535  __IO uint32_t PTPSSIR;
536  __IO uint32_t PTPTSHR;
537  __IO uint32_t PTPTSLR;
538  __IO uint32_t PTPTSHUR;
539  __IO uint32_t PTPTSLUR;
540  __IO uint32_t PTPTSAR;
541  __IO uint32_t PTPTTHR;
542  __IO uint32_t PTPTTLR;
543  __IO uint32_t RESERVED8;
544  __IO uint32_t PTPTSSR;
545  uint32_t RESERVED9[565];
546  __IO uint32_t DMABMR;
547  __IO uint32_t DMATPDR;
548  __IO uint32_t DMARPDR;
549  __IO uint32_t DMARDLAR;
550  __IO uint32_t DMATDLAR;
551  __IO uint32_t DMASR;
552  __IO uint32_t DMAOMR;
553  __IO uint32_t DMAIER;
554  __IO uint32_t DMAMFBOCR;
555  __IO uint32_t DMARSWTR;
556  uint32_t RESERVED10[8];
557  __IO uint32_t DMACHTDR;
558  __IO uint32_t DMACHRDR;
559  __IO uint32_t DMACHTBAR;
560  __IO uint32_t DMACHRBAR;
561 } ETH_TypeDef;
562 
567 typedef struct
568 {
569  __IO uint32_t IMR;
570  __IO uint32_t EMR;
571  __IO uint32_t RTSR;
572  __IO uint32_t FTSR;
573  __IO uint32_t SWIER;
574  __IO uint32_t PR;
575 } EXTI_TypeDef;
576 
581 typedef struct
582 {
583  __IO uint32_t ACR;
584  __IO uint32_t KEYR;
585  __IO uint32_t OPTKEYR;
586  __IO uint32_t SR;
587  __IO uint32_t CR;
588  __IO uint32_t OPTCR;
589  __IO uint32_t OPTCR1;
590 } FLASH_TypeDef;
591 
592 
593 
598 typedef struct
599 {
600  __IO uint32_t BTCR[8];
601 } FMC_Bank1_TypeDef;
602 
607 typedef struct
608 {
609  __IO uint32_t BWTR[7];
610 } FMC_Bank1E_TypeDef;
611 
616 typedef struct
617 {
618  __IO uint32_t PCR;
619  __IO uint32_t SR;
620  __IO uint32_t PMEM;
621  __IO uint32_t PATT;
622  uint32_t RESERVED0;
623  __IO uint32_t ECCR;
624 } FMC_Bank3_TypeDef;
625 
630 typedef struct
631 {
632  __IO uint32_t SDCR[2];
633  __IO uint32_t SDTR[2];
634  __IO uint32_t SDCMR;
635  __IO uint32_t SDRTR;
636  __IO uint32_t SDSR;
637 } FMC_Bank5_6_TypeDef;
638 
639 
644 typedef struct
645 {
646  __IO uint32_t MODER;
647  __IO uint32_t OTYPER;
648  __IO uint32_t OSPEEDR;
649  __IO uint32_t PUPDR;
650  __IO uint32_t IDR;
651  __IO uint32_t ODR;
652  __IO uint32_t BSRR;
653  __IO uint32_t LCKR;
654  __IO uint32_t AFR[2];
655 } GPIO_TypeDef;
656 
661 typedef struct
662 {
663  __IO uint32_t MEMRMP;
664  __IO uint32_t PMC;
665  __IO uint32_t EXTICR[4];
666  uint32_t RESERVED;
667  __IO uint32_t CBR;
668  __IO uint32_t CMPCR;
669 } SYSCFG_TypeDef;
670 
675 typedef struct
676 {
677  __IO uint32_t CR1;
678  __IO uint32_t CR2;
679  __IO uint32_t OAR1;
680  __IO uint32_t OAR2;
681  __IO uint32_t TIMINGR;
682  __IO uint32_t TIMEOUTR;
683  __IO uint32_t ISR;
684  __IO uint32_t ICR;
685  __IO uint32_t PECR;
686  __IO uint32_t RXDR;
687  __IO uint32_t TXDR;
688 } I2C_TypeDef;
689 
694 typedef struct
695 {
696  __IO uint32_t KR;
697  __IO uint32_t PR;
698  __IO uint32_t RLR;
699  __IO uint32_t SR;
700  __IO uint32_t WINR;
701 } IWDG_TypeDef;
702 
703 
708 typedef struct
709 {
710  uint32_t RESERVED0[2];
711  __IO uint32_t SSCR;
712  __IO uint32_t BPCR;
713  __IO uint32_t AWCR;
714  __IO uint32_t TWCR;
715  __IO uint32_t GCR;
716  uint32_t RESERVED1[2];
717  __IO uint32_t SRCR;
718  uint32_t RESERVED2[1];
719  __IO uint32_t BCCR;
720  uint32_t RESERVED3[1];
721  __IO uint32_t IER;
722  __IO uint32_t ISR;
723  __IO uint32_t ICR;
724  __IO uint32_t LIPCR;
725  __IO uint32_t CPSR;
726  __IO uint32_t CDSR;
727 } LTDC_TypeDef;
728 
733 typedef struct
734 {
735  __IO uint32_t CR;
736  __IO uint32_t WHPCR;
737  __IO uint32_t WVPCR;
738  __IO uint32_t CKCR;
739  __IO uint32_t PFCR;
740  __IO uint32_t CACR;
741  __IO uint32_t DCCR;
742  __IO uint32_t BFCR;
743  uint32_t RESERVED0[2];
744  __IO uint32_t CFBAR;
745  __IO uint32_t CFBLR;
746  __IO uint32_t CFBLNR;
747  uint32_t RESERVED1[3];
748  __IO uint32_t CLUTWR;
750 } LTDC_Layer_TypeDef;
751 
756 typedef struct
757 {
758  __IO uint32_t CR1;
759  __IO uint32_t CSR1;
760  __IO uint32_t CR2;
761  __IO uint32_t CSR2;
762 } PWR_TypeDef;
763 
764 
769 typedef struct
770 {
771  __IO uint32_t CR;
772  __IO uint32_t PLLCFGR;
773  __IO uint32_t CFGR;
774  __IO uint32_t CIR;
775  __IO uint32_t AHB1RSTR;
776  __IO uint32_t AHB2RSTR;
777  __IO uint32_t AHB3RSTR;
778  uint32_t RESERVED0;
779  __IO uint32_t APB1RSTR;
780  __IO uint32_t APB2RSTR;
781  uint32_t RESERVED1[2];
782  __IO uint32_t AHB1ENR;
783  __IO uint32_t AHB2ENR;
784  __IO uint32_t AHB3ENR;
785  uint32_t RESERVED2;
786  __IO uint32_t APB1ENR;
787  __IO uint32_t APB2ENR;
788  uint32_t RESERVED3[2];
789  __IO uint32_t AHB1LPENR;
790  __IO uint32_t AHB2LPENR;
791  __IO uint32_t AHB3LPENR;
792  uint32_t RESERVED4;
793  __IO uint32_t APB1LPENR;
794  __IO uint32_t APB2LPENR;
795  uint32_t RESERVED5[2];
796  __IO uint32_t BDCR;
797  __IO uint32_t CSR;
798  uint32_t RESERVED6[2];
799  __IO uint32_t SSCGR;
800  __IO uint32_t PLLI2SCFGR;
801  __IO uint32_t PLLSAICFGR;
802  __IO uint32_t DCKCFGR1;
803  __IO uint32_t DCKCFGR2;
805 } RCC_TypeDef;
806 
811 typedef struct
812 {
813  __IO uint32_t TR;
814  __IO uint32_t DR;
815  __IO uint32_t CR;
816  __IO uint32_t ISR;
817  __IO uint32_t PRER;
818  __IO uint32_t WUTR;
819  uint32_t reserved;
820  __IO uint32_t ALRMAR;
821  __IO uint32_t ALRMBR;
822  __IO uint32_t WPR;
823  __IO uint32_t SSR;
824  __IO uint32_t SHIFTR;
825  __IO uint32_t TSTR;
826  __IO uint32_t TSDR;
827  __IO uint32_t TSSSR;
828  __IO uint32_t CALR;
829  __IO uint32_t TAMPCR;
830  __IO uint32_t ALRMASSR;
831  __IO uint32_t ALRMBSSR;
832  __IO uint32_t OR;
833  __IO uint32_t BKP0R;
834  __IO uint32_t BKP1R;
835  __IO uint32_t BKP2R;
836  __IO uint32_t BKP3R;
837  __IO uint32_t BKP4R;
838  __IO uint32_t BKP5R;
839  __IO uint32_t BKP6R;
840  __IO uint32_t BKP7R;
841  __IO uint32_t BKP8R;
842  __IO uint32_t BKP9R;
843  __IO uint32_t BKP10R;
844  __IO uint32_t BKP11R;
845  __IO uint32_t BKP12R;
846  __IO uint32_t BKP13R;
847  __IO uint32_t BKP14R;
848  __IO uint32_t BKP15R;
849  __IO uint32_t BKP16R;
850  __IO uint32_t BKP17R;
851  __IO uint32_t BKP18R;
852  __IO uint32_t BKP19R;
853  __IO uint32_t BKP20R;
854  __IO uint32_t BKP21R;
855  __IO uint32_t BKP22R;
856  __IO uint32_t BKP23R;
857  __IO uint32_t BKP24R;
858  __IO uint32_t BKP25R;
859  __IO uint32_t BKP26R;
860  __IO uint32_t BKP27R;
861  __IO uint32_t BKP28R;
862  __IO uint32_t BKP29R;
863  __IO uint32_t BKP30R;
864  __IO uint32_t BKP31R;
865 } RTC_TypeDef;
866 
867 
872 typedef struct
873 {
874  __IO uint32_t GCR;
875 } SAI_TypeDef;
876 
877 typedef struct
878 {
879  __IO uint32_t CR1;
880  __IO uint32_t CR2;
881  __IO uint32_t FRCR;
882  __IO uint32_t SLOTR;
883  __IO uint32_t IMR;
884  __IO uint32_t SR;
885  __IO uint32_t CLRFR;
886  __IO uint32_t DR;
887 } SAI_Block_TypeDef;
888 
893 typedef struct
894 {
895  __IO uint32_t CR;
896  __IO uint32_t IMR;
897  __IO uint32_t SR;
898  __IO uint32_t IFCR;
899  __IO uint32_t DR;
900  __IO uint32_t CSR;
901  __IO uint32_t DIR;
902 } SPDIFRX_TypeDef;
903 
904 
909 typedef struct
910 {
911  __IO uint32_t POWER;
912  __IO uint32_t CLKCR;
913  __IO uint32_t ARG;
914  __IO uint32_t CMD;
915  __I uint32_t RESPCMD;
916  __I uint32_t RESP1;
917  __I uint32_t RESP2;
918  __I uint32_t RESP3;
919  __I uint32_t RESP4;
920  __IO uint32_t DTIMER;
921  __IO uint32_t DLEN;
922  __IO uint32_t DCTRL;
923  __I uint32_t DCOUNT;
924  __I uint32_t STA;
925  __IO uint32_t ICR;
926  __IO uint32_t MASK;
927  uint32_t RESERVED0[2];
928  __I uint32_t FIFOCNT;
929  uint32_t RESERVED1[13];
930  __IO uint32_t FIFO;
931 } SDMMC_TypeDef;
932 
937 typedef struct
938 {
939  __IO uint32_t CR1;
940  __IO uint32_t CR2;
941  __IO uint32_t SR;
942  __IO uint32_t DR;
943  __IO uint32_t CRCPR;
944  __IO uint32_t RXCRCR;
945  __IO uint32_t TXCRCR;
946  __IO uint32_t I2SCFGR;
947  __IO uint32_t I2SPR;
948 } SPI_TypeDef;
949 
954 typedef struct
955 {
956  __IO uint32_t CR;
957  __IO uint32_t DCR;
958  __IO uint32_t SR;
959  __IO uint32_t FCR;
960  __IO uint32_t DLR;
961  __IO uint32_t CCR;
962  __IO uint32_t AR;
963  __IO uint32_t ABR;
964  __IO uint32_t DR;
965  __IO uint32_t PSMKR;
966  __IO uint32_t PSMAR;
967  __IO uint32_t PIR;
968  __IO uint32_t LPTR;
969 } QUADSPI_TypeDef;
970 
975 typedef struct
976 {
977  __IO uint32_t CR1;
978  __IO uint32_t CR2;
979  __IO uint32_t SMCR;
980  __IO uint32_t DIER;
981  __IO uint32_t SR;
982  __IO uint32_t EGR;
983  __IO uint32_t CCMR1;
984  __IO uint32_t CCMR2;
985  __IO uint32_t CCER;
986  __IO uint32_t CNT;
987  __IO uint32_t PSC;
988  __IO uint32_t ARR;
989  __IO uint32_t RCR;
990  __IO uint32_t CCR1;
991  __IO uint32_t CCR2;
992  __IO uint32_t CCR3;
993  __IO uint32_t CCR4;
994  __IO uint32_t BDTR;
995  __IO uint32_t DCR;
996  __IO uint32_t DMAR;
997  __IO uint32_t OR;
998  __IO uint32_t CCMR3;
999  __IO uint32_t CCR5;
1000  __IO uint32_t CCR6;
1001  __IO uint32_t AF1;
1002  __IO uint32_t AF2;
1004 } TIM_TypeDef;
1005 
1009 typedef struct
1010 {
1011  __IO uint32_t ISR;
1012  __IO uint32_t ICR;
1013  __IO uint32_t IER;
1014  __IO uint32_t CFGR;
1015  __IO uint32_t CR;
1016  __IO uint32_t CMP;
1017  __IO uint32_t ARR;
1018  __IO uint32_t CNT;
1019 } LPTIM_TypeDef;
1020 
1021 
1026 typedef struct
1027 {
1028  __IO uint32_t CR1;
1029  __IO uint32_t CR2;
1030  __IO uint32_t CR3;
1031  __IO uint32_t BRR;
1032  __IO uint32_t GTPR;
1033  __IO uint32_t RTOR;
1034  __IO uint32_t RQR;
1035  __IO uint32_t ISR;
1036  __IO uint32_t ICR;
1037  __IO uint32_t RDR;
1038  __IO uint32_t TDR;
1039 } USART_TypeDef;
1040 
1041 
1046 typedef struct
1047 {
1048  __IO uint32_t CR;
1049  __IO uint32_t CFR;
1050  __IO uint32_t SR;
1051 } WWDG_TypeDef;
1052 
1053 
1058 typedef struct
1059 {
1060  __IO uint32_t CR;
1061  __IO uint32_t SR;
1062  __IO uint32_t DR;
1063 } RNG_TypeDef;
1064 
1072 typedef struct
1073 {
1074  __IO uint32_t GOTGCTL;
1075  __IO uint32_t GOTGINT;
1076  __IO uint32_t GAHBCFG;
1077  __IO uint32_t GUSBCFG;
1078  __IO uint32_t GRSTCTL;
1079  __IO uint32_t GINTSTS;
1080  __IO uint32_t GINTMSK;
1081  __IO uint32_t GRXSTSR;
1082  __IO uint32_t GRXSTSP;
1083  __IO uint32_t GRXFSIZ;
1084  __IO uint32_t DIEPTXF0_HNPTXFSIZ;
1085  __IO uint32_t HNPTXSTS;
1086  uint32_t Reserved30[2];
1087  __IO uint32_t GCCFG;
1088  __IO uint32_t CID;
1089  uint32_t Reserved5[3];
1090  __IO uint32_t GHWCFG3;
1091  uint32_t Reserved6;
1092  __IO uint32_t GLPMCFG;
1093  __IO uint32_t GPWRDN;
1094  __IO uint32_t GDFIFOCFG;
1095  __IO uint32_t GADPCTL;
1096  uint32_t Reserved43[39];
1097  __IO uint32_t HPTXFSIZ;
1098  __IO uint32_t DIEPTXF[0x0F];
1099 } USB_OTG_GlobalTypeDef;
1100 
1101 
1105 typedef struct
1106 {
1107  __IO uint32_t DCFG;
1108  __IO uint32_t DCTL;
1109  __IO uint32_t DSTS;
1110  uint32_t Reserved0C;
1111  __IO uint32_t DIEPMSK;
1112  __IO uint32_t DOEPMSK;
1113  __IO uint32_t DAINT;
1114  __IO uint32_t DAINTMSK;
1115  uint32_t Reserved20;
1116  uint32_t Reserved9;
1117  __IO uint32_t DVBUSDIS;
1118  __IO uint32_t DVBUSPULSE;
1119  __IO uint32_t DTHRCTL;
1120  __IO uint32_t DIEPEMPMSK;
1121  __IO uint32_t DEACHINT;
1122  __IO uint32_t DEACHMSK;
1123  uint32_t Reserved40;
1124  __IO uint32_t DINEP1MSK;
1125  uint32_t Reserved44[15];
1126  __IO uint32_t DOUTEP1MSK;
1127 } USB_OTG_DeviceTypeDef;
1128 
1129 
1133 typedef struct
1134 {
1135  __IO uint32_t DIEPCTL;
1136  uint32_t Reserved04;
1137  __IO uint32_t DIEPINT;
1138  uint32_t Reserved0C;
1139  __IO uint32_t DIEPTSIZ;
1140  __IO uint32_t DIEPDMA;
1141  __IO uint32_t DTXFSTS;
1142  uint32_t Reserved18;
1143 } USB_OTG_INEndpointTypeDef;
1144 
1145 
1149 typedef struct
1150 {
1151  __IO uint32_t DOEPCTL;
1152  uint32_t Reserved04;
1153  __IO uint32_t DOEPINT;
1154  uint32_t Reserved0C;
1155  __IO uint32_t DOEPTSIZ;
1156  __IO uint32_t DOEPDMA;
1157  uint32_t Reserved18[2];
1158 } USB_OTG_OUTEndpointTypeDef;
1159 
1160 
1164 typedef struct
1165 {
1166  __IO uint32_t HCFG;
1167  __IO uint32_t HFIR;
1168  __IO uint32_t HFNUM;
1169  uint32_t Reserved40C;
1170  __IO uint32_t HPTXSTS;
1171  __IO uint32_t HAINT;
1172  __IO uint32_t HAINTMSK;
1173 } USB_OTG_HostTypeDef;
1174 
1178 typedef struct
1179 {
1180  __IO uint32_t HCCHAR;
1181  __IO uint32_t HCSPLT;
1182  __IO uint32_t HCINT;
1183  __IO uint32_t HCINTMSK;
1184  __IO uint32_t HCTSIZ;
1185  __IO uint32_t HCDMA;
1186  uint32_t Reserved[2];
1187 } USB_OTG_HostChannelTypeDef;
1195 typedef struct
1196 {
1197  __IO uint32_t CONFR0;
1198  __IO uint32_t CONFR1;
1199  __IO uint32_t CONFR2;
1200  __IO uint32_t CONFR3;
1201  __IO uint32_t CONFR4;
1202  __IO uint32_t CONFR5;
1203  __IO uint32_t CONFR6;
1204  __IO uint32_t CONFR7;
1205  uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
1206  __IO uint32_t CR;
1207  __IO uint32_t SR;
1208  __IO uint32_t CFR;
1209  uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
1210  __IO uint32_t DIR;
1211  __IO uint32_t DOR;
1212  uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
1213  __IO uint32_t QMEM0[16];
1214  __IO uint32_t QMEM1[16];
1215  __IO uint32_t QMEM2[16];
1216  __IO uint32_t QMEM3[16];
1217  __IO uint32_t HUFFMIN[16];
1218  __IO uint32_t HUFFBASE[32];
1219  __IO uint32_t HUFFSYMB[84];
1220  __IO uint32_t DHTMEM[103];
1221  uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
1222  __IO uint32_t HUFFENC_AC0[88];
1223  __IO uint32_t HUFFENC_AC1[88];
1224  __IO uint32_t HUFFENC_DC0[8];
1225  __IO uint32_t HUFFENC_DC1[8];
1227 } JPEG_TypeDef;
1228 
1233 typedef struct
1234 {
1235  __IO uint32_t CR;
1236  __IO uint32_t WRFR;
1237  __IO uint32_t CWRFR;
1238  __IO uint32_t RDFR;
1239  __IO uint32_t CRDFR;
1240  __IO uint32_t SR;
1241  __IO uint32_t CLRFR;
1242  uint32_t RESERVED0[57]; /* Reserved Address offset: 1Ch */
1243  __IO uint32_t DINR0;
1244  __IO uint32_t DINR1;
1245  __IO uint32_t DINR2;
1246  __IO uint32_t DINR3;
1247  __IO uint32_t DINR4;
1248  __IO uint32_t DINR5;
1249  __IO uint32_t DINR6;
1250  __IO uint32_t DINR7;
1251  __IO uint32_t DINR8;
1252  __IO uint32_t DINR9;
1253  __IO uint32_t DINR10;
1254  __IO uint32_t DINR11;
1255  __IO uint32_t DINR12;
1256  __IO uint32_t DINR13;
1257  __IO uint32_t DINR14;
1258  __IO uint32_t DINR15;
1259  __IO uint32_t DINR16;
1260  __IO uint32_t DINR17;
1261  __IO uint32_t DINR18;
1262  __IO uint32_t DINR19;
1263  __IO uint32_t DINR20;
1264  __IO uint32_t DINR21;
1265  __IO uint32_t DINR22;
1266  __IO uint32_t DINR23;
1267  __IO uint32_t DINR24;
1268  __IO uint32_t DINR25;
1269  __IO uint32_t DINR26;
1270  __IO uint32_t DINR27;
1271  __IO uint32_t DINR28;
1272  __IO uint32_t DINR29;
1273  __IO uint32_t DINR30;
1274  __IO uint32_t DINR31;
1275  __IO uint32_t DOUTR0;
1276  __IO uint32_t DOUTR1;
1277  __IO uint32_t DOUTR2;
1278  __IO uint32_t DOUTR3;
1279  __IO uint32_t DOUTR4;
1280  __IO uint32_t DOUTR5;
1281  __IO uint32_t DOUTR6;
1282  __IO uint32_t DOUTR7;
1283  __IO uint32_t DOUTR8;
1284  __IO uint32_t DOUTR9;
1285  __IO uint32_t DOUTR10;
1286  __IO uint32_t DOUTR11;
1287  __IO uint32_t DOUTR12;
1288  __IO uint32_t DOUTR13;
1289  __IO uint32_t DOUTR14;
1290  __IO uint32_t DOUTR15;
1291  __IO uint32_t DOUTR16;
1292  __IO uint32_t DOUTR17;
1293  __IO uint32_t DOUTR18;
1294  __IO uint32_t DOUTR19;
1295  __IO uint32_t DOUTR20;
1296  __IO uint32_t DOUTR21;
1297  __IO uint32_t DOUTR22;
1298  __IO uint32_t DOUTR23;
1299  __IO uint32_t DOUTR24;
1300  __IO uint32_t DOUTR25;
1301  __IO uint32_t DOUTR26;
1302  __IO uint32_t DOUTR27;
1303  __IO uint32_t DOUTR28;
1304  __IO uint32_t DOUTR29;
1305  __IO uint32_t DOUTR30;
1306  __IO uint32_t DOUTR31;
1307 } MDIOS_TypeDef;
1308 
1313 typedef struct
1314 {
1315  __IO uint32_t VR;
1316  __IO uint32_t CR;
1317  __IO uint32_t CCR;
1318  __IO uint32_t LVCIDR;
1319  __IO uint32_t LCOLCR;
1320  __IO uint32_t LPCR;
1321  __IO uint32_t LPMCR;
1322  uint32_t RESERVED0[4];
1323  __IO uint32_t PCR;
1324  __IO uint32_t GVCIDR;
1325  __IO uint32_t MCR;
1326  __IO uint32_t VMCR;
1327  __IO uint32_t VPCR;
1328  __IO uint32_t VCCR;
1329  __IO uint32_t VNPCR;
1330  __IO uint32_t VHSACR;
1331  __IO uint32_t VHBPCR;
1332  __IO uint32_t VLCR;
1333  __IO uint32_t VVSACR;
1334  __IO uint32_t VVBPCR;
1335  __IO uint32_t VVFPCR;
1336  __IO uint32_t VVACR;
1337  __IO uint32_t LCCR;
1338  __IO uint32_t CMCR;
1339  __IO uint32_t GHCR;
1340  __IO uint32_t GPDR;
1341  __IO uint32_t GPSR;
1342  __IO uint32_t TCCR[6];
1343  __IO uint32_t TDCR;
1344  __IO uint32_t CLCR;
1345  __IO uint32_t CLTCR;
1346  __IO uint32_t DLTCR;
1347  __IO uint32_t PCTLR;
1348  __IO uint32_t PCONFR;
1349  __IO uint32_t PUCR;
1350  __IO uint32_t PTTCR;
1351  __IO uint32_t PSR;
1352  uint32_t RESERVED1[2];
1353  __IO uint32_t ISR[2];
1354  __IO uint32_t IER[2];
1355  uint32_t RESERVED2[3];
1356  __IO uint32_t FIR[2];
1357  uint32_t RESERVED3[8];
1358  __IO uint32_t VSCR;
1359  uint32_t RESERVED4[2];
1360  __IO uint32_t LCVCIDR;
1361  __IO uint32_t LCCCR;
1362  uint32_t RESERVED5;
1363  __IO uint32_t LPMCCR;
1364  uint32_t RESERVED6[7];
1365  __IO uint32_t VMCCR;
1366  __IO uint32_t VPCCR;
1367  __IO uint32_t VCCCR;
1368  __IO uint32_t VNPCCR;
1369  __IO uint32_t VHSACCR;
1370  __IO uint32_t VHBPCCR;
1371  __IO uint32_t VLCCR;
1372  __IO uint32_t VVSACCR;
1373  __IO uint32_t VVBPCCR;
1374  __IO uint32_t VVFPCCR;
1375  __IO uint32_t VVACCR;
1376  uint32_t RESERVED7[11];
1377  __IO uint32_t TDCCR;
1378  uint32_t RESERVED8[155];
1379  __IO uint32_t WCFGR;
1380  __IO uint32_t WCR;
1381  __IO uint32_t WIER;
1382  __IO uint32_t WISR;
1383  __IO uint32_t WIFCR;
1384  uint32_t RESERVED9;
1385  __IO uint32_t WPCR[5];
1386  uint32_t RESERVED10;
1387  __IO uint32_t WRPCR;
1388 } DSI_TypeDef;
1389 
1393 #define RAMITCM_BASE 0x00000000U
1394 #define FLASHITCM_BASE 0x00200000U
1395 #define FLASHAXI_BASE 0x08000000U
1396 #define RAMDTCM_BASE 0x20000000U
1397 #define PERIPH_BASE 0x40000000U
1398 #define BKPSRAM_BASE 0x40024000U
1399 #define QSPI_BASE 0x90000000U
1400 #define FMC_R_BASE 0xA0000000U
1401 #define QSPI_R_BASE 0xA0001000U
1402 #define SRAM1_BASE 0x20020000U
1403 #define SRAM2_BASE 0x2007C000U
1404 #define FLASH_END 0x081FFFFFU
1406 /* Legacy define */
1407 #define FLASH_BASE FLASHAXI_BASE
1408 
1410 #define APB1PERIPH_BASE PERIPH_BASE
1411 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
1412 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
1413 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
1414 
1416 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
1417 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
1418 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
1419 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
1420 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
1421 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
1422 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
1423 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
1424 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
1425 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
1426 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
1427 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
1428 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
1429 #define CAN3_BASE (APB1PERIPH_BASE + 0x3400U)
1430 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
1431 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
1432 #define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U)
1433 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
1434 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
1435 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
1436 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
1437 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
1438 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
1439 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
1440 #define I2C4_BASE (APB1PERIPH_BASE + 0x6000U)
1441 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
1442 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
1443 #define CEC_BASE (APB1PERIPH_BASE + 0x6C00U)
1444 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
1445 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
1446 #define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
1447 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
1448 
1450 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
1451 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
1452 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
1453 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
1454 #define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00U)
1455 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
1456 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
1457 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
1458 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
1459 #define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U)
1460 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1461 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
1462 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
1463 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
1464 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
1465 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
1466 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
1467 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
1468 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
1469 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
1470 #define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U)
1471 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
1472 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
1473 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004U)
1474 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024U)
1475 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
1476 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
1477 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
1478 #define DSI_BASE (APB2PERIPH_BASE + 0x6C00U)
1479 #define DFSDM1_BASE (APB2PERIPH_BASE + 0x7400U)
1480 #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U)
1481 #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U)
1482 #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U)
1483 #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U)
1484 #define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80U)
1485 #define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0U)
1486 #define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0U)
1487 #define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0U)
1488 #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U)
1489 #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)
1490 #define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200U)
1491 #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280U)
1492 #define MDIOS_BASE (APB2PERIPH_BASE + 0x7800U)
1493 
1494 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
1495 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
1496 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
1497 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
1498 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
1499 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
1500 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
1501 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
1502 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
1503 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
1504 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
1505 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1506 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
1507 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
1508 #define UID_BASE 0x1FF0F420U
1509 #define FLASHSIZE_BASE 0x1FF0F442U
1510 #define PACKAGESIZE_BASE 0x1FFF7BF0U
1511 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
1512 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
1513 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
1514 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
1515 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
1516 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
1517 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
1518 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
1519 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
1520 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
1521 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
1522 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
1523 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
1524 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
1525 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
1526 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
1527 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
1528 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
1529 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
1530 #define ETH_MAC_BASE (ETH_BASE)
1531 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
1532 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
1533 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
1534 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
1535 
1536 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
1537 #define JPEG_BASE (AHB2PERIPH_BASE + 0x51000U)
1538 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
1539 
1540 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
1541 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
1542 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
1543 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
1544 
1545 /* Debug MCU registers base address */
1546 #define DBGMCU_BASE 0xE0042000U
1547 
1549 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
1550 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
1551 
1552 #define USB_OTG_GLOBAL_BASE 0x000U
1553 #define USB_OTG_DEVICE_BASE 0x800U
1554 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
1555 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
1556 #define USB_OTG_EP_REG_SIZE 0x20U
1557 #define USB_OTG_HOST_BASE 0x400U
1558 #define USB_OTG_HOST_PORT_BASE 0x440U
1559 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
1560 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
1561 #define USB_OTG_PCGCCTL_BASE 0xE00U
1562 #define USB_OTG_FIFO_BASE 0x1000U
1563 #define USB_OTG_FIFO_SIZE 0x1000U
1564 
1572 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1573 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1574 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1575 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1576 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1577 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1578 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1579 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1580 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1581 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1582 #define RTC ((RTC_TypeDef *) RTC_BASE)
1583 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1584 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1585 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1586 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1587 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
1588 #define USART2 ((USART_TypeDef *) USART2_BASE)
1589 #define USART3 ((USART_TypeDef *) USART3_BASE)
1590 #define UART4 ((USART_TypeDef *) UART4_BASE)
1591 #define UART5 ((USART_TypeDef *) UART5_BASE)
1592 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1593 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1594 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1595 #define I2C4 ((I2C_TypeDef *) I2C4_BASE)
1596 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1597 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1598 #define CEC ((CEC_TypeDef *) CEC_BASE)
1599 #define PWR ((PWR_TypeDef *) PWR_BASE)
1600 #define DAC ((DAC_TypeDef *) DAC_BASE)
1601 #define UART7 ((USART_TypeDef *) UART7_BASE)
1602 #define UART8 ((USART_TypeDef *) UART8_BASE)
1603 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1604 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1605 #define USART1 ((USART_TypeDef *) USART1_BASE)
1606 #define USART6 ((USART_TypeDef *) USART6_BASE)
1607 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1608 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1609 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1610 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1611 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
1612 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1613 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1614 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1615 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1616 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1617 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1618 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1619 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1620 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
1621 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1622 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
1623 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1624 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1625 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
1626 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
1627 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
1628 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
1629 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
1630 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1631 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1632 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1633 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1634 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1635 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1636 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1637 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1638 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1639 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
1640 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
1641 #define CRC ((CRC_TypeDef *) CRC_BASE)
1642 #define RCC ((RCC_TypeDef *) RCC_BASE)
1643 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1644 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1645 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1646 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1647 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1648 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1649 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1650 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1651 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1652 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1653 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1654 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1655 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1656 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1657 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1658 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1659 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1660 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1661 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1662 #define ETH ((ETH_TypeDef *) ETH_BASE)
1663 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1664 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1665 #define RNG ((RNG_TypeDef *) RNG_BASE)
1666 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1667 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1668 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1669 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1670 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1671 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1672 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1673 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1674 #define CAN3 ((CAN_TypeDef *) CAN3_BASE)
1675 #define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
1676 #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
1677 #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
1678 #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
1679 #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
1680 #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
1681 #define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
1682 #define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
1683 #define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
1684 #define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
1685 #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
1686 #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
1687 #define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
1688 #define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
1689 #define JPEG ((JPEG_TypeDef *) JPEG_BASE)
1690 #define DSI ((DSI_TypeDef *)DSI_BASE)
1691 
1704 /******************************************************************************/
1705 /* Peripheral Registers_Bits_Definition */
1706 /******************************************************************************/
1707 
1708 /******************************************************************************/
1709 /* */
1710 /* Analog to Digital Converter */
1711 /* */
1712 /******************************************************************************/
1713 /******************** Bit definition for ADC_SR register ********************/
1714 #define ADC_SR_AWD 0x00000001U
1715 #define ADC_SR_EOC 0x00000002U
1716 #define ADC_SR_JEOC 0x00000004U
1717 #define ADC_SR_JSTRT 0x00000008U
1718 #define ADC_SR_STRT 0x00000010U
1719 #define ADC_SR_OVR 0x00000020U
1721 /******************* Bit definition for ADC_CR1 register ********************/
1722 #define ADC_CR1_AWDCH 0x0000001FU
1723 #define ADC_CR1_AWDCH_0 0x00000001U
1724 #define ADC_CR1_AWDCH_1 0x00000002U
1725 #define ADC_CR1_AWDCH_2 0x00000004U
1726 #define ADC_CR1_AWDCH_3 0x00000008U
1727 #define ADC_CR1_AWDCH_4 0x00000010U
1728 #define ADC_CR1_EOCIE 0x00000020U
1729 #define ADC_CR1_AWDIE 0x00000040U
1730 #define ADC_CR1_JEOCIE 0x00000080U
1731 #define ADC_CR1_SCAN 0x00000100U
1732 #define ADC_CR1_AWDSGL 0x00000200U
1733 #define ADC_CR1_JAUTO 0x00000400U
1734 #define ADC_CR1_DISCEN 0x00000800U
1735 #define ADC_CR1_JDISCEN 0x00001000U
1736 #define ADC_CR1_DISCNUM 0x0000E000U
1737 #define ADC_CR1_DISCNUM_0 0x00002000U
1738 #define ADC_CR1_DISCNUM_1 0x00004000U
1739 #define ADC_CR1_DISCNUM_2 0x00008000U
1740 #define ADC_CR1_JAWDEN 0x00400000U
1741 #define ADC_CR1_AWDEN 0x00800000U
1742 #define ADC_CR1_RES 0x03000000U
1743 #define ADC_CR1_RES_0 0x01000000U
1744 #define ADC_CR1_RES_1 0x02000000U
1745 #define ADC_CR1_OVRIE 0x04000000U
1747 /******************* Bit definition for ADC_CR2 register ********************/
1748 #define ADC_CR2_ADON 0x00000001U
1749 #define ADC_CR2_CONT 0x00000002U
1750 #define ADC_CR2_DMA 0x00000100U
1751 #define ADC_CR2_DDS 0x00000200U
1752 #define ADC_CR2_EOCS 0x00000400U
1753 #define ADC_CR2_ALIGN 0x00000800U
1754 #define ADC_CR2_JEXTSEL 0x000F0000U
1755 #define ADC_CR2_JEXTSEL_0 0x00010000U
1756 #define ADC_CR2_JEXTSEL_1 0x00020000U
1757 #define ADC_CR2_JEXTSEL_2 0x00040000U
1758 #define ADC_CR2_JEXTSEL_3 0x00080000U
1759 #define ADC_CR2_JEXTEN 0x00300000U
1760 #define ADC_CR2_JEXTEN_0 0x00100000U
1761 #define ADC_CR2_JEXTEN_1 0x00200000U
1762 #define ADC_CR2_JSWSTART 0x00400000U
1763 #define ADC_CR2_EXTSEL 0x0F000000U
1764 #define ADC_CR2_EXTSEL_0 0x01000000U
1765 #define ADC_CR2_EXTSEL_1 0x02000000U
1766 #define ADC_CR2_EXTSEL_2 0x04000000U
1767 #define ADC_CR2_EXTSEL_3 0x08000000U
1768 #define ADC_CR2_EXTEN 0x30000000U
1769 #define ADC_CR2_EXTEN_0 0x10000000U
1770 #define ADC_CR2_EXTEN_1 0x20000000U
1771 #define ADC_CR2_SWSTART 0x40000000U
1773 /****************** Bit definition for ADC_SMPR1 register *******************/
1774 #define ADC_SMPR1_SMP10 0x00000007U
1775 #define ADC_SMPR1_SMP10_0 0x00000001U
1776 #define ADC_SMPR1_SMP10_1 0x00000002U
1777 #define ADC_SMPR1_SMP10_2 0x00000004U
1778 #define ADC_SMPR1_SMP11 0x00000038U
1779 #define ADC_SMPR1_SMP11_0 0x00000008U
1780 #define ADC_SMPR1_SMP11_1 0x00000010U
1781 #define ADC_SMPR1_SMP11_2 0x00000020U
1782 #define ADC_SMPR1_SMP12 0x000001C0U
1783 #define ADC_SMPR1_SMP12_0 0x00000040U
1784 #define ADC_SMPR1_SMP12_1 0x00000080U
1785 #define ADC_SMPR1_SMP12_2 0x00000100U
1786 #define ADC_SMPR1_SMP13 0x00000E00U
1787 #define ADC_SMPR1_SMP13_0 0x00000200U
1788 #define ADC_SMPR1_SMP13_1 0x00000400U
1789 #define ADC_SMPR1_SMP13_2 0x00000800U
1790 #define ADC_SMPR1_SMP14 0x00007000U
1791 #define ADC_SMPR1_SMP14_0 0x00001000U
1792 #define ADC_SMPR1_SMP14_1 0x00002000U
1793 #define ADC_SMPR1_SMP14_2 0x00004000U
1794 #define ADC_SMPR1_SMP15 0x00038000U
1795 #define ADC_SMPR1_SMP15_0 0x00008000U
1796 #define ADC_SMPR1_SMP15_1 0x00010000U
1797 #define ADC_SMPR1_SMP15_2 0x00020000U
1798 #define ADC_SMPR1_SMP16 0x001C0000U
1799 #define ADC_SMPR1_SMP16_0 0x00040000U
1800 #define ADC_SMPR1_SMP16_1 0x00080000U
1801 #define ADC_SMPR1_SMP16_2 0x00100000U
1802 #define ADC_SMPR1_SMP17 0x00E00000U
1803 #define ADC_SMPR1_SMP17_0 0x00200000U
1804 #define ADC_SMPR1_SMP17_1 0x00400000U
1805 #define ADC_SMPR1_SMP17_2 0x00800000U
1806 #define ADC_SMPR1_SMP18 0x07000000U
1807 #define ADC_SMPR1_SMP18_0 0x01000000U
1808 #define ADC_SMPR1_SMP18_1 0x02000000U
1809 #define ADC_SMPR1_SMP18_2 0x04000000U
1811 /****************** Bit definition for ADC_SMPR2 register *******************/
1812 #define ADC_SMPR2_SMP0 0x00000007U
1813 #define ADC_SMPR2_SMP0_0 0x00000001U
1814 #define ADC_SMPR2_SMP0_1 0x00000002U
1815 #define ADC_SMPR2_SMP0_2 0x00000004U
1816 #define ADC_SMPR2_SMP1 0x00000038U
1817 #define ADC_SMPR2_SMP1_0 0x00000008U
1818 #define ADC_SMPR2_SMP1_1 0x00000010U
1819 #define ADC_SMPR2_SMP1_2 0x00000020U
1820 #define ADC_SMPR2_SMP2 0x000001C0U
1821 #define ADC_SMPR2_SMP2_0 0x00000040U
1822 #define ADC_SMPR2_SMP2_1 0x00000080U
1823 #define ADC_SMPR2_SMP2_2 0x00000100U
1824 #define ADC_SMPR2_SMP3 0x00000E00U
1825 #define ADC_SMPR2_SMP3_0 0x00000200U
1826 #define ADC_SMPR2_SMP3_1 0x00000400U
1827 #define ADC_SMPR2_SMP3_2 0x00000800U
1828 #define ADC_SMPR2_SMP4 0x00007000U
1829 #define ADC_SMPR2_SMP4_0 0x00001000U
1830 #define ADC_SMPR2_SMP4_1 0x00002000U
1831 #define ADC_SMPR2_SMP4_2 0x00004000U
1832 #define ADC_SMPR2_SMP5 0x00038000U
1833 #define ADC_SMPR2_SMP5_0 0x00008000U
1834 #define ADC_SMPR2_SMP5_1 0x00010000U
1835 #define ADC_SMPR2_SMP5_2 0x00020000U
1836 #define ADC_SMPR2_SMP6 0x001C0000U
1837 #define ADC_SMPR2_SMP6_0 0x00040000U
1838 #define ADC_SMPR2_SMP6_1 0x00080000U
1839 #define ADC_SMPR2_SMP6_2 0x00100000U
1840 #define ADC_SMPR2_SMP7 0x00E00000U
1841 #define ADC_SMPR2_SMP7_0 0x00200000U
1842 #define ADC_SMPR2_SMP7_1 0x00400000U
1843 #define ADC_SMPR2_SMP7_2 0x00800000U
1844 #define ADC_SMPR2_SMP8 0x07000000U
1845 #define ADC_SMPR2_SMP8_0 0x01000000U
1846 #define ADC_SMPR2_SMP8_1 0x02000000U
1847 #define ADC_SMPR2_SMP8_2 0x04000000U
1848 #define ADC_SMPR2_SMP9 0x38000000U
1849 #define ADC_SMPR2_SMP9_0 0x08000000U
1850 #define ADC_SMPR2_SMP9_1 0x10000000U
1851 #define ADC_SMPR2_SMP9_2 0x20000000U
1853 /****************** Bit definition for ADC_JOFR1 register *******************/
1854 #define ADC_JOFR1_JOFFSET1 0x0FFFU
1856 /****************** Bit definition for ADC_JOFR2 register *******************/
1857 #define ADC_JOFR2_JOFFSET2 0x0FFFU
1859 /****************** Bit definition for ADC_JOFR3 register *******************/
1860 #define ADC_JOFR3_JOFFSET3 0x0FFFU
1862 /****************** Bit definition for ADC_JOFR4 register *******************/
1863 #define ADC_JOFR4_JOFFSET4 0x0FFFU
1865 /******************* Bit definition for ADC_HTR register ********************/
1866 #define ADC_HTR_HT 0x0FFFU
1868 /******************* Bit definition for ADC_LTR register ********************/
1869 #define ADC_LTR_LT 0x0FFFU
1871 /******************* Bit definition for ADC_SQR1 register *******************/
1872 #define ADC_SQR1_SQ13 0x0000001FU
1873 #define ADC_SQR1_SQ13_0 0x00000001U
1874 #define ADC_SQR1_SQ13_1 0x00000002U
1875 #define ADC_SQR1_SQ13_2 0x00000004U
1876 #define ADC_SQR1_SQ13_3 0x00000008U
1877 #define ADC_SQR1_SQ13_4 0x00000010U
1878 #define ADC_SQR1_SQ14 0x000003E0U
1879 #define ADC_SQR1_SQ14_0 0x00000020U
1880 #define ADC_SQR1_SQ14_1 0x00000040U
1881 #define ADC_SQR1_SQ14_2 0x00000080U
1882 #define ADC_SQR1_SQ14_3 0x00000100U
1883 #define ADC_SQR1_SQ14_4 0x00000200U
1884 #define ADC_SQR1_SQ15 0x00007C00U
1885 #define ADC_SQR1_SQ15_0 0x00000400U
1886 #define ADC_SQR1_SQ15_1 0x00000800U
1887 #define ADC_SQR1_SQ15_2 0x00001000U
1888 #define ADC_SQR1_SQ15_3 0x00002000U
1889 #define ADC_SQR1_SQ15_4 0x00004000U
1890 #define ADC_SQR1_SQ16 0x000F8000U
1891 #define ADC_SQR1_SQ16_0 0x00008000U
1892 #define ADC_SQR1_SQ16_1 0x00010000U
1893 #define ADC_SQR1_SQ16_2 0x00020000U
1894 #define ADC_SQR1_SQ16_3 0x00040000U
1895 #define ADC_SQR1_SQ16_4 0x00080000U
1896 #define ADC_SQR1_L 0x00F00000U
1897 #define ADC_SQR1_L_0 0x00100000U
1898 #define ADC_SQR1_L_1 0x00200000U
1899 #define ADC_SQR1_L_2 0x00400000U
1900 #define ADC_SQR1_L_3 0x00800000U
1902 /******************* Bit definition for ADC_SQR2 register *******************/
1903 #define ADC_SQR2_SQ7 0x0000001FU
1904 #define ADC_SQR2_SQ7_0 0x00000001U
1905 #define ADC_SQR2_SQ7_1 0x00000002U
1906 #define ADC_SQR2_SQ7_2 0x00000004U
1907 #define ADC_SQR2_SQ7_3 0x00000008U
1908 #define ADC_SQR2_SQ7_4 0x00000010U
1909 #define ADC_SQR2_SQ8 0x000003E0U
1910 #define ADC_SQR2_SQ8_0 0x00000020U
1911 #define ADC_SQR2_SQ8_1 0x00000040U
1912 #define ADC_SQR2_SQ8_2 0x00000080U
1913 #define ADC_SQR2_SQ8_3 0x00000100U
1914 #define ADC_SQR2_SQ8_4 0x00000200U
1915 #define ADC_SQR2_SQ9 0x00007C00U
1916 #define ADC_SQR2_SQ9_0 0x00000400U
1917 #define ADC_SQR2_SQ9_1 0x00000800U
1918 #define ADC_SQR2_SQ9_2 0x00001000U
1919 #define ADC_SQR2_SQ9_3 0x00002000U
1920 #define ADC_SQR2_SQ9_4 0x00004000U
1921 #define ADC_SQR2_SQ10 0x000F8000U
1922 #define ADC_SQR2_SQ10_0 0x00008000U
1923 #define ADC_SQR2_SQ10_1 0x00010000U
1924 #define ADC_SQR2_SQ10_2 0x00020000U
1925 #define ADC_SQR2_SQ10_3 0x00040000U
1926 #define ADC_SQR2_SQ10_4 0x00080000U
1927 #define ADC_SQR2_SQ11 0x01F00000U
1928 #define ADC_SQR2_SQ11_0 0x00100000U
1929 #define ADC_SQR2_SQ11_1 0x00200000U
1930 #define ADC_SQR2_SQ11_2 0x00400000U
1931 #define ADC_SQR2_SQ11_3 0x00800000U
1932 #define ADC_SQR2_SQ11_4 0x01000000U
1933 #define ADC_SQR2_SQ12 0x3E000000U
1934 #define ADC_SQR2_SQ12_0 0x02000000U
1935 #define ADC_SQR2_SQ12_1 0x04000000U
1936 #define ADC_SQR2_SQ12_2 0x08000000U
1937 #define ADC_SQR2_SQ12_3 0x10000000U
1938 #define ADC_SQR2_SQ12_4 0x20000000U
1940 /******************* Bit definition for ADC_SQR3 register *******************/
1941 #define ADC_SQR3_SQ1 0x0000001FU
1942 #define ADC_SQR3_SQ1_0 0x00000001U
1943 #define ADC_SQR3_SQ1_1 0x00000002U
1944 #define ADC_SQR3_SQ1_2 0x00000004U
1945 #define ADC_SQR3_SQ1_3 0x00000008U
1946 #define ADC_SQR3_SQ1_4 0x00000010U
1947 #define ADC_SQR3_SQ2 0x000003E0U
1948 #define ADC_SQR3_SQ2_0 0x00000020U
1949 #define ADC_SQR3_SQ2_1 0x00000040U
1950 #define ADC_SQR3_SQ2_2 0x00000080U
1951 #define ADC_SQR3_SQ2_3 0x00000100U
1952 #define ADC_SQR3_SQ2_4 0x00000200U
1953 #define ADC_SQR3_SQ3 0x00007C00U
1954 #define ADC_SQR3_SQ3_0 0x00000400U
1955 #define ADC_SQR3_SQ3_1 0x00000800U
1956 #define ADC_SQR3_SQ3_2 0x00001000U
1957 #define ADC_SQR3_SQ3_3 0x00002000U
1958 #define ADC_SQR3_SQ3_4 0x00004000U
1959 #define ADC_SQR3_SQ4 0x000F8000U
1960 #define ADC_SQR3_SQ4_0 0x00008000U
1961 #define ADC_SQR3_SQ4_1 0x00010000U
1962 #define ADC_SQR3_SQ4_2 0x00020000U
1963 #define ADC_SQR3_SQ4_3 0x00040000U
1964 #define ADC_SQR3_SQ4_4 0x00080000U
1965 #define ADC_SQR3_SQ5 0x01F00000U
1966 #define ADC_SQR3_SQ5_0 0x00100000U
1967 #define ADC_SQR3_SQ5_1 0x00200000U
1968 #define ADC_SQR3_SQ5_2 0x00400000U
1969 #define ADC_SQR3_SQ5_3 0x00800000U
1970 #define ADC_SQR3_SQ5_4 0x01000000U
1971 #define ADC_SQR3_SQ6 0x3E000000U
1972 #define ADC_SQR3_SQ6_0 0x02000000U
1973 #define ADC_SQR3_SQ6_1 0x04000000U
1974 #define ADC_SQR3_SQ6_2 0x08000000U
1975 #define ADC_SQR3_SQ6_3 0x10000000U
1976 #define ADC_SQR3_SQ6_4 0x20000000U
1978 /******************* Bit definition for ADC_JSQR register *******************/
1979 #define ADC_JSQR_JSQ1 0x0000001FU
1980 #define ADC_JSQR_JSQ1_0 0x00000001U
1981 #define ADC_JSQR_JSQ1_1 0x00000002U
1982 #define ADC_JSQR_JSQ1_2 0x00000004U
1983 #define ADC_JSQR_JSQ1_3 0x00000008U
1984 #define ADC_JSQR_JSQ1_4 0x00000010U
1985 #define ADC_JSQR_JSQ2 0x000003E0U
1986 #define ADC_JSQR_JSQ2_0 0x00000020U
1987 #define ADC_JSQR_JSQ2_1 0x00000040U
1988 #define ADC_JSQR_JSQ2_2 0x00000080U
1989 #define ADC_JSQR_JSQ2_3 0x00000100U
1990 #define ADC_JSQR_JSQ2_4 0x00000200U
1991 #define ADC_JSQR_JSQ3 0x00007C00U
1992 #define ADC_JSQR_JSQ3_0 0x00000400U
1993 #define ADC_JSQR_JSQ3_1 0x00000800U
1994 #define ADC_JSQR_JSQ3_2 0x00001000U
1995 #define ADC_JSQR_JSQ3_3 0x00002000U
1996 #define ADC_JSQR_JSQ3_4 0x00004000U
1997 #define ADC_JSQR_JSQ4 0x000F8000U
1998 #define ADC_JSQR_JSQ4_0 0x00008000U
1999 #define ADC_JSQR_JSQ4_1 0x00010000U
2000 #define ADC_JSQR_JSQ4_2 0x00020000U
2001 #define ADC_JSQR_JSQ4_3 0x00040000U
2002 #define ADC_JSQR_JSQ4_4 0x00080000U
2003 #define ADC_JSQR_JL 0x00300000U
2004 #define ADC_JSQR_JL_0 0x00100000U
2005 #define ADC_JSQR_JL_1 0x00200000U
2007 /******************* Bit definition for ADC_JDR1 register *******************/
2008 #define ADC_JDR1_JDATA ((uint16_t)0xFFFFU)
2010 /******************* Bit definition for ADC_JDR2 register *******************/
2011 #define ADC_JDR2_JDATA ((uint16_t)0xFFFFU)
2013 /******************* Bit definition for ADC_JDR3 register *******************/
2014 #define ADC_JDR3_JDATA ((uint16_t)0xFFFFU)
2016 /******************* Bit definition for ADC_JDR4 register *******************/
2017 #define ADC_JDR4_JDATA ((uint16_t)0xFFFFU)
2019 /******************** Bit definition for ADC_DR register ********************/
2020 #define ADC_DR_DATA 0x0000FFFFU
2021 #define ADC_DR_ADC2DATA 0xFFFF0000U
2023 /******************* Bit definition for ADC_CSR register ********************/
2024 #define ADC_CSR_AWD1 0x00000001U
2025 #define ADC_CSR_EOC1 0x00000002U
2026 #define ADC_CSR_JEOC1 0x00000004U
2027 #define ADC_CSR_JSTRT1 0x00000008U
2028 #define ADC_CSR_STRT1 0x00000010U
2029 #define ADC_CSR_OVR1 0x00000020U
2030 #define ADC_CSR_AWD2 0x00000100U
2031 #define ADC_CSR_EOC2 0x00000200U
2032 #define ADC_CSR_JEOC2 0x00000400U
2033 #define ADC_CSR_JSTRT2 0x00000800U
2034 #define ADC_CSR_STRT2 0x00001000U
2035 #define ADC_CSR_OVR2 0x00002000U
2036 #define ADC_CSR_AWD3 0x00010000U
2037 #define ADC_CSR_EOC3 0x00020000U
2038 #define ADC_CSR_JEOC3 0x00040000U
2039 #define ADC_CSR_JSTRT3 0x00080000U
2040 #define ADC_CSR_STRT3 0x00100000U
2041 #define ADC_CSR_OVR3 0x00200000U
2043 /* Legacy defines */
2044 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
2045 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
2046 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
2047 
2048 
2049 /******************* Bit definition for ADC_CCR register ********************/
2050 #define ADC_CCR_MULTI 0x0000001FU
2051 #define ADC_CCR_MULTI_0 0x00000001U
2052 #define ADC_CCR_MULTI_1 0x00000002U
2053 #define ADC_CCR_MULTI_2 0x00000004U
2054 #define ADC_CCR_MULTI_3 0x00000008U
2055 #define ADC_CCR_MULTI_4 0x00000010U
2056 #define ADC_CCR_DELAY 0x00000F00U
2057 #define ADC_CCR_DELAY_0 0x00000100U
2058 #define ADC_CCR_DELAY_1 0x00000200U
2059 #define ADC_CCR_DELAY_2 0x00000400U
2060 #define ADC_CCR_DELAY_3 0x00000800U
2061 #define ADC_CCR_DDS 0x00002000U
2062 #define ADC_CCR_DMA 0x0000C000U
2063 #define ADC_CCR_DMA_0 0x00004000U
2064 #define ADC_CCR_DMA_1 0x00008000U
2065 #define ADC_CCR_ADCPRE 0x00030000U
2066 #define ADC_CCR_ADCPRE_0 0x00010000U
2067 #define ADC_CCR_ADCPRE_1 0x00020000U
2068 #define ADC_CCR_VBATE 0x00400000U
2069 #define ADC_CCR_TSVREFE 0x00800000U
2071 /******************* Bit definition for ADC_CDR register ********************/
2072 #define ADC_CDR_DATA1 0x0000FFFFU
2073 #define ADC_CDR_DATA2 0xFFFF0000U
2075 /******************************************************************************/
2076 /* */
2077 /* Controller Area Network */
2078 /* */
2079 /******************************************************************************/
2081 /******************* Bit definition for CAN_MCR register ********************/
2082 #define CAN_MCR_INRQ 0x00000001U
2083 #define CAN_MCR_SLEEP 0x00000002U
2084 #define CAN_MCR_TXFP 0x00000004U
2085 #define CAN_MCR_RFLM 0x00000008U
2086 #define CAN_MCR_NART 0x00000010U
2087 #define CAN_MCR_AWUM 0x00000020U
2088 #define CAN_MCR_ABOM 0x00000040U
2089 #define CAN_MCR_TTCM 0x00000080U
2090 #define CAN_MCR_RESET 0x00008000U
2092 /******************* Bit definition for CAN_MSR register ********************/
2093 #define CAN_MSR_INAK 0x00000001U
2094 #define CAN_MSR_SLAK 0x00000002U
2095 #define CAN_MSR_ERRI 0x00000004U
2096 #define CAN_MSR_WKUI 0x00000008U
2097 #define CAN_MSR_SLAKI 0x00000010U
2098 #define CAN_MSR_TXM 0x00000100U
2099 #define CAN_MSR_RXM 0x00000200U
2100 #define CAN_MSR_SAMP 0x00000400U
2101 #define CAN_MSR_RX 0x00000800U
2103 /******************* Bit definition for CAN_TSR register ********************/
2104 #define CAN_TSR_RQCP0 0x00000001U
2105 #define CAN_TSR_TXOK0 0x00000002U
2106 #define CAN_TSR_ALST0 0x00000004U
2107 #define CAN_TSR_TERR0 0x00000008U
2108 #define CAN_TSR_ABRQ0 0x00000080U
2109 #define CAN_TSR_RQCP1 0x00000100U
2110 #define CAN_TSR_TXOK1 0x00000200U
2111 #define CAN_TSR_ALST1 0x00000400U
2112 #define CAN_TSR_TERR1 0x00000800U
2113 #define CAN_TSR_ABRQ1 0x00008000U
2114 #define CAN_TSR_RQCP2 0x00010000U
2115 #define CAN_TSR_TXOK2 0x00020000U
2116 #define CAN_TSR_ALST2 0x00040000U
2117 #define CAN_TSR_TERR2 0x00080000U
2118 #define CAN_TSR_ABRQ2 0x00800000U
2119 #define CAN_TSR_CODE 0x03000000U
2121 #define CAN_TSR_TME 0x1C000000U
2122 #define CAN_TSR_TME0 0x04000000U
2123 #define CAN_TSR_TME1 0x08000000U
2124 #define CAN_TSR_TME2 0x10000000U
2126 #define CAN_TSR_LOW 0xE0000000U
2127 #define CAN_TSR_LOW0 0x20000000U
2128 #define CAN_TSR_LOW1 0x40000000U
2129 #define CAN_TSR_LOW2 0x80000000U
2131 /******************* Bit definition for CAN_RF0R register *******************/
2132 #define CAN_RF0R_FMP0 0x00000003U
2133 #define CAN_RF0R_FULL0 0x00000008U
2134 #define CAN_RF0R_FOVR0 0x00000010U
2135 #define CAN_RF0R_RFOM0 0x00000020U
2137 /******************* Bit definition for CAN_RF1R register *******************/
2138 #define CAN_RF1R_FMP1 0x00000003U
2139 #define CAN_RF1R_FULL1 0x00000008U
2140 #define CAN_RF1R_FOVR1 0x00000010U
2141 #define CAN_RF1R_RFOM1 0x00000020U
2143 /******************** Bit definition for CAN_IER register *******************/
2144 #define CAN_IER_TMEIE 0x00000001U
2145 #define CAN_IER_FMPIE0 0x00000002U
2146 #define CAN_IER_FFIE0 0x00000004U
2147 #define CAN_IER_FOVIE0 0x00000008U
2148 #define CAN_IER_FMPIE1 0x00000010U
2149 #define CAN_IER_FFIE1 0x00000020U
2150 #define CAN_IER_FOVIE1 0x00000040U
2151 #define CAN_IER_EWGIE 0x00000100U
2152 #define CAN_IER_EPVIE 0x00000200U
2153 #define CAN_IER_BOFIE 0x00000400U
2154 #define CAN_IER_LECIE 0x00000800U
2155 #define CAN_IER_ERRIE 0x00008000U
2156 #define CAN_IER_WKUIE 0x00010000U
2157 #define CAN_IER_SLKIE 0x00020000U
2159 /******************** Bit definition for CAN_ESR register *******************/
2160 #define CAN_ESR_EWGF 0x00000001U
2161 #define CAN_ESR_EPVF 0x00000002U
2162 #define CAN_ESR_BOFF 0x00000004U
2164 #define CAN_ESR_LEC 0x00000070U
2165 #define CAN_ESR_LEC_0 0x00000010U
2166 #define CAN_ESR_LEC_1 0x00000020U
2167 #define CAN_ESR_LEC_2 0x00000040U
2169 #define CAN_ESR_TEC 0x00FF0000U
2170 #define CAN_ESR_REC 0xFF000000U
2172 /******************* Bit definition for CAN_BTR register ********************/
2173 #define CAN_BTR_BRP 0x000003FFU
2174 #define CAN_BTR_TS1 0x000F0000U
2175 #define CAN_BTR_TS1_0 0x00010000U
2176 #define CAN_BTR_TS1_1 0x00020000U
2177 #define CAN_BTR_TS1_2 0x00040000U
2178 #define CAN_BTR_TS1_3 0x00080000U
2179 #define CAN_BTR_TS2 0x00700000U
2180 #define CAN_BTR_TS2_0 0x00100000U
2181 #define CAN_BTR_TS2_1 0x00200000U
2182 #define CAN_BTR_TS2_2 0x00400000U
2183 #define CAN_BTR_SJW 0x03000000U
2184 #define CAN_BTR_SJW_0 0x01000000U
2185 #define CAN_BTR_SJW_1 0x02000000U
2186 #define CAN_BTR_LBKM 0x40000000U
2187 #define CAN_BTR_SILM 0x80000000U
2190 /****************** Bit definition for CAN_TI0R register ********************/
2191 #define CAN_TI0R_TXRQ 0x00000001U
2192 #define CAN_TI0R_RTR 0x00000002U
2193 #define CAN_TI0R_IDE 0x00000004U
2194 #define CAN_TI0R_EXID 0x001FFFF8U
2195 #define CAN_TI0R_STID 0xFFE00000U
2197 /****************** Bit definition for CAN_TDT0R register *******************/
2198 #define CAN_TDT0R_DLC 0x0000000FU
2199 #define CAN_TDT0R_TGT 0x00000100U
2200 #define CAN_TDT0R_TIME 0xFFFF0000U
2202 /****************** Bit definition for CAN_TDL0R register *******************/
2203 #define CAN_TDL0R_DATA0 0x000000FFU
2204 #define CAN_TDL0R_DATA1 0x0000FF00U
2205 #define CAN_TDL0R_DATA2 0x00FF0000U
2206 #define CAN_TDL0R_DATA3 0xFF000000U
2208 /****************** Bit definition for CAN_TDH0R register *******************/
2209 #define CAN_TDH0R_DATA4 0x000000FFU
2210 #define CAN_TDH0R_DATA5 0x0000FF00U
2211 #define CAN_TDH0R_DATA6 0x00FF0000U
2212 #define CAN_TDH0R_DATA7 0xFF000000U
2214 /******************* Bit definition for CAN_TI1R register *******************/
2215 #define CAN_TI1R_TXRQ 0x00000001U
2216 #define CAN_TI1R_RTR 0x00000002U
2217 #define CAN_TI1R_IDE 0x00000004U
2218 #define CAN_TI1R_EXID 0x001FFFF8U
2219 #define CAN_TI1R_STID 0xFFE00000U
2221 /******************* Bit definition for CAN_TDT1R register ******************/
2222 #define CAN_TDT1R_DLC 0x0000000FU
2223 #define CAN_TDT1R_TGT 0x00000100U
2224 #define CAN_TDT1R_TIME 0xFFFF0000U
2226 /******************* Bit definition for CAN_TDL1R register ******************/
2227 #define CAN_TDL1R_DATA0 0x000000FFU
2228 #define CAN_TDL1R_DATA1 0x0000FF00U
2229 #define CAN_TDL1R_DATA2 0x00FF0000U
2230 #define CAN_TDL1R_DATA3 0xFF000000U
2232 /******************* Bit definition for CAN_TDH1R register ******************/
2233 #define CAN_TDH1R_DATA4 0x000000FFU
2234 #define CAN_TDH1R_DATA5 0x0000FF00U
2235 #define CAN_TDH1R_DATA6 0x00FF0000U
2236 #define CAN_TDH1R_DATA7 0xFF000000U
2238 /******************* Bit definition for CAN_TI2R register *******************/
2239 #define CAN_TI2R_TXRQ 0x00000001U
2240 #define CAN_TI2R_RTR 0x00000002U
2241 #define CAN_TI2R_IDE 0x00000004U
2242 #define CAN_TI2R_EXID 0x001FFFF8U
2243 #define CAN_TI2R_STID 0xFFE00000U
2245 /******************* Bit definition for CAN_TDT2R register ******************/
2246 #define CAN_TDT2R_DLC 0x0000000FU
2247 #define CAN_TDT2R_TGT 0x00000100U
2248 #define CAN_TDT2R_TIME 0xFFFF0000U
2250 /******************* Bit definition for CAN_TDL2R register ******************/
2251 #define CAN_TDL2R_DATA0 0x000000FFU
2252 #define CAN_TDL2R_DATA1 0x0000FF00U
2253 #define CAN_TDL2R_DATA2 0x00FF0000U
2254 #define CAN_TDL2R_DATA3 0xFF000000U
2256 /******************* Bit definition for CAN_TDH2R register ******************/
2257 #define CAN_TDH2R_DATA4 0x000000FFU
2258 #define CAN_TDH2R_DATA5 0x0000FF00U
2259 #define CAN_TDH2R_DATA6 0x00FF0000U
2260 #define CAN_TDH2R_DATA7 0xFF000000U
2262 /******************* Bit definition for CAN_RI0R register *******************/
2263 #define CAN_RI0R_RTR 0x00000002U
2264 #define CAN_RI0R_IDE 0x00000004U
2265 #define CAN_RI0R_EXID 0x001FFFF8U
2266 #define CAN_RI0R_STID 0xFFE00000U
2268 /******************* Bit definition for CAN_RDT0R register ******************/
2269 #define CAN_RDT0R_DLC 0x0000000FU
2270 #define CAN_RDT0R_FMI 0x0000FF00U
2271 #define CAN_RDT0R_TIME 0xFFFF0000U
2273 /******************* Bit definition for CAN_RDL0R register ******************/
2274 #define CAN_RDL0R_DATA0 0x000000FFU
2275 #define CAN_RDL0R_DATA1 0x0000FF00U
2276 #define CAN_RDL0R_DATA2 0x00FF0000U
2277 #define CAN_RDL0R_DATA3 0xFF000000U
2279 /******************* Bit definition for CAN_RDH0R register ******************/
2280 #define CAN_RDH0R_DATA4 0x000000FFU
2281 #define CAN_RDH0R_DATA5 0x0000FF00U
2282 #define CAN_RDH0R_DATA6 0x00FF0000U
2283 #define CAN_RDH0R_DATA7 0xFF000000U
2285 /******************* Bit definition for CAN_RI1R register *******************/
2286 #define CAN_RI1R_RTR 0x00000002U
2287 #define CAN_RI1R_IDE 0x00000004U
2288 #define CAN_RI1R_EXID 0x001FFFF8U
2289 #define CAN_RI1R_STID 0xFFE00000U
2291 /******************* Bit definition for CAN_RDT1R register ******************/
2292 #define CAN_RDT1R_DLC 0x0000000FU
2293 #define CAN_RDT1R_FMI 0x0000FF00U
2294 #define CAN_RDT1R_TIME 0xFFFF0000U
2296 /******************* Bit definition for CAN_RDL1R register ******************/
2297 #define CAN_RDL1R_DATA0 0x000000FFU
2298 #define CAN_RDL1R_DATA1 0x0000FF00U
2299 #define CAN_RDL1R_DATA2 0x00FF0000U
2300 #define CAN_RDL1R_DATA3 0xFF000000U
2302 /******************* Bit definition for CAN_RDH1R register ******************/
2303 #define CAN_RDH1R_DATA4 0x000000FFU
2304 #define CAN_RDH1R_DATA5 0x0000FF00U
2305 #define CAN_RDH1R_DATA6 0x00FF0000U
2306 #define CAN_RDH1R_DATA7 0xFF000000U
2309 /******************* Bit definition for CAN_FMR register ********************/
2310 #define CAN_FMR_FINIT ((uint8_t)0x01U)
2311 #define CAN_FMR_CAN2SB 0x00003F00U
2313 /******************* Bit definition for CAN_FM1R register *******************/
2314 #define CAN_FM1R_FBM 0x3FFFU
2315 #define CAN_FM1R_FBM0 0x0001U
2316 #define CAN_FM1R_FBM1 0x0002U
2317 #define CAN_FM1R_FBM2 0x0004U
2318 #define CAN_FM1R_FBM3 0x0008U
2319 #define CAN_FM1R_FBM4 0x0010U
2320 #define CAN_FM1R_FBM5 0x0020U
2321 #define CAN_FM1R_FBM6 0x0040U
2322 #define CAN_FM1R_FBM7 0x0080U
2323 #define CAN_FM1R_FBM8 0x0100U
2324 #define CAN_FM1R_FBM9 0x0200U
2325 #define CAN_FM1R_FBM10 0x0400U
2326 #define CAN_FM1R_FBM11 0x0800U
2327 #define CAN_FM1R_FBM12 0x1000U
2328 #define CAN_FM1R_FBM13 0x2000U
2330 /******************* Bit definition for CAN_FS1R register *******************/
2331 #define CAN_FS1R_FSC 0x00003FFFU
2332 #define CAN_FS1R_FSC0 0x00000001U
2333 #define CAN_FS1R_FSC1 0x00000002U
2334 #define CAN_FS1R_FSC2 0x00000004U
2335 #define CAN_FS1R_FSC3 0x00000008U
2336 #define CAN_FS1R_FSC4 0x00000010U
2337 #define CAN_FS1R_FSC5 0x00000020U
2338 #define CAN_FS1R_FSC6 0x00000040U
2339 #define CAN_FS1R_FSC7 0x00000080U
2340 #define CAN_FS1R_FSC8 0x00000100U
2341 #define CAN_FS1R_FSC9 0x00000200U
2342 #define CAN_FS1R_FSC10 0x00000400U
2343 #define CAN_FS1R_FSC11 0x00000800U
2344 #define CAN_FS1R_FSC12 0x00001000U
2345 #define CAN_FS1R_FSC13 0x00002000U
2347 /****************** Bit definition for CAN_FFA1R register *******************/
2348 #define CAN_FFA1R_FFA 0x00003FFFU
2349 #define CAN_FFA1R_FFA0 0x00000001U
2350 #define CAN_FFA1R_FFA1 0x00000002U
2351 #define CAN_FFA1R_FFA2 0x00000004U
2352 #define CAN_FFA1R_FFA3 0x00000008U
2353 #define CAN_FFA1R_FFA4 0x00000010U
2354 #define CAN_FFA1R_FFA5 0x00000020U
2355 #define CAN_FFA1R_FFA6 0x00000040U
2356 #define CAN_FFA1R_FFA7 0x00000080U
2357 #define CAN_FFA1R_FFA8 0x00000100U
2358 #define CAN_FFA1R_FFA9 0x00000200U
2359 #define CAN_FFA1R_FFA10 0x00000400U
2360 #define CAN_FFA1R_FFA11 0x00000800U
2361 #define CAN_FFA1R_FFA12 0x00001000U
2362 #define CAN_FFA1R_FFA13 0x00002000U
2364 /******************* Bit definition for CAN_FA1R register *******************/
2365 #define CAN_FA1R_FACT 0x00003FFFU
2366 #define CAN_FA1R_FACT0 0x00000001U
2367 #define CAN_FA1R_FACT1 0x00000002U
2368 #define CAN_FA1R_FACT2 0x00000004U
2369 #define CAN_FA1R_FACT3 0x00000008U
2370 #define CAN_FA1R_FACT4 0x00000010U
2371 #define CAN_FA1R_FACT5 0x00000020U
2372 #define CAN_FA1R_FACT6 0x00000040U
2373 #define CAN_FA1R_FACT7 0x00000080U
2374 #define CAN_FA1R_FACT8 0x00000100U
2375 #define CAN_FA1R_FACT9 0x00000200U
2376 #define CAN_FA1R_FACT10 0x00000400U
2377 #define CAN_FA1R_FACT11 0x00000800U
2378 #define CAN_FA1R_FACT12 0x00001000U
2379 #define CAN_FA1R_FACT13 0x00002000U
2381 /******************* Bit definition for CAN_F0R1 register *******************/
2382 #define CAN_F0R1_FB0 0x00000001U
2383 #define CAN_F0R1_FB1 0x00000002U
2384 #define CAN_F0R1_FB2 0x00000004U
2385 #define CAN_F0R1_FB3 0x00000008U
2386 #define CAN_F0R1_FB4 0x00000010U
2387 #define CAN_F0R1_FB5 0x00000020U
2388 #define CAN_F0R1_FB6 0x00000040U
2389 #define CAN_F0R1_FB7 0x00000080U
2390 #define CAN_F0R1_FB8 0x00000100U
2391 #define CAN_F0R1_FB9 0x00000200U
2392 #define CAN_F0R1_FB10 0x00000400U
2393 #define CAN_F0R1_FB11 0x00000800U
2394 #define CAN_F0R1_FB12 0x00001000U
2395 #define CAN_F0R1_FB13 0x00002000U
2396 #define CAN_F0R1_FB14 0x00004000U
2397 #define CAN_F0R1_FB15 0x00008000U
2398 #define CAN_F0R1_FB16 0x00010000U
2399 #define CAN_F0R1_FB17 0x00020000U
2400 #define CAN_F0R1_FB18 0x00040000U
2401 #define CAN_F0R1_FB19 0x00080000U
2402 #define CAN_F0R1_FB20 0x00100000U
2403 #define CAN_F0R1_FB21 0x00200000U
2404 #define CAN_F0R1_FB22 0x00400000U
2405 #define CAN_F0R1_FB23 0x00800000U
2406 #define CAN_F0R1_FB24 0x01000000U
2407 #define CAN_F0R1_FB25 0x02000000U
2408 #define CAN_F0R1_FB26 0x04000000U
2409 #define CAN_F0R1_FB27 0x08000000U
2410 #define CAN_F0R1_FB28 0x10000000U
2411 #define CAN_F0R1_FB29 0x20000000U
2412 #define CAN_F0R1_FB30 0x40000000U
2413 #define CAN_F0R1_FB31 0x80000000U
2415 /******************* Bit definition for CAN_F1R1 register *******************/
2416 #define CAN_F1R1_FB0 0x00000001U
2417 #define CAN_F1R1_FB1 0x00000002U
2418 #define CAN_F1R1_FB2 0x00000004U
2419 #define CAN_F1R1_FB3 0x00000008U
2420 #define CAN_F1R1_FB4 0x00000010U
2421 #define CAN_F1R1_FB5 0x00000020U
2422 #define CAN_F1R1_FB6 0x00000040U
2423 #define CAN_F1R1_FB7 0x00000080U
2424 #define CAN_F1R1_FB8 0x00000100U
2425 #define CAN_F1R1_FB9 0x00000200U
2426 #define CAN_F1R1_FB10 0x00000400U
2427 #define CAN_F1R1_FB11 0x00000800U
2428 #define CAN_F1R1_FB12 0x00001000U
2429 #define CAN_F1R1_FB13 0x00002000U
2430 #define CAN_F1R1_FB14 0x00004000U
2431 #define CAN_F1R1_FB15 0x00008000U
2432 #define CAN_F1R1_FB16 0x00010000U
2433 #define CAN_F1R1_FB17 0x00020000U
2434 #define CAN_F1R1_FB18 0x00040000U
2435 #define CAN_F1R1_FB19 0x00080000U
2436 #define CAN_F1R1_FB20 0x00100000U
2437 #define CAN_F1R1_FB21 0x00200000U
2438 #define CAN_F1R1_FB22 0x00400000U
2439 #define CAN_F1R1_FB23 0x00800000U
2440 #define CAN_F1R1_FB24 0x01000000U
2441 #define CAN_F1R1_FB25 0x02000000U
2442 #define CAN_F1R1_FB26 0x04000000U
2443 #define CAN_F1R1_FB27 0x08000000U
2444 #define CAN_F1R1_FB28 0x10000000U
2445 #define CAN_F1R1_FB29 0x20000000U
2446 #define CAN_F1R1_FB30 0x40000000U
2447 #define CAN_F1R1_FB31 0x80000000U
2449 /******************* Bit definition for CAN_F2R1 register *******************/
2450 #define CAN_F2R1_FB0 0x00000001U
2451 #define CAN_F2R1_FB1 0x00000002U
2452 #define CAN_F2R1_FB2 0x00000004U
2453 #define CAN_F2R1_FB3 0x00000008U
2454 #define CAN_F2R1_FB4 0x00000010U
2455 #define CAN_F2R1_FB5 0x00000020U
2456 #define CAN_F2R1_FB6 0x00000040U
2457 #define CAN_F2R1_FB7 0x00000080U
2458 #define CAN_F2R1_FB8 0x00000100U
2459 #define CAN_F2R1_FB9 0x00000200U
2460 #define CAN_F2R1_FB10 0x00000400U
2461 #define CAN_F2R1_FB11 0x00000800U
2462 #define CAN_F2R1_FB12 0x00001000U
2463 #define CAN_F2R1_FB13 0x00002000U
2464 #define CAN_F2R1_FB14 0x00004000U
2465 #define CAN_F2R1_FB15 0x00008000U
2466 #define CAN_F2R1_FB16 0x00010000U
2467 #define CAN_F2R1_FB17 0x00020000U
2468 #define CAN_F2R1_FB18 0x00040000U
2469 #define CAN_F2R1_FB19 0x00080000U
2470 #define CAN_F2R1_FB20 0x00100000U
2471 #define CAN_F2R1_FB21 0x00200000U
2472 #define CAN_F2R1_FB22 0x00400000U
2473 #define CAN_F2R1_FB23 0x00800000U
2474 #define CAN_F2R1_FB24 0x01000000U
2475 #define CAN_F2R1_FB25 0x02000000U
2476 #define CAN_F2R1_FB26 0x04000000U
2477 #define CAN_F2R1_FB27 0x08000000U
2478 #define CAN_F2R1_FB28 0x10000000U
2479 #define CAN_F2R1_FB29 0x20000000U
2480 #define CAN_F2R1_FB30 0x40000000U
2481 #define CAN_F2R1_FB31 0x80000000U
2483 /******************* Bit definition for CAN_F3R1 register *******************/
2484 #define CAN_F3R1_FB0 0x00000001U
2485 #define CAN_F3R1_FB1 0x00000002U
2486 #define CAN_F3R1_FB2 0x00000004U
2487 #define CAN_F3R1_FB3 0x00000008U
2488 #define CAN_F3R1_FB4 0x00000010U
2489 #define CAN_F3R1_FB5 0x00000020U
2490 #define CAN_F3R1_FB6 0x00000040U
2491 #define CAN_F3R1_FB7 0x00000080U
2492 #define CAN_F3R1_FB8 0x00000100U
2493 #define CAN_F3R1_FB9 0x00000200U
2494 #define CAN_F3R1_FB10 0x00000400U
2495 #define CAN_F3R1_FB11 0x00000800U
2496 #define CAN_F3R1_FB12 0x00001000U
2497 #define CAN_F3R1_FB13 0x00002000U
2498 #define CAN_F3R1_FB14 0x00004000U
2499 #define CAN_F3R1_FB15 0x00008000U
2500 #define CAN_F3R1_FB16 0x00010000U
2501 #define CAN_F3R1_FB17 0x00020000U
2502 #define CAN_F3R1_FB18 0x00040000U
2503 #define CAN_F3R1_FB19 0x00080000U
2504 #define CAN_F3R1_FB20 0x00100000U
2505 #define CAN_F3R1_FB21 0x00200000U
2506 #define CAN_F3R1_FB22 0x00400000U
2507 #define CAN_F3R1_FB23 0x00800000U
2508 #define CAN_F3R1_FB24 0x01000000U
2509 #define CAN_F3R1_FB25 0x02000000U
2510 #define CAN_F3R1_FB26 0x04000000U
2511 #define CAN_F3R1_FB27 0x08000000U
2512 #define CAN_F3R1_FB28 0x10000000U
2513 #define CAN_F3R1_FB29 0x20000000U
2514 #define CAN_F3R1_FB30 0x40000000U
2515 #define CAN_F3R1_FB31 0x80000000U
2517 /******************* Bit definition for CAN_F4R1 register *******************/
2518 #define CAN_F4R1_FB0 0x00000001U
2519 #define CAN_F4R1_FB1 0x00000002U
2520 #define CAN_F4R1_FB2 0x00000004U
2521 #define CAN_F4R1_FB3 0x00000008U
2522 #define CAN_F4R1_FB4 0x00000010U
2523 #define CAN_F4R1_FB5 0x00000020U
2524 #define CAN_F4R1_FB6 0x00000040U
2525 #define CAN_F4R1_FB7 0x00000080U
2526 #define CAN_F4R1_FB8 0x00000100U
2527 #define CAN_F4R1_FB9 0x00000200U
2528 #define CAN_F4R1_FB10 0x00000400U
2529 #define CAN_F4R1_FB11 0x00000800U
2530 #define CAN_F4R1_FB12 0x00001000U
2531 #define CAN_F4R1_FB13 0x00002000U
2532 #define CAN_F4R1_FB14 0x00004000U
2533 #define CAN_F4R1_FB15 0x00008000U
2534 #define CAN_F4R1_FB16 0x00010000U
2535 #define CAN_F4R1_FB17 0x00020000U
2536 #define CAN_F4R1_FB18 0x00040000U
2537 #define CAN_F4R1_FB19 0x00080000U
2538 #define CAN_F4R1_FB20 0x00100000U
2539 #define CAN_F4R1_FB21 0x00200000U
2540 #define CAN_F4R1_FB22 0x00400000U
2541 #define CAN_F4R1_FB23 0x00800000U
2542 #define CAN_F4R1_FB24 0x01000000U
2543 #define CAN_F4R1_FB25 0x02000000U
2544 #define CAN_F4R1_FB26 0x04000000U
2545 #define CAN_F4R1_FB27 0x08000000U
2546 #define CAN_F4R1_FB28 0x10000000U
2547 #define CAN_F4R1_FB29 0x20000000U
2548 #define CAN_F4R1_FB30 0x40000000U
2549 #define CAN_F4R1_FB31 0x80000000U
2551 /******************* Bit definition for CAN_F5R1 register *******************/
2552 #define CAN_F5R1_FB0 0x00000001U
2553 #define CAN_F5R1_FB1 0x00000002U
2554 #define CAN_F5R1_FB2 0x00000004U
2555 #define CAN_F5R1_FB3 0x00000008U
2556 #define CAN_F5R1_FB4 0x00000010U
2557 #define CAN_F5R1_FB5 0x00000020U
2558 #define CAN_F5R1_FB6 0x00000040U
2559 #define CAN_F5R1_FB7 0x00000080U
2560 #define CAN_F5R1_FB8 0x00000100U
2561 #define CAN_F5R1_FB9 0x00000200U
2562 #define CAN_F5R1_FB10 0x00000400U
2563 #define CAN_F5R1_FB11 0x00000800U
2564 #define CAN_F5R1_FB12 0x00001000U
2565 #define CAN_F5R1_FB13 0x00002000U
2566 #define CAN_F5R1_FB14 0x00004000U
2567 #define CAN_F5R1_FB15 0x00008000U
2568 #define CAN_F5R1_FB16 0x00010000U
2569 #define CAN_F5R1_FB17 0x00020000U
2570 #define CAN_F5R1_FB18 0x00040000U
2571 #define CAN_F5R1_FB19 0x00080000U
2572 #define CAN_F5R1_FB20 0x00100000U
2573 #define CAN_F5R1_FB21 0x00200000U
2574 #define CAN_F5R1_FB22 0x00400000U
2575 #define CAN_F5R1_FB23 0x00800000U
2576 #define CAN_F5R1_FB24 0x01000000U
2577 #define CAN_F5R1_FB25 0x02000000U
2578 #define CAN_F5R1_FB26 0x04000000U
2579 #define CAN_F5R1_FB27 0x08000000U
2580 #define CAN_F5R1_FB28 0x10000000U
2581 #define CAN_F5R1_FB29 0x20000000U
2582 #define CAN_F5R1_FB30 0x40000000U
2583 #define CAN_F5R1_FB31 0x80000000U
2585 /******************* Bit definition for CAN_F6R1 register *******************/
2586 #define CAN_F6R1_FB0 0x00000001U
2587 #define CAN_F6R1_FB1 0x00000002U
2588 #define CAN_F6R1_FB2 0x00000004U
2589 #define CAN_F6R1_FB3 0x00000008U
2590 #define CAN_F6R1_FB4 0x00000010U
2591 #define CAN_F6R1_FB5 0x00000020U
2592 #define CAN_F6R1_FB6 0x00000040U
2593 #define CAN_F6R1_FB7 0x00000080U
2594 #define CAN_F6R1_FB8 0x00000100U
2595 #define CAN_F6R1_FB9 0x00000200U
2596 #define CAN_F6R1_FB10 0x00000400U
2597 #define CAN_F6R1_FB11 0x00000800U
2598 #define CAN_F6R1_FB12 0x00001000U
2599 #define CAN_F6R1_FB13 0x00002000U
2600 #define CAN_F6R1_FB14 0x00004000U
2601 #define CAN_F6R1_FB15 0x00008000U
2602 #define CAN_F6R1_FB16 0x00010000U
2603 #define CAN_F6R1_FB17 0x00020000U
2604 #define CAN_F6R1_FB18 0x00040000U
2605 #define CAN_F6R1_FB19 0x00080000U
2606 #define CAN_F6R1_FB20 0x00100000U
2607 #define CAN_F6R1_FB21 0x00200000U
2608 #define CAN_F6R1_FB22 0x00400000U
2609 #define CAN_F6R1_FB23 0x00800000U
2610 #define CAN_F6R1_FB24 0x01000000U
2611 #define CAN_F6R1_FB25 0x02000000U
2612 #define CAN_F6R1_FB26 0x04000000U
2613 #define CAN_F6R1_FB27 0x08000000U
2614 #define CAN_F6R1_FB28 0x10000000U
2615 #define CAN_F6R1_FB29 0x20000000U
2616 #define CAN_F6R1_FB30 0x40000000U
2617 #define CAN_F6R1_FB31 0x80000000U
2619 /******************* Bit definition for CAN_F7R1 register *******************/
2620 #define CAN_F7R1_FB0 0x00000001U
2621 #define CAN_F7R1_FB1 0x00000002U
2622 #define CAN_F7R1_FB2 0x00000004U
2623 #define CAN_F7R1_FB3 0x00000008U
2624 #define CAN_F7R1_FB4 0x00000010U
2625 #define CAN_F7R1_FB5 0x00000020U
2626 #define CAN_F7R1_FB6 0x00000040U
2627 #define CAN_F7R1_FB7 0x00000080U
2628 #define CAN_F7R1_FB8 0x00000100U
2629 #define CAN_F7R1_FB9 0x00000200U
2630 #define CAN_F7R1_FB10 0x00000400U
2631 #define CAN_F7R1_FB11 0x00000800U
2632 #define CAN_F7R1_FB12 0x00001000U
2633 #define CAN_F7R1_FB13 0x00002000U
2634 #define CAN_F7R1_FB14 0x00004000U
2635 #define CAN_F7R1_FB15 0x00008000U
2636 #define CAN_F7R1_FB16 0x00010000U
2637 #define CAN_F7R1_FB17 0x00020000U
2638 #define CAN_F7R1_FB18 0x00040000U
2639 #define CAN_F7R1_FB19 0x00080000U
2640 #define CAN_F7R1_FB20 0x00100000U
2641 #define CAN_F7R1_FB21 0x00200000U
2642 #define CAN_F7R1_FB22 0x00400000U
2643 #define CAN_F7R1_FB23 0x00800000U
2644 #define CAN_F7R1_FB24 0x01000000U
2645 #define CAN_F7R1_FB25 0x02000000U
2646 #define CAN_F7R1_FB26 0x04000000U
2647 #define CAN_F7R1_FB27 0x08000000U
2648 #define CAN_F7R1_FB28 0x10000000U
2649 #define CAN_F7R1_FB29 0x20000000U
2650 #define CAN_F7R1_FB30 0x40000000U
2651 #define CAN_F7R1_FB31 0x80000000U
2653 /******************* Bit definition for CAN_F8R1 register *******************/
2654 #define CAN_F8R1_FB0 0x00000001U
2655 #define CAN_F8R1_FB1 0x00000002U
2656 #define CAN_F8R1_FB2 0x00000004U
2657 #define CAN_F8R1_FB3 0x00000008U
2658 #define CAN_F8R1_FB4 0x00000010U
2659 #define CAN_F8R1_FB5 0x00000020U
2660 #define CAN_F8R1_FB6 0x00000040U
2661 #define CAN_F8R1_FB7 0x00000080U
2662 #define CAN_F8R1_FB8 0x00000100U
2663 #define CAN_F8R1_FB9 0x00000200U
2664 #define CAN_F8R1_FB10 0x00000400U
2665 #define CAN_F8R1_FB11 0x00000800U
2666 #define CAN_F8R1_FB12 0x00001000U
2667 #define CAN_F8R1_FB13 0x00002000U
2668 #define CAN_F8R1_FB14 0x00004000U
2669 #define CAN_F8R1_FB15 0x00008000U
2670 #define CAN_F8R1_FB16 0x00010000U
2671 #define CAN_F8R1_FB17 0x00020000U
2672 #define CAN_F8R1_FB18 0x00040000U
2673 #define CAN_F8R1_FB19 0x00080000U
2674 #define CAN_F8R1_FB20 0x00100000U
2675 #define CAN_F8R1_FB21 0x00200000U
2676 #define CAN_F8R1_FB22 0x00400000U
2677 #define CAN_F8R1_FB23 0x00800000U
2678 #define CAN_F8R1_FB24 0x01000000U
2679 #define CAN_F8R1_FB25 0x02000000U
2680 #define CAN_F8R1_FB26 0x04000000U
2681 #define CAN_F8R1_FB27 0x08000000U
2682 #define CAN_F8R1_FB28 0x10000000U
2683 #define CAN_F8R1_FB29 0x20000000U
2684 #define CAN_F8R1_FB30 0x40000000U
2685 #define CAN_F8R1_FB31 0x80000000U
2687 /******************* Bit definition for CAN_F9R1 register *******************/
2688 #define CAN_F9R1_FB0 0x00000001U
2689 #define CAN_F9R1_FB1 0x00000002U
2690 #define CAN_F9R1_FB2 0x00000004U
2691 #define CAN_F9R1_FB3 0x00000008U
2692 #define CAN_F9R1_FB4 0x00000010U
2693 #define CAN_F9R1_FB5 0x00000020U
2694 #define CAN_F9R1_FB6 0x00000040U
2695 #define CAN_F9R1_FB7 0x00000080U
2696 #define CAN_F9R1_FB8 0x00000100U
2697 #define CAN_F9R1_FB9 0x00000200U
2698 #define CAN_F9R1_FB10 0x00000400U
2699 #define CAN_F9R1_FB11 0x00000800U
2700 #define CAN_F9R1_FB12 0x00001000U
2701 #define CAN_F9R1_FB13 0x00002000U
2702 #define CAN_F9R1_FB14 0x00004000U
2703 #define CAN_F9R1_FB15 0x00008000U
2704 #define CAN_F9R1_FB16 0x00010000U
2705 #define CAN_F9R1_FB17 0x00020000U
2706 #define CAN_F9R1_FB18 0x00040000U
2707 #define CAN_F9R1_FB19 0x00080000U
2708 #define CAN_F9R1_FB20 0x00100000U
2709 #define CAN_F9R1_FB21 0x00200000U
2710 #define CAN_F9R1_FB22 0x00400000U
2711 #define CAN_F9R1_FB23 0x00800000U
2712 #define CAN_F9R1_FB24 0x01000000U
2713 #define CAN_F9R1_FB25 0x02000000U
2714 #define CAN_F9R1_FB26 0x04000000U
2715 #define CAN_F9R1_FB27 0x08000000U
2716 #define CAN_F9R1_FB28 0x10000000U
2717 #define CAN_F9R1_FB29 0x20000000U
2718 #define CAN_F9R1_FB30 0x40000000U
2719 #define CAN_F9R1_FB31 0x80000000U
2721 /******************* Bit definition for CAN_F10R1 register ******************/
2722 #define CAN_F10R1_FB0 0x00000001U
2723 #define CAN_F10R1_FB1 0x00000002U
2724 #define CAN_F10R1_FB2 0x00000004U
2725 #define CAN_F10R1_FB3 0x00000008U
2726 #define CAN_F10R1_FB4 0x00000010U
2727 #define CAN_F10R1_FB5 0x00000020U
2728 #define CAN_F10R1_FB6 0x00000040U
2729 #define CAN_F10R1_FB7 0x00000080U
2730 #define CAN_F10R1_FB8 0x00000100U
2731 #define CAN_F10R1_FB9 0x00000200U
2732 #define CAN_F10R1_FB10 0x00000400U
2733 #define CAN_F10R1_FB11 0x00000800U
2734 #define CAN_F10R1_FB12 0x00001000U
2735 #define CAN_F10R1_FB13 0x00002000U
2736 #define CAN_F10R1_FB14 0x00004000U
2737 #define CAN_F10R1_FB15 0x00008000U
2738 #define CAN_F10R1_FB16 0x00010000U
2739 #define CAN_F10R1_FB17 0x00020000U
2740 #define CAN_F10R1_FB18 0x00040000U
2741 #define CAN_F10R1_FB19 0x00080000U
2742 #define CAN_F10R1_FB20 0x00100000U
2743 #define CAN_F10R1_FB21 0x00200000U
2744 #define CAN_F10R1_FB22 0x00400000U
2745 #define CAN_F10R1_FB23 0x00800000U
2746 #define CAN_F10R1_FB24 0x01000000U
2747 #define CAN_F10R1_FB25 0x02000000U
2748 #define CAN_F10R1_FB26 0x04000000U
2749 #define CAN_F10R1_FB27 0x08000000U
2750 #define CAN_F10R1_FB28 0x10000000U
2751 #define CAN_F10R1_FB29 0x20000000U
2752 #define CAN_F10R1_FB30 0x40000000U
2753 #define CAN_F10R1_FB31 0x80000000U
2755 /******************* Bit definition for CAN_F11R1 register ******************/
2756 #define CAN_F11R1_FB0 0x00000001U
2757 #define CAN_F11R1_FB1 0x00000002U
2758 #define CAN_F11R1_FB2 0x00000004U
2759 #define CAN_F11R1_FB3 0x00000008U
2760 #define CAN_F11R1_FB4 0x00000010U
2761 #define CAN_F11R1_FB5 0x00000020U
2762 #define CAN_F11R1_FB6 0x00000040U
2763 #define CAN_F11R1_FB7 0x00000080U
2764 #define CAN_F11R1_FB8 0x00000100U
2765 #define CAN_F11R1_FB9 0x00000200U
2766 #define CAN_F11R1_FB10 0x00000400U
2767 #define CAN_F11R1_FB11 0x00000800U
2768 #define CAN_F11R1_FB12 0x00001000U
2769 #define CAN_F11R1_FB13 0x00002000U
2770 #define CAN_F11R1_FB14 0x00004000U
2771 #define CAN_F11R1_FB15 0x00008000U
2772 #define CAN_F11R1_FB16 0x00010000U
2773 #define CAN_F11R1_FB17 0x00020000U
2774 #define CAN_F11R1_FB18 0x00040000U
2775 #define CAN_F11R1_FB19 0x00080000U
2776 #define CAN_F11R1_FB20 0x00100000U
2777 #define CAN_F11R1_FB21 0x00200000U
2778 #define CAN_F11R1_FB22 0x00400000U
2779 #define CAN_F11R1_FB23 0x00800000U
2780 #define CAN_F11R1_FB24 0x01000000U
2781 #define CAN_F11R1_FB25 0x02000000U
2782 #define CAN_F11R1_FB26 0x04000000U
2783 #define CAN_F11R1_FB27 0x08000000U
2784 #define CAN_F11R1_FB28 0x10000000U
2785 #define CAN_F11R1_FB29 0x20000000U
2786 #define CAN_F11R1_FB30 0x40000000U
2787 #define CAN_F11R1_FB31 0x80000000U
2789 /******************* Bit definition for CAN_F12R1 register ******************/
2790 #define CAN_F12R1_FB0 0x00000001U
2791 #define CAN_F12R1_FB1 0x00000002U
2792 #define CAN_F12R1_FB2 0x00000004U
2793 #define CAN_F12R1_FB3 0x00000008U
2794 #define CAN_F12R1_FB4 0x00000010U
2795 #define CAN_F12R1_FB5 0x00000020U
2796 #define CAN_F12R1_FB6 0x00000040U
2797 #define CAN_F12R1_FB7 0x00000080U
2798 #define CAN_F12R1_FB8 0x00000100U
2799 #define CAN_F12R1_FB9 0x00000200U
2800 #define CAN_F12R1_FB10 0x00000400U
2801 #define CAN_F12R1_FB11 0x00000800U
2802 #define CAN_F12R1_FB12 0x00001000U
2803 #define CAN_F12R1_FB13 0x00002000U
2804 #define CAN_F12R1_FB14 0x00004000U
2805 #define CAN_F12R1_FB15 0x00008000U
2806 #define CAN_F12R1_FB16 0x00010000U
2807 #define CAN_F12R1_FB17 0x00020000U
2808 #define CAN_F12R1_FB18 0x00040000U
2809 #define CAN_F12R1_FB19 0x00080000U
2810 #define CAN_F12R1_FB20 0x00100000U
2811 #define CAN_F12R1_FB21 0x00200000U
2812 #define CAN_F12R1_FB22 0x00400000U
2813 #define CAN_F12R1_FB23 0x00800000U
2814 #define CAN_F12R1_FB24 0x01000000U
2815 #define CAN_F12R1_FB25 0x02000000U
2816 #define CAN_F12R1_FB26 0x04000000U
2817 #define CAN_F12R1_FB27 0x08000000U
2818 #define CAN_F12R1_FB28 0x10000000U
2819 #define CAN_F12R1_FB29 0x20000000U
2820 #define CAN_F12R1_FB30 0x40000000U
2821 #define CAN_F12R1_FB31 0x80000000U
2823 /******************* Bit definition for CAN_F13R1 register ******************/
2824 #define CAN_F13R1_FB0 0x00000001U
2825 #define CAN_F13R1_FB1 0x00000002U
2826 #define CAN_F13R1_FB2 0x00000004U
2827 #define CAN_F13R1_FB3 0x00000008U
2828 #define CAN_F13R1_FB4 0x00000010U
2829 #define CAN_F13R1_FB5 0x00000020U
2830 #define CAN_F13R1_FB6 0x00000040U
2831 #define CAN_F13R1_FB7 0x00000080U
2832 #define CAN_F13R1_FB8 0x00000100U
2833 #define CAN_F13R1_FB9 0x00000200U
2834 #define CAN_F13R1_FB10 0x00000400U
2835 #define CAN_F13R1_FB11 0x00000800U
2836 #define CAN_F13R1_FB12 0x00001000U
2837 #define CAN_F13R1_FB13 0x00002000U
2838 #define CAN_F13R1_FB14 0x00004000U
2839 #define CAN_F13R1_FB15 0x00008000U
2840 #define CAN_F13R1_FB16 0x00010000U
2841 #define CAN_F13R1_FB17 0x00020000U
2842 #define CAN_F13R1_FB18 0x00040000U
2843 #define CAN_F13R1_FB19 0x00080000U
2844 #define CAN_F13R1_FB20 0x00100000U
2845 #define CAN_F13R1_FB21 0x00200000U
2846 #define CAN_F13R1_FB22 0x00400000U
2847 #define CAN_F13R1_FB23 0x00800000U
2848 #define CAN_F13R1_FB24 0x01000000U
2849 #define CAN_F13R1_FB25 0x02000000U
2850 #define CAN_F13R1_FB26 0x04000000U
2851 #define CAN_F13R1_FB27 0x08000000U
2852 #define CAN_F13R1_FB28 0x10000000U
2853 #define CAN_F13R1_FB29 0x20000000U
2854 #define CAN_F13R1_FB30 0x40000000U
2855 #define CAN_F13R1_FB31 0x80000000U
2857 /******************* Bit definition for CAN_F0R2 register *******************/
2858 #define CAN_F0R2_FB0 0x00000001U
2859 #define CAN_F0R2_FB1 0x00000002U
2860 #define CAN_F0R2_FB2 0x00000004U
2861 #define CAN_F0R2_FB3 0x00000008U
2862 #define CAN_F0R2_FB4 0x00000010U
2863 #define CAN_F0R2_FB5 0x00000020U
2864 #define CAN_F0R2_FB6 0x00000040U
2865 #define CAN_F0R2_FB7 0x00000080U
2866 #define CAN_F0R2_FB8 0x00000100U
2867 #define CAN_F0R2_FB9 0x00000200U
2868 #define CAN_F0R2_FB10 0x00000400U
2869 #define CAN_F0R2_FB11 0x00000800U
2870 #define CAN_F0R2_FB12 0x00001000U
2871 #define CAN_F0R2_FB13 0x00002000U
2872 #define CAN_F0R2_FB14 0x00004000U
2873 #define CAN_F0R2_FB15 0x00008000U
2874 #define CAN_F0R2_FB16 0x00010000U
2875 #define CAN_F0R2_FB17 0x00020000U
2876 #define CAN_F0R2_FB18 0x00040000U
2877 #define CAN_F0R2_FB19 0x00080000U
2878 #define CAN_F0R2_FB20 0x00100000U
2879 #define CAN_F0R2_FB21 0x00200000U
2880 #define CAN_F0R2_FB22 0x00400000U
2881 #define CAN_F0R2_FB23 0x00800000U
2882 #define CAN_F0R2_FB24 0x01000000U
2883 #define CAN_F0R2_FB25 0x02000000U
2884 #define CAN_F0R2_FB26 0x04000000U
2885 #define CAN_F0R2_FB27 0x08000000U
2886 #define CAN_F0R2_FB28 0x10000000U
2887 #define CAN_F0R2_FB29 0x20000000U
2888 #define CAN_F0R2_FB30 0x40000000U
2889 #define CAN_F0R2_FB31 0x80000000U
2891 /******************* Bit definition for CAN_F1R2 register *******************/
2892 #define CAN_F1R2_FB0 0x00000001U
2893 #define CAN_F1R2_FB1 0x00000002U
2894 #define CAN_F1R2_FB2 0x00000004U
2895 #define CAN_F1R2_FB3 0x00000008U
2896 #define CAN_F1R2_FB4 0x00000010U
2897 #define CAN_F1R2_FB5 0x00000020U
2898 #define CAN_F1R2_FB6 0x00000040U
2899 #define CAN_F1R2_FB7 0x00000080U
2900 #define CAN_F1R2_FB8 0x00000100U
2901 #define CAN_F1R2_FB9 0x00000200U
2902 #define CAN_F1R2_FB10 0x00000400U
2903 #define CAN_F1R2_FB11 0x00000800U
2904 #define CAN_F1R2_FB12 0x00001000U
2905 #define CAN_F1R2_FB13 0x00002000U
2906 #define CAN_F1R2_FB14 0x00004000U
2907 #define CAN_F1R2_FB15 0x00008000U
2908 #define CAN_F1R2_FB16 0x00010000U
2909 #define CAN_F1R2_FB17 0x00020000U
2910 #define CAN_F1R2_FB18 0x00040000U
2911 #define CAN_F1R2_FB19 0x00080000U
2912 #define CAN_F1R2_FB20 0x00100000U
2913 #define CAN_F1R2_FB21 0x00200000U
2914 #define CAN_F1R2_FB22 0x00400000U
2915 #define CAN_F1R2_FB23 0x00800000U
2916 #define CAN_F1R2_FB24 0x01000000U
2917 #define CAN_F1R2_FB25 0x02000000U
2918 #define CAN_F1R2_FB26 0x04000000U
2919 #define CAN_F1R2_FB27 0x08000000U
2920 #define CAN_F1R2_FB28 0x10000000U
2921 #define CAN_F1R2_FB29 0x20000000U
2922 #define CAN_F1R2_FB30 0x40000000U
2923 #define CAN_F1R2_FB31 0x80000000U
2925 /******************* Bit definition for CAN_F2R2 register *******************/
2926 #define CAN_F2R2_FB0 0x00000001U
2927 #define CAN_F2R2_FB1 0x00000002U
2928 #define CAN_F2R2_FB2 0x00000004U
2929 #define CAN_F2R2_FB3 0x00000008U
2930 #define CAN_F2R2_FB4 0x00000010U
2931 #define CAN_F2R2_FB5 0x00000020U
2932 #define CAN_F2R2_FB6 0x00000040U
2933 #define CAN_F2R2_FB7 0x00000080U
2934 #define CAN_F2R2_FB8 0x00000100U
2935 #define CAN_F2R2_FB9 0x00000200U
2936 #define CAN_F2R2_FB10 0x00000400U
2937 #define CAN_F2R2_FB11 0x00000800U
2938 #define CAN_F2R2_FB12 0x00001000U
2939 #define CAN_F2R2_FB13 0x00002000U
2940 #define CAN_F2R2_FB14 0x00004000U
2941 #define CAN_F2R2_FB15 0x00008000U
2942 #define CAN_F2R2_FB16 0x00010000U
2943 #define CAN_F2R2_FB17 0x00020000U
2944 #define CAN_F2R2_FB18 0x00040000U
2945 #define CAN_F2R2_FB19 0x00080000U
2946 #define CAN_F2R2_FB20 0x00100000U
2947 #define CAN_F2R2_FB21 0x00200000U
2948 #define CAN_F2R2_FB22 0x00400000U
2949 #define CAN_F2R2_FB23 0x00800000U
2950 #define CAN_F2R2_FB24 0x01000000U
2951 #define CAN_F2R2_FB25 0x02000000U
2952 #define CAN_F2R2_FB26 0x04000000U
2953 #define CAN_F2R2_FB27 0x08000000U
2954 #define CAN_F2R2_FB28 0x10000000U
2955 #define CAN_F2R2_FB29 0x20000000U
2956 #define CAN_F2R2_FB30 0x40000000U
2957 #define CAN_F2R2_FB31 0x80000000U
2959 /******************* Bit definition for CAN_F3R2 register *******************/
2960 #define CAN_F3R2_FB0 0x00000001U
2961 #define CAN_F3R2_FB1 0x00000002U
2962 #define CAN_F3R2_FB2 0x00000004U
2963 #define CAN_F3R2_FB3 0x00000008U
2964 #define CAN_F3R2_FB4 0x00000010U
2965 #define CAN_F3R2_FB5 0x00000020U
2966 #define CAN_F3R2_FB6 0x00000040U
2967 #define CAN_F3R2_FB7 0x00000080U
2968 #define CAN_F3R2_FB8 0x00000100U
2969 #define CAN_F3R2_FB9 0x00000200U
2970 #define CAN_F3R2_FB10 0x00000400U
2971 #define CAN_F3R2_FB11 0x00000800U
2972 #define CAN_F3R2_FB12 0x00001000U
2973 #define CAN_F3R2_FB13 0x00002000U
2974 #define CAN_F3R2_FB14 0x00004000U
2975 #define CAN_F3R2_FB15 0x00008000U
2976 #define CAN_F3R2_FB16 0x00010000U
2977 #define CAN_F3R2_FB17 0x00020000U
2978 #define CAN_F3R2_FB18 0x00040000U
2979 #define CAN_F3R2_FB19 0x00080000U
2980 #define CAN_F3R2_FB20 0x00100000U
2981 #define CAN_F3R2_FB21 0x00200000U
2982 #define CAN_F3R2_FB22 0x00400000U
2983 #define CAN_F3R2_FB23 0x00800000U
2984 #define CAN_F3R2_FB24 0x01000000U
2985 #define CAN_F3R2_FB25 0x02000000U
2986 #define CAN_F3R2_FB26 0x04000000U
2987 #define CAN_F3R2_FB27 0x08000000U
2988 #define CAN_F3R2_FB28 0x10000000U
2989 #define CAN_F3R2_FB29 0x20000000U
2990 #define CAN_F3R2_FB30 0x40000000U
2991 #define CAN_F3R2_FB31 0x80000000U
2993 /******************* Bit definition for CAN_F4R2 register *******************/
2994 #define CAN_F4R2_FB0 0x00000001U
2995 #define CAN_F4R2_FB1 0x00000002U
2996 #define CAN_F4R2_FB2 0x00000004U
2997 #define CAN_F4R2_FB3 0x00000008U
2998 #define CAN_F4R2_FB4 0x00000010U
2999 #define CAN_F4R2_FB5 0x00000020U
3000 #define CAN_F4R2_FB6 0x00000040U
3001 #define CAN_F4R2_FB7 0x00000080U
3002 #define CAN_F4R2_FB8 0x00000100U
3003 #define CAN_F4R2_FB9 0x00000200U
3004 #define CAN_F4R2_FB10 0x00000400U
3005 #define CAN_F4R2_FB11 0x00000800U
3006 #define CAN_F4R2_FB12 0x00001000U
3007 #define CAN_F4R2_FB13 0x00002000U
3008 #define CAN_F4R2_FB14 0x00004000U
3009 #define CAN_F4R2_FB15 0x00008000U
3010 #define CAN_F4R2_FB16 0x00010000U
3011 #define CAN_F4R2_FB17 0x00020000U
3012 #define CAN_F4R2_FB18 0x00040000U
3013 #define CAN_F4R2_FB19 0x00080000U
3014 #define CAN_F4R2_FB20 0x00100000U
3015 #define CAN_F4R2_FB21 0x00200000U
3016 #define CAN_F4R2_FB22 0x00400000U
3017 #define CAN_F4R2_FB23 0x00800000U
3018 #define CAN_F4R2_FB24 0x01000000U
3019 #define CAN_F4R2_FB25 0x02000000U
3020 #define CAN_F4R2_FB26 0x04000000U
3021 #define CAN_F4R2_FB27 0x08000000U
3022 #define CAN_F4R2_FB28 0x10000000U
3023 #define CAN_F4R2_FB29 0x20000000U
3024 #define CAN_F4R2_FB30 0x40000000U
3025 #define CAN_F4R2_FB31 0x80000000U
3027 /******************* Bit definition for CAN_F5R2 register *******************/
3028 #define CAN_F5R2_FB0 0x00000001U
3029 #define CAN_F5R2_FB1 0x00000002U
3030 #define CAN_F5R2_FB2 0x00000004U
3031 #define CAN_F5R2_FB3 0x00000008U
3032 #define CAN_F5R2_FB4 0x00000010U
3033 #define CAN_F5R2_FB5 0x00000020U
3034 #define CAN_F5R2_FB6 0x00000040U
3035 #define CAN_F5R2_FB7 0x00000080U
3036 #define CAN_F5R2_FB8 0x00000100U
3037 #define CAN_F5R2_FB9 0x00000200U
3038 #define CAN_F5R2_FB10 0x00000400U
3039 #define CAN_F5R2_FB11 0x00000800U
3040 #define CAN_F5R2_FB12 0x00001000U
3041 #define CAN_F5R2_FB13 0x00002000U
3042 #define CAN_F5R2_FB14 0x00004000U
3043 #define CAN_F5R2_FB15 0x00008000U
3044 #define CAN_F5R2_FB16 0x00010000U
3045 #define CAN_F5R2_FB17 0x00020000U
3046 #define CAN_F5R2_FB18 0x00040000U
3047 #define CAN_F5R2_FB19 0x00080000U
3048 #define CAN_F5R2_FB20 0x00100000U
3049 #define CAN_F5R2_FB21 0x00200000U
3050 #define CAN_F5R2_FB22 0x00400000U
3051 #define CAN_F5R2_FB23 0x00800000U
3052 #define CAN_F5R2_FB24 0x01000000U
3053 #define CAN_F5R2_FB25 0x02000000U
3054 #define CAN_F5R2_FB26 0x04000000U
3055 #define CAN_F5R2_FB27 0x08000000U
3056 #define CAN_F5R2_FB28 0x10000000U
3057 #define CAN_F5R2_FB29 0x20000000U
3058 #define CAN_F5R2_FB30 0x40000000U
3059 #define CAN_F5R2_FB31 0x80000000U
3061 /******************* Bit definition for CAN_F6R2 register *******************/
3062 #define CAN_F6R2_FB0 0x00000001U
3063 #define CAN_F6R2_FB1 0x00000002U
3064 #define CAN_F6R2_FB2 0x00000004U
3065 #define CAN_F6R2_FB3 0x00000008U
3066 #define CAN_F6R2_FB4 0x00000010U
3067 #define CAN_F6R2_FB5 0x00000020U
3068 #define CAN_F6R2_FB6 0x00000040U
3069 #define CAN_F6R2_FB7 0x00000080U
3070 #define CAN_F6R2_FB8 0x00000100U
3071 #define CAN_F6R2_FB9 0x00000200U
3072 #define CAN_F6R2_FB10 0x00000400U
3073 #define CAN_F6R2_FB11 0x00000800U
3074 #define CAN_F6R2_FB12 0x00001000U
3075 #define CAN_F6R2_FB13 0x00002000U
3076 #define CAN_F6R2_FB14 0x00004000U
3077 #define CAN_F6R2_FB15 0x00008000U
3078 #define CAN_F6R2_FB16 0x00010000U
3079 #define CAN_F6R2_FB17 0x00020000U
3080 #define CAN_F6R2_FB18 0x00040000U
3081 #define CAN_F6R2_FB19 0x00080000U
3082 #define CAN_F6R2_FB20 0x00100000U
3083 #define CAN_F6R2_FB21 0x00200000U
3084 #define CAN_F6R2_FB22 0x00400000U
3085 #define CAN_F6R2_FB23 0x00800000U
3086 #define CAN_F6R2_FB24 0x01000000U
3087 #define CAN_F6R2_FB25 0x02000000U
3088 #define CAN_F6R2_FB26 0x04000000U
3089 #define CAN_F6R2_FB27 0x08000000U
3090 #define CAN_F6R2_FB28 0x10000000U
3091 #define CAN_F6R2_FB29 0x20000000U
3092 #define CAN_F6R2_FB30 0x40000000U
3093 #define CAN_F6R2_FB31 0x80000000U
3095 /******************* Bit definition for CAN_F7R2 register *******************/
3096 #define CAN_F7R2_FB0 0x00000001U
3097 #define CAN_F7R2_FB1 0x00000002U
3098 #define CAN_F7R2_FB2 0x00000004U
3099 #define CAN_F7R2_FB3 0x00000008U
3100 #define CAN_F7R2_FB4 0x00000010U
3101 #define CAN_F7R2_FB5 0x00000020U
3102 #define CAN_F7R2_FB6 0x00000040U
3103 #define CAN_F7R2_FB7 0x00000080U
3104 #define CAN_F7R2_FB8 0x00000100U
3105 #define CAN_F7R2_FB9 0x00000200U
3106 #define CAN_F7R2_FB10 0x00000400U
3107 #define CAN_F7R2_FB11 0x00000800U
3108 #define CAN_F7R2_FB12 0x00001000U
3109 #define CAN_F7R2_FB13 0x00002000U
3110 #define CAN_F7R2_FB14 0x00004000U
3111 #define CAN_F7R2_FB15 0x00008000U
3112 #define CAN_F7R2_FB16 0x00010000U
3113 #define CAN_F7R2_FB17 0x00020000U
3114 #define CAN_F7R2_FB18 0x00040000U
3115 #define CAN_F7R2_FB19 0x00080000U
3116 #define CAN_F7R2_FB20 0x00100000U
3117 #define CAN_F7R2_FB21 0x00200000U
3118 #define CAN_F7R2_FB22 0x00400000U
3119 #define CAN_F7R2_FB23 0x00800000U
3120 #define CAN_F7R2_FB24 0x01000000U
3121 #define CAN_F7R2_FB25 0x02000000U
3122 #define CAN_F7R2_FB26 0x04000000U
3123 #define CAN_F7R2_FB27 0x08000000U
3124 #define CAN_F7R2_FB28 0x10000000U
3125 #define CAN_F7R2_FB29 0x20000000U
3126 #define CAN_F7R2_FB30 0x40000000U
3127 #define CAN_F7R2_FB31 0x80000000U
3129 /******************* Bit definition for CAN_F8R2 register *******************/
3130 #define CAN_F8R2_FB0 0x00000001U
3131 #define CAN_F8R2_FB1 0x00000002U
3132 #define CAN_F8R2_FB2 0x00000004U
3133 #define CAN_F8R2_FB3 0x00000008U
3134 #define CAN_F8R2_FB4 0x00000010U
3135 #define CAN_F8R2_FB5 0x00000020U
3136 #define CAN_F8R2_FB6 0x00000040U
3137 #define CAN_F8R2_FB7 0x00000080U
3138 #define CAN_F8R2_FB8 0x00000100U
3139 #define CAN_F8R2_FB9 0x00000200U
3140 #define CAN_F8R2_FB10 0x00000400U
3141 #define CAN_F8R2_FB11 0x00000800U
3142 #define CAN_F8R2_FB12 0x00001000U
3143 #define CAN_F8R2_FB13 0x00002000U
3144 #define CAN_F8R2_FB14 0x00004000U
3145 #define CAN_F8R2_FB15 0x00008000U
3146 #define CAN_F8R2_FB16 0x00010000U
3147 #define CAN_F8R2_FB17 0x00020000U
3148 #define CAN_F8R2_FB18 0x00040000U
3149 #define CAN_F8R2_FB19 0x00080000U
3150 #define CAN_F8R2_FB20 0x00100000U
3151 #define CAN_F8R2_FB21 0x00200000U
3152 #define CAN_F8R2_FB22 0x00400000U
3153 #define CAN_F8R2_FB23 0x00800000U
3154 #define CAN_F8R2_FB24 0x01000000U
3155 #define CAN_F8R2_FB25 0x02000000U
3156 #define CAN_F8R2_FB26 0x04000000U
3157 #define CAN_F8R2_FB27 0x08000000U
3158 #define CAN_F8R2_FB28 0x10000000U
3159 #define CAN_F8R2_FB29 0x20000000U
3160 #define CAN_F8R2_FB30 0x40000000U
3161 #define CAN_F8R2_FB31 0x80000000U
3163 /******************* Bit definition for CAN_F9R2 register *******************/
3164 #define CAN_F9R2_FB0 0x00000001U
3165 #define CAN_F9R2_FB1 0x00000002U
3166 #define CAN_F9R2_FB2 0x00000004U
3167 #define CAN_F9R2_FB3 0x00000008U
3168 #define CAN_F9R2_FB4 0x00000010U
3169 #define CAN_F9R2_FB5 0x00000020U
3170 #define CAN_F9R2_FB6 0x00000040U
3171 #define CAN_F9R2_FB7 0x00000080U
3172 #define CAN_F9R2_FB8 0x00000100U
3173 #define CAN_F9R2_FB9 0x00000200U
3174 #define CAN_F9R2_FB10 0x00000400U
3175 #define CAN_F9R2_FB11 0x00000800U
3176 #define CAN_F9R2_FB12 0x00001000U
3177 #define CAN_F9R2_FB13 0x00002000U
3178 #define CAN_F9R2_FB14 0x00004000U
3179 #define CAN_F9R2_FB15 0x00008000U
3180 #define CAN_F9R2_FB16 0x00010000U
3181 #define CAN_F9R2_FB17 0x00020000U
3182 #define CAN_F9R2_FB18 0x00040000U
3183 #define CAN_F9R2_FB19 0x00080000U
3184 #define CAN_F9R2_FB20 0x00100000U
3185 #define CAN_F9R2_FB21 0x00200000U
3186 #define CAN_F9R2_FB22 0x00400000U
3187 #define CAN_F9R2_FB23 0x00800000U
3188 #define CAN_F9R2_FB24 0x01000000U
3189 #define CAN_F9R2_FB25 0x02000000U
3190 #define CAN_F9R2_FB26 0x04000000U
3191 #define CAN_F9R2_FB27 0x08000000U
3192 #define CAN_F9R2_FB28 0x10000000U
3193 #define CAN_F9R2_FB29 0x20000000U
3194 #define CAN_F9R2_FB30 0x40000000U
3195 #define CAN_F9R2_FB31 0x80000000U
3197 /******************* Bit definition for CAN_F10R2 register ******************/
3198 #define CAN_F10R2_FB0 0x00000001U
3199 #define CAN_F10R2_FB1 0x00000002U
3200 #define CAN_F10R2_FB2 0x00000004U
3201 #define CAN_F10R2_FB3 0x00000008U
3202 #define CAN_F10R2_FB4 0x00000010U
3203 #define CAN_F10R2_FB5 0x00000020U
3204 #define CAN_F10R2_FB6 0x00000040U
3205 #define CAN_F10R2_FB7 0x00000080U
3206 #define CAN_F10R2_FB8 0x00000100U
3207 #define CAN_F10R2_FB9 0x00000200U
3208 #define CAN_F10R2_FB10 0x00000400U
3209 #define CAN_F10R2_FB11 0x00000800U
3210 #define CAN_F10R2_FB12 0x00001000U
3211 #define CAN_F10R2_FB13 0x00002000U
3212 #define CAN_F10R2_FB14 0x00004000U
3213 #define CAN_F10R2_FB15 0x00008000U
3214 #define CAN_F10R2_FB16 0x00010000U
3215 #define CAN_F10R2_FB17 0x00020000U
3216 #define CAN_F10R2_FB18 0x00040000U
3217 #define CAN_F10R2_FB19 0x00080000U
3218 #define CAN_F10R2_FB20 0x00100000U
3219 #define CAN_F10R2_FB21 0x00200000U
3220 #define CAN_F10R2_FB22 0x00400000U
3221 #define CAN_F10R2_FB23 0x00800000U
3222 #define CAN_F10R2_FB24 0x01000000U
3223 #define CAN_F10R2_FB25 0x02000000U
3224 #define CAN_F10R2_FB26 0x04000000U
3225 #define CAN_F10R2_FB27 0x08000000U
3226 #define CAN_F10R2_FB28 0x10000000U
3227 #define CAN_F10R2_FB29 0x20000000U
3228 #define CAN_F10R2_FB30 0x40000000U
3229 #define CAN_F10R2_FB31 0x80000000U
3231 /******************* Bit definition for CAN_F11R2 register ******************/
3232 #define CAN_F11R2_FB0 0x00000001U
3233 #define CAN_F11R2_FB1 0x00000002U
3234 #define CAN_F11R2_FB2 0x00000004U
3235 #define CAN_F11R2_FB3 0x00000008U
3236 #define CAN_F11R2_FB4 0x00000010U
3237 #define CAN_F11R2_FB5 0x00000020U
3238 #define CAN_F11R2_FB6 0x00000040U
3239 #define CAN_F11R2_FB7 0x00000080U
3240 #define CAN_F11R2_FB8 0x00000100U
3241 #define CAN_F11R2_FB9 0x00000200U
3242 #define CAN_F11R2_FB10 0x00000400U
3243 #define CAN_F11R2_FB11 0x00000800U
3244 #define CAN_F11R2_FB12 0x00001000U
3245 #define CAN_F11R2_FB13 0x00002000U
3246 #define CAN_F11R2_FB14 0x00004000U
3247 #define CAN_F11R2_FB15 0x00008000U
3248 #define CAN_F11R2_FB16 0x00010000U
3249 #define CAN_F11R2_FB17 0x00020000U
3250 #define CAN_F11R2_FB18 0x00040000U
3251 #define CAN_F11R2_FB19 0x00080000U
3252 #define CAN_F11R2_FB20 0x00100000U
3253 #define CAN_F11R2_FB21 0x00200000U
3254 #define CAN_F11R2_FB22 0x00400000U
3255 #define CAN_F11R2_FB23 0x00800000U
3256 #define CAN_F11R2_FB24 0x01000000U
3257 #define CAN_F11R2_FB25 0x02000000U
3258 #define CAN_F11R2_FB26 0x04000000U
3259 #define CAN_F11R2_FB27 0x08000000U
3260 #define CAN_F11R2_FB28 0x10000000U
3261 #define CAN_F11R2_FB29 0x20000000U
3262 #define CAN_F11R2_FB30 0x40000000U
3263 #define CAN_F11R2_FB31 0x80000000U
3265 /******************* Bit definition for CAN_F12R2 register ******************/
3266 #define CAN_F12R2_FB0 0x00000001U
3267 #define CAN_F12R2_FB1 0x00000002U
3268 #define CAN_F12R2_FB2 0x00000004U
3269 #define CAN_F12R2_FB3 0x00000008U
3270 #define CAN_F12R2_FB4 0x00000010U
3271 #define CAN_F12R2_FB5 0x00000020U
3272 #define CAN_F12R2_FB6 0x00000040U
3273 #define CAN_F12R2_FB7 0x00000080U
3274 #define CAN_F12R2_FB8 0x00000100U
3275 #define CAN_F12R2_FB9 0x00000200U
3276 #define CAN_F12R2_FB10 0x00000400U
3277 #define CAN_F12R2_FB11 0x00000800U
3278 #define CAN_F12R2_FB12 0x00001000U
3279 #define CAN_F12R2_FB13 0x00002000U
3280 #define CAN_F12R2_FB14 0x00004000U
3281 #define CAN_F12R2_FB15 0x00008000U
3282 #define CAN_F12R2_FB16 0x00010000U
3283 #define CAN_F12R2_FB17 0x00020000U
3284 #define CAN_F12R2_FB18 0x00040000U
3285 #define CAN_F12R2_FB19 0x00080000U
3286 #define CAN_F12R2_FB20 0x00100000U
3287 #define CAN_F12R2_FB21 0x00200000U
3288 #define CAN_F12R2_FB22 0x00400000U
3289 #define CAN_F12R2_FB23 0x00800000U
3290 #define CAN_F12R2_FB24 0x01000000U
3291 #define CAN_F12R2_FB25 0x02000000U
3292 #define CAN_F12R2_FB26 0x04000000U
3293 #define CAN_F12R2_FB27 0x08000000U
3294 #define CAN_F12R2_FB28 0x10000000U
3295 #define CAN_F12R2_FB29 0x20000000U
3296 #define CAN_F12R2_FB30 0x40000000U
3297 #define CAN_F12R2_FB31 0x80000000U
3299 /******************* Bit definition for CAN_F13R2 register ******************/
3300 #define CAN_F13R2_FB0 0x00000001U
3301 #define CAN_F13R2_FB1 0x00000002U
3302 #define CAN_F13R2_FB2 0x00000004U
3303 #define CAN_F13R2_FB3 0x00000008U
3304 #define CAN_F13R2_FB4 0x00000010U
3305 #define CAN_F13R2_FB5 0x00000020U
3306 #define CAN_F13R2_FB6 0x00000040U
3307 #define CAN_F13R2_FB7 0x00000080U
3308 #define CAN_F13R2_FB8 0x00000100U
3309 #define CAN_F13R2_FB9 0x00000200U
3310 #define CAN_F13R2_FB10 0x00000400U
3311 #define CAN_F13R2_FB11 0x00000800U
3312 #define CAN_F13R2_FB12 0x00001000U
3313 #define CAN_F13R2_FB13 0x00002000U
3314 #define CAN_F13R2_FB14 0x00004000U
3315 #define CAN_F13R2_FB15 0x00008000U
3316 #define CAN_F13R2_FB16 0x00010000U
3317 #define CAN_F13R2_FB17 0x00020000U
3318 #define CAN_F13R2_FB18 0x00040000U
3319 #define CAN_F13R2_FB19 0x00080000U
3320 #define CAN_F13R2_FB20 0x00100000U
3321 #define CAN_F13R2_FB21 0x00200000U
3322 #define CAN_F13R2_FB22 0x00400000U
3323 #define CAN_F13R2_FB23 0x00800000U
3324 #define CAN_F13R2_FB24 0x01000000U
3325 #define CAN_F13R2_FB25 0x02000000U
3326 #define CAN_F13R2_FB26 0x04000000U
3327 #define CAN_F13R2_FB27 0x08000000U
3328 #define CAN_F13R2_FB28 0x10000000U
3329 #define CAN_F13R2_FB29 0x20000000U
3330 #define CAN_F13R2_FB30 0x40000000U
3331 #define CAN_F13R2_FB31 0x80000000U
3333 /******************************************************************************/
3334 /* */
3335 /* HDMI-CEC (CEC) */
3336 /* */
3337 /******************************************************************************/
3338 
3339 /******************* Bit definition for CEC_CR register *********************/
3340 #define CEC_CR_CECEN 0x00000001U
3341 #define CEC_CR_TXSOM 0x00000002U
3342 #define CEC_CR_TXEOM 0x00000004U
3344 /******************* Bit definition for CEC_CFGR register *******************/
3345 #define CEC_CFGR_SFT 0x00000007U
3346 #define CEC_CFGR_RXTOL 0x00000008U
3347 #define CEC_CFGR_BRESTP 0x00000010U
3348 #define CEC_CFGR_BREGEN 0x00000020U
3349 #define CEC_CFGR_LBPEGEN 0x00000040U
3350 #define CEC_CFGR_BRDNOGEN 0x00000080U
3351 #define CEC_CFGR_SFTOPT 0x00000100U
3352 #define CEC_CFGR_OAR 0x7FFF0000U
3353 #define CEC_CFGR_LSTN 0x80000000U
3355 /******************* Bit definition for CEC_TXDR register *******************/
3356 #define CEC_TXDR_TXD 0x000000FFU
3358 /******************* Bit definition for CEC_RXDR register *******************/
3359 #define CEC_TXDR_RXD 0x000000FFU
3361 /******************* Bit definition for CEC_ISR register ********************/
3362 #define CEC_ISR_RXBR 0x00000001U
3363 #define CEC_ISR_RXEND 0x00000002U
3364 #define CEC_ISR_RXOVR 0x00000004U
3365 #define CEC_ISR_BRE 0x00000008U
3366 #define CEC_ISR_SBPE 0x00000010U
3367 #define CEC_ISR_LBPE 0x00000020U
3368 #define CEC_ISR_RXACKE 0x00000040U
3369 #define CEC_ISR_ARBLST 0x00000080U
3370 #define CEC_ISR_TXBR 0x00000100U
3371 #define CEC_ISR_TXEND 0x00000200U
3372 #define CEC_ISR_TXUDR 0x00000400U
3373 #define CEC_ISR_TXERR 0x00000800U
3374 #define CEC_ISR_TXACKE 0x00001000U
3376 /******************* Bit definition for CEC_IER register ********************/
3377 #define CEC_IER_RXBRIE 0x00000001U
3378 #define CEC_IER_RXENDIE 0x00000002U
3379 #define CEC_IER_RXOVRIE 0x00000004U
3380 #define CEC_IER_BREIE 0x00000008U
3381 #define CEC_IER_SBPEIE 0x00000010U
3382 #define CEC_IER_LBPEIE 0x00000020U
3383 #define CEC_IER_RXACKEIE 0x00000040U
3384 #define CEC_IER_ARBLSTIE 0x00000080U
3385 #define CEC_IER_TXBRIE 0x00000100U
3386 #define CEC_IER_TXENDIE 0x00000200U
3387 #define CEC_IER_TXUDRIE 0x00000400U
3388 #define CEC_IER_TXERRIE 0x00000800U
3389 #define CEC_IER_TXACKEIE 0x00001000U
3391 /******************************************************************************/
3392 /* */
3393 /* CRC calculation unit */
3394 /* */
3395 /******************************************************************************/
3396 /******************* Bit definition for CRC_DR register *********************/
3397 #define CRC_DR_DR 0xFFFFFFFFU
3399 /******************* Bit definition for CRC_IDR register ********************/
3400 #define CRC_IDR_IDR 0x000000FFU
3402 /******************** Bit definition for CRC_CR register ********************/
3403 #define CRC_CR_RESET 0x00000001U
3404 #define CRC_CR_POLYSIZE 0x00000018U
3405 #define CRC_CR_POLYSIZE_0 0x00000008U
3406 #define CRC_CR_POLYSIZE_1 0x00000010U
3407 #define CRC_CR_REV_IN 0x00000060U
3408 #define CRC_CR_REV_IN_0 0x00000020U
3409 #define CRC_CR_REV_IN_1 0x00000040U
3410 #define CRC_CR_REV_OUT 0x00000080U
3412 /******************* Bit definition for CRC_INIT register *******************/
3413 #define CRC_INIT_INIT 0xFFFFFFFFU
3415 /******************* Bit definition for CRC_POL register ********************/
3416 #define CRC_POL_POL 0xFFFFFFFFU
3419 /******************************************************************************/
3420 /* */
3421 /* Digital to Analog Converter */
3422 /* */
3423 /******************************************************************************/
3424 /******************** Bit definition for DAC_CR register ********************/
3425 #define DAC_CR_EN1 0x00000001U
3426 #define DAC_CR_BOFF1 0x00000002U
3427 #define DAC_CR_TEN1 0x00000004U
3428 #define DAC_CR_TSEL1 0x00000038U
3429 #define DAC_CR_TSEL1_0 0x00000008U
3430 #define DAC_CR_TSEL1_1 0x00000010U
3431 #define DAC_CR_TSEL1_2 0x00000020U
3432 #define DAC_CR_WAVE1 0x000000C0U
3433 #define DAC_CR_WAVE1_0 0x00000040U
3434 #define DAC_CR_WAVE1_1 0x00000080U
3435 #define DAC_CR_MAMP1 0x00000F00U
3436 #define DAC_CR_MAMP1_0 0x00000100U
3437 #define DAC_CR_MAMP1_1 0x00000200U
3438 #define DAC_CR_MAMP1_2 0x00000400U
3439 #define DAC_CR_MAMP1_3 0x00000800U
3440 #define DAC_CR_DMAEN1 0x00001000U
3441 #define DAC_CR_DMAUDRIE1 0x00002000U
3442 #define DAC_CR_EN2 0x00010000U
3443 #define DAC_CR_BOFF2 0x00020000U
3444 #define DAC_CR_TEN2 0x00040000U
3445 #define DAC_CR_TSEL2 0x00380000U
3446 #define DAC_CR_TSEL2_0 0x00080000U
3447 #define DAC_CR_TSEL2_1 0x00100000U
3448 #define DAC_CR_TSEL2_2 0x00200000U
3449 #define DAC_CR_WAVE2 0x00C00000U
3450 #define DAC_CR_WAVE2_0 0x00400000U
3451 #define DAC_CR_WAVE2_1 0x00800000U
3452 #define DAC_CR_MAMP2 0x0F000000U
3453 #define DAC_CR_MAMP2_0 0x01000000U
3454 #define DAC_CR_MAMP2_1 0x02000000U
3455 #define DAC_CR_MAMP2_2 0x04000000U
3456 #define DAC_CR_MAMP2_3 0x08000000U
3457 #define DAC_CR_DMAEN2 0x10000000U
3458 #define DAC_CR_DMAUDRIE2 0x20000000U
3460 /***************** Bit definition for DAC_SWTRIGR register ******************/
3461 #define DAC_SWTRIGR_SWTRIG1 0x01U
3462 #define DAC_SWTRIGR_SWTRIG2 0x02U
3464 /***************** Bit definition for DAC_DHR12R1 register ******************/
3465 #define DAC_DHR12R1_DACC1DHR 0x0FFFU
3467 /***************** Bit definition for DAC_DHR12L1 register ******************/
3468 #define DAC_DHR12L1_DACC1DHR 0xFFF0U
3470 /****************** Bit definition for DAC_DHR8R1 register ******************/
3471 #define DAC_DHR8R1_DACC1DHR 0xFFU
3473 /***************** Bit definition for DAC_DHR12R2 register ******************/
3474 #define DAC_DHR12R2_DACC2DHR 0x0FFFU
3476 /***************** Bit definition for DAC_DHR12L2 register ******************/
3477 #define DAC_DHR12L2_DACC2DHR 0xFFF0U
3479 /****************** Bit definition for DAC_DHR8R2 register ******************/
3480 #define DAC_DHR8R2_DACC2DHR 0xFFU
3482 /***************** Bit definition for DAC_DHR12RD register ******************/
3483 #define DAC_DHR12RD_DACC1DHR 0x00000FFFU
3484 #define DAC_DHR12RD_DACC2DHR 0x0FFF0000U
3486 /***************** Bit definition for DAC_DHR12LD register ******************/
3487 #define DAC_DHR12LD_DACC1DHR 0x0000FFF0U
3488 #define DAC_DHR12LD_DACC2DHR 0xFFF00000U
3490 /****************** Bit definition for DAC_DHR8RD register ******************/
3491 #define DAC_DHR8RD_DACC1DHR 0x00FFU
3492 #define DAC_DHR8RD_DACC2DHR 0xFF00U
3494 /******************* Bit definition for DAC_DOR1 register *******************/
3495 #define DAC_DOR1_DACC1DOR 0x0FFFU
3497 /******************* Bit definition for DAC_DOR2 register *******************/
3498 #define DAC_DOR2_DACC2DOR 0x0FFFU
3500 /******************** Bit definition for DAC_SR register ********************/
3501 #define DAC_SR_DMAUDR1 0x00002000U
3502 #define DAC_SR_DMAUDR2 0x20000000U
3504 /******************************************************************************/
3505 /* */
3506 /* Digital Filter for Sigma Delta Modulators */
3507 /* */
3508 /******************************************************************************/
3509 
3510 /**************** DFSDM channel configuration registers ********************/
3511 
3512 /*************** Bit definition for DFSDM_CHCFGR1 register ******************/
3513 #define DFSDM_CHCFGR1_DFSDMEN 0x80000000U
3514 #define DFSDM_CHCFGR1_CKOUTSRC 0x40000000U
3515 #define DFSDM_CHCFGR1_CKOUTDIV 0x00FF0000U
3516 #define DFSDM_CHCFGR1_DATPACK 0x0000C000U
3517 #define DFSDM_CHCFGR1_DATPACK_1 0x00008000U
3518 #define DFSDM_CHCFGR1_DATPACK_0 0x00004000U
3519 #define DFSDM_CHCFGR1_DATMPX 0x00003000U
3520 #define DFSDM_CHCFGR1_DATMPX_1 0x00002000U
3521 #define DFSDM_CHCFGR1_DATMPX_0 0x00001000U
3522 #define DFSDM_CHCFGR1_CHINSEL 0x00000100U
3523 #define DFSDM_CHCFGR1_CHEN 0x00000080U
3524 #define DFSDM_CHCFGR1_CKABEN 0x00000040U
3525 #define DFSDM_CHCFGR1_SCDEN 0x00000020U
3526 #define DFSDM_CHCFGR1_SPICKSEL 0x0000000CU
3527 #define DFSDM_CHCFGR1_SPICKSEL_1 0x00000008U
3528 #define DFSDM_CHCFGR1_SPICKSEL_0 0x00000004U
3529 #define DFSDM_CHCFGR1_SITP 0x00000003U
3530 #define DFSDM_CHCFGR1_SITP_1 0x00000002U
3531 #define DFSDM_CHCFGR1_SITP_0 0x00000001U
3533 /*************** Bit definition for DFSDM_CHCFGR2 register ******************/
3534 #define DFSDM_CHCFGR2_OFFSET 0xFFFFFF00U
3535 #define DFSDM_CHCFGR2_DTRBS 0x000000F8U
3537 /****************** Bit definition for DFSDM_CHAWSCDR register *****************/
3538 #define DFSDM_CHAWSCDR_AWFORD 0x00C00000U
3539 #define DFSDM_CHAWSCDR_AWFORD_1 0x00800000U
3540 #define DFSDM_CHAWSCDR_AWFORD_0 0x00400000U
3541 #define DFSDM_CHAWSCDR_AWFOSR 0x001F0000U
3542 #define DFSDM_CHAWSCDR_BKSCD 0x0000F000U
3543 #define DFSDM_CHAWSCDR_SCDT 0x000000FFU
3545 /**************** Bit definition for DFSDM_CHWDATR register *******************/
3546 #define DFSDM_CHWDATR_WDATA 0x0000FFFFU
3548 /**************** Bit definition for DFSDM_CHDATINR register *****************/
3549 #define DFSDM_CHDATINR_INDAT0 0x0000FFFFU
3550 #define DFSDM_CHDATINR_INDAT1 0xFFFF0000U
3552 /************************ DFSDM module registers ****************************/
3553 
3554 /******************** Bit definition for DFSDM_FLTCR1 register *******************/
3555 #define DFSDM_FLTCR1_AWFSEL 0x40000000U
3556 #define DFSDM_FLTCR1_FAST 0x20000000U
3557 #define DFSDM_FLTCR1_RCH 0x07000000U
3558 #define DFSDM_FLTCR1_RDMAEN 0x00200000U
3559 #define DFSDM_FLTCR1_RSYNC 0x00080000U
3560 #define DFSDM_FLTCR1_RCONT 0x00040000U
3561 #define DFSDM_FLTCR1_RSWSTART 0x00020000U
3562 #define DFSDM_FLTCR1_JEXTEN 0x00006000U
3563 #define DFSDM_FLTCR1_JEXTEN_1 0x00004000U
3564 #define DFSDM_FLTCR1_JEXTEN_0 0x00002000U
3565 #define DFSDM_FLTCR1_JEXTSEL 0x00001F00U
3566 #define DFSDM_FLTCR1_JEXTSEL_0 0x00000100U
3567 #define DFSDM_FLTCR1_JEXTSEL_1 0x00000200U
3568 #define DFSDM_FLTCR1_JEXTSEL_2 0x00000400U
3569 #define DFSDM_FLTCR1_JEXTSEL_3 0x00000800U
3570 #define DFSDM_FLTCR1_JEXTSEL_4 0x00001000U
3571 #define DFSDM_FLTCR1_JDMAEN 0x00000020U
3572 #define DFSDM_FLTCR1_JSCAN 0x00000010U
3573 #define DFSDM_FLTCR1_JSYNC 0x00000008U
3574 #define DFSDM_FLTCR1_JSWSTART 0x00000002U
3575 #define DFSDM_FLTCR1_DFEN 0x00000001U
3577 /******************** Bit definition for DFSDM_FLTCR2 register *******************/
3578 #define DFSDM_FLTCR2_AWDCH 0x00FF0000U
3579 #define DFSDM_FLTCR2_EXCH 0x0000FF00U
3580 #define DFSDM_FLTCR2_CKABIE 0x00000040U
3581 #define DFSDM_FLTCR2_SCDIE 0x00000020U
3582 #define DFSDM_FLTCR2_AWDIE 0x00000010U
3583 #define DFSDM_FLTCR2_ROVRIE 0x00000008U
3584 #define DFSDM_FLTCR2_JOVRIE 0x00000004U
3585 #define DFSDM_FLTCR2_REOCIE 0x00000002U
3586 #define DFSDM_FLTCR2_JEOCIE 0x00000001U
3588 /******************** Bit definition for DFSDM_FLTISR register *******************/
3589 #define DFSDM_FLTISR_SCDF 0xFF000000U
3590 #define DFSDM_FLTISR_CKABF 0x00FF0000U
3591 #define DFSDM_FLTISR_RCIP 0x00004000U
3592 #define DFSDM_FLTISR_JCIP 0x00002000U
3593 #define DFSDM_FLTISR_AWDF 0x00000010U
3594 #define DFSDM_FLTISR_ROVRF 0x00000008U
3595 #define DFSDM_FLTISR_JOVRF 0x00000004U
3596 #define DFSDM_FLTISR_REOCF 0x00000002U
3597 #define DFSDM_FLTISR_JEOCF 0x00000001U
3599 /******************** Bit definition for DFSDM_FLTICR register *******************/
3600 #define DFSDM_FLTICR_CLRSCSDF 0xFF000000U
3601 #define DFSDM_FLTICR_CLRCKABF 0x00FF0000U
3602 #define DFSDM_FLTICR_CLRROVRF 0x00000008U
3603 #define DFSDM_FLTICR_CLRJOVRF 0x00000004U
3605 /******************* Bit definition for DFSDM_FLTJCHGR register ******************/
3606 #define DFSDM_FLTJCHGR_JCHG 0x000000FFU
3608 /******************** Bit definition for DFSDM_FLTFCR register *******************/
3609 #define DFSDM_FLTFCR_FORD 0xE0000000U
3610 #define DFSDM_FLTFCR_FORD_2 0x80000000U
3611 #define DFSDM_FLTFCR_FORD_1 0x40000000U
3612 #define DFSDM_FLTFCR_FORD_0 0x20000000U
3613 #define DFSDM_FLTFCR_FOSR 0x03FF0000U
3614 #define DFSDM_FLTFCR_IOSR 0x000000FFU
3616 /****************** Bit definition for DFSDM_FLTJDATAR register *****************/
3617 #define DFSDM_FLTJDATAR_JDATA 0xFFFFFF00U
3618 #define DFSDM_FLTJDATAR_JDATACH 0x00000007U
3620 /****************** Bit definition for DFSDM_FLTRDATAR register *****************/
3621 #define DFSDM_FLTRDATAR_RDATA 0xFFFFFF00U
3622 #define DFSDM_FLTRDATAR_RPEND 0x00000010U
3623 #define DFSDM_FLTRDATAR_RDATACH 0x00000007U
3625 /****************** Bit definition for DFSDM_FLTAWHTR register ******************/
3626 #define DFSDM_FLTAWHTR_AWHT 0xFFFFFF00U
3627 #define DFSDM_FLTAWHTR_BKAWH 0x0000000FU
3629 /****************** Bit definition for DFSDM_FLTAWLTR register ******************/
3630 #define DFSDM_FLTAWLTR_AWLT 0xFFFFFF00U
3631 #define DFSDM_FLTAWLTR_BKAWL 0x0000000FU
3633 /****************** Bit definition for DFSDM_FLTAWSR register ******************/
3634 #define DFSDM_FLTAWSR_AWHTF 0x0000FF00U
3635 #define DFSDM_FLTAWSR_AWLTF 0x000000FFU
3637 /****************** Bit definition for DFSDM_FLTAWCFR register *****************/
3638 #define DFSDM_FLTAWCFR_CLRAWHTF 0x0000FF00U
3639 #define DFSDM_FLTAWCFR_CLRAWLTF 0x000000FFU
3641 /****************** Bit definition for DFSDM_FLTEXMAX register ******************/
3642 #define DFSDM_FLTEXMAX_EXMAX 0xFFFFFF00U
3643 #define DFSDM_FLTEXMAX_EXMAXCH 0x00000007U
3645 /****************** Bit definition for DFSDM_FLTEXMIN register ******************/
3646 #define DFSDM_FLTEXMIN_EXMIN 0xFFFFFF00U
3647 #define DFSDM_FLTEXMIN_EXMINCH 0x00000007U
3649 /****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/
3650 #define DFSDM_FLTCNVTIMR_CNVCNT 0xFFFFFFF0U
3652 /******************************************************************************/
3653 /* */
3654 /* Debug MCU */
3655 /* */
3656 /******************************************************************************/
3657 
3658 /******************************************************************************/
3659 /* */
3660 /* DCMI */
3661 /* */
3662 /******************************************************************************/
3663 /******************** Bits definition for DCMI_CR register ******************/
3664 #define DCMI_CR_CAPTURE 0x00000001U
3665 #define DCMI_CR_CM 0x00000002U
3666 #define DCMI_CR_CROP 0x00000004U
3667 #define DCMI_CR_JPEG 0x00000008U
3668 #define DCMI_CR_ESS 0x00000010U
3669 #define DCMI_CR_PCKPOL 0x00000020U
3670 #define DCMI_CR_HSPOL 0x00000040U
3671 #define DCMI_CR_VSPOL 0x00000080U
3672 #define DCMI_CR_FCRC_0 0x00000100U
3673 #define DCMI_CR_FCRC_1 0x00000200U
3674 #define DCMI_CR_EDM_0 0x00000400U
3675 #define DCMI_CR_EDM_1 0x00000800U
3676 #define DCMI_CR_CRE 0x00001000U
3677 #define DCMI_CR_ENABLE 0x00004000U
3678 #define DCMI_CR_BSM 0x00030000U
3679 #define DCMI_CR_BSM_0 0x00010000U
3680 #define DCMI_CR_BSM_1 0x00020000U
3681 #define DCMI_CR_OEBS 0x00040000U
3682 #define DCMI_CR_LSM 0x00080000U
3683 #define DCMI_CR_OELS 0x00100000U
3684 
3685 /******************** Bits definition for DCMI_SR register ******************/
3686 #define DCMI_SR_HSYNC 0x00000001U
3687 #define DCMI_SR_VSYNC 0x00000002U
3688 #define DCMI_SR_FNE 0x00000004U
3689 
3690 /******************** Bits definition for DCMI_RIS register ****************/
3691 #define DCMI_RIS_FRAME_RIS 0x00000001U
3692 #define DCMI_RIS_OVR_RIS 0x00000002U
3693 #define DCMI_RIS_ERR_RIS 0x00000004U
3694 #define DCMI_RIS_VSYNC_RIS 0x00000008U
3695 #define DCMI_RIS_LINE_RIS 0x00000010U
3696 
3697 /* Legacy defines */
3698 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
3699 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
3700 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
3701 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
3702 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
3703 
3704 /******************** Bits definition for DCMI_IER register *****************/
3705 #define DCMI_IER_FRAME_IE 0x00000001U
3706 #define DCMI_IER_OVR_IE 0x00000002U
3707 #define DCMI_IER_ERR_IE 0x00000004U
3708 #define DCMI_IER_VSYNC_IE 0x00000008U
3709 #define DCMI_IER_LINE_IE 0x00000010U
3710 
3711 
3712 /******************** Bits definition for DCMI_MIS register *****************/
3713 #define DCMI_MIS_FRAME_MIS 0x00000001U
3714 #define DCMI_MIS_OVR_MIS 0x00000002U
3715 #define DCMI_MIS_ERR_MIS 0x00000004U
3716 #define DCMI_MIS_VSYNC_MIS 0x00000008U
3717 #define DCMI_MIS_LINE_MIS 0x00000010U
3718 
3719 
3720 /******************** Bits definition for DCMI_ICR register *****************/
3721 #define DCMI_ICR_FRAME_ISC 0x00000001U
3722 #define DCMI_ICR_OVR_ISC 0x00000002U
3723 #define DCMI_ICR_ERR_ISC 0x00000004U
3724 #define DCMI_ICR_VSYNC_ISC 0x00000008U
3725 #define DCMI_ICR_LINE_ISC 0x00000010U
3726 
3727 
3728 /******************** Bits definition for DCMI_ESCR register ******************/
3729 #define DCMI_ESCR_FSC 0x000000FFU
3730 #define DCMI_ESCR_LSC 0x0000FF00U
3731 #define DCMI_ESCR_LEC 0x00FF0000U
3732 #define DCMI_ESCR_FEC 0xFF000000U
3733 
3734 /******************** Bits definition for DCMI_ESUR register ******************/
3735 #define DCMI_ESUR_FSU 0x000000FFU
3736 #define DCMI_ESUR_LSU 0x0000FF00U
3737 #define DCMI_ESUR_LEU 0x00FF0000U
3738 #define DCMI_ESUR_FEU 0xFF000000U
3739 
3740 /******************** Bits definition for DCMI_CWSTRT register ******************/
3741 #define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
3742 #define DCMI_CWSTRT_VST 0x1FFF0000U
3743 
3744 /******************** Bits definition for DCMI_CWSIZE register ******************/
3745 #define DCMI_CWSIZE_CAPCNT 0x00003FFFU
3746 #define DCMI_CWSIZE_VLINE 0x3FFF0000U
3747 
3748 /******************** Bits definition for DCMI_DR register ******************/
3749 #define DCMI_DR_BYTE0 0x000000FFU
3750 #define DCMI_DR_BYTE1 0x0000FF00U
3751 #define DCMI_DR_BYTE2 0x00FF0000U
3752 #define DCMI_DR_BYTE3 0xFF000000U
3753 
3754 /******************************************************************************/
3755 /* */
3756 /* DMA Controller */
3757 /* */
3758 /******************************************************************************/
3759 /******************** Bits definition for DMA_SxCR register *****************/
3760 #define DMA_SxCR_CHSEL 0x1E000000U
3761 #define DMA_SxCR_CHSEL_0 0x02000000U
3762 #define DMA_SxCR_CHSEL_1 0x04000000U
3763 #define DMA_SxCR_CHSEL_2 0x08000000U
3764 #define DMA_SxCR_CHSEL_3 0x10000000U
3765 #define DMA_SxCR_MBURST 0x01800000U
3766 #define DMA_SxCR_MBURST_0 0x00800000U
3767 #define DMA_SxCR_MBURST_1 0x01000000U
3768 #define DMA_SxCR_PBURST 0x00600000U
3769 #define DMA_SxCR_PBURST_0 0x00200000U
3770 #define DMA_SxCR_PBURST_1 0x00400000U
3771 #define DMA_SxCR_CT 0x00080000U
3772 #define DMA_SxCR_DBM 0x00040000U
3773 #define DMA_SxCR_PL 0x00030000U
3774 #define DMA_SxCR_PL_0 0x00010000U
3775 #define DMA_SxCR_PL_1 0x00020000U
3776 #define DMA_SxCR_PINCOS 0x00008000U
3777 #define DMA_SxCR_MSIZE 0x00006000U
3778 #define DMA_SxCR_MSIZE_0 0x00002000U
3779 #define DMA_SxCR_MSIZE_1 0x00004000U
3780 #define DMA_SxCR_PSIZE 0x00001800U
3781 #define DMA_SxCR_PSIZE_0 0x00000800U
3782 #define DMA_SxCR_PSIZE_1 0x00001000U
3783 #define DMA_SxCR_MINC 0x00000400U
3784 #define DMA_SxCR_PINC 0x00000200U
3785 #define DMA_SxCR_CIRC 0x00000100U
3786 #define DMA_SxCR_DIR 0x000000C0U
3787 #define DMA_SxCR_DIR_0 0x00000040U
3788 #define DMA_SxCR_DIR_1 0x00000080U
3789 #define DMA_SxCR_PFCTRL 0x00000020U
3790 #define DMA_SxCR_TCIE 0x00000010U
3791 #define DMA_SxCR_HTIE 0x00000008U
3792 #define DMA_SxCR_TEIE 0x00000004U
3793 #define DMA_SxCR_DMEIE 0x00000002U
3794 #define DMA_SxCR_EN 0x00000001U
3795 
3796 /******************** Bits definition for DMA_SxCNDTR register **************/
3797 #define DMA_SxNDT 0x0000FFFFU
3798 #define DMA_SxNDT_0 0x00000001U
3799 #define DMA_SxNDT_1 0x00000002U
3800 #define DMA_SxNDT_2 0x00000004U
3801 #define DMA_SxNDT_3 0x00000008U
3802 #define DMA_SxNDT_4 0x00000010U
3803 #define DMA_SxNDT_5 0x00000020U
3804 #define DMA_SxNDT_6 0x00000040U
3805 #define DMA_SxNDT_7 0x00000080U
3806 #define DMA_SxNDT_8 0x00000100U
3807 #define DMA_SxNDT_9 0x00000200U
3808 #define DMA_SxNDT_10 0x00000400U
3809 #define DMA_SxNDT_11 0x00000800U
3810 #define DMA_SxNDT_12 0x00001000U
3811 #define DMA_SxNDT_13 0x00002000U
3812 #define DMA_SxNDT_14 0x00004000U
3813 #define DMA_SxNDT_15 0x00008000U
3814 
3815 /******************** Bits definition for DMA_SxFCR register ****************/
3816 #define DMA_SxFCR_FEIE 0x00000080U
3817 #define DMA_SxFCR_FS 0x00000038U
3818 #define DMA_SxFCR_FS_0 0x00000008U
3819 #define DMA_SxFCR_FS_1 0x00000010U
3820 #define DMA_SxFCR_FS_2 0x00000020U
3821 #define DMA_SxFCR_DMDIS 0x00000004U
3822 #define DMA_SxFCR_FTH 0x00000003U
3823 #define DMA_SxFCR_FTH_0 0x00000001U
3824 #define DMA_SxFCR_FTH_1 0x00000002U
3825 
3826 /******************** Bits definition for DMA_LISR register *****************/
3827 #define DMA_LISR_TCIF3 0x08000000U
3828 #define DMA_LISR_HTIF3 0x04000000U
3829 #define DMA_LISR_TEIF3 0x02000000U
3830 #define DMA_LISR_DMEIF3 0x01000000U
3831 #define DMA_LISR_FEIF3 0x00400000U
3832 #define DMA_LISR_TCIF2 0x00200000U
3833 #define DMA_LISR_HTIF2 0x00100000U
3834 #define DMA_LISR_TEIF2 0x00080000U
3835 #define DMA_LISR_DMEIF2 0x00040000U
3836 #define DMA_LISR_FEIF2 0x00010000U
3837 #define DMA_LISR_TCIF1 0x00000800U
3838 #define DMA_LISR_HTIF1 0x00000400U
3839 #define DMA_LISR_TEIF1 0x00000200U
3840 #define DMA_LISR_DMEIF1 0x00000100U
3841 #define DMA_LISR_FEIF1 0x00000040U
3842 #define DMA_LISR_TCIF0 0x00000020U
3843 #define DMA_LISR_HTIF0 0x00000010U
3844 #define DMA_LISR_TEIF0 0x00000008U
3845 #define DMA_LISR_DMEIF0 0x00000004U
3846 #define DMA_LISR_FEIF0 0x00000001U
3847 
3848 /******************** Bits definition for DMA_HISR register *****************/
3849 #define DMA_HISR_TCIF7 0x08000000U
3850 #define DMA_HISR_HTIF7 0x04000000U
3851 #define DMA_HISR_TEIF7 0x02000000U
3852 #define DMA_HISR_DMEIF7 0x01000000U
3853 #define DMA_HISR_FEIF7 0x00400000U
3854 #define DMA_HISR_TCIF6 0x00200000U
3855 #define DMA_HISR_HTIF6 0x00100000U
3856 #define DMA_HISR_TEIF6 0x00080000U
3857 #define DMA_HISR_DMEIF6 0x00040000U
3858 #define DMA_HISR_FEIF6 0x00010000U
3859 #define DMA_HISR_TCIF5 0x00000800U
3860 #define DMA_HISR_HTIF5 0x00000400U
3861 #define DMA_HISR_TEIF5 0x00000200U
3862 #define DMA_HISR_DMEIF5 0x00000100U
3863 #define DMA_HISR_FEIF5 0x00000040U
3864 #define DMA_HISR_TCIF4 0x00000020U
3865 #define DMA_HISR_HTIF4 0x00000010U
3866 #define DMA_HISR_TEIF4 0x00000008U
3867 #define DMA_HISR_DMEIF4 0x00000004U
3868 #define DMA_HISR_FEIF4 0x00000001U
3869 
3870 /******************** Bits definition for DMA_LIFCR register ****************/
3871 #define DMA_LIFCR_CTCIF3 0x08000000U
3872 #define DMA_LIFCR_CHTIF3 0x04000000U
3873 #define DMA_LIFCR_CTEIF3 0x02000000U
3874 #define DMA_LIFCR_CDMEIF3 0x01000000U
3875 #define DMA_LIFCR_CFEIF3 0x00400000U
3876 #define DMA_LIFCR_CTCIF2 0x00200000U
3877 #define DMA_LIFCR_CHTIF2 0x00100000U
3878 #define DMA_LIFCR_CTEIF2 0x00080000U
3879 #define DMA_LIFCR_CDMEIF2 0x00040000U
3880 #define DMA_LIFCR_CFEIF2 0x00010000U
3881 #define DMA_LIFCR_CTCIF1 0x00000800U
3882 #define DMA_LIFCR_CHTIF1 0x00000400U
3883 #define DMA_LIFCR_CTEIF1 0x00000200U
3884 #define DMA_LIFCR_CDMEIF1 0x00000100U
3885 #define DMA_LIFCR_CFEIF1 0x00000040U
3886 #define DMA_LIFCR_CTCIF0 0x00000020U
3887 #define DMA_LIFCR_CHTIF0 0x00000010U
3888 #define DMA_LIFCR_CTEIF0 0x00000008U
3889 #define DMA_LIFCR_CDMEIF0 0x00000004U
3890 #define DMA_LIFCR_CFEIF0 0x00000001U
3891 
3892 /******************** Bits definition for DMA_HIFCR register ****************/
3893 #define DMA_HIFCR_CTCIF7 0x08000000U
3894 #define DMA_HIFCR_CHTIF7 0x04000000U
3895 #define DMA_HIFCR_CTEIF7 0x02000000U
3896 #define DMA_HIFCR_CDMEIF7 0x01000000U
3897 #define DMA_HIFCR_CFEIF7 0x00400000U
3898 #define DMA_HIFCR_CTCIF6 0x00200000U
3899 #define DMA_HIFCR_CHTIF6 0x00100000U
3900 #define DMA_HIFCR_CTEIF6 0x00080000U
3901 #define DMA_HIFCR_CDMEIF6 0x00040000U
3902 #define DMA_HIFCR_CFEIF6 0x00010000U
3903 #define DMA_HIFCR_CTCIF5 0x00000800U
3904 #define DMA_HIFCR_CHTIF5 0x00000400U
3905 #define DMA_HIFCR_CTEIF5 0x00000200U
3906 #define DMA_HIFCR_CDMEIF5 0x00000100U
3907 #define DMA_HIFCR_CFEIF5 0x00000040U
3908 #define DMA_HIFCR_CTCIF4 0x00000020U
3909 #define DMA_HIFCR_CHTIF4 0x00000010U
3910 #define DMA_HIFCR_CTEIF4 0x00000008U
3911 #define DMA_HIFCR_CDMEIF4 0x00000004U
3912 #define DMA_HIFCR_CFEIF4 0x00000001U
3913 
3914 /******************************************************************************/
3915 /* */
3916 /* AHB Master DMA2D Controller (DMA2D) */
3917 /* */
3918 /******************************************************************************/
3919 
3920 /******************** Bit definition for DMA2D_CR register ******************/
3921 
3922 #define DMA2D_CR_START 0x00000001U
3923 #define DMA2D_CR_SUSP 0x00000002U
3924 #define DMA2D_CR_ABORT 0x00000004U
3925 #define DMA2D_CR_TEIE 0x00000100U
3926 #define DMA2D_CR_TCIE 0x00000200U
3927 #define DMA2D_CR_TWIE 0x00000400U
3928 #define DMA2D_CR_CAEIE 0x00000800U
3929 #define DMA2D_CR_CTCIE 0x00001000U
3930 #define DMA2D_CR_CEIE 0x00002000U
3931 #define DMA2D_CR_MODE 0x00030000U
3932 #define DMA2D_CR_MODE_0 0x00010000U
3933 #define DMA2D_CR_MODE_1 0x00020000U
3935 /******************** Bit definition for DMA2D_ISR register *****************/
3936 
3937 #define DMA2D_ISR_TEIF 0x00000001U
3938 #define DMA2D_ISR_TCIF 0x00000002U
3939 #define DMA2D_ISR_TWIF 0x00000004U
3940 #define DMA2D_ISR_CAEIF 0x00000008U
3941 #define DMA2D_ISR_CTCIF 0x00000010U
3942 #define DMA2D_ISR_CEIF 0x00000020U
3944 /******************** Bit definition for DMA2D_IFCR register ****************/
3945 
3946 #define DMA2D_IFCR_CTEIF 0x00000001U
3947 #define DMA2D_IFCR_CTCIF 0x00000002U
3948 #define DMA2D_IFCR_CTWIF 0x00000004U
3949 #define DMA2D_IFCR_CAECIF 0x00000008U
3950 #define DMA2D_IFCR_CCTCIF 0x00000010U
3951 #define DMA2D_IFCR_CCEIF 0x00000020U
3953 /* Legacy defines */
3954 #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF
3955 #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF
3956 #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF
3957 #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF
3958 #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF
3959 #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF
3961 /******************** Bit definition for DMA2D_FGMAR register ***************/
3962 
3963 #define DMA2D_FGMAR_MA 0xFFFFFFFFU
3965 /******************** Bit definition for DMA2D_FGOR register ****************/
3966 
3967 #define DMA2D_FGOR_LO 0x00003FFFU
3969 /******************** Bit definition for DMA2D_BGMAR register ***************/
3970 
3971 #define DMA2D_BGMAR_MA 0xFFFFFFFFU
3973 /******************** Bit definition for DMA2D_BGOR register ****************/
3974 
3975 #define DMA2D_BGOR_LO 0x00003FFFU
3977 /******************** Bit definition for DMA2D_FGPFCCR register *************/
3978 
3979 #define DMA2D_FGPFCCR_CM 0x0000000FU
3980 #define DMA2D_FGPFCCR_CM_0 0x00000001U
3981 #define DMA2D_FGPFCCR_CM_1 0x00000002U
3982 #define DMA2D_FGPFCCR_CM_2 0x00000004U
3983 #define DMA2D_FGPFCCR_CM_3 0x00000008U
3984 #define DMA2D_FGPFCCR_CCM 0x00000010U
3985 #define DMA2D_FGPFCCR_START 0x00000020U
3986 #define DMA2D_FGPFCCR_CS 0x0000FF00U
3987 #define DMA2D_FGPFCCR_AM 0x00030000U
3988 #define DMA2D_FGPFCCR_AM_0 0x00010000U
3989 #define DMA2D_FGPFCCR_AM_1 0x00020000U
3990 #define DMA2D_FGPFCCR_AI 0x00100000U
3991 #define DMA2D_FGPFCCR_RBS 0x00200000U
3992 #define DMA2D_FGPFCCR_ALPHA 0xFF000000U
3994 /******************** Bit definition for DMA2D_FGCOLR register **************/
3995 
3996 #define DMA2D_FGCOLR_BLUE 0x000000FFU
3997 #define DMA2D_FGCOLR_GREEN 0x0000FF00U
3998 #define DMA2D_FGCOLR_RED 0x00FF0000U
4000 /******************** Bit definition for DMA2D_BGPFCCR register *************/
4001 
4002 #define DMA2D_BGPFCCR_CM 0x0000000FU
4003 #define DMA2D_BGPFCCR_CM_0 0x00000001U
4004 #define DMA2D_BGPFCCR_CM_1 0x00000002U
4005 #define DMA2D_BGPFCCR_CM_2 0x00000004U
4006 #define DMA2D_FGPFCCR_CM_3 0x00000008U
4007 #define DMA2D_BGPFCCR_CCM 0x00000010U
4008 #define DMA2D_BGPFCCR_START 0x00000020U
4009 #define DMA2D_BGPFCCR_CS 0x0000FF00U
4010 #define DMA2D_BGPFCCR_AM 0x00030000U
4011 #define DMA2D_BGPFCCR_AM_0 0x00010000U
4012 #define DMA2D_BGPFCCR_AM_1 0x00020000U
4013 #define DMA2D_BGPFCCR_AI 0x00100000U
4014 #define DMA2D_BGPFCCR_RBS 0x00200000U
4015 #define DMA2D_BGPFCCR_ALPHA 0xFF000000U
4017 /******************** Bit definition for DMA2D_BGCOLR register **************/
4018 
4019 #define DMA2D_BGCOLR_BLUE 0x000000FFU
4020 #define DMA2D_BGCOLR_GREEN 0x0000FF00U
4021 #define DMA2D_BGCOLR_RED 0x00FF0000U
4023 /******************** Bit definition for DMA2D_FGCMAR register **************/
4024 
4025 #define DMA2D_FGCMAR_MA 0xFFFFFFFFU
4027 /******************** Bit definition for DMA2D_BGCMAR register **************/
4028 
4029 #define DMA2D_BGCMAR_MA 0xFFFFFFFFU
4031 /******************** Bit definition for DMA2D_OPFCCR register **************/
4032 
4033 #define DMA2D_OPFCCR_CM 0x00000007U
4034 #define DMA2D_OPFCCR_CM_0 0x00000001U
4035 #define DMA2D_OPFCCR_CM_1 0x00000002U
4036 #define DMA2D_OPFCCR_CM_2 0x00000004U
4037 #define DMA2D_OPFCCR_AI 0x00100000U
4038 #define DMA2D_OPFCCR_RBS 0x00200000U
4040 /******************** Bit definition for DMA2D_OCOLR register ***************/
4041 
4044 #define DMA2D_OCOLR_BLUE_1 0x000000FFU
4045 #define DMA2D_OCOLR_GREEN_1 0x0000FF00U
4046 #define DMA2D_OCOLR_RED_1 0x00FF0000U
4047 #define DMA2D_OCOLR_ALPHA_1 0xFF000000U
4050 #define DMA2D_OCOLR_BLUE_2 0x0000001FU
4051 #define DMA2D_OCOLR_GREEN_2 0x000007E0U
4052 #define DMA2D_OCOLR_RED_2 0x0000F800U
4055 #define DMA2D_OCOLR_BLUE_3 0x0000001FU
4056 #define DMA2D_OCOLR_GREEN_3 0x000003E0U
4057 #define DMA2D_OCOLR_RED_3 0x00007C00U
4058 #define DMA2D_OCOLR_ALPHA_3 0x00008000U
4061 #define DMA2D_OCOLR_BLUE_4 0x0000000FU
4062 #define DMA2D_OCOLR_GREEN_4 0x000000F0U
4063 #define DMA2D_OCOLR_RED_4 0x00000F00U
4064 #define DMA2D_OCOLR_ALPHA_4 0x0000F000U
4066 /******************** Bit definition for DMA2D_OMAR register ****************/
4067 
4068 #define DMA2D_OMAR_MA 0xFFFFFFFFU
4070 /******************** Bit definition for DMA2D_OOR register *****************/
4071 
4072 #define DMA2D_OOR_LO 0x00003FFFU
4074 /******************** Bit definition for DMA2D_NLR register *****************/
4075 
4076 #define DMA2D_NLR_NL 0x0000FFFFU
4077 #define DMA2D_NLR_PL 0x3FFF0000U
4079 /******************** Bit definition for DMA2D_LWR register *****************/
4080 
4081 #define DMA2D_LWR_LW 0x0000FFFFU
4083 /******************** Bit definition for DMA2D_AMTCR register ***************/
4084 
4085 #define DMA2D_AMTCR_EN 0x00000001U
4086 #define DMA2D_AMTCR_DT 0x0000FF00U
4089 /******************** Bit definition for DMA2D_FGCLUT register **************/
4090 
4091 /******************** Bit definition for DMA2D_BGCLUT register **************/
4092 
4093 
4094 /******************************************************************************/
4095 /* */
4096 /* External Interrupt/Event Controller */
4097 /* */
4098 /******************************************************************************/
4099 /******************* Bit definition for EXTI_IMR register *******************/
4100 #define EXTI_IMR_MR0 0x00000001U
4101 #define EXTI_IMR_MR1 0x00000002U
4102 #define EXTI_IMR_MR2 0x00000004U
4103 #define EXTI_IMR_MR3 0x00000008U
4104 #define EXTI_IMR_MR4 0x00000010U
4105 #define EXTI_IMR_MR5 0x00000020U
4106 #define EXTI_IMR_MR6 0x00000040U
4107 #define EXTI_IMR_MR7 0x00000080U
4108 #define EXTI_IMR_MR8 0x00000100U
4109 #define EXTI_IMR_MR9 0x00000200U
4110 #define EXTI_IMR_MR10 0x00000400U
4111 #define EXTI_IMR_MR11 0x00000800U
4112 #define EXTI_IMR_MR12 0x00001000U
4113 #define EXTI_IMR_MR13 0x00002000U
4114 #define EXTI_IMR_MR14 0x00004000U
4115 #define EXTI_IMR_MR15 0x00008000U
4116 #define EXTI_IMR_MR16 0x00010000U
4117 #define EXTI_IMR_MR17 0x00020000U
4118 #define EXTI_IMR_MR18 0x00040000U
4119 #define EXTI_IMR_MR19 0x00080000U
4120 #define EXTI_IMR_MR20 0x00100000U
4121 #define EXTI_IMR_MR21 0x00200000U
4122 #define EXTI_IMR_MR22 0x00400000U
4123 #define EXTI_IMR_MR23 0x00800000U
4124 #define EXTI_IMR_MR24 0x01000000U
4126 /* Reference Defines */
4127 #define EXTI_IMR_IM0 EXTI_IMR_MR0
4128 #define EXTI_IMR_IM1 EXTI_IMR_MR1
4129 #define EXTI_IMR_IM2 EXTI_IMR_MR2
4130 #define EXTI_IMR_IM3 EXTI_IMR_MR3
4131 #define EXTI_IMR_IM4 EXTI_IMR_MR4
4132 #define EXTI_IMR_IM5 EXTI_IMR_MR5
4133 #define EXTI_IMR_IM6 EXTI_IMR_MR6
4134 #define EXTI_IMR_IM7 EXTI_IMR_MR7
4135 #define EXTI_IMR_IM8 EXTI_IMR_MR8
4136 #define EXTI_IMR_IM9 EXTI_IMR_MR9
4137 #define EXTI_IMR_IM10 EXTI_IMR_MR10
4138 #define EXTI_IMR_IM11 EXTI_IMR_MR11
4139 #define EXTI_IMR_IM12 EXTI_IMR_MR12
4140 #define EXTI_IMR_IM13 EXTI_IMR_MR13
4141 #define EXTI_IMR_IM14 EXTI_IMR_MR14
4142 #define EXTI_IMR_IM15 EXTI_IMR_MR15
4143 #define EXTI_IMR_IM16 EXTI_IMR_MR16
4144 #define EXTI_IMR_IM17 EXTI_IMR_MR17
4145 #define EXTI_IMR_IM18 EXTI_IMR_MR18
4146 #define EXTI_IMR_IM19 EXTI_IMR_MR19
4147 #define EXTI_IMR_IM20 EXTI_IMR_MR20
4148 #define EXTI_IMR_IM21 EXTI_IMR_MR21
4149 #define EXTI_IMR_IM22 EXTI_IMR_MR22
4150 #define EXTI_IMR_IM23 EXTI_IMR_MR23
4151 #define EXTI_IMR_IM24 EXTI_IMR_MR24
4152 
4153 #define EXTI_IMR_IM 0x01FFFFFFU
4155 /******************* Bit definition for EXTI_EMR register *******************/
4156 #define EXTI_EMR_MR0 0x00000001U
4157 #define EXTI_EMR_MR1 0x00000002U
4158 #define EXTI_EMR_MR2 0x00000004U
4159 #define EXTI_EMR_MR3 0x00000008U
4160 #define EXTI_EMR_MR4 0x00000010U
4161 #define EXTI_EMR_MR5 0x00000020U
4162 #define EXTI_EMR_MR6 0x00000040U
4163 #define EXTI_EMR_MR7 0x00000080U
4164 #define EXTI_EMR_MR8 0x00000100U
4165 #define EXTI_EMR_MR9 0x00000200U
4166 #define EXTI_EMR_MR10 0x00000400U
4167 #define EXTI_EMR_MR11 0x00000800U
4168 #define EXTI_EMR_MR12 0x00001000U
4169 #define EXTI_EMR_MR13 0x00002000U
4170 #define EXTI_EMR_MR14 0x00004000U
4171 #define EXTI_EMR_MR15 0x00008000U
4172 #define EXTI_EMR_MR16 0x00010000U
4173 #define EXTI_EMR_MR17 0x00020000U
4174 #define EXTI_EMR_MR18 0x00040000U
4175 #define EXTI_EMR_MR19 0x00080000U
4176 #define EXTI_EMR_MR20 0x00100000U
4177 #define EXTI_EMR_MR21 0x00200000U
4178 #define EXTI_EMR_MR22 0x00400000U
4179 #define EXTI_EMR_MR23 0x00800000U
4180 #define EXTI_EMR_MR24 0x01000000U
4182 /* Reference Defines */
4183 #define EXTI_EMR_EM0 EXTI_EMR_MR0
4184 #define EXTI_EMR_EM1 EXTI_EMR_MR1
4185 #define EXTI_EMR_EM2 EXTI_EMR_MR2
4186 #define EXTI_EMR_EM3 EXTI_EMR_MR3
4187 #define EXTI_EMR_EM4 EXTI_EMR_MR4
4188 #define EXTI_EMR_EM5 EXTI_EMR_MR5
4189 #define EXTI_EMR_EM6 EXTI_EMR_MR6
4190 #define EXTI_EMR_EM7 EXTI_EMR_MR7
4191 #define EXTI_EMR_EM8 EXTI_EMR_MR8
4192 #define EXTI_EMR_EM9 EXTI_EMR_MR9
4193 #define EXTI_EMR_EM10 EXTI_EMR_MR10
4194 #define EXTI_EMR_EM11 EXTI_EMR_MR11
4195 #define EXTI_EMR_EM12 EXTI_EMR_MR12
4196 #define EXTI_EMR_EM13 EXTI_EMR_MR13
4197 #define EXTI_EMR_EM14 EXTI_EMR_MR14
4198 #define EXTI_EMR_EM15 EXTI_EMR_MR15
4199 #define EXTI_EMR_EM16 EXTI_EMR_MR16
4200 #define EXTI_EMR_EM17 EXTI_EMR_MR17
4201 #define EXTI_EMR_EM18 EXTI_EMR_MR18
4202 #define EXTI_EMR_EM19 EXTI_EMR_MR19
4203 #define EXTI_EMR_EM20 EXTI_EMR_MR20
4204 #define EXTI_EMR_EM21 EXTI_EMR_MR21
4205 #define EXTI_EMR_EM22 EXTI_EMR_MR22
4206 #define EXTI_EMR_EM23 EXTI_EMR_MR23
4207 #define EXTI_EMR_EM24 EXTI_EMR_MR24
4208 
4209 
4210 /****************** Bit definition for EXTI_RTSR register *******************/
4211 #define EXTI_RTSR_TR0 0x00000001U
4212 #define EXTI_RTSR_TR1 0x00000002U
4213 #define EXTI_RTSR_TR2 0x00000004U
4214 #define EXTI_RTSR_TR3 0x00000008U
4215 #define EXTI_RTSR_TR4 0x00000010U
4216 #define EXTI_RTSR_TR5 0x00000020U
4217 #define EXTI_RTSR_TR6 0x00000040U
4218 #define EXTI_RTSR_TR7 0x00000080U
4219 #define EXTI_RTSR_TR8 0x00000100U
4220 #define EXTI_RTSR_TR9 0x00000200U
4221 #define EXTI_RTSR_TR10 0x00000400U
4222 #define EXTI_RTSR_TR11 0x00000800U
4223 #define EXTI_RTSR_TR12 0x00001000U
4224 #define EXTI_RTSR_TR13 0x00002000U
4225 #define EXTI_RTSR_TR14 0x00004000U
4226 #define EXTI_RTSR_TR15 0x00008000U
4227 #define EXTI_RTSR_TR16 0x00010000U
4228 #define EXTI_RTSR_TR17 0x00020000U
4229 #define EXTI_RTSR_TR18 0x00040000U
4230 #define EXTI_RTSR_TR19 0x00080000U
4231 #define EXTI_RTSR_TR20 0x00100000U
4232 #define EXTI_RTSR_TR21 0x00200000U
4233 #define EXTI_RTSR_TR22 0x00400000U
4234 #define EXTI_RTSR_TR23 0x00800000U
4235 #define EXTI_RTSR_TR24 0x01000000U
4237 /****************** Bit definition for EXTI_FTSR register *******************/
4238 #define EXTI_FTSR_TR0 0x00000001U
4239 #define EXTI_FTSR_TR1 0x00000002U
4240 #define EXTI_FTSR_TR2 0x00000004U
4241 #define EXTI_FTSR_TR3 0x00000008U
4242 #define EXTI_FTSR_TR4 0x00000010U
4243 #define EXTI_FTSR_TR5 0x00000020U
4244 #define EXTI_FTSR_TR6 0x00000040U
4245 #define EXTI_FTSR_TR7 0x00000080U
4246 #define EXTI_FTSR_TR8 0x00000100U
4247 #define EXTI_FTSR_TR9 0x00000200U
4248 #define EXTI_FTSR_TR10 0x00000400U
4249 #define EXTI_FTSR_TR11 0x00000800U
4250 #define EXTI_FTSR_TR12 0x00001000U
4251 #define EXTI_FTSR_TR13 0x00002000U
4252 #define EXTI_FTSR_TR14 0x00004000U
4253 #define EXTI_FTSR_TR15 0x00008000U
4254 #define EXTI_FTSR_TR16 0x00010000U
4255 #define EXTI_FTSR_TR17 0x00020000U
4256 #define EXTI_FTSR_TR18 0x00040000U
4257 #define EXTI_FTSR_TR19 0x00080000U
4258 #define EXTI_FTSR_TR20 0x00100000U
4259 #define EXTI_FTSR_TR21 0x00200000U
4260 #define EXTI_FTSR_TR22 0x00400000U
4261 #define EXTI_FTSR_TR23 0x00800000U
4262 #define EXTI_FTSR_TR24 0x01000000U
4264 /****************** Bit definition for EXTI_SWIER register ******************/
4265 #define EXTI_SWIER_SWIER0 0x00000001U
4266 #define EXTI_SWIER_SWIER1 0x00000002U
4267 #define EXTI_SWIER_SWIER2 0x00000004U
4268 #define EXTI_SWIER_SWIER3 0x00000008U
4269 #define EXTI_SWIER_SWIER4 0x00000010U
4270 #define EXTI_SWIER_SWIER5 0x00000020U
4271 #define EXTI_SWIER_SWIER6 0x00000040U
4272 #define EXTI_SWIER_SWIER7 0x00000080U
4273 #define EXTI_SWIER_SWIER8 0x00000100U
4274 #define EXTI_SWIER_SWIER9 0x00000200U
4275 #define EXTI_SWIER_SWIER10 0x00000400U
4276 #define EXTI_SWIER_SWIER11 0x00000800U
4277 #define EXTI_SWIER_SWIER12 0x00001000U
4278 #define EXTI_SWIER_SWIER13 0x00002000U
4279 #define EXTI_SWIER_SWIER14 0x00004000U
4280 #define EXTI_SWIER_SWIER15 0x00008000U
4281 #define EXTI_SWIER_SWIER16 0x00010000U
4282 #define EXTI_SWIER_SWIER17 0x00020000U
4283 #define EXTI_SWIER_SWIER18 0x00040000U
4284 #define EXTI_SWIER_SWIER19 0x00080000U
4285 #define EXTI_SWIER_SWIER20 0x00100000U
4286 #define EXTI_SWIER_SWIER21 0x00200000U
4287 #define EXTI_SWIER_SWIER22 0x00400000U
4288 #define EXTI_SWIER_SWIER23 0x00800000U
4289 #define EXTI_SWIER_SWIER24 0x01000000U
4291 /******************* Bit definition for EXTI_PR register ********************/
4292 #define EXTI_PR_PR0 0x00000001U
4293 #define EXTI_PR_PR1 0x00000002U
4294 #define EXTI_PR_PR2 0x00000004U
4295 #define EXTI_PR_PR3 0x00000008U
4296 #define EXTI_PR_PR4 0x00000010U
4297 #define EXTI_PR_PR5 0x00000020U
4298 #define EXTI_PR_PR6 0x00000040U
4299 #define EXTI_PR_PR7 0x00000080U
4300 #define EXTI_PR_PR8 0x00000100U
4301 #define EXTI_PR_PR9 0x00000200U
4302 #define EXTI_PR_PR10 0x00000400U
4303 #define EXTI_PR_PR11 0x00000800U
4304 #define EXTI_PR_PR12 0x00001000U
4305 #define EXTI_PR_PR13 0x00002000U
4306 #define EXTI_PR_PR14 0x00004000U
4307 #define EXTI_PR_PR15 0x00008000U
4308 #define EXTI_PR_PR16 0x00010000U
4309 #define EXTI_PR_PR17 0x00020000U
4310 #define EXTI_PR_PR18 0x00040000U
4311 #define EXTI_PR_PR19 0x00080000U
4312 #define EXTI_PR_PR20 0x00100000U
4313 #define EXTI_PR_PR21 0x00200000U
4314 #define EXTI_PR_PR22 0x00400000U
4315 #define EXTI_PR_PR23 0x00800000U
4316 #define EXTI_PR_PR24 0x01000000U
4318 /******************************************************************************/
4319 /* */
4320 /* FLASH */
4321 /* */
4322 /******************************************************************************/
4323 /*
4324 * @brief FLASH Total Sectors Number
4325 */
4326 #define FLASH_SECTOR_TOTAL 24
4327 
4328 /******************* Bits definition for FLASH_ACR register *****************/
4329 #define FLASH_ACR_LATENCY 0x0000000FU
4330 #define FLASH_ACR_LATENCY_0WS 0x00000000U
4331 #define FLASH_ACR_LATENCY_1WS 0x00000001U
4332 #define FLASH_ACR_LATENCY_2WS 0x00000002U
4333 #define FLASH_ACR_LATENCY_3WS 0x00000003U
4334 #define FLASH_ACR_LATENCY_4WS 0x00000004U
4335 #define FLASH_ACR_LATENCY_5WS 0x00000005U
4336 #define FLASH_ACR_LATENCY_6WS 0x00000006U
4337 #define FLASH_ACR_LATENCY_7WS 0x00000007U
4338 #define FLASH_ACR_LATENCY_8WS 0x00000008U
4339 #define FLASH_ACR_LATENCY_9WS 0x00000009U
4340 #define FLASH_ACR_LATENCY_10WS 0x0000000AU
4341 #define FLASH_ACR_LATENCY_11WS 0x0000000BU
4342 #define FLASH_ACR_LATENCY_12WS 0x0000000CU
4343 #define FLASH_ACR_LATENCY_13WS 0x0000000DU
4344 #define FLASH_ACR_LATENCY_14WS 0x0000000EU
4345 #define FLASH_ACR_LATENCY_15WS 0x0000000FU
4346 #define FLASH_ACR_PRFTEN 0x00000100U
4347 #define FLASH_ACR_ARTEN 0x00000200U
4348 #define FLASH_ACR_ARTRST 0x00000800U
4349 
4350 /******************* Bits definition for FLASH_SR register ******************/
4351 #define FLASH_SR_EOP 0x00000001U
4352 #define FLASH_SR_OPERR 0x00000002U
4353 #define FLASH_SR_WRPERR 0x00000010U
4354 #define FLASH_SR_PGAERR 0x00000020U
4355 #define FLASH_SR_PGPERR 0x00000040U
4356 #define FLASH_SR_ERSERR 0x00000080U
4357 #define FLASH_SR_BSY 0x00010000U
4358 
4359 /******************* Bits definition for FLASH_CR register ******************/
4360 #define FLASH_CR_PG 0x00000001U
4361 #define FLASH_CR_SER 0x00000002U
4362 #define FLASH_CR_MER 0x00000004U
4363 #define FLASH_CR_MER1 FLASH_CR_MER
4364 #define FLASH_CR_SNB 0x000000F8U
4365 #define FLASH_CR_SNB_0 0x00000008U
4366 #define FLASH_CR_SNB_1 0x00000010U
4367 #define FLASH_CR_SNB_2 0x00000020U
4368 #define FLASH_CR_SNB_3 0x00000040U
4369 #define FLASH_CR_SNB_4 0x00000080U
4370 #define FLASH_CR_PSIZE 0x00000300U
4371 #define FLASH_CR_PSIZE_0 0x00000100U
4372 #define FLASH_CR_PSIZE_1 0x00000200U
4373 #define FLASH_CR_MER2 0x00008000U
4374 #define FLASH_CR_STRT 0x00010000U
4375 #define FLASH_CR_EOPIE 0x01000000U
4376 #define FLASH_CR_ERRIE 0x02000000U
4377 #define FLASH_CR_LOCK 0x80000000U
4378 
4379 /******************* Bits definition for FLASH_OPTCR register ***************/
4380 #define FLASH_OPTCR_OPTLOCK 0x00000001U
4381 #define FLASH_OPTCR_OPTSTRT 0x00000002U
4382 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
4383 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
4384 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
4385 #define FLASH_OPTCR_WWDG_SW 0x00000010U
4386 #define FLASH_OPTCR_IWDG_SW 0x00000020U
4387 #define FLASH_OPTCR_nRST_STOP 0x00000040U
4388 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
4389 #define FLASH_OPTCR_RDP 0x0000FF00U
4390 #define FLASH_OPTCR_RDP_0 0x00000100U
4391 #define FLASH_OPTCR_RDP_1 0x00000200U
4392 #define FLASH_OPTCR_RDP_2 0x00000400U
4393 #define FLASH_OPTCR_RDP_3 0x00000800U
4394 #define FLASH_OPTCR_RDP_4 0x00001000U
4395 #define FLASH_OPTCR_RDP_5 0x00002000U
4396 #define FLASH_OPTCR_RDP_6 0x00004000U
4397 #define FLASH_OPTCR_RDP_7 0x00008000U
4398 #define FLASH_OPTCR_nWRP 0x0FFF0000U
4399 #define FLASH_OPTCR_nWRP_0 0x00010000U
4400 #define FLASH_OPTCR_nWRP_1 0x00020000U
4401 #define FLASH_OPTCR_nWRP_2 0x00040000U
4402 #define FLASH_OPTCR_nWRP_3 0x00080000U
4403 #define FLASH_OPTCR_nWRP_4 0x00100000U
4404 #define FLASH_OPTCR_nWRP_5 0x00200000U
4405 #define FLASH_OPTCR_nWRP_6 0x00400000U
4406 #define FLASH_OPTCR_nWRP_7 0x00800000U
4407 #define FLASH_OPTCR_nWRP_8 0x01000000U
4408 #define FLASH_OPTCR_nWRP_9 0x02000000U
4409 #define FLASH_OPTCR_nWRP_10 0x04000000U
4410 #define FLASH_OPTCR_nWRP_11 0x08000000U
4411 #define FLASH_OPTCR_nDBOOT 0x10000000U
4412 #define FLASH_OPTCR_nDBANK 0x20000000U
4413 #define FLASH_OPTCR_IWDG_STDBY 0x40000000U
4414 #define FLASH_OPTCR_IWDG_STOP 0x80000000U
4415 
4416 /******************* Bits definition for FLASH_OPTCR1 register ***************/
4417 #define FLASH_OPTCR1_BOOT_ADD0 0x0000FFFFU
4418 #define FLASH_OPTCR1_BOOT_ADD1 0xFFFF0000U
4419 
4420 /******************************************************************************/
4421 /* */
4422 /* Flexible Memory Controller */
4423 /* */
4424 /******************************************************************************/
4425 /****************** Bit definition for FMC_BCR1 register *******************/
4426 #define FMC_BCR1_MBKEN 0x00000001U
4427 #define FMC_BCR1_MUXEN 0x00000002U
4428 #define FMC_BCR1_MTYP 0x0000000CU
4429 #define FMC_BCR1_MTYP_0 0x00000004U
4430 #define FMC_BCR1_MTYP_1 0x00000008U
4431 #define FMC_BCR1_MWID 0x00000030U
4432 #define FMC_BCR1_MWID_0 0x00000010U
4433 #define FMC_BCR1_MWID_1 0x00000020U
4434 #define FMC_BCR1_FACCEN 0x00000040U
4435 #define FMC_BCR1_BURSTEN 0x00000100U
4436 #define FMC_BCR1_WAITPOL 0x00000200U
4437 #define FMC_BCR1_WRAPMOD 0x00000400U
4438 #define FMC_BCR1_WAITCFG 0x00000800U
4439 #define FMC_BCR1_WREN 0x00001000U
4440 #define FMC_BCR1_WAITEN 0x00002000U
4441 #define FMC_BCR1_EXTMOD 0x00004000U
4442 #define FMC_BCR1_ASYNCWAIT 0x00008000U
4443 #define FMC_BCR1_CPSIZE 0x00070000U
4444 #define FMC_BCR1_CPSIZE_0 0x00010000U
4445 #define FMC_BCR1_CPSIZE_1 0x00020000U
4446 #define FMC_BCR1_CPSIZE_2 0x00040000U
4447 #define FMC_BCR1_CBURSTRW 0x00080000U
4448 #define FMC_BCR1_CCLKEN 0x00100000U
4449 #define FMC_BCR1_WFDIS 0x00200000U
4451 /****************** Bit definition for FMC_BCR2 register *******************/
4452 #define FMC_BCR2_MBKEN 0x00000001U
4453 #define FMC_BCR2_MUXEN 0x00000002U
4454 #define FMC_BCR2_MTYP 0x0000000CU
4455 #define FMC_BCR2_MTYP_0 0x00000004U
4456 #define FMC_BCR2_MTYP_1 0x00000008U
4457 #define FMC_BCR2_MWID 0x00000030U
4458 #define FMC_BCR2_MWID_0 0x00000010U
4459 #define FMC_BCR2_MWID_1 0x00000020U
4460 #define FMC_BCR2_FACCEN 0x00000040U
4461 #define FMC_BCR2_BURSTEN 0x00000100U
4462 #define FMC_BCR2_WAITPOL 0x00000200U
4463 #define FMC_BCR2_WRAPMOD 0x00000400U
4464 #define FMC_BCR2_WAITCFG 0x00000800U
4465 #define FMC_BCR2_WREN 0x00001000U
4466 #define FMC_BCR2_WAITEN 0x00002000U
4467 #define FMC_BCR2_EXTMOD 0x00004000U
4468 #define FMC_BCR2_ASYNCWAIT 0x00008000U
4469 #define FMC_BCR2_CPSIZE 0x00070000U
4470 #define FMC_BCR2_CPSIZE_0 0x00010000U
4471 #define FMC_BCR2_CPSIZE_1 0x00020000U
4472 #define FMC_BCR2_CPSIZE_2 0x00040000U
4473 #define FMC_BCR2_CBURSTRW 0x00080000U
4475 /****************** Bit definition for FMC_BCR3 register *******************/
4476 #define FMC_BCR3_MBKEN 0x00000001U
4477 #define FMC_BCR3_MUXEN 0x00000002U
4478 #define FMC_BCR3_MTYP 0x0000000CU
4479 #define FMC_BCR3_MTYP_0 0x00000004U
4480 #define FMC_BCR3_MTYP_1 0x00000008U
4481 #define FMC_BCR3_MWID 0x00000030U
4482 #define FMC_BCR3_MWID_0 0x00000010U
4483 #define FMC_BCR3_MWID_1 0x00000020U
4484 #define FMC_BCR3_FACCEN 0x00000040U
4485 #define FMC_BCR3_BURSTEN 0x00000100U
4486 #define FMC_BCR3_WAITPOL 0x00000200U
4487 #define FMC_BCR3_WRAPMOD 0x00000400U
4488 #define FMC_BCR3_WAITCFG 0x00000800U
4489 #define FMC_BCR3_WREN 0x00001000U
4490 #define FMC_BCR3_WAITEN 0x00002000U
4491 #define FMC_BCR3_EXTMOD 0x00004000U
4492 #define FMC_BCR3_ASYNCWAIT 0x00008000U
4493 #define FMC_BCR3_CPSIZE 0x00070000U
4494 #define FMC_BCR3_CPSIZE_0 0x00010000U
4495 #define FMC_BCR3_CPSIZE_1 0x00020000U
4496 #define FMC_BCR3_CPSIZE_2 0x00040000U
4497 #define FMC_BCR3_CBURSTRW 0x00080000U
4499 /****************** Bit definition for FMC_BCR4 register *******************/
4500 #define FMC_BCR4_MBKEN 0x00000001U
4501 #define FMC_BCR4_MUXEN 0x00000002U
4502 #define FMC_BCR4_MTYP 0x0000000CU
4503 #define FMC_BCR4_MTYP_0 0x00000004U
4504 #define FMC_BCR4_MTYP_1 0x00000008U
4505 #define FMC_BCR4_MWID 0x00000030U
4506 #define FMC_BCR4_MWID_0 0x00000010U
4507 #define FMC_BCR4_MWID_1 0x00000020U
4508 #define FMC_BCR4_FACCEN 0x00000040U
4509 #define FMC_BCR4_BURSTEN 0x00000100U
4510 #define FMC_BCR4_WAITPOL 0x00000200U
4511 #define FMC_BCR4_WRAPMOD 0x00000400U
4512 #define FMC_BCR4_WAITCFG 0x00000800U
4513 #define FMC_BCR4_WREN 0x00001000U
4514 #define FMC_BCR4_WAITEN 0x00002000U
4515 #define FMC_BCR4_EXTMOD 0x00004000U
4516 #define FMC_BCR4_ASYNCWAIT 0x00008000U
4517 #define FMC_BCR4_CPSIZE 0x00070000U
4518 #define FMC_BCR4_CPSIZE_0 0x00010000U
4519 #define FMC_BCR4_CPSIZE_1 0x00020000U
4520 #define FMC_BCR4_CPSIZE_2 0x00040000U
4521 #define FMC_BCR4_CBURSTRW 0x00080000U
4523 /****************** Bit definition for FMC_BTR1 register ******************/
4524 #define FMC_BTR1_ADDSET 0x0000000FU
4525 #define FMC_BTR1_ADDSET_0 0x00000001U
4526 #define FMC_BTR1_ADDSET_1 0x00000002U
4527 #define FMC_BTR1_ADDSET_2 0x00000004U
4528 #define FMC_BTR1_ADDSET_3 0x00000008U
4529 #define FMC_BTR1_ADDHLD 0x000000F0U
4530 #define FMC_BTR1_ADDHLD_0 0x00000010U
4531 #define FMC_BTR1_ADDHLD_1 0x00000020U
4532 #define FMC_BTR1_ADDHLD_2 0x00000040U
4533 #define FMC_BTR1_ADDHLD_3 0x00000080U
4534 #define FMC_BTR1_DATAST 0x0000FF00U
4535 #define FMC_BTR1_DATAST_0 0x00000100U
4536 #define FMC_BTR1_DATAST_1 0x00000200U
4537 #define FMC_BTR1_DATAST_2 0x00000400U
4538 #define FMC_BTR1_DATAST_3 0x00000800U
4539 #define FMC_BTR1_DATAST_4 0x00001000U
4540 #define FMC_BTR1_DATAST_5 0x00002000U
4541 #define FMC_BTR1_DATAST_6 0x00004000U
4542 #define FMC_BTR1_DATAST_7 0x00008000U
4543 #define FMC_BTR1_BUSTURN 0x000F0000U
4544 #define FMC_BTR1_BUSTURN_0 0x00010000U
4545 #define FMC_BTR1_BUSTURN_1 0x00020000U
4546 #define FMC_BTR1_BUSTURN_2 0x00040000U
4547 #define FMC_BTR1_BUSTURN_3 0x00080000U
4548 #define FMC_BTR1_CLKDIV 0x00F00000U
4549 #define FMC_BTR1_CLKDIV_0 0x00100000U
4550 #define FMC_BTR1_CLKDIV_1 0x00200000U
4551 #define FMC_BTR1_CLKDIV_2 0x00400000U
4552 #define FMC_BTR1_CLKDIV_3 0x00800000U
4553 #define FMC_BTR1_DATLAT 0x0F000000U
4554 #define FMC_BTR1_DATLAT_0 0x01000000U
4555 #define FMC_BTR1_DATLAT_1 0x02000000U
4556 #define FMC_BTR1_DATLAT_2 0x04000000U
4557 #define FMC_BTR1_DATLAT_3 0x08000000U
4558 #define FMC_BTR1_ACCMOD 0x30000000U
4559 #define FMC_BTR1_ACCMOD_0 0x10000000U
4560 #define FMC_BTR1_ACCMOD_1 0x20000000U
4562 /****************** Bit definition for FMC_BTR2 register *******************/
4563 #define FMC_BTR2_ADDSET 0x0000000FU
4564 #define FMC_BTR2_ADDSET_0 0x00000001U
4565 #define FMC_BTR2_ADDSET_1 0x00000002U
4566 #define FMC_BTR2_ADDSET_2 0x00000004U
4567 #define FMC_BTR2_ADDSET_3 0x00000008U
4568 #define FMC_BTR2_ADDHLD 0x000000F0U
4569 #define FMC_BTR2_ADDHLD_0 0x00000010U
4570 #define FMC_BTR2_ADDHLD_1 0x00000020U
4571 #define FMC_BTR2_ADDHLD_2 0x00000040U
4572 #define FMC_BTR2_ADDHLD_3 0x00000080U
4573 #define FMC_BTR2_DATAST 0x0000FF00U
4574 #define FMC_BTR2_DATAST_0 0x00000100U
4575 #define FMC_BTR2_DATAST_1 0x00000200U
4576 #define FMC_BTR2_DATAST_2 0x00000400U
4577 #define FMC_BTR2_DATAST_3 0x00000800U
4578 #define FMC_BTR2_DATAST_4 0x00001000U
4579 #define FMC_BTR2_DATAST_5 0x00002000U
4580 #define FMC_BTR2_DATAST_6 0x00004000U
4581 #define FMC_BTR2_DATAST_7 0x00008000U
4582 #define FMC_BTR2_BUSTURN 0x000F0000U
4583 #define FMC_BTR2_BUSTURN_0 0x00010000U
4584 #define FMC_BTR2_BUSTURN_1 0x00020000U
4585 #define FMC_BTR2_BUSTURN_2 0x00040000U
4586 #define FMC_BTR2_BUSTURN_3 0x00080000U
4587 #define FMC_BTR2_CLKDIV 0x00F00000U
4588 #define FMC_BTR2_CLKDIV_0 0x00100000U
4589 #define FMC_BTR2_CLKDIV_1 0x00200000U
4590 #define FMC_BTR2_CLKDIV_2 0x00400000U
4591 #define FMC_BTR2_CLKDIV_3 0x00800000U
4592 #define FMC_BTR2_DATLAT 0x0F000000U
4593 #define FMC_BTR2_DATLAT_0 0x01000000U
4594 #define FMC_BTR2_DATLAT_1 0x02000000U
4595 #define FMC_BTR2_DATLAT_2 0x04000000U
4596 #define FMC_BTR2_DATLAT_3 0x08000000U
4597 #define FMC_BTR2_ACCMOD 0x30000000U
4598 #define FMC_BTR2_ACCMOD_0 0x10000000U
4599 #define FMC_BTR2_ACCMOD_1 0x20000000U
4601 /******************* Bit definition for FMC_BTR3 register *******************/
4602 #define FMC_BTR3_ADDSET 0x0000000FU
4603 #define FMC_BTR3_ADDSET_0 0x00000001U
4604 #define FMC_BTR3_ADDSET_1 0x00000002U
4605 #define FMC_BTR3_ADDSET_2 0x00000004U
4606 #define FMC_BTR3_ADDSET_3 0x00000008U
4607 #define FMC_BTR3_ADDHLD 0x000000F0U
4608 #define FMC_BTR3_ADDHLD_0 0x00000010U
4609 #define FMC_BTR3_ADDHLD_1 0x00000020U
4610 #define FMC_BTR3_ADDHLD_2 0x00000040U
4611 #define FMC_BTR3_ADDHLD_3 0x00000080U
4612 #define FMC_BTR3_DATAST 0x0000FF00U
4613 #define FMC_BTR3_DATAST_0 0x00000100U
4614 #define FMC_BTR3_DATAST_1 0x00000200U
4615 #define FMC_BTR3_DATAST_2 0x00000400U
4616 #define FMC_BTR3_DATAST_3 0x00000800U
4617 #define FMC_BTR3_DATAST_4 0x00001000U
4618 #define FMC_BTR3_DATAST_5 0x00002000U
4619 #define FMC_BTR3_DATAST_6 0x00004000U
4620 #define FMC_BTR3_DATAST_7 0x00008000U
4621 #define FMC_BTR3_BUSTURN 0x000F0000U
4622 #define FMC_BTR3_BUSTURN_0 0x00010000U
4623 #define FMC_BTR3_BUSTURN_1 0x00020000U
4624 #define FMC_BTR3_BUSTURN_2 0x00040000U
4625 #define FMC_BTR3_BUSTURN_3 0x00080000U
4626 #define FMC_BTR3_CLKDIV 0x00F00000U
4627 #define FMC_BTR3_CLKDIV_0 0x00100000U
4628 #define FMC_BTR3_CLKDIV_1 0x00200000U
4629 #define FMC_BTR3_CLKDIV_2 0x00400000U
4630 #define FMC_BTR3_CLKDIV_3 0x00800000U
4631 #define FMC_BTR3_DATLAT 0x0F000000U
4632 #define FMC_BTR3_DATLAT_0 0x01000000U
4633 #define FMC_BTR3_DATLAT_1 0x02000000U
4634 #define FMC_BTR3_DATLAT_2 0x04000000U
4635 #define FMC_BTR3_DATLAT_3 0x08000000U
4636 #define FMC_BTR3_ACCMOD 0x30000000U
4637 #define FMC_BTR3_ACCMOD_0 0x10000000U
4638 #define FMC_BTR3_ACCMOD_1 0x20000000U
4640 /****************** Bit definition for FMC_BTR4 register *******************/
4641 #define FMC_BTR4_ADDSET 0x0000000FU
4642 #define FMC_BTR4_ADDSET_0 0x00000001U
4643 #define FMC_BTR4_ADDSET_1 0x00000002U
4644 #define FMC_BTR4_ADDSET_2 0x00000004U
4645 #define FMC_BTR4_ADDSET_3 0x00000008U
4646 #define FMC_BTR4_ADDHLD 0x000000F0U
4647 #define FMC_BTR4_ADDHLD_0 0x00000010U
4648 #define FMC_BTR4_ADDHLD_1 0x00000020U
4649 #define FMC_BTR4_ADDHLD_2 0x00000040U
4650 #define FMC_BTR4_ADDHLD_3 0x00000080U
4651 #define FMC_BTR4_DATAST 0x0000FF00U
4652 #define FMC_BTR4_DATAST_0 0x00000100U
4653 #define FMC_BTR4_DATAST_1 0x00000200U
4654 #define FMC_BTR4_DATAST_2 0x00000400U
4655 #define FMC_BTR4_DATAST_3 0x00000800U
4656 #define FMC_BTR4_DATAST_4 0x00001000U
4657 #define FMC_BTR4_DATAST_5 0x00002000U
4658 #define FMC_BTR4_DATAST_6 0x00004000U
4659 #define FMC_BTR4_DATAST_7 0x00008000U
4660 #define FMC_BTR4_BUSTURN 0x000F0000U
4661 #define FMC_BTR4_BUSTURN_0 0x00010000U
4662 #define FMC_BTR4_BUSTURN_1 0x00020000U
4663 #define FMC_BTR4_BUSTURN_2 0x00040000U
4664 #define FMC_BTR4_BUSTURN_3 0x00080000U
4665 #define FMC_BTR4_CLKDIV 0x00F00000U
4666 #define FMC_BTR4_CLKDIV_0 0x00100000U
4667 #define FMC_BTR4_CLKDIV_1 0x00200000U
4668 #define FMC_BTR4_CLKDIV_2 0x00400000U
4669 #define FMC_BTR4_CLKDIV_3 0x00800000U
4670 #define FMC_BTR4_DATLAT 0x0F000000U
4671 #define FMC_BTR4_DATLAT_0 0x01000000U
4672 #define FMC_BTR4_DATLAT_1 0x02000000U
4673 #define FMC_BTR4_DATLAT_2 0x04000000U
4674 #define FMC_BTR4_DATLAT_3 0x08000000U
4675 #define FMC_BTR4_ACCMOD 0x30000000U
4676 #define FMC_BTR4_ACCMOD_0 0x10000000U
4677 #define FMC_BTR4_ACCMOD_1 0x20000000U
4679 /****************** Bit definition for FMC_BWTR1 register ******************/
4680 #define FMC_BWTR1_ADDSET 0x0000000FU
4681 #define FMC_BWTR1_ADDSET_0 0x00000001U
4682 #define FMC_BWTR1_ADDSET_1 0x00000002U
4683 #define FMC_BWTR1_ADDSET_2 0x00000004U
4684 #define FMC_BWTR1_ADDSET_3 0x00000008U
4685 #define FMC_BWTR1_ADDHLD 0x000000F0U
4686 #define FMC_BWTR1_ADDHLD_0 0x00000010U
4687 #define FMC_BWTR1_ADDHLD_1 0x00000020U
4688 #define FMC_BWTR1_ADDHLD_2 0x00000040U
4689 #define FMC_BWTR1_ADDHLD_3 0x00000080U
4690 #define FMC_BWTR1_DATAST 0x0000FF00U
4691 #define FMC_BWTR1_DATAST_0 0x00000100U
4692 #define FMC_BWTR1_DATAST_1 0x00000200U
4693 #define FMC_BWTR1_DATAST_2 0x00000400U
4694 #define FMC_BWTR1_DATAST_3 0x00000800U
4695 #define FMC_BWTR1_DATAST_4 0x00001000U
4696 #define FMC_BWTR1_DATAST_5 0x00002000U
4697 #define FMC_BWTR1_DATAST_6 0x00004000U
4698 #define FMC_BWTR1_DATAST_7 0x00008000U
4699 #define FMC_BWTR1_BUSTURN 0x000F0000U
4700 #define FMC_BWTR1_BUSTURN_0 0x00010000U
4701 #define FMC_BWTR1_BUSTURN_1 0x00020000U
4702 #define FMC_BWTR1_BUSTURN_2 0x00040000U
4703 #define FMC_BWTR1_BUSTURN_3 0x00080000U
4704 #define FMC_BWTR1_ACCMOD 0x30000000U
4705 #define FMC_BWTR1_ACCMOD_0 0x10000000U
4706 #define FMC_BWTR1_ACCMOD_1 0x20000000U
4708 /****************** Bit definition for FMC_BWTR2 register ******************/
4709 #define FMC_BWTR2_ADDSET 0x0000000FU
4710 #define FMC_BWTR2_ADDSET_0 0x00000001U
4711 #define FMC_BWTR2_ADDSET_1 0x00000002U
4712 #define FMC_BWTR2_ADDSET_2 0x00000004U
4713 #define FMC_BWTR2_ADDSET_3 0x00000008U
4714 #define FMC_BWTR2_ADDHLD 0x000000F0U
4715 #define FMC_BWTR2_ADDHLD_0 0x00000010U
4716 #define FMC_BWTR2_ADDHLD_1 0x00000020U
4717 #define FMC_BWTR2_ADDHLD_2 0x00000040U
4718 #define FMC_BWTR2_ADDHLD_3 0x00000080U
4719 #define FMC_BWTR2_DATAST 0x0000FF00U
4720 #define FMC_BWTR2_DATAST_0 0x00000100U
4721 #define FMC_BWTR2_DATAST_1 0x00000200U
4722 #define FMC_BWTR2_DATAST_2 0x00000400U
4723 #define FMC_BWTR2_DATAST_3 0x00000800U
4724 #define FMC_BWTR2_DATAST_4 0x00001000U
4725 #define FMC_BWTR2_DATAST_5 0x00002000U
4726 #define FMC_BWTR2_DATAST_6 0x00004000U
4727 #define FMC_BWTR2_DATAST_7 0x00008000U
4728 #define FMC_BWTR2_BUSTURN 0x000F0000U
4729 #define FMC_BWTR2_BUSTURN_0 0x00010000U
4730 #define FMC_BWTR2_BUSTURN_1 0x00020000U
4731 #define FMC_BWTR2_BUSTURN_2 0x00040000U
4732 #define FMC_BWTR2_BUSTURN_3 0x00080000U
4733 #define FMC_BWTR2_ACCMOD 0x30000000U
4734 #define FMC_BWTR2_ACCMOD_0 0x10000000U
4735 #define FMC_BWTR2_ACCMOD_1 0x20000000U
4737 /****************** Bit definition for FMC_BWTR3 register ******************/
4738 #define FMC_BWTR3_ADDSET 0x0000000FU
4739 #define FMC_BWTR3_ADDSET_0 0x00000001U
4740 #define FMC_BWTR3_ADDSET_1 0x00000002U
4741 #define FMC_BWTR3_ADDSET_2 0x00000004U
4742 #define FMC_BWTR3_ADDSET_3 0x00000008U
4743 #define FMC_BWTR3_ADDHLD 0x000000F0U
4744 #define FMC_BWTR3_ADDHLD_0 0x00000010U
4745 #define FMC_BWTR3_ADDHLD_1 0x00000020U
4746 #define FMC_BWTR3_ADDHLD_2 0x00000040U
4747 #define FMC_BWTR3_ADDHLD_3 0x00000080U
4748 #define FMC_BWTR3_DATAST 0x0000FF00U
4749 #define FMC_BWTR3_DATAST_0 0x00000100U
4750 #define FMC_BWTR3_DATAST_1 0x00000200U
4751 #define FMC_BWTR3_DATAST_2 0x00000400U
4752 #define FMC_BWTR3_DATAST_3 0x00000800U
4753 #define FMC_BWTR3_DATAST_4 0x00001000U
4754 #define FMC_BWTR3_DATAST_5 0x00002000U
4755 #define FMC_BWTR3_DATAST_6 0x00004000U
4756 #define FMC_BWTR3_DATAST_7 0x00008000U
4757 #define FMC_BWTR3_BUSTURN 0x000F0000U
4758 #define FMC_BWTR3_BUSTURN_0 0x00010000U
4759 #define FMC_BWTR3_BUSTURN_1 0x00020000U
4760 #define FMC_BWTR3_BUSTURN_2 0x00040000U
4761 #define FMC_BWTR3_BUSTURN_3 0x00080000U
4762 #define FMC_BWTR3_ACCMOD 0x30000000U
4763 #define FMC_BWTR3_ACCMOD_0 0x10000000U
4764 #define FMC_BWTR3_ACCMOD_1 0x20000000U
4766 /****************** Bit definition for FMC_BWTR4 register ******************/
4767 #define FMC_BWTR4_ADDSET 0x0000000FU
4768 #define FMC_BWTR4_ADDSET_0 0x00000001U
4769 #define FMC_BWTR4_ADDSET_1 0x00000002U
4770 #define FMC_BWTR4_ADDSET_2 0x00000004U
4771 #define FMC_BWTR4_ADDSET_3 0x00000008U
4772 #define FMC_BWTR4_ADDHLD 0x000000F0U
4773 #define FMC_BWTR4_ADDHLD_0 0x00000010U
4774 #define FMC_BWTR4_ADDHLD_1 0x00000020U
4775 #define FMC_BWTR4_ADDHLD_2 0x00000040U
4776 #define FMC_BWTR4_ADDHLD_3 0x00000080U
4777 #define FMC_BWTR4_DATAST 0x0000FF00U
4778 #define FMC_BWTR4_DATAST_0 0x00000100U
4779 #define FMC_BWTR4_DATAST_1 0x00000200U
4780 #define FMC_BWTR4_DATAST_2 0x00000400U
4781 #define FMC_BWTR4_DATAST_3 0x00000800U
4782 #define FMC_BWTR4_DATAST_4 0x00001000U
4783 #define FMC_BWTR4_DATAST_5 0x00002000U
4784 #define FMC_BWTR4_DATAST_6 0x00004000U
4785 #define FMC_BWTR4_DATAST_7 0x00008000U
4786 #define FMC_BWTR4_BUSTURN 0x000F0000U
4787 #define FMC_BWTR4_BUSTURN_0 0x00010000U
4788 #define FMC_BWTR4_BUSTURN_1 0x00020000U
4789 #define FMC_BWTR4_BUSTURN_2 0x00040000U
4790 #define FMC_BWTR4_BUSTURN_3 0x00080000U
4791 #define FMC_BWTR4_ACCMOD 0x30000000U
4792 #define FMC_BWTR4_ACCMOD_0 0x10000000U
4793 #define FMC_BWTR4_ACCMOD_1 0x20000000U
4795 /****************** Bit definition for FMC_PCR register *******************/
4796 #define FMC_PCR_PWAITEN 0x00000002U
4797 #define FMC_PCR_PBKEN 0x00000004U
4798 #define FMC_PCR_PTYP 0x00000008U
4799 #define FMC_PCR_PWID 0x00000030U
4800 #define FMC_PCR_PWID_0 0x00000010U
4801 #define FMC_PCR_PWID_1 0x00000020U
4802 #define FMC_PCR_ECCEN 0x00000040U
4803 #define FMC_PCR_TCLR 0x00001E00U
4804 #define FMC_PCR_TCLR_0 0x00000200U
4805 #define FMC_PCR_TCLR_1 0x00000400U
4806 #define FMC_PCR_TCLR_2 0x00000800U
4807 #define FMC_PCR_TCLR_3 0x00001000U
4808 #define FMC_PCR_TAR 0x0001E000U
4809 #define FMC_PCR_TAR_0 0x00002000U
4810 #define FMC_PCR_TAR_1 0x00004000U
4811 #define FMC_PCR_TAR_2 0x00008000U
4812 #define FMC_PCR_TAR_3 0x00010000U
4813 #define FMC_PCR_ECCPS 0x000E0000U
4814 #define FMC_PCR_ECCPS_0 0x00020000U
4815 #define FMC_PCR_ECCPS_1 0x00040000U
4816 #define FMC_PCR_ECCPS_2 0x00080000U
4818 /******************* Bit definition for FMC_SR register *******************/
4819 #define FMC_SR_IRS 0x01U
4820 #define FMC_SR_ILS 0x02U
4821 #define FMC_SR_IFS 0x04U
4822 #define FMC_SR_IREN 0x08U
4823 #define FMC_SR_ILEN 0x10U
4824 #define FMC_SR_IFEN 0x20U
4825 #define FMC_SR_FEMPT 0x40U
4827 /****************** Bit definition for FMC_PMEM register ******************/
4828 #define FMC_PMEM_MEMSET3 0x000000FFU
4829 #define FMC_PMEM_MEMSET3_0 0x00000001U
4830 #define FMC_PMEM_MEMSET3_1 0x00000002U
4831 #define FMC_PMEM_MEMSET3_2 0x00000004U
4832 #define FMC_PMEM_MEMSET3_3 0x00000008U
4833 #define FMC_PMEM_MEMSET3_4 0x00000010U
4834 #define FMC_PMEM_MEMSET3_5 0x00000020U
4835 #define FMC_PMEM_MEMSET3_6 0x00000040U
4836 #define FMC_PMEM_MEMSET3_7 0x00000080U
4837 #define FMC_PMEM_MEMWAIT3 0x0000FF00U
4838 #define FMC_PMEM_MEMWAIT3_0 0x00000100U
4839 #define FMC_PMEM_MEMWAIT3_1 0x00000200U
4840 #define FMC_PMEM_MEMWAIT3_2 0x00000400U
4841 #define FMC_PMEM_MEMWAIT3_3 0x00000800U
4842 #define FMC_PMEM_MEMWAIT3_4 0x00001000U
4843 #define FMC_PMEM_MEMWAIT3_5 0x00002000U
4844 #define FMC_PMEM_MEMWAIT3_6 0x00004000U
4845 #define FMC_PMEM_MEMWAIT3_7 0x00008000U
4846 #define FMC_PMEM_MEMHOLD3 0x00FF0000U
4847 #define FMC_PMEM_MEMHOLD3_0 0x00010000U
4848 #define FMC_PMEM_MEMHOLD3_1 0x00020000U
4849 #define FMC_PMEM_MEMHOLD3_2 0x00040000U
4850 #define FMC_PMEM_MEMHOLD3_3 0x00080000U
4851 #define FMC_PMEM_MEMHOLD3_4 0x00100000U
4852 #define FMC_PMEM_MEMHOLD3_5 0x00200000U
4853 #define FMC_PMEM_MEMHOLD3_6 0x00400000U
4854 #define FMC_PMEM_MEMHOLD3_7 0x00800000U
4855 #define FMC_PMEM_MEMHIZ3 0xFF000000U
4856 #define FMC_PMEM_MEMHIZ3_0 0x01000000U
4857 #define FMC_PMEM_MEMHIZ3_1 0x02000000U
4858 #define FMC_PMEM_MEMHIZ3_2 0x04000000U
4859 #define FMC_PMEM_MEMHIZ3_3 0x08000000U
4860 #define FMC_PMEM_MEMHIZ3_4 0x10000000U
4861 #define FMC_PMEM_MEMHIZ3_5 0x20000000U
4862 #define FMC_PMEM_MEMHIZ3_6 0x40000000U
4863 #define FMC_PMEM_MEMHIZ3_7 0x80000000U
4865 /****************** Bit definition for FMC_PATT register ******************/
4866 #define FMC_PATT_ATTSET3 0x000000FFU
4867 #define FMC_PATT_ATTSET3_0 0x00000001U
4868 #define FMC_PATT_ATTSET3_1 0x00000002U
4869 #define FMC_PATT_ATTSET3_2 0x00000004U
4870 #define FMC_PATT_ATTSET3_3 0x00000008U
4871 #define FMC_PATT_ATTSET3_4 0x00000010U
4872 #define FMC_PATT_ATTSET3_5 0x00000020U
4873 #define FMC_PATT_ATTSET3_6 0x00000040U
4874 #define FMC_PATT_ATTSET3_7 0x00000080U
4875 #define FMC_PATT_ATTWAIT3 0x0000FF00U
4876 #define FMC_PATT_ATTWAIT3_0 0x00000100U
4877 #define FMC_PATT_ATTWAIT3_1 0x00000200U
4878 #define FMC_PATT_ATTWAIT3_2 0x00000400U
4879 #define FMC_PATT_ATTWAIT3_3 0x00000800U
4880 #define FMC_PATT_ATTWAIT3_4 0x00001000U
4881 #define FMC_PATT_ATTWAIT3_5 0x00002000U
4882 #define FMC_PATT_ATTWAIT3_6 0x00004000U
4883 #define FMC_PATT_ATTWAIT3_7 0x00008000U
4884 #define FMC_PATT_ATTHOLD3 0x00FF0000U
4885 #define FMC_PATT_ATTHOLD3_0 0x00010000U
4886 #define FMC_PATT_ATTHOLD3_1 0x00020000U
4887 #define FMC_PATT_ATTHOLD3_2 0x00040000U
4888 #define FMC_PATT_ATTHOLD3_3 0x00080000U
4889 #define FMC_PATT_ATTHOLD3_4 0x00100000U
4890 #define FMC_PATT_ATTHOLD3_5 0x00200000U
4891 #define FMC_PATT_ATTHOLD3_6 0x00400000U
4892 #define FMC_PATT_ATTHOLD3_7 0x00800000U
4893 #define FMC_PATT_ATTHIZ3 0xFF000000U
4894 #define FMC_PATT_ATTHIZ3_0 0x01000000U
4895 #define FMC_PATT_ATTHIZ3_1 0x02000000U
4896 #define FMC_PATT_ATTHIZ3_2 0x04000000U
4897 #define FMC_PATT_ATTHIZ3_3 0x08000000U
4898 #define FMC_PATT_ATTHIZ3_4 0x10000000U
4899 #define FMC_PATT_ATTHIZ3_5 0x20000000U
4900 #define FMC_PATT_ATTHIZ3_6 0x40000000U
4901 #define FMC_PATT_ATTHIZ3_7 0x80000000U
4903 /****************** Bit definition for FMC_ECCR register ******************/
4904 #define FMC_ECCR_ECC3 0xFFFFFFFFU
4906 /****************** Bit definition for FMC_SDCR1 register ******************/
4907 #define FMC_SDCR1_NC 0x00000003U
4908 #define FMC_SDCR1_NC_0 0x00000001U
4909 #define FMC_SDCR1_NC_1 0x00000002U
4910 #define FMC_SDCR1_NR 0x0000000CU
4911 #define FMC_SDCR1_NR_0 0x00000004U
4912 #define FMC_SDCR1_NR_1 0x00000008U
4913 #define FMC_SDCR1_MWID 0x00000030U
4914 #define FMC_SDCR1_MWID_0 0x00000010U
4915 #define FMC_SDCR1_MWID_1 0x00000020U
4916 #define FMC_SDCR1_NB 0x00000040U
4917 #define FMC_SDCR1_CAS 0x00000180U
4918 #define FMC_SDCR1_CAS_0 0x00000080U
4919 #define FMC_SDCR1_CAS_1 0x00000100U
4920 #define FMC_SDCR1_WP 0x00000200U
4921 #define FMC_SDCR1_SDCLK 0x00000C00U
4922 #define FMC_SDCR1_SDCLK_0 0x00000400U
4923 #define FMC_SDCR1_SDCLK_1 0x00000800U
4924 #define FMC_SDCR1_RBURST 0x00001000U
4925 #define FMC_SDCR1_RPIPE 0x00006000U
4926 #define FMC_SDCR1_RPIPE_0 0x00002000U
4927 #define FMC_SDCR1_RPIPE_1 0x00004000U
4929 /****************** Bit definition for FMC_SDCR2 register ******************/
4930 #define FMC_SDCR2_NC 0x00000003U
4931 #define FMC_SDCR2_NC_0 0x00000001U
4932 #define FMC_SDCR2_NC_1 0x00000002U
4933 #define FMC_SDCR2_NR 0x0000000CU
4934 #define FMC_SDCR2_NR_0 0x00000004U
4935 #define FMC_SDCR2_NR_1 0x00000008U
4936 #define FMC_SDCR2_MWID 0x00000030U
4937 #define FMC_SDCR2_MWID_0 0x00000010U
4938 #define FMC_SDCR2_MWID_1 0x00000020U
4939 #define FMC_SDCR2_NB 0x00000040U
4940 #define FMC_SDCR2_CAS 0x00000180U
4941 #define FMC_SDCR2_CAS_0 0x00000080U
4942 #define FMC_SDCR2_CAS_1 0x00000100U
4943 #define FMC_SDCR2_WP 0x00000200U
4944 #define FMC_SDCR2_SDCLK 0x00000C00U
4945 #define FMC_SDCR2_SDCLK_0 0x00000400U
4946 #define FMC_SDCR2_SDCLK_1 0x00000800U
4947 #define FMC_SDCR2_RBURST 0x00001000U
4948 #define FMC_SDCR2_RPIPE 0x00006000U
4949 #define FMC_SDCR2_RPIPE_0 0x00002000U
4950 #define FMC_SDCR2_RPIPE_1 0x00004000U
4952 /****************** Bit definition for FMC_SDTR1 register ******************/
4953 #define FMC_SDTR1_TMRD 0x0000000FU
4954 #define FMC_SDTR1_TMRD_0 0x00000001U
4955 #define FMC_SDTR1_TMRD_1 0x00000002U
4956 #define FMC_SDTR1_TMRD_2 0x00000004U
4957 #define FMC_SDTR1_TMRD_3 0x00000008U
4958 #define FMC_SDTR1_TXSR 0x000000F0U
4959 #define FMC_SDTR1_TXSR_0 0x00000010U
4960 #define FMC_SDTR1_TXSR_1 0x00000020U
4961 #define FMC_SDTR1_TXSR_2 0x00000040U
4962 #define FMC_SDTR1_TXSR_3 0x00000080U
4963 #define FMC_SDTR1_TRAS 0x00000F00U
4964 #define FMC_SDTR1_TRAS_0 0x00000100U
4965 #define FMC_SDTR1_TRAS_1 0x00000200U
4966 #define FMC_SDTR1_TRAS_2 0x00000400U
4967 #define FMC_SDTR1_TRAS_3 0x00000800U
4968 #define FMC_SDTR1_TRC 0x0000F000U
4969 #define FMC_SDTR1_TRC_0 0x00001000U
4970 #define FMC_SDTR1_TRC_1 0x00002000U
4971 #define FMC_SDTR1_TRC_2 0x00004000U
4972 #define FMC_SDTR1_TWR 0x000F0000U
4973 #define FMC_SDTR1_TWR_0 0x00010000U
4974 #define FMC_SDTR1_TWR_1 0x00020000U
4975 #define FMC_SDTR1_TWR_2 0x00040000U
4976 #define FMC_SDTR1_TRP 0x00F00000U
4977 #define FMC_SDTR1_TRP_0 0x00100000U
4978 #define FMC_SDTR1_TRP_1 0x00200000U
4979 #define FMC_SDTR1_TRP_2 0x00400000U
4980 #define FMC_SDTR1_TRCD 0x0F000000U
4981 #define FMC_SDTR1_TRCD_0 0x01000000U
4982 #define FMC_SDTR1_TRCD_1 0x02000000U
4983 #define FMC_SDTR1_TRCD_2 0x04000000U
4985 /****************** Bit definition for FMC_SDTR2 register ******************/
4986 #define FMC_SDTR2_TMRD 0x0000000FU
4987 #define FMC_SDTR2_TMRD_0 0x00000001U
4988 #define FMC_SDTR2_TMRD_1 0x00000002U
4989 #define FMC_SDTR2_TMRD_2 0x00000004U
4990 #define FMC_SDTR2_TMRD_3 0x00000008U
4991 #define FMC_SDTR2_TXSR 0x000000F0U
4992 #define FMC_SDTR2_TXSR_0 0x00000010U
4993 #define FMC_SDTR2_TXSR_1 0x00000020U
4994 #define FMC_SDTR2_TXSR_2 0x00000040U
4995 #define FMC_SDTR2_TXSR_3 0x00000080U
4996 #define FMC_SDTR2_TRAS 0x00000F00U
4997 #define FMC_SDTR2_TRAS_0 0x00000100U
4998 #define FMC_SDTR2_TRAS_1 0x00000200U
4999 #define FMC_SDTR2_TRAS_2 0x00000400U
5000 #define FMC_SDTR2_TRAS_3 0x00000800U
5001 #define FMC_SDTR2_TRC 0x0000F000U
5002 #define FMC_SDTR2_TRC_0 0x00001000U
5003 #define FMC_SDTR2_TRC_1 0x00002000U
5004 #define FMC_SDTR2_TRC_2 0x00004000U
5005 #define FMC_SDTR2_TWR 0x000F0000U
5006 #define FMC_SDTR2_TWR_0 0x00010000U
5007 #define FMC_SDTR2_TWR_1 0x00020000U
5008 #define FMC_SDTR2_TWR_2 0x00040000U
5009 #define FMC_SDTR2_TRP 0x00F00000U
5010 #define FMC_SDTR2_TRP_0 0x00100000U
5011 #define FMC_SDTR2_TRP_1 0x00200000U
5012 #define FMC_SDTR2_TRP_2 0x00400000U
5013 #define FMC_SDTR2_TRCD 0x0F000000U
5014 #define FMC_SDTR2_TRCD_0 0x01000000U
5015 #define FMC_SDTR2_TRCD_1 0x02000000U
5016 #define FMC_SDTR2_TRCD_2 0x04000000U
5018 /****************** Bit definition for FMC_SDCMR register ******************/
5019 #define FMC_SDCMR_MODE 0x00000007U
5020 #define FMC_SDCMR_MODE_0 0x00000001U
5021 #define FMC_SDCMR_MODE_1 0x00000002U
5022 #define FMC_SDCMR_MODE_2 0x00000003U
5023 #define FMC_SDCMR_CTB2 0x00000008U
5024 #define FMC_SDCMR_CTB1 0x00000010U
5025 #define FMC_SDCMR_NRFS 0x000001E0U
5026 #define FMC_SDCMR_NRFS_0 0x00000020U
5027 #define FMC_SDCMR_NRFS_1 0x00000040U
5028 #define FMC_SDCMR_NRFS_2 0x00000080U
5029 #define FMC_SDCMR_NRFS_3 0x00000100U
5030 #define FMC_SDCMR_MRD 0x003FFE00U
5032 /****************** Bit definition for FMC_SDRTR register ******************/
5033 #define FMC_SDRTR_CRE 0x00000001U
5034 #define FMC_SDRTR_COUNT 0x00003FFEU
5035 #define FMC_SDRTR_REIE 0x00004000U
5037 /****************** Bit definition for FMC_SDSR register ******************/
5038 #define FMC_SDSR_RE 0x00000001U
5039 #define FMC_SDSR_MODES1 0x00000006U
5040 #define FMC_SDSR_MODES1_0 0x00000002U
5041 #define FMC_SDSR_MODES1_1 0x00000004U
5042 #define FMC_SDSR_MODES2 0x00000018U
5043 #define FMC_SDSR_MODES2_0 0x00000008U
5044 #define FMC_SDSR_MODES2_1 0x00000010U
5045 #define FMC_SDSR_BUSY 0x00000020U
5047 /******************************************************************************/
5048 /* */
5049 /* General Purpose I/O */
5050 /* */
5051 /******************************************************************************/
5052 /****************** Bits definition for GPIO_MODER register *****************/
5053 #define GPIO_MODER_MODER0 0x00000003U
5054 #define GPIO_MODER_MODER0_0 0x00000001U
5055 #define GPIO_MODER_MODER0_1 0x00000002U
5056 #define GPIO_MODER_MODER1 0x0000000CU
5057 #define GPIO_MODER_MODER1_0 0x00000004U
5058 #define GPIO_MODER_MODER1_1 0x00000008U
5059 #define GPIO_MODER_MODER2 0x00000030U
5060 #define GPIO_MODER_MODER2_0 0x00000010U
5061 #define GPIO_MODER_MODER2_1 0x00000020U
5062 #define GPIO_MODER_MODER3 0x000000C0U
5063 #define GPIO_MODER_MODER3_0 0x00000040U
5064 #define GPIO_MODER_MODER3_1 0x00000080U
5065 #define GPIO_MODER_MODER4 0x00000300U
5066 #define GPIO_MODER_MODER4_0 0x00000100U
5067 #define GPIO_MODER_MODER4_1 0x00000200U
5068 #define GPIO_MODER_MODER5 0x00000C00U
5069 #define GPIO_MODER_MODER5_0 0x00000400U
5070 #define GPIO_MODER_MODER5_1 0x00000800U
5071 #define GPIO_MODER_MODER6 0x00003000U
5072 #define GPIO_MODER_MODER6_0 0x00001000U
5073 #define GPIO_MODER_MODER6_1 0x00002000U
5074 #define GPIO_MODER_MODER7 0x0000C000U
5075 #define GPIO_MODER_MODER7_0 0x00004000U
5076 #define GPIO_MODER_MODER7_1 0x00008000U
5077 #define GPIO_MODER_MODER8 0x00030000U
5078 #define GPIO_MODER_MODER8_0 0x00010000U
5079 #define GPIO_MODER_MODER8_1 0x00020000U
5080 #define GPIO_MODER_MODER9 0x000C0000U
5081 #define GPIO_MODER_MODER9_0 0x00040000U
5082 #define GPIO_MODER_MODER9_1 0x00080000U
5083 #define GPIO_MODER_MODER10 0x00300000U
5084 #define GPIO_MODER_MODER10_0 0x00100000U
5085 #define GPIO_MODER_MODER10_1 0x00200000U
5086 #define GPIO_MODER_MODER11 0x00C00000U
5087 #define GPIO_MODER_MODER11_0 0x00400000U
5088 #define GPIO_MODER_MODER11_1 0x00800000U
5089 #define GPIO_MODER_MODER12 0x03000000U
5090 #define GPIO_MODER_MODER12_0 0x01000000U
5091 #define GPIO_MODER_MODER12_1 0x02000000U
5092 #define GPIO_MODER_MODER13 0x0C000000U
5093 #define GPIO_MODER_MODER13_0 0x04000000U
5094 #define GPIO_MODER_MODER13_1 0x08000000U
5095 #define GPIO_MODER_MODER14 0x30000000U
5096 #define GPIO_MODER_MODER14_0 0x10000000U
5097 #define GPIO_MODER_MODER14_1 0x20000000U
5098 #define GPIO_MODER_MODER15 0xC0000000U
5099 #define GPIO_MODER_MODER15_0 0x40000000U
5100 #define GPIO_MODER_MODER15_1 0x80000000U
5101 
5102 /****************** Bits definition for GPIO_OTYPER register ****************/
5103 #define GPIO_OTYPER_OT_0 0x00000001U
5104 #define GPIO_OTYPER_OT_1 0x00000002U
5105 #define GPIO_OTYPER_OT_2 0x00000004U
5106 #define GPIO_OTYPER_OT_3 0x00000008U
5107 #define GPIO_OTYPER_OT_4 0x00000010U
5108 #define GPIO_OTYPER_OT_5 0x00000020U
5109 #define GPIO_OTYPER_OT_6 0x00000040U
5110 #define GPIO_OTYPER_OT_7 0x00000080U
5111 #define GPIO_OTYPER_OT_8 0x00000100U
5112 #define GPIO_OTYPER_OT_9 0x00000200U
5113 #define GPIO_OTYPER_OT_10 0x00000400U
5114 #define GPIO_OTYPER_OT_11 0x00000800U
5115 #define GPIO_OTYPER_OT_12 0x00001000U
5116 #define GPIO_OTYPER_OT_13 0x00002000U
5117 #define GPIO_OTYPER_OT_14 0x00004000U
5118 #define GPIO_OTYPER_OT_15 0x00008000U
5119 
5120 /****************** Bits definition for GPIO_OSPEEDR register ***************/
5121 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
5122 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
5123 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
5124 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
5125 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
5126 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
5127 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
5128 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
5129 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
5130 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
5131 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
5132 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
5133 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
5134 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
5135 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
5136 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
5137 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
5138 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
5139 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
5140 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
5141 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
5142 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
5143 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
5144 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
5145 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
5146 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
5147 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
5148 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
5149 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
5150 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
5151 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
5152 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
5153 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
5154 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
5155 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
5156 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
5157 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
5158 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
5159 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
5160 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
5161 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
5162 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
5163 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
5164 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
5165 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
5166 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
5167 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
5168 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
5169 
5170 /****************** Bits definition for GPIO_PUPDR register *****************/
5171 #define GPIO_PUPDR_PUPDR0 0x00000003U
5172 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
5173 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
5174 #define GPIO_PUPDR_PUPDR1 0x0000000CU
5175 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
5176 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
5177 #define GPIO_PUPDR_PUPDR2 0x00000030U
5178 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
5179 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
5180 #define GPIO_PUPDR_PUPDR3 0x000000C0U
5181 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
5182 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
5183 #define GPIO_PUPDR_PUPDR4 0x00000300U
5184 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
5185 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
5186 #define GPIO_PUPDR_PUPDR5 0x00000C00U
5187 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
5188 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
5189 #define GPIO_PUPDR_PUPDR6 0x00003000U
5190 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
5191 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
5192 #define GPIO_PUPDR_PUPDR7 0x0000C000U
5193 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
5194 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
5195 #define GPIO_PUPDR_PUPDR8 0x00030000U
5196 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
5197 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
5198 #define GPIO_PUPDR_PUPDR9 0x000C0000U
5199 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
5200 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
5201 #define GPIO_PUPDR_PUPDR10 0x00300000U
5202 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
5203 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
5204 #define GPIO_PUPDR_PUPDR11 0x00C00000U
5205 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
5206 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
5207 #define GPIO_PUPDR_PUPDR12 0x03000000U
5208 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
5209 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
5210 #define GPIO_PUPDR_PUPDR13 0x0C000000U
5211 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
5212 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
5213 #define GPIO_PUPDR_PUPDR14 0x30000000U
5214 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
5215 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
5216 #define GPIO_PUPDR_PUPDR15 0xC0000000U
5217 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
5218 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
5219 
5220 /****************** Bits definition for GPIO_IDR register *******************/
5221 #define GPIO_IDR_IDR_0 0x00000001U
5222 #define GPIO_IDR_IDR_1 0x00000002U
5223 #define GPIO_IDR_IDR_2 0x00000004U
5224 #define GPIO_IDR_IDR_3 0x00000008U
5225 #define GPIO_IDR_IDR_4 0x00000010U
5226 #define GPIO_IDR_IDR_5 0x00000020U
5227 #define GPIO_IDR_IDR_6 0x00000040U
5228 #define GPIO_IDR_IDR_7 0x00000080U
5229 #define GPIO_IDR_IDR_8 0x00000100U
5230 #define GPIO_IDR_IDR_9 0x00000200U
5231 #define GPIO_IDR_IDR_10 0x00000400U
5232 #define GPIO_IDR_IDR_11 0x00000800U
5233 #define GPIO_IDR_IDR_12 0x00001000U
5234 #define GPIO_IDR_IDR_13 0x00002000U
5235 #define GPIO_IDR_IDR_14 0x00004000U
5236 #define GPIO_IDR_IDR_15 0x00008000U
5237 
5238 /****************** Bits definition for GPIO_ODR register *******************/
5239 #define GPIO_ODR_ODR_0 0x00000001U
5240 #define GPIO_ODR_ODR_1 0x00000002U
5241 #define GPIO_ODR_ODR_2 0x00000004U
5242 #define GPIO_ODR_ODR_3 0x00000008U
5243 #define GPIO_ODR_ODR_4 0x00000010U
5244 #define GPIO_ODR_ODR_5 0x00000020U
5245 #define GPIO_ODR_ODR_6 0x00000040U
5246 #define GPIO_ODR_ODR_7 0x00000080U
5247 #define GPIO_ODR_ODR_8 0x00000100U
5248 #define GPIO_ODR_ODR_9 0x00000200U
5249 #define GPIO_ODR_ODR_10 0x00000400U
5250 #define GPIO_ODR_ODR_11 0x00000800U
5251 #define GPIO_ODR_ODR_12 0x00001000U
5252 #define GPIO_ODR_ODR_13 0x00002000U
5253 #define GPIO_ODR_ODR_14 0x00004000U
5254 #define GPIO_ODR_ODR_15 0x00008000U
5255 
5256 /****************** Bits definition for GPIO_BSRR register ******************/
5257 #define GPIO_BSRR_BS_0 0x00000001U
5258 #define GPIO_BSRR_BS_1 0x00000002U
5259 #define GPIO_BSRR_BS_2 0x00000004U
5260 #define GPIO_BSRR_BS_3 0x00000008U
5261 #define GPIO_BSRR_BS_4 0x00000010U
5262 #define GPIO_BSRR_BS_5 0x00000020U
5263 #define GPIO_BSRR_BS_6 0x00000040U
5264 #define GPIO_BSRR_BS_7 0x00000080U
5265 #define GPIO_BSRR_BS_8 0x00000100U
5266 #define GPIO_BSRR_BS_9 0x00000200U
5267 #define GPIO_BSRR_BS_10 0x00000400U
5268 #define GPIO_BSRR_BS_11 0x00000800U
5269 #define GPIO_BSRR_BS_12 0x00001000U
5270 #define GPIO_BSRR_BS_13 0x00002000U
5271 #define GPIO_BSRR_BS_14 0x00004000U
5272 #define GPIO_BSRR_BS_15 0x00008000U
5273 #define GPIO_BSRR_BR_0 0x00010000U
5274 #define GPIO_BSRR_BR_1 0x00020000U
5275 #define GPIO_BSRR_BR_2 0x00040000U
5276 #define GPIO_BSRR_BR_3 0x00080000U
5277 #define GPIO_BSRR_BR_4 0x00100000U
5278 #define GPIO_BSRR_BR_5 0x00200000U
5279 #define GPIO_BSRR_BR_6 0x00400000U
5280 #define GPIO_BSRR_BR_7 0x00800000U
5281 #define GPIO_BSRR_BR_8 0x01000000U
5282 #define GPIO_BSRR_BR_9 0x02000000U
5283 #define GPIO_BSRR_BR_10 0x04000000U
5284 #define GPIO_BSRR_BR_11 0x08000000U
5285 #define GPIO_BSRR_BR_12 0x10000000U
5286 #define GPIO_BSRR_BR_13 0x20000000U
5287 #define GPIO_BSRR_BR_14 0x40000000U
5288 #define GPIO_BSRR_BR_15 0x80000000U
5289 
5290 /****************** Bit definition for GPIO_LCKR register *********************/
5291 #define GPIO_LCKR_LCK0 0x00000001U
5292 #define GPIO_LCKR_LCK1 0x00000002U
5293 #define GPIO_LCKR_LCK2 0x00000004U
5294 #define GPIO_LCKR_LCK3 0x00000008U
5295 #define GPIO_LCKR_LCK4 0x00000010U
5296 #define GPIO_LCKR_LCK5 0x00000020U
5297 #define GPIO_LCKR_LCK6 0x00000040U
5298 #define GPIO_LCKR_LCK7 0x00000080U
5299 #define GPIO_LCKR_LCK8 0x00000100U
5300 #define GPIO_LCKR_LCK9 0x00000200U
5301 #define GPIO_LCKR_LCK10 0x00000400U
5302 #define GPIO_LCKR_LCK11 0x00000800U
5303 #define GPIO_LCKR_LCK12 0x00001000U
5304 #define GPIO_LCKR_LCK13 0x00002000U
5305 #define GPIO_LCKR_LCK14 0x00004000U
5306 #define GPIO_LCKR_LCK15 0x00008000U
5307 #define GPIO_LCKR_LCKK 0x00010000U
5308 
5309 
5310 /******************************************************************************/
5311 /* */
5312 /* Inter-integrated Circuit Interface (I2C) */
5313 /* */
5314 /******************************************************************************/
5315 /******************* Bit definition for I2C_CR1 register *******************/
5316 #define I2C_CR1_PE 0x00000001U
5317 #define I2C_CR1_TXIE 0x00000002U
5318 #define I2C_CR1_RXIE 0x00000004U
5319 #define I2C_CR1_ADDRIE 0x00000008U
5320 #define I2C_CR1_NACKIE 0x00000010U
5321 #define I2C_CR1_STOPIE 0x00000020U
5322 #define I2C_CR1_TCIE 0x00000040U
5323 #define I2C_CR1_ERRIE 0x00000080U
5324 #define I2C_CR1_DNF 0x00000F00U
5325 #define I2C_CR1_ANFOFF 0x00001000U
5326 #define I2C_CR1_TXDMAEN 0x00004000U
5327 #define I2C_CR1_RXDMAEN 0x00008000U
5328 #define I2C_CR1_SBC 0x00010000U
5329 #define I2C_CR1_NOSTRETCH 0x00020000U
5330 #define I2C_CR1_GCEN 0x00080000U
5331 #define I2C_CR1_SMBHEN 0x00100000U
5332 #define I2C_CR1_SMBDEN 0x00200000U
5333 #define I2C_CR1_ALERTEN 0x00400000U
5334 #define I2C_CR1_PECEN 0x00800000U
5337 /****************** Bit definition for I2C_CR2 register ********************/
5338 #define I2C_CR2_SADD 0x000003FFU
5339 #define I2C_CR2_RD_WRN 0x00000400U
5340 #define I2C_CR2_ADD10 0x00000800U
5341 #define I2C_CR2_HEAD10R 0x00001000U
5342 #define I2C_CR2_START 0x00002000U
5343 #define I2C_CR2_STOP 0x00004000U
5344 #define I2C_CR2_NACK 0x00008000U
5345 #define I2C_CR2_NBYTES 0x00FF0000U
5346 #define I2C_CR2_RELOAD 0x01000000U
5347 #define I2C_CR2_AUTOEND 0x02000000U
5348 #define I2C_CR2_PECBYTE 0x04000000U
5350 /******************* Bit definition for I2C_OAR1 register ******************/
5351 #define I2C_OAR1_OA1 0x000003FFU
5352 #define I2C_OAR1_OA1MODE 0x00000400U
5353 #define I2C_OAR1_OA1EN 0x00008000U
5355 /******************* Bit definition for I2C_OAR2 register ******************/
5356 #define I2C_OAR2_OA2 0x000000FEU
5357 #define I2C_OAR2_OA2MSK 0x00000700U
5358 #define I2C_OAR2_OA2NOMASK 0x00000000U
5359 #define I2C_OAR2_OA2MASK01 0x00000100U
5360 #define I2C_OAR2_OA2MASK02 0x00000200U
5361 #define I2C_OAR2_OA2MASK03 0x00000300U
5362 #define I2C_OAR2_OA2MASK04 0x00000400U
5363 #define I2C_OAR2_OA2MASK05 0x00000500U
5364 #define I2C_OAR2_OA2MASK06 0x00000600U
5365 #define I2C_OAR2_OA2MASK07 0x00000700U
5366 #define I2C_OAR2_OA2EN 0x00008000U
5368 /******************* Bit definition for I2C_TIMINGR register *******************/
5369 #define I2C_TIMINGR_SCLL 0x000000FFU
5370 #define I2C_TIMINGR_SCLH 0x0000FF00U
5371 #define I2C_TIMINGR_SDADEL 0x000F0000U
5372 #define I2C_TIMINGR_SCLDEL 0x00F00000U
5373 #define I2C_TIMINGR_PRESC 0xF0000000U
5375 /******************* Bit definition for I2C_TIMEOUTR register *******************/
5376 #define I2C_TIMEOUTR_TIMEOUTA 0x00000FFFU
5377 #define I2C_TIMEOUTR_TIDLE 0x00001000U
5378 #define I2C_TIMEOUTR_TIMOUTEN 0x00008000U
5379 #define I2C_TIMEOUTR_TIMEOUTB 0x0FFF0000U
5380 #define I2C_TIMEOUTR_TEXTEN 0x80000000U
5382 /****************** Bit definition for I2C_ISR register *********************/
5383 #define I2C_ISR_TXE 0x00000001U
5384 #define I2C_ISR_TXIS 0x00000002U
5385 #define I2C_ISR_RXNE 0x00000004U
5386 #define I2C_ISR_ADDR 0x00000008U
5387 #define I2C_ISR_NACKF 0x00000010U
5388 #define I2C_ISR_STOPF 0x00000020U
5389 #define I2C_ISR_TC 0x00000040U
5390 #define I2C_ISR_TCR 0x00000080U
5391 #define I2C_ISR_BERR 0x00000100U
5392 #define I2C_ISR_ARLO 0x00000200U
5393 #define I2C_ISR_OVR 0x00000400U
5394 #define I2C_ISR_PECERR 0x00000800U
5395 #define I2C_ISR_TIMEOUT 0x00001000U
5396 #define I2C_ISR_ALERT 0x00002000U
5397 #define I2C_ISR_BUSY 0x00008000U
5398 #define I2C_ISR_DIR 0x00010000U
5399 #define I2C_ISR_ADDCODE 0x00FE0000U
5401 /****************** Bit definition for I2C_ICR register *********************/
5402 #define I2C_ICR_ADDRCF 0x00000008U
5403 #define I2C_ICR_NACKCF 0x00000010U
5404 #define I2C_ICR_STOPCF 0x00000020U
5405 #define I2C_ICR_BERRCF 0x00000100U
5406 #define I2C_ICR_ARLOCF 0x00000200U
5407 #define I2C_ICR_OVRCF 0x00000400U
5408 #define I2C_ICR_PECCF 0x00000800U
5409 #define I2C_ICR_TIMOUTCF 0x00001000U
5410 #define I2C_ICR_ALERTCF 0x00002000U
5412 /****************** Bit definition for I2C_PECR register *********************/
5413 #define I2C_PECR_PEC 0x000000FFU
5415 /****************** Bit definition for I2C_RXDR register *********************/
5416 #define I2C_RXDR_RXDATA 0x000000FFU
5418 /****************** Bit definition for I2C_TXDR register *********************/
5419 #define I2C_TXDR_TXDATA 0x000000FFU
5422 /******************************************************************************/
5423 /* */
5424 /* Independent WATCHDOG */
5425 /* */
5426 /******************************************************************************/
5427 /******************* Bit definition for IWDG_KR register ********************/
5428 #define IWDG_KR_KEY 0xFFFFU
5430 /******************* Bit definition for IWDG_PR register ********************/
5431 #define IWDG_PR_PR 0x07U
5432 #define IWDG_PR_PR_0 0x01U
5433 #define IWDG_PR_PR_1 0x02U
5434 #define IWDG_PR_PR_2 0x04U
5436 /******************* Bit definition for IWDG_RLR register *******************/
5437 #define IWDG_RLR_RL 0x0FFFU
5439 /******************* Bit definition for IWDG_SR register ********************/
5440 #define IWDG_SR_PVU 0x01U
5441 #define IWDG_SR_RVU 0x02U
5442 #define IWDG_SR_WVU 0x04U
5444 /******************* Bit definition for IWDG_KR register ********************/
5445 #define IWDG_WINR_WIN 0x0FFFU
5447 /******************************************************************************/
5448 /* */
5449 /* LCD-TFT Display Controller (LTDC) */
5450 /* */
5451 /******************************************************************************/
5452 
5453 /******************** Bit definition for LTDC_SSCR register *****************/
5454 
5455 #define LTDC_SSCR_VSH 0x000007FFU
5456 #define LTDC_SSCR_HSW 0x0FFF0000U
5458 /******************** Bit definition for LTDC_BPCR register *****************/
5459 
5460 #define LTDC_BPCR_AVBP 0x000007FFU
5461 #define LTDC_BPCR_AHBP 0x0FFF0000U
5463 /******************** Bit definition for LTDC_AWCR register *****************/
5464 
5465 #define LTDC_AWCR_AAH 0x000007FFU
5466 #define LTDC_AWCR_AAW 0x0FFF0000U
5468 /******************** Bit definition for LTDC_TWCR register *****************/
5469 
5470 #define LTDC_TWCR_TOTALH 0x000007FFU
5471 #define LTDC_TWCR_TOTALW 0x0FFF0000U
5473 /******************** Bit definition for LTDC_GCR register ******************/
5474 
5475 #define LTDC_GCR_LTDCEN 0x00000001U
5476 #define LTDC_GCR_DBW 0x00000070U
5477 #define LTDC_GCR_DGW 0x00000700U
5478 #define LTDC_GCR_DRW 0x00007000U
5479 #define LTDC_GCR_DEN 0x00010000U
5480 #define LTDC_GCR_PCPOL 0x10000000U
5481 #define LTDC_GCR_DEPOL 0x20000000U
5482 #define LTDC_GCR_VSPOL 0x40000000U
5483 #define LTDC_GCR_HSPOL 0x80000000U
5486 /******************** Bit definition for LTDC_SRCR register *****************/
5487 
5488 #define LTDC_SRCR_IMR 0x00000001U
5489 #define LTDC_SRCR_VBR 0x00000002U
5491 /******************** Bit definition for LTDC_BCCR register *****************/
5492 
5493 #define LTDC_BCCR_BCBLUE 0x000000FFU
5494 #define LTDC_BCCR_BCGREEN 0x0000FF00U
5495 #define LTDC_BCCR_BCRED 0x00FF0000U
5497 /******************** Bit definition for LTDC_IER register ******************/
5498 
5499 #define LTDC_IER_LIE 0x00000001U
5500 #define LTDC_IER_FUIE 0x00000002U
5501 #define LTDC_IER_TERRIE 0x00000004U
5502 #define LTDC_IER_RRIE 0x00000008U
5504 /******************** Bit definition for LTDC_ISR register ******************/
5505 
5506 #define LTDC_ISR_LIF 0x00000001U
5507 #define LTDC_ISR_FUIF 0x00000002U
5508 #define LTDC_ISR_TERRIF 0x00000004U
5509 #define LTDC_ISR_RRIF 0x00000008U
5511 /******************** Bit definition for LTDC_ICR register ******************/
5512 
5513 #define LTDC_ICR_CLIF 0x00000001U
5514 #define LTDC_ICR_CFUIF 0x00000002U
5515 #define LTDC_ICR_CTERRIF 0x00000004U
5516 #define LTDC_ICR_CRRIF 0x00000008U
5518 /******************** Bit definition for LTDC_LIPCR register ****************/
5519 
5520 #define LTDC_LIPCR_LIPOS 0x000007FFU
5522 /******************** Bit definition for LTDC_CPSR register *****************/
5523 
5524 #define LTDC_CPSR_CYPOS 0x0000FFFFU
5525 #define LTDC_CPSR_CXPOS 0xFFFF0000U
5527 /******************** Bit definition for LTDC_CDSR register *****************/
5528 
5529 #define LTDC_CDSR_VDES 0x00000001U
5530 #define LTDC_CDSR_HDES 0x00000002U
5531 #define LTDC_CDSR_VSYNCS 0x00000004U
5532 #define LTDC_CDSR_HSYNCS 0x00000008U
5534 /******************** Bit definition for LTDC_LxCR register *****************/
5535 
5536 #define LTDC_LxCR_LEN 0x00000001U
5537 #define LTDC_LxCR_COLKEN 0x00000002U
5538 #define LTDC_LxCR_CLUTEN 0x00000010U
5540 /******************** Bit definition for LTDC_LxWHPCR register **************/
5541 
5542 #define LTDC_LxWHPCR_WHSTPOS 0x00000FFFU
5543 #define LTDC_LxWHPCR_WHSPPOS 0xFFFF0000U
5545 /******************** Bit definition for LTDC_LxWVPCR register **************/
5546 
5547 #define LTDC_LxWVPCR_WVSTPOS 0x00000FFFU
5548 #define LTDC_LxWVPCR_WVSPPOS 0xFFFF0000U
5550 /******************** Bit definition for LTDC_LxCKCR register ***************/
5551 
5552 #define LTDC_LxCKCR_CKBLUE 0x000000FFU
5553 #define LTDC_LxCKCR_CKGREEN 0x0000FF00U
5554 #define LTDC_LxCKCR_CKRED 0x00FF0000U
5556 /******************** Bit definition for LTDC_LxPFCR register ***************/
5557 
5558 #define LTDC_LxPFCR_PF 0x00000007U
5560 /******************** Bit definition for LTDC_LxCACR register ***************/
5561 
5562 #define LTDC_LxCACR_CONSTA 0x000000FFU
5564 /******************** Bit definition for LTDC_LxDCCR register ***************/
5565 
5566 #define LTDC_LxDCCR_DCBLUE 0x000000FFU
5567 #define LTDC_LxDCCR_DCGREEN 0x0000FF00U
5568 #define LTDC_LxDCCR_DCRED 0x00FF0000U
5569 #define LTDC_LxDCCR_DCALPHA 0xFF000000U
5571 /******************** Bit definition for LTDC_LxBFCR register ***************/
5572 
5573 #define LTDC_LxBFCR_BF2 0x00000007U
5574 #define LTDC_LxBFCR_BF1 0x00000700U
5576 /******************** Bit definition for LTDC_LxCFBAR register **************/
5577 
5578 #define LTDC_LxCFBAR_CFBADD 0xFFFFFFFFU
5580 /******************** Bit definition for LTDC_LxCFBLR register **************/
5581 
5582 #define LTDC_LxCFBLR_CFBLL 0x00001FFFU
5583 #define LTDC_LxCFBLR_CFBP 0x1FFF0000U
5585 /******************** Bit definition for LTDC_LxCFBLNR register *************/
5586 
5587 #define LTDC_LxCFBLNR_CFBLNBR 0x000007FFU
5589 /******************** Bit definition for LTDC_LxCLUTWR register *************/
5590 
5591 #define LTDC_LxCLUTWR_BLUE 0x000000FFU
5592 #define LTDC_LxCLUTWR_GREEN 0x0000FF00U
5593 #define LTDC_LxCLUTWR_RED 0x00FF0000U
5594 #define LTDC_LxCLUTWR_CLUTADD 0xFF000000U
5596 /******************************************************************************/
5597 /* */
5598 /* Power Control */
5599 /* */
5600 /******************************************************************************/
5601 /******************** Bit definition for PWR_CR1 register ********************/
5602 #define PWR_CR1_LPDS 0x00000001U
5603 #define PWR_CR1_PDDS 0x00000002U
5604 #define PWR_CR1_CSBF 0x00000008U
5605 #define PWR_CR1_PVDE 0x00000010U
5606 #define PWR_CR1_PLS 0x000000E0U
5607 #define PWR_CR1_PLS_0 0x00000020U
5608 #define PWR_CR1_PLS_1 0x00000040U
5609 #define PWR_CR1_PLS_2 0x00000080U
5612 #define PWR_CR1_PLS_LEV0 0x00000000U
5613 #define PWR_CR1_PLS_LEV1 0x00000020U
5614 #define PWR_CR1_PLS_LEV2 0x00000040U
5615 #define PWR_CR1_PLS_LEV3 0x00000060U
5616 #define PWR_CR1_PLS_LEV4 0x00000080U
5617 #define PWR_CR1_PLS_LEV5 0x000000A0U
5618 #define PWR_CR1_PLS_LEV6 0x000000C0U
5619 #define PWR_CR1_PLS_LEV7 0x000000E0U
5620 #define PWR_CR1_DBP 0x00000100U
5621 #define PWR_CR1_FPDS 0x00000200U
5622 #define PWR_CR1_LPUDS 0x00000400U
5623 #define PWR_CR1_MRUDS 0x00000800U
5624 #define PWR_CR1_ADCDC1 0x00002000U
5625 #define PWR_CR1_VOS 0x0000C000U
5626 #define PWR_CR1_VOS_0 0x00004000U
5627 #define PWR_CR1_VOS_1 0x00008000U
5628 #define PWR_CR1_ODEN 0x00010000U
5629 #define PWR_CR1_ODSWEN 0x00020000U
5630 #define PWR_CR1_UDEN 0x000C0000U
5631 #define PWR_CR1_UDEN_0 0x00040000U
5632 #define PWR_CR1_UDEN_1 0x00080000U
5634 /******************* Bit definition for PWR_CSR1 register ********************/
5635 #define PWR_CSR1_WUIF 0x00000001U
5636 #define PWR_CSR1_SBF 0x00000002U
5637 #define PWR_CSR1_PVDO 0x00000004U
5638 #define PWR_CSR1_BRR 0x00000008U
5639 #define PWR_CSR1_EIWUP 0x00000100U
5640 #define PWR_CSR1_BRE 0x00000200U
5641 #define PWR_CSR1_VOSRDY 0x00004000U
5642 #define PWR_CSR1_ODRDY 0x00010000U
5643 #define PWR_CSR1_ODSWRDY 0x00020000U
5644 #define PWR_CSR1_UDRDY 0x000C0000U
5647 /******************** Bit definition for PWR_CR2 register ********************/
5648 #define PWR_CR2_CWUPF1 0x00000001U
5649 #define PWR_CR2_CWUPF2 0x00000002U
5650 #define PWR_CR2_CWUPF3 0x00000004U
5651 #define PWR_CR2_CWUPF4 0x00000008U
5652 #define PWR_CR2_CWUPF5 0x00000010U
5653 #define PWR_CR2_CWUPF6 0x00000020U
5654 #define PWR_CR2_WUPP1 0x00000100U
5655 #define PWR_CR2_WUPP2 0x00000200U
5656 #define PWR_CR2_WUPP3 0x00000400U
5657 #define PWR_CR2_WUPP4 0x00000800U
5658 #define PWR_CR2_WUPP5 0x00001000U
5659 #define PWR_CR2_WUPP6 0x00002000U
5661 /******************* Bit definition for PWR_CSR2 register ********************/
5662 #define PWR_CSR2_WUPF1 0x00000001U
5663 #define PWR_CSR2_WUPF2 0x00000002U
5664 #define PWR_CSR2_WUPF3 0x00000004U
5665 #define PWR_CSR2_WUPF4 0x00000008U
5666 #define PWR_CSR2_WUPF5 0x00000010U
5667 #define PWR_CSR2_WUPF6 0x00000020U
5668 #define PWR_CSR2_EWUP1 0x00000100U
5669 #define PWR_CSR2_EWUP2 0x00000200U
5670 #define PWR_CSR2_EWUP3 0x00000400U
5671 #define PWR_CSR2_EWUP4 0x00000800U
5672 #define PWR_CSR2_EWUP5 0x00001000U
5673 #define PWR_CSR2_EWUP6 0x00002000U
5675 /******************************************************************************/
5676 /* */
5677 /* QUADSPI */
5678 /* */
5679 /******************************************************************************/
5680 /***************** Bit definition for QUADSPI_CR register *******************/
5681 #define QUADSPI_CR_EN 0x00000001U
5682 #define QUADSPI_CR_ABORT 0x00000002U
5683 #define QUADSPI_CR_DMAEN 0x00000004U
5684 #define QUADSPI_CR_TCEN 0x00000008U
5685 #define QUADSPI_CR_SSHIFT 0x00000010U
5686 #define QUADSPI_CR_DFM 0x00000040U
5687 #define QUADSPI_CR_FSEL 0x00000080U
5688 #define QUADSPI_CR_FTHRES 0x00001F00U
5689 #define QUADSPI_CR_FTHRES_0 0x00000100U
5690 #define QUADSPI_CR_FTHRES_1 0x00000200U
5691 #define QUADSPI_CR_FTHRES_2 0x00000400U
5692 #define QUADSPI_CR_FTHRES_3 0x00000800U
5693 #define QUADSPI_CR_FTHRES_4 0x00001000U
5694 #define QUADSPI_CR_TEIE 0x00010000U
5695 #define QUADSPI_CR_TCIE 0x00020000U
5696 #define QUADSPI_CR_FTIE 0x00040000U
5697 #define QUADSPI_CR_SMIE 0x00080000U
5698 #define QUADSPI_CR_TOIE 0x00100000U
5699 #define QUADSPI_CR_APMS 0x00400000U
5700 #define QUADSPI_CR_PMM 0x00800000U
5701 #define QUADSPI_CR_PRESCALER 0xFF000000U
5702 #define QUADSPI_CR_PRESCALER_0 0x01000000U
5703 #define QUADSPI_CR_PRESCALER_1 0x02000000U
5704 #define QUADSPI_CR_PRESCALER_2 0x04000000U
5705 #define QUADSPI_CR_PRESCALER_3 0x08000000U
5706 #define QUADSPI_CR_PRESCALER_4 0x10000000U
5707 #define QUADSPI_CR_PRESCALER_5 0x20000000U
5708 #define QUADSPI_CR_PRESCALER_6 0x40000000U
5709 #define QUADSPI_CR_PRESCALER_7 0x80000000U
5711 /***************** Bit definition for QUADSPI_DCR register ******************/
5712 #define QUADSPI_DCR_CKMODE 0x00000001U
5713 #define QUADSPI_DCR_CSHT 0x00000700U
5714 #define QUADSPI_DCR_CSHT_0 0x00000100U
5715 #define QUADSPI_DCR_CSHT_1 0x00000200U
5716 #define QUADSPI_DCR_CSHT_2 0x00000400U
5717 #define QUADSPI_DCR_FSIZE 0x001F0000U
5718 #define QUADSPI_DCR_FSIZE_0 0x00010000U
5719 #define QUADSPI_DCR_FSIZE_1 0x00020000U
5720 #define QUADSPI_DCR_FSIZE_2 0x00040000U
5721 #define QUADSPI_DCR_FSIZE_3 0x00080000U
5722 #define QUADSPI_DCR_FSIZE_4 0x00100000U
5724 /****************** Bit definition for QUADSPI_SR register *******************/
5725 #define QUADSPI_SR_TEF 0x00000001U
5726 #define QUADSPI_SR_TCF 0x00000002U
5727 #define QUADSPI_SR_FTF 0x00000004U
5728 #define QUADSPI_SR_SMF 0x00000008U
5729 #define QUADSPI_SR_TOF 0x00000010U
5730 #define QUADSPI_SR_BUSY 0x00000020U
5731 #define QUADSPI_SR_FLEVEL 0x00001F00U
5732 #define QUADSPI_SR_FLEVEL_0 0x00000100U
5733 #define QUADSPI_SR_FLEVEL_1 0x00000200U
5734 #define QUADSPI_SR_FLEVEL_2 0x00000400U
5735 #define QUADSPI_SR_FLEVEL_3 0x00000800U
5736 #define QUADSPI_SR_FLEVEL_4 0x00001000U
5738 /****************** Bit definition for QUADSPI_FCR register ******************/
5739 #define QUADSPI_FCR_CTEF 0x00000001U
5740 #define QUADSPI_FCR_CTCF 0x00000002U
5741 #define QUADSPI_FCR_CSMF 0x00000008U
5742 #define QUADSPI_FCR_CTOF 0x00000010U
5744 /****************** Bit definition for QUADSPI_DLR register ******************/
5745 #define QUADSPI_DLR_DL 0xFFFFFFFFU
5747 /****************** Bit definition for QUADSPI_CCR register ******************/
5748 #define QUADSPI_CCR_INSTRUCTION 0x000000FFU
5749 #define QUADSPI_CCR_INSTRUCTION_0 0x00000001U
5750 #define QUADSPI_CCR_INSTRUCTION_1 0x00000002U
5751 #define QUADSPI_CCR_INSTRUCTION_2 0x00000004U
5752 #define QUADSPI_CCR_INSTRUCTION_3 0x00000008U
5753 #define QUADSPI_CCR_INSTRUCTION_4 0x00000010U
5754 #define QUADSPI_CCR_INSTRUCTION_5 0x00000020U
5755 #define QUADSPI_CCR_INSTRUCTION_6 0x00000040U
5756 #define QUADSPI_CCR_INSTRUCTION_7 0x00000080U
5757 #define QUADSPI_CCR_IMODE 0x00000300U
5758 #define QUADSPI_CCR_IMODE_0 0x00000100U
5759 #define QUADSPI_CCR_IMODE_1 0x00000200U
5760 #define QUADSPI_CCR_ADMODE 0x00000C00U
5761 #define QUADSPI_CCR_ADMODE_0 0x00000400U
5762 #define QUADSPI_CCR_ADMODE_1 0x00000800U
5763 #define QUADSPI_CCR_ADSIZE 0x00003000U
5764 #define QUADSPI_CCR_ADSIZE_0 0x00001000U
5765 #define QUADSPI_CCR_ADSIZE_1 0x00002000U
5766 #define QUADSPI_CCR_ABMODE 0x0000C000U
5767 #define QUADSPI_CCR_ABMODE_0 0x00004000U
5768 #define QUADSPI_CCR_ABMODE_1 0x00008000U
5769 #define QUADSPI_CCR_ABSIZE 0x00030000U
5770 #define QUADSPI_CCR_ABSIZE_0 0x00010000U
5771 #define QUADSPI_CCR_ABSIZE_1 0x00020000U
5772 #define QUADSPI_CCR_DCYC 0x007C0000U
5773 #define QUADSPI_CCR_DCYC_0 0x00040000U
5774 #define QUADSPI_CCR_DCYC_1 0x00080000U
5775 #define QUADSPI_CCR_DCYC_2 0x00100000U
5776 #define QUADSPI_CCR_DCYC_3 0x00200000U
5777 #define QUADSPI_CCR_DCYC_4 0x00400000U
5778 #define QUADSPI_CCR_DMODE 0x03000000U
5779 #define QUADSPI_CCR_DMODE_0 0x01000000U
5780 #define QUADSPI_CCR_DMODE_1 0x02000000U
5781 #define QUADSPI_CCR_FMODE 0x0C000000U
5782 #define QUADSPI_CCR_FMODE_0 0x04000000U
5783 #define QUADSPI_CCR_FMODE_1 0x08000000U
5784 #define QUADSPI_CCR_SIOO 0x10000000U
5785 #define QUADSPI_CCR_DHHC 0x40000000U
5786 #define QUADSPI_CCR_DDRM 0x80000000U
5787 /****************** Bit definition for QUADSPI_AR register *******************/
5788 #define QUADSPI_AR_ADDRESS 0xFFFFFFFFU
5790 /****************** Bit definition for QUADSPI_ABR register ******************/
5791 #define QUADSPI_ABR_ALTERNATE 0xFFFFFFFFU
5793 /****************** Bit definition for QUADSPI_DR register *******************/
5794 #define QUADSPI_DR_DATA 0xFFFFFFFFU
5796 /****************** Bit definition for QUADSPI_PSMKR register ****************/
5797 #define QUADSPI_PSMKR_MASK 0xFFFFFFFFU
5799 /****************** Bit definition for QUADSPI_PSMAR register ****************/
5800 #define QUADSPI_PSMAR_MATCH 0xFFFFFFFFU
5802 /****************** Bit definition for QUADSPI_PIR register *****************/
5803 #define QUADSPI_PIR_INTERVAL 0x0000FFFFU
5805 /****************** Bit definition for QUADSPI_LPTR register *****************/
5806 #define QUADSPI_LPTR_TIMEOUT 0x0000FFFFU
5808 /******************************************************************************/
5809 /* */
5810 /* Reset and Clock Control */
5811 /* */
5812 /******************************************************************************/
5813 /******************** Bit definition for RCC_CR register ********************/
5814 #define RCC_CR_HSION 0x00000001U
5815 #define RCC_CR_HSIRDY 0x00000002U
5816 #define RCC_CR_HSITRIM 0x000000F8U
5817 #define RCC_CR_HSITRIM_0 0x00000008U
5818 #define RCC_CR_HSITRIM_1 0x00000010U
5819 #define RCC_CR_HSITRIM_2 0x00000020U
5820 #define RCC_CR_HSITRIM_3 0x00000040U
5821 #define RCC_CR_HSITRIM_4 0x00000080U
5822 #define RCC_CR_HSICAL 0x0000FF00U
5823 #define RCC_CR_HSICAL_0 0x00000100U
5824 #define RCC_CR_HSICAL_1 0x00000200U
5825 #define RCC_CR_HSICAL_2 0x00000400U
5826 #define RCC_CR_HSICAL_3 0x00000800U
5827 #define RCC_CR_HSICAL_4 0x00001000U
5828 #define RCC_CR_HSICAL_5 0x00002000U
5829 #define RCC_CR_HSICAL_6 0x00004000U
5830 #define RCC_CR_HSICAL_7 0x00008000U
5831 #define RCC_CR_HSEON 0x00010000U
5832 #define RCC_CR_HSERDY 0x00020000U
5833 #define RCC_CR_HSEBYP 0x00040000U
5834 #define RCC_CR_CSSON 0x00080000U
5835 #define RCC_CR_PLLON 0x01000000U
5836 #define RCC_CR_PLLRDY 0x02000000U
5837 #define RCC_CR_PLLI2SON 0x04000000U
5838 #define RCC_CR_PLLI2SRDY 0x08000000U
5839 #define RCC_CR_PLLSAION 0x10000000U
5840 #define RCC_CR_PLLSAIRDY 0x20000000U
5841 
5842 /******************** Bit definition for RCC_PLLCFGR register ***************/
5843 #define RCC_PLLCFGR_PLLM 0x0000003FU
5844 #define RCC_PLLCFGR_PLLM_0 0x00000001U
5845 #define RCC_PLLCFGR_PLLM_1 0x00000002U
5846 #define RCC_PLLCFGR_PLLM_2 0x00000004U
5847 #define RCC_PLLCFGR_PLLM_3 0x00000008U
5848 #define RCC_PLLCFGR_PLLM_4 0x00000010U
5849 #define RCC_PLLCFGR_PLLM_5 0x00000020U
5850 #define RCC_PLLCFGR_PLLN 0x00007FC0U
5851 #define RCC_PLLCFGR_PLLN_0 0x00000040U
5852 #define RCC_PLLCFGR_PLLN_1 0x00000080U
5853 #define RCC_PLLCFGR_PLLN_2 0x00000100U
5854 #define RCC_PLLCFGR_PLLN_3 0x00000200U
5855 #define RCC_PLLCFGR_PLLN_4 0x00000400U
5856 #define RCC_PLLCFGR_PLLN_5 0x00000800U
5857 #define RCC_PLLCFGR_PLLN_6 0x00001000U
5858 #define RCC_PLLCFGR_PLLN_7 0x00002000U
5859 #define RCC_PLLCFGR_PLLN_8 0x00004000U
5860 #define RCC_PLLCFGR_PLLP 0x00030000U
5861 #define RCC_PLLCFGR_PLLP_0 0x00010000U
5862 #define RCC_PLLCFGR_PLLP_1 0x00020000U
5863 #define RCC_PLLCFGR_PLLSRC 0x00400000U
5864 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
5865 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
5866 #define RCC_PLLCFGR_PLLQ 0x0F000000U
5867 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
5868 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
5869 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
5870 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
5871 
5872 #define RCC_PLLCFGR_PLLR 0x70000000U
5873 #define RCC_PLLCFGR_PLLR_0 0x10000000U
5874 #define RCC_PLLCFGR_PLLR_1 0x20000000U
5875 #define RCC_PLLCFGR_PLLR_2 0x40000000U
5876 
5877 /******************** Bit definition for RCC_CFGR register ******************/
5879 #define RCC_CFGR_SW 0x00000003U
5880 #define RCC_CFGR_SW_0 0x00000001U
5881 #define RCC_CFGR_SW_1 0x00000002U
5882 #define RCC_CFGR_SW_HSI 0x00000000U
5883 #define RCC_CFGR_SW_HSE 0x00000001U
5884 #define RCC_CFGR_SW_PLL 0x00000002U
5887 #define RCC_CFGR_SWS 0x0000000CU
5888 #define RCC_CFGR_SWS_0 0x00000004U
5889 #define RCC_CFGR_SWS_1 0x00000008U
5890 #define RCC_CFGR_SWS_HSI 0x00000000U
5891 #define RCC_CFGR_SWS_HSE 0x00000004U
5892 #define RCC_CFGR_SWS_PLL 0x00000008U
5895 #define RCC_CFGR_HPRE 0x000000F0U
5896 #define RCC_CFGR_HPRE_0 0x00000010U
5897 #define RCC_CFGR_HPRE_1 0x00000020U
5898 #define RCC_CFGR_HPRE_2 0x00000040U
5899 #define RCC_CFGR_HPRE_3 0x00000080U
5901 #define RCC_CFGR_HPRE_DIV1 0x00000000U
5902 #define RCC_CFGR_HPRE_DIV2 0x00000080U
5903 #define RCC_CFGR_HPRE_DIV4 0x00000090U
5904 #define RCC_CFGR_HPRE_DIV8 0x000000A0U
5905 #define RCC_CFGR_HPRE_DIV16 0x000000B0U
5906 #define RCC_CFGR_HPRE_DIV64 0x000000C0U
5907 #define RCC_CFGR_HPRE_DIV128 0x000000D0U
5908 #define RCC_CFGR_HPRE_DIV256 0x000000E0U
5909 #define RCC_CFGR_HPRE_DIV512 0x000000F0U
5912 #define RCC_CFGR_PPRE1 0x00001C00U
5913 #define RCC_CFGR_PPRE1_0 0x00000400U
5914 #define RCC_CFGR_PPRE1_1 0x00000800U
5915 #define RCC_CFGR_PPRE1_2 0x00001000U
5917 #define RCC_CFGR_PPRE1_DIV1 0x00000000U
5918 #define RCC_CFGR_PPRE1_DIV2 0x00001000U
5919 #define RCC_CFGR_PPRE1_DIV4 0x00001400U
5920 #define RCC_CFGR_PPRE1_DIV8 0x00001800U
5921 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U
5924 #define RCC_CFGR_PPRE2 0x0000E000U
5925 #define RCC_CFGR_PPRE2_0 0x00002000U
5926 #define RCC_CFGR_PPRE2_1 0x00004000U
5927 #define RCC_CFGR_PPRE2_2 0x00008000U
5929 #define RCC_CFGR_PPRE2_DIV1 0x00000000U
5930 #define RCC_CFGR_PPRE2_DIV2 0x00008000U
5931 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U
5932 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U
5933 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U
5936 #define RCC_CFGR_RTCPRE 0x001F0000U
5937 #define RCC_CFGR_RTCPRE_0 0x00010000U
5938 #define RCC_CFGR_RTCPRE_1 0x00020000U
5939 #define RCC_CFGR_RTCPRE_2 0x00040000U
5940 #define RCC_CFGR_RTCPRE_3 0x00080000U
5941 #define RCC_CFGR_RTCPRE_4 0x00100000U
5942 
5944 #define RCC_CFGR_MCO1 0x00600000U
5945 #define RCC_CFGR_MCO1_0 0x00200000U
5946 #define RCC_CFGR_MCO1_1 0x00400000U
5947 
5948 #define RCC_CFGR_I2SSRC 0x00800000U
5949 
5950 #define RCC_CFGR_MCO1PRE 0x07000000U
5951 #define RCC_CFGR_MCO1PRE_0 0x01000000U
5952 #define RCC_CFGR_MCO1PRE_1 0x02000000U
5953 #define RCC_CFGR_MCO1PRE_2 0x04000000U
5954 
5955 #define RCC_CFGR_MCO2PRE 0x38000000U
5956 #define RCC_CFGR_MCO2PRE_0 0x08000000U
5957 #define RCC_CFGR_MCO2PRE_1 0x10000000U
5958 #define RCC_CFGR_MCO2PRE_2 0x20000000U
5959 
5960 #define RCC_CFGR_MCO2 0xC0000000U
5961 #define RCC_CFGR_MCO2_0 0x40000000U
5962 #define RCC_CFGR_MCO2_1 0x80000000U
5963 
5964 /******************** Bit definition for RCC_CIR register *******************/
5965 #define RCC_CIR_LSIRDYF 0x00000001U
5966 #define RCC_CIR_LSERDYF 0x00000002U
5967 #define RCC_CIR_HSIRDYF 0x00000004U
5968 #define RCC_CIR_HSERDYF 0x00000008U
5969 #define RCC_CIR_PLLRDYF 0x00000010U
5970 #define RCC_CIR_PLLI2SRDYF 0x00000020U
5971 #define RCC_CIR_PLLSAIRDYF 0x00000040U
5972 #define RCC_CIR_CSSF 0x00000080U
5973 #define RCC_CIR_LSIRDYIE 0x00000100U
5974 #define RCC_CIR_LSERDYIE 0x00000200U
5975 #define RCC_CIR_HSIRDYIE 0x00000400U
5976 #define RCC_CIR_HSERDYIE 0x00000800U
5977 #define RCC_CIR_PLLRDYIE 0x00001000U
5978 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
5979 #define RCC_CIR_PLLSAIRDYIE 0x00004000U
5980 #define RCC_CIR_LSIRDYC 0x00010000U
5981 #define RCC_CIR_LSERDYC 0x00020000U
5982 #define RCC_CIR_HSIRDYC 0x00040000U
5983 #define RCC_CIR_HSERDYC 0x00080000U
5984 #define RCC_CIR_PLLRDYC 0x00100000U
5985 #define RCC_CIR_PLLI2SRDYC 0x00200000U
5986 #define RCC_CIR_PLLSAIRDYC 0x00400000U
5987 #define RCC_CIR_CSSC 0x00800000U
5988 
5989 /******************** Bit definition for RCC_AHB1RSTR register **************/
5990 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
5991 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
5992 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
5993 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
5994 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
5995 #define RCC_AHB1RSTR_GPIOFRST 0x00000020U
5996 #define RCC_AHB1RSTR_GPIOGRST 0x00000040U
5997 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
5998 #define RCC_AHB1RSTR_GPIOIRST 0x00000100U
5999 #define RCC_AHB1RSTR_GPIOJRST 0x00000200U
6000 #define RCC_AHB1RSTR_GPIOKRST 0x00000400U
6001 #define RCC_AHB1RSTR_CRCRST 0x00001000U
6002 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
6003 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
6004 #define RCC_AHB1RSTR_DMA2DRST 0x00800000U
6005 #define RCC_AHB1RSTR_ETHMACRST 0x02000000U
6006 #define RCC_AHB1RSTR_OTGHRST 0x20000000U
6007 
6008 /******************** Bit definition for RCC_AHB2RSTR register **************/
6009 #define RCC_AHB2RSTR_DCMIRST 0x00000001U
6010 #define RCC_AHB2RSTR_JPEGRST 0x00000002U
6011 #define RCC_AHB2RSTR_RNGRST 0x00000040U
6012 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
6013 
6014 /******************** Bit definition for RCC_AHB3RSTR register **************/
6015 
6016 #define RCC_AHB3RSTR_FMCRST 0x00000001U
6017 #define RCC_AHB3RSTR_QSPIRST 0x00000002U
6018 
6019 /******************** Bit definition for RCC_APB1RSTR register **************/
6020 #define RCC_APB1RSTR_TIM2RST 0x00000001U
6021 #define RCC_APB1RSTR_TIM3RST 0x00000002U
6022 #define RCC_APB1RSTR_TIM4RST 0x00000004U
6023 #define RCC_APB1RSTR_TIM5RST 0x00000008U
6024 #define RCC_APB1RSTR_TIM6RST 0x00000010U
6025 #define RCC_APB1RSTR_TIM7RST 0x00000020U
6026 #define RCC_APB1RSTR_TIM12RST 0x00000040U
6027 #define RCC_APB1RSTR_TIM13RST 0x00000080U
6028 #define RCC_APB1RSTR_TIM14RST 0x00000100U
6029 #define RCC_APB1RSTR_LPTIM1RST 0x00000200U
6030 #define RCC_APB1RSTR_WWDGRST 0x00000800U
6031 #define RCC_APB1RSTR_CAN3RST 0x00002000U
6032 #define RCC_APB1RSTR_SPI2RST 0x00004000U
6033 #define RCC_APB1RSTR_SPI3RST 0x00008000U
6034 #define RCC_APB1RSTR_SPDIFRXRST 0x00010000U
6035 #define RCC_APB1RSTR_USART2RST 0x00020000U
6036 #define RCC_APB1RSTR_USART3RST 0x00040000U
6037 #define RCC_APB1RSTR_UART4RST 0x00080000U
6038 #define RCC_APB1RSTR_UART5RST 0x00100000U
6039 #define RCC_APB1RSTR_I2C1RST 0x00200000U
6040 #define RCC_APB1RSTR_I2C2RST 0x00400000U
6041 #define RCC_APB1RSTR_I2C3RST 0x00800000U
6042 #define RCC_APB1RSTR_I2C4RST 0x01000000U
6043 #define RCC_APB1RSTR_CAN1RST 0x02000000U
6044 #define RCC_APB1RSTR_CAN2RST 0x04000000U
6045 #define RCC_APB1RSTR_CECRST 0x08000000U
6046 #define RCC_APB1RSTR_PWRRST 0x10000000U
6047 #define RCC_APB1RSTR_DACRST 0x20000000U
6048 #define RCC_APB1RSTR_UART7RST 0x40000000U
6049 #define RCC_APB1RSTR_UART8RST 0x80000000U
6050 
6051 /******************** Bit definition for RCC_APB2RSTR register **************/
6052 #define RCC_APB2RSTR_TIM1RST 0x00000001U
6053 #define RCC_APB2RSTR_TIM8RST 0x00000002U
6054 #define RCC_APB2RSTR_USART1RST 0x00000010U
6055 #define RCC_APB2RSTR_USART6RST 0x00000020U
6056 #define RCC_APB2RSTR_SDMMC2RST 0x00000080U
6057 #define RCC_APB2RSTR_ADCRST 0x00000100U
6058 #define RCC_APB2RSTR_SDMMC1RST 0x00000800U
6059 #define RCC_APB2RSTR_SPI1RST 0x00001000U
6060 #define RCC_APB2RSTR_SPI4RST 0x00002000U
6061 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
6062 #define RCC_APB2RSTR_TIM9RST 0x00010000U
6063 #define RCC_APB2RSTR_TIM10RST 0x00020000U
6064 #define RCC_APB2RSTR_TIM11RST 0x00040000U
6065 #define RCC_APB2RSTR_SPI5RST 0x00100000U
6066 #define RCC_APB2RSTR_SPI6RST 0x00200000U
6067 #define RCC_APB2RSTR_SAI1RST 0x00400000U
6068 #define RCC_APB2RSTR_SAI2RST 0x00800000U
6069 #define RCC_APB2RSTR_LTDCRST 0x04000000U
6070 #define RCC_APB2RSTR_DSIRST 0x08000000U
6071 #define RCC_APB2RSTR_DFSDM1RST 0x20000000U
6072 #define RCC_APB2RSTR_MDIORST 0x40000000U
6073 
6074 /******************** Bit definition for RCC_AHB1ENR register ***************/
6075 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
6076 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
6077 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
6078 #define RCC_AHB1ENR_GPIODEN 0x00000008U
6079 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
6080 #define RCC_AHB1ENR_GPIOFEN 0x00000020U
6081 #define RCC_AHB1ENR_GPIOGEN 0x00000040U
6082 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
6083 #define RCC_AHB1ENR_GPIOIEN 0x00000100U
6084 #define RCC_AHB1ENR_GPIOJEN 0x00000200U
6085 #define RCC_AHB1ENR_GPIOKEN 0x00000400U
6086 #define RCC_AHB1ENR_CRCEN 0x00001000U
6087 #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
6088 #define RCC_AHB1ENR_DTCMRAMEN 0x00100000U
6089 #define RCC_AHB1ENR_DMA1EN 0x00200000U
6090 #define RCC_AHB1ENR_DMA2EN 0x00400000U
6091 #define RCC_AHB1ENR_DMA2DEN 0x00800000U
6092 #define RCC_AHB1ENR_ETHMACEN 0x02000000U
6093 #define RCC_AHB1ENR_ETHMACTXEN 0x04000000U
6094 #define RCC_AHB1ENR_ETHMACRXEN 0x08000000U
6095 #define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U
6096 #define RCC_AHB1ENR_OTGHSEN 0x20000000U
6097 #define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
6098 
6099 /******************** Bit definition for RCC_AHB2ENR register ***************/
6100 #define RCC_AHB2ENR_DCMIEN 0x00000001U
6101 #define RCC_AHB2ENR_JPEGEN 0x00000002U
6102 #define RCC_AHB2ENR_RNGEN 0x00000040U
6103 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
6104 
6105 /******************** Bit definition for RCC_AHB3ENR register ***************/
6106 #define RCC_AHB3ENR_FMCEN 0x00000001U
6107 #define RCC_AHB3ENR_QSPIEN 0x00000002U
6108 
6109 /******************** Bit definition for RCC_APB1ENR register ***************/
6110 #define RCC_APB1ENR_TIM2EN 0x00000001U
6111 #define RCC_APB1ENR_TIM3EN 0x00000002U
6112 #define RCC_APB1ENR_TIM4EN 0x00000004U
6113 #define RCC_APB1ENR_TIM5EN 0x00000008U
6114 #define RCC_APB1ENR_TIM6EN 0x00000010U
6115 #define RCC_APB1ENR_TIM7EN 0x00000020U
6116 #define RCC_APB1ENR_TIM12EN 0x00000040U
6117 #define RCC_APB1ENR_TIM13EN 0x00000080U
6118 #define RCC_APB1ENR_TIM14EN 0x00000100U
6119 #define RCC_APB1ENR_LPTIM1EN 0x00000200U
6120 #define RCC_APB1ENR_RTCEN 0x00000400U
6121 #define RCC_APB1ENR_WWDGEN 0x00000800U
6122 #define RCC_APB1ENR_CAN3EN 0x00002000U
6123 #define RCC_APB1ENR_SPI2EN 0x00004000U
6124 #define RCC_APB1ENR_SPI3EN 0x00008000U
6125 #define RCC_APB1ENR_SPDIFRXEN 0x00010000U
6126 #define RCC_APB1ENR_USART2EN 0x00020000U
6127 #define RCC_APB1ENR_USART3EN 0x00040000U
6128 #define RCC_APB1ENR_UART4EN 0x00080000U
6129 #define RCC_APB1ENR_UART5EN 0x00100000U
6130 #define RCC_APB1ENR_I2C1EN 0x00200000U
6131 #define RCC_APB1ENR_I2C2EN 0x00400000U
6132 #define RCC_APB1ENR_I2C3EN 0x00800000U
6133 #define RCC_APB1ENR_I2C4EN 0x01000000U
6134 #define RCC_APB1ENR_CAN1EN 0x02000000U
6135 #define RCC_APB1ENR_CAN2EN 0x04000000U
6136 #define RCC_APB1ENR_CECEN 0x08000000U
6137 #define RCC_APB1ENR_PWREN 0x10000000U
6138 #define RCC_APB1ENR_DACEN 0x20000000U
6139 #define RCC_APB1ENR_UART7EN 0x40000000U
6140 #define RCC_APB1ENR_UART8EN 0x80000000U
6141 
6142 /******************** Bit definition for RCC_APB2ENR register ***************/
6143 #define RCC_APB2ENR_TIM1EN 0x00000001U
6144 #define RCC_APB2ENR_TIM8EN 0x00000002U
6145 #define RCC_APB2ENR_USART1EN 0x00000010U
6146 #define RCC_APB2ENR_USART6EN 0x00000020U
6147 #define RCC_APB2ENR_SDMMC2EN 0x00000080U
6148 #define RCC_APB2ENR_ADC1EN 0x00000100U
6149 #define RCC_APB2ENR_ADC2EN 0x00000200U
6150 #define RCC_APB2ENR_ADC3EN 0x00000400U
6151 #define RCC_APB2ENR_SDMMC1EN 0x00000800U
6152 #define RCC_APB2ENR_SPI1EN 0x00001000U
6153 #define RCC_APB2ENR_SPI4EN 0x00002000U
6154 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
6155 #define RCC_APB2ENR_TIM9EN 0x00010000U
6156 #define RCC_APB2ENR_TIM10EN 0x00020000U
6157 #define RCC_APB2ENR_TIM11EN 0x00040000U
6158 #define RCC_APB2ENR_SPI5EN 0x00100000U
6159 #define RCC_APB2ENR_SPI6EN 0x00200000U
6160 #define RCC_APB2ENR_SAI1EN 0x00400000U
6161 #define RCC_APB2ENR_SAI2EN 0x00800000U
6162 #define RCC_APB2ENR_LTDCEN 0x04000000U
6163 #define RCC_APB2ENR_DSIEN 0x08000000U
6164 #define RCC_APB2ENR_DFSDM1EN 0x20000000U
6165 #define RCC_APB2ENR_MDIOEN 0x40000000U
6166 
6167 /******************** Bit definition for RCC_AHB1LPENR register *************/
6168 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
6169 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
6170 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
6171 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
6172 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
6173 #define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
6174 #define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
6175 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
6176 #define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
6177 #define RCC_AHB1LPENR_GPIOJLPEN 0x00000200U
6178 #define RCC_AHB1LPENR_GPIOKLPEN 0x00000400U
6179 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
6180 #define RCC_AHB1LPENR_AXILPEN 0x00002000U
6181 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
6182 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
6183 #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
6184 #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
6185 #define RCC_AHB1LPENR_DTCMLPEN 0x00100000U
6186 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
6187 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
6188 #define RCC_AHB1LPENR_DMA2DLPEN 0x00800000U
6189 #define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U
6190 #define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U
6191 #define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U
6192 #define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U
6193 #define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
6194 #define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
6195 
6196 /******************** Bit definition for RCC_AHB2LPENR register *************/
6197 #define RCC_AHB2LPENR_DCMILPEN 0x00000001U
6198 #define RCC_AHB2LPENR_JPEGLPEN 0x00000002U
6199 #define RCC_AHB2LPENR_RNGLPEN 0x00000040U
6200 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
6201 
6202 /******************** Bit definition for RCC_AHB3LPENR register *************/
6203 #define RCC_AHB3LPENR_FMCLPEN 0x00000001U
6204 #define RCC_AHB3LPENR_QSPILPEN 0x00000002U
6205 /******************** Bit definition for RCC_APB1LPENR register *************/
6206 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
6207 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
6208 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
6209 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
6210 #define RCC_APB1LPENR_TIM6LPEN 0x00000010U
6211 #define RCC_APB1LPENR_TIM7LPEN 0x00000020U
6212 #define RCC_APB1LPENR_TIM12LPEN 0x00000040U
6213 #define RCC_APB1LPENR_TIM13LPEN 0x00000080U
6214 #define RCC_APB1LPENR_TIM14LPEN 0x00000100U
6215 #define RCC_APB1LPENR_LPTIM1LPEN 0x00000200U
6216 #define RCC_APB1LPENR_RTCLPEN 0x00000400U
6217 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
6218 #define RCC_APB1LPENR_CAN3LPEN 0x00002000U
6219 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
6220 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
6221 #define RCC_APB1LPENR_SPDIFRXLPEN 0x00010000U
6222 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
6223 #define RCC_APB1LPENR_USART3LPEN 0x00040000U
6224 #define RCC_APB1LPENR_UART4LPEN 0x00080000U
6225 #define RCC_APB1LPENR_UART5LPEN 0x00100000U
6226 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
6227 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
6228 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
6229 #define RCC_APB1LPENR_I2C4LPEN 0x01000000U
6230 #define RCC_APB1LPENR_CAN1LPEN 0x02000000U
6231 #define RCC_APB1LPENR_CAN2LPEN 0x04000000U
6232 #define RCC_APB1LPENR_CECLPEN 0x08000000U
6233 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
6234 #define RCC_APB1LPENR_DACLPEN 0x20000000U
6235 #define RCC_APB1LPENR_UART7LPEN 0x40000000U
6236 #define RCC_APB1LPENR_UART8LPEN 0x80000000U
6237 
6238 /******************** Bit definition for RCC_APB2LPENR register *************/
6239 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
6240 #define RCC_APB2LPENR_TIM8LPEN 0x00000002U
6241 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
6242 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
6243 #define RCC_APB2LPENR_SDMMC2LPEN 0x00000080U
6244 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
6245 #define RCC_APB2LPENR_ADC2LPEN 0x00000200U
6246 #define RCC_APB2LPENR_ADC3LPEN 0x00000400U
6247 #define RCC_APB2LPENR_SDMMC1LPEN 0x00000800U
6248 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
6249 #define RCC_APB2LPENR_SPI4LPEN 0x00002000U
6250 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
6251 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
6252 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
6253 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
6254 #define RCC_APB2LPENR_SPI5LPEN 0x00100000U
6255 #define RCC_APB2LPENR_SPI6LPEN 0x00200000U
6256 #define RCC_APB2LPENR_SAI1LPEN 0x00400000U
6257 #define RCC_APB2LPENR_SAI2LPEN 0x00800000U
6258 #define RCC_APB2LPENR_LTDCLPEN 0x04000000U
6259 #define RCC_APB2LPENR_DSILPEN 0x08000000U
6260 #define RCC_APB2LPENR_DFSDM1LPEN 0x20000000U
6261 #define RCC_APB2LPENR_MDIOLPEN 0x40000000U
6262 
6263 /******************** Bit definition for RCC_BDCR register ******************/
6264 #define RCC_BDCR_LSEON 0x00000001U
6265 #define RCC_BDCR_LSERDY 0x00000002U
6266 #define RCC_BDCR_LSEBYP 0x00000004U
6267 #define RCC_BDCR_LSEDRV 0x00000018U
6268 #define RCC_BDCR_LSEDRV_0 0x00000008U
6269 #define RCC_BDCR_LSEDRV_1 0x00000010U
6270 #define RCC_BDCR_RTCSEL 0x00000300U
6271 #define RCC_BDCR_RTCSEL_0 0x00000100U
6272 #define RCC_BDCR_RTCSEL_1 0x00000200U
6273 #define RCC_BDCR_RTCEN 0x00008000U
6274 #define RCC_BDCR_BDRST 0x00010000U
6275 
6276 /******************** Bit definition for RCC_CSR register *******************/
6277 #define RCC_CSR_LSION 0x00000001U
6278 #define RCC_CSR_LSIRDY 0x00000002U
6279 #define RCC_CSR_RMVF 0x01000000U
6280 #define RCC_CSR_BORRSTF 0x02000000U
6281 #define RCC_CSR_PINRSTF 0x04000000U
6282 #define RCC_CSR_PORRSTF 0x08000000U
6283 #define RCC_CSR_SFTRSTF 0x10000000U
6284 #define RCC_CSR_IWDGRSTF 0x20000000U
6285 #define RCC_CSR_WWDGRSTF 0x40000000U
6286 #define RCC_CSR_LPWRRSTF 0x80000000U
6287 
6288 /******************** Bit definition for RCC_SSCGR register *****************/
6289 #define RCC_SSCGR_MODPER 0x00001FFFU
6290 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
6291 #define RCC_SSCGR_SPREADSEL 0x40000000U
6292 #define RCC_SSCGR_SSCGEN 0x80000000U
6293 
6294 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
6295 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
6296 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
6297 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
6298 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
6299 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
6300 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
6301 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
6302 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
6303 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
6304 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
6305 #define RCC_PLLI2SCFGR_PLLI2SP 0x00030000U
6306 #define RCC_PLLI2SCFGR_PLLI2SP_0 0x00010000U
6307 #define RCC_PLLI2SCFGR_PLLI2SP_1 0x00020000U
6308 #define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
6309 #define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
6310 #define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
6311 #define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
6312 #define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
6313 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
6314 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
6315 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
6316 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
6317 
6318 /******************** Bit definition for RCC_PLLSAICFGR register ************/
6319 #define RCC_PLLSAICFGR_PLLSAIN 0x00007FC0U
6320 #define RCC_PLLSAICFGR_PLLSAIN_0 0x00000040U
6321 #define RCC_PLLSAICFGR_PLLSAIN_1 0x00000080U
6322 #define RCC_PLLSAICFGR_PLLSAIN_2 0x00000100U
6323 #define RCC_PLLSAICFGR_PLLSAIN_3 0x00000200U
6324 #define RCC_PLLSAICFGR_PLLSAIN_4 0x00000400U
6325 #define RCC_PLLSAICFGR_PLLSAIN_5 0x00000800U
6326 #define RCC_PLLSAICFGR_PLLSAIN_6 0x00001000U
6327 #define RCC_PLLSAICFGR_PLLSAIN_7 0x00002000U
6328 #define RCC_PLLSAICFGR_PLLSAIN_8 0x00004000U
6329 #define RCC_PLLSAICFGR_PLLSAIP 0x00030000U
6330 #define RCC_PLLSAICFGR_PLLSAIP_0 0x00010000U
6331 #define RCC_PLLSAICFGR_PLLSAIP_1 0x00020000U
6332 #define RCC_PLLSAICFGR_PLLSAIQ 0x0F000000U
6333 #define RCC_PLLSAICFGR_PLLSAIQ_0 0x01000000U
6334 #define RCC_PLLSAICFGR_PLLSAIQ_1 0x02000000U
6335 #define RCC_PLLSAICFGR_PLLSAIQ_2 0x04000000U
6336 #define RCC_PLLSAICFGR_PLLSAIQ_3 0x08000000U
6337 #define RCC_PLLSAICFGR_PLLSAIR 0x70000000U
6338 #define RCC_PLLSAICFGR_PLLSAIR_0 0x10000000U
6339 #define RCC_PLLSAICFGR_PLLSAIR_1 0x20000000U
6340 #define RCC_PLLSAICFGR_PLLSAIR_2 0x40000000U
6341 
6342 /******************** Bit definition for RCC_DCKCFGR1 register ***************/
6343 #define RCC_DCKCFGR1_PLLI2SDIVQ 0x0000001FU
6344 #define RCC_DCKCFGR1_PLLI2SDIVQ_0 0x00000001U
6345 #define RCC_DCKCFGR1_PLLI2SDIVQ_1 0x00000002U
6346 #define RCC_DCKCFGR1_PLLI2SDIVQ_2 0x00000004U
6347 #define RCC_DCKCFGR1_PLLI2SDIVQ_3 0x00000008U
6348 #define RCC_DCKCFGR1_PLLI2SDIVQ_4 0x00000010U
6349 
6350 #define RCC_DCKCFGR1_PLLSAIDIVQ 0x00001F00U
6351 #define RCC_DCKCFGR1_PLLSAIDIVQ_0 0x00000100U
6352 #define RCC_DCKCFGR1_PLLSAIDIVQ_1 0x00000200U
6353 #define RCC_DCKCFGR1_PLLSAIDIVQ_2 0x00000400U
6354 #define RCC_DCKCFGR1_PLLSAIDIVQ_3 0x00000800U
6355 #define RCC_DCKCFGR1_PLLSAIDIVQ_4 0x00001000U
6356 
6357 #define RCC_DCKCFGR1_PLLSAIDIVR 0x00030000U
6358 #define RCC_DCKCFGR1_PLLSAIDIVR_0 0x00010000U
6359 #define RCC_DCKCFGR1_PLLSAIDIVR_1 0x00020000U
6360 
6361 #define RCC_DCKCFGR1_SAI1SEL 0x00300000U
6362 #define RCC_DCKCFGR1_SAI1SEL_0 0x00100000U
6363 #define RCC_DCKCFGR1_SAI1SEL_1 0x00200000U
6364 
6365 #define RCC_DCKCFGR1_SAI2SEL 0x00C00000U
6366 #define RCC_DCKCFGR1_SAI2SEL_0 0x00400000U
6367 #define RCC_DCKCFGR1_SAI2SEL_1 0x00800000U
6368 
6369 #define RCC_DCKCFGR1_TIMPRE 0x01000000U
6370 #define RCC_DCKCFGR1_DFSDM1SEL 0x02000000U
6371 #define RCC_DCKCFGR1_ADFSDM1SEL 0x04000000U
6372 
6373 /******************** Bit definition for RCC_DCKCFGR2 register ***************/
6374 #define RCC_DCKCFGR2_USART1SEL 0x00000003U
6375 #define RCC_DCKCFGR2_USART1SEL_0 0x00000001U
6376 #define RCC_DCKCFGR2_USART1SEL_1 0x00000002U
6377 #define RCC_DCKCFGR2_USART2SEL 0x0000000CU
6378 #define RCC_DCKCFGR2_USART2SEL_0 0x00000004U
6379 #define RCC_DCKCFGR2_USART2SEL_1 0x00000008U
6380 #define RCC_DCKCFGR2_USART3SEL 0x00000030U
6381 #define RCC_DCKCFGR2_USART3SEL_0 0x00000010U
6382 #define RCC_DCKCFGR2_USART3SEL_1 0x00000020U
6383 #define RCC_DCKCFGR2_UART4SEL 0x000000C0U
6384 #define RCC_DCKCFGR2_UART4SEL_0 0x00000040U
6385 #define RCC_DCKCFGR2_UART4SEL_1 0x00000080U
6386 #define RCC_DCKCFGR2_UART5SEL 0x00000300U
6387 #define RCC_DCKCFGR2_UART5SEL_0 0x00000100U
6388 #define RCC_DCKCFGR2_UART5SEL_1 0x00000200U
6389 #define RCC_DCKCFGR2_USART6SEL 0x00000C00U
6390 #define RCC_DCKCFGR2_USART6SEL_0 0x00000400U
6391 #define RCC_DCKCFGR2_USART6SEL_1 0x00000800U
6392 #define RCC_DCKCFGR2_UART7SEL 0x00003000U
6393 #define RCC_DCKCFGR2_UART7SEL_0 0x00001000U
6394 #define RCC_DCKCFGR2_UART7SEL_1 0x00002000U
6395 #define RCC_DCKCFGR2_UART8SEL 0x0000C000U
6396 #define RCC_DCKCFGR2_UART8SEL_0 0x00004000U
6397 #define RCC_DCKCFGR2_UART8SEL_1 0x00008000U
6398 #define RCC_DCKCFGR2_I2C1SEL 0x00030000U
6399 #define RCC_DCKCFGR2_I2C1SEL_0 0x00010000U
6400 #define RCC_DCKCFGR2_I2C1SEL_1 0x00020000U
6401 #define RCC_DCKCFGR2_I2C2SEL 0x000C0000U
6402 #define RCC_DCKCFGR2_I2C2SEL_0 0x00040000U
6403 #define RCC_DCKCFGR2_I2C2SEL_1 0x00080000U
6404 #define RCC_DCKCFGR2_I2C3SEL 0x00300000U
6405 #define RCC_DCKCFGR2_I2C3SEL_0 0x00100000U
6406 #define RCC_DCKCFGR2_I2C3SEL_1 0x00200000U
6407 #define RCC_DCKCFGR2_I2C4SEL 0x00C00000U
6408 #define RCC_DCKCFGR2_I2C4SEL_0 0x00400000U
6409 #define RCC_DCKCFGR2_I2C4SEL_1 0x00800000U
6410 #define RCC_DCKCFGR2_LPTIM1SEL 0x03000000U
6411 #define RCC_DCKCFGR2_LPTIM1SEL_0 0x01000000U
6412 #define RCC_DCKCFGR2_LPTIM1SEL_1 0x02000000U
6413 #define RCC_DCKCFGR2_CECSEL 0x04000000U
6414 #define RCC_DCKCFGR2_CK48MSEL 0x08000000U
6415 #define RCC_DCKCFGR2_SDMMC1SEL 0x10000000U
6416 #define RCC_DCKCFGR2_SDMMC2SEL 0x20000000U
6417 #define RCC_DCKCFGR2_DSISEL 0x40000000U
6418 
6419 /******************************************************************************/
6420 /* */
6421 /* RNG */
6422 /* */
6423 /******************************************************************************/
6424 /******************** Bits definition for RNG_CR register *******************/
6425 #define RNG_CR_RNGEN 0x00000004U
6426 #define RNG_CR_IE 0x00000008U
6427 
6428 /******************** Bits definition for RNG_SR register *******************/
6429 #define RNG_SR_DRDY 0x00000001U
6430 #define RNG_SR_CECS 0x00000002U
6431 #define RNG_SR_SECS 0x00000004U
6432 #define RNG_SR_CEIS 0x00000020U
6433 #define RNG_SR_SEIS 0x00000040U
6434 
6435 /******************************************************************************/
6436 /* */
6437 /* Real-Time Clock (RTC) */
6438 /* */
6439 /******************************************************************************/
6440 /******************** Bits definition for RTC_TR register *******************/
6441 #define RTC_TR_PM 0x00400000U
6442 #define RTC_TR_HT 0x00300000U
6443 #define RTC_TR_HT_0 0x00100000U
6444 #define RTC_TR_HT_1 0x00200000U
6445 #define RTC_TR_HU 0x000F0000U
6446 #define RTC_TR_HU_0 0x00010000U
6447 #define RTC_TR_HU_1 0x00020000U
6448 #define RTC_TR_HU_2 0x00040000U
6449 #define RTC_TR_HU_3 0x00080000U
6450 #define RTC_TR_MNT 0x00007000U
6451 #define RTC_TR_MNT_0 0x00001000U
6452 #define RTC_TR_MNT_1 0x00002000U
6453 #define RTC_TR_MNT_2 0x00004000U
6454 #define RTC_TR_MNU 0x00000F00U
6455 #define RTC_TR_MNU_0 0x00000100U
6456 #define RTC_TR_MNU_1 0x00000200U
6457 #define RTC_TR_MNU_2 0x00000400U
6458 #define RTC_TR_MNU_3 0x00000800U
6459 #define RTC_TR_ST 0x00000070U
6460 #define RTC_TR_ST_0 0x00000010U
6461 #define RTC_TR_ST_1 0x00000020U
6462 #define RTC_TR_ST_2 0x00000040U
6463 #define RTC_TR_SU 0x0000000FU
6464 #define RTC_TR_SU_0 0x00000001U
6465 #define RTC_TR_SU_1 0x00000002U
6466 #define RTC_TR_SU_2 0x00000004U
6467 #define RTC_TR_SU_3 0x00000008U
6468 
6469 /******************** Bits definition for RTC_DR register *******************/
6470 #define RTC_DR_YT 0x00F00000U
6471 #define RTC_DR_YT_0 0x00100000U
6472 #define RTC_DR_YT_1 0x00200000U
6473 #define RTC_DR_YT_2 0x00400000U
6474 #define RTC_DR_YT_3 0x00800000U
6475 #define RTC_DR_YU 0x000F0000U
6476 #define RTC_DR_YU_0 0x00010000U
6477 #define RTC_DR_YU_1 0x00020000U
6478 #define RTC_DR_YU_2 0x00040000U
6479 #define RTC_DR_YU_3 0x00080000U
6480 #define RTC_DR_WDU 0x0000E000U
6481 #define RTC_DR_WDU_0 0x00002000U
6482 #define RTC_DR_WDU_1 0x00004000U
6483 #define RTC_DR_WDU_2 0x00008000U
6484 #define RTC_DR_MT 0x00001000U
6485 #define RTC_DR_MU 0x00000F00U
6486 #define RTC_DR_MU_0 0x00000100U
6487 #define RTC_DR_MU_1 0x00000200U
6488 #define RTC_DR_MU_2 0x00000400U
6489 #define RTC_DR_MU_3 0x00000800U
6490 #define RTC_DR_DT 0x00000030U
6491 #define RTC_DR_DT_0 0x00000010U
6492 #define RTC_DR_DT_1 0x00000020U
6493 #define RTC_DR_DU 0x0000000FU
6494 #define RTC_DR_DU_0 0x00000001U
6495 #define RTC_DR_DU_1 0x00000002U
6496 #define RTC_DR_DU_2 0x00000004U
6497 #define RTC_DR_DU_3 0x00000008U
6498 
6499 /******************** Bits definition for RTC_CR register *******************/
6500 #define RTC_CR_ITSE 0x01000000U
6501 #define RTC_CR_COE 0x00800000U
6502 #define RTC_CR_OSEL 0x00600000U
6503 #define RTC_CR_OSEL_0 0x00200000U
6504 #define RTC_CR_OSEL_1 0x00400000U
6505 #define RTC_CR_POL 0x00100000U
6506 #define RTC_CR_COSEL 0x00080000U
6507 #define RTC_CR_BCK 0x00040000U
6508 #define RTC_CR_SUB1H 0x00020000U
6509 #define RTC_CR_ADD1H 0x00010000U
6510 #define RTC_CR_TSIE 0x00008000U
6511 #define RTC_CR_WUTIE 0x00004000U
6512 #define RTC_CR_ALRBIE 0x00002000U
6513 #define RTC_CR_ALRAIE 0x00001000U
6514 #define RTC_CR_TSE 0x00000800U
6515 #define RTC_CR_WUTE 0x00000400U
6516 #define RTC_CR_ALRBE 0x00000200U
6517 #define RTC_CR_ALRAE 0x00000100U
6518 #define RTC_CR_FMT 0x00000040U
6519 #define RTC_CR_BYPSHAD 0x00000020U
6520 #define RTC_CR_REFCKON 0x00000010U
6521 #define RTC_CR_TSEDGE 0x00000008U
6522 #define RTC_CR_WUCKSEL 0x00000007U
6523 #define RTC_CR_WUCKSEL_0 0x00000001U
6524 #define RTC_CR_WUCKSEL_1 0x00000002U
6525 #define RTC_CR_WUCKSEL_2 0x00000004U
6526 
6527 /******************** Bits definition for RTC_ISR register ******************/
6528 #define RTC_ISR_ITSF 0x00020000U
6529 #define RTC_ISR_RECALPF 0x00010000U
6530 #define RTC_ISR_TAMP3F 0x00008000U
6531 #define RTC_ISR_TAMP2F 0x00004000U
6532 #define RTC_ISR_TAMP1F 0x00002000U
6533 #define RTC_ISR_TSOVF 0x00001000U
6534 #define RTC_ISR_TSF 0x00000800U
6535 #define RTC_ISR_WUTF 0x00000400U
6536 #define RTC_ISR_ALRBF 0x00000200U
6537 #define RTC_ISR_ALRAF 0x00000100U
6538 #define RTC_ISR_INIT 0x00000080U
6539 #define RTC_ISR_INITF 0x00000040U
6540 #define RTC_ISR_RSF 0x00000020U
6541 #define RTC_ISR_INITS 0x00000010U
6542 #define RTC_ISR_SHPF 0x00000008U
6543 #define RTC_ISR_WUTWF 0x00000004U
6544 #define RTC_ISR_ALRBWF 0x00000002U
6545 #define RTC_ISR_ALRAWF 0x00000001U
6546 
6547 /******************** Bits definition for RTC_PRER register *****************/
6548 #define RTC_PRER_PREDIV_A 0x007F0000U
6549 #define RTC_PRER_PREDIV_S 0x00007FFFU
6550 
6551 /******************** Bits definition for RTC_WUTR register *****************/
6552 #define RTC_WUTR_WUT 0x0000FFFFU
6553 
6554 /******************** Bits definition for RTC_ALRMAR register ***************/
6555 #define RTC_ALRMAR_MSK4 0x80000000U
6556 #define RTC_ALRMAR_WDSEL 0x40000000U
6557 #define RTC_ALRMAR_DT 0x30000000U
6558 #define RTC_ALRMAR_DT_0 0x10000000U
6559 #define RTC_ALRMAR_DT_1 0x20000000U
6560 #define RTC_ALRMAR_DU 0x0F000000U
6561 #define RTC_ALRMAR_DU_0 0x01000000U
6562 #define RTC_ALRMAR_DU_1 0x02000000U
6563 #define RTC_ALRMAR_DU_2 0x04000000U
6564 #define RTC_ALRMAR_DU_3 0x08000000U
6565 #define RTC_ALRMAR_MSK3 0x00800000U
6566 #define RTC_ALRMAR_PM 0x00400000U
6567 #define RTC_ALRMAR_HT 0x00300000U
6568 #define RTC_ALRMAR_HT_0 0x00100000U
6569 #define RTC_ALRMAR_HT_1 0x00200000U
6570 #define RTC_ALRMAR_HU 0x000F0000U
6571 #define RTC_ALRMAR_HU_0 0x00010000U
6572 #define RTC_ALRMAR_HU_1 0x00020000U
6573 #define RTC_ALRMAR_HU_2 0x00040000U
6574 #define RTC_ALRMAR_HU_3 0x00080000U
6575 #define RTC_ALRMAR_MSK2 0x00008000U
6576 #define RTC_ALRMAR_MNT 0x00007000U
6577 #define RTC_ALRMAR_MNT_0 0x00001000U
6578 #define RTC_ALRMAR_MNT_1 0x00002000U
6579 #define RTC_ALRMAR_MNT_2 0x00004000U
6580 #define RTC_ALRMAR_MNU 0x00000F00U
6581 #define RTC_ALRMAR_MNU_0 0x00000100U
6582 #define RTC_ALRMAR_MNU_1 0x00000200U
6583 #define RTC_ALRMAR_MNU_2 0x00000400U
6584 #define RTC_ALRMAR_MNU_3 0x00000800U
6585 #define RTC_ALRMAR_MSK1 0x00000080U
6586 #define RTC_ALRMAR_ST 0x00000070U
6587 #define RTC_ALRMAR_ST_0 0x00000010U
6588 #define RTC_ALRMAR_ST_1 0x00000020U
6589 #define RTC_ALRMAR_ST_2 0x00000040U
6590 #define RTC_ALRMAR_SU 0x0000000FU
6591 #define RTC_ALRMAR_SU_0 0x00000001U
6592 #define RTC_ALRMAR_SU_1 0x00000002U
6593 #define RTC_ALRMAR_SU_2 0x00000004U
6594 #define RTC_ALRMAR_SU_3 0x00000008U
6595 
6596 /******************** Bits definition for RTC_ALRMBR register ***************/
6597 #define RTC_ALRMBR_MSK4 0x80000000U
6598 #define RTC_ALRMBR_WDSEL 0x40000000U
6599 #define RTC_ALRMBR_DT 0x30000000U
6600 #define RTC_ALRMBR_DT_0 0x10000000U
6601 #define RTC_ALRMBR_DT_1 0x20000000U
6602 #define RTC_ALRMBR_DU 0x0F000000U
6603 #define RTC_ALRMBR_DU_0 0x01000000U
6604 #define RTC_ALRMBR_DU_1 0x02000000U
6605 #define RTC_ALRMBR_DU_2 0x04000000U
6606 #define RTC_ALRMBR_DU_3 0x08000000U
6607 #define RTC_ALRMBR_MSK3 0x00800000U
6608 #define RTC_ALRMBR_PM 0x00400000U
6609 #define RTC_ALRMBR_HT 0x00300000U
6610 #define RTC_ALRMBR_HT_0 0x00100000U
6611 #define RTC_ALRMBR_HT_1 0x00200000U
6612 #define RTC_ALRMBR_HU 0x000F0000U
6613 #define RTC_ALRMBR_HU_0 0x00010000U
6614 #define RTC_ALRMBR_HU_1 0x00020000U
6615 #define RTC_ALRMBR_HU_2 0x00040000U
6616 #define RTC_ALRMBR_HU_3 0x00080000U
6617 #define RTC_ALRMBR_MSK2 0x00008000U
6618 #define RTC_ALRMBR_MNT 0x00007000U
6619 #define RTC_ALRMBR_MNT_0 0x00001000U
6620 #define RTC_ALRMBR_MNT_1 0x00002000U
6621 #define RTC_ALRMBR_MNT_2 0x00004000U
6622 #define RTC_ALRMBR_MNU 0x00000F00U
6623 #define RTC_ALRMBR_MNU_0 0x00000100U
6624 #define RTC_ALRMBR_MNU_1 0x00000200U
6625 #define RTC_ALRMBR_MNU_2 0x00000400U
6626 #define RTC_ALRMBR_MNU_3 0x00000800U
6627 #define RTC_ALRMBR_MSK1 0x00000080U
6628 #define RTC_ALRMBR_ST 0x00000070U
6629 #define RTC_ALRMBR_ST_0 0x00000010U
6630 #define RTC_ALRMBR_ST_1 0x00000020U
6631 #define RTC_ALRMBR_ST_2 0x00000040U
6632 #define RTC_ALRMBR_SU 0x0000000FU
6633 #define RTC_ALRMBR_SU_0 0x00000001U
6634 #define RTC_ALRMBR_SU_1 0x00000002U
6635 #define RTC_ALRMBR_SU_2 0x00000004U
6636 #define RTC_ALRMBR_SU_3 0x00000008U
6637 
6638 /******************** Bits definition for RTC_WPR register ******************/
6639 #define RTC_WPR_KEY 0x000000FFU
6640 
6641 /******************** Bits definition for RTC_SSR register ******************/
6642 #define RTC_SSR_SS 0x0000FFFFU
6643 
6644 /******************** Bits definition for RTC_SHIFTR register ***************/
6645 #define RTC_SHIFTR_SUBFS 0x00007FFFU
6646 #define RTC_SHIFTR_ADD1S 0x80000000U
6647 
6648 /******************** Bits definition for RTC_TSTR register *****************/
6649 #define RTC_TSTR_PM 0x00400000U
6650 #define RTC_TSTR_HT 0x00300000U
6651 #define RTC_TSTR_HT_0 0x00100000U
6652 #define RTC_TSTR_HT_1 0x00200000U
6653 #define RTC_TSTR_HU 0x000F0000U
6654 #define RTC_TSTR_HU_0 0x00010000U
6655 #define RTC_TSTR_HU_1 0x00020000U
6656 #define RTC_TSTR_HU_2 0x00040000U
6657 #define RTC_TSTR_HU_3 0x00080000U
6658 #define RTC_TSTR_MNT 0x00007000U
6659 #define RTC_TSTR_MNT_0 0x00001000U
6660 #define RTC_TSTR_MNT_1 0x00002000U
6661 #define RTC_TSTR_MNT_2 0x00004000U
6662 #define RTC_TSTR_MNU 0x00000F00U
6663 #define RTC_TSTR_MNU_0 0x00000100U
6664 #define RTC_TSTR_MNU_1 0x00000200U
6665 #define RTC_TSTR_MNU_2 0x00000400U
6666 #define RTC_TSTR_MNU_3 0x00000800U
6667 #define RTC_TSTR_ST 0x00000070U
6668 #define RTC_TSTR_ST_0 0x00000010U
6669 #define RTC_TSTR_ST_1 0x00000020U
6670 #define RTC_TSTR_ST_2 0x00000040U
6671 #define RTC_TSTR_SU 0x0000000FU
6672 #define RTC_TSTR_SU_0 0x00000001U
6673 #define RTC_TSTR_SU_1 0x00000002U
6674 #define RTC_TSTR_SU_2 0x00000004U
6675 #define RTC_TSTR_SU_3 0x00000008U
6676 
6677 /******************** Bits definition for RTC_TSDR register *****************/
6678 #define RTC_TSDR_WDU 0x0000E000U
6679 #define RTC_TSDR_WDU_0 0x00002000U
6680 #define RTC_TSDR_WDU_1 0x00004000U
6681 #define RTC_TSDR_WDU_2 0x00008000U
6682 #define RTC_TSDR_MT 0x00001000U
6683 #define RTC_TSDR_MU 0x00000F00U
6684 #define RTC_TSDR_MU_0 0x00000100U
6685 #define RTC_TSDR_MU_1 0x00000200U
6686 #define RTC_TSDR_MU_2 0x00000400U
6687 #define RTC_TSDR_MU_3 0x00000800U
6688 #define RTC_TSDR_DT 0x00000030U
6689 #define RTC_TSDR_DT_0 0x00000010U
6690 #define RTC_TSDR_DT_1 0x00000020U
6691 #define RTC_TSDR_DU 0x0000000FU
6692 #define RTC_TSDR_DU_0 0x00000001U
6693 #define RTC_TSDR_DU_1 0x00000002U
6694 #define RTC_TSDR_DU_2 0x00000004U
6695 #define RTC_TSDR_DU_3 0x00000008U
6696 
6697 /******************** Bits definition for RTC_TSSSR register ****************/
6698 #define RTC_TSSSR_SS 0x0000FFFFU
6699 
6700 /******************** Bits definition for RTC_CAL register *****************/
6701 #define RTC_CALR_CALP 0x00008000U
6702 #define RTC_CALR_CALW8 0x00004000U
6703 #define RTC_CALR_CALW16 0x00002000U
6704 #define RTC_CALR_CALM 0x000001FFU
6705 #define RTC_CALR_CALM_0 0x00000001U
6706 #define RTC_CALR_CALM_1 0x00000002U
6707 #define RTC_CALR_CALM_2 0x00000004U
6708 #define RTC_CALR_CALM_3 0x00000008U
6709 #define RTC_CALR_CALM_4 0x00000010U
6710 #define RTC_CALR_CALM_5 0x00000020U
6711 #define RTC_CALR_CALM_6 0x00000040U
6712 #define RTC_CALR_CALM_7 0x00000080U
6713 #define RTC_CALR_CALM_8 0x00000100U
6714 
6715 /******************** Bits definition for RTC_TAMPCR register ****************/
6716 #define RTC_TAMPCR_TAMP3MF 0x01000000U
6717 #define RTC_TAMPCR_TAMP3NOERASE 0x00800000U
6718 #define RTC_TAMPCR_TAMP3IE 0x00400000U
6719 #define RTC_TAMPCR_TAMP2MF 0x00200000U
6720 #define RTC_TAMPCR_TAMP2NOERASE 0x00100000U
6721 #define RTC_TAMPCR_TAMP2IE 0x00080000U
6722 #define RTC_TAMPCR_TAMP1MF 0x00040000U
6723 #define RTC_TAMPCR_TAMP1NOERASE 0x00020000U
6724 #define RTC_TAMPCR_TAMP1IE 0x00010000U
6725 #define RTC_TAMPCR_TAMPPUDIS 0x00008000U
6726 #define RTC_TAMPCR_TAMPPRCH 0x00006000U
6727 #define RTC_TAMPCR_TAMPPRCH_0 0x00002000U
6728 #define RTC_TAMPCR_TAMPPRCH_1 0x00004000U
6729 #define RTC_TAMPCR_TAMPFLT 0x00001800U
6730 #define RTC_TAMPCR_TAMPFLT_0 0x00000800U
6731 #define RTC_TAMPCR_TAMPFLT_1 0x00001000U
6732 #define RTC_TAMPCR_TAMPFREQ 0x00000700U
6733 #define RTC_TAMPCR_TAMPFREQ_0 0x00000100U
6734 #define RTC_TAMPCR_TAMPFREQ_1 0x00000200U
6735 #define RTC_TAMPCR_TAMPFREQ_2 0x00000400U
6736 #define RTC_TAMPCR_TAMPTS 0x00000080U
6737 #define RTC_TAMPCR_TAMP3TRG 0x00000040U
6738 #define RTC_TAMPCR_TAMP3E 0x00000020U
6739 #define RTC_TAMPCR_TAMP2TRG 0x00000010U
6740 #define RTC_TAMPCR_TAMP2E 0x00000008U
6741 #define RTC_TAMPCR_TAMPIE 0x00000004U
6742 #define RTC_TAMPCR_TAMP1TRG 0x00000002U
6743 #define RTC_TAMPCR_TAMP1E 0x00000001U
6744 
6745 
6746 /******************** Bits definition for RTC_ALRMASSR register *************/
6747 #define RTC_ALRMASSR_MASKSS 0x0F000000U
6748 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
6749 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
6750 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
6751 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
6752 #define RTC_ALRMASSR_SS 0x00007FFFU
6753 
6754 /******************** Bits definition for RTC_ALRMBSSR register *************/
6755 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
6756 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
6757 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
6758 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
6759 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
6760 #define RTC_ALRMBSSR_SS 0x00007FFFU
6761 
6762 /******************** Bits definition for RTC_OR register ****************/
6763 #define RTC_OR_TSINSEL 0x00000006U
6764 #define RTC_OR_TSINSEL_0 0x00000002U
6765 #define RTC_OR_TSINSEL_1 0x00000004U
6766 #define RTC_OR_ALARMTYPE 0x00000008U
6767 
6768 /******************** Bits definition for RTC_BKP0R register ****************/
6769 #define RTC_BKP0R 0xFFFFFFFFU
6770 
6771 /******************** Bits definition for RTC_BKP1R register ****************/
6772 #define RTC_BKP1R 0xFFFFFFFFU
6773 
6774 /******************** Bits definition for RTC_BKP2R register ****************/
6775 #define RTC_BKP2R 0xFFFFFFFFU
6776 
6777 /******************** Bits definition for RTC_BKP3R register ****************/
6778 #define RTC_BKP3R 0xFFFFFFFFU
6779 
6780 /******************** Bits definition for RTC_BKP4R register ****************/
6781 #define RTC_BKP4R 0xFFFFFFFFU
6782 
6783 /******************** Bits definition for RTC_BKP5R register ****************/
6784 #define RTC_BKP5R 0xFFFFFFFFU
6785 
6786 /******************** Bits definition for RTC_BKP6R register ****************/
6787 #define RTC_BKP6R 0xFFFFFFFFU
6788 
6789 /******************** Bits definition for RTC_BKP7R register ****************/
6790 #define RTC_BKP7R 0xFFFFFFFFU
6791 
6792 /******************** Bits definition for RTC_BKP8R register ****************/
6793 #define RTC_BKP8R 0xFFFFFFFFU
6794 
6795 /******************** Bits definition for RTC_BKP9R register ****************/
6796 #define RTC_BKP9R 0xFFFFFFFFU
6797 
6798 /******************** Bits definition for RTC_BKP10R register ***************/
6799 #define RTC_BKP10R 0xFFFFFFFFU
6800 
6801 /******************** Bits definition for RTC_BKP11R register ***************/
6802 #define RTC_BKP11R 0xFFFFFFFFU
6803 
6804 /******************** Bits definition for RTC_BKP12R register ***************/
6805 #define RTC_BKP12R 0xFFFFFFFFU
6806 
6807 /******************** Bits definition for RTC_BKP13R register ***************/
6808 #define RTC_BKP13R 0xFFFFFFFFU
6809 
6810 /******************** Bits definition for RTC_BKP14R register ***************/
6811 #define RTC_BKP14R 0xFFFFFFFFU
6812 
6813 /******************** Bits definition for RTC_BKP15R register ***************/
6814 #define RTC_BKP15R 0xFFFFFFFFU
6815 
6816 /******************** Bits definition for RTC_BKP16R register ***************/
6817 #define RTC_BKP16R 0xFFFFFFFFU
6818 
6819 /******************** Bits definition for RTC_BKP17R register ***************/
6820 #define RTC_BKP17R 0xFFFFFFFFU
6821 
6822 /******************** Bits definition for RTC_BKP18R register ***************/
6823 #define RTC_BKP18R 0xFFFFFFFFU
6824 
6825 /******************** Bits definition for RTC_BKP19R register ***************/
6826 #define RTC_BKP19R 0xFFFFFFFFU
6827 
6828 /******************** Bits definition for RTC_BKP20R register ***************/
6829 #define RTC_BKP20R 0xFFFFFFFFU
6830 
6831 /******************** Bits definition for RTC_BKP21R register ***************/
6832 #define RTC_BKP21R 0xFFFFFFFFU
6833 
6834 /******************** Bits definition for RTC_BKP22R register ***************/
6835 #define RTC_BKP22R 0xFFFFFFFFU
6836 
6837 /******************** Bits definition for RTC_BKP23R register ***************/
6838 #define RTC_BKP23R 0xFFFFFFFFU
6839 
6840 /******************** Bits definition for RTC_BKP24R register ***************/
6841 #define RTC_BKP24R 0xFFFFFFFFU
6842 
6843 /******************** Bits definition for RTC_BKP25R register ***************/
6844 #define RTC_BKP25R 0xFFFFFFFFU
6845 
6846 /******************** Bits definition for RTC_BKP26R register ***************/
6847 #define RTC_BKP26R 0xFFFFFFFFU
6848 
6849 /******************** Bits definition for RTC_BKP27R register ***************/
6850 #define RTC_BKP27R 0xFFFFFFFFU
6851 
6852 /******************** Bits definition for RTC_BKP28R register ***************/
6853 #define RTC_BKP28R 0xFFFFFFFFU
6854 
6855 /******************** Bits definition for RTC_BKP29R register ***************/
6856 #define RTC_BKP29R 0xFFFFFFFFU
6857 
6858 /******************** Bits definition for RTC_BKP30R register ***************/
6859 #define RTC_BKP30R 0xFFFFFFFFU
6860 
6861 /******************** Bits definition for RTC_BKP31R register ***************/
6862 #define RTC_BKP31R 0xFFFFFFFFU
6863 
6864 /******************** Number of backup registers ******************************/
6865 #define RTC_BKP_NUMBER 0x00000020U
6866 
6867 
6868 /******************************************************************************/
6869 /* */
6870 /* Serial Audio Interface */
6871 /* */
6872 /******************************************************************************/
6873 /******************** Bit definition for SAI_GCR register *******************/
6874 #define SAI_GCR_SYNCIN 0x00000003U
6875 #define SAI_GCR_SYNCIN_0 0x00000001U
6876 #define SAI_GCR_SYNCIN_1 0x00000002U
6878 #define SAI_GCR_SYNCOUT 0x00000030U
6879 #define SAI_GCR_SYNCOUT_0 0x00000010U
6880 #define SAI_GCR_SYNCOUT_1 0x00000020U
6882 /******************* Bit definition for SAI_xCR1 register *******************/
6883 #define SAI_xCR1_MODE 0x00000003U
6884 #define SAI_xCR1_MODE_0 0x00000001U
6885 #define SAI_xCR1_MODE_1 0x00000002U
6887 #define SAI_xCR1_PRTCFG 0x0000000CU
6888 #define SAI_xCR1_PRTCFG_0 0x00000004U
6889 #define SAI_xCR1_PRTCFG_1 0x00000008U
6891 #define SAI_xCR1_DS 0x000000E0U
6892 #define SAI_xCR1_DS_0 0x00000020U
6893 #define SAI_xCR1_DS_1 0x00000040U
6894 #define SAI_xCR1_DS_2 0x00000080U
6896 #define SAI_xCR1_LSBFIRST 0x00000100U
6897 #define SAI_xCR1_CKSTR 0x00000200U
6899 #define SAI_xCR1_SYNCEN 0x00000C00U
6900 #define SAI_xCR1_SYNCEN_0 0x00000400U
6901 #define SAI_xCR1_SYNCEN_1 0x00000800U
6903 #define SAI_xCR1_MONO 0x00001000U
6904 #define SAI_xCR1_OUTDRIV 0x00002000U
6905 #define SAI_xCR1_SAIEN 0x00010000U
6906 #define SAI_xCR1_DMAEN 0x00020000U
6907 #define SAI_xCR1_NODIV 0x00080000U
6909 #define SAI_xCR1_MCKDIV 0x00F00000U
6910 #define SAI_xCR1_MCKDIV_0 0x00100000U
6911 #define SAI_xCR1_MCKDIV_1 0x00200000U
6912 #define SAI_xCR1_MCKDIV_2 0x00400000U
6913 #define SAI_xCR1_MCKDIV_3 0x00800000U
6915 /******************* Bit definition for SAI_xCR2 register *******************/
6916 #define SAI_xCR2_FTH 0x00000007U
6917 #define SAI_xCR2_FTH_0 0x00000001U
6918 #define SAI_xCR2_FTH_1 0x00000002U
6919 #define SAI_xCR2_FTH_2 0x00000004U
6921 #define SAI_xCR2_FFLUSH 0x00000008U
6922 #define SAI_xCR2_TRIS 0x00000010U
6923 #define SAI_xCR2_MUTE 0x00000020U
6924 #define SAI_xCR2_MUTEVAL 0x00000040U
6926 #define SAI_xCR2_MUTECNT 0x00001F80U
6927 #define SAI_xCR2_MUTECNT_0 0x00000080U
6928 #define SAI_xCR2_MUTECNT_1 0x00000100U
6929 #define SAI_xCR2_MUTECNT_2 0x00000200U
6930 #define SAI_xCR2_MUTECNT_3 0x00000400U
6931 #define SAI_xCR2_MUTECNT_4 0x00000800U
6932 #define SAI_xCR2_MUTECNT_5 0x00001000U
6934 #define SAI_xCR2_CPL 0x00002000U
6936 #define SAI_xCR2_COMP 0x0000C000U
6937 #define SAI_xCR2_COMP_0 0x00004000U
6938 #define SAI_xCR2_COMP_1 0x00008000U
6940 /****************** Bit definition for SAI_xFRCR register *******************/
6941 #define SAI_xFRCR_FRL 0x000000FFU
6942 #define SAI_xFRCR_FRL_0 0x00000001U
6943 #define SAI_xFRCR_FRL_1 0x00000002U
6944 #define SAI_xFRCR_FRL_2 0x00000004U
6945 #define SAI_xFRCR_FRL_3 0x00000008U
6946 #define SAI_xFRCR_FRL_4 0x00000010U
6947 #define SAI_xFRCR_FRL_5 0x00000020U
6948 #define SAI_xFRCR_FRL_6 0x00000040U
6949 #define SAI_xFRCR_FRL_7 0x00000080U
6951 #define SAI_xFRCR_FSALL 0x00007F00U
6952 #define SAI_xFRCR_FSALL_0 0x00000100U
6953 #define SAI_xFRCR_FSALL_1 0x00000200U
6954 #define SAI_xFRCR_FSALL_2 0x00000400U
6955 #define SAI_xFRCR_FSALL_3 0x00000800U
6956 #define SAI_xFRCR_FSALL_4 0x00001000U
6957 #define SAI_xFRCR_FSALL_5 0x00002000U
6958 #define SAI_xFRCR_FSALL_6 0x00004000U
6960 #define SAI_xFRCR_FSDEF 0x00010000U
6961 #define SAI_xFRCR_FSPOL 0x00020000U
6962 #define SAI_xFRCR_FSOFF 0x00040000U
6964 /* Legacy define */
6965 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
6966 
6967 /****************** Bit definition for SAI_xSLOTR register *******************/
6968 #define SAI_xSLOTR_FBOFF 0x0000001FU
6969 #define SAI_xSLOTR_FBOFF_0 0x00000001U
6970 #define SAI_xSLOTR_FBOFF_1 0x00000002U
6971 #define SAI_xSLOTR_FBOFF_2 0x00000004U
6972 #define SAI_xSLOTR_FBOFF_3 0x00000008U
6973 #define SAI_xSLOTR_FBOFF_4 0x00000010U
6975 #define SAI_xSLOTR_SLOTSZ 0x000000C0U
6976 #define SAI_xSLOTR_SLOTSZ_0 0x00000040U
6977 #define SAI_xSLOTR_SLOTSZ_1 0x00000080U
6979 #define SAI_xSLOTR_NBSLOT 0x00000F00U
6980 #define SAI_xSLOTR_NBSLOT_0 0x00000100U
6981 #define SAI_xSLOTR_NBSLOT_1 0x00000200U
6982 #define SAI_xSLOTR_NBSLOT_2 0x00000400U
6983 #define SAI_xSLOTR_NBSLOT_3 0x00000800U
6985 #define SAI_xSLOTR_SLOTEN 0xFFFF0000U
6987 /******************* Bit definition for SAI_xIMR register *******************/
6988 #define SAI_xIMR_OVRUDRIE 0x00000001U
6989 #define SAI_xIMR_MUTEDETIE 0x00000002U
6990 #define SAI_xIMR_WCKCFGIE 0x00000004U
6991 #define SAI_xIMR_FREQIE 0x00000008U
6992 #define SAI_xIMR_CNRDYIE 0x00000010U
6993 #define SAI_xIMR_AFSDETIE 0x00000020U
6994 #define SAI_xIMR_LFSDETIE 0x00000040U
6996 /******************** Bit definition for SAI_xSR register *******************/
6997 #define SAI_xSR_OVRUDR 0x00000001U
6998 #define SAI_xSR_MUTEDET 0x00000002U
6999 #define SAI_xSR_WCKCFG 0x00000004U
7000 #define SAI_xSR_FREQ 0x00000008U
7001 #define SAI_xSR_CNRDY 0x00000010U
7002 #define SAI_xSR_AFSDET 0x00000020U
7003 #define SAI_xSR_LFSDET 0x00000040U
7005 #define SAI_xSR_FLVL 0x00070000U
7006 #define SAI_xSR_FLVL_0 0x00010000U
7007 #define SAI_xSR_FLVL_1 0x00020000U
7008 #define SAI_xSR_FLVL_2 0x00040000U
7010 /****************** Bit definition for SAI_xCLRFR register ******************/
7011 #define SAI_xCLRFR_COVRUDR 0x00000001U
7012 #define SAI_xCLRFR_CMUTEDET 0x00000002U
7013 #define SAI_xCLRFR_CWCKCFG 0x00000004U
7014 #define SAI_xCLRFR_CFREQ 0x00000008U
7015 #define SAI_xCLRFR_CCNRDY 0x00000010U
7016 #define SAI_xCLRFR_CAFSDET 0x00000020U
7017 #define SAI_xCLRFR_CLFSDET 0x00000040U
7019 /****************** Bit definition for SAI_xDR register *********************/
7020 #define SAI_xDR_DATA 0xFFFFFFFFU
7021 
7022 /******************************************************************************/
7023 /* */
7024 /* SPDIF-RX Interface */
7025 /* */
7026 /******************************************************************************/
7027 /******************** Bit definition for SPDIF_CR register *******************/
7028 #define SPDIFRX_CR_SPDIFEN 0x00000003U
7029 #define SPDIFRX_CR_RXDMAEN 0x00000004U
7030 #define SPDIFRX_CR_RXSTEO 0x00000008U
7031 #define SPDIFRX_CR_DRFMT 0x00000030U
7032 #define SPDIFRX_CR_PMSK 0x00000040U
7033 #define SPDIFRX_CR_VMSK 0x00000080U
7034 #define SPDIFRX_CR_CUMSK 0x00000100U
7035 #define SPDIFRX_CR_PTMSK 0x00000200U
7036 #define SPDIFRX_CR_CBDMAEN 0x00000400U
7037 #define SPDIFRX_CR_CHSEL 0x00000800U
7038 #define SPDIFRX_CR_NBTR 0x00003000U
7039 #define SPDIFRX_CR_WFA 0x00004000U
7040 #define SPDIFRX_CR_INSEL 0x00070000U
7042 /******************* Bit definition for SPDIFRX_IMR register *******************/
7043 #define SPDIFRX_IMR_RXNEIE 0x00000001U
7044 #define SPDIFRX_IMR_CSRNEIE 0x00000002U
7045 #define SPDIFRX_IMR_PERRIE 0x00000004U
7046 #define SPDIFRX_IMR_OVRIE 0x00000008U
7047 #define SPDIFRX_IMR_SBLKIE 0x00000010U
7048 #define SPDIFRX_IMR_SYNCDIE 0x00000020U
7049 #define SPDIFRX_IMR_IFEIE 0x00000040U
7051 /******************* Bit definition for SPDIFRX_SR register *******************/
7052 #define SPDIFRX_SR_RXNE 0x00000001U
7053 #define SPDIFRX_SR_CSRNE 0x00000002U
7054 #define SPDIFRX_SR_PERR 0x00000004U
7055 #define SPDIFRX_SR_OVR 0x00000008U
7056 #define SPDIFRX_SR_SBD 0x00000010U
7057 #define SPDIFRX_SR_SYNCD 0x00000020U
7058 #define SPDIFRX_SR_FERR 0x00000040U
7059 #define SPDIFRX_SR_SERR 0x00000080U
7060 #define SPDIFRX_SR_TERR 0x00000100U
7061 #define SPDIFRX_SR_WIDTH5 0x7FFF0000U
7063 /******************* Bit definition for SPDIFRX_IFCR register *******************/
7064 #define SPDIFRX_IFCR_PERRCF 0x00000004U
7065 #define SPDIFRX_IFCR_OVRCF 0x00000008U
7066 #define SPDIFRX_IFCR_SBDCF 0x00000010U
7067 #define SPDIFRX_IFCR_SYNCDCF 0x00000020U
7069 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
7070 #define SPDIFRX_DR0_DR 0x00FFFFFFU
7071 #define SPDIFRX_DR0_PE 0x01000000U
7072 #define SPDIFRX_DR0_V 0x02000000U
7073 #define SPDIFRX_DR0_U 0x04000000U
7074 #define SPDIFRX_DR0_C 0x08000000U
7075 #define SPDIFRX_DR0_PT 0x30000000U
7077 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
7078 #define SPDIFRX_DR1_DR 0xFFFFFF00U
7079 #define SPDIFRX_DR1_PT 0x00000030U
7080 #define SPDIFRX_DR1_C 0x00000008U
7081 #define SPDIFRX_DR1_U 0x00000004U
7082 #define SPDIFRX_DR1_V 0x00000002U
7083 #define SPDIFRX_DR1_PE 0x00000001U
7085 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
7086 #define SPDIFRX_DR1_DRNL1 0xFFFF0000U
7087 #define SPDIFRX_DR1_DRNL2 0x0000FFFFU
7089 /******************* Bit definition for SPDIFRX_CSR register *******************/
7090 #define SPDIFRX_CSR_USR 0x0000FFFFU
7091 #define SPDIFRX_CSR_CS 0x00FF0000U
7092 #define SPDIFRX_CSR_SOB 0x01000000U
7094 /******************* Bit definition for SPDIFRX_DIR register *******************/
7095 #define SPDIFRX_DIR_THI 0x000013FFU
7096 #define SPDIFRX_DIR_TLO 0x1FFF0000U
7099 /******************************************************************************/
7100 /* */
7101 /* SD host Interface */
7102 /* */
7103 /******************************************************************************/
7104 /****************** Bit definition for SDMMC_POWER register ******************/
7105 #define SDMMC_POWER_PWRCTRL 0x03U
7106 #define SDMMC_POWER_PWRCTRL_0 0x01U
7107 #define SDMMC_POWER_PWRCTRL_1 0x02U
7109 /****************** Bit definition for SDMMC_CLKCR register ******************/
7110 #define SDMMC_CLKCR_CLKDIV 0x00FFU
7111 #define SDMMC_CLKCR_CLKEN 0x0100U
7112 #define SDMMC_CLKCR_PWRSAV 0x0200U
7113 #define SDMMC_CLKCR_BYPASS 0x0400U
7115 #define SDMMC_CLKCR_WIDBUS 0x1800U
7116 #define SDMMC_CLKCR_WIDBUS_0 0x0800U
7117 #define SDMMC_CLKCR_WIDBUS_1 0x1000U
7119 #define SDMMC_CLKCR_NEGEDGE 0x2000U
7120 #define SDMMC_CLKCR_HWFC_EN 0x4000U
7122 /******************* Bit definition for SDMMC_ARG register *******************/
7123 #define SDMMC_ARG_CMDARG 0xFFFFFFFFU
7125 /******************* Bit definition for SDMMC_CMD register *******************/
7126 #define SDMMC_CMD_CMDINDEX 0x003FU
7128 #define SDMMC_CMD_WAITRESP 0x00C0U
7129 #define SDMMC_CMD_WAITRESP_0 0x0040U
7130 #define SDMMC_CMD_WAITRESP_1 0x0080U
7132 #define SDMMC_CMD_WAITINT 0x0100U
7133 #define SDMMC_CMD_WAITPEND 0x0200U
7134 #define SDMMC_CMD_CPSMEN 0x0400U
7135 #define SDMMC_CMD_SDIOSUSPEND 0x0800U
7137 /***************** Bit definition for SDMMC_RESPCMD register *****************/
7138 #define SDMMC_RESPCMD_RESPCMD 0x3FU
7140 /****************** Bit definition for SDMMC_RESP0 register ******************/
7141 #define SDMMC_RESP0_CARDSTATUS0 0xFFFFFFFFU
7143 /****************** Bit definition for SDMMC_RESP1 register ******************/
7144 #define SDMMC_RESP1_CARDSTATUS1 0xFFFFFFFFU
7146 /****************** Bit definition for SDMMC_RESP2 register ******************/
7147 #define SDMMC_RESP2_CARDSTATUS2 0xFFFFFFFFU
7149 /****************** Bit definition for SDMMC_RESP3 register ******************/
7150 #define SDMMC_RESP3_CARDSTATUS3 0xFFFFFFFFU
7152 /****************** Bit definition for SDMMC_RESP4 register ******************/
7153 #define SDMMC_RESP4_CARDSTATUS4 0xFFFFFFFFU
7155 /****************** Bit definition for SDMMC_DTIMER register *****************/
7156 #define SDMMC_DTIMER_DATATIME 0xFFFFFFFFU
7158 /****************** Bit definition for SDMMC_DLEN register *******************/
7159 #define SDMMC_DLEN_DATALENGTH 0x01FFFFFFU
7161 /****************** Bit definition for SDMMC_DCTRL register ******************/
7162 #define SDMMC_DCTRL_DTEN 0x0001U
7163 #define SDMMC_DCTRL_DTDIR 0x0002U
7164 #define SDMMC_DCTRL_DTMODE 0x0004U
7165 #define SDMMC_DCTRL_DMAEN 0x0008U
7167 #define SDMMC_DCTRL_DBLOCKSIZE 0x00F0U
7168 #define SDMMC_DCTRL_DBLOCKSIZE_0 0x0010U
7169 #define SDMMC_DCTRL_DBLOCKSIZE_1 0x0020U
7170 #define SDMMC_DCTRL_DBLOCKSIZE_2 0x0040U
7171 #define SDMMC_DCTRL_DBLOCKSIZE_3 0x0080U
7173 #define SDMMC_DCTRL_RWSTART 0x0100U
7174 #define SDMMC_DCTRL_RWSTOP 0x0200U
7175 #define SDMMC_DCTRL_RWMOD 0x0400U
7176 #define SDMMC_DCTRL_SDIOEN 0x0800U
7178 /****************** Bit definition for SDMMC_DCOUNT register *****************/
7179 #define SDMMC_DCOUNT_DATACOUNT 0x01FFFFFFU
7181 /****************** Bit definition for SDMMC_STA registe ********************/
7182 #define SDMMC_STA_CCRCFAIL 0x00000001U
7183 #define SDMMC_STA_DCRCFAIL 0x00000002U
7184 #define SDMMC_STA_CTIMEOUT 0x00000004U
7185 #define SDMMC_STA_DTIMEOUT 0x00000008U
7186 #define SDMMC_STA_TXUNDERR 0x00000010U
7187 #define SDMMC_STA_RXOVERR 0x00000020U
7188 #define SDMMC_STA_CMDREND 0x00000040U
7189 #define SDMMC_STA_CMDSENT 0x00000080U
7190 #define SDMMC_STA_DATAEND 0x00000100U
7191 #define SDMMC_STA_DBCKEND 0x00000400U
7192 #define SDMMC_STA_CMDACT 0x00000800U
7193 #define SDMMC_STA_TXACT 0x00001000U
7194 #define SDMMC_STA_RXACT 0x00002000U
7195 #define SDMMC_STA_TXFIFOHE 0x00004000U
7196 #define SDMMC_STA_RXFIFOHF 0x00008000U
7197 #define SDMMC_STA_TXFIFOF 0x00010000U
7198 #define SDMMC_STA_RXFIFOF 0x00020000U
7199 #define SDMMC_STA_TXFIFOE 0x00040000U
7200 #define SDMMC_STA_RXFIFOE 0x00080000U
7201 #define SDMMC_STA_TXDAVL 0x00100000U
7202 #define SDMMC_STA_RXDAVL 0x00200000U
7203 #define SDMMC_STA_SDIOIT 0x00400000U
7205 /******************* Bit definition for SDMMC_ICR register *******************/
7206 #define SDMMC_ICR_CCRCFAILC 0x00000001U
7207 #define SDMMC_ICR_DCRCFAILC 0x00000002U
7208 #define SDMMC_ICR_CTIMEOUTC 0x00000004U
7209 #define SDMMC_ICR_DTIMEOUTC 0x00000008U
7210 #define SDMMC_ICR_TXUNDERRC 0x00000010U
7211 #define SDMMC_ICR_RXOVERRC 0x00000020U
7212 #define SDMMC_ICR_CMDRENDC 0x00000040U
7213 #define SDMMC_ICR_CMDSENTC 0x00000080U
7214 #define SDMMC_ICR_DATAENDC 0x00000100U
7215 #define SDMMC_ICR_DBCKENDC 0x00000400U
7216 #define SDMMC_ICR_SDIOITC 0x00400000U
7218 /****************** Bit definition for SDMMC_MASK register *******************/
7219 #define SDMMC_MASK_CCRCFAILIE 0x00000001U
7220 #define SDMMC_MASK_DCRCFAILIE 0x00000002U
7221 #define SDMMC_MASK_CTIMEOUTIE 0x00000004U
7222 #define SDMMC_MASK_DTIMEOUTIE 0x00000008U
7223 #define SDMMC_MASK_TXUNDERRIE 0x00000010U
7224 #define SDMMC_MASK_RXOVERRIE 0x00000020U
7225 #define SDMMC_MASK_CMDRENDIE 0x00000040U
7226 #define SDMMC_MASK_CMDSENTIE 0x00000080U
7227 #define SDMMC_MASK_DATAENDIE 0x00000100U
7228 #define SDMMC_MASK_DBCKENDIE 0x00000400U
7229 #define SDMMC_MASK_CMDACTIE 0x00000800U
7230 #define SDMMC_MASK_TXACTIE 0x00001000U
7231 #define SDMMC_MASK_RXACTIE 0x00002000U
7232 #define SDMMC_MASK_TXFIFOHEIE 0x00004000U
7233 #define SDMMC_MASK_RXFIFOHFIE 0x00008000U
7234 #define SDMMC_MASK_TXFIFOFIE 0x00010000U
7235 #define SDMMC_MASK_RXFIFOFIE 0x00020000U
7236 #define SDMMC_MASK_TXFIFOEIE 0x00040000U
7237 #define SDMMC_MASK_RXFIFOEIE 0x00080000U
7238 #define SDMMC_MASK_TXDAVLIE 0x00100000U
7239 #define SDMMC_MASK_RXDAVLIE 0x00200000U
7240 #define SDMMC_MASK_SDIOITIE 0x00400000U
7242 /***************** Bit definition for SDMMC_FIFOCNT register *****************/
7243 #define SDMMC_FIFOCNT_FIFOCOUNT 0x00FFFFFFU
7245 /****************** Bit definition for SDMMC_FIFO register *******************/
7246 #define SDMMC_FIFO_FIFODATA 0xFFFFFFFFU
7248 /******************************************************************************/
7249 /* */
7250 /* Serial Peripheral Interface (SPI) */
7251 /* */
7252 /******************************************************************************/
7253 /******************* Bit definition for SPI_CR1 register ********************/
7254 #define SPI_CR1_CPHA 0x00000001U
7255 #define SPI_CR1_CPOL 0x00000002U
7256 #define SPI_CR1_MSTR 0x00000004U
7257 #define SPI_CR1_BR 0x00000038U
7258 #define SPI_CR1_BR_0 0x00000008U
7259 #define SPI_CR1_BR_1 0x00000010U
7260 #define SPI_CR1_BR_2 0x00000020U
7261 #define SPI_CR1_SPE 0x00000040U
7262 #define SPI_CR1_LSBFIRST 0x00000080U
7263 #define SPI_CR1_SSI 0x00000100U
7264 #define SPI_CR1_SSM 0x00000200U
7265 #define SPI_CR1_RXONLY 0x00000400U
7266 #define SPI_CR1_CRCL 0x00000800U
7267 #define SPI_CR1_CRCNEXT 0x00001000U
7268 #define SPI_CR1_CRCEN 0x00002000U
7269 #define SPI_CR1_BIDIOE 0x00004000U
7270 #define SPI_CR1_BIDIMODE 0x00008000U
7272 /******************* Bit definition for SPI_CR2 register ********************/
7273 #define SPI_CR2_RXDMAEN 0x00000001U
7274 #define SPI_CR2_TXDMAEN 0x00000002U
7275 #define SPI_CR2_SSOE 0x00000004U
7276 #define SPI_CR2_NSSP 0x00000008U
7277 #define SPI_CR2_FRF 0x00000010U
7278 #define SPI_CR2_ERRIE 0x00000020U
7279 #define SPI_CR2_RXNEIE 0x00000040U
7280 #define SPI_CR2_TXEIE 0x00000080U
7281 #define SPI_CR2_DS 0x00000F00U
7282 #define SPI_CR2_DS_0 0x00000100U
7283 #define SPI_CR2_DS_1 0x00000200U
7284 #define SPI_CR2_DS_2 0x00000400U
7285 #define SPI_CR2_DS_3 0x00000800U
7286 #define SPI_CR2_FRXTH 0x00001000U
7287 #define SPI_CR2_LDMARX 0x00002000U
7288 #define SPI_CR2_LDMATX 0x00004000U
7290 /******************** Bit definition for SPI_SR register ********************/
7291 #define SPI_SR_RXNE 0x00000001U
7292 #define SPI_SR_TXE 0x00000002U
7293 #define SPI_SR_CHSIDE 0x00000004U
7294 #define SPI_SR_UDR 0x00000008U
7295 #define SPI_SR_CRCERR 0x00000010U
7296 #define SPI_SR_MODF 0x00000020U
7297 #define SPI_SR_OVR 0x00000040U
7298 #define SPI_SR_BSY 0x00000080U
7299 #define SPI_SR_FRE 0x00000100U
7300 #define SPI_SR_FRLVL 0x00000600U
7301 #define SPI_SR_FRLVL_0 0x00000200U
7302 #define SPI_SR_FRLVL_1 0x00000400U
7303 #define SPI_SR_FTLVL 0x00001800U
7304 #define SPI_SR_FTLVL_0 0x00000800U
7305 #define SPI_SR_FTLVL_1 0x00001000U
7307 /******************** Bit definition for SPI_DR register ********************/
7308 #define SPI_DR_DR 0xFFFFU
7310 /******************* Bit definition for SPI_CRCPR register ******************/
7311 #define SPI_CRCPR_CRCPOLY 0xFFFFU
7313 /****************** Bit definition for SPI_RXCRCR register ******************/
7314 #define SPI_RXCRCR_RXCRC 0xFFFFU
7316 /****************** Bit definition for SPI_TXCRCR register ******************/
7317 #define SPI_TXCRCR_TXCRC 0xFFFFU
7319 /****************** Bit definition for SPI_I2SCFGR register *****************/
7320 #define SPI_I2SCFGR_CHLEN 0x00000001U
7321 #define SPI_I2SCFGR_DATLEN 0x00000006U
7322 #define SPI_I2SCFGR_DATLEN_0 0x00000002U
7323 #define SPI_I2SCFGR_DATLEN_1 0x00000004U
7324 #define SPI_I2SCFGR_CKPOL 0x00000008U
7325 #define SPI_I2SCFGR_I2SSTD 0x00000030U
7326 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U
7327 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U
7328 #define SPI_I2SCFGR_PCMSYNC 0x00000080U
7329 #define SPI_I2SCFGR_I2SCFG 0x00000300U
7330 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U
7331 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U
7332 #define SPI_I2SCFGR_I2SE 0x00000400U
7333 #define SPI_I2SCFGR_I2SMOD 0x00000800U
7334 #define SPI_I2SCFGR_ASTRTEN 0x00001000U
7336 /****************** Bit definition for SPI_I2SPR register *******************/
7337 #define SPI_I2SPR_I2SDIV 0x00FFU
7338 #define SPI_I2SPR_ODD 0x0100U
7339 #define SPI_I2SPR_MCKOE 0x0200U
7342 /******************************************************************************/
7343 /* */
7344 /* SYSCFG */
7345 /* */
7346 /******************************************************************************/
7347 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
7348 #define SYSCFG_MEMRMP_MEM_BOOT 0x00000001U
7350 #define SYSCFG_MEMRMP_SWP_FB 0x00000100U
7352 #define SYSCFG_MEMRMP_SWP_FMC 0x00000C00U
7353 #define SYSCFG_MEMRMP_SWP_FMC_0 0x00000400U
7354 #define SYSCFG_MEMRMP_SWP_FMC_1 0x00000800U
7355 
7356 /****************** Bit definition for SYSCFG_PMC register ******************/
7357 #define SYSCFG_PMC_I2C1_FMP 0x00000001U
7358 #define SYSCFG_PMC_I2C2_FMP 0x00000002U
7359 #define SYSCFG_PMC_I2C3_FMP 0x00000004U
7360 #define SYSCFG_PMC_I2C4_FMP 0x00000008U
7361 #define SYSCFG_PMC_I2C_PB6_FMP 0x00000010U
7362 #define SYSCFG_PMC_I2C_PB7_FMP 0x00000020U
7363 #define SYSCFG_PMC_I2C_PB8_FMP 0x00000040U
7364 #define SYSCFG_PMC_I2C_PB9_FMP 0x00000080U
7366 #define SYSCFG_PMC_ADCxDC2 0x00070000U
7367 #define SYSCFG_PMC_ADC1DC2 0x00010000U
7368 #define SYSCFG_PMC_ADC2DC2 0x00020000U
7369 #define SYSCFG_PMC_ADC3DC2 0x00040000U
7371 #define SYSCFG_PMC_MII_RMII_SEL 0x00800000U
7373 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
7374 #define SYSCFG_EXTICR1_EXTI0 0x000FU
7375 #define SYSCFG_EXTICR1_EXTI1 0x00F0U
7376 #define SYSCFG_EXTICR1_EXTI2 0x0F00U
7377 #define SYSCFG_EXTICR1_EXTI3 0xF000U
7381 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
7382 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
7383 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
7384 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
7385 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
7386 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
7387 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
7388 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
7389 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U
7390 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U
7391 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU
7396 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
7397 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
7398 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
7399 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
7400 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
7401 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
7402 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
7403 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
7404 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U
7405 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U
7406 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U
7411 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
7412 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
7413 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
7414 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
7415 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
7416 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
7417 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
7418 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
7419 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U
7420 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U
7421 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U
7426 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
7427 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
7428 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
7429 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
7430 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
7431 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
7432 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
7433 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
7434 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U
7435 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U
7436 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U
7438 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
7439 #define SYSCFG_EXTICR2_EXTI4 0x000FU
7440 #define SYSCFG_EXTICR2_EXTI5 0x00F0U
7441 #define SYSCFG_EXTICR2_EXTI6 0x0F00U
7442 #define SYSCFG_EXTICR2_EXTI7 0xF000U
7446 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
7447 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
7448 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
7449 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
7450 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
7451 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
7452 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
7453 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
7454 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U
7455 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U
7456 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU
7461 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
7462 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
7463 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
7464 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
7465 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
7466 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
7467 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
7468 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
7469 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U
7470 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U
7471 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U
7476 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
7477 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
7478 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
7479 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
7480 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
7481 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
7482 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
7483 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
7484 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U
7485 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U
7486 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U
7491 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
7492 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
7493 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
7494 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
7495 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
7496 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
7497 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
7498 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
7499 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U
7500 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U
7501 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U
7503 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
7504 #define SYSCFG_EXTICR3_EXTI8 0x000FU
7505 #define SYSCFG_EXTICR3_EXTI9 0x00F0U
7506 #define SYSCFG_EXTICR3_EXTI10 0x0F00U
7507 #define SYSCFG_EXTICR3_EXTI11 0xF000U
7512 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
7513 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
7514 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
7515 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
7516 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
7517 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
7518 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
7519 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
7520 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U
7521 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U
7526 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
7527 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
7528 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
7529 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
7530 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
7531 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
7532 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
7533 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
7534 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U
7535 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U
7540 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
7541 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
7542 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
7543 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
7544 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
7545 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
7546 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
7547 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
7548 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U
7549 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U
7554 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
7555 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
7556 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
7557 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
7558 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
7559 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
7560 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
7561 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
7562 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U
7563 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U
7566 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
7567 #define SYSCFG_EXTICR4_EXTI12 0x000FU
7568 #define SYSCFG_EXTICR4_EXTI13 0x00F0U
7569 #define SYSCFG_EXTICR4_EXTI14 0x0F00U
7570 #define SYSCFG_EXTICR4_EXTI15 0xF000U
7574 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
7575 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
7576 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
7577 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
7578 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
7579 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
7580 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
7581 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
7582 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U
7583 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U
7588 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
7589 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
7590 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
7591 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
7592 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
7593 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
7594 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
7595 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
7596 #define SYSCFG_EXTICR4_EXTI13_PI 0x0080U
7597 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0090U
7602 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
7603 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
7604 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
7605 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
7606 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
7607 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
7608 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
7609 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
7610 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U
7611 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U
7616 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
7617 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
7618 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
7619 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
7620 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
7621 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
7622 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
7623 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
7624 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U
7625 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U
7627 /****************** Bit definition for SYSCFG_CBR register ******************/
7628 #define SYSCFG_CBR_CLL 0x00000001U
7629 #define SYSCFG_CBR_PVDL 0x00000004U
7631 /****************** Bit definition for SYSCFG_CMPCR register ****************/
7632 #define SYSCFG_CMPCR_CMP_PD 0x00000001U
7633 #define SYSCFG_CMPCR_READY 0x00000100U
7635 /******************************************************************************/
7636 /* */
7637 /* TIM */
7638 /* */
7639 /******************************************************************************/
7640 /******************* Bit definition for TIM_CR1 register ********************/
7641 #define TIM_CR1_CEN 0x0001U
7642 #define TIM_CR1_UDIS 0x0002U
7643 #define TIM_CR1_URS 0x0004U
7644 #define TIM_CR1_OPM 0x0008U
7645 #define TIM_CR1_DIR 0x0010U
7647 #define TIM_CR1_CMS 0x0060U
7648 #define TIM_CR1_CMS_0 0x0020U
7649 #define TIM_CR1_CMS_1 0x0040U
7651 #define TIM_CR1_ARPE 0x0080U
7653 #define TIM_CR1_CKD 0x0300U
7654 #define TIM_CR1_CKD_0 0x0100U
7655 #define TIM_CR1_CKD_1 0x0200U
7656 #define TIM_CR1_UIFREMAP 0x0800U
7658 /******************* Bit definition for TIM_CR2 register ********************/
7659 #define TIM_CR2_CCPC 0x00000001U
7660 #define TIM_CR2_CCUS 0x00000004U
7661 #define TIM_CR2_CCDS 0x00000008U
7663 #define TIM_CR2_OIS5 0x00010000U
7664 #define TIM_CR2_OIS6 0x00040000U
7666 #define TIM_CR2_MMS 0x0070U
7667 #define TIM_CR2_MMS_0 0x0010U
7668 #define TIM_CR2_MMS_1 0x0020U
7669 #define TIM_CR2_MMS_2 0x0040U
7671 #define TIM_CR2_MMS2 0x00F00000U
7672 #define TIM_CR2_MMS2_0 0x00100000U
7673 #define TIM_CR2_MMS2_1 0x00200000U
7674 #define TIM_CR2_MMS2_2 0x00400000U
7675 #define TIM_CR2_MMS2_3 0x00800000U
7677 #define TIM_CR2_TI1S 0x0080U
7678 #define TIM_CR2_OIS1 0x0100U
7679 #define TIM_CR2_OIS1N 0x0200U
7680 #define TIM_CR2_OIS2 0x0400U
7681 #define TIM_CR2_OIS2N 0x0800U
7682 #define TIM_CR2_OIS3 0x1000U
7683 #define TIM_CR2_OIS3N 0x2000U
7684 #define TIM_CR2_OIS4 0x4000U
7686 /******************* Bit definition for TIM_SMCR register *******************/
7687 #define TIM_SMCR_SMS 0x00010007U
7688 #define TIM_SMCR_SMS_0 0x00000001U
7689 #define TIM_SMCR_SMS_1 0x00000002U
7690 #define TIM_SMCR_SMS_2 0x00000004U
7691 #define TIM_SMCR_SMS_3 0x00010000U
7692 #define TIM_SMCR_OCCS 0x00000008U
7694 #define TIM_SMCR_TS 0x0070U
7695 #define TIM_SMCR_TS_0 0x0010U
7696 #define TIM_SMCR_TS_1 0x0020U
7697 #define TIM_SMCR_TS_2 0x0040U
7699 #define TIM_SMCR_MSM 0x0080U
7701 #define TIM_SMCR_ETF 0x0F00U
7702 #define TIM_SMCR_ETF_0 0x0100U
7703 #define TIM_SMCR_ETF_1 0x0200U
7704 #define TIM_SMCR_ETF_2 0x0400U
7705 #define TIM_SMCR_ETF_3 0x0800U
7707 #define TIM_SMCR_ETPS 0x3000U
7708 #define TIM_SMCR_ETPS_0 0x1000U
7709 #define TIM_SMCR_ETPS_1 0x2000U
7711 #define TIM_SMCR_ECE 0x4000U
7712 #define TIM_SMCR_ETP 0x8000U
7714 /******************* Bit definition for TIM_DIER register *******************/
7715 #define TIM_DIER_UIE 0x0001U
7716 #define TIM_DIER_CC1IE 0x0002U
7717 #define TIM_DIER_CC2IE 0x0004U
7718 #define TIM_DIER_CC3IE 0x0008U
7719 #define TIM_DIER_CC4IE 0x0010U
7720 #define TIM_DIER_COMIE 0x0020U
7721 #define TIM_DIER_TIE 0x0040U
7722 #define TIM_DIER_BIE 0x0080U
7723 #define TIM_DIER_UDE 0x0100U
7724 #define TIM_DIER_CC1DE 0x0200U
7725 #define TIM_DIER_CC2DE 0x0400U
7726 #define TIM_DIER_CC3DE 0x0800U
7727 #define TIM_DIER_CC4DE 0x1000U
7728 #define TIM_DIER_COMDE 0x2000U
7729 #define TIM_DIER_TDE 0x4000U
7731 /******************** Bit definition for TIM_SR register ********************/
7732 #define TIM_SR_UIF 0x0001U
7733 #define TIM_SR_CC1IF 0x0002U
7734 #define TIM_SR_CC2IF 0x0004U
7735 #define TIM_SR_CC3IF 0x0008U
7736 #define TIM_SR_CC4IF 0x0010U
7737 #define TIM_SR_COMIF 0x0020U
7738 #define TIM_SR_TIF 0x0040U
7739 #define TIM_SR_BIF 0x0080U
7740 #define TIM_SR_B2IF 0x0100U
7741 #define TIM_SR_CC1OF 0x0200U
7742 #define TIM_SR_CC2OF 0x0400U
7743 #define TIM_SR_CC3OF 0x0800U
7744 #define TIM_SR_CC4OF 0x1000U
7746 /******************* Bit definition for TIM_EGR register ********************/
7747 #define TIM_EGR_UG 0x00000001U
7748 #define TIM_EGR_CC1G 0x00000002U
7749 #define TIM_EGR_CC2G 0x00000004U
7750 #define TIM_EGR_CC3G 0x00000008U
7751 #define TIM_EGR_CC4G 0x00000010U
7752 #define TIM_EGR_COMG 0x00000020U
7753 #define TIM_EGR_TG 0x00000040U
7754 #define TIM_EGR_BG 0x00000080U
7755 #define TIM_EGR_B2G 0x00000100U
7757 /****************** Bit definition for TIM_CCMR1 register *******************/
7758 #define TIM_CCMR1_CC1S 0x00000003U
7759 #define TIM_CCMR1_CC1S_0 0x00000001U
7760 #define TIM_CCMR1_CC1S_1 0x00000002U
7762 #define TIM_CCMR1_OC1FE 0x00000004U
7763 #define TIM_CCMR1_OC1PE 0x00000008U
7765 #define TIM_CCMR1_OC1M 0x00010070U
7766 #define TIM_CCMR1_OC1M_0 0x00000010U
7767 #define TIM_CCMR1_OC1M_1 0x00000020U
7768 #define TIM_CCMR1_OC1M_2 0x00000040U
7769 #define TIM_CCMR1_OC1M_3 0x00010000U
7771 #define TIM_CCMR1_OC1CE 0x00000080U
7773 #define TIM_CCMR1_CC2S 0x00000300U
7774 #define TIM_CCMR1_CC2S_0 0x00000100U
7775 #define TIM_CCMR1_CC2S_1 0x00000200U
7777 #define TIM_CCMR1_OC2FE 0x00000400U
7778 #define TIM_CCMR1_OC2PE 0x00000800U
7780 #define TIM_CCMR1_OC2M 0x01007000U
7781 #define TIM_CCMR1_OC2M_0 0x00001000U
7782 #define TIM_CCMR1_OC2M_1 0x00002000U
7783 #define TIM_CCMR1_OC2M_2 0x00004000U
7784 #define TIM_CCMR1_OC2M_3 0x01000000U
7786 #define TIM_CCMR1_OC2CE 0x00008000U
7788 /*----------------------------------------------------------------------------*/
7789 
7790 #define TIM_CCMR1_IC1PSC 0x000CU
7791 #define TIM_CCMR1_IC1PSC_0 0x0004U
7792 #define TIM_CCMR1_IC1PSC_1 0x0008U
7794 #define TIM_CCMR1_IC1F 0x00F0U
7795 #define TIM_CCMR1_IC1F_0 0x0010U
7796 #define TIM_CCMR1_IC1F_1 0x0020U
7797 #define TIM_CCMR1_IC1F_2 0x0040U
7798 #define TIM_CCMR1_IC1F_3 0x0080U
7800 #define TIM_CCMR1_IC2PSC 0x0C00U
7801 #define TIM_CCMR1_IC2PSC_0 0x0400U
7802 #define TIM_CCMR1_IC2PSC_1 0x0800U
7804 #define TIM_CCMR1_IC2F 0xF000U
7805 #define TIM_CCMR1_IC2F_0 0x1000U
7806 #define TIM_CCMR1_IC2F_1 0x2000U
7807 #define TIM_CCMR1_IC2F_2 0x4000U
7808 #define TIM_CCMR1_IC2F_3 0x8000U
7810 /****************** Bit definition for TIM_CCMR2 register *******************/
7811 #define TIM_CCMR2_CC3S 0x00000003U
7812 #define TIM_CCMR2_CC3S_0 0x00000001U
7813 #define TIM_CCMR2_CC3S_1 0x00000002U
7815 #define TIM_CCMR2_OC3FE 0x00000004U
7816 #define TIM_CCMR2_OC3PE 0x00000008U
7818 #define TIM_CCMR2_OC3M 0x00010070U
7819 #define TIM_CCMR2_OC3M_0 0x00000010U
7820 #define TIM_CCMR2_OC3M_1 0x00000020U
7821 #define TIM_CCMR2_OC3M_2 0x00000040U
7822 #define TIM_CCMR2_OC3M_3 0x00010000U
7826 #define TIM_CCMR2_OC3CE 0x00000080U
7828 #define TIM_CCMR2_CC4S 0x00000300U
7829 #define TIM_CCMR2_CC4S_0 0x00000100U
7830 #define TIM_CCMR2_CC4S_1 0x00000200U
7832 #define TIM_CCMR2_OC4FE 0x00000400U
7833 #define TIM_CCMR2_OC4PE 0x00000800U
7835 #define TIM_CCMR2_OC4M 0x01007000U
7836 #define TIM_CCMR2_OC4M_0 0x00001000U
7837 #define TIM_CCMR2_OC4M_1 0x00002000U
7838 #define TIM_CCMR2_OC4M_2 0x00004000U
7839 #define TIM_CCMR2_OC4M_3 0x01000000U
7841 #define TIM_CCMR2_OC4CE 0x8000U
7843 /*----------------------------------------------------------------------------*/
7844 
7845 #define TIM_CCMR2_IC3PSC 0x000CU
7846 #define TIM_CCMR2_IC3PSC_0 0x0004U
7847 #define TIM_CCMR2_IC3PSC_1 0x0008U
7849 #define TIM_CCMR2_IC3F 0x00F0U
7850 #define TIM_CCMR2_IC3F_0 0x0010U
7851 #define TIM_CCMR2_IC3F_1 0x0020U
7852 #define TIM_CCMR2_IC3F_2 0x0040U
7853 #define TIM_CCMR2_IC3F_3 0x0080U
7855 #define TIM_CCMR2_IC4PSC 0x0C00U
7856 #define TIM_CCMR2_IC4PSC_0 0x0400U
7857 #define TIM_CCMR2_IC4PSC_1 0x0800U
7859 #define TIM_CCMR2_IC4F 0xF000U
7860 #define TIM_CCMR2_IC4F_0 0x1000U
7861 #define TIM_CCMR2_IC4F_1 0x2000U
7862 #define TIM_CCMR2_IC4F_2 0x4000U
7863 #define TIM_CCMR2_IC4F_3 0x8000U
7865 /******************* Bit definition for TIM_CCER register *******************/
7866 #define TIM_CCER_CC1E 0x00000001U
7867 #define TIM_CCER_CC1P 0x00000002U
7868 #define TIM_CCER_CC1NE 0x00000004U
7869 #define TIM_CCER_CC1NP 0x00000008U
7870 #define TIM_CCER_CC2E 0x00000010U
7871 #define TIM_CCER_CC2P 0x00000020U
7872 #define TIM_CCER_CC2NE 0x00000040U
7873 #define TIM_CCER_CC2NP 0x00000080U
7874 #define TIM_CCER_CC3E 0x00000100U
7875 #define TIM_CCER_CC3P 0x00000200U
7876 #define TIM_CCER_CC3NE 0x00000400U
7877 #define TIM_CCER_CC3NP 0x00000800U
7878 #define TIM_CCER_CC4E 0x00001000U
7879 #define TIM_CCER_CC4P 0x00002000U
7880 #define TIM_CCER_CC4NP 0x00008000U
7881 #define TIM_CCER_CC5E 0x00010000U
7882 #define TIM_CCER_CC5P 0x00020000U
7883 #define TIM_CCER_CC6E 0x00100000U
7884 #define TIM_CCER_CC6P 0x00200000U
7887 /******************* Bit definition for TIM_CNT register ********************/
7888 #define TIM_CNT_CNT 0xFFFFU
7890 /******************* Bit definition for TIM_PSC register ********************/
7891 #define TIM_PSC_PSC 0xFFFFU
7893 /******************* Bit definition for TIM_ARR register ********************/
7894 #define TIM_ARR_ARR 0xFFFFU
7896 /******************* Bit definition for TIM_RCR register ********************/
7897 #define TIM_RCR_REP ((uint8_t)0xFFU)
7899 /******************* Bit definition for TIM_CCR1 register *******************/
7900 #define TIM_CCR1_CCR1 0xFFFFU
7902 /******************* Bit definition for TIM_CCR2 register *******************/
7903 #define TIM_CCR2_CCR2 0xFFFFU
7905 /******************* Bit definition for TIM_CCR3 register *******************/
7906 #define TIM_CCR3_CCR3 0xFFFFU
7908 /******************* Bit definition for TIM_CCR4 register *******************/
7909 #define TIM_CCR4_CCR4 0xFFFFU
7911 /******************* Bit definition for TIM_BDTR register *******************/
7912 #define TIM_BDTR_DTG 0x000000FFU
7913 #define TIM_BDTR_DTG_0 0x00000001U
7914 #define TIM_BDTR_DTG_1 0x00000002U
7915 #define TIM_BDTR_DTG_2 0x00000004U
7916 #define TIM_BDTR_DTG_3 0x00000008U
7917 #define TIM_BDTR_DTG_4 0x00000010U
7918 #define TIM_BDTR_DTG_5 0x00000020U
7919 #define TIM_BDTR_DTG_6 0x00000040U
7920 #define TIM_BDTR_DTG_7 0x00000080U
7922 #define TIM_BDTR_LOCK 0x00000300U
7923 #define TIM_BDTR_LOCK_0 0x00000100U
7924 #define TIM_BDTR_LOCK_1 0x00000200U
7926 #define TIM_BDTR_OSSI 0x00000400U
7927 #define TIM_BDTR_OSSR 0x00000800U
7928 #define TIM_BDTR_BKE 0x00001000U
7929 #define TIM_BDTR_BKP 0x00002000U
7930 #define TIM_BDTR_AOE 0x00004000U
7931 #define TIM_BDTR_MOE 0x00008000U
7932 #define TIM_BDTR_BKF 0x000F0000U
7933 #define TIM_BDTR_BK2F 0x00F00000U
7934 #define TIM_BDTR_BK2E 0x01000000U
7935 #define TIM_BDTR_BK2P 0x02000000U
7937 /******************* Bit definition for TIM_DCR register ********************/
7938 #define TIM_DCR_DBA 0x001FU
7939 #define TIM_DCR_DBA_0 0x0001U
7940 #define TIM_DCR_DBA_1 0x0002U
7941 #define TIM_DCR_DBA_2 0x0004U
7942 #define TIM_DCR_DBA_3 0x0008U
7943 #define TIM_DCR_DBA_4 0x0010U
7945 #define TIM_DCR_DBL 0x1F00U
7946 #define TIM_DCR_DBL_0 0x0100U
7947 #define TIM_DCR_DBL_1 0x0200U
7948 #define TIM_DCR_DBL_2 0x0400U
7949 #define TIM_DCR_DBL_3 0x0800U
7950 #define TIM_DCR_DBL_4 0x1000U
7952 /******************* Bit definition for TIM_DMAR register *******************/
7953 #define TIM_DMAR_DMAB 0xFFFFU
7955 /******************* Bit definition for TIM_OR regiter *********************/
7956 #define TIM_OR_TI4_RMP 0x00C0U
7957 #define TIM_OR_TI4_RMP_0 0x0040U
7958 #define TIM_OR_TI4_RMP_1 0x0080U
7959 #define TIM_OR_ITR1_RMP 0x0C00U
7960 #define TIM_OR_ITR1_RMP_0 0x0400U
7961 #define TIM_OR_ITR1_RMP_1 0x0800U
7963 /****************** Bit definition for TIM_CCMR3 register *******************/
7964 #define TIM_CCMR3_OC5FE 0x00000004U
7965 #define TIM_CCMR3_OC5PE 0x00000008U
7967 #define TIM_CCMR3_OC5M 0x00010070U
7968 #define TIM_CCMR3_OC5M_0 0x00000010U
7969 #define TIM_CCMR3_OC5M_1 0x00000020U
7970 #define TIM_CCMR3_OC5M_2 0x00000040U
7971 #define TIM_CCMR3_OC5M_3 0x00010000U
7973 #define TIM_CCMR3_OC5CE 0x00000080U
7975 #define TIM_CCMR3_OC6FE 0x00000400U
7976 #define TIM_CCMR3_OC6PE 0x00000800U
7978 #define TIM_CCMR3_OC6M 0x01007000U
7979 #define TIM_CCMR3_OC6M_0 0x00001000U
7980 #define TIM_CCMR3_OC6M_1 0x00002000U
7981 #define TIM_CCMR3_OC6M_2 0x00004000U
7982 #define TIM_CCMR3_OC6M_3 0x01000000U
7984 #define TIM_CCMR3_OC6CE 0x00008000U
7986 /******************* Bit definition for TIM_CCR5 register *******************/
7987 #define TIM_CCR5_CCR5 0xFFFFFFFFU
7988 #define TIM_CCR5_GC5C1 0x20000000U
7989 #define TIM_CCR5_GC5C2 0x40000000U
7990 #define TIM_CCR5_GC5C3 0x80000000U
7992 /******************* Bit definition for TIM_CCR6 register *******************/
7993 #define TIM_CCR6_CCR6 ((uint16_t)0xFFFFU)
7995 /******************* Bit definition for TIM1_AF1 register *******************/
7996 #define TIM1_AF1_BKINE 0x00000001U
7997 #define TIM1_AF1_BKDF1BKE 0x00000100U
7999 /******************* Bit definition for TIM1_AF2 register *******************/
8000 #define TIM1_AF2_BK2INE 0x00000001U
8001 #define TIM1_AF2_BK2DF1BKE 0x00000100U
8003 /******************* Bit definition for TIM8_AF1 register *******************/
8004 #define TIM8_AF1_BKINE 0x00000001U
8005 #define TIM8_AF1_BKDF1BKE 0x00000100U
8007 /******************* Bit definition for TIM8_AF2 register *******************/
8008 #define TIM8_AF2_BK2INE 0x00000001U
8009 #define TIM8_AF2_BK2DF1BKE 0x00000100U
8011 /******************************************************************************/
8012 /* */
8013 /* Low Power Timer (LPTIM) */
8014 /* */
8015 /******************************************************************************/
8016 /****************** Bit definition for LPTIM_ISR register *******************/
8017 #define LPTIM_ISR_CMPM 0x00000001U
8018 #define LPTIM_ISR_ARRM 0x00000002U
8019 #define LPTIM_ISR_EXTTRIG 0x00000004U
8020 #define LPTIM_ISR_CMPOK 0x00000008U
8021 #define LPTIM_ISR_ARROK 0x00000010U
8022 #define LPTIM_ISR_UP 0x00000020U
8023 #define LPTIM_ISR_DOWN 0x00000040U
8025 /****************** Bit definition for LPTIM_ICR register *******************/
8026 #define LPTIM_ICR_CMPMCF 0x00000001U
8027 #define LPTIM_ICR_ARRMCF 0x00000002U
8028 #define LPTIM_ICR_EXTTRIGCF 0x00000004U
8029 #define LPTIM_ICR_CMPOKCF 0x00000008U
8030 #define LPTIM_ICR_ARROKCF 0x00000010U
8031 #define LPTIM_ICR_UPCF 0x00000020U
8032 #define LPTIM_ICR_DOWNCF 0x00000040U
8034 /****************** Bit definition for LPTIM_IER register *******************/
8035 #define LPTIM_IER_CMPMIE 0x00000001U
8036 #define LPTIM_IER_ARRMIE 0x00000002U
8037 #define LPTIM_IER_EXTTRIGIE 0x00000004U
8038 #define LPTIM_IER_CMPOKIE 0x00000008U
8039 #define LPTIM_IER_ARROKIE 0x00000010U
8040 #define LPTIM_IER_UPIE 0x00000020U
8041 #define LPTIM_IER_DOWNIE 0x00000040U
8043 /****************** Bit definition for LPTIM_CFGR register*******************/
8044 #define LPTIM_CFGR_CKSEL 0x00000001U
8046 #define LPTIM_CFGR_CKPOL 0x00000006U
8047 #define LPTIM_CFGR_CKPOL_0 0x00000002U
8048 #define LPTIM_CFGR_CKPOL_1 0x00000004U
8050 #define LPTIM_CFGR_CKFLT 0x00000018U
8051 #define LPTIM_CFGR_CKFLT_0 0x00000008U
8052 #define LPTIM_CFGR_CKFLT_1 0x00000010U
8054 #define LPTIM_CFGR_TRGFLT 0x000000C0U
8055 #define LPTIM_CFGR_TRGFLT_0 0x00000040U
8056 #define LPTIM_CFGR_TRGFLT_1 0x00000080U
8058 #define LPTIM_CFGR_PRESC 0x00000E00U
8059 #define LPTIM_CFGR_PRESC_0 0x00000200U
8060 #define LPTIM_CFGR_PRESC_1 0x00000400U
8061 #define LPTIM_CFGR_PRESC_2 0x00000800U
8063 #define LPTIM_CFGR_TRIGSEL 0x0000E000U
8064 #define LPTIM_CFGR_TRIGSEL_0 0x00002000U
8065 #define LPTIM_CFGR_TRIGSEL_1 0x00004000U
8066 #define LPTIM_CFGR_TRIGSEL_2 0x00008000U
8068 #define LPTIM_CFGR_TRIGEN 0x00060000U
8069 #define LPTIM_CFGR_TRIGEN_0 0x00020000U
8070 #define LPTIM_CFGR_TRIGEN_1 0x00040000U
8072 #define LPTIM_CFGR_TIMOUT 0x00080000U
8073 #define LPTIM_CFGR_WAVE 0x00100000U
8074 #define LPTIM_CFGR_WAVPOL 0x00200000U
8075 #define LPTIM_CFGR_PRELOAD 0x00400000U
8076 #define LPTIM_CFGR_COUNTMODE 0x00800000U
8077 #define LPTIM_CFGR_ENC 0x01000000U
8079 /****************** Bit definition for LPTIM_CR register ********************/
8080 #define LPTIM_CR_ENABLE 0x00000001U
8081 #define LPTIM_CR_SNGSTRT 0x00000002U
8082 #define LPTIM_CR_CNTSTRT 0x00000004U
8084 /****************** Bit definition for LPTIM_CMP register *******************/
8085 #define LPTIM_CMP_CMP 0x0000FFFFU
8087 /****************** Bit definition for LPTIM_ARR register *******************/
8088 #define LPTIM_ARR_ARR 0x0000FFFFU
8090 /****************** Bit definition for LPTIM_CNT register *******************/
8091 #define LPTIM_CNT_CNT 0x0000FFFFU
8092 /******************************************************************************/
8093 /* */
8094 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
8095 /* */
8096 /******************************************************************************/
8097 /****************** Bit definition for USART_CR1 register *******************/
8098 #define USART_CR1_UE 0x00000001U
8099 #define USART_CR1_RE 0x00000004U
8100 #define USART_CR1_TE 0x00000008U
8101 #define USART_CR1_IDLEIE 0x00000010U
8102 #define USART_CR1_RXNEIE 0x00000020U
8103 #define USART_CR1_TCIE 0x00000040U
8104 #define USART_CR1_TXEIE 0x00000080U
8105 #define USART_CR1_PEIE 0x00000100U
8106 #define USART_CR1_PS 0x00000200U
8107 #define USART_CR1_PCE 0x00000400U
8108 #define USART_CR1_WAKE 0x00000800U
8109 #define USART_CR1_M 0x10001000U
8110 #define USART_CR1_M_0 0x00001000U
8111 #define USART_CR1_MME 0x00002000U
8112 #define USART_CR1_CMIE 0x00004000U
8113 #define USART_CR1_OVER8 0x00008000U
8114 #define USART_CR1_DEDT 0x001F0000U
8115 #define USART_CR1_DEDT_0 0x00010000U
8116 #define USART_CR1_DEDT_1 0x00020000U
8117 #define USART_CR1_DEDT_2 0x00040000U
8118 #define USART_CR1_DEDT_3 0x00080000U
8119 #define USART_CR1_DEDT_4 0x00100000U
8120 #define USART_CR1_DEAT 0x03E00000U
8121 #define USART_CR1_DEAT_0 0x00200000U
8122 #define USART_CR1_DEAT_1 0x00400000U
8123 #define USART_CR1_DEAT_2 0x00800000U
8124 #define USART_CR1_DEAT_3 0x01000000U
8125 #define USART_CR1_DEAT_4 0x02000000U
8126 #define USART_CR1_RTOIE 0x04000000U
8127 #define USART_CR1_EOBIE 0x08000000U
8128 #define USART_CR1_M_1 0x10000000U
8130 /****************** Bit definition for USART_CR2 register *******************/
8131 #define USART_CR2_ADDM7 0x00000010U
8132 #define USART_CR2_LBDL 0x00000020U
8133 #define USART_CR2_LBDIE 0x00000040U
8134 #define USART_CR2_LBCL 0x00000100U
8135 #define USART_CR2_CPHA 0x00000200U
8136 #define USART_CR2_CPOL 0x00000400U
8137 #define USART_CR2_CLKEN 0x00000800U
8138 #define USART_CR2_STOP 0x00003000U
8139 #define USART_CR2_STOP_0 0x00001000U
8140 #define USART_CR2_STOP_1 0x00002000U
8141 #define USART_CR2_LINEN 0x00004000U
8142 #define USART_CR2_SWAP 0x00008000U
8143 #define USART_CR2_RXINV 0x00010000U
8144 #define USART_CR2_TXINV 0x00020000U
8145 #define USART_CR2_DATAINV 0x00040000U
8146 #define USART_CR2_MSBFIRST 0x00080000U
8147 #define USART_CR2_ABREN 0x00100000U
8148 #define USART_CR2_ABRMODE 0x00600000U
8149 #define USART_CR2_ABRMODE_0 0x00200000U
8150 #define USART_CR2_ABRMODE_1 0x00400000U
8151 #define USART_CR2_RTOEN 0x00800000U
8152 #define USART_CR2_ADD 0xFF000000U
8154 /****************** Bit definition for USART_CR3 register *******************/
8155 #define USART_CR3_EIE 0x00000001U
8156 #define USART_CR3_IREN 0x00000002U
8157 #define USART_CR3_IRLP 0x00000004U
8158 #define USART_CR3_HDSEL 0x00000008U
8159 #define USART_CR3_NACK 0x00000010U
8160 #define USART_CR3_SCEN 0x00000020U
8161 #define USART_CR3_DMAR 0x00000040U
8162 #define USART_CR3_DMAT 0x00000080U
8163 #define USART_CR3_RTSE 0x00000100U
8164 #define USART_CR3_CTSE 0x00000200U
8165 #define USART_CR3_CTSIE 0x00000400U
8166 #define USART_CR3_ONEBIT 0x00000800U
8167 #define USART_CR3_OVRDIS 0x00001000U
8168 #define USART_CR3_DDRE 0x00002000U
8169 #define USART_CR3_DEM 0x00004000U
8170 #define USART_CR3_DEP 0x00008000U
8171 #define USART_CR3_SCARCNT 0x000E0000U
8172 #define USART_CR3_SCARCNT_0 0x00020000U
8173 #define USART_CR3_SCARCNT_1 0x00040000U
8174 #define USART_CR3_SCARCNT_2 0x00080000U
8177 /****************** Bit definition for USART_BRR register *******************/
8178 #define USART_BRR_DIV_FRACTION 0x000FU
8179 #define USART_BRR_DIV_MANTISSA 0xFFF0U
8181 /****************** Bit definition for USART_GTPR register ******************/
8182 #define USART_GTPR_PSC 0x00FFU
8183 #define USART_GTPR_GT 0xFF00U
8186 /******************* Bit definition for USART_RTOR register *****************/
8187 #define USART_RTOR_RTO 0x00FFFFFFU
8188 #define USART_RTOR_BLEN 0xFF000000U
8190 /******************* Bit definition for USART_RQR register ******************/
8191 #define USART_RQR_ABRRQ 0x0001U
8192 #define USART_RQR_SBKRQ 0x0002U
8193 #define USART_RQR_MMRQ 0x0004U
8194 #define USART_RQR_RXFRQ 0x0008U
8195 #define USART_RQR_TXFRQ 0x0010U
8197 /******************* Bit definition for USART_ISR register ******************/
8198 #define USART_ISR_PE 0x00000001U
8199 #define USART_ISR_FE 0x00000002U
8200 #define USART_ISR_NE 0x00000004U
8201 #define USART_ISR_ORE 0x00000008U
8202 #define USART_ISR_IDLE 0x00000010U
8203 #define USART_ISR_RXNE 0x00000020U
8204 #define USART_ISR_TC 0x00000040U
8205 #define USART_ISR_TXE 0x00000080U
8206 #define USART_ISR_LBDF 0x00000100U
8207 #define USART_ISR_CTSIF 0x00000200U
8208 #define USART_ISR_CTS 0x00000400U
8209 #define USART_ISR_RTOF 0x00000800U
8210 #define USART_ISR_EOBF 0x00001000U
8211 #define USART_ISR_ABRE 0x00004000U
8212 #define USART_ISR_ABRF 0x00008000U
8213 #define USART_ISR_BUSY 0x00010000U
8214 #define USART_ISR_CMF 0x00020000U
8215 #define USART_ISR_SBKF 0x00040000U
8216 #define USART_ISR_RWU 0x00080000U
8217 #define USART_ISR_WUF 0x00100000U
8218 #define USART_ISR_TEACK 0x00200000U
8219 #define USART_ISR_REACK 0x00400000U
8222 /******************* Bit definition for USART_ICR register ******************/
8223 #define USART_ICR_PECF 0x00000001U
8224 #define USART_ICR_FECF 0x00000002U
8225 #define USART_ICR_NCF 0x00000004U
8226 #define USART_ICR_ORECF 0x00000008U
8227 #define USART_ICR_IDLECF 0x00000010U
8228 #define USART_ICR_TCCF 0x00000040U
8229 #define USART_ICR_LBDCF 0x00000100U
8230 #define USART_ICR_CTSCF 0x00000200U
8231 #define USART_ICR_RTOCF 0x00000800U
8232 #define USART_ICR_EOBCF 0x00001000U
8233 #define USART_ICR_CMCF 0x00020000U
8234 #define USART_ICR_WUCF 0x00100000U
8236 /******************* Bit definition for USART_RDR register ******************/
8237 #define USART_RDR_RDR 0x01FFU
8239 /******************* Bit definition for USART_TDR register ******************/
8240 #define USART_TDR_TDR 0x01FFU
8242 /******************************************************************************/
8243 /* */
8244 /* Window WATCHDOG */
8245 /* */
8246 /******************************************************************************/
8247 /******************* Bit definition for WWDG_CR register ********************/
8248 #define WWDG_CR_T 0x7FU
8249 #define WWDG_CR_T_0 0x01U
8250 #define WWDG_CR_T_1 0x02U
8251 #define WWDG_CR_T_2 0x04U
8252 #define WWDG_CR_T_3 0x08U
8253 #define WWDG_CR_T_4 0x10U
8254 #define WWDG_CR_T_5 0x20U
8255 #define WWDG_CR_T_6 0x40U
8258 #define WWDG_CR_WDGA 0x80U
8260 /******************* Bit definition for WWDG_CFR register *******************/
8261 #define WWDG_CFR_W 0x007FU
8262 #define WWDG_CFR_W_0 0x0001U
8263 #define WWDG_CFR_W_1 0x0002U
8264 #define WWDG_CFR_W_2 0x0004U
8265 #define WWDG_CFR_W_3 0x0008U
8266 #define WWDG_CFR_W_4 0x0010U
8267 #define WWDG_CFR_W_5 0x0020U
8268 #define WWDG_CFR_W_6 0x0040U
8271 #define WWDG_CFR_WDGTB 0x0180U
8272 #define WWDG_CFR_WDGTB_0 0x0080U
8273 #define WWDG_CFR_WDGTB_1 0x0100U
8276 #define WWDG_CFR_EWI 0x0200U
8278 /******************* Bit definition for WWDG_SR register ********************/
8279 #define WWDG_SR_EWIF 0x01U
8281 /******************************************************************************/
8282 /* */
8283 /* DBG */
8284 /* */
8285 /******************************************************************************/
8286 /******************** Bit definition for DBGMCU_IDCODE register *************/
8287 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
8288 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
8289 
8290 /******************** Bit definition for DBGMCU_CR register *****************/
8291 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
8292 #define DBGMCU_CR_DBG_STOP 0x00000002U
8293 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
8294 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
8295 
8296 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
8297 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U
8298 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U
8300 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
8301 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
8302 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
8303 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
8304 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
8305 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
8306 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
8307 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
8308 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
8309 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
8310 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
8311 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
8312 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
8313 #define DBGMCU_APB1_FZ_DBG_CAN3_STOP 0x00002000U
8314 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
8315 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
8316 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
8317 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
8318 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
8319 
8320 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
8321 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
8322 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
8323 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
8324 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
8325 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
8326 
8327 /******************************************************************************/
8328 /* */
8329 /* Ethernet MAC Registers bits definitions */
8330 /* */
8331 /******************************************************************************/
8332 /* Bit definition for Ethernet MAC Control Register register */
8333 #define ETH_MACCR_WD 0x00800000U /* Watchdog disable */
8334 #define ETH_MACCR_JD 0x00400000U /* Jabber disable */
8335 #define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */
8336 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
8337 #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
8338 #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
8339 #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
8340 #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
8341 #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
8342 #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
8343 #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
8344 #define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */
8345 #define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */
8346 #define ETH_MACCR_ROD 0x00002000U /* Receive own disable */
8347 #define ETH_MACCR_LM 0x00001000U /* loopback mode */
8348 #define ETH_MACCR_DM 0x00000800U /* Duplex mode */
8349 #define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */
8350 #define ETH_MACCR_RD 0x00000200U /* Retry disable */
8351 #define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */
8352 #define ETH_MACCR_BL 0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling
8353  a transmission attempt during retries after a collision: 0 =< r <2^k */
8354 #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
8355 #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
8356 #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
8357 #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
8358 #define ETH_MACCR_DC 0x00000010U /* Defferal check */
8359 #define ETH_MACCR_TE 0x00000008U /* Transmitter enable */
8360 #define ETH_MACCR_RE 0x00000004U /* Receiver enable */
8361 
8362 /* Bit definition for Ethernet MAC Frame Filter Register */
8363 #define ETH_MACFFR_RA 0x80000000U /* Receive all */
8364 #define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */
8365 #define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */
8366 #define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */
8367 #define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */
8368 #define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */
8369 #define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
8370 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
8371 #define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */
8372 #define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */
8373 #define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */
8374 #define ETH_MACFFR_HM 0x00000004U /* Hash multicast */
8375 #define ETH_MACFFR_HU 0x00000002U /* Hash unicast */
8376 #define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */
8377 
8378 /* Bit definition for Ethernet MAC Hash Table High Register */
8379 #define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */
8380 
8381 /* Bit definition for Ethernet MAC Hash Table Low Register */
8382 #define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */
8383 
8384 /* Bit definition for Ethernet MAC MII Address Register */
8385 #define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */
8386 #define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */
8387 #define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */
8388 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
8389 #define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
8390 #define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
8391 #define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
8392 #define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
8393 #define ETH_MACMIIAR_MW 0x00000002U /* MII write */
8394 #define ETH_MACMIIAR_MB 0x00000001U /* MII busy */
8395 
8396 /* Bit definition for Ethernet MAC MII Data Register */
8397 #define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */
8398 
8399 /* Bit definition for Ethernet MAC Flow Control Register */
8400 #define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */
8401 #define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */
8402 #define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */
8403 #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
8404 #define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */
8405 #define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */
8406 #define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */
8407 #define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */
8408 #define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */
8409 #define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */
8410 #define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */
8411 
8412 /* Bit definition for Ethernet MAC VLAN Tag Register */
8413 #define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */
8414 #define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */
8415 
8416 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
8417 #define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */
8418 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
8419  Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
8420 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
8421  Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
8422  Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
8423  Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
8424  Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
8425  RSVD - Filter1 Command - RSVD - Filter0 Command
8426  Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
8427  Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
8428  Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
8429 
8430 /* Bit definition for Ethernet MAC PMT Control and Status Register */
8431 #define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
8432 #define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */
8433 #define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */
8434 #define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */
8435 #define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */
8436 #define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */
8437 #define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */
8438 
8439 /* Bit definition for Ethernet MAC Status Register */
8440 #define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */
8441 #define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */
8442 #define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */
8443 #define ETH_MACSR_MMCS 0x00000010U /* MMC status */
8444 #define ETH_MACSR_PMTS 0x00000008U /* PMT status */
8445 
8446 /* Bit definition for Ethernet MAC Interrupt Mask Register */
8447 #define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */
8448 #define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */
8449 
8450 /* Bit definition for Ethernet MAC Address0 High Register */
8451 #define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */
8452 
8453 /* Bit definition for Ethernet MAC Address0 Low Register */
8454 #define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */
8455 
8456 /* Bit definition for Ethernet MAC Address1 High Register */
8457 #define ETH_MACA1HR_AE 0x80000000U /* Address enable */
8458 #define ETH_MACA1HR_SA 0x40000000U /* Source address */
8459 #define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
8460  #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
8461  #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
8462  #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
8463  #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
8464  #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
8465  #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
8466 #define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */
8467 
8468 /* Bit definition for Ethernet MAC Address1 Low Register */
8469 #define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */
8470 
8471 /* Bit definition for Ethernet MAC Address2 High Register */
8472 #define ETH_MACA2HR_AE 0x80000000U /* Address enable */
8473 #define ETH_MACA2HR_SA 0x40000000U /* Source address */
8474 #define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */
8475  #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
8476  #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
8477  #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
8478  #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
8479  #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
8480  #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
8481 #define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */
8482 
8483 /* Bit definition for Ethernet MAC Address2 Low Register */
8484 #define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */
8485 
8486 /* Bit definition for Ethernet MAC Address3 High Register */
8487 #define ETH_MACA3HR_AE 0x80000000U /* Address enable */
8488 #define ETH_MACA3HR_SA 0x40000000U /* Source address */
8489 #define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */
8490  #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
8491  #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
8492  #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
8493  #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
8494  #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
8495  #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
8496 #define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */
8497 
8498 /* Bit definition for Ethernet MAC Address3 Low Register */
8499 #define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */
8500 
8501 /******************************************************************************/
8502 /* Ethernet MMC Registers bits definition */
8503 /******************************************************************************/
8504 
8505 /* Bit definition for Ethernet MMC Contol Register */
8506 #define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */
8507 #define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */
8508 #define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */
8509 #define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */
8510 #define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */
8511 #define ETH_MMCCR_CR 0x00000001U /* Counters Reset */
8512 
8513 /* Bit definition for Ethernet MMC Receive Interrupt Register */
8514 #define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
8515 #define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
8516 #define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
8517 
8518 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
8519 #define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
8520 #define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
8521 #define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
8522 
8523 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
8524 #define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
8525 #define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
8526 #define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
8527 
8528 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
8529 #define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
8530 #define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
8531 #define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
8532 
8533 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
8534 #define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
8535 
8536 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
8537 #define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
8538 
8539 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
8540 #define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */
8541 
8542 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
8543 #define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */
8544 
8545 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
8546 #define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
8547 
8548 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
8549 #define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */
8550 
8551 /******************************************************************************/
8552 /* Ethernet PTP Registers bits definition */
8553 /******************************************************************************/
8554 
8555 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
8556 #define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */
8557 #define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */
8558 #define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */
8559 #define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */
8560 #define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */
8561 #define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
8562 #define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
8563 #define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */
8564 #define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */
8565 
8566 #define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */
8567 #define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */
8568 #define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */
8569 #define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */
8570 #define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */
8571 #define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */
8572 
8573 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
8574 #define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */
8575 
8576 /* Bit definition for Ethernet PTP Time Stamp High Register */
8577 #define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */
8578 
8579 /* Bit definition for Ethernet PTP Time Stamp Low Register */
8580 #define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */
8581 #define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */
8582 
8583 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
8584 #define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */
8585 
8586 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
8587 #define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */
8588 #define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */
8589 
8590 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
8591 #define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */
8592 
8593 /* Bit definition for Ethernet PTP Target Time High Register */
8594 #define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */
8595 
8596 /* Bit definition for Ethernet PTP Target Time Low Register */
8597 #define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */
8598 
8599 /* Bit definition for Ethernet PTP Time Stamp Status Register */
8600 #define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */
8601 #define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */
8602 
8603 /******************************************************************************/
8604 /* Ethernet DMA Registers bits definition */
8605 /******************************************************************************/
8606 
8607 /* Bit definition for Ethernet DMA Bus Mode Register */
8608 #define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */
8609 #define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */
8610 #define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */
8611 #define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */
8612  #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
8613  #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
8614  #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
8615  #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
8616  #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
8617  #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
8618  #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
8619  #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
8620  #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
8621  #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
8622  #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
8623  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
8624 #define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */
8625 #define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */
8626  #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
8627  #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
8628  #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
8629  #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
8630 #define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */
8631  #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
8632  #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
8633  #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
8634  #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
8635  #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
8636  #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
8637  #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
8638  #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
8639  #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
8640  #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
8641  #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
8642  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
8643 #define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */
8644 #define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */
8645 #define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */
8646 #define ETH_DMABMR_SR 0x00000001U /* Software reset */
8647 
8648 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
8649 #define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */
8650 
8651 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
8652 #define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */
8653 
8654 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
8655 #define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */
8656 
8657 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
8658 #define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */
8659 
8660 /* Bit definition for Ethernet DMA Status Register */
8661 #define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */
8662 #define ETH_DMASR_PMTS 0x10000000U /* PMT status */
8663 #define ETH_DMASR_MMCS 0x08000000U /* MMC status */
8664 #define ETH_DMASR_EBS 0x03800000U /* Error bits status */
8665  /* combination with EBS[2:0] for GetFlagStatus function */
8666  #define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */
8667  #define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
8668  #define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
8669 #define ETH_DMASR_TPS 0x00700000U /* Transmit process state */
8670  #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
8671  #define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */
8672  #define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */
8673  #define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */
8674  #define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */
8675  #define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */
8676 #define ETH_DMASR_RPS 0x000E0000U /* Receive process state */
8677  #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
8678  #define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */
8679  #define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */
8680  #define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */
8681  #define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */
8682  #define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */
8683 #define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */
8684 #define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */
8685 #define ETH_DMASR_ERS 0x00004000U /* Early receive status */
8686 #define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */
8687 #define ETH_DMASR_ETS 0x00000400U /* Early transmit status */
8688 #define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */
8689 #define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */
8690 #define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */
8691 #define ETH_DMASR_RS 0x00000040U /* Receive status */
8692 #define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */
8693 #define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */
8694 #define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */
8695 #define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */
8696 #define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */
8697 #define ETH_DMASR_TS 0x00000001U /* Transmit status */
8698 
8699 /* Bit definition for Ethernet DMA Operation Mode Register */
8700 #define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
8701 #define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */
8702 #define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */
8703 #define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */
8704 #define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */
8705 #define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */
8706  #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
8707  #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
8708  #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
8709  #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
8710  #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
8711  #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
8712  #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
8713  #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
8714 #define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */
8715 #define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */
8716 #define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */
8717 #define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */
8718  #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
8719  #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
8720  #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
8721  #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
8722 #define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */
8723 #define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */
8724 
8725 /* Bit definition for Ethernet DMA Interrupt Enable Register */
8726 #define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */
8727 #define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */
8728 #define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */
8729 #define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */
8730 #define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */
8731 #define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */
8732 #define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */
8733 #define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */
8734 #define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */
8735 #define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */
8736 #define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */
8737 #define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */
8738 #define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */
8739 #define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */
8740 #define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */
8741 
8742 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
8743 #define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */
8744 #define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */
8745 #define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */
8746 #define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */
8747 
8748 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
8749 #define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */
8750 
8751 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
8752 #define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */
8753 
8754 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
8755 #define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */
8756 
8757 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
8758 #define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */
8759 
8760 /******************************************************************************/
8761 /* */
8762 /* USB_OTG */
8763 /* */
8764 /******************************************************************************/
8765 /******************** Bit definition for USB_OTG_GOTGCTL register ********************/
8766 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U
8767 #define USB_OTG_GOTGCTL_SRQ 0x00000002U
8768 #define USB_OTG_GOTGCTL_VBVALOEN 0x00000004U
8769 #define USB_OTG_GOTGCTL_VBVALOVAL 0x00000008U
8770 #define USB_OTG_GOTGCTL_AVALOEN 0x00000010U
8771 #define USB_OTG_GOTGCTL_AVALOVAL 0x00000020U
8772 #define USB_OTG_GOTGCTL_BVALOEN 0x00000040U
8773 #define USB_OTG_GOTGCTL_BVALOVAL 0x00000080U
8774 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U
8775 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U
8776 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U
8777 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U
8778 #define USB_OTG_GOTGCTL_EHEN 0x00001000U
8779 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U
8780 #define USB_OTG_GOTGCTL_DBCT 0x00020000U
8781 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U
8782 #define USB_OTG_GOTGCTL_BSESVLD 0x00080000U
8783 #define USB_OTG_GOTGCTL_OTGVER 0x00100000U
8785 /******************** Bit definition for USB_OTG_HCFG register ********************/
8786 #define USB_OTG_HCFG_FSLSPCS 0x00000003U
8787 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U
8788 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U
8789 #define USB_OTG_HCFG_FSLSS 0x00000004U
8791 /******************** Bit definition for USB_OTG_DCFG register ********************/
8792 #define USB_OTG_DCFG_DSPD 0x00000003U
8793 #define USB_OTG_DCFG_DSPD_0 0x00000001U
8794 #define USB_OTG_DCFG_DSPD_1 0x00000002U
8795 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U
8797 #define USB_OTG_DCFG_DAD 0x000007F0U
8798 #define USB_OTG_DCFG_DAD_0 0x00000010U
8799 #define USB_OTG_DCFG_DAD_1 0x00000020U
8800 #define USB_OTG_DCFG_DAD_2 0x00000040U
8801 #define USB_OTG_DCFG_DAD_3 0x00000080U
8802 #define USB_OTG_DCFG_DAD_4 0x00000100U
8803 #define USB_OTG_DCFG_DAD_5 0x00000200U
8804 #define USB_OTG_DCFG_DAD_6 0x00000400U
8806 #define USB_OTG_DCFG_PFIVL 0x00001800U
8807 #define USB_OTG_DCFG_PFIVL_0 0x00000800U
8808 #define USB_OTG_DCFG_PFIVL_1 0x00001000U
8810 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U
8811 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U
8812 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U
8814 /******************** Bit definition for USB_OTG_PCGCR register ********************/
8815 #define USB_OTG_PCGCR_STPPCLK 0x00000001U
8816 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U
8817 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U
8819 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
8820 #define USB_OTG_GOTGINT_SEDET 0x00000004U
8821 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U
8822 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U
8823 #define USB_OTG_GOTGINT_HNGDET 0x00020000U
8824 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U
8825 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U
8826 #define USB_OTG_GOTGINT_IDCHNG 0x00100000U
8828 /******************** Bit definition for USB_OTG_DCTL register ********************/
8829 #define USB_OTG_DCTL_RWUSIG 0x00000001U
8830 #define USB_OTG_DCTL_SDIS 0x00000002U
8831 #define USB_OTG_DCTL_GINSTS 0x00000004U
8832 #define USB_OTG_DCTL_GONSTS 0x00000008U
8834 #define USB_OTG_DCTL_TCTL 0x00000070U
8835 #define USB_OTG_DCTL_TCTL_0 0x00000010U
8836 #define USB_OTG_DCTL_TCTL_1 0x00000020U
8837 #define USB_OTG_DCTL_TCTL_2 0x00000040U
8838 #define USB_OTG_DCTL_SGINAK 0x00000080U
8839 #define USB_OTG_DCTL_CGINAK 0x00000100U
8840 #define USB_OTG_DCTL_SGONAK 0x00000200U
8841 #define USB_OTG_DCTL_CGONAK 0x00000400U
8842 #define USB_OTG_DCTL_POPRGDNE 0x00000800U
8844 /******************** Bit definition for USB_OTG_HFIR register ********************/
8845 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU
8847 /******************** Bit definition for USB_OTG_HFNUM register ********************/
8848 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU
8849 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U
8851 /******************** Bit definition for USB_OTG_DSTS register ********************/
8852 #define USB_OTG_DSTS_SUSPSTS 0x00000001U
8854 #define USB_OTG_DSTS_ENUMSPD 0x00000006U
8855 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U
8856 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U
8857 #define USB_OTG_DSTS_EERR 0x00000008U
8858 #define USB_OTG_DSTS_FNSOF 0x003FFF00U
8860 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
8861 #define USB_OTG_GAHBCFG_GINT 0x00000001U
8862 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU
8863 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U
8864 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U
8865 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U
8866 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U
8867 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U
8868 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U
8869 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U
8871 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
8872 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U
8873 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U
8874 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U
8875 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U
8876 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U
8877 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U
8878 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U
8879 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U
8880 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U
8881 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U
8882 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U
8883 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U
8884 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U
8885 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U
8886 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U
8887 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U
8888 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U
8889 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U
8890 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U
8891 #define USB_OTG_GUSBCFG_PCCI 0x00800000U
8892 #define USB_OTG_GUSBCFG_PTCI 0x01000000U
8893 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U
8894 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U
8895 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U
8896 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U
8898 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
8899 #define USB_OTG_GRSTCTL_CSRST 0x00000001U
8900 #define USB_OTG_GRSTCTL_HSRST 0x00000002U
8901 #define USB_OTG_GRSTCTL_FCRST 0x00000004U
8902 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U
8903 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U
8904 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U
8905 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U
8906 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U
8907 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U
8908 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U
8909 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U
8910 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U
8911 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U
8913 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
8914 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U
8915 #define USB_OTG_DIEPMSK_EPDM 0x00000002U
8916 #define USB_OTG_DIEPMSK_TOM 0x00000008U
8917 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U
8918 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U
8919 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U
8920 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U
8921 #define USB_OTG_DIEPMSK_BIM 0x00000200U
8923 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
8924 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU
8925 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U
8926 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U
8927 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U
8928 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U
8929 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U
8930 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U
8931 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U
8932 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U
8933 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U
8935 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U
8936 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U
8937 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U
8938 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U
8939 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U
8940 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U
8941 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U
8942 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U
8943 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U
8945 /******************** Bit definition for USB_OTG_HAINT register ********************/
8946 #define USB_OTG_HAINT_HAINT 0x0000FFFFU
8948 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
8949 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U
8950 #define USB_OTG_DOEPMSK_EPDM 0x00000002U
8951 #define USB_OTG_DOEPMSK_STUPM 0x00000008U
8952 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U
8953 #define USB_OTG_DOEPMSK_OTEPSPRM 0x00000020U
8954 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U
8955 #define USB_OTG_DOEPMSK_OPEM 0x00000100U
8956 #define USB_OTG_DOEPMSK_BOIM 0x00000200U
8958 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
8959 #define USB_OTG_GINTSTS_CMOD 0x00000001U
8960 #define USB_OTG_GINTSTS_MMIS 0x00000002U
8961 #define USB_OTG_GINTSTS_OTGINT 0x00000004U
8962 #define USB_OTG_GINTSTS_SOF 0x00000008U
8963 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U
8964 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U
8965 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U
8966 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U
8967 #define USB_OTG_GINTSTS_ESUSP 0x00000400U
8968 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U
8969 #define USB_OTG_GINTSTS_USBRST 0x00001000U
8970 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U
8971 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U
8972 #define USB_OTG_GINTSTS_EOPF 0x00008000U
8973 #define USB_OTG_GINTSTS_IEPINT 0x00040000U
8974 #define USB_OTG_GINTSTS_OEPINT 0x00080000U
8975 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U
8976 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U
8977 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U
8978 #define USB_OTG_GINTSTS_RSTDET 0x00800000U
8979 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U
8980 #define USB_OTG_GINTSTS_HCINT 0x02000000U
8981 #define USB_OTG_GINTSTS_PTXFE 0x04000000U
8982 #define USB_OTG_GINTSTS_LPMINT 0x08000000U
8983 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U
8984 #define USB_OTG_GINTSTS_DISCINT 0x20000000U
8985 #define USB_OTG_GINTSTS_SRQINT 0x40000000U
8986 #define USB_OTG_GINTSTS_WKUINT 0x80000000U
8988 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
8989 #define USB_OTG_GINTMSK_MMISM 0x00000002U
8990 #define USB_OTG_GINTMSK_OTGINT 0x00000004U
8991 #define USB_OTG_GINTMSK_SOFM 0x00000008U
8992 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U
8993 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U
8994 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U
8995 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U
8996 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U
8997 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U
8998 #define USB_OTG_GINTMSK_USBRST 0x00001000U
8999 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U
9000 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U
9001 #define USB_OTG_GINTMSK_EOPFM 0x00008000U
9002 #define USB_OTG_GINTMSK_EPMISM 0x00020000U
9003 #define USB_OTG_GINTMSK_IEPINT 0x00040000U
9004 #define USB_OTG_GINTMSK_OEPINT 0x00080000U
9005 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U
9006 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U
9007 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U
9008 #define USB_OTG_GINTMSK_RSTDEM 0x00800000U
9009 #define USB_OTG_GINTMSK_PRTIM 0x01000000U
9010 #define USB_OTG_GINTMSK_HCIM 0x02000000U
9011 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U
9012 #define USB_OTG_GINTMSK_LPMINTM 0x08000000U
9013 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U
9014 #define USB_OTG_GINTMSK_DISCINT 0x20000000U
9015 #define USB_OTG_GINTMSK_SRQIM 0x40000000U
9016 #define USB_OTG_GINTMSK_WUIM 0x80000000U
9018 /******************** Bit definition for USB_OTG_DAINT register ********************/
9019 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU
9020 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U
9022 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
9023 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU
9025 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
9026 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU
9027 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U
9028 #define USB_OTG_GRXSTSP_DPID 0x00018000U
9029 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U
9031 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
9032 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU
9033 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U
9035 /******************** Bit definition for OTG register ********************/
9036 
9037 #define USB_OTG_CHNUM 0x0000000FU
9038 #define USB_OTG_CHNUM_0 0x00000001U
9039 #define USB_OTG_CHNUM_1 0x00000002U
9040 #define USB_OTG_CHNUM_2 0x00000004U
9041 #define USB_OTG_CHNUM_3 0x00000008U
9042 #define USB_OTG_BCNT 0x00007FF0U
9044 #define USB_OTG_DPID 0x00018000U
9045 #define USB_OTG_DPID_0 0x00008000U
9046 #define USB_OTG_DPID_1 0x00010000U
9048 #define USB_OTG_PKTSTS 0x001E0000U
9049 #define USB_OTG_PKTSTS_0 0x00020000U
9050 #define USB_OTG_PKTSTS_1 0x00040000U
9051 #define USB_OTG_PKTSTS_2 0x00080000U
9052 #define USB_OTG_PKTSTS_3 0x00100000U
9054 #define USB_OTG_EPNUM 0x0000000FU
9055 #define USB_OTG_EPNUM_0 0x00000001U
9056 #define USB_OTG_EPNUM_1 0x00000002U
9057 #define USB_OTG_EPNUM_2 0x00000004U
9058 #define USB_OTG_EPNUM_3 0x00000008U
9060 #define USB_OTG_FRMNUM 0x01E00000U
9061 #define USB_OTG_FRMNUM_0 0x00200000U
9062 #define USB_OTG_FRMNUM_1 0x00400000U
9063 #define USB_OTG_FRMNUM_2 0x00800000U
9064 #define USB_OTG_FRMNUM_3 0x01000000U
9066 /******************** Bit definition for OTG register ********************/
9067 
9068 #define USB_OTG_CHNUM 0x0000000FU
9069 #define USB_OTG_CHNUM_0 0x00000001U
9070 #define USB_OTG_CHNUM_1 0x00000002U
9071 #define USB_OTG_CHNUM_2 0x00000004U
9072 #define USB_OTG_CHNUM_3 0x00000008U
9073 #define USB_OTG_BCNT 0x00007FF0U
9075 #define USB_OTG_DPID 0x00018000U
9076 #define USB_OTG_DPID_0 0x00008000U
9077 #define USB_OTG_DPID_1 0x00010000U
9079 #define USB_OTG_PKTSTS 0x001E0000U
9080 #define USB_OTG_PKTSTS_0 0x00020000U
9081 #define USB_OTG_PKTSTS_1 0x00040000U
9082 #define USB_OTG_PKTSTS_2 0x00080000U
9083 #define USB_OTG_PKTSTS_3 0x00100000U
9085 #define USB_OTG_EPNUM 0x0000000FU
9086 #define USB_OTG_EPNUM_0 0x00000001U
9087 #define USB_OTG_EPNUM_1 0x00000002U
9088 #define USB_OTG_EPNUM_2 0x00000004U
9089 #define USB_OTG_EPNUM_3 0x00000008U
9091 #define USB_OTG_FRMNUM 0x01E00000U
9092 #define USB_OTG_FRMNUM_0 0x00200000U
9093 #define USB_OTG_FRMNUM_1 0x00400000U
9094 #define USB_OTG_FRMNUM_2 0x00800000U
9095 #define USB_OTG_FRMNUM_3 0x01000000U
9097 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
9098 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU
9100 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
9101 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU
9103 /******************** Bit definition for OTG register ********************/
9104 #define USB_OTG_NPTXFSA 0x0000FFFFU
9105 #define USB_OTG_NPTXFD 0xFFFF0000U
9106 #define USB_OTG_TX0FSA 0x0000FFFFU
9107 #define USB_OTG_TX0FD 0xFFFF0000U
9109 /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
9110 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU
9112 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
9113 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU
9115 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U
9116 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U
9117 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U
9118 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U
9119 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U
9120 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U
9121 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U
9122 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U
9123 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U
9125 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U
9126 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U
9127 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U
9128 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U
9129 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U
9130 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U
9131 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U
9132 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U
9134 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
9135 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U
9136 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U
9138 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU
9139 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U
9140 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U
9141 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U
9142 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U
9143 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U
9144 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U
9145 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U
9146 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U
9147 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U
9148 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U
9150 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U
9151 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U
9152 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U
9153 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U
9154 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U
9155 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U
9156 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U
9157 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U
9158 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U
9159 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U
9160 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U
9162 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
9163 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU
9165 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
9166 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U
9167 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U
9169 /******************** Bit definition for USB_OTG_GCCFG register ********************/
9170 #define USB_OTG_GCCFG_PWRDWN 0x00010000U
9171 #define USB_OTG_GCCFG_VBDEN 0x00200000U
9173 /******************** Bit definition for USB_OTG_GPWRDN) register ********************/
9174 #define USB_OTG_GPWRDN_ADPMEN 0x00000001U
9175 #define USB_OTG_GPWRDN_ADPIF 0x00800000U
9177 /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
9178 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U
9179 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U
9181 /******************** Bit definition for USB_OTG_CID register ********************/
9182 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU
9184 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
9185 #define USB_OTG_GLPMCFG_LPMEN 0x00000001U
9186 #define USB_OTG_GLPMCFG_LPMACK 0x00000002U
9187 #define USB_OTG_GLPMCFG_BESL 0x0000003CU
9188 #define USB_OTG_GLPMCFG_REMWAKE 0x00000040U
9189 #define USB_OTG_GLPMCFG_L1SSEN 0x00000080U
9190 #define USB_OTG_GLPMCFG_BESLTHRS 0x00000F00U
9191 #define USB_OTG_GLPMCFG_L1DSEN 0x00001000U
9192 #define USB_OTG_GLPMCFG_LPMRSP 0x00006000U
9193 #define USB_OTG_GLPMCFG_SLPSTS 0x00008000U
9194 #define USB_OTG_GLPMCFG_L1RSMOK 0x00010000U
9195 #define USB_OTG_GLPMCFG_LPMCHIDX 0x001E0000U
9196 #define USB_OTG_GLPMCFG_LPMRCNT 0x00E00000U
9197 #define USB_OTG_GLPMCFG_SNDLPM 0x01000000U
9198 #define USB_OTG_GLPMCFG_LPMRCNTSTS 0x0E000000U
9199 #define USB_OTG_GLPMCFG_ENBESL 0x10000000U
9201 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
9202 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U
9203 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U
9204 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U
9205 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U
9206 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U
9207 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U
9208 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U
9209 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U
9210 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U
9212 /******************** Bit definition for USB_OTG_HPRT register ********************/
9213 #define USB_OTG_HPRT_PCSTS 0x00000001U
9214 #define USB_OTG_HPRT_PCDET 0x00000002U
9215 #define USB_OTG_HPRT_PENA 0x00000004U
9216 #define USB_OTG_HPRT_PENCHNG 0x00000008U
9217 #define USB_OTG_HPRT_POCA 0x00000010U
9218 #define USB_OTG_HPRT_POCCHNG 0x00000020U
9219 #define USB_OTG_HPRT_PRES 0x00000040U
9220 #define USB_OTG_HPRT_PSUSP 0x00000080U
9221 #define USB_OTG_HPRT_PRST 0x00000100U
9223 #define USB_OTG_HPRT_PLSTS 0x00000C00U
9224 #define USB_OTG_HPRT_PLSTS_0 0x00000400U
9225 #define USB_OTG_HPRT_PLSTS_1 0x00000800U
9226 #define USB_OTG_HPRT_PPWR 0x00001000U
9228 #define USB_OTG_HPRT_PTCTL 0x0001E000U
9229 #define USB_OTG_HPRT_PTCTL_0 0x00002000U
9230 #define USB_OTG_HPRT_PTCTL_1 0x00004000U
9231 #define USB_OTG_HPRT_PTCTL_2 0x00008000U
9232 #define USB_OTG_HPRT_PTCTL_3 0x00010000U
9234 #define USB_OTG_HPRT_PSPD 0x00060000U
9235 #define USB_OTG_HPRT_PSPD_0 0x00020000U
9236 #define USB_OTG_HPRT_PSPD_1 0x00040000U
9238 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
9239 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U
9240 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U
9241 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U
9242 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U
9243 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U
9244 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U
9245 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U
9246 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U
9247 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U
9248 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U
9249 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U
9251 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
9252 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU
9253 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U
9255 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
9256 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU
9257 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U
9258 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U
9259 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U
9261 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U
9262 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U
9263 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U
9264 #define USB_OTG_DIEPCTL_STALL 0x00200000U
9266 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U
9267 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U
9268 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U
9269 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U
9270 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U
9271 #define USB_OTG_DIEPCTL_CNAK 0x04000000U
9272 #define USB_OTG_DIEPCTL_SNAK 0x08000000U
9273 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U
9274 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U
9275 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U
9276 #define USB_OTG_DIEPCTL_EPENA 0x80000000U
9278 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
9279 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU
9281 #define USB_OTG_HCCHAR_EPNUM 0x00007800U
9282 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U
9283 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U
9284 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U
9285 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U
9286 #define USB_OTG_HCCHAR_EPDIR 0x00008000U
9287 #define USB_OTG_HCCHAR_LSDEV 0x00020000U
9289 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U
9290 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U
9291 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U
9293 #define USB_OTG_HCCHAR_MC 0x00300000U
9294 #define USB_OTG_HCCHAR_MC_0 0x00100000U
9295 #define USB_OTG_HCCHAR_MC_1 0x00200000U
9297 #define USB_OTG_HCCHAR_DAD 0x1FC00000U
9298 #define USB_OTG_HCCHAR_DAD_0 0x00400000U
9299 #define USB_OTG_HCCHAR_DAD_1 0x00800000U
9300 #define USB_OTG_HCCHAR_DAD_2 0x01000000U
9301 #define USB_OTG_HCCHAR_DAD_3 0x02000000U
9302 #define USB_OTG_HCCHAR_DAD_4 0x04000000U
9303 #define USB_OTG_HCCHAR_DAD_5 0x08000000U
9304 #define USB_OTG_HCCHAR_DAD_6 0x10000000U
9305 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U
9306 #define USB_OTG_HCCHAR_CHDIS 0x40000000U
9307 #define USB_OTG_HCCHAR_CHENA 0x80000000U
9309 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
9310 
9311 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU
9312 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U
9313 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U
9314 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U
9315 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U
9316 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U
9317 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U
9318 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U
9320 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U
9321 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U
9322 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U
9323 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U
9324 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U
9325 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U
9326 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U
9327 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U
9329 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U
9330 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U
9331 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U
9332 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U
9333 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U
9335 /******************** Bit definition for USB_OTG_HCINT register ********************/
9336 #define USB_OTG_HCINT_XFRC 0x00000001U
9337 #define USB_OTG_HCINT_CHH 0x00000002U
9338 #define USB_OTG_HCINT_AHBERR 0x00000004U
9339 #define USB_OTG_HCINT_STALL 0x00000008U
9340 #define USB_OTG_HCINT_NAK 0x00000010U
9341 #define USB_OTG_HCINT_ACK 0x00000020U
9342 #define USB_OTG_HCINT_NYET 0x00000040U
9343 #define USB_OTG_HCINT_TXERR 0x00000080U
9344 #define USB_OTG_HCINT_BBERR 0x00000100U
9345 #define USB_OTG_HCINT_FRMOR 0x00000200U
9346 #define USB_OTG_HCINT_DTERR 0x00000400U
9348 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
9349 #define USB_OTG_DIEPINT_XFRC 0x00000001U
9350 #define USB_OTG_DIEPINT_EPDISD 0x00000002U
9351 #define USB_OTG_DIEPINT_TOC 0x00000008U
9352 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U
9353 #define USB_OTG_DIEPINT_INEPNE 0x00000040U
9354 #define USB_OTG_DIEPINT_TXFE 0x00000080U
9355 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U
9356 #define USB_OTG_DIEPINT_BNA 0x00000200U
9357 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U
9358 #define USB_OTG_DIEPINT_BERR 0x00001000U
9359 #define USB_OTG_DIEPINT_NAK 0x00002000U
9361 /******************** Bit definition for USB_OTG_HCINTMSK register ********************/
9362 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U
9363 #define USB_OTG_HCINTMSK_CHHM 0x00000002U
9364 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U
9365 #define USB_OTG_HCINTMSK_STALLM 0x00000008U
9366 #define USB_OTG_HCINTMSK_NAKM 0x00000010U
9367 #define USB_OTG_HCINTMSK_ACKM 0x00000020U
9368 #define USB_OTG_HCINTMSK_NYET 0x00000040U
9369 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U
9370 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U
9371 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U
9372 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U
9374 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
9375 
9376 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU
9377 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U
9378 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U
9379 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
9380 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU
9381 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U
9382 #define USB_OTG_HCTSIZ_DOPING 0x80000000U
9383 #define USB_OTG_HCTSIZ_DPID 0x60000000U
9384 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U
9385 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U
9387 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
9388 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU
9390 /******************** Bit definition for USB_OTG_HCDMA register ********************/
9391 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU
9393 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
9394 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU
9396 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
9397 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU
9398 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U
9400 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
9401 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU
9402 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U
9403 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U
9404 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U
9405 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U
9406 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U
9407 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U
9408 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U
9409 #define USB_OTG_DOEPCTL_SNPM 0x00100000U
9410 #define USB_OTG_DOEPCTL_STALL 0x00200000U
9411 #define USB_OTG_DOEPCTL_CNAK 0x04000000U
9412 #define USB_OTG_DOEPCTL_SNAK 0x08000000U
9413 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U
9414 #define USB_OTG_DOEPCTL_EPENA 0x80000000U
9416 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
9417 #define USB_OTG_DOEPINT_XFRC 0x00000001U
9418 #define USB_OTG_DOEPINT_EPDISD 0x00000002U
9419 #define USB_OTG_DOEPINT_STUP 0x00000008U
9420 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U
9421 #define USB_OTG_DOEPINT_OTEPSPR 0x00000020U
9422 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U
9423 #define USB_OTG_DOEPINT_NYET 0x00004000U
9425 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
9426 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU
9427 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U
9429 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U
9430 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U
9431 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U
9433 /******************** Bit definition for PCGCCTL register ********************/
9434 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U
9435 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U
9436 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U
9438 /******************************************************************************/
9439 /* */
9440 /* JPEG Encoder/Decoder */
9441 /* */
9442 /******************************************************************************/
9443 /******************** Bit definition for CONFR0 register ********************/
9444 #define JPEG_CONFR0_START 0x00000001U
9446 /******************** Bit definition for CONFR1 register *******************/
9447 #define JPEG_CONFR1_NF 0x00000003U
9448 #define JPEG_CONFR1_NF_0 0x00000001U
9449 #define JPEG_CONFR1_NF_1 0x00000002U
9450 #define JPEG_CONFR1_RE 0x00000004U
9451 #define JPEG_CONFR1_DE 0x00000008U
9452 #define JPEG_CONFR1_COLORSPACE 0x00000030U
9453 #define JPEG_CONFR1_COLORSPACE_0 0x00000010U
9454 #define JPEG_CONFR1_COLORSPACE_1 0x00000020U
9455 #define JPEG_CONFR1_NS 0x000000C0U
9456 #define JPEG_CONFR1_NS_0 0x00000040U
9457 #define JPEG_CONFR1_NS_1 0x00000080U
9458 #define JPEG_CONFR1_HDR 0x00000100U
9459 #define JPEG_CONFR1_YSIZE 0xFFFF0000U
9461 /******************** Bit definition for CONFR2 register *******************/
9462 #define JPEG_CONFR2_NMCU 0x03FFFFFFU
9464 /******************** Bit definition for CONFR3 register *******************/
9465 #define JPEG_CONFR3_NRST 0x0000FFFFU
9466 #define JPEG_CONFR3_XSIZE 0xFFFF0000U
9468 /******************** Bit definition for CONFR4 register *******************/
9469 #define JPEG_CONFR4_HD 0x00000001U
9470 #define JPEG_CONFR4_HA 0x00000002U
9471 #define JPEG_CONFR4_QT 0x0000000CU
9472 #define JPEG_CONFR4_QT_0 0x00000004U
9473 #define JPEG_CONFR4_QT_1 0x00000008U
9474 #define JPEG_CONFR4_NB 0x000000F0U
9475 #define JPEG_CONFR4_NB_0 0x00000010U
9476 #define JPEG_CONFR4_NB_1 0x00000020U
9477 #define JPEG_CONFR4_NB_2 0x00000040U
9478 #define JPEG_CONFR4_NB_3 0x00000080U
9479 #define JPEG_CONFR4_VSF 0x00000F00U
9480 #define JPEG_CONFR4_VSF_0 0x00000100U
9481 #define JPEG_CONFR4_VSF_1 0x00000200U
9482 #define JPEG_CONFR4_VSF_2 0x00000400U
9483 #define JPEG_CONFR4_VSF_3 0x00000800U
9484 #define JPEG_CONFR4_HSF 0x0000F000U
9485 #define JPEG_CONFR4_HSF_0 0x00001000U
9486 #define JPEG_CONFR4_HSF_1 0x00002000U
9487 #define JPEG_CONFR4_HSF_2 0x00004000U
9488 #define JPEG_CONFR4_HSF_3 0x00008000U
9490 /******************** Bit definition for CONFR5 register *******************/
9491 #define JPEG_CONFR5_HD 0x00000001U
9492 #define JPEG_CONFR5_HA 0x00000002U
9493 #define JPEG_CONFR5_QT 0x0000000CU
9494 #define JPEG_CONFR5_QT_0 0x00000004U
9495 #define JPEG_CONFR5_QT_1 0x00000008U
9496 #define JPEG_CONFR5_NB 0x000000F0U
9497 #define JPEG_CONFR5_NB_0 0x00000010U
9498 #define JPEG_CONFR5_NB_1 0x00000020U
9499 #define JPEG_CONFR5_NB_2 0x00000040U
9500 #define JPEG_CONFR5_NB_3 0x00000080U
9501 #define JPEG_CONFR5_VSF 0x00000F00U
9502 #define JPEG_CONFR5_VSF_0 0x00000100U
9503 #define JPEG_CONFR5_VSF_1 0x00000200U
9504 #define JPEG_CONFR5_VSF_2 0x00000400U
9505 #define JPEG_CONFR5_VSF_3 0x00000800U
9506 #define JPEG_CONFR5_HSF 0x0000F000U
9507 #define JPEG_CONFR5_HSF_0 0x00001000U
9508 #define JPEG_CONFR5_HSF_1 0x00002000U
9509 #define JPEG_CONFR5_HSF_2 0x00004000U
9510 #define JPEG_CONFR5_HSF_3 0x00008000U
9512 /******************** Bit definition for CONFR6 register *******************/
9513 #define JPEG_CONFR6_HD 0x00000001U
9514 #define JPEG_CONFR6_HA 0x00000002U
9515 #define JPEG_CONFR6_QT 0x0000000CU
9516 #define JPEG_CONFR6_QT_0 0x00000004U
9517 #define JPEG_CONFR6_QT_1 0x00000008U
9518 #define JPEG_CONFR6_NB 0x000000F0U
9519 #define JPEG_CONFR6_NB_0 0x00000010U
9520 #define JPEG_CONFR6_NB_1 0x00000020U
9521 #define JPEG_CONFR6_NB_2 0x00000040U
9522 #define JPEG_CONFR6_NB_3 0x00000080U
9523 #define JPEG_CONFR6_VSF 0x00000F00U
9524 #define JPEG_CONFR6_VSF_0 0x00000100U
9525 #define JPEG_CONFR6_VSF_1 0x00000200U
9526 #define JPEG_CONFR6_VSF_2 0x00000400U
9527 #define JPEG_CONFR6_VSF_3 0x00000800U
9528 #define JPEG_CONFR6_HSF 0x0000F000U
9529 #define JPEG_CONFR6_HSF_0 0x00001000U
9530 #define JPEG_CONFR6_HSF_1 0x00002000U
9531 #define JPEG_CONFR6_HSF_2 0x00004000U
9532 #define JPEG_CONFR6_HSF_3 0x00008000U
9534 /******************** Bit definition for CONFR7 register *******************/
9535 #define JPEG_CONFR7_HD 0x00000001U
9536 #define JPEG_CONFR7_HA 0x00000002U
9537 #define JPEG_CONFR7_QT 0x0000000CU
9538 #define JPEG_CONFR7_QT_0 0x00000004U
9539 #define JPEG_CONFR7_QT_1 0x00000008U
9540 #define JPEG_CONFR7_NB 0x000000F0U
9541 #define JPEG_CONFR7_NB_0 0x00000010U
9542 #define JPEG_CONFR7_NB_1 0x00000020U
9543 #define JPEG_CONFR7_NB_2 0x00000040U
9544 #define JPEG_CONFR7_NB_3 0x00000080U
9545 #define JPEG_CONFR7_VSF 0x00000F00U
9546 #define JPEG_CONFR7_VSF_0 0x00000100U
9547 #define JPEG_CONFR7_VSF_1 0x00000200U
9548 #define JPEG_CONFR7_VSF_2 0x00000400U
9549 #define JPEG_CONFR7_VSF_3 0x00000800U
9550 #define JPEG_CONFR7_HSF 0x0000F000U
9551 #define JPEG_CONFR7_HSF_0 0x00001000U
9552 #define JPEG_CONFR7_HSF_1 0x00002000U
9553 #define JPEG_CONFR7_HSF_2 0x00004000U
9554 #define JPEG_CONFR7_HSF_3 0x00008000U
9556 /******************** Bit definition for CR register *******************/
9557 #define JPEG_CR_JCEN 0x00000001U
9558 #define JPEG_CR_IFTIE 0x00000002U
9559 #define JPEG_CR_IFNFIE 0x00000004U
9560 #define JPEG_CR_OFTIE 0x00000008U
9561 #define JPEG_CR_OFNEIE 0x00000010U
9562 #define JPEG_CR_EOCIE 0x00000020U
9563 #define JPEG_CR_HPDIE 0x00000040U
9564 #define JPEG_CR_IDMAEN 0x00000800U
9565 #define JPEG_CR_ODMAEN 0x00001000U
9566 #define JPEG_CR_IFF 0x00002000U
9567 #define JPEG_CR_OFF 0x00004000U
9569 /******************** Bit definition for SR register *******************/
9570 #define JPEG_SR_IFTF 0x00000002U
9571 #define JPEG_SR_IFNFF 0x00000004U
9572 #define JPEG_SR_OFTF 0x00000008U
9573 #define JPEG_SR_OFNEF 0x000000010U
9574 #define JPEG_SR_EOCF 0x000000020U
9575 #define JPEG_SR_HPDF 0x000000040U
9576 #define JPEG_SR_COF 0x000000080U
9578 /******************** Bit definition for CFR register *******************/
9579 #define JPEG_CFR_CEOCF 0x00000020U
9580 #define JPEG_CFR_CHPDF 0x00000040U
9582 /******************** Bit definition for DIR register ********************/
9583 #define JPEG_DIR_DATAIN 0xFFFFFFFFU
9585 /******************** Bit definition for DOR register ********************/
9586 #define JPEG_DOR_DATAOUT 0xFFFFFFFFU
9588 /******************************************************************************/
9589 /* */
9590 /* MDIOS */
9591 /* */
9592 /******************************************************************************/
9593 /******************** Bit definition for MDIOS_CR register *******************/
9594 #define MDIOS_CR_EN 0x00000001U
9595 #define MDIOS_CR_WRIE 0x00000002U
9596 #define MDIOS_CR_RDIE 0x00000004U
9597 #define MDIOS_CR_EIE 0x00000008U
9598 #define MDIOS_CR_DPC 0x00000080U
9599 #define MDIOS_CR_PORT_ADDRESS 0x00001F00U
9600 #define MDIOS_CR_PORT_ADDRESS_0 0x00000100U
9601 #define MDIOS_CR_PORT_ADDRESS_1 0x00000200U
9602 #define MDIOS_CR_PORT_ADDRESS_2 0x00000400U
9603 #define MDIOS_CR_PORT_ADDRESS_3 0x00000800U
9604 #define MDIOS_CR_PORT_ADDRESS_4 0x00001000U
9606 /******************** Bit definition for MDIOS_WRFR register *******************/
9607 #define MDIOS_WRFR_WRF 0xFFFFFFFFU
9609 /******************** Bit definition for MDIOS_CWRFR register *******************/
9610 #define MDIOS_CWRFR_CWRF 0xFFFFFFFFU
9612 /******************** Bit definition for MDIOS_RDFR register *******************/
9613 #define MDIOS_RDFR_RDF 0xFFFFFFFFU
9615 /******************** Bit definition for MDIOS_CRDFR register *******************/
9616 #define MDIOS_CRDFR_CRDF 0xFFFFFFFFU
9618 /******************** Bit definition for MDIOS_SR register *******************/
9619 #define MDIOS_SR_PERF 0x00000001U
9620 #define MDIOS_SR_SERF 0x00000002U
9621 #define MDIOS_SR_TERF 0x00000004U
9623 /******************** Bit definition for MDIOS_CLRFR register *******************/
9624 #define MDIOS_CLRFR_CPERF 0x00000001U
9625 #define MDIOS_CLRFR_CSERF 0x00000002U
9626 #define MDIOS_CLRFR_CTERF 0x00000004U
9628 /******************************************************************************/
9629 /* */
9630 /* Display Serial Interface (DSI) */
9631 /* */
9632 /******************************************************************************/
9633 /******************* Bit definition for DSI_VR register *****************/
9634 #define DSI_VR 0x3133302AU
9636 /******************* Bit definition for DSI_CR register *****************/
9637 #define DSI_CR_EN 0x00000001U
9639 /******************* Bit definition for DSI_CCR register ****************/
9640 #define DSI_CCR_TXECKDIV 0x000000FFU
9641 #define DSI_CCR_TXECKDIV0 0x00000001U
9642 #define DSI_CCR_TXECKDIV1 0x00000002U
9643 #define DSI_CCR_TXECKDIV2 0x00000004U
9644 #define DSI_CCR_TXECKDIV3 0x00000008U
9645 #define DSI_CCR_TXECKDIV4 0x00000010U
9646 #define DSI_CCR_TXECKDIV5 0x00000020U
9647 #define DSI_CCR_TXECKDIV6 0x00000040U
9648 #define DSI_CCR_TXECKDIV7 0x00000080U
9649 
9650 #define DSI_CCR_TOCKDIV 0x0000FF00U
9651 #define DSI_CCR_TOCKDIV0 0x00000100U
9652 #define DSI_CCR_TOCKDIV1 0x00000200U
9653 #define DSI_CCR_TOCKDIV2 0x00000400U
9654 #define DSI_CCR_TOCKDIV3 0x00000800U
9655 #define DSI_CCR_TOCKDIV4 0x00001000U
9656 #define DSI_CCR_TOCKDIV5 0x00002000U
9657 #define DSI_CCR_TOCKDIV6 0x00004000U
9658 #define DSI_CCR_TOCKDIV7 0x00008000U
9659 
9660 /******************* Bit definition for DSI_LVCIDR register *************/
9661 #define DSI_LVCIDR_VCID 0x00000003U
9662 #define DSI_LVCIDR_VCID0 0x00000001U
9663 #define DSI_LVCIDR_VCID1 0x00000002U
9664 
9665 /******************* Bit definition for DSI_LCOLCR register *************/
9666 #define DSI_LCOLCR_COLC 0x0000000FU
9667 #define DSI_LCOLCR_COLC0 0x00000001U
9668 #define DSI_LCOLCR_COLC1 0x00000020U
9669 #define DSI_LCOLCR_COLC2 0x00000040U
9670 #define DSI_LCOLCR_COLC3 0x00000080U
9671 
9672 #define DSI_LCOLCR_LPE 0x00000100U
9674 /******************* Bit definition for DSI_LPCR register ***************/
9675 #define DSI_LPCR_DEP 0x00000001U
9676 #define DSI_LPCR_VSP 0x00000002U
9677 #define DSI_LPCR_HSP 0x00000004U
9679 /******************* Bit definition for DSI_LPMCR register **************/
9680 #define DSI_LPMCR_VLPSIZE 0x000000FFU
9681 #define DSI_LPMCR_VLPSIZE0 0x00000001U
9682 #define DSI_LPMCR_VLPSIZE1 0x00000002U
9683 #define DSI_LPMCR_VLPSIZE2 0x00000004U
9684 #define DSI_LPMCR_VLPSIZE3 0x00000008U
9685 #define DSI_LPMCR_VLPSIZE4 0x00000010U
9686 #define DSI_LPMCR_VLPSIZE5 0x00000020U
9687 #define DSI_LPMCR_VLPSIZE6 0x00000040U
9688 #define DSI_LPMCR_VLPSIZE7 0x00000080U
9689 
9690 #define DSI_LPMCR_LPSIZE 0x00FF0000U
9691 #define DSI_LPMCR_LPSIZE0 0x00010000U
9692 #define DSI_LPMCR_LPSIZE1 0x00020000U
9693 #define DSI_LPMCR_LPSIZE2 0x00040000U
9694 #define DSI_LPMCR_LPSIZE3 0x00080000U
9695 #define DSI_LPMCR_LPSIZE4 0x00100000U
9696 #define DSI_LPMCR_LPSIZE5 0x00200000U
9697 #define DSI_LPMCR_LPSIZE6 0x00400000U
9698 #define DSI_LPMCR_LPSIZE7 0x00800000U
9699 
9700 /******************* Bit definition for DSI_PCR register ****************/
9701 #define DSI_PCR_ETTXE 0x00000001U
9702 #define DSI_PCR_ETRXE 0x00000002U
9703 #define DSI_PCR_BTAE 0x00000004U
9704 #define DSI_PCR_ECCRXE 0x00000008U
9705 #define DSI_PCR_CRCRXE 0x00000010U
9707 /******************* Bit definition for DSI_GVCIDR register *************/
9708 #define DSI_GVCIDR_VCID 0x00000003U
9709 #define DSI_GVCIDR_VCID0 0x00000001U
9710 #define DSI_GVCIDR_VCID1 0x00000002U
9711 
9712 /******************* Bit definition for DSI_MCR register ****************/
9713 #define DSI_MCR_CMDM 0x00000001U
9715 /******************* Bit definition for DSI_VMCR register ***************/
9716 #define DSI_VMCR_VMT 0x00000003U
9717 #define DSI_VMCR_VMT0 0x00000001U
9718 #define DSI_VMCR_VMT1 0x00000002U
9719 
9720 #define DSI_VMCR_LPVSAE 0x00000100U
9721 #define DSI_VMCR_LPVBPE 0x00000200U
9722 #define DSI_VMCR_LPVFPE 0x00000400U
9723 #define DSI_VMCR_LPVAE 0x00000800U
9724 #define DSI_VMCR_LPHBPE 0x00001000U
9725 #define DSI_VMCR_LPHFPE 0x00002000U
9726 #define DSI_VMCR_FBTAAE 0x00004000U
9727 #define DSI_VMCR_LPCE 0x00008000U
9728 #define DSI_VMCR_PGE 0x00010000U
9729 #define DSI_VMCR_PGM 0x00100000U
9730 #define DSI_VMCR_PGO 0x01000000U
9732 /******************* Bit definition for DSI_VPCR register ***************/
9733 #define DSI_VPCR_VPSIZE 0x00003FFFU
9734 #define DSI_VPCR_VPSIZE0 0x00000001U
9735 #define DSI_VPCR_VPSIZE1 0x00000002U
9736 #define DSI_VPCR_VPSIZE2 0x00000004U
9737 #define DSI_VPCR_VPSIZE3 0x00000008U
9738 #define DSI_VPCR_VPSIZE4 0x00000010U
9739 #define DSI_VPCR_VPSIZE5 0x00000020U
9740 #define DSI_VPCR_VPSIZE6 0x00000040U
9741 #define DSI_VPCR_VPSIZE7 0x00000080U
9742 #define DSI_VPCR_VPSIZE8 0x00000100U
9743 #define DSI_VPCR_VPSIZE9 0x00000200U
9744 #define DSI_VPCR_VPSIZE10 0x00000400U
9745 #define DSI_VPCR_VPSIZE11 0x00000800U
9746 #define DSI_VPCR_VPSIZE12 0x00001000U
9747 #define DSI_VPCR_VPSIZE13 0x00002000U
9748 
9749 /******************* Bit definition for DSI_VCCR register ***************/
9750 #define DSI_VCCR_NUMC 0x00001FFFU
9751 #define DSI_VCCR_NUMC0 0x00000001U
9752 #define DSI_VCCR_NUMC1 0x00000002U
9753 #define DSI_VCCR_NUMC2 0x00000004U
9754 #define DSI_VCCR_NUMC3 0x00000008U
9755 #define DSI_VCCR_NUMC4 0x00000010U
9756 #define DSI_VCCR_NUMC5 0x00000020U
9757 #define DSI_VCCR_NUMC6 0x00000040U
9758 #define DSI_VCCR_NUMC7 0x00000080U
9759 #define DSI_VCCR_NUMC8 0x00000100U
9760 #define DSI_VCCR_NUMC9 0x00000200U
9761 #define DSI_VCCR_NUMC10 0x00000400U
9762 #define DSI_VCCR_NUMC11 0x00000800U
9763 #define DSI_VCCR_NUMC12 0x00001000U
9764 
9765 /******************* Bit definition for DSI_VNPCR register **************/
9766 #define DSI_VNPCR_NPSIZE 0x00001FFFU
9767 #define DSI_VNPCR_NPSIZE0 0x00000001U
9768 #define DSI_VNPCR_NPSIZE1 0x00000002U
9769 #define DSI_VNPCR_NPSIZE2 0x00000004U
9770 #define DSI_VNPCR_NPSIZE3 0x00000008U
9771 #define DSI_VNPCR_NPSIZE4 0x00000010U
9772 #define DSI_VNPCR_NPSIZE5 0x00000020U
9773 #define DSI_VNPCR_NPSIZE6 0x00000040U
9774 #define DSI_VNPCR_NPSIZE7 0x00000080U
9775 #define DSI_VNPCR_NPSIZE8 0x00000100U
9776 #define DSI_VNPCR_NPSIZE9 0x00000200U
9777 #define DSI_VNPCR_NPSIZE10 0x00000400U
9778 #define DSI_VNPCR_NPSIZE11 0x00000800U
9779 #define DSI_VNPCR_NPSIZE12 0x00001000U
9780 
9781 /******************* Bit definition for DSI_VHSACR register *************/
9782 #define DSI_VHSACR_HSA 0x00000FFFU
9783 #define DSI_VHSACR_HSA0 0x00000001U
9784 #define DSI_VHSACR_HSA1 0x00000002U
9785 #define DSI_VHSACR_HSA2 0x00000004U
9786 #define DSI_VHSACR_HSA3 0x00000008U
9787 #define DSI_VHSACR_HSA4 0x00000010U
9788 #define DSI_VHSACR_HSA5 0x00000020U
9789 #define DSI_VHSACR_HSA6 0x00000040U
9790 #define DSI_VHSACR_HSA7 0x00000080U
9791 #define DSI_VHSACR_HSA8 0x00000100U
9792 #define DSI_VHSACR_HSA9 0x00000200U
9793 #define DSI_VHSACR_HSA10 0x00000400U
9794 #define DSI_VHSACR_HSA11 0x00000800U
9795 
9796 /******************* Bit definition for DSI_VHBPCR register *************/
9797 #define DSI_VHBPCR_HBP 0x00000FFFU
9798 #define DSI_VHBPCR_HBP0 0x00000001U
9799 #define DSI_VHBPCR_HBP1 0x00000002U
9800 #define DSI_VHBPCR_HBP2 0x00000004U
9801 #define DSI_VHBPCR_HBP3 0x00000008U
9802 #define DSI_VHBPCR_HBP4 0x00000010U
9803 #define DSI_VHBPCR_HBP5 0x00000020U
9804 #define DSI_VHBPCR_HBP6 0x00000040U
9805 #define DSI_VHBPCR_HBP7 0x00000080U
9806 #define DSI_VHBPCR_HBP8 0x00000100U
9807 #define DSI_VHBPCR_HBP9 0x00000200U
9808 #define DSI_VHBPCR_HBP10 0x00000400U
9809 #define DSI_VHBPCR_HBP11 0x00000800U
9810 
9811 /******************* Bit definition for DSI_VLCR register ***************/
9812 #define DSI_VLCR_HLINE 0x00007FFFU
9813 #define DSI_VLCR_HLINE0 0x00000001U
9814 #define DSI_VLCR_HLINE1 0x00000002U
9815 #define DSI_VLCR_HLINE2 0x00000004U
9816 #define DSI_VLCR_HLINE3 0x00000008U
9817 #define DSI_VLCR_HLINE4 0x00000010U
9818 #define DSI_VLCR_HLINE5 0x00000020U
9819 #define DSI_VLCR_HLINE6 0x00000040U
9820 #define DSI_VLCR_HLINE7 0x00000080U
9821 #define DSI_VLCR_HLINE8 0x00000100U
9822 #define DSI_VLCR_HLINE9 0x00000200U
9823 #define DSI_VLCR_HLINE10 0x00000400U
9824 #define DSI_VLCR_HLINE11 0x00000800U
9825 #define DSI_VLCR_HLINE12 0x00001000U
9826 #define DSI_VLCR_HLINE13 0x00002000U
9827 #define DSI_VLCR_HLINE14 0x00004000U
9828 
9829 /******************* Bit definition for DSI_VVSACR register *************/
9830 #define DSI_VVSACR_VSA 0x000003FFU
9831 #define DSI_VVSACR_VSA0 0x00000001U
9832 #define DSI_VVSACR_VSA1 0x00000002U
9833 #define DSI_VVSACR_VSA2 0x00000004U
9834 #define DSI_VVSACR_VSA3 0x00000008U
9835 #define DSI_VVSACR_VSA4 0x00000010U
9836 #define DSI_VVSACR_VSA5 0x00000020U
9837 #define DSI_VVSACR_VSA6 0x00000040U
9838 #define DSI_VVSACR_VSA7 0x00000080U
9839 #define DSI_VVSACR_VSA8 0x00000100U
9840 #define DSI_VVSACR_VSA9 0x00000200U
9841 
9842 /******************* Bit definition for DSI_VVBPCR register *************/
9843 #define DSI_VVBPCR_VBP 0x000003FFU
9844 #define DSI_VVBPCR_VBP0 0x00000001U
9845 #define DSI_VVBPCR_VBP1 0x00000002U
9846 #define DSI_VVBPCR_VBP2 0x00000004U
9847 #define DSI_VVBPCR_VBP3 0x00000008U
9848 #define DSI_VVBPCR_VBP4 0x00000010U
9849 #define DSI_VVBPCR_VBP5 0x00000020U
9850 #define DSI_VVBPCR_VBP6 0x00000040U
9851 #define DSI_VVBPCR_VBP7 0x00000080U
9852 #define DSI_VVBPCR_VBP8 0x00000100U
9853 #define DSI_VVBPCR_VBP9 0x00000200U
9854 
9855 /******************* Bit definition for DSI_VVFPCR register *************/
9856 #define DSI_VVFPCR_VFP 0x000003FFU
9857 #define DSI_VVFPCR_VFP0 0x00000001U
9858 #define DSI_VVFPCR_VFP1 0x00000002U
9859 #define DSI_VVFPCR_VFP2 0x00000004U
9860 #define DSI_VVFPCR_VFP3 0x00000008U
9861 #define DSI_VVFPCR_VFP4 0x00000010U
9862 #define DSI_VVFPCR_VFP5 0x00000020U
9863 #define DSI_VVFPCR_VFP6 0x00000040U
9864 #define DSI_VVFPCR_VFP7 0x00000080U
9865 #define DSI_VVFPCR_VFP8 0x00000100U
9866 #define DSI_VVFPCR_VFP9 0x00000200U
9867 
9868 /******************* Bit definition for DSI_VVACR register **************/
9869 #define DSI_VVACR_VA 0x00003FFFU
9870 #define DSI_VVACR_VA0 0x00000001U
9871 #define DSI_VVACR_VA1 0x00000002U
9872 #define DSI_VVACR_VA2 0x00000004U
9873 #define DSI_VVACR_VA3 0x00000008U
9874 #define DSI_VVACR_VA4 0x00000010U
9875 #define DSI_VVACR_VA5 0x00000020U
9876 #define DSI_VVACR_VA6 0x00000040U
9877 #define DSI_VVACR_VA7 0x00000080U
9878 #define DSI_VVACR_VA8 0x00000100U
9879 #define DSI_VVACR_VA9 0x00000200U
9880 #define DSI_VVACR_VA10 0x00000400U
9881 #define DSI_VVACR_VA11 0x00000800U
9882 #define DSI_VVACR_VA12 0x00001000U
9883 #define DSI_VVACR_VA13 0x00002000U
9884 
9885 /******************* Bit definition for DSI_LCCR register ***************/
9886 #define DSI_LCCR_CMDSIZE 0x0000FFFFU
9887 #define DSI_LCCR_CMDSIZE0 0x00000001U
9888 #define DSI_LCCR_CMDSIZE1 0x00000002U
9889 #define DSI_LCCR_CMDSIZE2 0x00000004U
9890 #define DSI_LCCR_CMDSIZE3 0x00000008U
9891 #define DSI_LCCR_CMDSIZE4 0x00000010U
9892 #define DSI_LCCR_CMDSIZE5 0x00000020U
9893 #define DSI_LCCR_CMDSIZE6 0x00000040U
9894 #define DSI_LCCR_CMDSIZE7 0x00000080U
9895 #define DSI_LCCR_CMDSIZE8 0x00000100U
9896 #define DSI_LCCR_CMDSIZE9 0x00000200U
9897 #define DSI_LCCR_CMDSIZE10 0x00000400U
9898 #define DSI_LCCR_CMDSIZE11 0x00000800U
9899 #define DSI_LCCR_CMDSIZE12 0x00001000U
9900 #define DSI_LCCR_CMDSIZE13 0x00002000U
9901 #define DSI_LCCR_CMDSIZE14 0x00004000U
9902 #define DSI_LCCR_CMDSIZE15 0x00008000U
9903 
9904 /******************* Bit definition for DSI_CMCR register ***************/
9905 #define DSI_CMCR_TEARE 0x00000001U
9906 #define DSI_CMCR_ARE 0x00000002U
9907 #define DSI_CMCR_GSW0TX 0x00000100U
9908 #define DSI_CMCR_GSW1TX 0x00000200U
9909 #define DSI_CMCR_GSW2TX 0x00000400U
9910 #define DSI_CMCR_GSR0TX 0x00000800U
9911 #define DSI_CMCR_GSR1TX 0x00001000U
9912 #define DSI_CMCR_GSR2TX 0x00002000U
9913 #define DSI_CMCR_GLWTX 0x00004000U
9914 #define DSI_CMCR_DSW0TX 0x00010000U
9915 #define DSI_CMCR_DSW1TX 0x00020000U
9916 #define DSI_CMCR_DSR0TX 0x00040000U
9917 #define DSI_CMCR_DLWTX 0x00080000U
9918 #define DSI_CMCR_MRDPS 0x01000000U
9920 /******************* Bit definition for DSI_GHCR register ***************/
9921 #define DSI_GHCR_DT 0x0000003FU
9922 #define DSI_GHCR_DT0 0x00000001U
9923 #define DSI_GHCR_DT1 0x00000002U
9924 #define DSI_GHCR_DT2 0x00000004U
9925 #define DSI_GHCR_DT3 0x00000008U
9926 #define DSI_GHCR_DT4 0x00000010U
9927 #define DSI_GHCR_DT5 0x00000020U
9928 
9929 #define DSI_GHCR_VCID 0x000000C0U
9930 #define DSI_GHCR_VCID0 0x00000040U
9931 #define DSI_GHCR_VCID1 0x00000080U
9932 
9933 #define DSI_GHCR_WCLSB 0x0000FF00U
9934 #define DSI_GHCR_WCLSB0 0x00000100U
9935 #define DSI_GHCR_WCLSB1 0x00000200U
9936 #define DSI_GHCR_WCLSB2 0x00000400U
9937 #define DSI_GHCR_WCLSB3 0x00000800U
9938 #define DSI_GHCR_WCLSB4 0x00001000U
9939 #define DSI_GHCR_WCLSB5 0x00002000U
9940 #define DSI_GHCR_WCLSB6 0x00004000U
9941 #define DSI_GHCR_WCLSB7 0x00008000U
9942 
9943 #define DSI_GHCR_WCMSB 0x00FF0000U
9944 #define DSI_GHCR_WCMSB0 0x00010000U
9945 #define DSI_GHCR_WCMSB1 0x00020000U
9946 #define DSI_GHCR_WCMSB2 0x00040000U
9947 #define DSI_GHCR_WCMSB3 0x00080000U
9948 #define DSI_GHCR_WCMSB4 0x00100000U
9949 #define DSI_GHCR_WCMSB5 0x00200000U
9950 #define DSI_GHCR_WCMSB6 0x00400000U
9951 #define DSI_GHCR_WCMSB7 0x00800000U
9952 
9953 /******************* Bit definition for DSI_GPDR register ***************/
9954 #define DSI_GPDR_DATA1 0x000000FFU
9955 #define DSI_GPDR_DATA1_0 0x00000001U
9956 #define DSI_GPDR_DATA1_1 0x00000002U
9957 #define DSI_GPDR_DATA1_2 0x00000004U
9958 #define DSI_GPDR_DATA1_3 0x00000008U
9959 #define DSI_GPDR_DATA1_4 0x00000010U
9960 #define DSI_GPDR_DATA1_5 0x00000020U
9961 #define DSI_GPDR_DATA1_6 0x00000040U
9962 #define DSI_GPDR_DATA1_7 0x00000080U
9963 
9964 #define DSI_GPDR_DATA2 0x0000FF00U
9965 #define DSI_GPDR_DATA2_0 0x00000100U
9966 #define DSI_GPDR_DATA2_1 0x00000200U
9967 #define DSI_GPDR_DATA2_2 0x00000400U
9968 #define DSI_GPDR_DATA2_3 0x00000800U
9969 #define DSI_GPDR_DATA2_4 0x00001000U
9970 #define DSI_GPDR_DATA2_5 0x00002000U
9971 #define DSI_GPDR_DATA2_6 0x00004000U
9972 #define DSI_GPDR_DATA2_7 0x00008000U
9973 
9974 #define DSI_GPDR_DATA3 0x00FF0000U
9975 #define DSI_GPDR_DATA3_0 0x00010000U
9976 #define DSI_GPDR_DATA3_1 0x00020000U
9977 #define DSI_GPDR_DATA3_2 0x00040000U
9978 #define DSI_GPDR_DATA3_3 0x00080000U
9979 #define DSI_GPDR_DATA3_4 0x00100000U
9980 #define DSI_GPDR_DATA3_5 0x00200000U
9981 #define DSI_GPDR_DATA3_6 0x00400000U
9982 #define DSI_GPDR_DATA3_7 0x00800000U
9983 
9984 #define DSI_GPDR_DATA4 0xFF000000U
9985 #define DSI_GPDR_DATA4_0 0x01000000U
9986 #define DSI_GPDR_DATA4_1 0x02000000U
9987 #define DSI_GPDR_DATA4_2 0x04000000U
9988 #define DSI_GPDR_DATA4_3 0x08000000U
9989 #define DSI_GPDR_DATA4_4 0x10000000U
9990 #define DSI_GPDR_DATA4_5 0x20000000U
9991 #define DSI_GPDR_DATA4_6 0x40000000U
9992 #define DSI_GPDR_DATA4_7 0x80000000U
9993 
9994 /******************* Bit definition for DSI_GPSR register ***************/
9995 #define DSI_GPSR_CMDFE 0x00000001U
9996 #define DSI_GPSR_CMDFF 0x00000002U
9997 #define DSI_GPSR_PWRFE 0x00000004U
9998 #define DSI_GPSR_PWRFF 0x00000008U
9999 #define DSI_GPSR_PRDFE 0x00000010U
10000 #define DSI_GPSR_PRDFF 0x00000020U
10001 #define DSI_GPSR_RCB 0x00000040U
10003 /******************* Bit definition for DSI_TCCR0register **************/
10004 #define DSI_TCCR0_LPRX_TOCNT 0x0000FFFFU
10005 #define DSI_TCCR0_LPRX_TOCNT0 0x00000001U
10006 #define DSI_TCCR0_LPRX_TOCNT1 0x00000002U
10007 #define DSI_TCCR0_LPRX_TOCNT2 0x00000004U
10008 #define DSI_TCCR0_LPRX_TOCNT3 0x00000008U
10009 #define DSI_TCCR0_LPRX_TOCNT4 0x00000010U
10010 #define DSI_TCCR0_LPRX_TOCNT5 0x00000020U
10011 #define DSI_TCCR0_LPRX_TOCNT6 0x00000040U
10012 #define DSI_TCCR0_LPRX_TOCNT7 0x00000080U
10013 #define DSI_TCCR0_LPRX_TOCNT8 0x00000100U
10014 #define DSI_TCCR0_LPRX_TOCNT9 0x00000200U
10015 #define DSI_TCCR0_LPRX_TOCNT10 0x00000400U
10016 #define DSI_TCCR0_LPRX_TOCNT11 0x00000800U
10017 #define DSI_TCCR0_LPRX_TOCNT12 0x00001000U
10018 #define DSI_TCCR0_LPRX_TOCNT13 0x00002000U
10019 #define DSI_TCCR0_LPRX_TOCNT14 0x00004000U
10020 #define DSI_TCCR0_LPRX_TOCNT15 0x00008000U
10021 
10022 #define DSI_TCCR0_HSTX_TOCNT 0xFFFF0000U
10023 #define DSI_TCCR0_HSTX_TOCNT0 0x00010000U
10024 #define DSI_TCCR0_HSTX_TOCNT1 0x00020000U
10025 #define DSI_TCCR0_HSTX_TOCNT2 0x00040000U
10026 #define DSI_TCCR0_HSTX_TOCNT3 0x00080000U
10027 #define DSI_TCCR0_HSTX_TOCNT4 0x00100000U
10028 #define DSI_TCCR0_HSTX_TOCNT5 0x00200000U
10029 #define DSI_TCCR0_HSTX_TOCNT6 0x00400000U
10030 #define DSI_TCCR0_HSTX_TOCNT7 0x00800000U
10031 #define DSI_TCCR0_HSTX_TOCNT8 0x01000000U
10032 #define DSI_TCCR0_HSTX_TOCNT9 0x02000000U
10033 #define DSI_TCCR0_HSTX_TOCNT10 0x04000000U
10034 #define DSI_TCCR0_HSTX_TOCNT11 0x08000000U
10035 #define DSI_TCCR0_HSTX_TOCNT12 0x10000000U
10036 #define DSI_TCCR0_HSTX_TOCNT13 0x20000000U
10037 #define DSI_TCCR0_HSTX_TOCNT14 0x40000000U
10038 #define DSI_TCCR0_HSTX_TOCNT15 0x80000000U
10039 
10040 /******************* Bit definition for DSI_TCCR1register **************/
10041 #define DSI_TCCR1_HSRD_TOCNT 0x0000FFFFU
10042 #define DSI_TCCR1_HSRD_TOCNT0 0x00000001U
10043 #define DSI_TCCR1_HSRD_TOCNT1 0x00000002U
10044 #define DSI_TCCR1_HSRD_TOCNT2 0x00000004U
10045 #define DSI_TCCR1_HSRD_TOCNT3 0x00000008U
10046 #define DSI_TCCR1_HSRD_TOCNT4 0x00000010U
10047 #define DSI_TCCR1_HSRD_TOCNT5 0x00000020U
10048 #define DSI_TCCR1_HSRD_TOCNT6 0x00000040U
10049 #define DSI_TCCR1_HSRD_TOCNT7 0x00000080U
10050 #define DSI_TCCR1_HSRD_TOCNT8 0x00000100U
10051 #define DSI_TCCR1_HSRD_TOCNT9 0x00000200U
10052 #define DSI_TCCR1_HSRD_TOCNT10 0x00000400U
10053 #define DSI_TCCR1_HSRD_TOCNT11 0x00000800U
10054 #define DSI_TCCR1_HSRD_TOCNT12 0x00001000U
10055 #define DSI_TCCR1_HSRD_TOCNT13 0x00002000U
10056 #define DSI_TCCR1_HSRD_TOCNT14 0x00004000U
10057 #define DSI_TCCR1_HSRD_TOCNT15 0x00008000U
10058 
10059 /******************* Bit definition for DSI_TCCR2 register **************/
10060 #define DSI_TCCR2_LPRD_TOCNT 0x0000FFFFU
10061 #define DSI_TCCR2_LPRD_TOCNT0 0x00000001U
10062 #define DSI_TCCR2_LPRD_TOCNT1 0x00000002U
10063 #define DSI_TCCR2_LPRD_TOCNT2 0x00000004U
10064 #define DSI_TCCR2_LPRD_TOCNT3 0x00000008U
10065 #define DSI_TCCR2_LPRD_TOCNT4 0x00000010U
10066 #define DSI_TCCR2_LPRD_TOCNT5 0x00000020U
10067 #define DSI_TCCR2_LPRD_TOCNT6 0x00000040U
10068 #define DSI_TCCR2_LPRD_TOCNT7 0x00000080U
10069 #define DSI_TCCR2_LPRD_TOCNT8 0x00000100U
10070 #define DSI_TCCR2_LPRD_TOCNT9 0x00000200U
10071 #define DSI_TCCR2_LPRD_TOCNT10 0x00000400U
10072 #define DSI_TCCR2_LPRD_TOCNT11 0x00000800U
10073 #define DSI_TCCR2_LPRD_TOCNT12 0x00001000U
10074 #define DSI_TCCR2_LPRD_TOCNT13 0x00002000U
10075 #define DSI_TCCR2_LPRD_TOCNT14 0x00004000U
10076 #define DSI_TCCR2_LPRD_TOCNT15 0x00008000U
10077 
10078 /******************* Bit definition for DSI_TCCR3 register **************/
10079 #define DSI_TCCR3_HSWR_TOCNT 0x0000FFFFU
10080 #define DSI_TCCR3_HSWR_TOCNT0 0x00000001U
10081 #define DSI_TCCR3_HSWR_TOCNT1 0x00000002U
10082 #define DSI_TCCR3_HSWR_TOCNT2 0x00000004U
10083 #define DSI_TCCR3_HSWR_TOCNT3 0x00000008U
10084 #define DSI_TCCR3_HSWR_TOCNT4 0x00000010U
10085 #define DSI_TCCR3_HSWR_TOCNT5 0x00000020U
10086 #define DSI_TCCR3_HSWR_TOCNT6 0x00000040U
10087 #define DSI_TCCR3_HSWR_TOCNT7 0x00000080U
10088 #define DSI_TCCR3_HSWR_TOCNT8 0x00000100U
10089 #define DSI_TCCR3_HSWR_TOCNT9 0x00000200U
10090 #define DSI_TCCR3_HSWR_TOCNT10 0x00000400U
10091 #define DSI_TCCR3_HSWR_TOCNT11 0x00000800U
10092 #define DSI_TCCR3_HSWR_TOCNT12 0x00001000U
10093 #define DSI_TCCR3_HSWR_TOCNT13 0x00002000U
10094 #define DSI_TCCR3_HSWR_TOCNT14 0x00004000U
10095 #define DSI_TCCR3_HSWR_TOCNT15 0x00008000U
10096 
10097 #define DSI_TCCR3_PM 0x01000000U
10099 /******************* Bit definition for DSI_TCCR4 register **************/
10100 #define DSI_TCCR4_LPWR_TOCNT 0x0000FFFFU
10101 #define DSI_TCCR4_LPWR_TOCNT0 0x00000001U
10102 #define DSI_TCCR4_LPWR_TOCNT1 0x00000002U
10103 #define DSI_TCCR4_LPWR_TOCNT2 0x00000004U
10104 #define DSI_TCCR4_LPWR_TOCNT3 0x00000008U
10105 #define DSI_TCCR4_LPWR_TOCNT4 0x00000010U
10106 #define DSI_TCCR4_LPWR_TOCNT5 0x00000020U
10107 #define DSI_TCCR4_LPWR_TOCNT6 0x00000040U
10108 #define DSI_TCCR4_LPWR_TOCNT7 0x00000080U
10109 #define DSI_TCCR4_LPWR_TOCNT8 0x00000100U
10110 #define DSI_TCCR4_LPWR_TOCNT9 0x00000200U
10111 #define DSI_TCCR4_LPWR_TOCNT10 0x00000400U
10112 #define DSI_TCCR4_LPWR_TOCNT11 0x00000800U
10113 #define DSI_TCCR4_LPWR_TOCNT12 0x00001000U
10114 #define DSI_TCCR4_LPWR_TOCNT13 0x00002000U
10115 #define DSI_TCCR4_LPWR_TOCNT14 0x00004000U
10116 #define DSI_TCCR4_LPWR_TOCNT15 0x00008000U
10117 
10118 /******************* Bit definition for DSI_TCCR5register **************/
10119 #define DSI_TCCR5_BTA_TOCNT 0x0000FFFFU
10120 #define DSI_TCCR5_BTA_TOCNT0 0x00000001U
10121 #define DSI_TCCR5_BTA_TOCNT1 0x00000002U
10122 #define DSI_TCCR5_BTA_TOCNT2 0x00000004U
10123 #define DSI_TCCR5_BTA_TOCNT3 0x00000008U
10124 #define DSI_TCCR5_BTA_TOCNT4 0x00000010U
10125 #define DSI_TCCR5_BTA_TOCNT5 0x00000020U
10126 #define DSI_TCCR5_BTA_TOCNT6 0x00000040U
10127 #define DSI_TCCR5_BTA_TOCNT7 0x00000080U
10128 #define DSI_TCCR5_BTA_TOCNT8 0x00000100U
10129 #define DSI_TCCR5_BTA_TOCNT9 0x00000200U
10130 #define DSI_TCCR5_BTA_TOCNT10 0x00000400U
10131 #define DSI_TCCR5_BTA_TOCNT11 0x00000800U
10132 #define DSI_TCCR5_BTA_TOCNT12 0x00001000U
10133 #define DSI_TCCR5_BTA_TOCNT13 0x00002000U
10134 #define DSI_TCCR5_BTA_TOCNT14 0x00004000U
10135 #define DSI_TCCR5_BTA_TOCNT15 0x00008000U
10136 
10137 /******************* Bit definition for DSI_TDCR register ***************/
10138 #define DSI_TDCR_3DM 0x00000003U
10139 #define DSI_TDCR_3DM0 0x00000001U
10140 #define DSI_TDCR_3DM1 0x00000002U
10141 
10142 #define DSI_TDCR_3DF 0x0000000CU
10143 #define DSI_TDCR_3DF0 0x00000004U
10144 #define DSI_TDCR_3DF1 0x00000008U
10145 
10146 #define DSI_TDCR_SVS 0x00000010U
10147 #define DSI_TDCR_RF 0x00000020U
10148 #define DSI_TDCR_S3DC 0x00010000U
10150 /******************* Bit definition for DSI_CLCR register ***************/
10151 #define DSI_CLCR_DPCC 0x00000001U
10152 #define DSI_CLCR_ACR 0x00000002U
10154 /******************* Bit definition for DSI_CLTCR register **************/
10155 #define DSI_CLTCR_LP2HS_TIME 0x000003FFU
10156 #define DSI_CLTCR_LP2HS_TIME0 0x00000001U
10157 #define DSI_CLTCR_LP2HS_TIME1 0x00000002U
10158 #define DSI_CLTCR_LP2HS_TIME2 0x00000004U
10159 #define DSI_CLTCR_LP2HS_TIME3 0x00000008U
10160 #define DSI_CLTCR_LP2HS_TIME4 0x00000010U
10161 #define DSI_CLTCR_LP2HS_TIME5 0x00000020U
10162 #define DSI_CLTCR_LP2HS_TIME6 0x00000040U
10163 #define DSI_CLTCR_LP2HS_TIME7 0x00000080U
10164 #define DSI_CLTCR_LP2HS_TIME8 0x00000100U
10165 #define DSI_CLTCR_LP2HS_TIME9 0x00000200U
10166 
10167 #define DSI_CLTCR_HS2LP_TIME 0x03FF0000U
10168 #define DSI_CLTCR_HS2LP_TIME0 0x00010000U
10169 #define DSI_CLTCR_HS2LP_TIME1 0x00020000U
10170 #define DSI_CLTCR_HS2LP_TIME2 0x00040000U
10171 #define DSI_CLTCR_HS2LP_TIME3 0x00080000U
10172 #define DSI_CLTCR_HS2LP_TIME4 0x00100000U
10173 #define DSI_CLTCR_HS2LP_TIME5 0x00200000U
10174 #define DSI_CLTCR_HS2LP_TIME6 0x00400000U
10175 #define DSI_CLTCR_HS2LP_TIME7 0x00800000U
10176 #define DSI_CLTCR_HS2LP_TIME8 0x01000000U
10177 #define DSI_CLTCR_HS2LP_TIME9 0x02000000U
10178 
10179 /******************* Bit definition for DSI_DLTCR register **************/
10180 #define DSI_DLTCR_MRD_TIME 0x00007FFFU
10181 #define DSI_DLTCR_MRD_TIME0 0x00000001U
10182 #define DSI_DLTCR_MRD_TIME1 0x00000002U
10183 #define DSI_DLTCR_MRD_TIME2 0x00000004U
10184 #define DSI_DLTCR_MRD_TIME3 0x00000008U
10185 #define DSI_DLTCR_MRD_TIME4 0x00000010U
10186 #define DSI_DLTCR_MRD_TIME5 0x00000020U
10187 #define DSI_DLTCR_MRD_TIME6 0x00000040U
10188 #define DSI_DLTCR_MRD_TIME7 0x00000080U
10189 #define DSI_DLTCR_MRD_TIME8 0x00000100U
10190 #define DSI_DLTCR_MRD_TIME9 0x00000200U
10191 #define DSI_DLTCR_MRD_TIME10 0x00000400U
10192 #define DSI_DLTCR_MRD_TIME11 0x00000800U
10193 #define DSI_DLTCR_MRD_TIME12 0x00001000U
10194 #define DSI_DLTCR_MRD_TIME13 0x00002000U
10195 #define DSI_DLTCR_MRD_TIME14 0x00004000U
10196 
10197 #define DSI_DLTCR_LP2HS_TIME 0x00FF0000U
10198 #define DSI_DLTCR_LP2HS_TIME0 0x00010000U
10199 #define DSI_DLTCR_LP2HS_TIME1 0x00020000U
10200 #define DSI_DLTCR_LP2HS_TIME2 0x00040000U
10201 #define DSI_DLTCR_LP2HS_TIME3 0x00080000U
10202 #define DSI_DLTCR_LP2HS_TIME4 0x00100000U
10203 #define DSI_DLTCR_LP2HS_TIME5 0x00200000U
10204 #define DSI_DLTCR_LP2HS_TIME6 0x00400000U
10205 #define DSI_DLTCR_LP2HS_TIME7 0x00800000U
10206 
10207 #define DSI_DLTCR_HS2LP_TIME 0xFF000000U
10208 #define DSI_DLTCR_HS2LP_TIME0 0x01000000U
10209 #define DSI_DLTCR_HS2LP_TIME1 0x02000000U
10210 #define DSI_DLTCR_HS2LP_TIME2 0x04000000U
10211 #define DSI_DLTCR_HS2LP_TIME3 0x08000000U
10212 #define DSI_DLTCR_HS2LP_TIME4 0x10000000U
10213 #define DSI_DLTCR_HS2LP_TIME5 0x20000000U
10214 #define DSI_DLTCR_HS2LP_TIME6 0x40000000U
10215 #define DSI_DLTCR_HS2LP_TIME7 0x80000000U
10216 
10217 /******************* Bit definition for DSI_PCTLRregister **************/
10218 #define DSI_PCTLR_DEN 0x00000002U
10219 #define DSI_PCTLR_CKE 0x00000004U
10221 /******************* Bit definition for DSI_PCONFR register *************/
10222 #define DSI_PCONFR_NL 0x00000003U
10223 #define DSI_PCONFR_NL0 0x00000001U
10224 #define DSI_PCONFR_NL1 0x00000002U
10225 
10226 #define DSI_PCONFR_SW_TIME 0x0000FF00U
10227 #define DSI_PCONFR_SW_TIME0 0x00000100U
10228 #define DSI_PCONFR_SW_TIME1 0x00000200U
10229 #define DSI_PCONFR_SW_TIME2 0x00000400U
10230 #define DSI_PCONFR_SW_TIME3 0x00000800U
10231 #define DSI_PCONFR_SW_TIME4 0x00001000U
10232 #define DSI_PCONFR_SW_TIME5 0x00002000U
10233 #define DSI_PCONFR_SW_TIME6 0x00004000U
10234 #define DSI_PCONFR_SW_TIME7 0x00008000U
10235 
10236 /******************* Bit definition for DSI_PUCR register ***************/
10237 #define DSI_PUCR_URCL 0x00000001U
10238 #define DSI_PUCR_UECL 0x00000002U
10239 #define DSI_PUCR_URDL 0x00000004U
10240 #define DSI_PUCR_UEDL 0x00000008U
10242 /******************* Bit definition for DSI_PTTCRregister **************/
10243 #define DSI_PTTCR_TX_TRIG 0x0000000FU
10244 #define DSI_PTTCR_TX_TRIG0 0x00000001U
10245 #define DSI_PTTCR_TX_TRIG1 0x00000002U
10246 #define DSI_PTTCR_TX_TRIG2 0x00000004U
10247 #define DSI_PTTCR_TX_TRIG3 0x00000008U
10248 
10249 /******************* Bit definition for DSI_PSR register ****************/
10250 #define DSI_PSR_PD 0x00000002U
10251 #define DSI_PSR_PSSC 0x00000004U
10252 #define DSI_PSR_UANC 0x00000008U
10253 #define DSI_PSR_PSS0 0x00000010U
10254 #define DSI_PSR_UAN0 0x00000020U
10255 #define DSI_PSR_RUE0 0x00000040U
10256 #define DSI_PSR_PSS1 0x00000080U
10257 #define DSI_PSR_UAN1 0x00000100U
10259 /******************* Bit definition for DSI_ISR0 register ***************/
10260 #define DSI_ISR0_AE0 0x00000001U
10261 #define DSI_ISR0_AE1 0x00000002U
10262 #define DSI_ISR0_AE2 0x00000004U
10263 #define DSI_ISR0_AE3 0x00000008U
10264 #define DSI_ISR0_AE4 0x00000010U
10265 #define DSI_ISR0_AE5 0x00000020U
10266 #define DSI_ISR0_AE6 0x00000040U
10267 #define DSI_ISR0_AE7 0x00000080U
10268 #define DSI_ISR0_AE8 0x00000100U
10269 #define DSI_ISR0_AE9 0x00000200U
10270 #define DSI_ISR0_AE10 0x00000400U
10271 #define DSI_ISR0_AE11 0x00000800U
10272 #define DSI_ISR0_AE12 0x00001000U
10273 #define DSI_ISR0_AE13 0x00002000U
10274 #define DSI_ISR0_AE14 0x00004000U
10275 #define DSI_ISR0_AE15 0x00008000U
10276 #define DSI_ISR0_PE0 0x00010000U
10277 #define DSI_ISR0_PE1 0x00020000U
10278 #define DSI_ISR0_PE2 0x00040000U
10279 #define DSI_ISR0_PE3 0x00080000U
10280 #define DSI_ISR0_PE4 0x00100000U
10282 /******************* Bit definition for DSI_ISR1 register ***************/
10283 #define DSI_ISR1_TOHSTX 0x00000001U
10284 #define DSI_ISR1_TOLPRX 0x00000002U
10285 #define DSI_ISR1_ECCSE 0x00000004U
10286 #define DSI_ISR1_ECCME 0x00000008U
10287 #define DSI_ISR1_CRCE 0x00000010U
10288 #define DSI_ISR1_PSE 0x00000020U
10289 #define DSI_ISR1_EOTPE 0x00000040U
10290 #define DSI_ISR1_LPWRE 0x00000080U
10291 #define DSI_ISR1_GCWRE 0x00000100U
10292 #define DSI_ISR1_GPWRE 0x00000200U
10293 #define DSI_ISR1_GPTXE 0x00000400U
10294 #define DSI_ISR1_GPRDE 0x00000800U
10295 #define DSI_ISR1_GPRXE 0x00001000U
10297 /******************* Bit definition for DSI_IER0 register ***************/
10298 #define DSI_IER0_AE0IE 0x00000001U
10299 #define DSI_IER0_AE1IE 0x00000002U
10300 #define DSI_IER0_AE2IE 0x00000004U
10301 #define DSI_IER0_AE3IE 0x00000008U
10302 #define DSI_IER0_AE4IE 0x00000010U
10303 #define DSI_IER0_AE5IE 0x00000020U
10304 #define DSI_IER0_AE6IE 0x00000040U
10305 #define DSI_IER0_AE7IE 0x00000080U
10306 #define DSI_IER0_AE8IE 0x00000100U
10307 #define DSI_IER0_AE9IE 0x00000200U
10308 #define DSI_IER0_AE10IE 0x00000400U
10309 #define DSI_IER0_AE11IE 0x00000800U
10310 #define DSI_IER0_AE12IE 0x00001000U
10311 #define DSI_IER0_AE13IE 0x00002000U
10312 #define DSI_IER0_AE14IE 0x00004000U
10313 #define DSI_IER0_AE15IE 0x00008000U
10314 #define DSI_IER0_PE0IE 0x00010000U
10315 #define DSI_IER0_PE1IE 0x00020000U
10316 #define DSI_IER0_PE2IE 0x00040000U
10317 #define DSI_IER0_PE3IE 0x00080000U
10318 #define DSI_IER0_PE4IE 0x00100000U
10320 /******************* Bit definition for DSI_IER1 register ***************/
10321 #define DSI_IER1_TOHSTXIE 0x00000001U
10322 #define DSI_IER1_TOLPRXIE 0x00000002U
10323 #define DSI_IER1_ECCSEIE 0x00000004U
10324 #define DSI_IER1_ECCMEIE 0x00000008U
10325 #define DSI_IER1_CRCEIE 0x00000010U
10326 #define DSI_IER1_PSEIE 0x00000020U
10327 #define DSI_IER1_EOTPEIE 0x00000040U
10328 #define DSI_IER1_LPWREIE 0x00000080U
10329 #define DSI_IER1_GCWREIE 0x00000100U
10330 #define DSI_IER1_GPWREIE 0x00000200U
10331 #define DSI_IER1_GPTXEIE 0x00000400U
10332 #define DSI_IER1_GPRDEIE 0x00000800U
10333 #define DSI_IER1_GPRXEIE 0x00001000U
10335 /******************* Bit definition for DSI_FIR0 register ***************/
10336 #define DSI_FIR0_FAE0 0x00000001U
10337 #define DSI_FIR0_FAE1 0x00000002U
10338 #define DSI_FIR0_FAE2 0x00000004U
10339 #define DSI_FIR0_FAE3 0x00000008U
10340 #define DSI_FIR0_FAE4 0x00000010U
10341 #define DSI_FIR0_FAE5 0x00000020U
10342 #define DSI_FIR0_FAE6 0x00000040U
10343 #define DSI_FIR0_FAE7 0x00000080U
10344 #define DSI_FIR0_FAE8 0x00000100U
10345 #define DSI_FIR0_FAE9 0x00000200U
10346 #define DSI_FIR0_FAE10 0x00000400U
10347 #define DSI_FIR0_FAE11 0x00000800U
10348 #define DSI_FIR0_FAE12 0x00001000U
10349 #define DSI_FIR0_FAE13 0x00002000U
10350 #define DSI_FIR0_FAE14 0x00004000U
10351 #define DSI_FIR0_FAE15 0x00008000U
10352 #define DSI_FIR0_FPE0 0x00010000U
10353 #define DSI_FIR0_FPE1 0x00020000U
10354 #define DSI_FIR0_FPE2 0x00040000U
10355 #define DSI_FIR0_FPE3 0x00080000U
10356 #define DSI_FIR0_FPE4 0x00100000U
10358 /******************* Bit definition for DSI_FIR1 register ***************/
10359 #define DSI_FIR1_FTOHSTX 0x00000001U
10360 #define DSI_FIR1_FTOLPRX 0x00000002U
10361 #define DSI_FIR1_FECCSE 0x00000004U
10362 #define DSI_FIR1_FECCME 0x00000008U
10363 #define DSI_FIR1_FCRCE 0x00000010U
10364 #define DSI_FIR1_FPSE 0x00000020U
10365 #define DSI_FIR1_FEOTPE 0x00000040U
10366 #define DSI_FIR1_FLPWRE 0x00000080U
10367 #define DSI_FIR1_FGCWRE 0x00000100U
10368 #define DSI_FIR1_FGPWRE 0x00000200U
10369 #define DSI_FIR1_FGPTXE 0x00000400U
10370 #define DSI_FIR1_FGPRDE 0x00000800U
10371 #define DSI_FIR1_FGPRXE 0x00001000U
10373 /******************* Bit definition for DSI_VSCR register ***************/
10374 #define DSI_VSCR_EN 0x00000001U
10375 #define DSI_VSCR_UR 0x00000100U
10377 /******************* Bit definition for DSI_LCVCIDR register ************/
10378 #define DSI_LCVCIDR_VCID 0x00000003U
10379 #define DSI_LCVCIDR_VCID0 0x00000001U
10380 #define DSI_LCVCIDR_VCID1 0x00000002U
10381 
10382 /******************* Bit definition for DSI_LCCCR register **************/
10383 #define DSI_LCCCR_COLC 0x0000000FU
10384 #define DSI_LCCCR_COLC0 0x00000001U
10385 #define DSI_LCCCR_COLC1 0x00000002U
10386 #define DSI_LCCCR_COLC2 0x00000004U
10387 #define DSI_LCCCR_COLC3 0x00000008U
10388 
10389 #define DSI_LCCCR_LPE 0x00000100U
10391 /******************* Bit definition for DSI_LPMCCR register *************/
10392 #define DSI_LPMCCR_VLPSIZE 0x000000FFU
10393 #define DSI_LPMCCR_VLPSIZE0 0x00000001U
10394 #define DSI_LPMCCR_VLPSIZE1 0x00000002U
10395 #define DSI_LPMCCR_VLPSIZE2 0x00000004U
10396 #define DSI_LPMCCR_VLPSIZE3 0x00000008U
10397 #define DSI_LPMCCR_VLPSIZE4 0x00000010U
10398 #define DSI_LPMCCR_VLPSIZE5 0x00000020U
10399 #define DSI_LPMCCR_VLPSIZE6 0x00000040U
10400 #define DSI_LPMCCR_VLPSIZE7 0x00000080U
10401 
10402 #define DSI_LPMCCR_LPSIZE 0x00FF0000U
10403 #define DSI_LPMCCR_LPSIZE0 0x00010000U
10404 #define DSI_LPMCCR_LPSIZE1 0x00020000U
10405 #define DSI_LPMCCR_LPSIZE2 0x00040000U
10406 #define DSI_LPMCCR_LPSIZE3 0x00080000U
10407 #define DSI_LPMCCR_LPSIZE4 0x00100000U
10408 #define DSI_LPMCCR_LPSIZE5 0x00200000U
10409 #define DSI_LPMCCR_LPSIZE6 0x00400000U
10410 #define DSI_LPMCCR_LPSIZE7 0x00800000U
10411 
10412 /******************* Bit definition for DSI_VMCCR register **************/
10413 #define DSI_VMCCR_VMT 0x00000003U
10414 #define DSI_VMCCR_VMT0 0x00000001U
10415 #define DSI_VMCCR_VMT1 0x00000002U
10416 
10417 #define DSI_VMCCR_LPVSAE 0x00000100U
10418 #define DSI_VMCCR_LPVBPE 0x00000200U
10419 #define DSI_VMCCR_LPVFPE 0x00000400U
10420 #define DSI_VMCCR_LPVAE 0x00000800U
10421 #define DSI_VMCCR_LPHBPE 0x00001000U
10422 #define DSI_VMCCR_LPHFE 0x00002000U
10423 #define DSI_VMCCR_FBTAAE 0x00004000U
10424 #define DSI_VMCCR_LPCE 0x00008000U
10426 /******************* Bit definition for DSI_VPCCR register **************/
10427 #define DSI_VPCCR_VPSIZE 0x00003FFFU
10428 #define DSI_VPCCR_VPSIZE0 0x00000001U
10429 #define DSI_VPCCR_VPSIZE1 0x00000002U
10430 #define DSI_VPCCR_VPSIZE2 0x00000004U
10431 #define DSI_VPCCR_VPSIZE3 0x00000008U
10432 #define DSI_VPCCR_VPSIZE4 0x00000010U
10433 #define DSI_VPCCR_VPSIZE5 0x00000020U
10434 #define DSI_VPCCR_VPSIZE6 0x00000040U
10435 #define DSI_VPCCR_VPSIZE7 0x00000080U
10436 #define DSI_VPCCR_VPSIZE8 0x00000100U
10437 #define DSI_VPCCR_VPSIZE9 0x00000200U
10438 #define DSI_VPCCR_VPSIZE10 0x00000400U
10439 #define DSI_VPCCR_VPSIZE11 0x00000800U
10440 #define DSI_VPCCR_VPSIZE12 0x00001000U
10441 #define DSI_VPCCR_VPSIZE13 0x00002000U
10442 
10443 /******************* Bit definition for DSI_VCCCR register **************/
10444 #define DSI_VCCCR_NUMC 0x00001FFFU
10445 #define DSI_VCCCR_NUMC0 0x00000001U
10446 #define DSI_VCCCR_NUMC1 0x00000002U
10447 #define DSI_VCCCR_NUMC2 0x00000004U
10448 #define DSI_VCCCR_NUMC3 0x00000008U
10449 #define DSI_VCCCR_NUMC4 0x00000010U
10450 #define DSI_VCCCR_NUMC5 0x00000020U
10451 #define DSI_VCCCR_NUMC6 0x00000040U
10452 #define DSI_VCCCR_NUMC7 0x00000080U
10453 #define DSI_VCCCR_NUMC8 0x00000100U
10454 #define DSI_VCCCR_NUMC9 0x00000200U
10455 #define DSI_VCCCR_NUMC10 0x00000400U
10456 #define DSI_VCCCR_NUMC11 0x00000800U
10457 #define DSI_VCCCR_NUMC12 0x00001000U
10458 
10459 /******************* Bit definition for DSI_VNPCCR register *************/
10460 #define DSI_VNPCCR_NPSIZE 0x00001FFFU
10461 #define DSI_VNPCCR_NPSIZE0 0x00000001U
10462 #define DSI_VNPCCR_NPSIZE1 0x00000002U
10463 #define DSI_VNPCCR_NPSIZE2 0x00000004U
10464 #define DSI_VNPCCR_NPSIZE3 0x00000008U
10465 #define DSI_VNPCCR_NPSIZE4 0x00000010U
10466 #define DSI_VNPCCR_NPSIZE5 0x00000020U
10467 #define DSI_VNPCCR_NPSIZE6 0x00000040U
10468 #define DSI_VNPCCR_NPSIZE7 0x00000080U
10469 #define DSI_VNPCCR_NPSIZE8 0x00000100U
10470 #define DSI_VNPCCR_NPSIZE9 0x00000200U
10471 #define DSI_VNPCCR_NPSIZE10 0x00000400U
10472 #define DSI_VNPCCR_NPSIZE11 0x00000800U
10473 #define DSI_VNPCCR_NPSIZE12 0x00001000U
10474 
10475 /******************* Bit definition for DSI_VHSACCR register ************/
10476 #define DSI_VHSACCR_HSA 0x00000FFFU
10477 #define DSI_VHSACCR_HSA0 0x00000001U
10478 #define DSI_VHSACCR_HSA1 0x00000002U
10479 #define DSI_VHSACCR_HSA2 0x00000004U
10480 #define DSI_VHSACCR_HSA3 0x00000008U
10481 #define DSI_VHSACCR_HSA4 0x00000010U
10482 #define DSI_VHSACCR_HSA5 0x00000020U
10483 #define DSI_VHSACCR_HSA6 0x00000040U
10484 #define DSI_VHSACCR_HSA7 0x00000080U
10485 #define DSI_VHSACCR_HSA8 0x00000100U
10486 #define DSI_VHSACCR_HSA9 0x00000200U
10487 #define DSI_VHSACCR_HSA10 0x00000400U
10488 #define DSI_VHSACCR_HSA11 0x00000800U
10489 
10490 /******************* Bit definition for DSI_VHBPCCR register ************/
10491 #define DSI_VHBPCCR_HBP 0x00000FFFU
10492 #define DSI_VHBPCCR_HBP0 0x00000001U
10493 #define DSI_VHBPCCR_HBP1 0x00000002U
10494 #define DSI_VHBPCCR_HBP2 0x00000004U
10495 #define DSI_VHBPCCR_HBP3 0x00000008U
10496 #define DSI_VHBPCCR_HBP4 0x00000010U
10497 #define DSI_VHBPCCR_HBP5 0x00000020U
10498 #define DSI_VHBPCCR_HBP6 0x00000040U
10499 #define DSI_VHBPCCR_HBP7 0x00000080U
10500 #define DSI_VHBPCCR_HBP8 0x00000100U
10501 #define DSI_VHBPCCR_HBP9 0x00000200U
10502 #define DSI_VHBPCCR_HBP10 0x00000400U
10503 #define DSI_VHBPCCR_HBP11 0x00000800U
10504 
10505 /******************* Bit definition for DSI_VLCCR register **************/
10506 #define DSI_VLCCR_HLINE 0x00007FFFU
10507 #define DSI_VLCCR_HLINE0 0x00000001U
10508 #define DSI_VLCCR_HLINE1 0x00000002U
10509 #define DSI_VLCCR_HLINE2 0x00000004U
10510 #define DSI_VLCCR_HLINE3 0x00000008U
10511 #define DSI_VLCCR_HLINE4 0x00000010U
10512 #define DSI_VLCCR_HLINE5 0x00000020U
10513 #define DSI_VLCCR_HLINE6 0x00000040U
10514 #define DSI_VLCCR_HLINE7 0x00000080U
10515 #define DSI_VLCCR_HLINE8 0x00000100U
10516 #define DSI_VLCCR_HLINE9 0x00000200U
10517 #define DSI_VLCCR_HLINE10 0x00000400U
10518 #define DSI_VLCCR_HLINE11 0x00000800U
10519 #define DSI_VLCCR_HLINE12 0x00001000U
10520 #define DSI_VLCCR_HLINE13 0x00002000U
10521 #define DSI_VLCCR_HLINE14 0x00004000U
10522 
10523 /******************* Bit definition for DSI_VVSACCR register ***************/
10524 #define DSI_VVSACCR_VSA 0x000003FFU
10525 #define DSI_VVSACCR_VSA0 0x00000001U
10526 #define DSI_VVSACCR_VSA1 0x00000002U
10527 #define DSI_VVSACCR_VSA2 0x00000004U
10528 #define DSI_VVSACCR_VSA3 0x00000008U
10529 #define DSI_VVSACCR_VSA4 0x00000010U
10530 #define DSI_VVSACCR_VSA5 0x00000020U
10531 #define DSI_VVSACCR_VSA6 0x00000040U
10532 #define DSI_VVSACCR_VSA7 0x00000080U
10533 #define DSI_VVSACCR_VSA8 0x00000100U
10534 #define DSI_VVSACCR_VSA9 0x00000200U
10535 
10536 /******************* Bit definition for DSI_VVBPCCR register ************/
10537 #define DSI_VVBPCCR_VBP 0x000003FFU
10538 #define DSI_VVBPCCR_VBP0 0x00000001U
10539 #define DSI_VVBPCCR_VBP1 0x00000002U
10540 #define DSI_VVBPCCR_VBP2 0x00000004U
10541 #define DSI_VVBPCCR_VBP3 0x00000008U
10542 #define DSI_VVBPCCR_VBP4 0x00000010U
10543 #define DSI_VVBPCCR_VBP5 0x00000020U
10544 #define DSI_VVBPCCR_VBP6 0x00000040U
10545 #define DSI_VVBPCCR_VBP7 0x00000080U
10546 #define DSI_VVBPCCR_VBP8 0x00000100U
10547 #define DSI_VVBPCCR_VBP9 0x00000200U
10548 
10549 /******************* Bit definition for DSI_VVFPCCR register ************/
10550 #define DSI_VVFPCCR_VFP 0x000003FFU
10551 #define DSI_VVFPCCR_VFP0 0x00000001U
10552 #define DSI_VVFPCCR_VFP1 0x00000002U
10553 #define DSI_VVFPCCR_VFP2 0x00000004U
10554 #define DSI_VVFPCCR_VFP3 0x00000008U
10555 #define DSI_VVFPCCR_VFP4 0x00000010U
10556 #define DSI_VVFPCCR_VFP5 0x00000020U
10557 #define DSI_VVFPCCR_VFP6 0x00000040U
10558 #define DSI_VVFPCCR_VFP7 0x00000080U
10559 #define DSI_VVFPCCR_VFP8 0x00000100U
10560 #define DSI_VVFPCCR_VFP9 0x00000200U
10561 
10562 /******************* Bit definition for DSI_VVACCR register *************/
10563 #define DSI_VVACCR_VA 0x00003FFFU
10564 #define DSI_VVACCR_VA0 0x00000001U
10565 #define DSI_VVACCR_VA1 0x00000002U
10566 #define DSI_VVACCR_VA2 0x00000004U
10567 #define DSI_VVACCR_VA3 0x00000008U
10568 #define DSI_VVACCR_VA4 0x00000010U
10569 #define DSI_VVACCR_VA5 0x00000020U
10570 #define DSI_VVACCR_VA6 0x00000040U
10571 #define DSI_VVACCR_VA7 0x00000080U
10572 #define DSI_VVACCR_VA8 0x00000100U
10573 #define DSI_VVACCR_VA9 0x00000200U
10574 #define DSI_VVACCR_VA10 0x00000400U
10575 #define DSI_VVACCR_VA11 0x00000800U
10576 #define DSI_VVACCR_VA12 0x00001000U
10577 #define DSI_VVACCR_VA13 0x00002000U
10578 
10579 /******************* Bit definition for DSI_TDCCR register **************/
10580 #define DSI_TDCCR_3DM 0x00000003U
10581 #define DSI_TDCCR_3DM0 0x00000001U
10582 #define DSI_TDCCR_3DM1 0x00000002U
10583 
10584 #define DSI_TDCCR_3DF 0x0000000CU
10585 #define DSI_TDCCR_3DF0 0x00000004U
10586 #define DSI_TDCCR_3DF1 0x00000008U
10587 
10588 #define DSI_TDCCR_SVS 0x00000010U
10589 #define DSI_TDCCR_RF 0x00000020U
10590 #define DSI_TDCCR_S3DC 0x00010000U
10592 /******************* Bit definition for DSI_WCFGR register ***************/
10593 #define DSI_WCFGR_DSIM 0x00000001U
10594 #define DSI_WCFGR_COLMUX 0x0000000EU
10595 #define DSI_WCFGR_COLMUX0 0x00000002U
10596 #define DSI_WCFGR_COLMUX1 0x00000004U
10597 #define DSI_WCFGR_COLMUX2 0x00000008U
10598 
10599 #define DSI_WCFGR_TESRC 0x00000010U
10600 #define DSI_WCFGR_TEPOL 0x00000020U
10601 #define DSI_WCFGR_AR 0x00000040U
10602 #define DSI_WCFGR_VSPOL 0x00000080U
10604 /******************* Bit definition for DSI_WCR register *****************/
10605 #define DSI_WCR_COLM 0x00000001U
10606 #define DSI_WCR_SHTDN 0x00000002U
10607 #define DSI_WCR_LTDCEN 0x00000004U
10608 #define DSI_WCR_DSIEN 0x00000008U
10610 /******************* Bit definition for DSI_WIER register ****************/
10611 #define DSI_WIER_TEIE 0x00000001U
10612 #define DSI_WIER_ERIE 0x00000002U
10613 #define DSI_WIER_PLLLIE 0x00000200U
10614 #define DSI_WIER_PLLUIE 0x00000400U
10615 #define DSI_WIER_RRIE 0x00002000U
10617 /******************* Bit definition for DSI_WISR register ****************/
10618 #define DSI_WISR_TEIF 0x00000001U
10619 #define DSI_WISR_ERIF 0x00000002U
10620 #define DSI_WISR_BUSY 0x00000004U
10621 #define DSI_WISR_PLLLS 0x00000100U
10622 #define DSI_WISR_PLLLIF 0x00000200U
10623 #define DSI_WISR_PLLUIF 0x00000400U
10624 #define DSI_WISR_RRS 0x00001000U
10625 #define DSI_WISR_RRIF 0x00002000U
10627 /******************* Bit definition for DSI_WIFCR register ***************/
10628 #define DSI_WIFCR_CTEIF 0x00000001U
10629 #define DSI_WIFCR_CERIF 0x00000002U
10630 #define DSI_WIFCR_CPLLLIF 0x00000200U
10631 #define DSI_WIFCR_CPLLUIF 0x00000400U
10632 #define DSI_WIFCR_CRRIF 0x00002000U
10634 /******************* Bit definition for DSI_WPCR0 register ***************/
10635 #define DSI_WPCR0_UIX4 0x0000003FU
10636 #define DSI_WPCR0_UIX4_0 0x00000001U
10637 #define DSI_WPCR0_UIX4_1 0x00000002U
10638 #define DSI_WPCR0_UIX4_2 0x00000004U
10639 #define DSI_WPCR0_UIX4_3 0x00000008U
10640 #define DSI_WPCR0_UIX4_4 0x00000010U
10641 #define DSI_WPCR0_UIX4_5 0x00000020U
10642 
10643 #define DSI_WPCR0_SWCL 0x00000040U
10644 #define DSI_WPCR0_SWDL0 0x00000080U
10645 #define DSI_WPCR0_SWDL1 0x00000100U
10646 #define DSI_WPCR0_HSICL 0x00000200U
10647 #define DSI_WPCR0_HSIDL0 0x00000400U
10648 #define DSI_WPCR0_HSIDL1 0x00000800U
10649 #define DSI_WPCR0_FTXSMCL 0x00001000U
10650 #define DSI_WPCR0_FTXSMDL 0x00002000U
10651 #define DSI_WPCR0_CDOFFDL 0x00004000U
10652 #define DSI_WPCR0_TDDL 0x00010000U
10653 #define DSI_WPCR0_PDEN 0x00040000U
10654 #define DSI_WPCR0_TCLKPREPEN 0x00080000U
10655 #define DSI_WPCR0_TCLKZEROEN 0x00100000U
10656 #define DSI_WPCR0_THSPREPEN 0x00200000U
10657 #define DSI_WPCR0_THSTRAILEN 0x00400000U
10658 #define DSI_WPCR0_THSZEROEN 0x00800000U
10659 #define DSI_WPCR0_TLPXDEN 0x01000000U
10660 #define DSI_WPCR0_THSEXITEN 0x02000000U
10661 #define DSI_WPCR0_TLPXCEN 0x04000000U
10662 #define DSI_WPCR0_TCLKPOSTEN 0x08000000U
10664 /******************* Bit definition for DSI_WPCR1 register ***************/
10665 #define DSI_WPCR1_HSTXDCL 0x00000003U
10666 #define DSI_WPCR1_HSTXDCL0 0x00000001U
10667 #define DSI_WPCR1_HSTXDCL1 0x00000002U
10668 
10669 #define DSI_WPCR1_HSTXDDL 0x0000000CU
10670 #define DSI_WPCR1_HSTXDDL0 0x00000004U
10671 #define DSI_WPCR1_HSTXDDL1 0x00000008U
10672 
10673 #define DSI_WPCR1_LPSRCCL 0x000000C0U
10674 #define DSI_WPCR1_LPSRCCL0 0x00000040U
10675 #define DSI_WPCR1_LPSRCCL1 0x00000080U
10676 
10677 #define DSI_WPCR1_LPSRCDL 0x00000300U
10678 #define DSI_WPCR1_LPSRCDL0 0x00000100U
10679 #define DSI_WPCR1_LPSRCDL1 0x00000200U
10680 
10681 #define DSI_WPCR1_SDDC 0x00001000U
10683 #define DSI_WPCR1_LPRXVCDL 0x0000C000U
10684 #define DSI_WPCR1_LPRXVCDL0 0x00004000U
10685 #define DSI_WPCR1_LPRXVCDL1 0x00008000U
10686 
10687 #define DSI_WPCR1_HSTXSRCCL 0x00030000U
10688 #define DSI_WPCR1_HSTXSRCCL0 0x00010000U
10689 #define DSI_WPCR1_HSTXSRCCL1 0x00020000U
10690 
10691 #define DSI_WPCR1_HSTXSRCDL 0x000C0000U
10692 #define DSI_WPCR1_HSTXSRCDL0 0x00040000U
10693 #define DSI_WPCR1_HSTXSRCDL1 0x00080000U
10694 
10695 #define DSI_WPCR1_FLPRXLPM 0x00400000U
10697 #define DSI_WPCR1_LPRXFT 0x06000000U
10698 #define DSI_WPCR1_LPRXFT0 0x02000000U
10699 #define DSI_WPCR1_LPRXFT1 0x04000000U
10700 
10701 /******************* Bit definition for DSI_WPCR2 register ***************/
10702 #define DSI_WPCR2_TCLKPREP 0x000000FFU
10703 #define DSI_WPCR2_TCLKPREP0 0x00000001U
10704 #define DSI_WPCR2_TCLKPREP1 0x00000002U
10705 #define DSI_WPCR2_TCLKPREP2 0x00000004U
10706 #define DSI_WPCR2_TCLKPREP3 0x00000008U
10707 #define DSI_WPCR2_TCLKPREP4 0x00000010U
10708 #define DSI_WPCR2_TCLKPREP5 0x00000020U
10709 #define DSI_WPCR2_TCLKPREP6 0x00000040U
10710 #define DSI_WPCR2_TCLKPREP7 0x00000080U
10711 
10712 #define DSI_WPCR2_TCLKZERO 0x0000FF00U
10713 #define DSI_WPCR2_TCLKZERO0 0x00000100U
10714 #define DSI_WPCR2_TCLKZERO1 0x00000200U
10715 #define DSI_WPCR2_TCLKZERO2 0x00000400U
10716 #define DSI_WPCR2_TCLKZERO3 0x00000800U
10717 #define DSI_WPCR2_TCLKZERO4 0x00001000U
10718 #define DSI_WPCR2_TCLKZERO5 0x00002000U
10719 #define DSI_WPCR2_TCLKZERO6 0x00004000U
10720 #define DSI_WPCR2_TCLKZERO7 0x00008000U
10721 
10722 #define DSI_WPCR2_THSPREP 0x00FF0000U
10723 #define DSI_WPCR2_THSPREP0 0x00010000U
10724 #define DSI_WPCR2_THSPREP1 0x00020000U
10725 #define DSI_WPCR2_THSPREP2 0x00040000U
10726 #define DSI_WPCR2_THSPREP3 0x00080000U
10727 #define DSI_WPCR2_THSPREP4 0x00100000U
10728 #define DSI_WPCR2_THSPREP5 0x00200000U
10729 #define DSI_WPCR2_THSPREP6 0x00400000U
10730 #define DSI_WPCR2_THSPREP7 0x00800000U
10731 
10732 #define DSI_WPCR2_THSTRAIL 0xFF000000U
10733 #define DSI_WPCR2_THSTRAIL0 0x01000000U
10734 #define DSI_WPCR2_THSTRAIL1 0x02000000U
10735 #define DSI_WPCR2_THSTRAIL2 0x04000000U
10736 #define DSI_WPCR2_THSTRAIL3 0x08000000U
10737 #define DSI_WPCR2_THSTRAIL4 0x10000000U
10738 #define DSI_WPCR2_THSTRAIL5 0x20000000U
10739 #define DSI_WPCR2_THSTRAIL6 0x40000000U
10740 #define DSI_WPCR2_THSTRAIL7 0x80000000U
10741 
10742 /******************* Bit definition for DSI_WPCR3 register ***************/
10743 #define DSI_WPCR3_THSZERO 0x000000FFU
10744 #define DSI_WPCR3_THSZERO0 0x00000001U
10745 #define DSI_WPCR3_THSZERO1 0x00000002U
10746 #define DSI_WPCR3_THSZERO2 0x00000004U
10747 #define DSI_WPCR3_THSZERO3 0x00000008U
10748 #define DSI_WPCR3_THSZERO4 0x00000010U
10749 #define DSI_WPCR3_THSZERO5 0x00000020U
10750 #define DSI_WPCR3_THSZERO6 0x00000040U
10751 #define DSI_WPCR3_THSZERO7 0x00000080U
10752 
10753 #define DSI_WPCR3_TLPXD 0x0000FF00U
10754 #define DSI_WPCR3_TLPXD0 0x00000100U
10755 #define DSI_WPCR3_TLPXD1 0x00000200U
10756 #define DSI_WPCR3_TLPXD2 0x00000400U
10757 #define DSI_WPCR3_TLPXD3 0x00000800U
10758 #define DSI_WPCR3_TLPXD4 0x00001000U
10759 #define DSI_WPCR3_TLPXD5 0x00002000U
10760 #define DSI_WPCR3_TLPXD6 0x00004000U
10761 #define DSI_WPCR3_TLPXD7 0x00008000U
10762 
10763 #define DSI_WPCR3_THSEXIT 0x00FF0000U
10764 #define DSI_WPCR3_THSEXIT0 0x00010000U
10765 #define DSI_WPCR3_THSEXIT1 0x00020000U
10766 #define DSI_WPCR3_THSEXIT2 0x00040000U
10767 #define DSI_WPCR3_THSEXIT3 0x00080000U
10768 #define DSI_WPCR3_THSEXIT4 0x00100000U
10769 #define DSI_WPCR3_THSEXIT5 0x00200000U
10770 #define DSI_WPCR3_THSEXIT6 0x00400000U
10771 #define DSI_WPCR3_THSEXIT7 0x00800000U
10772 
10773 #define DSI_WPCR3_TLPXC 0xFF000000U
10774 #define DSI_WPCR3_TLPXC0 0x01000000U
10775 #define DSI_WPCR3_TLPXC1 0x02000000U
10776 #define DSI_WPCR3_TLPXC2 0x04000000U
10777 #define DSI_WPCR3_TLPXC3 0x08000000U
10778 #define DSI_WPCR3_TLPXC4 0x10000000U
10779 #define DSI_WPCR3_TLPXC5 0x20000000U
10780 #define DSI_WPCR3_TLPXC6 0x40000000U
10781 #define DSI_WPCR3_TLPXC7 0x80000000U
10782 
10783 /******************* Bit definition for DSI_WPCR4 register ***************/
10784 #define DSI_WPCR4_TCLKPOST 0x000000FFU
10785 #define DSI_WPCR4_TCLKPOST0 0x00000001U
10786 #define DSI_WPCR4_TCLKPOST1 0x00000002U
10787 #define DSI_WPCR4_TCLKPOST2 0x00000004U
10788 #define DSI_WPCR4_TCLKPOST3 0x00000008U
10789 #define DSI_WPCR4_TCLKPOST4 0x00000010U
10790 #define DSI_WPCR4_TCLKPOST5 0x00000020U
10791 #define DSI_WPCR4_TCLKPOST6 0x00000040U
10792 #define DSI_WPCR4_TCLKPOST7 0x00000080U
10793 
10794 /******************* Bit definition for DSI_WRPCR register ***************/
10795 #define DSI_WRPCR_PLLEN 0x00000001U
10796 #define DSI_WRPCR_PLL_NDIV 0x000001FCU
10797 #define DSI_WRPCR_PLL_NDIV0 0x00000004U
10798 #define DSI_WRPCR_PLL_NDIV1 0x00000008U
10799 #define DSI_WRPCR_PLL_NDIV2 0x00000010U
10800 #define DSI_WRPCR_PLL_NDIV3 0x00000020U
10801 #define DSI_WRPCR_PLL_NDIV4 0x00000040U
10802 #define DSI_WRPCR_PLL_NDIV5 0x00000080U
10803 #define DSI_WRPCR_PLL_NDIV6 0x00000100U
10804 
10805 #define DSI_WRPCR_PLL_IDF 0x00007800U
10806 #define DSI_WRPCR_PLL_IDF0 0x00000800U
10807 #define DSI_WRPCR_PLL_IDF1 0x00001000U
10808 #define DSI_WRPCR_PLL_IDF2 0x00002000U
10809 #define DSI_WRPCR_PLL_IDF3 0x00004000U
10810 
10811 #define DSI_WRPCR_PLL_ODF 0x00030000U
10812 #define DSI_WRPCR_PLL_ODF0 0x00010000U
10813 #define DSI_WRPCR_PLL_ODF1 0x00020000U
10814 
10815 #define DSI_WRPCR_REGEN 0x01000000U
10829 /******************************* ADC Instances ********************************/
10830 #define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
10831  ((__INSTANCE__) == ADC2) || \
10832  ((__INSTANCE__) == ADC3))
10833 
10834 /******************************* CAN Instances ********************************/
10835 #define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
10836  ((__INSTANCE__) == CAN2) || \
10837  ((__INSTANCE__) == CAN3))
10838 /******************************* CRC Instances ********************************/
10839 #define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
10840 
10841 /******************************* DAC Instances ********************************/
10842 #define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)
10843 
10844 /******************************* DCMI Instances *******************************/
10845 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
10846 
10847 /****************************** DFSDM Instances *******************************/
10848 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
10849  ((INSTANCE) == DFSDM1_Filter1) || \
10850  ((INSTANCE) == DFSDM1_Filter2) || \
10851  ((INSTANCE) == DFSDM1_Filter3))
10852 
10853 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
10854  ((INSTANCE) == DFSDM1_Channel1) || \
10855  ((INSTANCE) == DFSDM1_Channel2) || \
10856  ((INSTANCE) == DFSDM1_Channel3) || \
10857  ((INSTANCE) == DFSDM1_Channel4) || \
10858  ((INSTANCE) == DFSDM1_Channel5) || \
10859  ((INSTANCE) == DFSDM1_Channel6) || \
10860  ((INSTANCE) == DFSDM1_Channel7))
10861 
10862 /******************************* DMA2D Instances *******************************/
10863 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
10864 
10865 /******************************** DMA Instances *******************************/
10866 #define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
10867  ((__INSTANCE__) == DMA1_Stream1) || \
10868  ((__INSTANCE__) == DMA1_Stream2) || \
10869  ((__INSTANCE__) == DMA1_Stream3) || \
10870  ((__INSTANCE__) == DMA1_Stream4) || \
10871  ((__INSTANCE__) == DMA1_Stream5) || \
10872  ((__INSTANCE__) == DMA1_Stream6) || \
10873  ((__INSTANCE__) == DMA1_Stream7) || \
10874  ((__INSTANCE__) == DMA2_Stream0) || \
10875  ((__INSTANCE__) == DMA2_Stream1) || \
10876  ((__INSTANCE__) == DMA2_Stream2) || \
10877  ((__INSTANCE__) == DMA2_Stream3) || \
10878  ((__INSTANCE__) == DMA2_Stream4) || \
10879  ((__INSTANCE__) == DMA2_Stream5) || \
10880  ((__INSTANCE__) == DMA2_Stream6) || \
10881  ((__INSTANCE__) == DMA2_Stream7))
10882 
10883 /******************************* GPIO Instances *******************************/
10884 #define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
10885  ((__INSTANCE__) == GPIOB) || \
10886  ((__INSTANCE__) == GPIOC) || \
10887  ((__INSTANCE__) == GPIOD) || \
10888  ((__INSTANCE__) == GPIOE) || \
10889  ((__INSTANCE__) == GPIOF) || \
10890  ((__INSTANCE__) == GPIOG) || \
10891  ((__INSTANCE__) == GPIOH) || \
10892  ((__INSTANCE__) == GPIOI) || \
10893  ((__INSTANCE__) == GPIOJ) || \
10894  ((__INSTANCE__) == GPIOK))
10895 
10896 #define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
10897  ((__INSTANCE__) == GPIOB) || \
10898  ((__INSTANCE__) == GPIOC) || \
10899  ((__INSTANCE__) == GPIOD) || \
10900  ((__INSTANCE__) == GPIOE) || \
10901  ((__INSTANCE__) == GPIOF) || \
10902  ((__INSTANCE__) == GPIOG) || \
10903  ((__INSTANCE__) == GPIOH) || \
10904  ((__INSTANCE__) == GPIOI) || \
10905  ((__INSTANCE__) == GPIOJ) || \
10906  ((__INSTANCE__) == GPIOK))
10907 
10908 /****************************** CEC Instances *********************************/
10909 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
10910 
10911 /****************************** QSPI Instances *********************************/
10912 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
10913 
10914 
10915 /******************************** I2C Instances *******************************/
10916 #define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
10917  ((__INSTANCE__) == I2C2) || \
10918  ((__INSTANCE__) == I2C3) || \
10919  ((__INSTANCE__) == I2C4))
10920 
10921 /******************************** I2S Instances *******************************/
10922 #define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
10923  ((__INSTANCE__) == SPI2) || \
10924  ((__INSTANCE__) == SPI3))
10925 
10926 /******************************* LPTIM Instances ********************************/
10927 #define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
10928 
10929 /****************************** LTDC Instances ********************************/
10930 #define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)
10931 
10932 /****************************** MDIOS Instances ********************************/
10933 #define IS_MDIOS_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == MDIOS)
10934 
10935 /****************************** MDIOS Instances ********************************/
10936 #define IS_JPEG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == JPEG)
10937 
10938 /******************************* RNG Instances ********************************/
10939 #define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
10940 
10941 /****************************** RTC Instances *********************************/
10942 #define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)
10943 
10944 /******************************* SAI Instances ********************************/
10945 #define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
10946  ((__PERIPH__) == SAI1_Block_B) || \
10947  ((__PERIPH__) == SAI2_Block_A) || \
10948  ((__PERIPH__) == SAI2_Block_B))
10949 /* Legacy define */
10950 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
10951 
10952 /******************************** SDMMC Instances *******************************/
10953 #define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SDMMC1) || \
10954  ((__INSTANCE__) == SDMMC2))
10955 
10956 /****************************** SPDIFRX Instances *********************************/
10957 #define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
10958 
10959 /******************************** SPI Instances *******************************/
10960 #define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
10961  ((__INSTANCE__) == SPI2) || \
10962  ((__INSTANCE__) == SPI3) || \
10963  ((__INSTANCE__) == SPI4) || \
10964  ((__INSTANCE__) == SPI5) || \
10965  ((__INSTANCE__) == SPI6))
10966 
10967 /****************** TIM Instances : All supported instances *******************/
10968 #define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
10969  ((__INSTANCE__) == TIM2) || \
10970  ((__INSTANCE__) == TIM3) || \
10971  ((__INSTANCE__) == TIM4) || \
10972  ((__INSTANCE__) == TIM5) || \
10973  ((__INSTANCE__) == TIM6) || \
10974  ((__INSTANCE__) == TIM7) || \
10975  ((__INSTANCE__) == TIM8) || \
10976  ((__INSTANCE__) == TIM9) || \
10977  ((__INSTANCE__) == TIM10) || \
10978  ((__INSTANCE__) == TIM11) || \
10979  ((__INSTANCE__) == TIM12) || \
10980  ((__INSTANCE__) == TIM13) || \
10981  ((__INSTANCE__) == TIM14))
10982 
10983 /************* TIM Instances : at least 1 capture/compare channel *************/
10984 #define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
10985  ((__INSTANCE__) == TIM2) || \
10986  ((__INSTANCE__) == TIM3) || \
10987  ((__INSTANCE__) == TIM4) || \
10988  ((__INSTANCE__) == TIM5) || \
10989  ((__INSTANCE__) == TIM8) || \
10990  ((__INSTANCE__) == TIM9) || \
10991  ((__INSTANCE__) == TIM10) || \
10992  ((__INSTANCE__) == TIM11) || \
10993  ((__INSTANCE__) == TIM12) || \
10994  ((__INSTANCE__) == TIM13) || \
10995  ((__INSTANCE__) == TIM14))
10996 
10997 /************ TIM Instances : at least 2 capture/compare channels *************/
10998 #define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
10999  ((__INSTANCE__) == TIM2) || \
11000  ((__INSTANCE__) == TIM3) || \
11001  ((__INSTANCE__) == TIM4) || \
11002  ((__INSTANCE__) == TIM5) || \
11003  ((__INSTANCE__) == TIM8) || \
11004  ((__INSTANCE__) == TIM9) || \
11005  ((__INSTANCE__) == TIM12))
11006 
11007 /************ TIM Instances : at least 3 capture/compare channels *************/
11008 #define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
11009  ((__INSTANCE__) == TIM2) || \
11010  ((__INSTANCE__) == TIM3) || \
11011  ((__INSTANCE__) == TIM4) || \
11012  ((__INSTANCE__) == TIM5) || \
11013  ((__INSTANCE__) == TIM8))
11014 
11015 /************ TIM Instances : at least 4 capture/compare channels *************/
11016 #define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
11017  ((__INSTANCE__) == TIM2) || \
11018  ((__INSTANCE__) == TIM3) || \
11019  ((__INSTANCE__) == TIM4) || \
11020  ((__INSTANCE__) == TIM5) || \
11021  ((__INSTANCE__) == TIM8))
11022 
11023 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
11024 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
11025  (((__INSTANCE__) == TIM1) || \
11026  ((__INSTANCE__) == TIM8))
11027 
11028 /****************** TIM Instances : supporting OCxREF clear *******************/
11029 #define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
11030  (((__INSTANCE__) == TIM1) || \
11031  ((__INSTANCE__) == TIM2) || \
11032  ((__INSTANCE__) == TIM3) || \
11033  ((__INSTANCE__) == TIM4) || \
11034  ((__INSTANCE__) == TIM8))
11035 
11036 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
11037 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
11038  (((__INSTANCE__) == TIM1) || \
11039  ((__INSTANCE__) == TIM2) || \
11040  ((__INSTANCE__) == TIM3) || \
11041  ((__INSTANCE__) == TIM4) || \
11042  ((__INSTANCE__) == TIM5) || \
11043  ((__INSTANCE__) == TIM8))
11044 
11045 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
11046 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
11047  (((__INSTANCE__) == TIM1) || \
11048  ((__INSTANCE__) == TIM2) || \
11049  ((__INSTANCE__) == TIM3) || \
11050  ((__INSTANCE__) == TIM4) || \
11051  ((__INSTANCE__) == TIM5) || \
11052  ((__INSTANCE__) == TIM8))
11053 /****************** TIM Instances : at least 5 capture/compare channels *******/
11054 #define IS_TIM_CC5_INSTANCE(__INSTANCE__)\
11055  (((__INSTANCE__) == TIM1) || \
11056  ((__INSTANCE__) == TIM8) )
11057 
11058 /****************** TIM Instances : at least 6 capture/compare channels *******/
11059 #define IS_TIM_CC6_INSTANCE(__INSTANCE__)\
11060  (((__INSTANCE__) == TIM1) || \
11061  ((__INSTANCE__) == TIM8))
11062 
11063 
11064 /******************** TIM Instances : Advanced-control timers *****************/
11065 #define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
11066  ((__INSTANCE__) == TIM8))
11067 
11068 /****************** TIM Instances : supporting 2 break inputs *****************/
11069 #define IS_TIM_BREAK_INSTANCE(__INSTANCE__)\
11070  (((__INSTANCE__) == TIM1) || \
11071  ((__INSTANCE__) == TIM8))
11072 
11073 /******************* TIM Instances : Timer input XOR function *****************/
11074 #define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
11075  ((__INSTANCE__) == TIM2) || \
11076  ((__INSTANCE__) == TIM3) || \
11077  ((__INSTANCE__) == TIM4) || \
11078  ((__INSTANCE__) == TIM5) || \
11079  ((__INSTANCE__) == TIM8))
11080 
11081 /****************** TIM Instances : DMA requests generation (UDE) *************/
11082 #define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
11083  ((__INSTANCE__) == TIM2) || \
11084  ((__INSTANCE__) == TIM3) || \
11085  ((__INSTANCE__) == TIM4) || \
11086  ((__INSTANCE__) == TIM5) || \
11087  ((__INSTANCE__) == TIM6) || \
11088  ((__INSTANCE__) == TIM7) || \
11089  ((__INSTANCE__) == TIM8))
11090 
11091 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
11092 #define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
11093  ((__INSTANCE__) == TIM2) || \
11094  ((__INSTANCE__) == TIM3) || \
11095  ((__INSTANCE__) == TIM4) || \
11096  ((__INSTANCE__) == TIM5) || \
11097  ((__INSTANCE__) == TIM8))
11098 
11099 /************ TIM Instances : DMA requests generation (COMDE) *****************/
11100 #define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
11101  ((__INSTANCE__) == TIM2) || \
11102  ((__INSTANCE__) == TIM3) || \
11103  ((__INSTANCE__) == TIM4) || \
11104  ((__INSTANCE__) == TIM5) || \
11105  ((__INSTANCE__) == TIM8))
11106 
11107 /******************** TIM Instances : DMA burst feature ***********************/
11108 #define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
11109  ((__INSTANCE__) == TIM2) || \
11110  ((__INSTANCE__) == TIM3) || \
11111  ((__INSTANCE__) == TIM4) || \
11112  ((__INSTANCE__) == TIM5) || \
11113  ((__INSTANCE__) == TIM8))
11114 
11115 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
11116 #define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
11117  ((__INSTANCE__) == TIM2) || \
11118  ((__INSTANCE__) == TIM3) || \
11119  ((__INSTANCE__) == TIM4) || \
11120  ((__INSTANCE__) == TIM5) || \
11121  ((__INSTANCE__) == TIM6) || \
11122  ((__INSTANCE__) == TIM7) || \
11123  ((__INSTANCE__) == TIM8) || \
11124  ((__INSTANCE__) == TIM13) || \
11125  ((__INSTANCE__) == TIM14))
11126 
11127 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
11128 #define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
11129  ((__INSTANCE__) == TIM2) || \
11130  ((__INSTANCE__) == TIM3) || \
11131  ((__INSTANCE__) == TIM4) || \
11132  ((__INSTANCE__) == TIM5) || \
11133  ((__INSTANCE__) == TIM8) || \
11134  ((__INSTANCE__) == TIM9) || \
11135  ((__INSTANCE__) == TIM12))
11136 
11137 /********************** TIM Instances : 32 bit Counter ************************/
11138 #define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)(((__INSTANCE__) == TIM2) || \
11139  ((__INSTANCE__) == TIM5))
11140 
11141 /***************** TIM Instances : external trigger input available ************/
11142 #define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
11143  ((__INSTANCE__) == TIM2) || \
11144  ((__INSTANCE__) == TIM3) || \
11145  ((__INSTANCE__) == TIM4) || \
11146  ((__INSTANCE__) == TIM5) || \
11147  ((__INSTANCE__) == TIM8))
11148 
11149 /****************** TIM Instances : remapping capability **********************/
11150 #define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
11151  ((__INSTANCE__) == TIM5) || \
11152  ((__INSTANCE__) == TIM11))
11153 
11154 /******************* TIM Instances : output(s) available **********************/
11155 #define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
11156  ((((__INSTANCE__) == TIM1) && \
11157  (((__CHANNEL__) == TIM_CHANNEL_1) || \
11158  ((__CHANNEL__) == TIM_CHANNEL_2) || \
11159  ((__CHANNEL__) == TIM_CHANNEL_3) || \
11160  ((__CHANNEL__) == TIM_CHANNEL_4))) \
11161  || \
11162  (((__INSTANCE__) == TIM2) && \
11163  (((__CHANNEL__) == TIM_CHANNEL_1) || \
11164  ((__CHANNEL__) == TIM_CHANNEL_2) || \
11165  ((__CHANNEL__) == TIM_CHANNEL_3) || \
11166  ((__CHANNEL__) == TIM_CHANNEL_4))) \
11167  || \
11168  (((__INSTANCE__) == TIM3) && \
11169  (((__CHANNEL__) == TIM_CHANNEL_1) || \
11170  ((__CHANNEL__) == TIM_CHANNEL_2) || \
11171  ((__CHANNEL__) == TIM_CHANNEL_3) || \
11172  ((__CHANNEL__) == TIM_CHANNEL_4))) \
11173  || \
11174  (((__INSTANCE__) == TIM4) && \
11175  (((__CHANNEL__) == TIM_CHANNEL_1) || \
11176  ((__CHANNEL__) == TIM_CHANNEL_2) || \
11177  ((__CHANNEL__) == TIM_CHANNEL_3) || \
11178  ((__CHANNEL__) == TIM_CHANNEL_4))) \
11179  || \
11180  (((__INSTANCE__) == TIM5) && \
11181  (((__CHANNEL__) == TIM_CHANNEL_1) || \
11182  ((__CHANNEL__) == TIM_CHANNEL_2) || \
11183  ((__CHANNEL__) == TIM_CHANNEL_3) || \
11184  ((__CHANNEL__) == TIM_CHANNEL_4))) \
11185  || \
11186  (((__INSTANCE__) == TIM8) && \
11187  (((__CHANNEL__) == TIM_CHANNEL_1) || \
11188  ((__CHANNEL__) == TIM_CHANNEL_2) || \
11189  ((__CHANNEL__) == TIM_CHANNEL_3) || \
11190  ((__CHANNEL__) == TIM_CHANNEL_4))) \
11191  || \
11192  (((__INSTANCE__) == TIM9) && \
11193  (((__CHANNEL__) == TIM_CHANNEL_1) || \
11194  ((__CHANNEL__) == TIM_CHANNEL_2))) \
11195  || \
11196  (((__INSTANCE__) == TIM10) && \
11197  (((__CHANNEL__) == TIM_CHANNEL_1))) \
11198  || \
11199  (((__INSTANCE__) == TIM11) && \
11200  (((__CHANNEL__) == TIM_CHANNEL_1))) \
11201  || \
11202  (((__INSTANCE__) == TIM12) && \
11203  (((__CHANNEL__) == TIM_CHANNEL_1) || \
11204  ((__CHANNEL__) == TIM_CHANNEL_2))) \
11205  || \
11206  (((__INSTANCE__) == TIM13) && \
11207  (((__CHANNEL__) == TIM_CHANNEL_1))) \
11208  || \
11209  (((__INSTANCE__) == TIM14) && \
11210  (((__CHANNEL__) == TIM_CHANNEL_1))))
11211 
11212 /************ TIM Instances : complementary output(s) available ***************/
11213 #define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
11214  ((((__INSTANCE__) == TIM1) && \
11215  (((__CHANNEL__) == TIM_CHANNEL_1) || \
11216  ((__CHANNEL__) == TIM_CHANNEL_2) || \
11217  ((__CHANNEL__) == TIM_CHANNEL_3))) \
11218  || \
11219  (((__INSTANCE__) == TIM8) && \
11220  (((__CHANNEL__) == TIM_CHANNEL_1) || \
11221  ((__CHANNEL__) == TIM_CHANNEL_2) || \
11222  ((__CHANNEL__) == TIM_CHANNEL_3))))
11223 
11224 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
11225 #define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
11226  (((__INSTANCE__) == TIM1) || \
11227  ((__INSTANCE__) == TIM8) )
11228 
11229 /****************** TIM Instances : supporting synchronization ****************/
11230 #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
11231  (((__INSTANCE__) == TIM1) || \
11232  ((__INSTANCE__) == TIM2) || \
11233  ((__INSTANCE__) == TIM3) || \
11234  ((__INSTANCE__) == TIM4) || \
11235  ((__INSTANCE__) == TIM5) || \
11236  ((__INSTANCE__) == TIM6) || \
11237  ((__INSTANCE__) == TIM7) || \
11238  ((__INSTANCE__) == TIM8))
11239 
11240 /******************** USART Instances : Synchronous mode **********************/
11241 #define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
11242  ((__INSTANCE__) == USART2) || \
11243  ((__INSTANCE__) == USART3) || \
11244  ((__INSTANCE__) == USART6))
11245 
11246 /******************** UART Instances : Asynchronous mode **********************/
11247 #define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
11248  ((__INSTANCE__) == USART2) || \
11249  ((__INSTANCE__) == USART3) || \
11250  ((__INSTANCE__) == UART4) || \
11251  ((__INSTANCE__) == UART5) || \
11252  ((__INSTANCE__) == USART6) || \
11253  ((__INSTANCE__) == UART7) || \
11254  ((__INSTANCE__) == UART8))
11255 
11256 /****************** UART Instances : Driver Enable *****************/
11257 #define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
11258  ((__INSTANCE__) == USART2) || \
11259  ((__INSTANCE__) == USART3) || \
11260  ((__INSTANCE__) == UART4) || \
11261  ((__INSTANCE__) == UART5) || \
11262  ((__INSTANCE__) == USART6) || \
11263  ((__INSTANCE__) == UART7) || \
11264  ((__INSTANCE__) == UART8))
11265 
11266 /****************** UART Instances : Hardware Flow control ********************/
11267 #define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
11268  ((__INSTANCE__) == USART2) || \
11269  ((__INSTANCE__) == USART3) || \
11270  ((__INSTANCE__) == UART4) || \
11271  ((__INSTANCE__) == UART5) || \
11272  ((__INSTANCE__) == USART6) || \
11273  ((__INSTANCE__) == UART7) || \
11274  ((__INSTANCE__) == UART8))
11275 
11276 /********************* UART Instances : Smart card mode ***********************/
11277 #define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
11278  ((__INSTANCE__) == USART2) || \
11279  ((__INSTANCE__) == USART3) || \
11280  ((__INSTANCE__) == USART6))
11281 
11282 /*********************** UART Instances : IRDA mode ***************************/
11283 #define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
11284  ((__INSTANCE__) == USART2) || \
11285  ((__INSTANCE__) == USART3) || \
11286  ((__INSTANCE__) == UART4) || \
11287  ((__INSTANCE__) == UART5) || \
11288  ((__INSTANCE__) == USART6) || \
11289  ((__INSTANCE__) == UART7) || \
11290  ((__INSTANCE__) == UART8))
11291 
11292 /****************************** IWDG Instances ********************************/
11293 #define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)
11294 
11295 /****************************** WWDG Instances ********************************/
11296 #define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)
11297 
11298 
11299 /******************************************************************************/
11300 /* For a painless codes migration between the STM32F7xx device product */
11301 /* lines, the aliases defined below are put in place to overcome the */
11302 /* differences in the interrupt handlers and IRQn definitions. */
11303 /* No need to update developed interrupt code when moving across */
11304 /* product lines within the same STM32F7 Family */
11305 /******************************************************************************/
11306 
11307 /* Aliases for __IRQn */
11308 #define HASH_RNG_IRQn RNG_IRQn
11309 
11310 /* Aliases for __IRQHandler */
11311 #define HASH_RNG_IRQHandler RNG_IRQHandler
11312 
11325 #ifdef __cplusplus
11326 }
11327 #endif /* __cplusplus */
11328 
11329 #endif /* __STM32F769xx_H */
11330 
11331 
11332 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
DSI_TypeDef::MCR
__IO uint32_t MCR
Definition: stm32f769xx.h:1325
RESERVED
#define RESERVED
Definition: usbh_cdc.h:68
DSI_TypeDef::VVBPCCR
__IO uint32_t VVBPCCR
Definition: stm32f769xx.h:1373
LTDC_TypeDef
LCD-TFT Display Controller.
Definition: stm32f746xx.h:661
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition: stm32f745xx.h:253
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f745xx.h:613
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f745xx.h:841
SPI5_IRQn
Definition: stm32f769xx.h:163
DSI_TypeDef::VVFPCR
__IO uint32_t VVFPCR
Definition: stm32f769xx.h:1335
DMA1_Stream2_IRQn
Definition: stm32f769xx.h:92
CAN2_SCE_IRQn
Definition: stm32f769xx.h:145
DSI_TypeDef::LCCCR
__IO uint32_t LCCCR
Definition: stm32f769xx.h:1361
OTG_FS_WKUP_IRQn
Definition: stm32f769xx.h:121
DSI_TypeDef::VVACCR
__IO uint32_t VVACCR
Definition: stm32f769xx.h:1375
SVCall_IRQn
Definition: stm32f769xx.h:74
DMA2_Stream6_IRQn
Definition: stm32f769xx.h:148
OTG_HS_EP1_IN_IRQn
Definition: stm32f769xx.h:154
DSI_TypeDef::LVCIDR
__IO uint32_t LVCIDR
Definition: stm32f769xx.h:1318
DMA2_Stream7_IRQn
Definition: stm32f769xx.h:149
EXTI4_IRQn
Definition: stm32f769xx.h:89
TIM4_IRQn
Definition: stm32f769xx.h:109
DFSDM1_FLT1_IRQn
Definition: stm32f769xx.h:178
LPTIM1_IRQn
Definition: stm32f769xx.h:171
SAI2_IRQn
Definition: stm32f769xx.h:169
ADC_IRQn
Definition: stm32f769xx.h:97
CAN1_SCE_IRQn
Definition: stm32f769xx.h:101
DSI_TypeDef::LPMCR
__IO uint32_t LPMCR
Definition: stm32f769xx.h:1321
DSI_TypeDef::RESERVED10
uint32_t RESERVED10
Definition: stm32f769xx.h:1386
EXTI1_IRQn
Definition: stm32f769xx.h:86
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f745xx.h:519
SDMMC2_IRQn
Definition: stm32f769xx.h:181
DSI_TypeDef::LCCR
__IO uint32_t LCCR
Definition: stm32f769xx.h:1337
DMA2_Stream1_IRQn
Definition: stm32f769xx.h:136
I2C4_EV_IRQn
Definition: stm32f769xx.h:173
EXTI15_10_IRQn
Definition: stm32f769xx.h:119
CAN3_RX0_IRQn
Definition: stm32f769xx.h:183
DSI_TypeDef::PUCR
__IO uint32_t PUCR
Definition: stm32f769xx.h:1349
SPDIFRX_TypeDef
SPDIF-RX Interface.
Definition: stm32f745xx.h:797
CEC_TypeDef
HDMI-CEC.
Definition: stm32f745xx.h:305
SPI4_IRQn
Definition: stm32f769xx.h:162
UART5_IRQn
Definition: stm32f769xx.h:132
SAI1_IRQn
Definition: stm32f769xx.h:165
TIM1_TRG_COM_TIM11_IRQn
Definition: stm32f769xx.h:105
FMC_Bank3_TypeDef
Flexible Memory Controller Bank3.
Definition: stm32f745xx.h:568
CRC_TypeDef
CRC calculation unit.
Definition: stm32f745xx.h:320
EXTI9_5_IRQn
Definition: stm32f769xx.h:102
DIR
Definition: ff.h:151
DFSDM1_FLT0_IRQn
Definition: stm32f769xx.h:177
CAN1_RX1_IRQn
Definition: stm32f769xx.h:100
DMA2_Stream0_IRQn
Definition: stm32f769xx.h:135
CEC_IRQn
Definition: stm32f769xx.h:172
USB_OTG_INEndpointTypeDef
USB_OTG_IN_Endpoint-Specific_Register.
Definition: stm32f745xx.h:1035
SDMMC1_IRQn
Definition: stm32f769xx.h:128
I2C2_ER_IRQn
Definition: stm32f769xx.h:113
DMA2_Stream4_IRQn
Definition: stm32f769xx.h:139
EXTI3_IRQn
Definition: stm32f769xx.h:88
CAN2_RX1_IRQn
Definition: stm32f769xx.h:144
FMC_Bank1E_TypeDef
Flexible Memory Controller Bank1E.
Definition: stm32f745xx.h:559
DMA_TypeDef
Definition: stm32f745xx.h:400
TAMP_STAMP_IRQn
Definition: stm32f769xx.h:81
DSI_TypeDef::LPMCCR
__IO uint32_t LPMCCR
Definition: stm32f769xx.h:1363
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f745xx.h:948
DSI_TypeDef::VHSACR
__IO uint32_t VHSACR
Definition: stm32f769xx.h:1330
DFSDM1_FLT2_IRQn
Definition: stm32f769xx.h:179
DSI_TypeDef::PCTLR
__IO uint32_t PCTLR
Definition: stm32f769xx.h:1347
DSI_TypeDef::VR
__IO uint32_t VR
Definition: stm32f769xx.h:1315
UART4_IRQn
Definition: stm32f769xx.h:131
DMA1_Stream6_IRQn
Definition: stm32f769xx.h:96
RTC_Alarm_IRQn
Definition: stm32f769xx.h:120
__I
#define __I
Definition: core_cm0.h:210
DSI_TypeDef::VCCR
__IO uint32_t VCCR
Definition: stm32f769xx.h:1328
DMA1_Stream5_IRQn
Definition: stm32f769xx.h:95
SPI2_IRQn
Definition: stm32f769xx.h:115
LTDC_Layer_TypeDef
LCD-TFT Display layer x Controller.
Definition: stm32f746xx.h:686
DSI_TypeDef::VVBPCR
__IO uint32_t VVBPCR
Definition: stm32f769xx.h:1334
CAN3_RX1_IRQn
Definition: stm32f769xx.h:184
DSI_TypeDef::PTTCR
__IO uint32_t PTTCR
Definition: stm32f769xx.h:1350
USB_OTG_GlobalTypeDef
USB_OTG_Core_Registers.
Definition: stm32f745xx.h:974
DMA1_Stream1_IRQn
Definition: stm32f769xx.h:91
DSI_TypeDef::VVFPCCR
__IO uint32_t VVFPCCR
Definition: stm32f769xx.h:1374
DSI_TypeDef::PCONFR
__IO uint32_t PCONFR
Definition: stm32f769xx.h:1348
DSI_TypeDef::VNPCCR
__IO uint32_t VNPCCR
Definition: stm32f769xx.h:1368
PendSV_IRQn
Definition: stm32f769xx.h:76
UART7_IRQn
Definition: stm32f769xx.h:160
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f745xx.h:596
BusFault_IRQn
Definition: stm32f769xx.h:72
I2C2_EV_IRQn
Definition: stm32f769xx.h:112
MDIOS_IRQn
Definition: stm32f769xx.h:187
TIM8_TRG_COM_TIM14_IRQn
Definition: stm32f769xx.h:124
QUADSPI_TypeDef
QUAD Serial Peripheral Interface.
Definition: stm32f745xx.h:858
DSI_TypeDef::WIFCR
__IO uint32_t WIFCR
Definition: stm32f769xx.h:1383
CAN2_TX_IRQn
Definition: stm32f769xx.h:142
I2C1_EV_IRQn
Definition: stm32f769xx.h:110
CAN_TypeDef
Controller Area Network.
Definition: stm32f745xx.h:275
LPTIM_TypeDef
LPTIMIMER.
Definition: stm32f745xx.h:911
FMC_IRQn
Definition: stm32f769xx.h:127
DCMI_IRQn
Definition: stm32f769xx.h:157
TIM7_IRQn
Definition: stm32f769xx.h:134
DMA2D_TypeDef
DMA2D Controller.
Definition: stm32f745xx.h:413
RCC_IRQn
Definition: stm32f769xx.h:84
DSI_TypeDef::PSR
__IO uint32_t PSR
Definition: stm32f769xx.h:1351
I2C3_EV_IRQn
Definition: stm32f769xx.h:151
__IO
#define __IO
Definition: core_cm0.h:213
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32f745xx.h:204
DSI_TypeDef::GPDR
__IO uint32_t GPDR
Definition: stm32f769xx.h:1340
SysTick_IRQn
Definition: stm32f769xx.h:77
DSI_TypeDef::CLTCR
__IO uint32_t CLTCR
Definition: stm32f769xx.h:1345
SAI_TypeDef
Serial Audio Interface.
Definition: stm32f745xx.h:776
DMA1_Stream0_IRQn
Definition: stm32f769xx.h:90
DSI_TypeDef::CMCR
__IO uint32_t CMCR
Definition: stm32f769xx.h:1338
USB_OTG_HostTypeDef
USB_OTG_Host_Mode_Register_Structures.
Definition: stm32f745xx.h:1066
IRQn_Type
IRQn_Type
STM32F7xx Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f769xx.h:67
QUADSPI_IRQn
Definition: stm32f769xx.h:170
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition: stm32f745xx.h:241
ETH_TypeDef
Ethernet MAC.
Definition: stm32f745xx.h:445
TIM2_IRQn
Definition: stm32f769xx.h:107
DSI_TypeDef::CLCR
__IO uint32_t CLCR
Definition: stm32f769xx.h:1344
SPI3_IRQn
Definition: stm32f769xx.h:130
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f745xx.h:928
TIM_TypeDef
TIM.
Definition: stm32f745xx.h:879
DMA1_Stream7_IRQn
Definition: stm32f769xx.h:126
DMA2_Stream5_IRQn
Definition: stm32f769xx.h:147
DFSDM_Filter_TypeDef
DFSDM module registers.
Definition: stm32f765xx.h:367
DSI_TypeDef::VLCCR
__IO uint32_t VLCCR
Definition: stm32f769xx.h:1371
USART1_IRQn
Definition: stm32f769xx.h:116
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f745xx.h:390
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32f745xx.h:336
USB_OTG_HostChannelTypeDef
USB_OTG_Host_Channel_Specific_Registers.
Definition: stm32f745xx.h:1080
OTG_HS_WKUP_IRQn
Definition: stm32f769xx.h:155
I2C4_ER_IRQn
Definition: stm32f769xx.h:174
FLASH_TypeDef
FLASH Registers.
Definition: stm32f745xx.h:533
DMA2_Stream2_IRQn
Definition: stm32f769xx.h:137
PWR_TypeDef
Power Control.
Definition: stm32f745xx.h:660
PVD_IRQn
Definition: stm32f769xx.h:80
ETH_IRQn
Definition: stm32f769xx.h:140
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f745xx.h:645
DSI_IRQn
Definition: stm32f769xx.h:176
FPU_IRQn
Definition: stm32f769xx.h:159
DFSDM_Channel_TypeDef
DFSDM channel configuration registers.
Definition: stm32f765xx.h:389
DSI_TypeDef::GVCIDR
__IO uint32_t GVCIDR
Definition: stm32f769xx.h:1324
DSI_TypeDef::WCR
__IO uint32_t WCR
Definition: stm32f769xx.h:1380
OTG_HS_EP1_OUT_IRQn
Definition: stm32f769xx.h:153
DSI_TypeDef::LCOLCR
__IO uint32_t LCOLCR
Definition: stm32f769xx.h:1319
DSI_TypeDef::VHBPCCR
__IO uint32_t VHBPCCR
Definition: stm32f769xx.h:1370
JPEG_TypeDef
JPEG Codec.
Definition: stm32f767xx.h:1194
DSI_TypeDef::GPSR
__IO uint32_t GPSR
Definition: stm32f769xx.h:1341
ADC_Common_TypeDef
Definition: stm32f745xx.h:228
DMA1_Stream3_IRQn
Definition: stm32f769xx.h:93
RTC_WKUP_IRQn
Definition: stm32f769xx.h:82
DSI_TypeDef::GHCR
__IO uint32_t GHCR
Definition: stm32f769xx.h:1339
DSI_TypeDef::VCCCR
__IO uint32_t VCCCR
Definition: stm32f769xx.h:1367
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f745xx.h:673
DSI_TypeDef::PCR
__IO uint32_t PCR
Definition: stm32f769xx.h:1323
WWDG_IRQn
Definition: stm32f769xx.h:79
CAN2_RX0_IRQn
Definition: stm32f769xx.h:143
TIM8_BRK_TIM12_IRQn
Definition: stm32f769xx.h:122
DMA2D_IRQn
Definition: stm32f769xx.h:168
I2C3_ER_IRQn
Definition: stm32f769xx.h:152
DSI_TypeDef::LCVCIDR
__IO uint32_t LCVCIDR
Definition: stm32f769xx.h:1360
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition: stm32f745xx.h:265
DSI_TypeDef::VMCR
__IO uint32_t VMCR
Definition: stm32f769xx.h:1326
DSI_TypeDef::WISR
__IO uint32_t WISR
Definition: stm32f769xx.h:1382
CAN1_TX_IRQn
Definition: stm32f769xx.h:98
DebugMonitor_IRQn
Definition: stm32f769xx.h:75
FMC_Bank1_TypeDef
Flexible Memory Controller.
Definition: stm32f745xx.h:550
DMA1_Stream4_IRQn
Definition: stm32f769xx.h:94
TIM6_DAC_IRQn
Definition: stm32f769xx.h:133
DSI_TypeDef::VHBPCR
__IO uint32_t VHBPCR
Definition: stm32f769xx.h:1331
SPDIF_RX_IRQn
Definition: stm32f769xx.h:175
DSI_TypeDef::VVSACCR
__IO uint32_t VVSACCR
Definition: stm32f769xx.h:1372
RTC_TypeDef
Real-Time Clock.
Definition: stm32f745xx.h:715
ETH_WKUP_IRQn
Definition: stm32f769xx.h:141
DCMI_TypeDef
DCMI.
Definition: stm32f745xx.h:371
I2C1_ER_IRQn
Definition: stm32f769xx.h:111
FMC_Bank5_6_TypeDef
Flexible Memory Controller Bank5_6.
Definition: stm32f745xx.h:582
OTG_HS_IRQn
Definition: stm32f769xx.h:156
TIM1_CC_IRQn
Definition: stm32f769xx.h:106
DSI_TypeDef::VMCCR
__IO uint32_t VMCCR
Definition: stm32f769xx.h:1365
RNG_IRQn
Definition: stm32f769xx.h:158
DSI_TypeDef::CR
__IO uint32_t CR
Definition: stm32f769xx.h:1316
FLASH_IRQn
Definition: stm32f769xx.h:83
DMA2_Stream3_IRQn
Definition: stm32f769xx.h:138
DSI_TypeDef::TDCR
__IO uint32_t TDCR
Definition: stm32f769xx.h:1343
JPEG_IRQn
Definition: stm32f769xx.h:186
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f745xx.h:626
TIM8_UP_TIM13_IRQn
Definition: stm32f769xx.h:123
DSI_TypeDef::RESERVED5
uint32_t RESERVED5
Definition: stm32f769xx.h:1362
DSI_TypeDef::VLCR
__IO uint32_t VLCR
Definition: stm32f769xx.h:1332
DSI_TypeDef::WCFGR
__IO uint32_t WCFGR
Definition: stm32f769xx.h:1379
DSI_TypeDef::DLTCR
__IO uint32_t DLTCR
Definition: stm32f769xx.h:1346
DSI_TypeDef::TDCCR
__IO uint32_t TDCCR
Definition: stm32f769xx.h:1377
DSI_TypeDef::VPCR
__IO uint32_t VPCR
Definition: stm32f769xx.h:1327
RNG_TypeDef
RNG.
Definition: stm32f745xx.h:960
SPI6_IRQn
Definition: stm32f769xx.h:164
TIM1_BRK_TIM9_IRQn
Definition: stm32f769xx.h:103
TIM1_UP_TIM10_IRQn
Definition: stm32f769xx.h:104
DSI_TypeDef::VVSACR
__IO uint32_t VVSACR
Definition: stm32f769xx.h:1333
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f745xx.h:359
DSI_TypeDef::VNPCR
__IO uint32_t VNPCR
Definition: stm32f769xx.h:1329
SPI1_IRQn
Definition: stm32f769xx.h:114
TIM3_IRQn
Definition: stm32f769xx.h:108
NonMaskableInt_IRQn
Definition: stm32f769xx.h:70
SDMMC_TypeDef
SD host Interface.
Definition: stm32f745xx.h:813
TIM8_CC_IRQn
Definition: stm32f769xx.h:125
SAI_Block_TypeDef
Definition: stm32f745xx.h:781
DSI_TypeDef::RESERVED9
uint32_t RESERVED9
Definition: stm32f769xx.h:1384
EXTI0_IRQn
Definition: stm32f769xx.h:85
DSI_TypeDef::VHSACCR
__IO uint32_t VHSACCR
Definition: stm32f769xx.h:1369
LTDC_IRQn
Definition: stm32f769xx.h:166
DSI_TypeDef::VVACR
__IO uint32_t VVACR
Definition: stm32f769xx.h:1336
DSI_TypeDef::WIER
__IO uint32_t WIER
Definition: stm32f769xx.h:1381
EXTI2_IRQn
Definition: stm32f769xx.h:87
USB_OTG_OUTEndpointTypeDef
USB_OTG_OUT_Endpoint-Specific_Registers.
Definition: stm32f745xx.h:1051
LTDC_ER_IRQn
Definition: stm32f769xx.h:167
USART3_IRQn
Definition: stm32f769xx.h:118
DFSDM1_FLT3_IRQn
Definition: stm32f769xx.h:180
DSI_TypeDef::WRPCR
__IO uint32_t WRPCR
Definition: stm32f769xx.h:1387
MDIOS_TypeDef
MDIOS.
Definition: stm32f765xx.h:1146
USART2_IRQn
Definition: stm32f769xx.h:117
DSI_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32f769xx.h:1317
DSI_TypeDef::VSCR
__IO uint32_t VSCR
Definition: stm32f769xx.h:1358
UART8_IRQn
Definition: stm32f769xx.h:161
DSI_TypeDef::VPCCR
__IO uint32_t VPCCR
Definition: stm32f769xx.h:1366
CAN3_SCE_IRQn
Definition: stm32f769xx.h:185
OTG_FS_IRQn
Definition: stm32f769xx.h:146
UsageFault_IRQn
Definition: stm32f769xx.h:73
MemoryManagement_IRQn
Definition: stm32f769xx.h:71
USB_OTG_DeviceTypeDef
USB_OTG_device_Registers.
Definition: stm32f745xx.h:1007
TIM5_IRQn
Definition: stm32f769xx.h:129
CAN3_TX_IRQn
Definition: stm32f769xx.h:182
DSI_TypeDef::LPCR
__IO uint32_t LPCR
Definition: stm32f769xx.h:1320
DSI_TypeDef
DSI Controller.
Definition: stm32f769xx.h:1313
USART6_IRQn
Definition: stm32f769xx.h:150
CAN1_RX0_IRQn
Definition: stm32f769xx.h:99
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