STM32F769IDiscovery  1.00
uDANTE Audio Networking with STM32F7 DISCO board
Macros
Peripheral_memory_map
CMSIS_Device

Macros

#define RAMITCM_BASE   0x00000000U
 
#define FLASHITCM_BASE   0x00200000U
 
#define FLASHAXI_BASE   0x08000000U
 
#define RAMDTCM_BASE   0x20000000U
 
#define PERIPH_BASE   0x40000000U
 
#define BKPSRAM_BASE   0x40024000U
 
#define QSPI_BASE   0x90000000U
 
#define FMC_R_BASE   0xA0000000U
 
#define QSPI_R_BASE   0xA0001000U
 
#define SRAM1_BASE   0x20010000U
 
#define SRAM2_BASE   0x2004C000U
 
#define FLASH_END   0x080FFFFFU
 
#define FLASH_BASE   FLASHAXI_BASE
 
#define APB1PERIPH_BASE   PERIPH_BASE
 
#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000U)
 
#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000U)
 
#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000U)
 
#define TIM2_BASE   (APB1PERIPH_BASE + 0x0000U)
 
#define TIM3_BASE   (APB1PERIPH_BASE + 0x0400U)
 
#define TIM4_BASE   (APB1PERIPH_BASE + 0x0800U)
 
#define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00U)
 
#define TIM6_BASE   (APB1PERIPH_BASE + 0x1000U)
 
#define TIM7_BASE   (APB1PERIPH_BASE + 0x1400U)
 
#define TIM12_BASE   (APB1PERIPH_BASE + 0x1800U)
 
#define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00U)
 
#define TIM14_BASE   (APB1PERIPH_BASE + 0x2000U)
 
#define LPTIM1_BASE   (APB1PERIPH_BASE + 0x2400U)
 
#define RTC_BASE   (APB1PERIPH_BASE + 0x2800U)
 
#define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00U)
 
#define IWDG_BASE   (APB1PERIPH_BASE + 0x3000U)
 
#define SPI2_BASE   (APB1PERIPH_BASE + 0x3800U)
 
#define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00U)
 
#define SPDIFRX_BASE   (APB1PERIPH_BASE + 0x4000U)
 
#define USART2_BASE   (APB1PERIPH_BASE + 0x4400U)
 
#define USART3_BASE   (APB1PERIPH_BASE + 0x4800U)
 
#define UART4_BASE   (APB1PERIPH_BASE + 0x4C00U)
 
#define UART5_BASE   (APB1PERIPH_BASE + 0x5000U)
 
#define I2C1_BASE   (APB1PERIPH_BASE + 0x5400U)
 
#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800U)
 
#define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00U)
 
#define I2C4_BASE   (APB1PERIPH_BASE + 0x6000U)
 
#define CAN1_BASE   (APB1PERIPH_BASE + 0x6400U)
 
#define CAN2_BASE   (APB1PERIPH_BASE + 0x6800U)
 
#define CEC_BASE   (APB1PERIPH_BASE + 0x6C00U)
 
#define PWR_BASE   (APB1PERIPH_BASE + 0x7000U)
 
#define DAC_BASE   (APB1PERIPH_BASE + 0x7400U)
 
#define UART7_BASE   (APB1PERIPH_BASE + 0x7800U)
 
#define UART8_BASE   (APB1PERIPH_BASE + 0x7C00U)
 
#define TIM1_BASE   (APB2PERIPH_BASE + 0x0000U)
 
#define TIM8_BASE   (APB2PERIPH_BASE + 0x0400U)
 
#define USART1_BASE   (APB2PERIPH_BASE + 0x1000U)
 
#define USART6_BASE   (APB2PERIPH_BASE + 0x1400U)
 
#define ADC1_BASE   (APB2PERIPH_BASE + 0x2000U)
 
#define ADC2_BASE   (APB2PERIPH_BASE + 0x2100U)
 
#define ADC3_BASE   (APB2PERIPH_BASE + 0x2200U)
 
#define ADC_BASE   (APB2PERIPH_BASE + 0x2300U)
 
#define SDMMC1_BASE   (APB2PERIPH_BASE + 0x2C00U)
 
#define SPI1_BASE   (APB2PERIPH_BASE + 0x3000U)
 
#define SPI4_BASE   (APB2PERIPH_BASE + 0x3400U)
 
#define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800U)
 
#define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00U)
 
#define TIM9_BASE   (APB2PERIPH_BASE + 0x4000U)
 
#define TIM10_BASE   (APB2PERIPH_BASE + 0x4400U)
 
#define TIM11_BASE   (APB2PERIPH_BASE + 0x4800U)
 
#define SPI5_BASE   (APB2PERIPH_BASE + 0x5000U)
 
#define SPI6_BASE   (APB2PERIPH_BASE + 0x5400U)
 
#define SAI1_BASE   (APB2PERIPH_BASE + 0x5800U)
 
#define SAI2_BASE   (APB2PERIPH_BASE + 0x5C00U)
 
#define SAI1_Block_A_BASE   (SAI1_BASE + 0x004U)
 
#define SAI1_Block_B_BASE   (SAI1_BASE + 0x024U)
 
#define SAI2_Block_A_BASE   (SAI2_BASE + 0x004U)
 
#define SAI2_Block_B_BASE   (SAI2_BASE + 0x024U)
 
#define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000U)
 
#define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400U)
 
#define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800U)
 
#define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00U)
 
#define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000U)
 
#define GPIOF_BASE   (AHB1PERIPH_BASE + 0x1400U)
 
#define GPIOG_BASE   (AHB1PERIPH_BASE + 0x1800U)
 
#define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00U)
 
#define GPIOI_BASE   (AHB1PERIPH_BASE + 0x2000U)
 
#define GPIOJ_BASE   (AHB1PERIPH_BASE + 0x2400U)
 
#define GPIOK_BASE   (AHB1PERIPH_BASE + 0x2800U)
 
#define CRC_BASE   (AHB1PERIPH_BASE + 0x3000U)
 
#define RCC_BASE   (AHB1PERIPH_BASE + 0x3800U)
 
#define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00U)
 
#define UID_BASE   0x1FF0F420U
 
#define FLASHSIZE_BASE   0x1FF0F442U
 
#define PACKAGESIZE_BASE   0x1FFF7BF0U
 
#define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000U)
 
#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010U)
 
#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028U)
 
#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040U)
 
#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058U)
 
#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070U)
 
#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088U)
 
#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0U)
 
#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8U)
 
#define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400U)
 
#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010U)
 
#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028U)
 
#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040U)
 
#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058U)
 
#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070U)
 
#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088U)
 
#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0U)
 
#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8U)
 
#define ETH_BASE   (AHB1PERIPH_BASE + 0x8000U)
 
#define ETH_MAC_BASE   (ETH_BASE)
 
#define ETH_MMC_BASE   (ETH_BASE + 0x0100U)
 
#define ETH_PTP_BASE   (ETH_BASE + 0x0700U)
 
#define ETH_DMA_BASE   (ETH_BASE + 0x1000U)
 
#define DMA2D_BASE   (AHB1PERIPH_BASE + 0xB000U)
 
#define DCMI_BASE   (AHB2PERIPH_BASE + 0x50000U)
 
#define RNG_BASE   (AHB2PERIPH_BASE + 0x60800U)
 
#define FMC_Bank1_R_BASE   (FMC_R_BASE + 0x0000U)
 
#define FMC_Bank1E_R_BASE   (FMC_R_BASE + 0x0104U)
 
#define FMC_Bank3_R_BASE   (FMC_R_BASE + 0x0080U)
 
#define FMC_Bank5_6_R_BASE   (FMC_R_BASE + 0x0140U)
 
#define DBGMCU_BASE   0xE0042000U
 
#define USB_OTG_HS_PERIPH_BASE   0x40040000U
 
#define USB_OTG_FS_PERIPH_BASE   0x50000000U
 
#define USB_OTG_GLOBAL_BASE   0x000U
 
#define USB_OTG_DEVICE_BASE   0x800U
 
#define USB_OTG_IN_ENDPOINT_BASE   0x900U
 
#define USB_OTG_OUT_ENDPOINT_BASE   0xB00U
 
#define USB_OTG_EP_REG_SIZE   0x20U
 
#define USB_OTG_HOST_BASE   0x400U
 
#define USB_OTG_HOST_PORT_BASE   0x440U
 
#define USB_OTG_HOST_CHANNEL_BASE   0x500U
 
#define USB_OTG_HOST_CHANNEL_SIZE   0x20U
 
#define USB_OTG_PCGCCTL_BASE   0xE00U
 
#define USB_OTG_FIFO_BASE   0x1000U
 
#define USB_OTG_FIFO_SIZE   0x1000U
 
#define RAMITCM_BASE   0x00000000U
 
#define FLASHITCM_BASE   0x00200000U
 
#define FLASHAXI_BASE   0x08000000U
 
#define RAMDTCM_BASE   0x20000000U
 
#define PERIPH_BASE   0x40000000U
 
#define BKPSRAM_BASE   0x40024000U
 
#define QSPI_BASE   0x90000000U
 
#define FMC_R_BASE   0xA0000000U
 
#define QSPI_R_BASE   0xA0001000U
 
#define SRAM1_BASE   0x20010000U
 
#define SRAM2_BASE   0x2004C000U
 
#define FLASH_END   0x080FFFFFU
 
#define FLASH_BASE   FLASHAXI_BASE
 
#define APB1PERIPH_BASE   PERIPH_BASE
 
#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000U)
 
#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000U)
 
#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000U)
 
#define TIM2_BASE   (APB1PERIPH_BASE + 0x0000U)
 
#define TIM3_BASE   (APB1PERIPH_BASE + 0x0400U)
 
#define TIM4_BASE   (APB1PERIPH_BASE + 0x0800U)
 
#define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00U)
 
#define TIM6_BASE   (APB1PERIPH_BASE + 0x1000U)
 
#define TIM7_BASE   (APB1PERIPH_BASE + 0x1400U)
 
#define TIM12_BASE   (APB1PERIPH_BASE + 0x1800U)
 
#define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00U)
 
#define TIM14_BASE   (APB1PERIPH_BASE + 0x2000U)
 
#define LPTIM1_BASE   (APB1PERIPH_BASE + 0x2400U)
 
#define RTC_BASE   (APB1PERIPH_BASE + 0x2800U)
 
#define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00U)
 
#define IWDG_BASE   (APB1PERIPH_BASE + 0x3000U)
 
#define SPI2_BASE   (APB1PERIPH_BASE + 0x3800U)
 
#define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00U)
 
#define SPDIFRX_BASE   (APB1PERIPH_BASE + 0x4000U)
 
#define USART2_BASE   (APB1PERIPH_BASE + 0x4400U)
 
#define USART3_BASE   (APB1PERIPH_BASE + 0x4800U)
 
#define UART4_BASE   (APB1PERIPH_BASE + 0x4C00U)
 
#define UART5_BASE   (APB1PERIPH_BASE + 0x5000U)
 
#define I2C1_BASE   (APB1PERIPH_BASE + 0x5400U)
 
#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800U)
 
#define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00U)
 
#define I2C4_BASE   (APB1PERIPH_BASE + 0x6000U)
 
#define CAN1_BASE   (APB1PERIPH_BASE + 0x6400U)
 
#define CAN2_BASE   (APB1PERIPH_BASE + 0x6800U)
 
#define CEC_BASE   (APB1PERIPH_BASE + 0x6C00U)
 
#define PWR_BASE   (APB1PERIPH_BASE + 0x7000U)
 
#define DAC_BASE   (APB1PERIPH_BASE + 0x7400U)
 
#define UART7_BASE   (APB1PERIPH_BASE + 0x7800U)
 
#define UART8_BASE   (APB1PERIPH_BASE + 0x7C00U)
 
#define TIM1_BASE   (APB2PERIPH_BASE + 0x0000U)
 
#define TIM8_BASE   (APB2PERIPH_BASE + 0x0400U)
 
#define USART1_BASE   (APB2PERIPH_BASE + 0x1000U)
 
#define USART6_BASE   (APB2PERIPH_BASE + 0x1400U)
 
#define ADC1_BASE   (APB2PERIPH_BASE + 0x2000U)
 
#define ADC2_BASE   (APB2PERIPH_BASE + 0x2100U)
 
#define ADC3_BASE   (APB2PERIPH_BASE + 0x2200U)
 
#define ADC_BASE   (APB2PERIPH_BASE + 0x2300U)
 
#define SDMMC1_BASE   (APB2PERIPH_BASE + 0x2C00U)
 
#define SPI1_BASE   (APB2PERIPH_BASE + 0x3000U)
 
#define SPI4_BASE   (APB2PERIPH_BASE + 0x3400U)
 
#define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800U)
 
#define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00U)
 
#define TIM9_BASE   (APB2PERIPH_BASE + 0x4000U)
 
#define TIM10_BASE   (APB2PERIPH_BASE + 0x4400U)
 
#define TIM11_BASE   (APB2PERIPH_BASE + 0x4800U)
 
#define SPI5_BASE   (APB2PERIPH_BASE + 0x5000U)
 
#define SPI6_BASE   (APB2PERIPH_BASE + 0x5400U)
 
#define SAI1_BASE   (APB2PERIPH_BASE + 0x5800U)
 
#define SAI2_BASE   (APB2PERIPH_BASE + 0x5C00U)
 
#define SAI1_Block_A_BASE   (SAI1_BASE + 0x004U)
 
#define SAI1_Block_B_BASE   (SAI1_BASE + 0x024U)
 
#define SAI2_Block_A_BASE   (SAI2_BASE + 0x004U)
 
#define SAI2_Block_B_BASE   (SAI2_BASE + 0x024U)
 
#define LTDC_BASE   (APB2PERIPH_BASE + 0x6800U)
 
#define LTDC_Layer1_BASE   (LTDC_BASE + 0x84U)
 
#define LTDC_Layer2_BASE   (LTDC_BASE + 0x104U)
 
#define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000U)
 
#define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400U)
 
#define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800U)
 
#define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00U)
 
#define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000U)
 
#define GPIOF_BASE   (AHB1PERIPH_BASE + 0x1400U)
 
#define GPIOG_BASE   (AHB1PERIPH_BASE + 0x1800U)
 
#define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00U)
 
#define GPIOI_BASE   (AHB1PERIPH_BASE + 0x2000U)
 
#define GPIOJ_BASE   (AHB1PERIPH_BASE + 0x2400U)
 
#define GPIOK_BASE   (AHB1PERIPH_BASE + 0x2800U)
 
#define CRC_BASE   (AHB1PERIPH_BASE + 0x3000U)
 
#define RCC_BASE   (AHB1PERIPH_BASE + 0x3800U)
 
#define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00U)
 
#define UID_BASE   0x1FF0F420U
 
#define FLASHSIZE_BASE   0x1FF0F442U
 
#define PACKAGESIZE_BASE   0x1FFF7BF0U
 
#define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000U)
 
#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010U)
 
#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028U)
 
#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040U)
 
#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058U)
 
#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070U)
 
#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088U)
 
#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0U)
 
#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8U)
 
#define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400U)
 
#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010U)
 
#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028U)
 
#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040U)
 
#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058U)
 
#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070U)
 
#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088U)
 
#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0U)
 
#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8U)
 
#define ETH_BASE   (AHB1PERIPH_BASE + 0x8000U)
 
#define ETH_MAC_BASE   (ETH_BASE)
 
#define ETH_MMC_BASE   (ETH_BASE + 0x0100U)
 
#define ETH_PTP_BASE   (ETH_BASE + 0x0700U)
 
#define ETH_DMA_BASE   (ETH_BASE + 0x1000U)
 
#define DMA2D_BASE   (AHB1PERIPH_BASE + 0xB000U)
 
#define DCMI_BASE   (AHB2PERIPH_BASE + 0x50000U)
 
#define RNG_BASE   (AHB2PERIPH_BASE + 0x60800U)
 
#define FMC_Bank1_R_BASE   (FMC_R_BASE + 0x0000U)
 
#define FMC_Bank1E_R_BASE   (FMC_R_BASE + 0x0104U)
 
#define FMC_Bank3_R_BASE   (FMC_R_BASE + 0x0080U)
 
#define FMC_Bank5_6_R_BASE   (FMC_R_BASE + 0x0140U)
 
#define DBGMCU_BASE   0xE0042000U
 
#define USB_OTG_HS_PERIPH_BASE   0x40040000U
 
#define USB_OTG_FS_PERIPH_BASE   0x50000000U
 
#define USB_OTG_GLOBAL_BASE   0x000U
 
#define USB_OTG_DEVICE_BASE   0x800U
 
#define USB_OTG_IN_ENDPOINT_BASE   0x900U
 
#define USB_OTG_OUT_ENDPOINT_BASE   0xB00U
 
#define USB_OTG_EP_REG_SIZE   0x20U
 
#define USB_OTG_HOST_BASE   0x400U
 
#define USB_OTG_HOST_PORT_BASE   0x440U
 
#define USB_OTG_HOST_CHANNEL_BASE   0x500U
 
#define USB_OTG_HOST_CHANNEL_SIZE   0x20U
 
#define USB_OTG_PCGCCTL_BASE   0xE00U
 
#define USB_OTG_FIFO_BASE   0x1000U
 
#define USB_OTG_FIFO_SIZE   0x1000U
 
#define RAMITCM_BASE   0x00000000U
 
#define FLASHITCM_BASE   0x00200000U
 
#define FLASHAXI_BASE   0x08000000U
 
#define RAMDTCM_BASE   0x20000000U
 
#define PERIPH_BASE   0x40000000U
 
#define BKPSRAM_BASE   0x40024000U
 
#define QSPI_BASE   0x90000000U
 
#define FMC_R_BASE   0xA0000000U
 
#define QSPI_R_BASE   0xA0001000U
 
#define SRAM1_BASE   0x20010000U
 
#define SRAM2_BASE   0x2004C000U
 
#define FLASH_END   0x080FFFFFU
 
#define FLASH_BASE   FLASHAXI_BASE
 
#define APB1PERIPH_BASE   PERIPH_BASE
 
#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000U)
 
#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000U)
 
#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000U)
 
#define TIM2_BASE   (APB1PERIPH_BASE + 0x0000U)
 
#define TIM3_BASE   (APB1PERIPH_BASE + 0x0400U)
 
#define TIM4_BASE   (APB1PERIPH_BASE + 0x0800U)
 
#define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00U)
 
#define TIM6_BASE   (APB1PERIPH_BASE + 0x1000U)
 
#define TIM7_BASE   (APB1PERIPH_BASE + 0x1400U)
 
#define TIM12_BASE   (APB1PERIPH_BASE + 0x1800U)
 
#define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00U)
 
#define TIM14_BASE   (APB1PERIPH_BASE + 0x2000U)
 
#define LPTIM1_BASE   (APB1PERIPH_BASE + 0x2400U)
 
#define RTC_BASE   (APB1PERIPH_BASE + 0x2800U)
 
#define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00U)
 
#define IWDG_BASE   (APB1PERIPH_BASE + 0x3000U)
 
#define SPI2_BASE   (APB1PERIPH_BASE + 0x3800U)
 
#define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00U)
 
#define SPDIFRX_BASE   (APB1PERIPH_BASE + 0x4000U)
 
#define USART2_BASE   (APB1PERIPH_BASE + 0x4400U)
 
#define USART3_BASE   (APB1PERIPH_BASE + 0x4800U)
 
#define UART4_BASE   (APB1PERIPH_BASE + 0x4C00U)
 
#define UART5_BASE   (APB1PERIPH_BASE + 0x5000U)
 
#define I2C1_BASE   (APB1PERIPH_BASE + 0x5400U)
 
#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800U)
 
#define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00U)
 
#define I2C4_BASE   (APB1PERIPH_BASE + 0x6000U)
 
#define CAN1_BASE   (APB1PERIPH_BASE + 0x6400U)
 
#define CAN2_BASE   (APB1PERIPH_BASE + 0x6800U)
 
#define CEC_BASE   (APB1PERIPH_BASE + 0x6C00U)
 
#define PWR_BASE   (APB1PERIPH_BASE + 0x7000U)
 
#define DAC_BASE   (APB1PERIPH_BASE + 0x7400U)
 
#define UART7_BASE   (APB1PERIPH_BASE + 0x7800U)
 
#define UART8_BASE   (APB1PERIPH_BASE + 0x7C00U)
 
#define TIM1_BASE   (APB2PERIPH_BASE + 0x0000U)
 
#define TIM8_BASE   (APB2PERIPH_BASE + 0x0400U)
 
#define USART1_BASE   (APB2PERIPH_BASE + 0x1000U)
 
#define USART6_BASE   (APB2PERIPH_BASE + 0x1400U)
 
#define ADC1_BASE   (APB2PERIPH_BASE + 0x2000U)
 
#define ADC2_BASE   (APB2PERIPH_BASE + 0x2100U)
 
#define ADC3_BASE   (APB2PERIPH_BASE + 0x2200U)
 
#define ADC_BASE   (APB2PERIPH_BASE + 0x2300U)
 
#define SDMMC1_BASE   (APB2PERIPH_BASE + 0x2C00U)
 
#define SPI1_BASE   (APB2PERIPH_BASE + 0x3000U)
 
#define SPI4_BASE   (APB2PERIPH_BASE + 0x3400U)
 
#define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800U)
 
#define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00U)
 
#define TIM9_BASE   (APB2PERIPH_BASE + 0x4000U)
 
#define TIM10_BASE   (APB2PERIPH_BASE + 0x4400U)
 
#define TIM11_BASE   (APB2PERIPH_BASE + 0x4800U)
 
#define SPI5_BASE   (APB2PERIPH_BASE + 0x5000U)
 
#define SPI6_BASE   (APB2PERIPH_BASE + 0x5400U)
 
#define SAI1_BASE   (APB2PERIPH_BASE + 0x5800U)
 
#define SAI2_BASE   (APB2PERIPH_BASE + 0x5C00U)
 
#define SAI1_Block_A_BASE   (SAI1_BASE + 0x004U)
 
#define SAI1_Block_B_BASE   (SAI1_BASE + 0x024U)
 
#define SAI2_Block_A_BASE   (SAI2_BASE + 0x004U)
 
#define SAI2_Block_B_BASE   (SAI2_BASE + 0x024U)
 
#define LTDC_BASE   (APB2PERIPH_BASE + 0x6800U)
 
#define LTDC_Layer1_BASE   (LTDC_BASE + 0x84U)
 
#define LTDC_Layer2_BASE   (LTDC_BASE + 0x104U)
 
#define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000U)
 
#define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400U)
 
#define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800U)
 
#define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00U)
 
#define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000U)
 
#define GPIOF_BASE   (AHB1PERIPH_BASE + 0x1400U)
 
#define GPIOG_BASE   (AHB1PERIPH_BASE + 0x1800U)
 
#define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00U)
 
#define GPIOI_BASE   (AHB1PERIPH_BASE + 0x2000U)
 
#define GPIOJ_BASE   (AHB1PERIPH_BASE + 0x2400U)
 
#define GPIOK_BASE   (AHB1PERIPH_BASE + 0x2800U)
 
#define CRC_BASE   (AHB1PERIPH_BASE + 0x3000U)
 
#define RCC_BASE   (AHB1PERIPH_BASE + 0x3800U)
 
#define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00U)
 
#define UID_BASE   0x1FF0F420U
 
#define FLASHSIZE_BASE   0x1FF0F442U
 
#define PACKAGESIZE_BASE   0x1FFF7BF0U
 
#define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000U)
 
#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010U)
 
#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028U)
 
#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040U)
 
#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058U)
 
#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070U)
 
#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088U)
 
#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0U)
 
#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8U)
 
#define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400U)
 
#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010U)
 
#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028U)
 
#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040U)
 
#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058U)
 
#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070U)
 
#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088U)
 
#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0U)
 
#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8U)
 
#define ETH_BASE   (AHB1PERIPH_BASE + 0x8000U)
 
#define ETH_MAC_BASE   (ETH_BASE)
 
#define ETH_MMC_BASE   (ETH_BASE + 0x0100U)
 
#define ETH_PTP_BASE   (ETH_BASE + 0x0700U)
 
#define ETH_DMA_BASE   (ETH_BASE + 0x1000U)
 
#define DMA2D_BASE   (AHB1PERIPH_BASE + 0xB000U)
 
#define DCMI_BASE   (AHB2PERIPH_BASE + 0x50000U)
 
#define CRYP_BASE   (AHB2PERIPH_BASE + 0x60000U)
 
#define HASH_BASE   (AHB2PERIPH_BASE + 0x60400U)
 
#define HASH_DIGEST_BASE   (AHB2PERIPH_BASE + 0x60710U)
 
#define RNG_BASE   (AHB2PERIPH_BASE + 0x60800U)
 
#define FMC_Bank1_R_BASE   (FMC_R_BASE + 0x0000U)
 
#define FMC_Bank1E_R_BASE   (FMC_R_BASE + 0x0104U)
 
#define FMC_Bank3_R_BASE   (FMC_R_BASE + 0x0080U)
 
#define FMC_Bank5_6_R_BASE   (FMC_R_BASE + 0x0140U)
 
#define DBGMCU_BASE   0xE0042000U
 
#define USB_OTG_HS_PERIPH_BASE   0x40040000U
 
#define USB_OTG_FS_PERIPH_BASE   0x50000000U
 
#define USB_OTG_GLOBAL_BASE   0x000U
 
#define USB_OTG_DEVICE_BASE   0x800U
 
#define USB_OTG_IN_ENDPOINT_BASE   0x900U
 
#define USB_OTG_OUT_ENDPOINT_BASE   0xB00U
 
#define USB_OTG_EP_REG_SIZE   0x20U
 
#define USB_OTG_HOST_BASE   0x400U
 
#define USB_OTG_HOST_PORT_BASE   0x440U
 
#define USB_OTG_HOST_CHANNEL_BASE   0x500U
 
#define USB_OTG_HOST_CHANNEL_SIZE   0x20U
 
#define USB_OTG_PCGCCTL_BASE   0xE00U
 
#define USB_OTG_FIFO_BASE   0x1000U
 
#define USB_OTG_FIFO_SIZE   0x1000U
 
#define RAMITCM_BASE   0x00000000U
 
#define FLASHITCM_BASE   0x00200000U
 
#define FLASHAXI_BASE   0x08000000U
 
#define RAMDTCM_BASE   0x20000000U
 
#define PERIPH_BASE   0x40000000U
 
#define BKPSRAM_BASE   0x40024000U
 
#define QSPI_BASE   0x90000000U
 
#define FMC_R_BASE   0xA0000000U
 
#define QSPI_R_BASE   0xA0001000U
 
#define SRAM1_BASE   0x20020000U
 
#define SRAM2_BASE   0x2007C000U
 
#define FLASH_END   0x081FFFFFU
 
#define FLASH_BASE   FLASHAXI_BASE
 
#define APB1PERIPH_BASE   PERIPH_BASE
 
#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000U)
 
#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000U)
 
#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000U)
 
#define TIM2_BASE   (APB1PERIPH_BASE + 0x0000U)
 
#define TIM3_BASE   (APB1PERIPH_BASE + 0x0400U)
 
#define TIM4_BASE   (APB1PERIPH_BASE + 0x0800U)
 
#define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00U)
 
#define TIM6_BASE   (APB1PERIPH_BASE + 0x1000U)
 
#define TIM7_BASE   (APB1PERIPH_BASE + 0x1400U)
 
#define TIM12_BASE   (APB1PERIPH_BASE + 0x1800U)
 
#define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00U)
 
#define TIM14_BASE   (APB1PERIPH_BASE + 0x2000U)
 
#define LPTIM1_BASE   (APB1PERIPH_BASE + 0x2400U)
 
#define RTC_BASE   (APB1PERIPH_BASE + 0x2800U)
 
#define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00U)
 
#define IWDG_BASE   (APB1PERIPH_BASE + 0x3000U)
 
#define CAN3_BASE   (APB1PERIPH_BASE + 0x3400U)
 
#define SPI2_BASE   (APB1PERIPH_BASE + 0x3800U)
 
#define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00U)
 
#define SPDIFRX_BASE   (APB1PERIPH_BASE + 0x4000U)
 
#define USART2_BASE   (APB1PERIPH_BASE + 0x4400U)
 
#define USART3_BASE   (APB1PERIPH_BASE + 0x4800U)
 
#define UART4_BASE   (APB1PERIPH_BASE + 0x4C00U)
 
#define UART5_BASE   (APB1PERIPH_BASE + 0x5000U)
 
#define I2C1_BASE   (APB1PERIPH_BASE + 0x5400U)
 
#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800U)
 
#define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00U)
 
#define I2C4_BASE   (APB1PERIPH_BASE + 0x6000U)
 
#define CAN1_BASE   (APB1PERIPH_BASE + 0x6400U)
 
#define CAN2_BASE   (APB1PERIPH_BASE + 0x6800U)
 
#define CEC_BASE   (APB1PERIPH_BASE + 0x6C00U)
 
#define PWR_BASE   (APB1PERIPH_BASE + 0x7000U)
 
#define DAC_BASE   (APB1PERIPH_BASE + 0x7400U)
 
#define UART7_BASE   (APB1PERIPH_BASE + 0x7800U)
 
#define UART8_BASE   (APB1PERIPH_BASE + 0x7C00U)
 
#define TIM1_BASE   (APB2PERIPH_BASE + 0x0000U)
 
#define TIM8_BASE   (APB2PERIPH_BASE + 0x0400U)
 
#define USART1_BASE   (APB2PERIPH_BASE + 0x1000U)
 
#define USART6_BASE   (APB2PERIPH_BASE + 0x1400U)
 
#define SDMMC2_BASE   (APB2PERIPH_BASE + 0x1C00U)
 
#define ADC1_BASE   (APB2PERIPH_BASE + 0x2000U)
 
#define ADC2_BASE   (APB2PERIPH_BASE + 0x2100U)
 
#define ADC3_BASE   (APB2PERIPH_BASE + 0x2200U)
 
#define ADC_BASE   (APB2PERIPH_BASE + 0x2300U)
 
#define SDMMC1_BASE   (APB2PERIPH_BASE + 0x2C00U)
 
#define SPI1_BASE   (APB2PERIPH_BASE + 0x3000U)
 
#define SPI4_BASE   (APB2PERIPH_BASE + 0x3400U)
 
#define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800U)
 
#define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00U)
 
#define TIM9_BASE   (APB2PERIPH_BASE + 0x4000U)
 
#define TIM10_BASE   (APB2PERIPH_BASE + 0x4400U)
 
#define TIM11_BASE   (APB2PERIPH_BASE + 0x4800U)
 
#define SPI5_BASE   (APB2PERIPH_BASE + 0x5000U)
 
#define SPI6_BASE   (APB2PERIPH_BASE + 0x5400U)
 
#define SAI1_BASE   (APB2PERIPH_BASE + 0x5800U)
 
#define SAI2_BASE   (APB2PERIPH_BASE + 0x5C00U)
 
#define SAI1_Block_A_BASE   (SAI1_BASE + 0x004U)
 
#define SAI1_Block_B_BASE   (SAI1_BASE + 0x024U)
 
#define SAI2_Block_A_BASE   (SAI2_BASE + 0x004U)
 
#define SAI2_Block_B_BASE   (SAI2_BASE + 0x024U)
 
#define DFSDM1_BASE   (APB2PERIPH_BASE + 0x7400U)
 
#define DFSDM1_Channel0_BASE   (DFSDM1_BASE + 0x00U)
 
#define DFSDM1_Channel1_BASE   (DFSDM1_BASE + 0x20U)
 
#define DFSDM1_Channel2_BASE   (DFSDM1_BASE + 0x40U)
 
#define DFSDM1_Channel3_BASE   (DFSDM1_BASE + 0x60U)
 
#define DFSDM1_Channel4_BASE   (DFSDM1_BASE + 0x80U)
 
#define DFSDM1_Channel5_BASE   (DFSDM1_BASE + 0xA0U)
 
#define DFSDM1_Channel6_BASE   (DFSDM1_BASE + 0xC0U)
 
#define DFSDM1_Channel7_BASE   (DFSDM1_BASE + 0xE0U)
 
#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100U)
 
#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180U)
 
#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200U)
 
#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280U)
 
#define MDIOS_BASE   (APB2PERIPH_BASE + 0x7800U)
 
#define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000U)
 
#define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400U)
 
#define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800U)
 
#define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00U)
 
#define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000U)
 
#define GPIOF_BASE   (AHB1PERIPH_BASE + 0x1400U)
 
#define GPIOG_BASE   (AHB1PERIPH_BASE + 0x1800U)
 
#define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00U)
 
#define GPIOI_BASE   (AHB1PERIPH_BASE + 0x2000U)
 
#define GPIOJ_BASE   (AHB1PERIPH_BASE + 0x2400U)
 
#define GPIOK_BASE   (AHB1PERIPH_BASE + 0x2800U)
 
#define CRC_BASE   (AHB1PERIPH_BASE + 0x3000U)
 
#define RCC_BASE   (AHB1PERIPH_BASE + 0x3800U)
 
#define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00U)
 
#define UID_BASE   0x1FF0F420U
 
#define FLASHSIZE_BASE   0x1FF0F442U
 
#define PACKAGESIZE_BASE   0x1FFF7BF0U
 
#define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000U)
 
#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010U)
 
#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028U)
 
#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040U)
 
#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058U)
 
#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070U)
 
#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088U)
 
#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0U)
 
#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8U)
 
#define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400U)
 
#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010U)
 
#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028U)
 
#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040U)
 
#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058U)
 
#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070U)
 
#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088U)
 
#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0U)
 
#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8U)
 
#define ETH_BASE   (AHB1PERIPH_BASE + 0x8000U)
 
#define ETH_MAC_BASE   (ETH_BASE)
 
#define ETH_MMC_BASE   (ETH_BASE + 0x0100U)
 
#define ETH_PTP_BASE   (ETH_BASE + 0x0700U)
 
#define ETH_DMA_BASE   (ETH_BASE + 0x1000U)
 
#define DMA2D_BASE   (AHB1PERIPH_BASE + 0xB000U)
 
#define DCMI_BASE   (AHB2PERIPH_BASE + 0x50000U)
 
#define RNG_BASE   (AHB2PERIPH_BASE + 0x60800U)
 
#define FMC_Bank1_R_BASE   (FMC_R_BASE + 0x0000U)
 
#define FMC_Bank1E_R_BASE   (FMC_R_BASE + 0x0104U)
 
#define FMC_Bank3_R_BASE   (FMC_R_BASE + 0x0080U)
 
#define FMC_Bank5_6_R_BASE   (FMC_R_BASE + 0x0140U)
 
#define DBGMCU_BASE   0xE0042000U
 
#define USB_OTG_HS_PERIPH_BASE   0x40040000U
 
#define USB_OTG_FS_PERIPH_BASE   0x50000000U
 
#define USB_OTG_GLOBAL_BASE   0x000U
 
#define USB_OTG_DEVICE_BASE   0x800U
 
#define USB_OTG_IN_ENDPOINT_BASE   0x900U
 
#define USB_OTG_OUT_ENDPOINT_BASE   0xB00U
 
#define USB_OTG_EP_REG_SIZE   0x20U
 
#define USB_OTG_HOST_BASE   0x400U
 
#define USB_OTG_HOST_PORT_BASE   0x440U
 
#define USB_OTG_HOST_CHANNEL_BASE   0x500U
 
#define USB_OTG_HOST_CHANNEL_SIZE   0x20U
 
#define USB_OTG_PCGCCTL_BASE   0xE00U
 
#define USB_OTG_FIFO_BASE   0x1000U
 
#define USB_OTG_FIFO_SIZE   0x1000U
 
#define RAMITCM_BASE   0x00000000U
 
#define FLASHITCM_BASE   0x00200000U
 
#define FLASHAXI_BASE   0x08000000U
 
#define RAMDTCM_BASE   0x20000000U
 
#define PERIPH_BASE   0x40000000U
 
#define BKPSRAM_BASE   0x40024000U
 
#define QSPI_BASE   0x90000000U
 
#define FMC_R_BASE   0xA0000000U
 
#define QSPI_R_BASE   0xA0001000U
 
#define SRAM1_BASE   0x20020000U
 
#define SRAM2_BASE   0x2007C000U
 
#define FLASH_END   0x081FFFFFU
 
#define FLASH_BASE   FLASHAXI_BASE
 
#define APB1PERIPH_BASE   PERIPH_BASE
 
#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000U)
 
#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000U)
 
#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000U)
 
#define TIM2_BASE   (APB1PERIPH_BASE + 0x0000U)
 
#define TIM3_BASE   (APB1PERIPH_BASE + 0x0400U)
 
#define TIM4_BASE   (APB1PERIPH_BASE + 0x0800U)
 
#define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00U)
 
#define TIM6_BASE   (APB1PERIPH_BASE + 0x1000U)
 
#define TIM7_BASE   (APB1PERIPH_BASE + 0x1400U)
 
#define TIM12_BASE   (APB1PERIPH_BASE + 0x1800U)
 
#define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00U)
 
#define TIM14_BASE   (APB1PERIPH_BASE + 0x2000U)
 
#define LPTIM1_BASE   (APB1PERIPH_BASE + 0x2400U)
 
#define RTC_BASE   (APB1PERIPH_BASE + 0x2800U)
 
#define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00U)
 
#define IWDG_BASE   (APB1PERIPH_BASE + 0x3000U)
 
#define CAN3_BASE   (APB1PERIPH_BASE + 0x3400U)
 
#define SPI2_BASE   (APB1PERIPH_BASE + 0x3800U)
 
#define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00U)
 
#define SPDIFRX_BASE   (APB1PERIPH_BASE + 0x4000U)
 
#define USART2_BASE   (APB1PERIPH_BASE + 0x4400U)
 
#define USART3_BASE   (APB1PERIPH_BASE + 0x4800U)
 
#define UART4_BASE   (APB1PERIPH_BASE + 0x4C00U)
 
#define UART5_BASE   (APB1PERIPH_BASE + 0x5000U)
 
#define I2C1_BASE   (APB1PERIPH_BASE + 0x5400U)
 
#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800U)
 
#define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00U)
 
#define I2C4_BASE   (APB1PERIPH_BASE + 0x6000U)
 
#define CAN1_BASE   (APB1PERIPH_BASE + 0x6400U)
 
#define CAN2_BASE   (APB1PERIPH_BASE + 0x6800U)
 
#define CEC_BASE   (APB1PERIPH_BASE + 0x6C00U)
 
#define PWR_BASE   (APB1PERIPH_BASE + 0x7000U)
 
#define DAC_BASE   (APB1PERIPH_BASE + 0x7400U)
 
#define UART7_BASE   (APB1PERIPH_BASE + 0x7800U)
 
#define UART8_BASE   (APB1PERIPH_BASE + 0x7C00U)
 
#define TIM1_BASE   (APB2PERIPH_BASE + 0x0000U)
 
#define TIM8_BASE   (APB2PERIPH_BASE + 0x0400U)
 
#define USART1_BASE   (APB2PERIPH_BASE + 0x1000U)
 
#define USART6_BASE   (APB2PERIPH_BASE + 0x1400U)
 
#define SDMMC2_BASE   (APB2PERIPH_BASE + 0x1C00U)
 
#define ADC1_BASE   (APB2PERIPH_BASE + 0x2000U)
 
#define ADC2_BASE   (APB2PERIPH_BASE + 0x2100U)
 
#define ADC3_BASE   (APB2PERIPH_BASE + 0x2200U)
 
#define ADC_BASE   (APB2PERIPH_BASE + 0x2300U)
 
#define SDMMC1_BASE   (APB2PERIPH_BASE + 0x2C00U)
 
#define SPI1_BASE   (APB2PERIPH_BASE + 0x3000U)
 
#define SPI4_BASE   (APB2PERIPH_BASE + 0x3400U)
 
#define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800U)
 
#define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00U)
 
#define TIM9_BASE   (APB2PERIPH_BASE + 0x4000U)
 
#define TIM10_BASE   (APB2PERIPH_BASE + 0x4400U)
 
#define TIM11_BASE   (APB2PERIPH_BASE + 0x4800U)
 
#define SPI5_BASE   (APB2PERIPH_BASE + 0x5000U)
 
#define SPI6_BASE   (APB2PERIPH_BASE + 0x5400U)
 
#define SAI1_BASE   (APB2PERIPH_BASE + 0x5800U)
 
#define SAI2_BASE   (APB2PERIPH_BASE + 0x5C00U)
 
#define SAI1_Block_A_BASE   (SAI1_BASE + 0x004U)
 
#define SAI1_Block_B_BASE   (SAI1_BASE + 0x024U)
 
#define SAI2_Block_A_BASE   (SAI2_BASE + 0x004U)
 
#define SAI2_Block_B_BASE   (SAI2_BASE + 0x024U)
 
#define LTDC_BASE   (APB2PERIPH_BASE + 0x6800U)
 
#define LTDC_Layer1_BASE   (LTDC_BASE + 0x84U)
 
#define LTDC_Layer2_BASE   (LTDC_BASE + 0x104U)
 
#define DFSDM1_BASE   (APB2PERIPH_BASE + 0x7400U)
 
#define DFSDM1_Channel0_BASE   (DFSDM1_BASE + 0x00U)
 
#define DFSDM1_Channel1_BASE   (DFSDM1_BASE + 0x20U)
 
#define DFSDM1_Channel2_BASE   (DFSDM1_BASE + 0x40U)
 
#define DFSDM1_Channel3_BASE   (DFSDM1_BASE + 0x60U)
 
#define DFSDM1_Channel4_BASE   (DFSDM1_BASE + 0x80U)
 
#define DFSDM1_Channel5_BASE   (DFSDM1_BASE + 0xA0U)
 
#define DFSDM1_Channel6_BASE   (DFSDM1_BASE + 0xC0U)
 
#define DFSDM1_Channel7_BASE   (DFSDM1_BASE + 0xE0U)
 
#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100U)
 
#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180U)
 
#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200U)
 
#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280U)
 
#define MDIOS_BASE   (APB2PERIPH_BASE + 0x7800U)
 
#define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000U)
 
#define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400U)
 
#define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800U)
 
#define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00U)
 
#define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000U)
 
#define GPIOF_BASE   (AHB1PERIPH_BASE + 0x1400U)
 
#define GPIOG_BASE   (AHB1PERIPH_BASE + 0x1800U)
 
#define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00U)
 
#define GPIOI_BASE   (AHB1PERIPH_BASE + 0x2000U)
 
#define GPIOJ_BASE   (AHB1PERIPH_BASE + 0x2400U)
 
#define GPIOK_BASE   (AHB1PERIPH_BASE + 0x2800U)
 
#define CRC_BASE   (AHB1PERIPH_BASE + 0x3000U)
 
#define RCC_BASE   (AHB1PERIPH_BASE + 0x3800U)
 
#define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00U)
 
#define UID_BASE   0x1FF0F420U
 
#define FLASHSIZE_BASE   0x1FF0F442U
 
#define PACKAGESIZE_BASE   0x1FFF7BF0U
 
#define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000U)
 
#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010U)
 
#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028U)
 
#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040U)
 
#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058U)
 
#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070U)
 
#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088U)
 
#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0U)
 
#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8U)
 
#define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400U)
 
#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010U)
 
#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028U)
 
#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040U)
 
#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058U)
 
#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070U)
 
#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088U)
 
#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0U)
 
#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8U)
 
#define ETH_BASE   (AHB1PERIPH_BASE + 0x8000U)
 
#define ETH_MAC_BASE   (ETH_BASE)
 
#define ETH_MMC_BASE   (ETH_BASE + 0x0100U)
 
#define ETH_PTP_BASE   (ETH_BASE + 0x0700U)
 
#define ETH_DMA_BASE   (ETH_BASE + 0x1000U)
 
#define DMA2D_BASE   (AHB1PERIPH_BASE + 0xB000U)
 
#define DCMI_BASE   (AHB2PERIPH_BASE + 0x50000U)
 
#define JPEG_BASE   (AHB2PERIPH_BASE + 0x51000U)
 
#define RNG_BASE   (AHB2PERIPH_BASE + 0x60800U)
 
#define FMC_Bank1_R_BASE   (FMC_R_BASE + 0x0000U)
 
#define FMC_Bank1E_R_BASE   (FMC_R_BASE + 0x0104U)
 
#define FMC_Bank3_R_BASE   (FMC_R_BASE + 0x0080U)
 
#define FMC_Bank5_6_R_BASE   (FMC_R_BASE + 0x0140U)
 
#define DBGMCU_BASE   0xE0042000U
 
#define USB_OTG_HS_PERIPH_BASE   0x40040000U
 
#define USB_OTG_FS_PERIPH_BASE   0x50000000U
 
#define USB_OTG_GLOBAL_BASE   0x000U
 
#define USB_OTG_DEVICE_BASE   0x800U
 
#define USB_OTG_IN_ENDPOINT_BASE   0x900U
 
#define USB_OTG_OUT_ENDPOINT_BASE   0xB00U
 
#define USB_OTG_EP_REG_SIZE   0x20U
 
#define USB_OTG_HOST_BASE   0x400U
 
#define USB_OTG_HOST_PORT_BASE   0x440U
 
#define USB_OTG_HOST_CHANNEL_BASE   0x500U
 
#define USB_OTG_HOST_CHANNEL_SIZE   0x20U
 
#define USB_OTG_PCGCCTL_BASE   0xE00U
 
#define USB_OTG_FIFO_BASE   0x1000U
 
#define USB_OTG_FIFO_SIZE   0x1000U
 
#define RAMITCM_BASE   0x00000000U
 
#define FLASHITCM_BASE   0x00200000U
 
#define FLASHAXI_BASE   0x08000000U
 
#define RAMDTCM_BASE   0x20000000U
 
#define PERIPH_BASE   0x40000000U
 
#define BKPSRAM_BASE   0x40024000U
 
#define QSPI_BASE   0x90000000U
 
#define FMC_R_BASE   0xA0000000U
 
#define QSPI_R_BASE   0xA0001000U
 
#define SRAM1_BASE   0x20020000U
 
#define SRAM2_BASE   0x2007C000U
 
#define FLASH_END   0x081FFFFFU
 
#define FLASH_BASE   FLASHAXI_BASE
 
#define APB1PERIPH_BASE   PERIPH_BASE
 
#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000U)
 
#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000U)
 
#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000U)
 
#define TIM2_BASE   (APB1PERIPH_BASE + 0x0000U)
 
#define TIM3_BASE   (APB1PERIPH_BASE + 0x0400U)
 
#define TIM4_BASE   (APB1PERIPH_BASE + 0x0800U)
 
#define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00U)
 
#define TIM6_BASE   (APB1PERIPH_BASE + 0x1000U)
 
#define TIM7_BASE   (APB1PERIPH_BASE + 0x1400U)
 
#define TIM12_BASE   (APB1PERIPH_BASE + 0x1800U)
 
#define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00U)
 
#define TIM14_BASE   (APB1PERIPH_BASE + 0x2000U)
 
#define LPTIM1_BASE   (APB1PERIPH_BASE + 0x2400U)
 
#define RTC_BASE   (APB1PERIPH_BASE + 0x2800U)
 
#define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00U)
 
#define IWDG_BASE   (APB1PERIPH_BASE + 0x3000U)
 
#define CAN3_BASE   (APB1PERIPH_BASE + 0x3400U)
 
#define SPI2_BASE   (APB1PERIPH_BASE + 0x3800U)
 
#define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00U)
 
#define SPDIFRX_BASE   (APB1PERIPH_BASE + 0x4000U)
 
#define USART2_BASE   (APB1PERIPH_BASE + 0x4400U)
 
#define USART3_BASE   (APB1PERIPH_BASE + 0x4800U)
 
#define UART4_BASE   (APB1PERIPH_BASE + 0x4C00U)
 
#define UART5_BASE   (APB1PERIPH_BASE + 0x5000U)
 
#define I2C1_BASE   (APB1PERIPH_BASE + 0x5400U)
 
#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800U)
 
#define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00U)
 
#define I2C4_BASE   (APB1PERIPH_BASE + 0x6000U)
 
#define CAN1_BASE   (APB1PERIPH_BASE + 0x6400U)
 
#define CAN2_BASE   (APB1PERIPH_BASE + 0x6800U)
 
#define CEC_BASE   (APB1PERIPH_BASE + 0x6C00U)
 
#define PWR_BASE   (APB1PERIPH_BASE + 0x7000U)
 
#define DAC_BASE   (APB1PERIPH_BASE + 0x7400U)
 
#define UART7_BASE   (APB1PERIPH_BASE + 0x7800U)
 
#define UART8_BASE   (APB1PERIPH_BASE + 0x7C00U)
 
#define TIM1_BASE   (APB2PERIPH_BASE + 0x0000U)
 
#define TIM8_BASE   (APB2PERIPH_BASE + 0x0400U)
 
#define USART1_BASE   (APB2PERIPH_BASE + 0x1000U)
 
#define USART6_BASE   (APB2PERIPH_BASE + 0x1400U)
 
#define SDMMC2_BASE   (APB2PERIPH_BASE + 0x1C00U)
 
#define ADC1_BASE   (APB2PERIPH_BASE + 0x2000U)
 
#define ADC2_BASE   (APB2PERIPH_BASE + 0x2100U)
 
#define ADC3_BASE   (APB2PERIPH_BASE + 0x2200U)
 
#define ADC_BASE   (APB2PERIPH_BASE + 0x2300U)
 
#define SDMMC1_BASE   (APB2PERIPH_BASE + 0x2C00U)
 
#define SPI1_BASE   (APB2PERIPH_BASE + 0x3000U)
 
#define SPI4_BASE   (APB2PERIPH_BASE + 0x3400U)
 
#define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800U)
 
#define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00U)
 
#define TIM9_BASE   (APB2PERIPH_BASE + 0x4000U)
 
#define TIM10_BASE   (APB2PERIPH_BASE + 0x4400U)
 
#define TIM11_BASE   (APB2PERIPH_BASE + 0x4800U)
 
#define SPI5_BASE   (APB2PERIPH_BASE + 0x5000U)
 
#define SPI6_BASE   (APB2PERIPH_BASE + 0x5400U)
 
#define SAI1_BASE   (APB2PERIPH_BASE + 0x5800U)
 
#define SAI2_BASE   (APB2PERIPH_BASE + 0x5C00U)
 
#define SAI1_Block_A_BASE   (SAI1_BASE + 0x004U)
 
#define SAI1_Block_B_BASE   (SAI1_BASE + 0x024U)
 
#define SAI2_Block_A_BASE   (SAI2_BASE + 0x004U)
 
#define SAI2_Block_B_BASE   (SAI2_BASE + 0x024U)
 
#define LTDC_BASE   (APB2PERIPH_BASE + 0x6800U)
 
#define LTDC_Layer1_BASE   (LTDC_BASE + 0x84U)
 
#define LTDC_Layer2_BASE   (LTDC_BASE + 0x104U)
 
#define DSI_BASE   (APB2PERIPH_BASE + 0x6C00U)
 
#define DFSDM1_BASE   (APB2PERIPH_BASE + 0x7400U)
 
#define DFSDM1_Channel0_BASE   (DFSDM1_BASE + 0x00U)
 
#define DFSDM1_Channel1_BASE   (DFSDM1_BASE + 0x20U)
 
#define DFSDM1_Channel2_BASE   (DFSDM1_BASE + 0x40U)
 
#define DFSDM1_Channel3_BASE   (DFSDM1_BASE + 0x60U)
 
#define DFSDM1_Channel4_BASE   (DFSDM1_BASE + 0x80U)
 
#define DFSDM1_Channel5_BASE   (DFSDM1_BASE + 0xA0U)
 
#define DFSDM1_Channel6_BASE   (DFSDM1_BASE + 0xC0U)
 
#define DFSDM1_Channel7_BASE   (DFSDM1_BASE + 0xE0U)
 
#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100U)
 
#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180U)
 
#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200U)
 
#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280U)
 
#define MDIOS_BASE   (APB2PERIPH_BASE + 0x7800U)
 
#define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000U)
 
#define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400U)
 
#define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800U)
 
#define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00U)
 
#define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000U)
 
#define GPIOF_BASE   (AHB1PERIPH_BASE + 0x1400U)
 
#define GPIOG_BASE   (AHB1PERIPH_BASE + 0x1800U)
 
#define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00U)
 
#define GPIOI_BASE   (AHB1PERIPH_BASE + 0x2000U)
 
#define GPIOJ_BASE   (AHB1PERIPH_BASE + 0x2400U)
 
#define GPIOK_BASE   (AHB1PERIPH_BASE + 0x2800U)
 
#define CRC_BASE   (AHB1PERIPH_BASE + 0x3000U)
 
#define RCC_BASE   (AHB1PERIPH_BASE + 0x3800U)
 
#define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00U)
 
#define UID_BASE   0x1FF0F420U
 
#define FLASHSIZE_BASE   0x1FF0F442U
 
#define PACKAGESIZE_BASE   0x1FFF7BF0U
 
#define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000U)
 
#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010U)
 
#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028U)
 
#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040U)
 
#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058U)
 
#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070U)
 
#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088U)
 
#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0U)
 
#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8U)
 
#define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400U)
 
#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010U)
 
#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028U)
 
#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040U)
 
#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058U)
 
#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070U)
 
#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088U)
 
#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0U)
 
#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8U)
 
#define ETH_BASE   (AHB1PERIPH_BASE + 0x8000U)
 
#define ETH_MAC_BASE   (ETH_BASE)
 
#define ETH_MMC_BASE   (ETH_BASE + 0x0100U)
 
#define ETH_PTP_BASE   (ETH_BASE + 0x0700U)
 
#define ETH_DMA_BASE   (ETH_BASE + 0x1000U)
 
#define DMA2D_BASE   (AHB1PERIPH_BASE + 0xB000U)
 
#define DCMI_BASE   (AHB2PERIPH_BASE + 0x50000U)
 
#define JPEG_BASE   (AHB2PERIPH_BASE + 0x51000U)
 
#define RNG_BASE   (AHB2PERIPH_BASE + 0x60800U)
 
#define FMC_Bank1_R_BASE   (FMC_R_BASE + 0x0000U)
 
#define FMC_Bank1E_R_BASE   (FMC_R_BASE + 0x0104U)
 
#define FMC_Bank3_R_BASE   (FMC_R_BASE + 0x0080U)
 
#define FMC_Bank5_6_R_BASE   (FMC_R_BASE + 0x0140U)
 
#define DBGMCU_BASE   0xE0042000U
 
#define USB_OTG_HS_PERIPH_BASE   0x40040000U
 
#define USB_OTG_FS_PERIPH_BASE   0x50000000U
 
#define USB_OTG_GLOBAL_BASE   0x000U
 
#define USB_OTG_DEVICE_BASE   0x800U
 
#define USB_OTG_IN_ENDPOINT_BASE   0x900U
 
#define USB_OTG_OUT_ENDPOINT_BASE   0xB00U
 
#define USB_OTG_EP_REG_SIZE   0x20U
 
#define USB_OTG_HOST_BASE   0x400U
 
#define USB_OTG_HOST_PORT_BASE   0x440U
 
#define USB_OTG_HOST_CHANNEL_BASE   0x500U
 
#define USB_OTG_HOST_CHANNEL_SIZE   0x20U
 
#define USB_OTG_PCGCCTL_BASE   0xE00U
 
#define USB_OTG_FIFO_BASE   0x1000U
 
#define USB_OTG_FIFO_SIZE   0x1000U
 
#define RAMITCM_BASE   0x00000000U
 
#define FLASHITCM_BASE   0x00200000U
 
#define FLASHAXI_BASE   0x08000000U
 
#define RAMDTCM_BASE   0x20000000U
 
#define PERIPH_BASE   0x40000000U
 
#define BKPSRAM_BASE   0x40024000U
 
#define QSPI_BASE   0x90000000U
 
#define FMC_R_BASE   0xA0000000U
 
#define QSPI_R_BASE   0xA0001000U
 
#define SRAM1_BASE   0x20020000U
 
#define SRAM2_BASE   0x2007C000U
 
#define FLASH_END   0x081FFFFFU
 
#define FLASH_BASE   FLASHAXI_BASE
 
#define APB1PERIPH_BASE   PERIPH_BASE
 
#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000U)
 
#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000U)
 
#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000U)
 
#define TIM2_BASE   (APB1PERIPH_BASE + 0x0000U)
 
#define TIM3_BASE   (APB1PERIPH_BASE + 0x0400U)
 
#define TIM4_BASE   (APB1PERIPH_BASE + 0x0800U)
 
#define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00U)
 
#define TIM6_BASE   (APB1PERIPH_BASE + 0x1000U)
 
#define TIM7_BASE   (APB1PERIPH_BASE + 0x1400U)
 
#define TIM12_BASE   (APB1PERIPH_BASE + 0x1800U)
 
#define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00U)
 
#define TIM14_BASE   (APB1PERIPH_BASE + 0x2000U)
 
#define LPTIM1_BASE   (APB1PERIPH_BASE + 0x2400U)
 
#define RTC_BASE   (APB1PERIPH_BASE + 0x2800U)
 
#define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00U)
 
#define IWDG_BASE   (APB1PERIPH_BASE + 0x3000U)
 
#define CAN3_BASE   (APB1PERIPH_BASE + 0x3400U)
 
#define SPI2_BASE   (APB1PERIPH_BASE + 0x3800U)
 
#define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00U)
 
#define SPDIFRX_BASE   (APB1PERIPH_BASE + 0x4000U)
 
#define USART2_BASE   (APB1PERIPH_BASE + 0x4400U)
 
#define USART3_BASE   (APB1PERIPH_BASE + 0x4800U)
 
#define UART4_BASE   (APB1PERIPH_BASE + 0x4C00U)
 
#define UART5_BASE   (APB1PERIPH_BASE + 0x5000U)
 
#define I2C1_BASE   (APB1PERIPH_BASE + 0x5400U)
 
#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800U)
 
#define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00U)
 
#define I2C4_BASE   (APB1PERIPH_BASE + 0x6000U)
 
#define CAN1_BASE   (APB1PERIPH_BASE + 0x6400U)
 
#define CAN2_BASE   (APB1PERIPH_BASE + 0x6800U)
 
#define CEC_BASE   (APB1PERIPH_BASE + 0x6C00U)
 
#define PWR_BASE   (APB1PERIPH_BASE + 0x7000U)
 
#define DAC_BASE   (APB1PERIPH_BASE + 0x7400U)
 
#define UART7_BASE   (APB1PERIPH_BASE + 0x7800U)
 
#define UART8_BASE   (APB1PERIPH_BASE + 0x7C00U)
 
#define TIM1_BASE   (APB2PERIPH_BASE + 0x0000U)
 
#define TIM8_BASE   (APB2PERIPH_BASE + 0x0400U)
 
#define USART1_BASE   (APB2PERIPH_BASE + 0x1000U)
 
#define USART6_BASE   (APB2PERIPH_BASE + 0x1400U)
 
#define SDMMC2_BASE   (APB2PERIPH_BASE + 0x1C00U)
 
#define ADC1_BASE   (APB2PERIPH_BASE + 0x2000U)
 
#define ADC2_BASE   (APB2PERIPH_BASE + 0x2100U)
 
#define ADC3_BASE   (APB2PERIPH_BASE + 0x2200U)
 
#define ADC_BASE   (APB2PERIPH_BASE + 0x2300U)
 
#define SDMMC1_BASE   (APB2PERIPH_BASE + 0x2C00U)
 
#define SPI1_BASE   (APB2PERIPH_BASE + 0x3000U)
 
#define SPI4_BASE   (APB2PERIPH_BASE + 0x3400U)
 
#define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800U)
 
#define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00U)
 
#define TIM9_BASE   (APB2PERIPH_BASE + 0x4000U)
 
#define TIM10_BASE   (APB2PERIPH_BASE + 0x4400U)
 
#define TIM11_BASE   (APB2PERIPH_BASE + 0x4800U)
 
#define SPI5_BASE   (APB2PERIPH_BASE + 0x5000U)
 
#define SPI6_BASE   (APB2PERIPH_BASE + 0x5400U)
 
#define SAI1_BASE   (APB2PERIPH_BASE + 0x5800U)
 
#define SAI2_BASE   (APB2PERIPH_BASE + 0x5C00U)
 
#define SAI1_Block_A_BASE   (SAI1_BASE + 0x004U)
 
#define SAI1_Block_B_BASE   (SAI1_BASE + 0x024U)
 
#define SAI2_Block_A_BASE   (SAI2_BASE + 0x004U)
 
#define SAI2_Block_B_BASE   (SAI2_BASE + 0x024U)
 
#define LTDC_BASE   (APB2PERIPH_BASE + 0x6800U)
 
#define LTDC_Layer1_BASE   (LTDC_BASE + 0x84U)
 
#define LTDC_Layer2_BASE   (LTDC_BASE + 0x104U)
 
#define DFSDM1_BASE   (APB2PERIPH_BASE + 0x7400U)
 
#define DFSDM1_Channel0_BASE   (DFSDM1_BASE + 0x00U)
 
#define DFSDM1_Channel1_BASE   (DFSDM1_BASE + 0x20U)
 
#define DFSDM1_Channel2_BASE   (DFSDM1_BASE + 0x40U)
 
#define DFSDM1_Channel3_BASE   (DFSDM1_BASE + 0x60U)
 
#define DFSDM1_Channel4_BASE   (DFSDM1_BASE + 0x80U)
 
#define DFSDM1_Channel5_BASE   (DFSDM1_BASE + 0xA0U)
 
#define DFSDM1_Channel6_BASE   (DFSDM1_BASE + 0xC0U)
 
#define DFSDM1_Channel7_BASE   (DFSDM1_BASE + 0xE0U)
 
#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100U)
 
#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180U)
 
#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200U)
 
#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280U)
 
#define MDIOS_BASE   (APB2PERIPH_BASE + 0x7800U)
 
#define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000U)
 
#define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400U)
 
#define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800U)
 
#define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00U)
 
#define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000U)
 
#define GPIOF_BASE   (AHB1PERIPH_BASE + 0x1400U)
 
#define GPIOG_BASE   (AHB1PERIPH_BASE + 0x1800U)
 
#define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00U)
 
#define GPIOI_BASE   (AHB1PERIPH_BASE + 0x2000U)
 
#define GPIOJ_BASE   (AHB1PERIPH_BASE + 0x2400U)
 
#define GPIOK_BASE   (AHB1PERIPH_BASE + 0x2800U)
 
#define CRC_BASE   (AHB1PERIPH_BASE + 0x3000U)
 
#define RCC_BASE   (AHB1PERIPH_BASE + 0x3800U)
 
#define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00U)
 
#define UID_BASE   0x1FF0F420U
 
#define FLASHSIZE_BASE   0x1FF0F442U
 
#define PACKAGESIZE_BASE   0x1FFF7BF0U
 
#define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000U)
 
#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010U)
 
#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028U)
 
#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040U)
 
#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058U)
 
#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070U)
 
#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088U)
 
#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0U)
 
#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8U)
 
#define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400U)
 
#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010U)
 
#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028U)
 
#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040U)
 
#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058U)
 
#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070U)
 
#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088U)
 
#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0U)
 
#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8U)
 
#define ETH_BASE   (AHB1PERIPH_BASE + 0x8000U)
 
#define ETH_MAC_BASE   (ETH_BASE)
 
#define ETH_MMC_BASE   (ETH_BASE + 0x0100U)
 
#define ETH_PTP_BASE   (ETH_BASE + 0x0700U)
 
#define ETH_DMA_BASE   (ETH_BASE + 0x1000U)
 
#define DMA2D_BASE   (AHB1PERIPH_BASE + 0xB000U)
 
#define DCMI_BASE   (AHB2PERIPH_BASE + 0x50000U)
 
#define JPEG_BASE   (AHB2PERIPH_BASE + 0x51000U)
 
#define CRYP_BASE   (AHB2PERIPH_BASE + 0x60000U)
 
#define HASH_BASE   (AHB2PERIPH_BASE + 0x60400U)
 
#define HASH_DIGEST_BASE   (AHB2PERIPH_BASE + 0x60710U)
 
#define RNG_BASE   (AHB2PERIPH_BASE + 0x60800U)
 
#define FMC_Bank1_R_BASE   (FMC_R_BASE + 0x0000U)
 
#define FMC_Bank1E_R_BASE   (FMC_R_BASE + 0x0104U)
 
#define FMC_Bank3_R_BASE   (FMC_R_BASE + 0x0080U)
 
#define FMC_Bank5_6_R_BASE   (FMC_R_BASE + 0x0140U)
 
#define DBGMCU_BASE   0xE0042000U
 
#define USB_OTG_HS_PERIPH_BASE   0x40040000U
 
#define USB_OTG_FS_PERIPH_BASE   0x50000000U
 
#define USB_OTG_GLOBAL_BASE   0x000U
 
#define USB_OTG_DEVICE_BASE   0x800U
 
#define USB_OTG_IN_ENDPOINT_BASE   0x900U
 
#define USB_OTG_OUT_ENDPOINT_BASE   0xB00U
 
#define USB_OTG_EP_REG_SIZE   0x20U
 
#define USB_OTG_HOST_BASE   0x400U
 
#define USB_OTG_HOST_PORT_BASE   0x440U
 
#define USB_OTG_HOST_CHANNEL_BASE   0x500U
 
#define USB_OTG_HOST_CHANNEL_SIZE   0x20U
 
#define USB_OTG_PCGCCTL_BASE   0xE00U
 
#define USB_OTG_FIFO_BASE   0x1000U
 
#define USB_OTG_FIFO_SIZE   0x1000U
 
#define RAMITCM_BASE   0x00000000U
 
#define FLASHITCM_BASE   0x00200000U
 
#define FLASHAXI_BASE   0x08000000U
 
#define RAMDTCM_BASE   0x20000000U
 
#define PERIPH_BASE   0x40000000U
 
#define BKPSRAM_BASE   0x40024000U
 
#define QSPI_BASE   0x90000000U
 
#define FMC_R_BASE   0xA0000000U
 
#define QSPI_R_BASE   0xA0001000U
 
#define SRAM1_BASE   0x20020000U
 
#define SRAM2_BASE   0x2007C000U
 
#define FLASH_END   0x081FFFFFU
 
#define FLASH_BASE   FLASHAXI_BASE
 
#define APB1PERIPH_BASE   PERIPH_BASE
 
#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000U)
 
#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000U)
 
#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000U)
 
#define TIM2_BASE   (APB1PERIPH_BASE + 0x0000U)
 
#define TIM3_BASE   (APB1PERIPH_BASE + 0x0400U)
 
#define TIM4_BASE   (APB1PERIPH_BASE + 0x0800U)
 
#define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00U)
 
#define TIM6_BASE   (APB1PERIPH_BASE + 0x1000U)
 
#define TIM7_BASE   (APB1PERIPH_BASE + 0x1400U)
 
#define TIM12_BASE   (APB1PERIPH_BASE + 0x1800U)
 
#define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00U)
 
#define TIM14_BASE   (APB1PERIPH_BASE + 0x2000U)
 
#define LPTIM1_BASE   (APB1PERIPH_BASE + 0x2400U)
 
#define RTC_BASE   (APB1PERIPH_BASE + 0x2800U)
 
#define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00U)
 
#define IWDG_BASE   (APB1PERIPH_BASE + 0x3000U)
 
#define CAN3_BASE   (APB1PERIPH_BASE + 0x3400U)
 
#define SPI2_BASE   (APB1PERIPH_BASE + 0x3800U)
 
#define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00U)
 
#define SPDIFRX_BASE   (APB1PERIPH_BASE + 0x4000U)
 
#define USART2_BASE   (APB1PERIPH_BASE + 0x4400U)
 
#define USART3_BASE   (APB1PERIPH_BASE + 0x4800U)
 
#define UART4_BASE   (APB1PERIPH_BASE + 0x4C00U)
 
#define UART5_BASE   (APB1PERIPH_BASE + 0x5000U)
 
#define I2C1_BASE   (APB1PERIPH_BASE + 0x5400U)
 
#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800U)
 
#define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00U)
 
#define I2C4_BASE   (APB1PERIPH_BASE + 0x6000U)
 
#define CAN1_BASE   (APB1PERIPH_BASE + 0x6400U)
 
#define CAN2_BASE   (APB1PERIPH_BASE + 0x6800U)
 
#define CEC_BASE   (APB1PERIPH_BASE + 0x6C00U)
 
#define PWR_BASE   (APB1PERIPH_BASE + 0x7000U)
 
#define DAC_BASE   (APB1PERIPH_BASE + 0x7400U)
 
#define UART7_BASE   (APB1PERIPH_BASE + 0x7800U)
 
#define UART8_BASE   (APB1PERIPH_BASE + 0x7C00U)
 
#define TIM1_BASE   (APB2PERIPH_BASE + 0x0000U)
 
#define TIM8_BASE   (APB2PERIPH_BASE + 0x0400U)
 
#define USART1_BASE   (APB2PERIPH_BASE + 0x1000U)
 
#define USART6_BASE   (APB2PERIPH_BASE + 0x1400U)
 
#define SDMMC2_BASE   (APB2PERIPH_BASE + 0x1C00U)
 
#define ADC1_BASE   (APB2PERIPH_BASE + 0x2000U)
 
#define ADC2_BASE   (APB2PERIPH_BASE + 0x2100U)
 
#define ADC3_BASE   (APB2PERIPH_BASE + 0x2200U)
 
#define ADC_BASE   (APB2PERIPH_BASE + 0x2300U)
 
#define SDMMC1_BASE   (APB2PERIPH_BASE + 0x2C00U)
 
#define SPI1_BASE   (APB2PERIPH_BASE + 0x3000U)
 
#define SPI4_BASE   (APB2PERIPH_BASE + 0x3400U)
 
#define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800U)
 
#define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00U)
 
#define TIM9_BASE   (APB2PERIPH_BASE + 0x4000U)
 
#define TIM10_BASE   (APB2PERIPH_BASE + 0x4400U)
 
#define TIM11_BASE   (APB2PERIPH_BASE + 0x4800U)
 
#define SPI5_BASE   (APB2PERIPH_BASE + 0x5000U)
 
#define SPI6_BASE   (APB2PERIPH_BASE + 0x5400U)
 
#define SAI1_BASE   (APB2PERIPH_BASE + 0x5800U)
 
#define SAI2_BASE   (APB2PERIPH_BASE + 0x5C00U)
 
#define SAI1_Block_A_BASE   (SAI1_BASE + 0x004U)
 
#define SAI1_Block_B_BASE   (SAI1_BASE + 0x024U)
 
#define SAI2_Block_A_BASE   (SAI2_BASE + 0x004U)
 
#define SAI2_Block_B_BASE   (SAI2_BASE + 0x024U)
 
#define LTDC_BASE   (APB2PERIPH_BASE + 0x6800U)
 
#define LTDC_Layer1_BASE   (LTDC_BASE + 0x84U)
 
#define LTDC_Layer2_BASE   (LTDC_BASE + 0x104U)
 
#define DSI_BASE   (APB2PERIPH_BASE + 0x6C00U)
 
#define DFSDM1_BASE   (APB2PERIPH_BASE + 0x7400U)
 
#define DFSDM1_Channel0_BASE   (DFSDM1_BASE + 0x00U)
 
#define DFSDM1_Channel1_BASE   (DFSDM1_BASE + 0x20U)
 
#define DFSDM1_Channel2_BASE   (DFSDM1_BASE + 0x40U)
 
#define DFSDM1_Channel3_BASE   (DFSDM1_BASE + 0x60U)
 
#define DFSDM1_Channel4_BASE   (DFSDM1_BASE + 0x80U)
 
#define DFSDM1_Channel5_BASE   (DFSDM1_BASE + 0xA0U)
 
#define DFSDM1_Channel6_BASE   (DFSDM1_BASE + 0xC0U)
 
#define DFSDM1_Channel7_BASE   (DFSDM1_BASE + 0xE0U)
 
#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100U)
 
#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180U)
 
#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200U)
 
#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280U)
 
#define MDIOS_BASE   (APB2PERIPH_BASE + 0x7800U)
 
#define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000U)
 
#define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400U)
 
#define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800U)
 
#define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00U)
 
#define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000U)
 
#define GPIOF_BASE   (AHB1PERIPH_BASE + 0x1400U)
 
#define GPIOG_BASE   (AHB1PERIPH_BASE + 0x1800U)
 
#define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00U)
 
#define GPIOI_BASE   (AHB1PERIPH_BASE + 0x2000U)
 
#define GPIOJ_BASE   (AHB1PERIPH_BASE + 0x2400U)
 
#define GPIOK_BASE   (AHB1PERIPH_BASE + 0x2800U)
 
#define CRC_BASE   (AHB1PERIPH_BASE + 0x3000U)
 
#define RCC_BASE   (AHB1PERIPH_BASE + 0x3800U)
 
#define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00U)
 
#define UID_BASE   0x1FF0F420U
 
#define FLASHSIZE_BASE   0x1FF0F442U
 
#define PACKAGESIZE_BASE   0x1FFF7BF0U
 
#define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000U)
 
#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010U)
 
#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028U)
 
#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040U)
 
#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058U)
 
#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070U)
 
#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088U)
 
#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0U)
 
#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8U)
 
#define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400U)
 
#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010U)
 
#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028U)
 
#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040U)
 
#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058U)
 
#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070U)
 
#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088U)
 
#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0U)
 
#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8U)
 
#define ETH_BASE   (AHB1PERIPH_BASE + 0x8000U)
 
#define ETH_MAC_BASE   (ETH_BASE)
 
#define ETH_MMC_BASE   (ETH_BASE + 0x0100U)
 
#define ETH_PTP_BASE   (ETH_BASE + 0x0700U)
 
#define ETH_DMA_BASE   (ETH_BASE + 0x1000U)
 
#define DMA2D_BASE   (AHB1PERIPH_BASE + 0xB000U)
 
#define DCMI_BASE   (AHB2PERIPH_BASE + 0x50000U)
 
#define JPEG_BASE   (AHB2PERIPH_BASE + 0x51000U)
 
#define CRYP_BASE   (AHB2PERIPH_BASE + 0x60000U)
 
#define HASH_BASE   (AHB2PERIPH_BASE + 0x60400U)
 
#define HASH_DIGEST_BASE   (AHB2PERIPH_BASE + 0x60710U)
 
#define RNG_BASE   (AHB2PERIPH_BASE + 0x60800U)
 
#define FMC_Bank1_R_BASE   (FMC_R_BASE + 0x0000U)
 
#define FMC_Bank1E_R_BASE   (FMC_R_BASE + 0x0104U)
 
#define FMC_Bank3_R_BASE   (FMC_R_BASE + 0x0080U)
 
#define FMC_Bank5_6_R_BASE   (FMC_R_BASE + 0x0140U)
 
#define DBGMCU_BASE   0xE0042000U
 
#define USB_OTG_HS_PERIPH_BASE   0x40040000U
 
#define USB_OTG_FS_PERIPH_BASE   0x50000000U
 
#define USB_OTG_GLOBAL_BASE   0x000U
 
#define USB_OTG_DEVICE_BASE   0x800U
 
#define USB_OTG_IN_ENDPOINT_BASE   0x900U
 
#define USB_OTG_OUT_ENDPOINT_BASE   0xB00U
 
#define USB_OTG_EP_REG_SIZE   0x20U
 
#define USB_OTG_HOST_BASE   0x400U
 
#define USB_OTG_HOST_PORT_BASE   0x440U
 
#define USB_OTG_HOST_CHANNEL_BASE   0x500U
 
#define USB_OTG_HOST_CHANNEL_SIZE   0x20U
 
#define USB_OTG_PCGCCTL_BASE   0xE00U
 
#define USB_OTG_FIFO_BASE   0x1000U
 
#define USB_OTG_FIFO_SIZE   0x1000U
 

Detailed Description

Macro Definition Documentation

#define ADC1_BASE   (APB2PERIPH_BASE + 0x2000U)

Definition at line 1160 of file stm32f745xx.h.

#define ADC1_BASE   (APB2PERIPH_BASE + 0x2000U)

Definition at line 1209 of file stm32f746xx.h.

#define ADC1_BASE   (APB2PERIPH_BASE + 0x2000U)

Definition at line 1278 of file stm32f756xx.h.

#define ADC1_BASE   (APB2PERIPH_BASE + 0x2000U)

Definition at line 1288 of file stm32f765xx.h.

#define ADC1_BASE   (APB2PERIPH_BASE + 0x2000U)

Definition at line 1374 of file stm32f767xx.h.

#define ADC1_BASE   (APB2PERIPH_BASE + 0x2000U)

Definition at line 1443 of file stm32f777xx.h.

#define ADC1_BASE   (APB2PERIPH_BASE + 0x2000U)

Definition at line 1455 of file stm32f769xx.h.

#define ADC1_BASE   (APB2PERIPH_BASE + 0x2000U)

Definition at line 1524 of file stm32f779xx.h.

#define ADC2_BASE   (APB2PERIPH_BASE + 0x2100U)

Definition at line 1161 of file stm32f745xx.h.

#define ADC2_BASE   (APB2PERIPH_BASE + 0x2100U)

Definition at line 1210 of file stm32f746xx.h.

#define ADC2_BASE   (APB2PERIPH_BASE + 0x2100U)

Definition at line 1279 of file stm32f756xx.h.

#define ADC2_BASE   (APB2PERIPH_BASE + 0x2100U)

Definition at line 1289 of file stm32f765xx.h.

#define ADC2_BASE   (APB2PERIPH_BASE + 0x2100U)

Definition at line 1375 of file stm32f767xx.h.

#define ADC2_BASE   (APB2PERIPH_BASE + 0x2100U)

Definition at line 1444 of file stm32f777xx.h.

#define ADC2_BASE   (APB2PERIPH_BASE + 0x2100U)

Definition at line 1456 of file stm32f769xx.h.

#define ADC2_BASE   (APB2PERIPH_BASE + 0x2100U)

Definition at line 1525 of file stm32f779xx.h.

#define ADC3_BASE   (APB2PERIPH_BASE + 0x2200U)

Definition at line 1162 of file stm32f745xx.h.

#define ADC3_BASE   (APB2PERIPH_BASE + 0x2200U)

Definition at line 1211 of file stm32f746xx.h.

#define ADC3_BASE   (APB2PERIPH_BASE + 0x2200U)

Definition at line 1280 of file stm32f756xx.h.

#define ADC3_BASE   (APB2PERIPH_BASE + 0x2200U)

Definition at line 1290 of file stm32f765xx.h.

#define ADC3_BASE   (APB2PERIPH_BASE + 0x2200U)

Definition at line 1376 of file stm32f767xx.h.

#define ADC3_BASE   (APB2PERIPH_BASE + 0x2200U)

Definition at line 1445 of file stm32f777xx.h.

#define ADC3_BASE   (APB2PERIPH_BASE + 0x2200U)

Definition at line 1457 of file stm32f769xx.h.

#define ADC3_BASE   (APB2PERIPH_BASE + 0x2200U)

Definition at line 1526 of file stm32f779xx.h.

#define ADC_BASE   (APB2PERIPH_BASE + 0x2300U)

Definition at line 1163 of file stm32f745xx.h.

#define ADC_BASE   (APB2PERIPH_BASE + 0x2300U)

Definition at line 1212 of file stm32f746xx.h.

#define ADC_BASE   (APB2PERIPH_BASE + 0x2300U)

Definition at line 1281 of file stm32f756xx.h.

#define ADC_BASE   (APB2PERIPH_BASE + 0x2300U)

Definition at line 1291 of file stm32f765xx.h.

#define ADC_BASE   (APB2PERIPH_BASE + 0x2300U)

Definition at line 1377 of file stm32f767xx.h.

#define ADC_BASE   (APB2PERIPH_BASE + 0x2300U)

Definition at line 1446 of file stm32f777xx.h.

#define ADC_BASE   (APB2PERIPH_BASE + 0x2300U)

Definition at line 1458 of file stm32f769xx.h.

#define ADC_BASE   (APB2PERIPH_BASE + 0x2300U)

Definition at line 1527 of file stm32f779xx.h.

#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000U)

Definition at line 1119 of file stm32f745xx.h.

#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000U)

Definition at line 1168 of file stm32f746xx.h.

#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000U)

Definition at line 1237 of file stm32f756xx.h.

#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000U)

Definition at line 1245 of file stm32f765xx.h.

#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000U)

Definition at line 1331 of file stm32f767xx.h.

#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000U)

Definition at line 1400 of file stm32f777xx.h.

#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000U)

Definition at line 1412 of file stm32f769xx.h.

#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000U)

Definition at line 1481 of file stm32f779xx.h.

#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000U)

APB1 peripherals

Definition at line 1120 of file stm32f745xx.h.

#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000U)

APB1 peripherals

Definition at line 1169 of file stm32f746xx.h.

#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000U)

APB1 peripherals

Definition at line 1238 of file stm32f756xx.h.

#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000U)

APB1 peripherals

Definition at line 1246 of file stm32f765xx.h.

#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000U)

APB1 peripherals

Definition at line 1332 of file stm32f767xx.h.

#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000U)

APB1 peripherals

Definition at line 1401 of file stm32f777xx.h.

#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000U)

APB1 peripherals

Definition at line 1413 of file stm32f769xx.h.

#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000U)

APB1 peripherals

Definition at line 1482 of file stm32f779xx.h.

#define APB1PERIPH_BASE   PERIPH_BASE

Definition at line 1117 of file stm32f745xx.h.

#define APB1PERIPH_BASE   PERIPH_BASE

Definition at line 1166 of file stm32f746xx.h.

#define APB1PERIPH_BASE   PERIPH_BASE

Definition at line 1235 of file stm32f756xx.h.

#define APB1PERIPH_BASE   PERIPH_BASE

Definition at line 1243 of file stm32f765xx.h.

#define APB1PERIPH_BASE   PERIPH_BASE

Definition at line 1329 of file stm32f767xx.h.

#define APB1PERIPH_BASE   PERIPH_BASE

Definition at line 1398 of file stm32f777xx.h.

#define APB1PERIPH_BASE   PERIPH_BASE

Definition at line 1410 of file stm32f769xx.h.

#define APB1PERIPH_BASE   PERIPH_BASE

Definition at line 1479 of file stm32f779xx.h.

#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000U)

Definition at line 1118 of file stm32f745xx.h.

#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000U)

Definition at line 1167 of file stm32f746xx.h.

#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000U)

Definition at line 1236 of file stm32f756xx.h.

#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000U)

Definition at line 1244 of file stm32f765xx.h.

#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000U)

Definition at line 1330 of file stm32f767xx.h.

#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000U)

Definition at line 1399 of file stm32f777xx.h.

#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000U)

Definition at line 1411 of file stm32f769xx.h.

#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000U)

Definition at line 1480 of file stm32f779xx.h.

#define BKPSRAM_BASE   0x40024000U

Base address of : Backup SRAM(4 KB)

Definition at line 1105 of file stm32f745xx.h.

#define BKPSRAM_BASE   0x40024000U

Base address of : Backup SRAM(4 KB)

Definition at line 1154 of file stm32f746xx.h.

#define BKPSRAM_BASE   0x40024000U

Base address of : Backup SRAM(4 KB)

Definition at line 1223 of file stm32f756xx.h.

#define BKPSRAM_BASE   0x40024000U

Base address of : Backup SRAM(4 KB)

Definition at line 1231 of file stm32f765xx.h.

#define BKPSRAM_BASE   0x40024000U

Base address of : Backup SRAM(4 KB)

Definition at line 1317 of file stm32f767xx.h.

#define BKPSRAM_BASE   0x40024000U

Base address of : Backup SRAM(4 KB)

Definition at line 1386 of file stm32f777xx.h.

#define BKPSRAM_BASE   0x40024000U

Base address of : Backup SRAM(4 KB)

Definition at line 1398 of file stm32f769xx.h.

#define BKPSRAM_BASE   0x40024000U

Base address of : Backup SRAM(4 KB)

Definition at line 1467 of file stm32f779xx.h.

#define CAN1_BASE   (APB1PERIPH_BASE + 0x6400U)

Definition at line 1147 of file stm32f745xx.h.

#define CAN1_BASE   (APB1PERIPH_BASE + 0x6400U)

Definition at line 1196 of file stm32f746xx.h.

#define CAN1_BASE   (APB1PERIPH_BASE + 0x6400U)

Definition at line 1265 of file stm32f756xx.h.

#define CAN1_BASE   (APB1PERIPH_BASE + 0x6400U)

Definition at line 1274 of file stm32f765xx.h.

#define CAN1_BASE   (APB1PERIPH_BASE + 0x6400U)

Definition at line 1360 of file stm32f767xx.h.

#define CAN1_BASE   (APB1PERIPH_BASE + 0x6400U)

Definition at line 1429 of file stm32f777xx.h.

#define CAN1_BASE   (APB1PERIPH_BASE + 0x6400U)

Definition at line 1441 of file stm32f769xx.h.

#define CAN1_BASE   (APB1PERIPH_BASE + 0x6400U)

Definition at line 1510 of file stm32f779xx.h.

#define CAN2_BASE   (APB1PERIPH_BASE + 0x6800U)

Definition at line 1148 of file stm32f745xx.h.

#define CAN2_BASE   (APB1PERIPH_BASE + 0x6800U)

Definition at line 1197 of file stm32f746xx.h.

#define CAN2_BASE   (APB1PERIPH_BASE + 0x6800U)

Definition at line 1266 of file stm32f756xx.h.

#define CAN2_BASE   (APB1PERIPH_BASE + 0x6800U)

Definition at line 1275 of file stm32f765xx.h.

#define CAN2_BASE   (APB1PERIPH_BASE + 0x6800U)

Definition at line 1361 of file stm32f767xx.h.

#define CAN2_BASE   (APB1PERIPH_BASE + 0x6800U)

Definition at line 1430 of file stm32f777xx.h.

#define CAN2_BASE   (APB1PERIPH_BASE + 0x6800U)

Definition at line 1442 of file stm32f769xx.h.

#define CAN2_BASE   (APB1PERIPH_BASE + 0x6800U)

Definition at line 1511 of file stm32f779xx.h.

#define CAN3_BASE   (APB1PERIPH_BASE + 0x3400U)

Definition at line 1262 of file stm32f765xx.h.

#define CAN3_BASE   (APB1PERIPH_BASE + 0x3400U)

Definition at line 1348 of file stm32f767xx.h.

#define CAN3_BASE   (APB1PERIPH_BASE + 0x3400U)

Definition at line 1417 of file stm32f777xx.h.

#define CAN3_BASE   (APB1PERIPH_BASE + 0x3400U)

Definition at line 1429 of file stm32f769xx.h.

#define CAN3_BASE   (APB1PERIPH_BASE + 0x3400U)

Definition at line 1498 of file stm32f779xx.h.

#define CEC_BASE   (APB1PERIPH_BASE + 0x6C00U)

Definition at line 1149 of file stm32f745xx.h.

#define CEC_BASE   (APB1PERIPH_BASE + 0x6C00U)

Definition at line 1198 of file stm32f746xx.h.

#define CEC_BASE   (APB1PERIPH_BASE + 0x6C00U)

Definition at line 1267 of file stm32f756xx.h.

#define CEC_BASE   (APB1PERIPH_BASE + 0x6C00U)

Definition at line 1276 of file stm32f765xx.h.

#define CEC_BASE   (APB1PERIPH_BASE + 0x6C00U)

Definition at line 1362 of file stm32f767xx.h.

#define CEC_BASE   (APB1PERIPH_BASE + 0x6C00U)

Definition at line 1431 of file stm32f777xx.h.

#define CEC_BASE   (APB1PERIPH_BASE + 0x6C00U)

Definition at line 1443 of file stm32f769xx.h.

#define CEC_BASE   (APB1PERIPH_BASE + 0x6C00U)

Definition at line 1512 of file stm32f779xx.h.

#define CRC_BASE   (AHB1PERIPH_BASE + 0x3000U)

Definition at line 1192 of file stm32f745xx.h.

#define CRC_BASE   (AHB1PERIPH_BASE + 0x3000U)

Definition at line 1244 of file stm32f746xx.h.

#define CRC_BASE   (AHB1PERIPH_BASE + 0x3000U)

Definition at line 1313 of file stm32f756xx.h.

#define CRC_BASE   (AHB1PERIPH_BASE + 0x3000U)

Definition at line 1334 of file stm32f765xx.h.

#define CRC_BASE   (AHB1PERIPH_BASE + 0x3000U)

Definition at line 1423 of file stm32f767xx.h.

#define CRC_BASE   (AHB1PERIPH_BASE + 0x3000U)

Definition at line 1492 of file stm32f777xx.h.

#define CRC_BASE   (AHB1PERIPH_BASE + 0x3000U)

Definition at line 1505 of file stm32f769xx.h.

#define CRC_BASE   (AHB1PERIPH_BASE + 0x3000U)

Definition at line 1574 of file stm32f779xx.h.

#define CRYP_BASE   (AHB2PERIPH_BASE + 0x60000U)

Definition at line 1345 of file stm32f756xx.h.

#define CRYP_BASE   (AHB2PERIPH_BASE + 0x60000U)

Definition at line 1525 of file stm32f777xx.h.

#define CRYP_BASE   (AHB2PERIPH_BASE + 0x60000U)

Definition at line 1607 of file stm32f779xx.h.

#define DAC_BASE   (APB1PERIPH_BASE + 0x7400U)

Definition at line 1151 of file stm32f745xx.h.

#define DAC_BASE   (APB1PERIPH_BASE + 0x7400U)

Definition at line 1200 of file stm32f746xx.h.

#define DAC_BASE   (APB1PERIPH_BASE + 0x7400U)

Definition at line 1269 of file stm32f756xx.h.

#define DAC_BASE   (APB1PERIPH_BASE + 0x7400U)

Definition at line 1278 of file stm32f765xx.h.

#define DAC_BASE   (APB1PERIPH_BASE + 0x7400U)

Definition at line 1364 of file stm32f767xx.h.

#define DAC_BASE   (APB1PERIPH_BASE + 0x7400U)

Definition at line 1433 of file stm32f777xx.h.

#define DAC_BASE   (APB1PERIPH_BASE + 0x7400U)

Definition at line 1445 of file stm32f769xx.h.

#define DAC_BASE   (APB1PERIPH_BASE + 0x7400U)

Definition at line 1514 of file stm32f779xx.h.

#define DBGMCU_BASE   0xE0042000U

USB registers base address

Definition at line 1232 of file stm32f745xx.h.

#define DBGMCU_BASE   0xE0042000U

USB registers base address

Definition at line 1284 of file stm32f746xx.h.

#define DBGMCU_BASE   0xE0042000U

USB registers base address

Definition at line 1356 of file stm32f756xx.h.

#define DBGMCU_BASE   0xE0042000U

USB registers base address

Definition at line 1374 of file stm32f765xx.h.

#define DBGMCU_BASE   0xE0042000U

USB registers base address

Definition at line 1464 of file stm32f767xx.h.

#define DBGMCU_BASE   0xE0042000U

USB registers base address

Definition at line 1536 of file stm32f777xx.h.

#define DBGMCU_BASE   0xE0042000U

USB registers base address

Definition at line 1546 of file stm32f769xx.h.

#define DBGMCU_BASE   0xE0042000U

USB registers base address

Definition at line 1618 of file stm32f779xx.h.

#define DCMI_BASE   (AHB2PERIPH_BASE + 0x50000U)

Definition at line 1223 of file stm32f745xx.h.

#define DCMI_BASE   (AHB2PERIPH_BASE + 0x50000U)

Definition at line 1275 of file stm32f746xx.h.

#define DCMI_BASE   (AHB2PERIPH_BASE + 0x50000U)

Definition at line 1344 of file stm32f756xx.h.

#define DCMI_BASE   (AHB2PERIPH_BASE + 0x50000U)

Definition at line 1365 of file stm32f765xx.h.

#define DCMI_BASE   (AHB2PERIPH_BASE + 0x50000U)

Definition at line 1454 of file stm32f767xx.h.

#define DCMI_BASE   (AHB2PERIPH_BASE + 0x50000U)

Definition at line 1523 of file stm32f777xx.h.

#define DCMI_BASE   (AHB2PERIPH_BASE + 0x50000U)

Definition at line 1536 of file stm32f769xx.h.

#define DCMI_BASE   (AHB2PERIPH_BASE + 0x50000U)

Definition at line 1605 of file stm32f779xx.h.

#define DFSDM1_BASE   (APB2PERIPH_BASE + 0x7400U)

Definition at line 1308 of file stm32f765xx.h.

#define DFSDM1_BASE   (APB2PERIPH_BASE + 0x7400U)

Definition at line 1397 of file stm32f767xx.h.

#define DFSDM1_BASE   (APB2PERIPH_BASE + 0x7400U)

Definition at line 1466 of file stm32f777xx.h.

#define DFSDM1_BASE   (APB2PERIPH_BASE + 0x7400U)

Definition at line 1479 of file stm32f769xx.h.

#define DFSDM1_BASE   (APB2PERIPH_BASE + 0x7400U)

Definition at line 1548 of file stm32f779xx.h.

#define DFSDM1_Channel0_BASE   (DFSDM1_BASE + 0x00U)

Definition at line 1309 of file stm32f765xx.h.

#define DFSDM1_Channel0_BASE   (DFSDM1_BASE + 0x00U)

Definition at line 1398 of file stm32f767xx.h.

#define DFSDM1_Channel0_BASE   (DFSDM1_BASE + 0x00U)

Definition at line 1467 of file stm32f777xx.h.

#define DFSDM1_Channel0_BASE   (DFSDM1_BASE + 0x00U)

Definition at line 1480 of file stm32f769xx.h.

#define DFSDM1_Channel0_BASE   (DFSDM1_BASE + 0x00U)

Definition at line 1549 of file stm32f779xx.h.

#define DFSDM1_Channel1_BASE   (DFSDM1_BASE + 0x20U)

Definition at line 1310 of file stm32f765xx.h.

#define DFSDM1_Channel1_BASE   (DFSDM1_BASE + 0x20U)

Definition at line 1399 of file stm32f767xx.h.

#define DFSDM1_Channel1_BASE   (DFSDM1_BASE + 0x20U)

Definition at line 1468 of file stm32f777xx.h.

#define DFSDM1_Channel1_BASE   (DFSDM1_BASE + 0x20U)

Definition at line 1481 of file stm32f769xx.h.

#define DFSDM1_Channel1_BASE   (DFSDM1_BASE + 0x20U)

Definition at line 1550 of file stm32f779xx.h.

#define DFSDM1_Channel2_BASE   (DFSDM1_BASE + 0x40U)

Definition at line 1311 of file stm32f765xx.h.

#define DFSDM1_Channel2_BASE   (DFSDM1_BASE + 0x40U)

Definition at line 1400 of file stm32f767xx.h.

#define DFSDM1_Channel2_BASE   (DFSDM1_BASE + 0x40U)

Definition at line 1469 of file stm32f777xx.h.

#define DFSDM1_Channel2_BASE   (DFSDM1_BASE + 0x40U)

Definition at line 1482 of file stm32f769xx.h.

#define DFSDM1_Channel2_BASE   (DFSDM1_BASE + 0x40U)

Definition at line 1551 of file stm32f779xx.h.

#define DFSDM1_Channel3_BASE   (DFSDM1_BASE + 0x60U)

Definition at line 1312 of file stm32f765xx.h.

#define DFSDM1_Channel3_BASE   (DFSDM1_BASE + 0x60U)

Definition at line 1401 of file stm32f767xx.h.

#define DFSDM1_Channel3_BASE   (DFSDM1_BASE + 0x60U)

Definition at line 1470 of file stm32f777xx.h.

#define DFSDM1_Channel3_BASE   (DFSDM1_BASE + 0x60U)

Definition at line 1483 of file stm32f769xx.h.

#define DFSDM1_Channel3_BASE   (DFSDM1_BASE + 0x60U)

Definition at line 1552 of file stm32f779xx.h.

#define DFSDM1_Channel4_BASE   (DFSDM1_BASE + 0x80U)

Definition at line 1313 of file stm32f765xx.h.

#define DFSDM1_Channel4_BASE   (DFSDM1_BASE + 0x80U)

Definition at line 1402 of file stm32f767xx.h.

#define DFSDM1_Channel4_BASE   (DFSDM1_BASE + 0x80U)

Definition at line 1471 of file stm32f777xx.h.

#define DFSDM1_Channel4_BASE   (DFSDM1_BASE + 0x80U)

Definition at line 1484 of file stm32f769xx.h.

#define DFSDM1_Channel4_BASE   (DFSDM1_BASE + 0x80U)

Definition at line 1553 of file stm32f779xx.h.

#define DFSDM1_Channel5_BASE   (DFSDM1_BASE + 0xA0U)

Definition at line 1314 of file stm32f765xx.h.

#define DFSDM1_Channel5_BASE   (DFSDM1_BASE + 0xA0U)

Definition at line 1403 of file stm32f767xx.h.

#define DFSDM1_Channel5_BASE   (DFSDM1_BASE + 0xA0U)

Definition at line 1472 of file stm32f777xx.h.

#define DFSDM1_Channel5_BASE   (DFSDM1_BASE + 0xA0U)

Definition at line 1485 of file stm32f769xx.h.

#define DFSDM1_Channel5_BASE   (DFSDM1_BASE + 0xA0U)

Definition at line 1554 of file stm32f779xx.h.

#define DFSDM1_Channel6_BASE   (DFSDM1_BASE + 0xC0U)

Definition at line 1315 of file stm32f765xx.h.

#define DFSDM1_Channel6_BASE   (DFSDM1_BASE + 0xC0U)

Definition at line 1404 of file stm32f767xx.h.

#define DFSDM1_Channel6_BASE   (DFSDM1_BASE + 0xC0U)

Definition at line 1473 of file stm32f777xx.h.

#define DFSDM1_Channel6_BASE   (DFSDM1_BASE + 0xC0U)

Definition at line 1486 of file stm32f769xx.h.

#define DFSDM1_Channel6_BASE   (DFSDM1_BASE + 0xC0U)

Definition at line 1555 of file stm32f779xx.h.

#define DFSDM1_Channel7_BASE   (DFSDM1_BASE + 0xE0U)

Definition at line 1316 of file stm32f765xx.h.

#define DFSDM1_Channel7_BASE   (DFSDM1_BASE + 0xE0U)

Definition at line 1405 of file stm32f767xx.h.

#define DFSDM1_Channel7_BASE   (DFSDM1_BASE + 0xE0U)

Definition at line 1474 of file stm32f777xx.h.

#define DFSDM1_Channel7_BASE   (DFSDM1_BASE + 0xE0U)

Definition at line 1487 of file stm32f769xx.h.

#define DFSDM1_Channel7_BASE   (DFSDM1_BASE + 0xE0U)

Definition at line 1556 of file stm32f779xx.h.

#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100U)

Definition at line 1317 of file stm32f765xx.h.

#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100U)

Definition at line 1406 of file stm32f767xx.h.

#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100U)

Definition at line 1475 of file stm32f777xx.h.

#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100U)

Definition at line 1488 of file stm32f769xx.h.

#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100U)

Definition at line 1557 of file stm32f779xx.h.

#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180U)

Definition at line 1318 of file stm32f765xx.h.

#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180U)

Definition at line 1407 of file stm32f767xx.h.

#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180U)

Definition at line 1476 of file stm32f777xx.h.

#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180U)

Definition at line 1489 of file stm32f769xx.h.

#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180U)

Definition at line 1558 of file stm32f779xx.h.

#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200U)

Definition at line 1319 of file stm32f765xx.h.

#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200U)

Definition at line 1408 of file stm32f767xx.h.

#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200U)

Definition at line 1477 of file stm32f777xx.h.

#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200U)

Definition at line 1490 of file stm32f769xx.h.

#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200U)

Definition at line 1559 of file stm32f779xx.h.

#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280U)

Definition at line 1320 of file stm32f765xx.h.

#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280U)

Definition at line 1409 of file stm32f767xx.h.

#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280U)

Definition at line 1478 of file stm32f777xx.h.

#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280U)

Definition at line 1491 of file stm32f769xx.h.

#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280U)

Definition at line 1560 of file stm32f779xx.h.

#define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000U)

Definition at line 1198 of file stm32f745xx.h.

#define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000U)

Definition at line 1250 of file stm32f746xx.h.

#define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000U)

Definition at line 1319 of file stm32f756xx.h.

#define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000U)

Definition at line 1340 of file stm32f765xx.h.

#define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000U)

Definition at line 1429 of file stm32f767xx.h.

#define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000U)

Definition at line 1498 of file stm32f777xx.h.

#define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000U)

Definition at line 1511 of file stm32f769xx.h.

#define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000U)

Definition at line 1580 of file stm32f779xx.h.

#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010U)

Definition at line 1199 of file stm32f745xx.h.

#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010U)

Definition at line 1251 of file stm32f746xx.h.

#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010U)

Definition at line 1320 of file stm32f756xx.h.

#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010U)

Definition at line 1341 of file stm32f765xx.h.

#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010U)

Definition at line 1430 of file stm32f767xx.h.

#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010U)

Definition at line 1499 of file stm32f777xx.h.

#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010U)

Definition at line 1512 of file stm32f769xx.h.

#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010U)

Definition at line 1581 of file stm32f779xx.h.

#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028U)

Definition at line 1200 of file stm32f745xx.h.

#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028U)

Definition at line 1252 of file stm32f746xx.h.

#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028U)

Definition at line 1321 of file stm32f756xx.h.

#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028U)

Definition at line 1342 of file stm32f765xx.h.

#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028U)

Definition at line 1431 of file stm32f767xx.h.

#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028U)

Definition at line 1500 of file stm32f777xx.h.

#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028U)

Definition at line 1513 of file stm32f769xx.h.

#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028U)

Definition at line 1582 of file stm32f779xx.h.

#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040U)

Definition at line 1201 of file stm32f745xx.h.

#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040U)

Definition at line 1253 of file stm32f746xx.h.

#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040U)

Definition at line 1322 of file stm32f756xx.h.

#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040U)

Definition at line 1343 of file stm32f765xx.h.

#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040U)

Definition at line 1432 of file stm32f767xx.h.

#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040U)

Definition at line 1501 of file stm32f777xx.h.

#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040U)

Definition at line 1514 of file stm32f769xx.h.

#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040U)

Definition at line 1583 of file stm32f779xx.h.

#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058U)

Definition at line 1202 of file stm32f745xx.h.

#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058U)

Definition at line 1254 of file stm32f746xx.h.

#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058U)

Definition at line 1323 of file stm32f756xx.h.

#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058U)

Definition at line 1344 of file stm32f765xx.h.

#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058U)

Definition at line 1433 of file stm32f767xx.h.

#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058U)

Definition at line 1502 of file stm32f777xx.h.

#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058U)

Definition at line 1515 of file stm32f769xx.h.

#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058U)

Definition at line 1584 of file stm32f779xx.h.

#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070U)

Definition at line 1203 of file stm32f745xx.h.

#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070U)

Definition at line 1255 of file stm32f746xx.h.

#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070U)

Definition at line 1324 of file stm32f756xx.h.

#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070U)

Definition at line 1345 of file stm32f765xx.h.

#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070U)

Definition at line 1434 of file stm32f767xx.h.

#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070U)

Definition at line 1503 of file stm32f777xx.h.

#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070U)

Definition at line 1516 of file stm32f769xx.h.

#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070U)

Definition at line 1585 of file stm32f779xx.h.

#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088U)

Definition at line 1204 of file stm32f745xx.h.

#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088U)

Definition at line 1256 of file stm32f746xx.h.

#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088U)

Definition at line 1325 of file stm32f756xx.h.

#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088U)

Definition at line 1346 of file stm32f765xx.h.

#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088U)

Definition at line 1435 of file stm32f767xx.h.

#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088U)

Definition at line 1504 of file stm32f777xx.h.

#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088U)

Definition at line 1517 of file stm32f769xx.h.

#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088U)

Definition at line 1586 of file stm32f779xx.h.

#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0U)

Definition at line 1205 of file stm32f745xx.h.

#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0U)

Definition at line 1257 of file stm32f746xx.h.

#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0U)

Definition at line 1326 of file stm32f756xx.h.

#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0U)

Definition at line 1347 of file stm32f765xx.h.

#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0U)

Definition at line 1436 of file stm32f767xx.h.

#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0U)

Definition at line 1505 of file stm32f777xx.h.

#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0U)

Definition at line 1518 of file stm32f769xx.h.

#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0U)

Definition at line 1587 of file stm32f779xx.h.

#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8U)

Definition at line 1206 of file stm32f745xx.h.

#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8U)

Definition at line 1258 of file stm32f746xx.h.

#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8U)

Definition at line 1327 of file stm32f756xx.h.

#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8U)

Definition at line 1348 of file stm32f765xx.h.

#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8U)

Definition at line 1437 of file stm32f767xx.h.

#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8U)

Definition at line 1506 of file stm32f777xx.h.

#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8U)

Definition at line 1519 of file stm32f769xx.h.

#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8U)

Definition at line 1588 of file stm32f779xx.h.

#define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400U)

Definition at line 1207 of file stm32f745xx.h.

#define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400U)

Definition at line 1259 of file stm32f746xx.h.

#define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400U)

Definition at line 1328 of file stm32f756xx.h.

#define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400U)

Definition at line 1349 of file stm32f765xx.h.

#define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400U)

Definition at line 1438 of file stm32f767xx.h.

#define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400U)

Definition at line 1507 of file stm32f777xx.h.

#define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400U)

Definition at line 1520 of file stm32f769xx.h.

#define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400U)

Definition at line 1589 of file stm32f779xx.h.

#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010U)

Definition at line 1208 of file stm32f745xx.h.

#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010U)

Definition at line 1260 of file stm32f746xx.h.

#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010U)

Definition at line 1329 of file stm32f756xx.h.

#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010U)

Definition at line 1350 of file stm32f765xx.h.

#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010U)

Definition at line 1439 of file stm32f767xx.h.

#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010U)

Definition at line 1508 of file stm32f777xx.h.

#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010U)

Definition at line 1521 of file stm32f769xx.h.

#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010U)

Definition at line 1590 of file stm32f779xx.h.

#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028U)

Definition at line 1209 of file stm32f745xx.h.

#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028U)

Definition at line 1261 of file stm32f746xx.h.

#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028U)

Definition at line 1330 of file stm32f756xx.h.

#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028U)

Definition at line 1351 of file stm32f765xx.h.

#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028U)

Definition at line 1440 of file stm32f767xx.h.

#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028U)

Definition at line 1509 of file stm32f777xx.h.

#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028U)

Definition at line 1522 of file stm32f769xx.h.

#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028U)

Definition at line 1591 of file stm32f779xx.h.

#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040U)

Definition at line 1210 of file stm32f745xx.h.

#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040U)

Definition at line 1262 of file stm32f746xx.h.

#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040U)

Definition at line 1331 of file stm32f756xx.h.

#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040U)

Definition at line 1352 of file stm32f765xx.h.

#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040U)

Definition at line 1441 of file stm32f767xx.h.

#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040U)

Definition at line 1510 of file stm32f777xx.h.

#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040U)

Definition at line 1523 of file stm32f769xx.h.

#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040U)

Definition at line 1592 of file stm32f779xx.h.

#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058U)

Definition at line 1211 of file stm32f745xx.h.

#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058U)

Definition at line 1263 of file stm32f746xx.h.

#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058U)

Definition at line 1332 of file stm32f756xx.h.

#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058U)

Definition at line 1353 of file stm32f765xx.h.

#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058U)

Definition at line 1442 of file stm32f767xx.h.

#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058U)

Definition at line 1511 of file stm32f777xx.h.

#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058U)

Definition at line 1524 of file stm32f769xx.h.

#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058U)

Definition at line 1593 of file stm32f779xx.h.

#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070U)

Definition at line 1212 of file stm32f745xx.h.

#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070U)

Definition at line 1264 of file stm32f746xx.h.

#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070U)

Definition at line 1333 of file stm32f756xx.h.

#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070U)

Definition at line 1354 of file stm32f765xx.h.

#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070U)

Definition at line 1443 of file stm32f767xx.h.

#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070U)

Definition at line 1512 of file stm32f777xx.h.

#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070U)

Definition at line 1525 of file stm32f769xx.h.

#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070U)

Definition at line 1594 of file stm32f779xx.h.

#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088U)

Definition at line 1213 of file stm32f745xx.h.

#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088U)

Definition at line 1265 of file stm32f746xx.h.

#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088U)

Definition at line 1334 of file stm32f756xx.h.

#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088U)

Definition at line 1355 of file stm32f765xx.h.

#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088U)

Definition at line 1444 of file stm32f767xx.h.

#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088U)

Definition at line 1513 of file stm32f777xx.h.

#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088U)

Definition at line 1526 of file stm32f769xx.h.

#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088U)

Definition at line 1595 of file stm32f779xx.h.

#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0U)

Definition at line 1214 of file stm32f745xx.h.

#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0U)

Definition at line 1266 of file stm32f746xx.h.

#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0U)

Definition at line 1335 of file stm32f756xx.h.

#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0U)

Definition at line 1356 of file stm32f765xx.h.

#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0U)

Definition at line 1445 of file stm32f767xx.h.

#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0U)

Definition at line 1514 of file stm32f777xx.h.

#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0U)

Definition at line 1527 of file stm32f769xx.h.

#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0U)

Definition at line 1596 of file stm32f779xx.h.

#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8U)

Definition at line 1215 of file stm32f745xx.h.

#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8U)

Definition at line 1267 of file stm32f746xx.h.

#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8U)

Definition at line 1336 of file stm32f756xx.h.

#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8U)

Definition at line 1357 of file stm32f765xx.h.

#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8U)

Definition at line 1446 of file stm32f767xx.h.

#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8U)

Definition at line 1515 of file stm32f777xx.h.

#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8U)

Definition at line 1528 of file stm32f769xx.h.

#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8U)

Definition at line 1597 of file stm32f779xx.h.

#define DMA2D_BASE   (AHB1PERIPH_BASE + 0xB000U)

AHB2 peripherals

Definition at line 1221 of file stm32f745xx.h.

#define DMA2D_BASE   (AHB1PERIPH_BASE + 0xB000U)

AHB2 peripherals

Definition at line 1273 of file stm32f746xx.h.

#define DMA2D_BASE   (AHB1PERIPH_BASE + 0xB000U)

AHB2 peripherals

Definition at line 1342 of file stm32f756xx.h.

#define DMA2D_BASE   (AHB1PERIPH_BASE + 0xB000U)

AHB2 peripherals

Definition at line 1363 of file stm32f765xx.h.

#define DMA2D_BASE   (AHB1PERIPH_BASE + 0xB000U)

AHB2 peripherals

Definition at line 1452 of file stm32f767xx.h.

#define DMA2D_BASE   (AHB1PERIPH_BASE + 0xB000U)

AHB2 peripherals

Definition at line 1521 of file stm32f777xx.h.

#define DMA2D_BASE   (AHB1PERIPH_BASE + 0xB000U)

AHB2 peripherals

Definition at line 1534 of file stm32f769xx.h.

#define DMA2D_BASE   (AHB1PERIPH_BASE + 0xB000U)

AHB2 peripherals

Definition at line 1603 of file stm32f779xx.h.

#define DSI_BASE   (APB2PERIPH_BASE + 0x6C00U)

Definition at line 1478 of file stm32f769xx.h.

#define DSI_BASE   (APB2PERIPH_BASE + 0x6C00U)

Definition at line 1547 of file stm32f779xx.h.

#define ETH_BASE   (AHB1PERIPH_BASE + 0x8000U)

Definition at line 1216 of file stm32f745xx.h.

#define ETH_BASE   (AHB1PERIPH_BASE + 0x8000U)

Definition at line 1268 of file stm32f746xx.h.

#define ETH_BASE   (AHB1PERIPH_BASE + 0x8000U)

Definition at line 1337 of file stm32f756xx.h.

#define ETH_BASE   (AHB1PERIPH_BASE + 0x8000U)

Definition at line 1358 of file stm32f765xx.h.

#define ETH_BASE   (AHB1PERIPH_BASE + 0x8000U)

Definition at line 1447 of file stm32f767xx.h.

#define ETH_BASE   (AHB1PERIPH_BASE + 0x8000U)

Definition at line 1516 of file stm32f777xx.h.

#define ETH_BASE   (AHB1PERIPH_BASE + 0x8000U)

Definition at line 1529 of file stm32f769xx.h.

#define ETH_BASE   (AHB1PERIPH_BASE + 0x8000U)

Definition at line 1598 of file stm32f779xx.h.

#define ETH_DMA_BASE   (ETH_BASE + 0x1000U)

Definition at line 1220 of file stm32f745xx.h.

#define ETH_DMA_BASE   (ETH_BASE + 0x1000U)

Definition at line 1272 of file stm32f746xx.h.

#define ETH_DMA_BASE   (ETH_BASE + 0x1000U)

Definition at line 1341 of file stm32f756xx.h.

#define ETH_DMA_BASE   (ETH_BASE + 0x1000U)

Definition at line 1362 of file stm32f765xx.h.

#define ETH_DMA_BASE   (ETH_BASE + 0x1000U)

Definition at line 1451 of file stm32f767xx.h.

#define ETH_DMA_BASE   (ETH_BASE + 0x1000U)

Definition at line 1520 of file stm32f777xx.h.

#define ETH_DMA_BASE   (ETH_BASE + 0x1000U)

Definition at line 1533 of file stm32f769xx.h.

#define ETH_DMA_BASE   (ETH_BASE + 0x1000U)

Definition at line 1602 of file stm32f779xx.h.

#define ETH_MAC_BASE   (ETH_BASE)

Definition at line 1217 of file stm32f745xx.h.

#define ETH_MAC_BASE   (ETH_BASE)

Definition at line 1269 of file stm32f746xx.h.

#define ETH_MAC_BASE   (ETH_BASE)

Definition at line 1338 of file stm32f756xx.h.

#define ETH_MAC_BASE   (ETH_BASE)

Definition at line 1359 of file stm32f765xx.h.

#define ETH_MAC_BASE   (ETH_BASE)

Definition at line 1448 of file stm32f767xx.h.

#define ETH_MAC_BASE   (ETH_BASE)

Definition at line 1517 of file stm32f777xx.h.

#define ETH_MAC_BASE   (ETH_BASE)

Definition at line 1530 of file stm32f769xx.h.

#define ETH_MAC_BASE   (ETH_BASE)

Definition at line 1599 of file stm32f779xx.h.

#define ETH_MMC_BASE   (ETH_BASE + 0x0100U)

Definition at line 1218 of file stm32f745xx.h.

#define ETH_MMC_BASE   (ETH_BASE + 0x0100U)

Definition at line 1270 of file stm32f746xx.h.

#define ETH_MMC_BASE   (ETH_BASE + 0x0100U)

Definition at line 1339 of file stm32f756xx.h.

#define ETH_MMC_BASE   (ETH_BASE + 0x0100U)

Definition at line 1360 of file stm32f765xx.h.

#define ETH_MMC_BASE   (ETH_BASE + 0x0100U)

Definition at line 1449 of file stm32f767xx.h.

#define ETH_MMC_BASE   (ETH_BASE + 0x0100U)

Definition at line 1518 of file stm32f777xx.h.

#define ETH_MMC_BASE   (ETH_BASE + 0x0100U)

Definition at line 1531 of file stm32f769xx.h.

#define ETH_MMC_BASE   (ETH_BASE + 0x0100U)

Definition at line 1600 of file stm32f779xx.h.

#define ETH_PTP_BASE   (ETH_BASE + 0x0700U)

Definition at line 1219 of file stm32f745xx.h.

#define ETH_PTP_BASE   (ETH_BASE + 0x0700U)

Definition at line 1271 of file stm32f746xx.h.

#define ETH_PTP_BASE   (ETH_BASE + 0x0700U)

Definition at line 1340 of file stm32f756xx.h.

#define ETH_PTP_BASE   (ETH_BASE + 0x0700U)

Definition at line 1361 of file stm32f765xx.h.

#define ETH_PTP_BASE   (ETH_BASE + 0x0700U)

Definition at line 1450 of file stm32f767xx.h.

#define ETH_PTP_BASE   (ETH_BASE + 0x0700U)

Definition at line 1519 of file stm32f777xx.h.

#define ETH_PTP_BASE   (ETH_BASE + 0x0700U)

Definition at line 1532 of file stm32f769xx.h.

#define ETH_PTP_BASE   (ETH_BASE + 0x0700U)

Definition at line 1601 of file stm32f779xx.h.

#define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00U)

Definition at line 1168 of file stm32f745xx.h.

#define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00U)

Definition at line 1217 of file stm32f746xx.h.

#define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00U)

Definition at line 1286 of file stm32f756xx.h.

#define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00U)

Definition at line 1296 of file stm32f765xx.h.

#define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00U)

Definition at line 1382 of file stm32f767xx.h.

#define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00U)

Definition at line 1451 of file stm32f777xx.h.

#define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00U)

Definition at line 1463 of file stm32f769xx.h.

#define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00U)

Definition at line 1532 of file stm32f779xx.h.

#define FLASH_BASE   FLASHAXI_BASE

Peripheral memory map

Definition at line 1114 of file stm32f745xx.h.

#define FLASH_BASE   FLASHAXI_BASE

Peripheral memory map

Definition at line 1163 of file stm32f746xx.h.

#define FLASH_BASE   FLASHAXI_BASE

Peripheral memory map

Definition at line 1232 of file stm32f756xx.h.

#define FLASH_BASE   FLASHAXI_BASE

Peripheral memory map

Definition at line 1240 of file stm32f765xx.h.

#define FLASH_BASE   FLASHAXI_BASE

Peripheral memory map

Definition at line 1326 of file stm32f767xx.h.

#define FLASH_BASE   FLASHAXI_BASE

Peripheral memory map

Definition at line 1395 of file stm32f777xx.h.

#define FLASH_BASE   FLASHAXI_BASE

Peripheral memory map

Definition at line 1407 of file stm32f769xx.h.

#define FLASH_BASE   FLASHAXI_BASE

Peripheral memory map

Definition at line 1476 of file stm32f779xx.h.

#define FLASH_END   0x080FFFFFU

FLASH end address

Definition at line 1111 of file stm32f745xx.h.

#define FLASH_END   0x080FFFFFU

FLASH end address

Definition at line 1160 of file stm32f746xx.h.

#define FLASH_END   0x080FFFFFU

FLASH end address

Definition at line 1229 of file stm32f756xx.h.

#define FLASH_END   0x081FFFFFU

FLASH end address

Definition at line 1237 of file stm32f765xx.h.

#define FLASH_END   0x081FFFFFU

FLASH end address

Definition at line 1323 of file stm32f767xx.h.

#define FLASH_END   0x081FFFFFU

FLASH end address

Definition at line 1392 of file stm32f777xx.h.

#define FLASH_END   0x081FFFFFU

FLASH end address

Definition at line 1404 of file stm32f769xx.h.

#define FLASH_END   0x081FFFFFU

FLASH end address

Definition at line 1473 of file stm32f779xx.h.

#define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00U)

Definition at line 1194 of file stm32f745xx.h.

#define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00U)

Definition at line 1246 of file stm32f746xx.h.

#define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00U)

Definition at line 1315 of file stm32f756xx.h.

#define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00U)

Definition at line 1336 of file stm32f765xx.h.

#define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00U)

Definition at line 1425 of file stm32f767xx.h.

#define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00U)

Definition at line 1494 of file stm32f777xx.h.

#define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00U)

Definition at line 1507 of file stm32f769xx.h.

#define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00U)

Definition at line 1576 of file stm32f779xx.h.

#define FLASHAXI_BASE   0x08000000U

Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI

Definition at line 1102 of file stm32f745xx.h.

#define FLASHAXI_BASE   0x08000000U

Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI

Definition at line 1151 of file stm32f746xx.h.

#define FLASHAXI_BASE   0x08000000U

Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI

Definition at line 1220 of file stm32f756xx.h.

#define FLASHAXI_BASE   0x08000000U

Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI

Definition at line 1228 of file stm32f765xx.h.

#define FLASHAXI_BASE   0x08000000U

Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI

Definition at line 1314 of file stm32f767xx.h.

#define FLASHAXI_BASE   0x08000000U

Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI

Definition at line 1383 of file stm32f777xx.h.

#define FLASHAXI_BASE   0x08000000U

Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI

Definition at line 1395 of file stm32f769xx.h.

#define FLASHAXI_BASE   0x08000000U

Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI

Definition at line 1464 of file stm32f779xx.h.

#define FLASHITCM_BASE   0x00200000U

Base address of : (up to 1 MB) embedded FLASH memory accessible over ITCM

Definition at line 1101 of file stm32f745xx.h.

#define FLASHITCM_BASE   0x00200000U

Base address of : (up to 1 MB) embedded FLASH memory accessible over ITCM

Definition at line 1150 of file stm32f746xx.h.

#define FLASHITCM_BASE   0x00200000U

Base address of : (up to 1 MB) embedded FLASH memory accessible over ITCM

Definition at line 1219 of file stm32f756xx.h.

#define FLASHITCM_BASE   0x00200000U

Base address of : (up to 2 MB) embedded FLASH memory accessible over ITCM

Definition at line 1227 of file stm32f765xx.h.

#define FLASHITCM_BASE   0x00200000U

Base address of : (up to 2 MB) embedded FLASH memory accessible over ITCM

Definition at line 1313 of file stm32f767xx.h.

#define FLASHITCM_BASE   0x00200000U

Base address of : (up to 2 MB) embedded FLASH memory accessible over ITCM

Definition at line 1382 of file stm32f777xx.h.

#define FLASHITCM_BASE   0x00200000U

Base address of : (up to 2 MB) embedded FLASH memory accessible over ITCM

Definition at line 1394 of file stm32f769xx.h.

#define FLASHITCM_BASE   0x00200000U

Base address of : (up to 2 MB) embedded FLASH memory accessible over ITCM

Definition at line 1463 of file stm32f779xx.h.

#define FLASHSIZE_BASE   0x1FF0F442U

FLASH Size register base address

Definition at line 1196 of file stm32f745xx.h.

#define FLASHSIZE_BASE   0x1FF0F442U

FLASH Size register base address

Definition at line 1248 of file stm32f746xx.h.

#define FLASHSIZE_BASE   0x1FF0F442U

FLASH Size register base address

Definition at line 1317 of file stm32f756xx.h.

#define FLASHSIZE_BASE   0x1FF0F442U

FLASH Size register base address

Definition at line 1338 of file stm32f765xx.h.

#define FLASHSIZE_BASE   0x1FF0F442U

FLASH Size register base address

Definition at line 1427 of file stm32f767xx.h.

#define FLASHSIZE_BASE   0x1FF0F442U

FLASH Size register base address

Definition at line 1496 of file stm32f777xx.h.

#define FLASHSIZE_BASE   0x1FF0F442U

FLASH Size register base address

Definition at line 1509 of file stm32f769xx.h.

#define FLASHSIZE_BASE   0x1FF0F442U

FLASH Size register base address

Definition at line 1578 of file stm32f779xx.h.

#define FMC_Bank1_R_BASE   (FMC_R_BASE + 0x0000U)

Definition at line 1226 of file stm32f745xx.h.

#define FMC_Bank1_R_BASE   (FMC_R_BASE + 0x0000U)

Definition at line 1278 of file stm32f746xx.h.

#define FMC_Bank1_R_BASE   (FMC_R_BASE + 0x0000U)

Definition at line 1350 of file stm32f756xx.h.

#define FMC_Bank1_R_BASE   (FMC_R_BASE + 0x0000U)

Definition at line 1368 of file stm32f765xx.h.

#define FMC_Bank1_R_BASE   (FMC_R_BASE + 0x0000U)

Definition at line 1458 of file stm32f767xx.h.

#define FMC_Bank1_R_BASE   (FMC_R_BASE + 0x0000U)

Definition at line 1530 of file stm32f777xx.h.

#define FMC_Bank1_R_BASE   (FMC_R_BASE + 0x0000U)

Definition at line 1540 of file stm32f769xx.h.

#define FMC_Bank1_R_BASE   (FMC_R_BASE + 0x0000U)

Definition at line 1612 of file stm32f779xx.h.

#define FMC_Bank1E_R_BASE   (FMC_R_BASE + 0x0104U)

Definition at line 1227 of file stm32f745xx.h.

#define FMC_Bank1E_R_BASE   (FMC_R_BASE + 0x0104U)

Definition at line 1279 of file stm32f746xx.h.

#define FMC_Bank1E_R_BASE   (FMC_R_BASE + 0x0104U)

Definition at line 1351 of file stm32f756xx.h.

#define FMC_Bank1E_R_BASE   (FMC_R_BASE + 0x0104U)

Definition at line 1369 of file stm32f765xx.h.

#define FMC_Bank1E_R_BASE   (FMC_R_BASE + 0x0104U)

Definition at line 1459 of file stm32f767xx.h.

#define FMC_Bank1E_R_BASE   (FMC_R_BASE + 0x0104U)

Definition at line 1531 of file stm32f777xx.h.

#define FMC_Bank1E_R_BASE   (FMC_R_BASE + 0x0104U)

Definition at line 1541 of file stm32f769xx.h.

#define FMC_Bank1E_R_BASE   (FMC_R_BASE + 0x0104U)

Definition at line 1613 of file stm32f779xx.h.

#define FMC_Bank3_R_BASE   (FMC_R_BASE + 0x0080U)

Definition at line 1228 of file stm32f745xx.h.

#define FMC_Bank3_R_BASE   (FMC_R_BASE + 0x0080U)

Definition at line 1280 of file stm32f746xx.h.

#define FMC_Bank3_R_BASE   (FMC_R_BASE + 0x0080U)

Definition at line 1352 of file stm32f756xx.h.

#define FMC_Bank3_R_BASE   (FMC_R_BASE + 0x0080U)

Definition at line 1370 of file stm32f765xx.h.

#define FMC_Bank3_R_BASE   (FMC_R_BASE + 0x0080U)

Definition at line 1460 of file stm32f767xx.h.

#define FMC_Bank3_R_BASE   (FMC_R_BASE + 0x0080U)

Definition at line 1532 of file stm32f777xx.h.

#define FMC_Bank3_R_BASE   (FMC_R_BASE + 0x0080U)

Definition at line 1542 of file stm32f769xx.h.

#define FMC_Bank3_R_BASE   (FMC_R_BASE + 0x0080U)

Definition at line 1614 of file stm32f779xx.h.

#define FMC_Bank5_6_R_BASE   (FMC_R_BASE + 0x0140U)

Definition at line 1229 of file stm32f745xx.h.

#define FMC_Bank5_6_R_BASE   (FMC_R_BASE + 0x0140U)

Definition at line 1281 of file stm32f746xx.h.

#define FMC_Bank5_6_R_BASE   (FMC_R_BASE + 0x0140U)

Definition at line 1353 of file stm32f756xx.h.

#define FMC_Bank5_6_R_BASE   (FMC_R_BASE + 0x0140U)

Definition at line 1371 of file stm32f765xx.h.

#define FMC_Bank5_6_R_BASE   (FMC_R_BASE + 0x0140U)

Definition at line 1461 of file stm32f767xx.h.

#define FMC_Bank5_6_R_BASE   (FMC_R_BASE + 0x0140U)

Definition at line 1533 of file stm32f777xx.h.

#define FMC_Bank5_6_R_BASE   (FMC_R_BASE + 0x0140U)

Definition at line 1543 of file stm32f769xx.h.

#define FMC_Bank5_6_R_BASE   (FMC_R_BASE + 0x0140U)

Definition at line 1615 of file stm32f779xx.h.

#define FMC_R_BASE   0xA0000000U

Base address of : FMC Control registers

Definition at line 1107 of file stm32f745xx.h.

#define FMC_R_BASE   0xA0000000U

Base address of : FMC Control registers

Definition at line 1156 of file stm32f746xx.h.

#define FMC_R_BASE   0xA0000000U

Base address of : FMC Control registers

Definition at line 1225 of file stm32f756xx.h.

#define FMC_R_BASE   0xA0000000U

Base address of : FMC Control registers

Definition at line 1233 of file stm32f765xx.h.

#define FMC_R_BASE   0xA0000000U

Base address of : FMC Control registers

Definition at line 1319 of file stm32f767xx.h.

#define FMC_R_BASE   0xA0000000U

Base address of : FMC Control registers

Definition at line 1388 of file stm32f777xx.h.

#define FMC_R_BASE   0xA0000000U

Base address of : FMC Control registers

Definition at line 1400 of file stm32f769xx.h.

#define FMC_R_BASE   0xA0000000U

Base address of : FMC Control registers

Definition at line 1469 of file stm32f779xx.h.

#define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000U)

Definition at line 1181 of file stm32f745xx.h.

#define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000U)

Definition at line 1233 of file stm32f746xx.h.

#define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000U)

Definition at line 1302 of file stm32f756xx.h.

#define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000U)

Definition at line 1323 of file stm32f765xx.h.

#define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000U)

Definition at line 1412 of file stm32f767xx.h.

#define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000U)

Definition at line 1481 of file stm32f777xx.h.

#define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000U)

Definition at line 1494 of file stm32f769xx.h.

#define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000U)

Definition at line 1563 of file stm32f779xx.h.

#define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400U)

Definition at line 1182 of file stm32f745xx.h.

#define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400U)

Definition at line 1234 of file stm32f746xx.h.

#define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400U)

Definition at line 1303 of file stm32f756xx.h.

#define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400U)

Definition at line 1324 of file stm32f765xx.h.

#define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400U)

Definition at line 1413 of file stm32f767xx.h.

#define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400U)

Definition at line 1482 of file stm32f777xx.h.

#define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400U)

Definition at line 1495 of file stm32f769xx.h.

#define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400U)

Definition at line 1564 of file stm32f779xx.h.

#define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800U)

Definition at line 1183 of file stm32f745xx.h.

#define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800U)

Definition at line 1235 of file stm32f746xx.h.

#define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800U)

Definition at line 1304 of file stm32f756xx.h.

#define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800U)

Definition at line 1325 of file stm32f765xx.h.

#define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800U)

Definition at line 1414 of file stm32f767xx.h.

#define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800U)

Definition at line 1483 of file stm32f777xx.h.

#define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800U)

Definition at line 1496 of file stm32f769xx.h.

#define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800U)

Definition at line 1565 of file stm32f779xx.h.

#define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00U)

Definition at line 1184 of file stm32f745xx.h.

#define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00U)

Definition at line 1236 of file stm32f746xx.h.

#define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00U)

Definition at line 1305 of file stm32f756xx.h.

#define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00U)

Definition at line 1326 of file stm32f765xx.h.

#define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00U)

Definition at line 1415 of file stm32f767xx.h.

#define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00U)

Definition at line 1484 of file stm32f777xx.h.

#define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00U)

Definition at line 1497 of file stm32f769xx.h.

#define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00U)

Definition at line 1566 of file stm32f779xx.h.

#define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000U)

Definition at line 1185 of file stm32f745xx.h.

#define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000U)

Definition at line 1237 of file stm32f746xx.h.

#define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000U)

Definition at line 1306 of file stm32f756xx.h.

#define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000U)

Definition at line 1327 of file stm32f765xx.h.

#define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000U)

Definition at line 1416 of file stm32f767xx.h.

#define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000U)

Definition at line 1485 of file stm32f777xx.h.

#define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000U)

Definition at line 1498 of file stm32f769xx.h.

#define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000U)

Definition at line 1567 of file stm32f779xx.h.

#define GPIOF_BASE   (AHB1PERIPH_BASE + 0x1400U)

Definition at line 1186 of file stm32f745xx.h.

#define GPIOF_BASE   (AHB1PERIPH_BASE + 0x1400U)

Definition at line 1238 of file stm32f746xx.h.

#define GPIOF_BASE   (AHB1PERIPH_BASE + 0x1400U)

Definition at line 1307 of file stm32f756xx.h.

#define GPIOF_BASE   (AHB1PERIPH_BASE + 0x1400U)

Definition at line 1328 of file stm32f765xx.h.

#define GPIOF_BASE   (AHB1PERIPH_BASE + 0x1400U)

Definition at line 1417 of file stm32f767xx.h.

#define GPIOF_BASE   (AHB1PERIPH_BASE + 0x1400U)

Definition at line 1486 of file stm32f777xx.h.

#define GPIOF_BASE   (AHB1PERIPH_BASE + 0x1400U)

Definition at line 1499 of file stm32f769xx.h.

#define GPIOF_BASE   (AHB1PERIPH_BASE + 0x1400U)

Definition at line 1568 of file stm32f779xx.h.

#define GPIOG_BASE   (AHB1PERIPH_BASE + 0x1800U)

Definition at line 1187 of file stm32f745xx.h.

#define GPIOG_BASE   (AHB1PERIPH_BASE + 0x1800U)

Definition at line 1239 of file stm32f746xx.h.

#define GPIOG_BASE   (AHB1PERIPH_BASE + 0x1800U)

Definition at line 1308 of file stm32f756xx.h.

#define GPIOG_BASE   (AHB1PERIPH_BASE + 0x1800U)

Definition at line 1329 of file stm32f765xx.h.

#define GPIOG_BASE   (AHB1PERIPH_BASE + 0x1800U)

Definition at line 1418 of file stm32f767xx.h.

#define GPIOG_BASE   (AHB1PERIPH_BASE + 0x1800U)

Definition at line 1487 of file stm32f777xx.h.

#define GPIOG_BASE   (AHB1PERIPH_BASE + 0x1800U)

Definition at line 1500 of file stm32f769xx.h.

#define GPIOG_BASE   (AHB1PERIPH_BASE + 0x1800U)

Definition at line 1569 of file stm32f779xx.h.

#define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00U)

Definition at line 1188 of file stm32f745xx.h.

#define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00U)

Definition at line 1240 of file stm32f746xx.h.

#define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00U)

Definition at line 1309 of file stm32f756xx.h.

#define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00U)

Definition at line 1330 of file stm32f765xx.h.

#define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00U)

Definition at line 1419 of file stm32f767xx.h.

#define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00U)

Definition at line 1488 of file stm32f777xx.h.

#define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00U)

Definition at line 1501 of file stm32f769xx.h.

#define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00U)

Definition at line 1570 of file stm32f779xx.h.

#define GPIOI_BASE   (AHB1PERIPH_BASE + 0x2000U)

Definition at line 1189 of file stm32f745xx.h.

#define GPIOI_BASE   (AHB1PERIPH_BASE + 0x2000U)

Definition at line 1241 of file stm32f746xx.h.

#define GPIOI_BASE   (AHB1PERIPH_BASE + 0x2000U)

Definition at line 1310 of file stm32f756xx.h.

#define GPIOI_BASE   (AHB1PERIPH_BASE + 0x2000U)

Definition at line 1331 of file stm32f765xx.h.

#define GPIOI_BASE   (AHB1PERIPH_BASE + 0x2000U)

Definition at line 1420 of file stm32f767xx.h.

#define GPIOI_BASE   (AHB1PERIPH_BASE + 0x2000U)

Definition at line 1489 of file stm32f777xx.h.

#define GPIOI_BASE   (AHB1PERIPH_BASE + 0x2000U)

Definition at line 1502 of file stm32f769xx.h.

#define GPIOI_BASE   (AHB1PERIPH_BASE + 0x2000U)

Definition at line 1571 of file stm32f779xx.h.

#define GPIOJ_BASE   (AHB1PERIPH_BASE + 0x2400U)

Definition at line 1190 of file stm32f745xx.h.

#define GPIOJ_BASE   (AHB1PERIPH_BASE + 0x2400U)

Definition at line 1242 of file stm32f746xx.h.

#define GPIOJ_BASE   (AHB1PERIPH_BASE + 0x2400U)

Definition at line 1311 of file stm32f756xx.h.

#define GPIOJ_BASE   (AHB1PERIPH_BASE + 0x2400U)

Definition at line 1332 of file stm32f765xx.h.

#define GPIOJ_BASE   (AHB1PERIPH_BASE + 0x2400U)

Definition at line 1421 of file stm32f767xx.h.

#define GPIOJ_BASE   (AHB1PERIPH_BASE + 0x2400U)

Definition at line 1490 of file stm32f777xx.h.

#define GPIOJ_BASE   (AHB1PERIPH_BASE + 0x2400U)

Definition at line 1503 of file stm32f769xx.h.

#define GPIOJ_BASE   (AHB1PERIPH_BASE + 0x2400U)

Definition at line 1572 of file stm32f779xx.h.

#define GPIOK_BASE   (AHB1PERIPH_BASE + 0x2800U)

Definition at line 1191 of file stm32f745xx.h.

#define GPIOK_BASE   (AHB1PERIPH_BASE + 0x2800U)

Definition at line 1243 of file stm32f746xx.h.

#define GPIOK_BASE   (AHB1PERIPH_BASE + 0x2800U)

Definition at line 1312 of file stm32f756xx.h.

#define GPIOK_BASE   (AHB1PERIPH_BASE + 0x2800U)

Definition at line 1333 of file stm32f765xx.h.

#define GPIOK_BASE   (AHB1PERIPH_BASE + 0x2800U)

Definition at line 1422 of file stm32f767xx.h.

#define GPIOK_BASE   (AHB1PERIPH_BASE + 0x2800U)

Definition at line 1491 of file stm32f777xx.h.

#define GPIOK_BASE   (AHB1PERIPH_BASE + 0x2800U)

Definition at line 1504 of file stm32f769xx.h.

#define GPIOK_BASE   (AHB1PERIPH_BASE + 0x2800U)

Definition at line 1573 of file stm32f779xx.h.

#define HASH_BASE   (AHB2PERIPH_BASE + 0x60400U)

Definition at line 1346 of file stm32f756xx.h.

#define HASH_BASE   (AHB2PERIPH_BASE + 0x60400U)

Definition at line 1526 of file stm32f777xx.h.

#define HASH_BASE   (AHB2PERIPH_BASE + 0x60400U)

Definition at line 1608 of file stm32f779xx.h.

#define HASH_DIGEST_BASE   (AHB2PERIPH_BASE + 0x60710U)

Definition at line 1347 of file stm32f756xx.h.

#define HASH_DIGEST_BASE   (AHB2PERIPH_BASE + 0x60710U)

Definition at line 1527 of file stm32f777xx.h.

#define HASH_DIGEST_BASE   (AHB2PERIPH_BASE + 0x60710U)

Definition at line 1609 of file stm32f779xx.h.

#define I2C1_BASE   (APB1PERIPH_BASE + 0x5400U)

Definition at line 1143 of file stm32f745xx.h.

#define I2C1_BASE   (APB1PERIPH_BASE + 0x5400U)

Definition at line 1192 of file stm32f746xx.h.

#define I2C1_BASE   (APB1PERIPH_BASE + 0x5400U)

Definition at line 1261 of file stm32f756xx.h.

#define I2C1_BASE   (APB1PERIPH_BASE + 0x5400U)

Definition at line 1270 of file stm32f765xx.h.

#define I2C1_BASE   (APB1PERIPH_BASE + 0x5400U)

Definition at line 1356 of file stm32f767xx.h.

#define I2C1_BASE   (APB1PERIPH_BASE + 0x5400U)

Definition at line 1425 of file stm32f777xx.h.

#define I2C1_BASE   (APB1PERIPH_BASE + 0x5400U)

Definition at line 1437 of file stm32f769xx.h.

#define I2C1_BASE   (APB1PERIPH_BASE + 0x5400U)

Definition at line 1506 of file stm32f779xx.h.

#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800U)

Definition at line 1144 of file stm32f745xx.h.

#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800U)

Definition at line 1193 of file stm32f746xx.h.

#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800U)

Definition at line 1262 of file stm32f756xx.h.

#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800U)

Definition at line 1271 of file stm32f765xx.h.

#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800U)

Definition at line 1357 of file stm32f767xx.h.

#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800U)

Definition at line 1426 of file stm32f777xx.h.

#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800U)

Definition at line 1438 of file stm32f769xx.h.

#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800U)

Definition at line 1507 of file stm32f779xx.h.

#define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00U)

Definition at line 1145 of file stm32f745xx.h.

#define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00U)

Definition at line 1194 of file stm32f746xx.h.

#define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00U)

Definition at line 1263 of file stm32f756xx.h.

#define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00U)

Definition at line 1272 of file stm32f765xx.h.

#define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00U)

Definition at line 1358 of file stm32f767xx.h.

#define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00U)

Definition at line 1427 of file stm32f777xx.h.

#define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00U)

Definition at line 1439 of file stm32f769xx.h.

#define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00U)

Definition at line 1508 of file stm32f779xx.h.

#define I2C4_BASE   (APB1PERIPH_BASE + 0x6000U)

Definition at line 1146 of file stm32f745xx.h.

#define I2C4_BASE   (APB1PERIPH_BASE + 0x6000U)

Definition at line 1195 of file stm32f746xx.h.

#define I2C4_BASE   (APB1PERIPH_BASE + 0x6000U)

Definition at line 1264 of file stm32f756xx.h.

#define I2C4_BASE   (APB1PERIPH_BASE + 0x6000U)

Definition at line 1273 of file stm32f765xx.h.

#define I2C4_BASE   (APB1PERIPH_BASE + 0x6000U)

Definition at line 1359 of file stm32f767xx.h.

#define I2C4_BASE   (APB1PERIPH_BASE + 0x6000U)

Definition at line 1428 of file stm32f777xx.h.

#define I2C4_BASE   (APB1PERIPH_BASE + 0x6000U)

Definition at line 1440 of file stm32f769xx.h.

#define I2C4_BASE   (APB1PERIPH_BASE + 0x6000U)

Definition at line 1509 of file stm32f779xx.h.

#define IWDG_BASE   (APB1PERIPH_BASE + 0x3000U)

Definition at line 1135 of file stm32f745xx.h.

#define IWDG_BASE   (APB1PERIPH_BASE + 0x3000U)

Definition at line 1184 of file stm32f746xx.h.

#define IWDG_BASE   (APB1PERIPH_BASE + 0x3000U)

Definition at line 1253 of file stm32f756xx.h.

#define IWDG_BASE   (APB1PERIPH_BASE + 0x3000U)

Definition at line 1261 of file stm32f765xx.h.

#define IWDG_BASE   (APB1PERIPH_BASE + 0x3000U)

Definition at line 1347 of file stm32f767xx.h.

#define IWDG_BASE   (APB1PERIPH_BASE + 0x3000U)

Definition at line 1416 of file stm32f777xx.h.

#define IWDG_BASE   (APB1PERIPH_BASE + 0x3000U)

Definition at line 1428 of file stm32f769xx.h.

#define IWDG_BASE   (APB1PERIPH_BASE + 0x3000U)

Definition at line 1497 of file stm32f779xx.h.

#define JPEG_BASE   (AHB2PERIPH_BASE + 0x51000U)

Definition at line 1455 of file stm32f767xx.h.

#define JPEG_BASE   (AHB2PERIPH_BASE + 0x51000U)

Definition at line 1524 of file stm32f777xx.h.

#define JPEG_BASE   (AHB2PERIPH_BASE + 0x51000U)

Definition at line 1537 of file stm32f769xx.h.

#define JPEG_BASE   (AHB2PERIPH_BASE + 0x51000U)

Definition at line 1606 of file stm32f779xx.h.

#define LPTIM1_BASE   (APB1PERIPH_BASE + 0x2400U)

Definition at line 1132 of file stm32f745xx.h.

#define LPTIM1_BASE   (APB1PERIPH_BASE + 0x2400U)

Definition at line 1181 of file stm32f746xx.h.

#define LPTIM1_BASE   (APB1PERIPH_BASE + 0x2400U)

Definition at line 1250 of file stm32f756xx.h.

#define LPTIM1_BASE   (APB1PERIPH_BASE + 0x2400U)

Definition at line 1258 of file stm32f765xx.h.

#define LPTIM1_BASE   (APB1PERIPH_BASE + 0x2400U)

Definition at line 1344 of file stm32f767xx.h.

#define LPTIM1_BASE   (APB1PERIPH_BASE + 0x2400U)

Definition at line 1413 of file stm32f777xx.h.

#define LPTIM1_BASE   (APB1PERIPH_BASE + 0x2400U)

Definition at line 1425 of file stm32f769xx.h.

#define LPTIM1_BASE   (APB1PERIPH_BASE + 0x2400U)

Definition at line 1494 of file stm32f779xx.h.

#define LTDC_BASE   (APB2PERIPH_BASE + 0x6800U)

Definition at line 1229 of file stm32f746xx.h.

#define LTDC_BASE   (APB2PERIPH_BASE + 0x6800U)

Definition at line 1298 of file stm32f756xx.h.

#define LTDC_BASE   (APB2PERIPH_BASE + 0x6800U)

Definition at line 1394 of file stm32f767xx.h.

#define LTDC_BASE   (APB2PERIPH_BASE + 0x6800U)

Definition at line 1463 of file stm32f777xx.h.

#define LTDC_BASE   (APB2PERIPH_BASE + 0x6800U)

Definition at line 1475 of file stm32f769xx.h.

#define LTDC_BASE   (APB2PERIPH_BASE + 0x6800U)

Definition at line 1544 of file stm32f779xx.h.

#define LTDC_Layer1_BASE   (LTDC_BASE + 0x84U)

Definition at line 1230 of file stm32f746xx.h.

#define LTDC_Layer1_BASE   (LTDC_BASE + 0x84U)

Definition at line 1299 of file stm32f756xx.h.

#define LTDC_Layer1_BASE   (LTDC_BASE + 0x84U)

Definition at line 1395 of file stm32f767xx.h.

#define LTDC_Layer1_BASE   (LTDC_BASE + 0x84U)

Definition at line 1464 of file stm32f777xx.h.

#define LTDC_Layer1_BASE   (LTDC_BASE + 0x84U)

Definition at line 1476 of file stm32f769xx.h.

#define LTDC_Layer1_BASE   (LTDC_BASE + 0x84U)

Definition at line 1545 of file stm32f779xx.h.

#define LTDC_Layer2_BASE   (LTDC_BASE + 0x104U)

AHB1 peripherals

Definition at line 1231 of file stm32f746xx.h.

#define LTDC_Layer2_BASE   (LTDC_BASE + 0x104U)

AHB1 peripherals

Definition at line 1300 of file stm32f756xx.h.

#define LTDC_Layer2_BASE   (LTDC_BASE + 0x104U)

Definition at line 1396 of file stm32f767xx.h.

#define LTDC_Layer2_BASE   (LTDC_BASE + 0x104U)

Definition at line 1465 of file stm32f777xx.h.

#define LTDC_Layer2_BASE   (LTDC_BASE + 0x104U)

Definition at line 1477 of file stm32f769xx.h.

#define LTDC_Layer2_BASE   (LTDC_BASE + 0x104U)

Definition at line 1546 of file stm32f779xx.h.

#define MDIOS_BASE   (APB2PERIPH_BASE + 0x7800U)

AHB1 peripherals

Definition at line 1321 of file stm32f765xx.h.

#define MDIOS_BASE   (APB2PERIPH_BASE + 0x7800U)

AHB1 peripherals

Definition at line 1410 of file stm32f767xx.h.

#define MDIOS_BASE   (APB2PERIPH_BASE + 0x7800U)

AHB1 peripherals

Definition at line 1479 of file stm32f777xx.h.

#define MDIOS_BASE   (APB2PERIPH_BASE + 0x7800U)

AHB1 peripherals

Definition at line 1492 of file stm32f769xx.h.

#define MDIOS_BASE   (APB2PERIPH_BASE + 0x7800U)

AHB1 peripherals

Definition at line 1561 of file stm32f779xx.h.

#define PACKAGESIZE_BASE   0x1FFF7BF0U

Package size register base address

Definition at line 1197 of file stm32f745xx.h.

#define PACKAGESIZE_BASE   0x1FFF7BF0U

Package size register base address

Definition at line 1249 of file stm32f746xx.h.

#define PACKAGESIZE_BASE   0x1FFF7BF0U

Package size register base address

Definition at line 1318 of file stm32f756xx.h.

#define PACKAGESIZE_BASE   0x1FFF7BF0U

Package size register base address

Definition at line 1339 of file stm32f765xx.h.

#define PACKAGESIZE_BASE   0x1FFF7BF0U

Package size register base address

Definition at line 1428 of file stm32f767xx.h.

#define PACKAGESIZE_BASE   0x1FFF7BF0U

Package size register base address

Definition at line 1497 of file stm32f777xx.h.

#define PACKAGESIZE_BASE   0x1FFF7BF0U

Package size register base address

Definition at line 1510 of file stm32f769xx.h.

#define PACKAGESIZE_BASE   0x1FFF7BF0U

Package size register base address

Definition at line 1579 of file stm32f779xx.h.

#define PERIPH_BASE   0x40000000U

Base address of : AHB/ABP Peripherals

Definition at line 1104 of file stm32f745xx.h.

#define PERIPH_BASE   0x40000000U

Base address of : AHB/ABP Peripherals

Definition at line 1153 of file stm32f746xx.h.

#define PERIPH_BASE   0x40000000U

Base address of : AHB/ABP Peripherals

Definition at line 1222 of file stm32f756xx.h.

#define PERIPH_BASE   0x40000000U

Base address of : AHB/ABP Peripherals

Definition at line 1230 of file stm32f765xx.h.

#define PERIPH_BASE   0x40000000U

Base address of : AHB/ABP Peripherals

Definition at line 1316 of file stm32f767xx.h.

#define PERIPH_BASE   0x40000000U

Base address of : AHB/ABP Peripherals

Definition at line 1385 of file stm32f777xx.h.

#define PERIPH_BASE   0x40000000U

Base address of : AHB/ABP Peripherals

Definition at line 1397 of file stm32f769xx.h.

#define PERIPH_BASE   0x40000000U

Base address of : AHB/ABP Peripherals

Definition at line 1466 of file stm32f779xx.h.

#define PWR_BASE   (APB1PERIPH_BASE + 0x7000U)

Definition at line 1150 of file stm32f745xx.h.

#define PWR_BASE   (APB1PERIPH_BASE + 0x7000U)

Definition at line 1199 of file stm32f746xx.h.

#define PWR_BASE   (APB1PERIPH_BASE + 0x7000U)

Definition at line 1268 of file stm32f756xx.h.

#define PWR_BASE   (APB1PERIPH_BASE + 0x7000U)

Definition at line 1277 of file stm32f765xx.h.

#define PWR_BASE   (APB1PERIPH_BASE + 0x7000U)

Definition at line 1363 of file stm32f767xx.h.

#define PWR_BASE   (APB1PERIPH_BASE + 0x7000U)

Definition at line 1432 of file stm32f777xx.h.

#define PWR_BASE   (APB1PERIPH_BASE + 0x7000U)

Definition at line 1444 of file stm32f769xx.h.

#define PWR_BASE   (APB1PERIPH_BASE + 0x7000U)

Definition at line 1513 of file stm32f779xx.h.

#define QSPI_BASE   0x90000000U

Base address of : QSPI memories accessible over AXI

Definition at line 1106 of file stm32f745xx.h.

#define QSPI_BASE   0x90000000U

Base address of : QSPI memories accessible over AXI

Definition at line 1155 of file stm32f746xx.h.

#define QSPI_BASE   0x90000000U

Base address of : QSPI memories accessible over AXI

Definition at line 1224 of file stm32f756xx.h.

#define QSPI_BASE   0x90000000U

Base address of : QSPI memories accessible over AXI

Definition at line 1232 of file stm32f765xx.h.

#define QSPI_BASE   0x90000000U

Base address of : QSPI memories accessible over AXI

Definition at line 1318 of file stm32f767xx.h.

#define QSPI_BASE   0x90000000U

Base address of : QSPI memories accessible over AXI

Definition at line 1387 of file stm32f777xx.h.

#define QSPI_BASE   0x90000000U

Base address of : QSPI memories accessible over AXI

Definition at line 1399 of file stm32f769xx.h.

#define QSPI_BASE   0x90000000U

Base address of : QSPI memories accessible over AXI

Definition at line 1468 of file stm32f779xx.h.

#define QSPI_R_BASE   0xA0001000U

Base address of : QSPI Control registers

Definition at line 1108 of file stm32f745xx.h.

#define QSPI_R_BASE   0xA0001000U

Base address of : QSPI Control registers

Definition at line 1157 of file stm32f746xx.h.

#define QSPI_R_BASE   0xA0001000U

Base address of : QSPI Control registers

Definition at line 1226 of file stm32f756xx.h.

#define QSPI_R_BASE   0xA0001000U

Base address of : QSPI Control registers

Definition at line 1234 of file stm32f765xx.h.

#define QSPI_R_BASE   0xA0001000U

Base address of : QSPI Control registers

Definition at line 1320 of file stm32f767xx.h.

#define QSPI_R_BASE   0xA0001000U

Base address of : QSPI Control registers

Definition at line 1389 of file stm32f777xx.h.

#define QSPI_R_BASE   0xA0001000U

Base address of : QSPI Control registers

Definition at line 1401 of file stm32f769xx.h.

#define QSPI_R_BASE   0xA0001000U

Base address of : QSPI Control registers

Definition at line 1470 of file stm32f779xx.h.

#define RAMDTCM_BASE   0x20000000U

Base address of : 64KB system data RAM accessible over DTCM

Definition at line 1103 of file stm32f745xx.h.

#define RAMDTCM_BASE   0x20000000U

Base address of : 64KB system data RAM accessible over DTCM

Definition at line 1152 of file stm32f746xx.h.

#define RAMDTCM_BASE   0x20000000U

Base address of : 64KB system data RAM accessible over DTCM

Definition at line 1221 of file stm32f756xx.h.

#define RAMDTCM_BASE   0x20000000U

Base address of : 128KB system data RAM accessible over DTCM

Definition at line 1229 of file stm32f765xx.h.

#define RAMDTCM_BASE   0x20000000U

Base address of : 128KB system data RAM accessible over DTCM

Definition at line 1315 of file stm32f767xx.h.

#define RAMDTCM_BASE   0x20000000U

Base address of : 128KB system data RAM accessible over DTCM

Definition at line 1384 of file stm32f777xx.h.

#define RAMDTCM_BASE   0x20000000U

Base address of : 128KB system data RAM accessible over DTCM

Definition at line 1396 of file stm32f769xx.h.

#define RAMDTCM_BASE   0x20000000U

Base address of : 128KB system data RAM accessible over DTCM

Definition at line 1465 of file stm32f779xx.h.

#define RAMITCM_BASE   0x00000000U

Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM

Definition at line 1100 of file stm32f745xx.h.

#define RAMITCM_BASE   0x00000000U

Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM

Definition at line 1149 of file stm32f746xx.h.

#define RAMITCM_BASE   0x00000000U

Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM

Definition at line 1218 of file stm32f756xx.h.

#define RAMITCM_BASE   0x00000000U

Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM

Definition at line 1226 of file stm32f765xx.h.

#define RAMITCM_BASE   0x00000000U

Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM

Definition at line 1312 of file stm32f767xx.h.

#define RAMITCM_BASE   0x00000000U

Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM

Definition at line 1381 of file stm32f777xx.h.

#define RAMITCM_BASE   0x00000000U

Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM

Definition at line 1393 of file stm32f769xx.h.

#define RAMITCM_BASE   0x00000000U

Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM

Definition at line 1462 of file stm32f779xx.h.

#define RCC_BASE   (AHB1PERIPH_BASE + 0x3800U)

Definition at line 1193 of file stm32f745xx.h.

#define RCC_BASE   (AHB1PERIPH_BASE + 0x3800U)

Definition at line 1245 of file stm32f746xx.h.

#define RCC_BASE   (AHB1PERIPH_BASE + 0x3800U)

Definition at line 1314 of file stm32f756xx.h.

#define RCC_BASE   (AHB1PERIPH_BASE + 0x3800U)

Definition at line 1335 of file stm32f765xx.h.

#define RCC_BASE   (AHB1PERIPH_BASE + 0x3800U)

Definition at line 1424 of file stm32f767xx.h.

#define RCC_BASE   (AHB1PERIPH_BASE + 0x3800U)

Definition at line 1493 of file stm32f777xx.h.

#define RCC_BASE   (AHB1PERIPH_BASE + 0x3800U)

Definition at line 1506 of file stm32f769xx.h.

#define RCC_BASE   (AHB1PERIPH_BASE + 0x3800U)

Definition at line 1575 of file stm32f779xx.h.

#define RNG_BASE   (AHB2PERIPH_BASE + 0x60800U)

FMC Bankx registers base address

Definition at line 1224 of file stm32f745xx.h.

#define RNG_BASE   (AHB2PERIPH_BASE + 0x60800U)

FMC Bankx registers base address

Definition at line 1276 of file stm32f746xx.h.

#define RNG_BASE   (AHB2PERIPH_BASE + 0x60800U)

FMC Bankx registers base address

Definition at line 1348 of file stm32f756xx.h.

#define RNG_BASE   (AHB2PERIPH_BASE + 0x60800U)

FMC Bankx registers base address

Definition at line 1366 of file stm32f765xx.h.

#define RNG_BASE   (AHB2PERIPH_BASE + 0x60800U)

FMC Bankx registers base address

Definition at line 1456 of file stm32f767xx.h.

#define RNG_BASE   (AHB2PERIPH_BASE + 0x60800U)

FMC Bankx registers base address

Definition at line 1528 of file stm32f777xx.h.

#define RNG_BASE   (AHB2PERIPH_BASE + 0x60800U)

FMC Bankx registers base address

Definition at line 1538 of file stm32f769xx.h.

#define RNG_BASE   (AHB2PERIPH_BASE + 0x60800U)

FMC Bankx registers base address

Definition at line 1610 of file stm32f779xx.h.

#define RTC_BASE   (APB1PERIPH_BASE + 0x2800U)

Definition at line 1133 of file stm32f745xx.h.

#define RTC_BASE   (APB1PERIPH_BASE + 0x2800U)

Definition at line 1182 of file stm32f746xx.h.

#define RTC_BASE   (APB1PERIPH_BASE + 0x2800U)

Definition at line 1251 of file stm32f756xx.h.

#define RTC_BASE   (APB1PERIPH_BASE + 0x2800U)

Definition at line 1259 of file stm32f765xx.h.

#define RTC_BASE   (APB1PERIPH_BASE + 0x2800U)

Definition at line 1345 of file stm32f767xx.h.

#define RTC_BASE   (APB1PERIPH_BASE + 0x2800U)

Definition at line 1414 of file stm32f777xx.h.

#define RTC_BASE   (APB1PERIPH_BASE + 0x2800U)

Definition at line 1426 of file stm32f769xx.h.

#define RTC_BASE   (APB1PERIPH_BASE + 0x2800U)

Definition at line 1495 of file stm32f779xx.h.

#define SAI1_BASE   (APB2PERIPH_BASE + 0x5800U)

Definition at line 1174 of file stm32f745xx.h.

#define SAI1_BASE   (APB2PERIPH_BASE + 0x5800U)

Definition at line 1223 of file stm32f746xx.h.

#define SAI1_BASE   (APB2PERIPH_BASE + 0x5800U)

Definition at line 1292 of file stm32f756xx.h.

#define SAI1_BASE   (APB2PERIPH_BASE + 0x5800U)

Definition at line 1302 of file stm32f765xx.h.

#define SAI1_BASE   (APB2PERIPH_BASE + 0x5800U)

Definition at line 1388 of file stm32f767xx.h.

#define SAI1_BASE   (APB2PERIPH_BASE + 0x5800U)

Definition at line 1457 of file stm32f777xx.h.

#define SAI1_BASE   (APB2PERIPH_BASE + 0x5800U)

Definition at line 1469 of file stm32f769xx.h.

#define SAI1_BASE   (APB2PERIPH_BASE + 0x5800U)

Definition at line 1538 of file stm32f779xx.h.

#define SAI1_Block_A_BASE   (SAI1_BASE + 0x004U)

Definition at line 1176 of file stm32f745xx.h.

#define SAI1_Block_A_BASE   (SAI1_BASE + 0x004U)

Definition at line 1225 of file stm32f746xx.h.

#define SAI1_Block_A_BASE   (SAI1_BASE + 0x004U)

Definition at line 1294 of file stm32f756xx.h.

#define SAI1_Block_A_BASE   (SAI1_BASE + 0x004U)

Definition at line 1304 of file stm32f765xx.h.

#define SAI1_Block_A_BASE   (SAI1_BASE + 0x004U)

Definition at line 1390 of file stm32f767xx.h.

#define SAI1_Block_A_BASE   (SAI1_BASE + 0x004U)

Definition at line 1459 of file stm32f777xx.h.

#define SAI1_Block_A_BASE   (SAI1_BASE + 0x004U)

Definition at line 1471 of file stm32f769xx.h.

#define SAI1_Block_A_BASE   (SAI1_BASE + 0x004U)

Definition at line 1540 of file stm32f779xx.h.

#define SAI1_Block_B_BASE   (SAI1_BASE + 0x024U)

Definition at line 1177 of file stm32f745xx.h.

#define SAI1_Block_B_BASE   (SAI1_BASE + 0x024U)

Definition at line 1226 of file stm32f746xx.h.

#define SAI1_Block_B_BASE   (SAI1_BASE + 0x024U)

Definition at line 1295 of file stm32f756xx.h.

#define SAI1_Block_B_BASE   (SAI1_BASE + 0x024U)

Definition at line 1305 of file stm32f765xx.h.

#define SAI1_Block_B_BASE   (SAI1_BASE + 0x024U)

Definition at line 1391 of file stm32f767xx.h.

#define SAI1_Block_B_BASE   (SAI1_BASE + 0x024U)

Definition at line 1460 of file stm32f777xx.h.

#define SAI1_Block_B_BASE   (SAI1_BASE + 0x024U)

Definition at line 1472 of file stm32f769xx.h.

#define SAI1_Block_B_BASE   (SAI1_BASE + 0x024U)

Definition at line 1541 of file stm32f779xx.h.

#define SAI2_BASE   (APB2PERIPH_BASE + 0x5C00U)

Definition at line 1175 of file stm32f745xx.h.

#define SAI2_BASE   (APB2PERIPH_BASE + 0x5C00U)

Definition at line 1224 of file stm32f746xx.h.

#define SAI2_BASE   (APB2PERIPH_BASE + 0x5C00U)

Definition at line 1293 of file stm32f756xx.h.

#define SAI2_BASE   (APB2PERIPH_BASE + 0x5C00U)

Definition at line 1303 of file stm32f765xx.h.

#define SAI2_BASE   (APB2PERIPH_BASE + 0x5C00U)

Definition at line 1389 of file stm32f767xx.h.

#define SAI2_BASE   (APB2PERIPH_BASE + 0x5C00U)

Definition at line 1458 of file stm32f777xx.h.

#define SAI2_BASE   (APB2PERIPH_BASE + 0x5C00U)

Definition at line 1470 of file stm32f769xx.h.

#define SAI2_BASE   (APB2PERIPH_BASE + 0x5C00U)

Definition at line 1539 of file stm32f779xx.h.

#define SAI2_Block_A_BASE   (SAI2_BASE + 0x004U)

Definition at line 1178 of file stm32f745xx.h.

#define SAI2_Block_A_BASE   (SAI2_BASE + 0x004U)

Definition at line 1227 of file stm32f746xx.h.

#define SAI2_Block_A_BASE   (SAI2_BASE + 0x004U)

Definition at line 1296 of file stm32f756xx.h.

#define SAI2_Block_A_BASE   (SAI2_BASE + 0x004U)

Definition at line 1306 of file stm32f765xx.h.

#define SAI2_Block_A_BASE   (SAI2_BASE + 0x004U)

Definition at line 1392 of file stm32f767xx.h.

#define SAI2_Block_A_BASE   (SAI2_BASE + 0x004U)

Definition at line 1461 of file stm32f777xx.h.

#define SAI2_Block_A_BASE   (SAI2_BASE + 0x004U)

Definition at line 1473 of file stm32f769xx.h.

#define SAI2_Block_A_BASE   (SAI2_BASE + 0x004U)

Definition at line 1542 of file stm32f779xx.h.

#define SAI2_Block_B_BASE   (SAI2_BASE + 0x024U)

AHB1 peripherals

Definition at line 1179 of file stm32f745xx.h.

#define SAI2_Block_B_BASE   (SAI2_BASE + 0x024U)

Definition at line 1228 of file stm32f746xx.h.

#define SAI2_Block_B_BASE   (SAI2_BASE + 0x024U)

Definition at line 1297 of file stm32f756xx.h.

#define SAI2_Block_B_BASE   (SAI2_BASE + 0x024U)

Definition at line 1307 of file stm32f765xx.h.

#define SAI2_Block_B_BASE   (SAI2_BASE + 0x024U)

Definition at line 1393 of file stm32f767xx.h.

#define SAI2_Block_B_BASE   (SAI2_BASE + 0x024U)

Definition at line 1462 of file stm32f777xx.h.

#define SAI2_Block_B_BASE   (SAI2_BASE + 0x024U)

Definition at line 1474 of file stm32f769xx.h.

#define SAI2_Block_B_BASE   (SAI2_BASE + 0x024U)

Definition at line 1543 of file stm32f779xx.h.

#define SDMMC1_BASE   (APB2PERIPH_BASE + 0x2C00U)

Definition at line 1164 of file stm32f745xx.h.

#define SDMMC1_BASE   (APB2PERIPH_BASE + 0x2C00U)

Definition at line 1213 of file stm32f746xx.h.

#define SDMMC1_BASE   (APB2PERIPH_BASE + 0x2C00U)

Definition at line 1282 of file stm32f756xx.h.

#define SDMMC1_BASE   (APB2PERIPH_BASE + 0x2C00U)

Definition at line 1292 of file stm32f765xx.h.

#define SDMMC1_BASE   (APB2PERIPH_BASE + 0x2C00U)

Definition at line 1378 of file stm32f767xx.h.

#define SDMMC1_BASE   (APB2PERIPH_BASE + 0x2C00U)

Definition at line 1447 of file stm32f777xx.h.

#define SDMMC1_BASE   (APB2PERIPH_BASE + 0x2C00U)

Definition at line 1459 of file stm32f769xx.h.

#define SDMMC1_BASE   (APB2PERIPH_BASE + 0x2C00U)

Definition at line 1528 of file stm32f779xx.h.

#define SDMMC2_BASE   (APB2PERIPH_BASE + 0x1C00U)

Definition at line 1287 of file stm32f765xx.h.

#define SDMMC2_BASE   (APB2PERIPH_BASE + 0x1C00U)

Definition at line 1373 of file stm32f767xx.h.

#define SDMMC2_BASE   (APB2PERIPH_BASE + 0x1C00U)

Definition at line 1442 of file stm32f777xx.h.

#define SDMMC2_BASE   (APB2PERIPH_BASE + 0x1C00U)

Definition at line 1454 of file stm32f769xx.h.

#define SDMMC2_BASE   (APB2PERIPH_BASE + 0x1C00U)

Definition at line 1523 of file stm32f779xx.h.

#define SPDIFRX_BASE   (APB1PERIPH_BASE + 0x4000U)

Definition at line 1138 of file stm32f745xx.h.

#define SPDIFRX_BASE   (APB1PERIPH_BASE + 0x4000U)

Definition at line 1187 of file stm32f746xx.h.

#define SPDIFRX_BASE   (APB1PERIPH_BASE + 0x4000U)

Definition at line 1256 of file stm32f756xx.h.

#define SPDIFRX_BASE   (APB1PERIPH_BASE + 0x4000U)

Definition at line 1265 of file stm32f765xx.h.

#define SPDIFRX_BASE   (APB1PERIPH_BASE + 0x4000U)

Definition at line 1351 of file stm32f767xx.h.

#define SPDIFRX_BASE   (APB1PERIPH_BASE + 0x4000U)

Definition at line 1420 of file stm32f777xx.h.

#define SPDIFRX_BASE   (APB1PERIPH_BASE + 0x4000U)

Definition at line 1432 of file stm32f769xx.h.

#define SPDIFRX_BASE   (APB1PERIPH_BASE + 0x4000U)

Definition at line 1501 of file stm32f779xx.h.

#define SPI1_BASE   (APB2PERIPH_BASE + 0x3000U)

Definition at line 1165 of file stm32f745xx.h.

#define SPI1_BASE   (APB2PERIPH_BASE + 0x3000U)

Definition at line 1214 of file stm32f746xx.h.

#define SPI1_BASE   (APB2PERIPH_BASE + 0x3000U)

Definition at line 1283 of file stm32f756xx.h.

#define SPI1_BASE   (APB2PERIPH_BASE + 0x3000U)

Definition at line 1293 of file stm32f765xx.h.

#define SPI1_BASE   (APB2PERIPH_BASE + 0x3000U)

Definition at line 1379 of file stm32f767xx.h.

#define SPI1_BASE   (APB2PERIPH_BASE + 0x3000U)

Definition at line 1448 of file stm32f777xx.h.

#define SPI1_BASE   (APB2PERIPH_BASE + 0x3000U)

Definition at line 1460 of file stm32f769xx.h.

#define SPI1_BASE   (APB2PERIPH_BASE + 0x3000U)

Definition at line 1529 of file stm32f779xx.h.

#define SPI2_BASE   (APB1PERIPH_BASE + 0x3800U)

Definition at line 1136 of file stm32f745xx.h.

#define SPI2_BASE   (APB1PERIPH_BASE + 0x3800U)

Definition at line 1185 of file stm32f746xx.h.

#define SPI2_BASE   (APB1PERIPH_BASE + 0x3800U)

Definition at line 1254 of file stm32f756xx.h.

#define SPI2_BASE   (APB1PERIPH_BASE + 0x3800U)

Definition at line 1263 of file stm32f765xx.h.

#define SPI2_BASE   (APB1PERIPH_BASE + 0x3800U)

Definition at line 1349 of file stm32f767xx.h.

#define SPI2_BASE   (APB1PERIPH_BASE + 0x3800U)

Definition at line 1418 of file stm32f777xx.h.

#define SPI2_BASE   (APB1PERIPH_BASE + 0x3800U)

Definition at line 1430 of file stm32f769xx.h.

#define SPI2_BASE   (APB1PERIPH_BASE + 0x3800U)

Definition at line 1499 of file stm32f779xx.h.

#define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00U)

Definition at line 1137 of file stm32f745xx.h.

#define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00U)

Definition at line 1186 of file stm32f746xx.h.

#define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00U)

Definition at line 1255 of file stm32f756xx.h.

#define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00U)

Definition at line 1264 of file stm32f765xx.h.

#define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00U)

Definition at line 1350 of file stm32f767xx.h.

#define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00U)

Definition at line 1419 of file stm32f777xx.h.

#define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00U)

Definition at line 1431 of file stm32f769xx.h.

#define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00U)

Definition at line 1500 of file stm32f779xx.h.

#define SPI4_BASE   (APB2PERIPH_BASE + 0x3400U)

Definition at line 1166 of file stm32f745xx.h.

#define SPI4_BASE   (APB2PERIPH_BASE + 0x3400U)

Definition at line 1215 of file stm32f746xx.h.

#define SPI4_BASE   (APB2PERIPH_BASE + 0x3400U)

Definition at line 1284 of file stm32f756xx.h.

#define SPI4_BASE   (APB2PERIPH_BASE + 0x3400U)

Definition at line 1294 of file stm32f765xx.h.

#define SPI4_BASE   (APB2PERIPH_BASE + 0x3400U)

Definition at line 1380 of file stm32f767xx.h.

#define SPI4_BASE   (APB2PERIPH_BASE + 0x3400U)

Definition at line 1449 of file stm32f777xx.h.

#define SPI4_BASE   (APB2PERIPH_BASE + 0x3400U)

Definition at line 1461 of file stm32f769xx.h.

#define SPI4_BASE   (APB2PERIPH_BASE + 0x3400U)

Definition at line 1530 of file stm32f779xx.h.

#define SPI5_BASE   (APB2PERIPH_BASE + 0x5000U)

Definition at line 1172 of file stm32f745xx.h.

#define SPI5_BASE   (APB2PERIPH_BASE + 0x5000U)

Definition at line 1221 of file stm32f746xx.h.

#define SPI5_BASE   (APB2PERIPH_BASE + 0x5000U)

Definition at line 1290 of file stm32f756xx.h.

#define SPI5_BASE   (APB2PERIPH_BASE + 0x5000U)

Definition at line 1300 of file stm32f765xx.h.

#define SPI5_BASE   (APB2PERIPH_BASE + 0x5000U)

Definition at line 1386 of file stm32f767xx.h.

#define SPI5_BASE   (APB2PERIPH_BASE + 0x5000U)

Definition at line 1455 of file stm32f777xx.h.

#define SPI5_BASE   (APB2PERIPH_BASE + 0x5000U)

Definition at line 1467 of file stm32f769xx.h.

#define SPI5_BASE   (APB2PERIPH_BASE + 0x5000U)

Definition at line 1536 of file stm32f779xx.h.

#define SPI6_BASE   (APB2PERIPH_BASE + 0x5400U)

Definition at line 1173 of file stm32f745xx.h.

#define SPI6_BASE   (APB2PERIPH_BASE + 0x5400U)

Definition at line 1222 of file stm32f746xx.h.

#define SPI6_BASE   (APB2PERIPH_BASE + 0x5400U)

Definition at line 1291 of file stm32f756xx.h.

#define SPI6_BASE   (APB2PERIPH_BASE + 0x5400U)

Definition at line 1301 of file stm32f765xx.h.

#define SPI6_BASE   (APB2PERIPH_BASE + 0x5400U)

Definition at line 1387 of file stm32f767xx.h.

#define SPI6_BASE   (APB2PERIPH_BASE + 0x5400U)

Definition at line 1456 of file stm32f777xx.h.

#define SPI6_BASE   (APB2PERIPH_BASE + 0x5400U)

Definition at line 1468 of file stm32f769xx.h.

#define SPI6_BASE   (APB2PERIPH_BASE + 0x5400U)

Definition at line 1537 of file stm32f779xx.h.

#define SRAM1_BASE   0x20010000U

Base address of : 240KB RAM1 accessible over AXI/AHB

Definition at line 1109 of file stm32f745xx.h.

#define SRAM1_BASE   0x20010000U

Base address of : 240KB RAM1 accessible over AXI/AHB

Definition at line 1158 of file stm32f746xx.h.

#define SRAM1_BASE   0x20010000U

Base address of : 240KB RAM1 accessible over AXI/AHB

Definition at line 1227 of file stm32f756xx.h.

#define SRAM1_BASE   0x20020000U

Base address of : 368KB RAM1 accessible over AXI/AHB

Definition at line 1235 of file stm32f765xx.h.

#define SRAM1_BASE   0x20020000U

Base address of : 368KB RAM1 accessible over AXI/AHB

Definition at line 1321 of file stm32f767xx.h.

#define SRAM1_BASE   0x20020000U

Base address of : 368KB RAM1 accessible over AXI/AHB

Definition at line 1390 of file stm32f777xx.h.

#define SRAM1_BASE   0x20020000U

Base address of : 368KB RAM1 accessible over AXI/AHB

Definition at line 1402 of file stm32f769xx.h.

#define SRAM1_BASE   0x20020000U

Base address of : 368KB RAM1 accessible over AXI/AHB

Definition at line 1471 of file stm32f779xx.h.

#define SRAM2_BASE   0x2004C000U

Base address of : 16KB RAM2 accessible over AXI/AHB

Definition at line 1110 of file stm32f745xx.h.

#define SRAM2_BASE   0x2004C000U

Base address of : 16KB RAM2 accessible over AXI/AHB

Definition at line 1159 of file stm32f746xx.h.

#define SRAM2_BASE   0x2004C000U

Base address of : 16KB RAM2 accessible over AXI/AHB

Definition at line 1228 of file stm32f756xx.h.

#define SRAM2_BASE   0x2007C000U

Base address of : 16KB RAM2 accessible over AXI/AHB

Definition at line 1236 of file stm32f765xx.h.

#define SRAM2_BASE   0x2007C000U

Base address of : 16KB RAM2 accessible over AXI/AHB

Definition at line 1322 of file stm32f767xx.h.

#define SRAM2_BASE   0x2007C000U

Base address of : 16KB RAM2 accessible over AXI/AHB

Definition at line 1391 of file stm32f777xx.h.

#define SRAM2_BASE   0x2007C000U

Base address of : 16KB RAM2 accessible over AXI/AHB

Definition at line 1403 of file stm32f769xx.h.

#define SRAM2_BASE   0x2007C000U

Base address of : 16KB RAM2 accessible over AXI/AHB

Definition at line 1472 of file stm32f779xx.h.

#define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800U)

Definition at line 1167 of file stm32f745xx.h.

#define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800U)

Definition at line 1216 of file stm32f746xx.h.

#define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800U)

Definition at line 1285 of file stm32f756xx.h.

#define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800U)

Definition at line 1295 of file stm32f765xx.h.

#define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800U)

Definition at line 1381 of file stm32f767xx.h.

#define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800U)

Definition at line 1450 of file stm32f777xx.h.

#define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800U)

Definition at line 1462 of file stm32f769xx.h.

#define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800U)

Definition at line 1531 of file stm32f779xx.h.

#define TIM10_BASE   (APB2PERIPH_BASE + 0x4400U)

Definition at line 1170 of file stm32f745xx.h.

#define TIM10_BASE   (APB2PERIPH_BASE + 0x4400U)

Definition at line 1219 of file stm32f746xx.h.

#define TIM10_BASE   (APB2PERIPH_BASE + 0x4400U)

Definition at line 1288 of file stm32f756xx.h.

#define TIM10_BASE   (APB2PERIPH_BASE + 0x4400U)

Definition at line 1298 of file stm32f765xx.h.

#define TIM10_BASE   (APB2PERIPH_BASE + 0x4400U)

Definition at line 1384 of file stm32f767xx.h.

#define TIM10_BASE   (APB2PERIPH_BASE + 0x4400U)

Definition at line 1453 of file stm32f777xx.h.

#define TIM10_BASE   (APB2PERIPH_BASE + 0x4400U)

Definition at line 1465 of file stm32f769xx.h.

#define TIM10_BASE   (APB2PERIPH_BASE + 0x4400U)

Definition at line 1534 of file stm32f779xx.h.

#define TIM11_BASE   (APB2PERIPH_BASE + 0x4800U)

Definition at line 1171 of file stm32f745xx.h.

#define TIM11_BASE   (APB2PERIPH_BASE + 0x4800U)

Definition at line 1220 of file stm32f746xx.h.

#define TIM11_BASE   (APB2PERIPH_BASE + 0x4800U)

Definition at line 1289 of file stm32f756xx.h.

#define TIM11_BASE   (APB2PERIPH_BASE + 0x4800U)

Definition at line 1299 of file stm32f765xx.h.

#define TIM11_BASE   (APB2PERIPH_BASE + 0x4800U)

Definition at line 1385 of file stm32f767xx.h.

#define TIM11_BASE   (APB2PERIPH_BASE + 0x4800U)

Definition at line 1454 of file stm32f777xx.h.

#define TIM11_BASE   (APB2PERIPH_BASE + 0x4800U)

Definition at line 1466 of file stm32f769xx.h.

#define TIM11_BASE   (APB2PERIPH_BASE + 0x4800U)

Definition at line 1535 of file stm32f779xx.h.

#define TIM12_BASE   (APB1PERIPH_BASE + 0x1800U)

Definition at line 1129 of file stm32f745xx.h.

#define TIM12_BASE   (APB1PERIPH_BASE + 0x1800U)

Definition at line 1178 of file stm32f746xx.h.

#define TIM12_BASE   (APB1PERIPH_BASE + 0x1800U)

Definition at line 1247 of file stm32f756xx.h.

#define TIM12_BASE   (APB1PERIPH_BASE + 0x1800U)

Definition at line 1255 of file stm32f765xx.h.

#define TIM12_BASE   (APB1PERIPH_BASE + 0x1800U)

Definition at line 1341 of file stm32f767xx.h.

#define TIM12_BASE   (APB1PERIPH_BASE + 0x1800U)

Definition at line 1410 of file stm32f777xx.h.

#define TIM12_BASE   (APB1PERIPH_BASE + 0x1800U)

Definition at line 1422 of file stm32f769xx.h.

#define TIM12_BASE   (APB1PERIPH_BASE + 0x1800U)

Definition at line 1491 of file stm32f779xx.h.

#define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00U)

Definition at line 1130 of file stm32f745xx.h.

#define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00U)

Definition at line 1179 of file stm32f746xx.h.

#define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00U)

Definition at line 1248 of file stm32f756xx.h.

#define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00U)

Definition at line 1256 of file stm32f765xx.h.

#define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00U)

Definition at line 1342 of file stm32f767xx.h.

#define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00U)

Definition at line 1411 of file stm32f777xx.h.

#define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00U)

Definition at line 1423 of file stm32f769xx.h.

#define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00U)

Definition at line 1492 of file stm32f779xx.h.

#define TIM14_BASE   (APB1PERIPH_BASE + 0x2000U)

Definition at line 1131 of file stm32f745xx.h.

#define TIM14_BASE   (APB1PERIPH_BASE + 0x2000U)

Definition at line 1180 of file stm32f746xx.h.

#define TIM14_BASE   (APB1PERIPH_BASE + 0x2000U)

Definition at line 1249 of file stm32f756xx.h.

#define TIM14_BASE   (APB1PERIPH_BASE + 0x2000U)

Definition at line 1257 of file stm32f765xx.h.

#define TIM14_BASE   (APB1PERIPH_BASE + 0x2000U)

Definition at line 1343 of file stm32f767xx.h.

#define TIM14_BASE   (APB1PERIPH_BASE + 0x2000U)

Definition at line 1412 of file stm32f777xx.h.

#define TIM14_BASE   (APB1PERIPH_BASE + 0x2000U)

Definition at line 1424 of file stm32f769xx.h.

#define TIM14_BASE   (APB1PERIPH_BASE + 0x2000U)

Definition at line 1493 of file stm32f779xx.h.

#define TIM1_BASE   (APB2PERIPH_BASE + 0x0000U)

Definition at line 1156 of file stm32f745xx.h.

#define TIM1_BASE   (APB2PERIPH_BASE + 0x0000U)

Definition at line 1205 of file stm32f746xx.h.

#define TIM1_BASE   (APB2PERIPH_BASE + 0x0000U)

Definition at line 1274 of file stm32f756xx.h.

#define TIM1_BASE   (APB2PERIPH_BASE + 0x0000U)

Definition at line 1283 of file stm32f765xx.h.

#define TIM1_BASE   (APB2PERIPH_BASE + 0x0000U)

Definition at line 1369 of file stm32f767xx.h.

#define TIM1_BASE   (APB2PERIPH_BASE + 0x0000U)

Definition at line 1438 of file stm32f777xx.h.

#define TIM1_BASE   (APB2PERIPH_BASE + 0x0000U)

Definition at line 1450 of file stm32f769xx.h.

#define TIM1_BASE   (APB2PERIPH_BASE + 0x0000U)

Definition at line 1519 of file stm32f779xx.h.

#define TIM2_BASE   (APB1PERIPH_BASE + 0x0000U)

Definition at line 1123 of file stm32f745xx.h.

#define TIM2_BASE   (APB1PERIPH_BASE + 0x0000U)

Definition at line 1172 of file stm32f746xx.h.

#define TIM2_BASE   (APB1PERIPH_BASE + 0x0000U)

Definition at line 1241 of file stm32f756xx.h.

#define TIM2_BASE   (APB1PERIPH_BASE + 0x0000U)

Definition at line 1249 of file stm32f765xx.h.

#define TIM2_BASE   (APB1PERIPH_BASE + 0x0000U)

Definition at line 1335 of file stm32f767xx.h.

#define TIM2_BASE   (APB1PERIPH_BASE + 0x0000U)

Definition at line 1404 of file stm32f777xx.h.

#define TIM2_BASE   (APB1PERIPH_BASE + 0x0000U)

Definition at line 1416 of file stm32f769xx.h.

#define TIM2_BASE   (APB1PERIPH_BASE + 0x0000U)

Definition at line 1485 of file stm32f779xx.h.

#define TIM3_BASE   (APB1PERIPH_BASE + 0x0400U)

Definition at line 1124 of file stm32f745xx.h.

#define TIM3_BASE   (APB1PERIPH_BASE + 0x0400U)

Definition at line 1173 of file stm32f746xx.h.

#define TIM3_BASE   (APB1PERIPH_BASE + 0x0400U)

Definition at line 1242 of file stm32f756xx.h.

#define TIM3_BASE   (APB1PERIPH_BASE + 0x0400U)

Definition at line 1250 of file stm32f765xx.h.

#define TIM3_BASE   (APB1PERIPH_BASE + 0x0400U)

Definition at line 1336 of file stm32f767xx.h.

#define TIM3_BASE   (APB1PERIPH_BASE + 0x0400U)

Definition at line 1405 of file stm32f777xx.h.

#define TIM3_BASE   (APB1PERIPH_BASE + 0x0400U)

Definition at line 1417 of file stm32f769xx.h.

#define TIM3_BASE   (APB1PERIPH_BASE + 0x0400U)

Definition at line 1486 of file stm32f779xx.h.

#define TIM4_BASE   (APB1PERIPH_BASE + 0x0800U)

Definition at line 1125 of file stm32f745xx.h.

#define TIM4_BASE   (APB1PERIPH_BASE + 0x0800U)

Definition at line 1174 of file stm32f746xx.h.

#define TIM4_BASE   (APB1PERIPH_BASE + 0x0800U)

Definition at line 1243 of file stm32f756xx.h.

#define TIM4_BASE   (APB1PERIPH_BASE + 0x0800U)

Definition at line 1251 of file stm32f765xx.h.

#define TIM4_BASE   (APB1PERIPH_BASE + 0x0800U)

Definition at line 1337 of file stm32f767xx.h.

#define TIM4_BASE   (APB1PERIPH_BASE + 0x0800U)

Definition at line 1406 of file stm32f777xx.h.

#define TIM4_BASE   (APB1PERIPH_BASE + 0x0800U)

Definition at line 1418 of file stm32f769xx.h.

#define TIM4_BASE   (APB1PERIPH_BASE + 0x0800U)

Definition at line 1487 of file stm32f779xx.h.

#define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00U)

Definition at line 1126 of file stm32f745xx.h.

#define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00U)

Definition at line 1175 of file stm32f746xx.h.

#define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00U)

Definition at line 1244 of file stm32f756xx.h.

#define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00U)

Definition at line 1252 of file stm32f765xx.h.

#define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00U)

Definition at line 1338 of file stm32f767xx.h.

#define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00U)

Definition at line 1407 of file stm32f777xx.h.

#define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00U)

Definition at line 1419 of file stm32f769xx.h.

#define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00U)

Definition at line 1488 of file stm32f779xx.h.

#define TIM6_BASE   (APB1PERIPH_BASE + 0x1000U)

Definition at line 1127 of file stm32f745xx.h.

#define TIM6_BASE   (APB1PERIPH_BASE + 0x1000U)

Definition at line 1176 of file stm32f746xx.h.

#define TIM6_BASE   (APB1PERIPH_BASE + 0x1000U)

Definition at line 1245 of file stm32f756xx.h.

#define TIM6_BASE   (APB1PERIPH_BASE + 0x1000U)

Definition at line 1253 of file stm32f765xx.h.

#define TIM6_BASE   (APB1PERIPH_BASE + 0x1000U)

Definition at line 1339 of file stm32f767xx.h.

#define TIM6_BASE   (APB1PERIPH_BASE + 0x1000U)

Definition at line 1408 of file stm32f777xx.h.

#define TIM6_BASE   (APB1PERIPH_BASE + 0x1000U)

Definition at line 1420 of file stm32f769xx.h.

#define TIM6_BASE   (APB1PERIPH_BASE + 0x1000U)

Definition at line 1489 of file stm32f779xx.h.

#define TIM7_BASE   (APB1PERIPH_BASE + 0x1400U)

Definition at line 1128 of file stm32f745xx.h.

#define TIM7_BASE   (APB1PERIPH_BASE + 0x1400U)

Definition at line 1177 of file stm32f746xx.h.

#define TIM7_BASE   (APB1PERIPH_BASE + 0x1400U)

Definition at line 1246 of file stm32f756xx.h.

#define TIM7_BASE   (APB1PERIPH_BASE + 0x1400U)

Definition at line 1254 of file stm32f765xx.h.

#define TIM7_BASE   (APB1PERIPH_BASE + 0x1400U)

Definition at line 1340 of file stm32f767xx.h.

#define TIM7_BASE   (APB1PERIPH_BASE + 0x1400U)

Definition at line 1409 of file stm32f777xx.h.

#define TIM7_BASE   (APB1PERIPH_BASE + 0x1400U)

Definition at line 1421 of file stm32f769xx.h.

#define TIM7_BASE   (APB1PERIPH_BASE + 0x1400U)

Definition at line 1490 of file stm32f779xx.h.

#define TIM8_BASE   (APB2PERIPH_BASE + 0x0400U)

Definition at line 1157 of file stm32f745xx.h.

#define TIM8_BASE   (APB2PERIPH_BASE + 0x0400U)

Definition at line 1206 of file stm32f746xx.h.

#define TIM8_BASE   (APB2PERIPH_BASE + 0x0400U)

Definition at line 1275 of file stm32f756xx.h.

#define TIM8_BASE   (APB2PERIPH_BASE + 0x0400U)

Definition at line 1284 of file stm32f765xx.h.

#define TIM8_BASE   (APB2PERIPH_BASE + 0x0400U)

Definition at line 1370 of file stm32f767xx.h.

#define TIM8_BASE   (APB2PERIPH_BASE + 0x0400U)

Definition at line 1439 of file stm32f777xx.h.

#define TIM8_BASE   (APB2PERIPH_BASE + 0x0400U)

Definition at line 1451 of file stm32f769xx.h.

#define TIM8_BASE   (APB2PERIPH_BASE + 0x0400U)

Definition at line 1520 of file stm32f779xx.h.

#define TIM9_BASE   (APB2PERIPH_BASE + 0x4000U)

Definition at line 1169 of file stm32f745xx.h.

#define TIM9_BASE   (APB2PERIPH_BASE + 0x4000U)

Definition at line 1218 of file stm32f746xx.h.

#define TIM9_BASE   (APB2PERIPH_BASE + 0x4000U)

Definition at line 1287 of file stm32f756xx.h.

#define TIM9_BASE   (APB2PERIPH_BASE + 0x4000U)

Definition at line 1297 of file stm32f765xx.h.

#define TIM9_BASE   (APB2PERIPH_BASE + 0x4000U)

Definition at line 1383 of file stm32f767xx.h.

#define TIM9_BASE   (APB2PERIPH_BASE + 0x4000U)

Definition at line 1452 of file stm32f777xx.h.

#define TIM9_BASE   (APB2PERIPH_BASE + 0x4000U)

Definition at line 1464 of file stm32f769xx.h.

#define TIM9_BASE   (APB2PERIPH_BASE + 0x4000U)

Definition at line 1533 of file stm32f779xx.h.

#define UART4_BASE   (APB1PERIPH_BASE + 0x4C00U)

Definition at line 1141 of file stm32f745xx.h.

#define UART4_BASE   (APB1PERIPH_BASE + 0x4C00U)

Definition at line 1190 of file stm32f746xx.h.

#define UART4_BASE   (APB1PERIPH_BASE + 0x4C00U)

Definition at line 1259 of file stm32f756xx.h.

#define UART4_BASE   (APB1PERIPH_BASE + 0x4C00U)

Definition at line 1268 of file stm32f765xx.h.

#define UART4_BASE   (APB1PERIPH_BASE + 0x4C00U)

Definition at line 1354 of file stm32f767xx.h.

#define UART4_BASE   (APB1PERIPH_BASE + 0x4C00U)

Definition at line 1423 of file stm32f777xx.h.

#define UART4_BASE   (APB1PERIPH_BASE + 0x4C00U)

Definition at line 1435 of file stm32f769xx.h.

#define UART4_BASE   (APB1PERIPH_BASE + 0x4C00U)

Definition at line 1504 of file stm32f779xx.h.

#define UART5_BASE   (APB1PERIPH_BASE + 0x5000U)

Definition at line 1142 of file stm32f745xx.h.

#define UART5_BASE   (APB1PERIPH_BASE + 0x5000U)

Definition at line 1191 of file stm32f746xx.h.

#define UART5_BASE   (APB1PERIPH_BASE + 0x5000U)

Definition at line 1260 of file stm32f756xx.h.

#define UART5_BASE   (APB1PERIPH_BASE + 0x5000U)

Definition at line 1269 of file stm32f765xx.h.

#define UART5_BASE   (APB1PERIPH_BASE + 0x5000U)

Definition at line 1355 of file stm32f767xx.h.

#define UART5_BASE   (APB1PERIPH_BASE + 0x5000U)

Definition at line 1424 of file stm32f777xx.h.

#define UART5_BASE   (APB1PERIPH_BASE + 0x5000U)

Definition at line 1436 of file stm32f769xx.h.

#define UART5_BASE   (APB1PERIPH_BASE + 0x5000U)

Definition at line 1505 of file stm32f779xx.h.

#define UART7_BASE   (APB1PERIPH_BASE + 0x7800U)

Definition at line 1152 of file stm32f745xx.h.

#define UART7_BASE   (APB1PERIPH_BASE + 0x7800U)

Definition at line 1201 of file stm32f746xx.h.

#define UART7_BASE   (APB1PERIPH_BASE + 0x7800U)

Definition at line 1270 of file stm32f756xx.h.

#define UART7_BASE   (APB1PERIPH_BASE + 0x7800U)

Definition at line 1279 of file stm32f765xx.h.

#define UART7_BASE   (APB1PERIPH_BASE + 0x7800U)

Definition at line 1365 of file stm32f767xx.h.

#define UART7_BASE   (APB1PERIPH_BASE + 0x7800U)

Definition at line 1434 of file stm32f777xx.h.

#define UART7_BASE   (APB1PERIPH_BASE + 0x7800U)

Definition at line 1446 of file stm32f769xx.h.

#define UART7_BASE   (APB1PERIPH_BASE + 0x7800U)

Definition at line 1515 of file stm32f779xx.h.

#define UART8_BASE   (APB1PERIPH_BASE + 0x7C00U)

APB2 peripherals

Definition at line 1153 of file stm32f745xx.h.

#define UART8_BASE   (APB1PERIPH_BASE + 0x7C00U)

APB2 peripherals

Definition at line 1202 of file stm32f746xx.h.

#define UART8_BASE   (APB1PERIPH_BASE + 0x7C00U)

APB2 peripherals

Definition at line 1271 of file stm32f756xx.h.

#define UART8_BASE   (APB1PERIPH_BASE + 0x7C00U)

APB2 peripherals

Definition at line 1280 of file stm32f765xx.h.

#define UART8_BASE   (APB1PERIPH_BASE + 0x7C00U)

APB2 peripherals

Definition at line 1366 of file stm32f767xx.h.

#define UART8_BASE   (APB1PERIPH_BASE + 0x7C00U)

APB2 peripherals

Definition at line 1435 of file stm32f777xx.h.

#define UART8_BASE   (APB1PERIPH_BASE + 0x7C00U)

APB2 peripherals

Definition at line 1447 of file stm32f769xx.h.

#define UART8_BASE   (APB1PERIPH_BASE + 0x7C00U)

APB2 peripherals

Definition at line 1516 of file stm32f779xx.h.

#define UID_BASE   0x1FF0F420U

Unique device ID register base address

Definition at line 1195 of file stm32f745xx.h.

#define UID_BASE   0x1FF0F420U

Unique device ID register base address

Definition at line 1247 of file stm32f746xx.h.

#define UID_BASE   0x1FF0F420U

Unique device ID register base address

Definition at line 1316 of file stm32f756xx.h.

#define UID_BASE   0x1FF0F420U

Unique device ID register base address

Definition at line 1337 of file stm32f765xx.h.

#define UID_BASE   0x1FF0F420U

Unique device ID register base address

Definition at line 1426 of file stm32f767xx.h.

#define UID_BASE   0x1FF0F420U

Unique device ID register base address

Definition at line 1495 of file stm32f777xx.h.

#define UID_BASE   0x1FF0F420U

Unique device ID register base address

Definition at line 1508 of file stm32f769xx.h.

#define UID_BASE   0x1FF0F420U

Unique device ID register base address

Definition at line 1577 of file stm32f779xx.h.

#define USART1_BASE   (APB2PERIPH_BASE + 0x1000U)

Definition at line 1158 of file stm32f745xx.h.

#define USART1_BASE   (APB2PERIPH_BASE + 0x1000U)

Definition at line 1207 of file stm32f746xx.h.

#define USART1_BASE   (APB2PERIPH_BASE + 0x1000U)

Definition at line 1276 of file stm32f756xx.h.

#define USART1_BASE   (APB2PERIPH_BASE + 0x1000U)

Definition at line 1285 of file stm32f765xx.h.

#define USART1_BASE   (APB2PERIPH_BASE + 0x1000U)

Definition at line 1371 of file stm32f767xx.h.

#define USART1_BASE   (APB2PERIPH_BASE + 0x1000U)

Definition at line 1440 of file stm32f777xx.h.

#define USART1_BASE   (APB2PERIPH_BASE + 0x1000U)

Definition at line 1452 of file stm32f769xx.h.

#define USART1_BASE   (APB2PERIPH_BASE + 0x1000U)

Definition at line 1521 of file stm32f779xx.h.

#define USART2_BASE   (APB1PERIPH_BASE + 0x4400U)

Definition at line 1139 of file stm32f745xx.h.

#define USART2_BASE   (APB1PERIPH_BASE + 0x4400U)

Definition at line 1188 of file stm32f746xx.h.

#define USART2_BASE   (APB1PERIPH_BASE + 0x4400U)

Definition at line 1257 of file stm32f756xx.h.

#define USART2_BASE   (APB1PERIPH_BASE + 0x4400U)

Definition at line 1266 of file stm32f765xx.h.

#define USART2_BASE   (APB1PERIPH_BASE + 0x4400U)

Definition at line 1352 of file stm32f767xx.h.

#define USART2_BASE   (APB1PERIPH_BASE + 0x4400U)

Definition at line 1421 of file stm32f777xx.h.

#define USART2_BASE   (APB1PERIPH_BASE + 0x4400U)

Definition at line 1433 of file stm32f769xx.h.

#define USART2_BASE   (APB1PERIPH_BASE + 0x4400U)

Definition at line 1502 of file stm32f779xx.h.

#define USART3_BASE   (APB1PERIPH_BASE + 0x4800U)

Definition at line 1140 of file stm32f745xx.h.

#define USART3_BASE   (APB1PERIPH_BASE + 0x4800U)

Definition at line 1189 of file stm32f746xx.h.

#define USART3_BASE   (APB1PERIPH_BASE + 0x4800U)

Definition at line 1258 of file stm32f756xx.h.

#define USART3_BASE   (APB1PERIPH_BASE + 0x4800U)

Definition at line 1267 of file stm32f765xx.h.

#define USART3_BASE   (APB1PERIPH_BASE + 0x4800U)

Definition at line 1353 of file stm32f767xx.h.

#define USART3_BASE   (APB1PERIPH_BASE + 0x4800U)

Definition at line 1422 of file stm32f777xx.h.

#define USART3_BASE   (APB1PERIPH_BASE + 0x4800U)

Definition at line 1434 of file stm32f769xx.h.

#define USART3_BASE   (APB1PERIPH_BASE + 0x4800U)

Definition at line 1503 of file stm32f779xx.h.

#define USART6_BASE   (APB2PERIPH_BASE + 0x1400U)

Definition at line 1159 of file stm32f745xx.h.

#define USART6_BASE   (APB2PERIPH_BASE + 0x1400U)

Definition at line 1208 of file stm32f746xx.h.

#define USART6_BASE   (APB2PERIPH_BASE + 0x1400U)

Definition at line 1277 of file stm32f756xx.h.

#define USART6_BASE   (APB2PERIPH_BASE + 0x1400U)

Definition at line 1286 of file stm32f765xx.h.

#define USART6_BASE   (APB2PERIPH_BASE + 0x1400U)

Definition at line 1372 of file stm32f767xx.h.

#define USART6_BASE   (APB2PERIPH_BASE + 0x1400U)

Definition at line 1441 of file stm32f777xx.h.

#define USART6_BASE   (APB2PERIPH_BASE + 0x1400U)

Definition at line 1453 of file stm32f769xx.h.

#define USART6_BASE   (APB2PERIPH_BASE + 0x1400U)

Definition at line 1522 of file stm32f779xx.h.

#define USB_OTG_DEVICE_BASE   0x800U

Definition at line 1239 of file stm32f745xx.h.

#define USB_OTG_DEVICE_BASE   0x800U

Definition at line 1291 of file stm32f746xx.h.

#define USB_OTG_DEVICE_BASE   0x800U

Definition at line 1363 of file stm32f756xx.h.

#define USB_OTG_DEVICE_BASE   0x800U

Definition at line 1381 of file stm32f765xx.h.

#define USB_OTG_DEVICE_BASE   0x800U

Definition at line 1471 of file stm32f767xx.h.

#define USB_OTG_DEVICE_BASE   0x800U

Definition at line 1543 of file stm32f777xx.h.

#define USB_OTG_DEVICE_BASE   0x800U

Definition at line 1553 of file stm32f769xx.h.

#define USB_OTG_DEVICE_BASE   0x800U

Definition at line 1625 of file stm32f779xx.h.

#define USB_OTG_EP_REG_SIZE   0x20U

Definition at line 1242 of file stm32f745xx.h.

#define USB_OTG_EP_REG_SIZE   0x20U

Definition at line 1294 of file stm32f746xx.h.

#define USB_OTG_EP_REG_SIZE   0x20U

Definition at line 1366 of file stm32f756xx.h.

#define USB_OTG_EP_REG_SIZE   0x20U

Definition at line 1384 of file stm32f765xx.h.

#define USB_OTG_EP_REG_SIZE   0x20U

Definition at line 1474 of file stm32f767xx.h.

#define USB_OTG_EP_REG_SIZE   0x20U

Definition at line 1546 of file stm32f777xx.h.

#define USB_OTG_EP_REG_SIZE   0x20U

Definition at line 1556 of file stm32f769xx.h.

#define USB_OTG_EP_REG_SIZE   0x20U

Definition at line 1628 of file stm32f779xx.h.

#define USB_OTG_FIFO_BASE   0x1000U

Definition at line 1248 of file stm32f745xx.h.

#define USB_OTG_FIFO_BASE   0x1000U

Definition at line 1300 of file stm32f746xx.h.

#define USB_OTG_FIFO_BASE   0x1000U

Definition at line 1372 of file stm32f756xx.h.

#define USB_OTG_FIFO_BASE   0x1000U

Definition at line 1390 of file stm32f765xx.h.

#define USB_OTG_FIFO_BASE   0x1000U

Definition at line 1480 of file stm32f767xx.h.

#define USB_OTG_FIFO_BASE   0x1000U

Definition at line 1552 of file stm32f777xx.h.

#define USB_OTG_FIFO_BASE   0x1000U

Definition at line 1562 of file stm32f769xx.h.

#define USB_OTG_FIFO_BASE   0x1000U

Definition at line 1634 of file stm32f779xx.h.

#define USB_OTG_FIFO_SIZE   0x1000U

Definition at line 1249 of file stm32f745xx.h.

#define USB_OTG_FIFO_SIZE   0x1000U

Definition at line 1301 of file stm32f746xx.h.

#define USB_OTG_FIFO_SIZE   0x1000U

Definition at line 1373 of file stm32f756xx.h.

#define USB_OTG_FIFO_SIZE   0x1000U

Definition at line 1391 of file stm32f765xx.h.

#define USB_OTG_FIFO_SIZE   0x1000U

Definition at line 1481 of file stm32f767xx.h.

#define USB_OTG_FIFO_SIZE   0x1000U

Definition at line 1553 of file stm32f777xx.h.

#define USB_OTG_FIFO_SIZE   0x1000U

Definition at line 1563 of file stm32f769xx.h.

#define USB_OTG_FIFO_SIZE   0x1000U

Definition at line 1635 of file stm32f779xx.h.

#define USB_OTG_FS_PERIPH_BASE   0x50000000U

Definition at line 1236 of file stm32f745xx.h.

#define USB_OTG_FS_PERIPH_BASE   0x50000000U

Definition at line 1288 of file stm32f746xx.h.

#define USB_OTG_FS_PERIPH_BASE   0x50000000U

Definition at line 1360 of file stm32f756xx.h.

#define USB_OTG_FS_PERIPH_BASE   0x50000000U

Definition at line 1378 of file stm32f765xx.h.

#define USB_OTG_FS_PERIPH_BASE   0x50000000U

Definition at line 1468 of file stm32f767xx.h.

#define USB_OTG_FS_PERIPH_BASE   0x50000000U

Definition at line 1540 of file stm32f777xx.h.

#define USB_OTG_FS_PERIPH_BASE   0x50000000U

Definition at line 1550 of file stm32f769xx.h.

#define USB_OTG_FS_PERIPH_BASE   0x50000000U

Definition at line 1622 of file stm32f779xx.h.

#define USB_OTG_GLOBAL_BASE   0x000U

Definition at line 1238 of file stm32f745xx.h.

#define USB_OTG_GLOBAL_BASE   0x000U

Definition at line 1290 of file stm32f746xx.h.

#define USB_OTG_GLOBAL_BASE   0x000U

Definition at line 1362 of file stm32f756xx.h.

#define USB_OTG_GLOBAL_BASE   0x000U

Definition at line 1380 of file stm32f765xx.h.

#define USB_OTG_GLOBAL_BASE   0x000U

Definition at line 1470 of file stm32f767xx.h.

#define USB_OTG_GLOBAL_BASE   0x000U

Definition at line 1542 of file stm32f777xx.h.

#define USB_OTG_GLOBAL_BASE   0x000U

Definition at line 1552 of file stm32f769xx.h.

#define USB_OTG_GLOBAL_BASE   0x000U

Definition at line 1624 of file stm32f779xx.h.

#define USB_OTG_HOST_BASE   0x400U

Definition at line 1243 of file stm32f745xx.h.

#define USB_OTG_HOST_BASE   0x400U

Definition at line 1295 of file stm32f746xx.h.

#define USB_OTG_HOST_BASE   0x400U

Definition at line 1367 of file stm32f756xx.h.

#define USB_OTG_HOST_BASE   0x400U

Definition at line 1385 of file stm32f765xx.h.

#define USB_OTG_HOST_BASE   0x400U

Definition at line 1475 of file stm32f767xx.h.

#define USB_OTG_HOST_BASE   0x400U

Definition at line 1547 of file stm32f777xx.h.

#define USB_OTG_HOST_BASE   0x400U

Definition at line 1557 of file stm32f769xx.h.

#define USB_OTG_HOST_BASE   0x400U

Definition at line 1629 of file stm32f779xx.h.

#define USB_OTG_HOST_CHANNEL_BASE   0x500U

Definition at line 1245 of file stm32f745xx.h.

#define USB_OTG_HOST_CHANNEL_BASE   0x500U

Definition at line 1297 of file stm32f746xx.h.

#define USB_OTG_HOST_CHANNEL_BASE   0x500U

Definition at line 1369 of file stm32f756xx.h.

#define USB_OTG_HOST_CHANNEL_BASE   0x500U

Definition at line 1387 of file stm32f765xx.h.

#define USB_OTG_HOST_CHANNEL_BASE   0x500U

Definition at line 1477 of file stm32f767xx.h.

#define USB_OTG_HOST_CHANNEL_BASE   0x500U

Definition at line 1549 of file stm32f777xx.h.

#define USB_OTG_HOST_CHANNEL_BASE   0x500U

Definition at line 1559 of file stm32f769xx.h.

#define USB_OTG_HOST_CHANNEL_BASE   0x500U

Definition at line 1631 of file stm32f779xx.h.

#define USB_OTG_HOST_CHANNEL_SIZE   0x20U

Definition at line 1246 of file stm32f745xx.h.

#define USB_OTG_HOST_CHANNEL_SIZE   0x20U

Definition at line 1298 of file stm32f746xx.h.

#define USB_OTG_HOST_CHANNEL_SIZE   0x20U

Definition at line 1370 of file stm32f756xx.h.

#define USB_OTG_HOST_CHANNEL_SIZE   0x20U

Definition at line 1388 of file stm32f765xx.h.

#define USB_OTG_HOST_CHANNEL_SIZE   0x20U

Definition at line 1478 of file stm32f767xx.h.

#define USB_OTG_HOST_CHANNEL_SIZE   0x20U

Definition at line 1550 of file stm32f777xx.h.

#define USB_OTG_HOST_CHANNEL_SIZE   0x20U

Definition at line 1560 of file stm32f769xx.h.

#define USB_OTG_HOST_CHANNEL_SIZE   0x20U

Definition at line 1632 of file stm32f779xx.h.

#define USB_OTG_HOST_PORT_BASE   0x440U

Definition at line 1244 of file stm32f745xx.h.

#define USB_OTG_HOST_PORT_BASE   0x440U

Definition at line 1296 of file stm32f746xx.h.

#define USB_OTG_HOST_PORT_BASE   0x440U

Definition at line 1368 of file stm32f756xx.h.

#define USB_OTG_HOST_PORT_BASE   0x440U

Definition at line 1386 of file stm32f765xx.h.

#define USB_OTG_HOST_PORT_BASE   0x440U

Definition at line 1476 of file stm32f767xx.h.

#define USB_OTG_HOST_PORT_BASE   0x440U

Definition at line 1548 of file stm32f777xx.h.

#define USB_OTG_HOST_PORT_BASE   0x440U

Definition at line 1558 of file stm32f769xx.h.

#define USB_OTG_HOST_PORT_BASE   0x440U

Definition at line 1630 of file stm32f779xx.h.

#define USB_OTG_HS_PERIPH_BASE   0x40040000U

Definition at line 1235 of file stm32f745xx.h.

#define USB_OTG_HS_PERIPH_BASE   0x40040000U

Definition at line 1287 of file stm32f746xx.h.

#define USB_OTG_HS_PERIPH_BASE   0x40040000U

Definition at line 1359 of file stm32f756xx.h.

#define USB_OTG_HS_PERIPH_BASE   0x40040000U

Definition at line 1377 of file stm32f765xx.h.

#define USB_OTG_HS_PERIPH_BASE   0x40040000U

Definition at line 1467 of file stm32f767xx.h.

#define USB_OTG_HS_PERIPH_BASE   0x40040000U

Definition at line 1539 of file stm32f777xx.h.

#define USB_OTG_HS_PERIPH_BASE   0x40040000U

Definition at line 1549 of file stm32f769xx.h.

#define USB_OTG_HS_PERIPH_BASE   0x40040000U

Definition at line 1621 of file stm32f779xx.h.

#define USB_OTG_IN_ENDPOINT_BASE   0x900U

Definition at line 1240 of file stm32f745xx.h.

#define USB_OTG_IN_ENDPOINT_BASE   0x900U

Definition at line 1292 of file stm32f746xx.h.

#define USB_OTG_IN_ENDPOINT_BASE   0x900U

Definition at line 1364 of file stm32f756xx.h.

#define USB_OTG_IN_ENDPOINT_BASE   0x900U

Definition at line 1382 of file stm32f765xx.h.

#define USB_OTG_IN_ENDPOINT_BASE   0x900U

Definition at line 1472 of file stm32f767xx.h.

#define USB_OTG_IN_ENDPOINT_BASE   0x900U

Definition at line 1544 of file stm32f777xx.h.

#define USB_OTG_IN_ENDPOINT_BASE   0x900U

Definition at line 1554 of file stm32f769xx.h.

#define USB_OTG_IN_ENDPOINT_BASE   0x900U

Definition at line 1626 of file stm32f779xx.h.

#define USB_OTG_OUT_ENDPOINT_BASE   0xB00U

Definition at line 1241 of file stm32f745xx.h.

#define USB_OTG_OUT_ENDPOINT_BASE   0xB00U

Definition at line 1293 of file stm32f746xx.h.

#define USB_OTG_OUT_ENDPOINT_BASE   0xB00U

Definition at line 1365 of file stm32f756xx.h.

#define USB_OTG_OUT_ENDPOINT_BASE   0xB00U

Definition at line 1383 of file stm32f765xx.h.

#define USB_OTG_OUT_ENDPOINT_BASE   0xB00U

Definition at line 1473 of file stm32f767xx.h.

#define USB_OTG_OUT_ENDPOINT_BASE   0xB00U

Definition at line 1545 of file stm32f777xx.h.

#define USB_OTG_OUT_ENDPOINT_BASE   0xB00U

Definition at line 1555 of file stm32f769xx.h.

#define USB_OTG_OUT_ENDPOINT_BASE   0xB00U

Definition at line 1627 of file stm32f779xx.h.

#define USB_OTG_PCGCCTL_BASE   0xE00U

Definition at line 1247 of file stm32f745xx.h.

#define USB_OTG_PCGCCTL_BASE   0xE00U

Definition at line 1299 of file stm32f746xx.h.

#define USB_OTG_PCGCCTL_BASE   0xE00U

Definition at line 1371 of file stm32f756xx.h.

#define USB_OTG_PCGCCTL_BASE   0xE00U

Definition at line 1389 of file stm32f765xx.h.

#define USB_OTG_PCGCCTL_BASE   0xE00U

Definition at line 1479 of file stm32f767xx.h.

#define USB_OTG_PCGCCTL_BASE   0xE00U

Definition at line 1551 of file stm32f777xx.h.

#define USB_OTG_PCGCCTL_BASE   0xE00U

Definition at line 1561 of file stm32f769xx.h.

#define USB_OTG_PCGCCTL_BASE   0xE00U

Definition at line 1633 of file stm32f779xx.h.

#define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00U)

Definition at line 1134 of file stm32f745xx.h.

#define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00U)

Definition at line 1183 of file stm32f746xx.h.

#define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00U)

Definition at line 1252 of file stm32f756xx.h.

#define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00U)

Definition at line 1260 of file stm32f765xx.h.

#define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00U)

Definition at line 1346 of file stm32f767xx.h.

#define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00U)

Definition at line 1415 of file stm32f777xx.h.

#define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00U)

Definition at line 1427 of file stm32f769xx.h.

#define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00U)

Definition at line 1496 of file stm32f779xx.h.

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