STM32F769IDiscovery  1.00
uDANTE Audio Networking with STM32F7 DISCO board
stm32f746xx.h
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1 
52 #ifndef __STM32F746xx_H
53 #define __STM32F746xx_H
54 
55 #ifdef __cplusplus
56  extern "C" {
57 #endif /* __cplusplus */
58 
67 typedef enum
68 {
69 /****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/
70  NonMaskableInt_IRQn = -14,
71  MemoryManagement_IRQn = -12,
72  BusFault_IRQn = -11,
73  UsageFault_IRQn = -10,
74  SVCall_IRQn = -5,
75  DebugMonitor_IRQn = -4,
76  PendSV_IRQn = -2,
77  SysTick_IRQn = -1,
78 /****** STM32 specific Interrupt Numbers **********************************************************************/
79  WWDG_IRQn = 0,
80  PVD_IRQn = 1,
81  TAMP_STAMP_IRQn = 2,
82  RTC_WKUP_IRQn = 3,
83  FLASH_IRQn = 4,
84  RCC_IRQn = 5,
85  EXTI0_IRQn = 6,
86  EXTI1_IRQn = 7,
87  EXTI2_IRQn = 8,
88  EXTI3_IRQn = 9,
89  EXTI4_IRQn = 10,
90  DMA1_Stream0_IRQn = 11,
91  DMA1_Stream1_IRQn = 12,
92  DMA1_Stream2_IRQn = 13,
93  DMA1_Stream3_IRQn = 14,
94  DMA1_Stream4_IRQn = 15,
95  DMA1_Stream5_IRQn = 16,
96  DMA1_Stream6_IRQn = 17,
97  ADC_IRQn = 18,
98  CAN1_TX_IRQn = 19,
99  CAN1_RX0_IRQn = 20,
100  CAN1_RX1_IRQn = 21,
101  CAN1_SCE_IRQn = 22,
102  EXTI9_5_IRQn = 23,
103  TIM1_BRK_TIM9_IRQn = 24,
104  TIM1_UP_TIM10_IRQn = 25,
105  TIM1_TRG_COM_TIM11_IRQn = 26,
106  TIM1_CC_IRQn = 27,
107  TIM2_IRQn = 28,
108  TIM3_IRQn = 29,
109  TIM4_IRQn = 30,
110  I2C1_EV_IRQn = 31,
111  I2C1_ER_IRQn = 32,
112  I2C2_EV_IRQn = 33,
113  I2C2_ER_IRQn = 34,
114  SPI1_IRQn = 35,
115  SPI2_IRQn = 36,
116  USART1_IRQn = 37,
117  USART2_IRQn = 38,
118  USART3_IRQn = 39,
119  EXTI15_10_IRQn = 40,
120  RTC_Alarm_IRQn = 41,
121  OTG_FS_WKUP_IRQn = 42,
122  TIM8_BRK_TIM12_IRQn = 43,
123  TIM8_UP_TIM13_IRQn = 44,
124  TIM8_TRG_COM_TIM14_IRQn = 45,
125  TIM8_CC_IRQn = 46,
126  DMA1_Stream7_IRQn = 47,
127  FMC_IRQn = 48,
128  SDMMC1_IRQn = 49,
129  TIM5_IRQn = 50,
130  SPI3_IRQn = 51,
131  UART4_IRQn = 52,
132  UART5_IRQn = 53,
133  TIM6_DAC_IRQn = 54,
134  TIM7_IRQn = 55,
135  DMA2_Stream0_IRQn = 56,
136  DMA2_Stream1_IRQn = 57,
137  DMA2_Stream2_IRQn = 58,
138  DMA2_Stream3_IRQn = 59,
139  DMA2_Stream4_IRQn = 60,
140  ETH_IRQn = 61,
141  ETH_WKUP_IRQn = 62,
142  CAN2_TX_IRQn = 63,
143  CAN2_RX0_IRQn = 64,
144  CAN2_RX1_IRQn = 65,
145  CAN2_SCE_IRQn = 66,
146  OTG_FS_IRQn = 67,
147  DMA2_Stream5_IRQn = 68,
148  DMA2_Stream6_IRQn = 69,
149  DMA2_Stream7_IRQn = 70,
150  USART6_IRQn = 71,
151  I2C3_EV_IRQn = 72,
152  I2C3_ER_IRQn = 73,
153  OTG_HS_EP1_OUT_IRQn = 74,
154  OTG_HS_EP1_IN_IRQn = 75,
155  OTG_HS_WKUP_IRQn = 76,
156  OTG_HS_IRQn = 77,
157  DCMI_IRQn = 78,
158  RNG_IRQn = 80,
159  FPU_IRQn = 81,
160  UART7_IRQn = 82,
161  UART8_IRQn = 83,
162  SPI4_IRQn = 84,
163  SPI5_IRQn = 85,
164  SPI6_IRQn = 86,
165  SAI1_IRQn = 87,
166  LTDC_IRQn = 88,
167  LTDC_ER_IRQn = 89,
168  DMA2D_IRQn = 90,
169  SAI2_IRQn = 91,
170  QUADSPI_IRQn = 92,
171  LPTIM1_IRQn = 93,
172  CEC_IRQn = 94,
173  I2C4_EV_IRQn = 95,
174  I2C4_ER_IRQn = 96,
175  SPDIF_RX_IRQn = 97,
176 } IRQn_Type;
177 
185 #define __CM7_REV 0x0001U
186 #define __MPU_PRESENT 1
187 #define __NVIC_PRIO_BITS 4
188 #define __Vendor_SysTickConfig 0
189 #define __FPU_PRESENT 1
190 #define __ICACHE_PRESENT 1
191 #define __DCACHE_PRESENT 1
192 #include "core_cm7.h"
195 #include "system_stm32f7xx.h"
196 #include <stdint.h>
197 
206 typedef struct
207 {
208  __IO uint32_t SR;
209  __IO uint32_t CR1;
210  __IO uint32_t CR2;
211  __IO uint32_t SMPR1;
212  __IO uint32_t SMPR2;
213  __IO uint32_t JOFR1;
214  __IO uint32_t JOFR2;
215  __IO uint32_t JOFR3;
216  __IO uint32_t JOFR4;
217  __IO uint32_t HTR;
218  __IO uint32_t LTR;
219  __IO uint32_t SQR1;
220  __IO uint32_t SQR2;
221  __IO uint32_t SQR3;
222  __IO uint32_t JSQR;
223  __IO uint32_t JDR1;
224  __IO uint32_t JDR2;
225  __IO uint32_t JDR3;
226  __IO uint32_t JDR4;
227  __IO uint32_t DR;
228 } ADC_TypeDef;
229 
230 typedef struct
231 {
232  __IO uint32_t CSR;
233  __IO uint32_t CCR;
234  __IO uint32_t CDR;
236 } ADC_Common_TypeDef;
237 
238 
243 typedef struct
244 {
245  __IO uint32_t TIR;
246  __IO uint32_t TDTR;
247  __IO uint32_t TDLR;
248  __IO uint32_t TDHR;
249 } CAN_TxMailBox_TypeDef;
250 
255 typedef struct
256 {
257  __IO uint32_t RIR;
258  __IO uint32_t RDTR;
259  __IO uint32_t RDLR;
260  __IO uint32_t RDHR;
261 } CAN_FIFOMailBox_TypeDef;
262 
267 typedef struct
268 {
269  __IO uint32_t FR1;
270  __IO uint32_t FR2;
271 } CAN_FilterRegister_TypeDef;
272 
277 typedef struct
278 {
279  __IO uint32_t MCR;
280  __IO uint32_t MSR;
281  __IO uint32_t TSR;
282  __IO uint32_t RF0R;
283  __IO uint32_t RF1R;
284  __IO uint32_t IER;
285  __IO uint32_t ESR;
286  __IO uint32_t BTR;
287  uint32_t RESERVED0[88];
288  CAN_TxMailBox_TypeDef sTxMailBox[3];
289  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
290  uint32_t RESERVED1[12];
291  __IO uint32_t FMR;
292  __IO uint32_t FM1R;
293  uint32_t RESERVED2;
294  __IO uint32_t FS1R;
295  uint32_t RESERVED3;
296  __IO uint32_t FFA1R;
297  uint32_t RESERVED4;
298  __IO uint32_t FA1R;
299  uint32_t RESERVED5[8];
300  CAN_FilterRegister_TypeDef sFilterRegister[28];
301 } CAN_TypeDef;
302 
307 typedef struct
308 {
309  __IO uint32_t CR;
310  __IO uint32_t CFGR;
311  __IO uint32_t TXDR;
312  __IO uint32_t RXDR;
313  __IO uint32_t ISR;
314  __IO uint32_t IER;
315 }CEC_TypeDef;
316 
317 
322 typedef struct
323 {
324  __IO uint32_t DR;
325  __IO uint8_t IDR;
326  uint8_t RESERVED0;
327  uint16_t RESERVED1;
328  __IO uint32_t CR;
329  uint32_t RESERVED2;
330  __IO uint32_t INIT;
331  __IO uint32_t POL;
332 } CRC_TypeDef;
333 
338 typedef struct
339 {
340  __IO uint32_t CR;
341  __IO uint32_t SWTRIGR;
342  __IO uint32_t DHR12R1;
343  __IO uint32_t DHR12L1;
344  __IO uint32_t DHR8R1;
345  __IO uint32_t DHR12R2;
346  __IO uint32_t DHR12L2;
347  __IO uint32_t DHR8R2;
348  __IO uint32_t DHR12RD;
349  __IO uint32_t DHR12LD;
350  __IO uint32_t DHR8RD;
351  __IO uint32_t DOR1;
352  __IO uint32_t DOR2;
353  __IO uint32_t SR;
354 } DAC_TypeDef;
355 
356 
361 typedef struct
362 {
363  __IO uint32_t IDCODE;
364  __IO uint32_t CR;
365  __IO uint32_t APB1FZ;
366  __IO uint32_t APB2FZ;
367 }DBGMCU_TypeDef;
368 
373 typedef struct
374 {
375  __IO uint32_t CR;
376  __IO uint32_t SR;
377  __IO uint32_t RISR;
378  __IO uint32_t IER;
379  __IO uint32_t MISR;
380  __IO uint32_t ICR;
381  __IO uint32_t ESCR;
382  __IO uint32_t ESUR;
383  __IO uint32_t CWSTRTR;
384  __IO uint32_t CWSIZER;
385  __IO uint32_t DR;
386 } DCMI_TypeDef;
387 
392 typedef struct
393 {
394  __IO uint32_t CR;
395  __IO uint32_t NDTR;
396  __IO uint32_t PAR;
397  __IO uint32_t M0AR;
398  __IO uint32_t M1AR;
399  __IO uint32_t FCR;
400 } DMA_Stream_TypeDef;
401 
402 typedef struct
403 {
404  __IO uint32_t LISR;
405  __IO uint32_t HISR;
406  __IO uint32_t LIFCR;
407  __IO uint32_t HIFCR;
408 } DMA_TypeDef;
409 
410 
415 typedef struct
416 {
417  __IO uint32_t CR;
418  __IO uint32_t ISR;
419  __IO uint32_t IFCR;
420  __IO uint32_t FGMAR;
421  __IO uint32_t FGOR;
422  __IO uint32_t BGMAR;
423  __IO uint32_t BGOR;
424  __IO uint32_t FGPFCCR;
425  __IO uint32_t FGCOLR;
426  __IO uint32_t BGPFCCR;
427  __IO uint32_t BGCOLR;
428  __IO uint32_t FGCMAR;
429  __IO uint32_t BGCMAR;
430  __IO uint32_t OPFCCR;
431  __IO uint32_t OCOLR;
432  __IO uint32_t OMAR;
433  __IO uint32_t OOR;
434  __IO uint32_t NLR;
435  __IO uint32_t LWR;
436  __IO uint32_t AMTCR;
437  uint32_t RESERVED[236];
438  __IO uint32_t FGCLUT[256];
439  __IO uint32_t BGCLUT[256];
440 } DMA2D_TypeDef;
441 
442 
447 typedef struct
448 {
449  __IO uint32_t MACCR;
450  __IO uint32_t MACFFR;
451  __IO uint32_t MACHTHR;
452  __IO uint32_t MACHTLR;
453  __IO uint32_t MACMIIAR;
454  __IO uint32_t MACMIIDR;
455  __IO uint32_t MACFCR;
456  __IO uint32_t MACVLANTR; /* 8 */
457  uint32_t RESERVED0[2];
458  __IO uint32_t MACRWUFFR; /* 11 */
459  __IO uint32_t MACPMTCSR;
460  uint32_t RESERVED1[2];
461  __IO uint32_t MACSR; /* 15 */
462  __IO uint32_t MACIMR;
463  __IO uint32_t MACA0HR;
464  __IO uint32_t MACA0LR;
465  __IO uint32_t MACA1HR;
466  __IO uint32_t MACA1LR;
467  __IO uint32_t MACA2HR;
468  __IO uint32_t MACA2LR;
469  __IO uint32_t MACA3HR;
470  __IO uint32_t MACA3LR; /* 24 */
471  uint32_t RESERVED2[40];
472  __IO uint32_t MMCCR; /* 65 */
473  __IO uint32_t MMCRIR;
474  __IO uint32_t MMCTIR;
475  __IO uint32_t MMCRIMR;
476  __IO uint32_t MMCTIMR; /* 69 */
477  uint32_t RESERVED3[14];
478  __IO uint32_t MMCTGFSCCR; /* 84 */
479  __IO uint32_t MMCTGFMSCCR;
480  uint32_t RESERVED4[5];
481  __IO uint32_t MMCTGFCR;
482  uint32_t RESERVED5[10];
483  __IO uint32_t MMCRFCECR;
484  __IO uint32_t MMCRFAECR;
485  uint32_t RESERVED6[10];
486  __IO uint32_t MMCRGUFCR;
487  uint32_t RESERVED7[334];
488  __IO uint32_t PTPTSCR;
489  __IO uint32_t PTPSSIR;
490  __IO uint32_t PTPTSHR;
491  __IO uint32_t PTPTSLR;
492  __IO uint32_t PTPTSHUR;
493  __IO uint32_t PTPTSLUR;
494  __IO uint32_t PTPTSAR;
495  __IO uint32_t PTPTTHR;
496  __IO uint32_t PTPTTLR;
497  __IO uint32_t RESERVED8;
498  __IO uint32_t PTPTSSR;
499  uint32_t RESERVED9[565];
500  __IO uint32_t DMABMR;
501  __IO uint32_t DMATPDR;
502  __IO uint32_t DMARPDR;
503  __IO uint32_t DMARDLAR;
504  __IO uint32_t DMATDLAR;
505  __IO uint32_t DMASR;
506  __IO uint32_t DMAOMR;
507  __IO uint32_t DMAIER;
508  __IO uint32_t DMAMFBOCR;
509  __IO uint32_t DMARSWTR;
510  uint32_t RESERVED10[8];
511  __IO uint32_t DMACHTDR;
512  __IO uint32_t DMACHRDR;
513  __IO uint32_t DMACHTBAR;
514  __IO uint32_t DMACHRBAR;
515 } ETH_TypeDef;
516 
521 typedef struct
522 {
523  __IO uint32_t IMR;
524  __IO uint32_t EMR;
525  __IO uint32_t RTSR;
526  __IO uint32_t FTSR;
527  __IO uint32_t SWIER;
528  __IO uint32_t PR;
529 } EXTI_TypeDef;
530 
535 typedef struct
536 {
537  __IO uint32_t ACR;
538  __IO uint32_t KEYR;
539  __IO uint32_t OPTKEYR;
540  __IO uint32_t SR;
541  __IO uint32_t CR;
542  __IO uint32_t OPTCR;
543  __IO uint32_t OPTCR1;
544 } FLASH_TypeDef;
545 
546 
547 
552 typedef struct
553 {
554  __IO uint32_t BTCR[8];
555 } FMC_Bank1_TypeDef;
556 
561 typedef struct
562 {
563  __IO uint32_t BWTR[7];
564 } FMC_Bank1E_TypeDef;
565 
570 typedef struct
571 {
572  __IO uint32_t PCR;
573  __IO uint32_t SR;
574  __IO uint32_t PMEM;
575  __IO uint32_t PATT;
576  uint32_t RESERVED0;
577  __IO uint32_t ECCR;
578 } FMC_Bank3_TypeDef;
579 
584 typedef struct
585 {
586  __IO uint32_t SDCR[2];
587  __IO uint32_t SDTR[2];
588  __IO uint32_t SDCMR;
589  __IO uint32_t SDRTR;
590  __IO uint32_t SDSR;
591 } FMC_Bank5_6_TypeDef;
592 
593 
598 typedef struct
599 {
600  __IO uint32_t MODER;
601  __IO uint32_t OTYPER;
602  __IO uint32_t OSPEEDR;
603  __IO uint32_t PUPDR;
604  __IO uint32_t IDR;
605  __IO uint32_t ODR;
606  __IO uint32_t BSRR;
607  __IO uint32_t LCKR;
608  __IO uint32_t AFR[2];
609 } GPIO_TypeDef;
610 
615 typedef struct
616 {
617  __IO uint32_t MEMRMP;
618  __IO uint32_t PMC;
619  __IO uint32_t EXTICR[4];
620  uint32_t RESERVED[2];
621  __IO uint32_t CMPCR;
622 } SYSCFG_TypeDef;
623 
628 typedef struct
629 {
630  __IO uint32_t CR1;
631  __IO uint32_t CR2;
632  __IO uint32_t OAR1;
633  __IO uint32_t OAR2;
634  __IO uint32_t TIMINGR;
635  __IO uint32_t TIMEOUTR;
636  __IO uint32_t ISR;
637  __IO uint32_t ICR;
638  __IO uint32_t PECR;
639  __IO uint32_t RXDR;
640  __IO uint32_t TXDR;
641 } I2C_TypeDef;
642 
647 typedef struct
648 {
649  __IO uint32_t KR;
650  __IO uint32_t PR;
651  __IO uint32_t RLR;
652  __IO uint32_t SR;
653  __IO uint32_t WINR;
654 } IWDG_TypeDef;
655 
656 
661 typedef struct
662 {
663  uint32_t RESERVED0[2];
664  __IO uint32_t SSCR;
665  __IO uint32_t BPCR;
666  __IO uint32_t AWCR;
667  __IO uint32_t TWCR;
668  __IO uint32_t GCR;
669  uint32_t RESERVED1[2];
670  __IO uint32_t SRCR;
671  uint32_t RESERVED2[1];
672  __IO uint32_t BCCR;
673  uint32_t RESERVED3[1];
674  __IO uint32_t IER;
675  __IO uint32_t ISR;
676  __IO uint32_t ICR;
677  __IO uint32_t LIPCR;
678  __IO uint32_t CPSR;
679  __IO uint32_t CDSR;
680 } LTDC_TypeDef;
681 
686 typedef struct
687 {
688  __IO uint32_t CR;
689  __IO uint32_t WHPCR;
690  __IO uint32_t WVPCR;
691  __IO uint32_t CKCR;
692  __IO uint32_t PFCR;
693  __IO uint32_t CACR;
694  __IO uint32_t DCCR;
695  __IO uint32_t BFCR;
696  uint32_t RESERVED0[2];
697  __IO uint32_t CFBAR;
698  __IO uint32_t CFBLR;
699  __IO uint32_t CFBLNR;
700  uint32_t RESERVED1[3];
701  __IO uint32_t CLUTWR;
703 } LTDC_Layer_TypeDef;
704 
709 typedef struct
710 {
711  __IO uint32_t CR1;
712  __IO uint32_t CSR1;
713  __IO uint32_t CR2;
714  __IO uint32_t CSR2;
715 } PWR_TypeDef;
716 
717 
722 typedef struct
723 {
724  __IO uint32_t CR;
725  __IO uint32_t PLLCFGR;
726  __IO uint32_t CFGR;
727  __IO uint32_t CIR;
728  __IO uint32_t AHB1RSTR;
729  __IO uint32_t AHB2RSTR;
730  __IO uint32_t AHB3RSTR;
731  uint32_t RESERVED0;
732  __IO uint32_t APB1RSTR;
733  __IO uint32_t APB2RSTR;
734  uint32_t RESERVED1[2];
735  __IO uint32_t AHB1ENR;
736  __IO uint32_t AHB2ENR;
737  __IO uint32_t AHB3ENR;
738  uint32_t RESERVED2;
739  __IO uint32_t APB1ENR;
740  __IO uint32_t APB2ENR;
741  uint32_t RESERVED3[2];
742  __IO uint32_t AHB1LPENR;
743  __IO uint32_t AHB2LPENR;
744  __IO uint32_t AHB3LPENR;
745  uint32_t RESERVED4;
746  __IO uint32_t APB1LPENR;
747  __IO uint32_t APB2LPENR;
748  uint32_t RESERVED5[2];
749  __IO uint32_t BDCR;
750  __IO uint32_t CSR;
751  uint32_t RESERVED6[2];
752  __IO uint32_t SSCGR;
753  __IO uint32_t PLLI2SCFGR;
754  __IO uint32_t PLLSAICFGR;
755  __IO uint32_t DCKCFGR1;
756  __IO uint32_t DCKCFGR2;
758 } RCC_TypeDef;
759 
764 typedef struct
765 {
766  __IO uint32_t TR;
767  __IO uint32_t DR;
768  __IO uint32_t CR;
769  __IO uint32_t ISR;
770  __IO uint32_t PRER;
771  __IO uint32_t WUTR;
772  uint32_t reserved;
773  __IO uint32_t ALRMAR;
774  __IO uint32_t ALRMBR;
775  __IO uint32_t WPR;
776  __IO uint32_t SSR;
777  __IO uint32_t SHIFTR;
778  __IO uint32_t TSTR;
779  __IO uint32_t TSDR;
780  __IO uint32_t TSSSR;
781  __IO uint32_t CALR;
782  __IO uint32_t TAMPCR;
783  __IO uint32_t ALRMASSR;
784  __IO uint32_t ALRMBSSR;
785  __IO uint32_t OR;
786  __IO uint32_t BKP0R;
787  __IO uint32_t BKP1R;
788  __IO uint32_t BKP2R;
789  __IO uint32_t BKP3R;
790  __IO uint32_t BKP4R;
791  __IO uint32_t BKP5R;
792  __IO uint32_t BKP6R;
793  __IO uint32_t BKP7R;
794  __IO uint32_t BKP8R;
795  __IO uint32_t BKP9R;
796  __IO uint32_t BKP10R;
797  __IO uint32_t BKP11R;
798  __IO uint32_t BKP12R;
799  __IO uint32_t BKP13R;
800  __IO uint32_t BKP14R;
801  __IO uint32_t BKP15R;
802  __IO uint32_t BKP16R;
803  __IO uint32_t BKP17R;
804  __IO uint32_t BKP18R;
805  __IO uint32_t BKP19R;
806  __IO uint32_t BKP20R;
807  __IO uint32_t BKP21R;
808  __IO uint32_t BKP22R;
809  __IO uint32_t BKP23R;
810  __IO uint32_t BKP24R;
811  __IO uint32_t BKP25R;
812  __IO uint32_t BKP26R;
813  __IO uint32_t BKP27R;
814  __IO uint32_t BKP28R;
815  __IO uint32_t BKP29R;
816  __IO uint32_t BKP30R;
817  __IO uint32_t BKP31R;
818 } RTC_TypeDef;
819 
820 
825 typedef struct
826 {
827  __IO uint32_t GCR;
828 } SAI_TypeDef;
829 
830 typedef struct
831 {
832  __IO uint32_t CR1;
833  __IO uint32_t CR2;
834  __IO uint32_t FRCR;
835  __IO uint32_t SLOTR;
836  __IO uint32_t IMR;
837  __IO uint32_t SR;
838  __IO uint32_t CLRFR;
839  __IO uint32_t DR;
840 } SAI_Block_TypeDef;
841 
846 typedef struct
847 {
848  __IO uint32_t CR;
849  __IO uint32_t IMR;
850  __IO uint32_t SR;
851  __IO uint32_t IFCR;
852  __IO uint32_t DR;
853  __IO uint32_t CSR;
854  __IO uint32_t DIR;
855 } SPDIFRX_TypeDef;
856 
857 
862 typedef struct
863 {
864  __IO uint32_t POWER;
865  __IO uint32_t CLKCR;
866  __IO uint32_t ARG;
867  __IO uint32_t CMD;
868  __I uint32_t RESPCMD;
869  __I uint32_t RESP1;
870  __I uint32_t RESP2;
871  __I uint32_t RESP3;
872  __I uint32_t RESP4;
873  __IO uint32_t DTIMER;
874  __IO uint32_t DLEN;
875  __IO uint32_t DCTRL;
876  __I uint32_t DCOUNT;
877  __I uint32_t STA;
878  __IO uint32_t ICR;
879  __IO uint32_t MASK;
880  uint32_t RESERVED0[2];
881  __I uint32_t FIFOCNT;
882  uint32_t RESERVED1[13];
883  __IO uint32_t FIFO;
884 } SDMMC_TypeDef;
885 
890 typedef struct
891 {
892  __IO uint32_t CR1;
893  __IO uint32_t CR2;
894  __IO uint32_t SR;
895  __IO uint32_t DR;
896  __IO uint32_t CRCPR;
897  __IO uint32_t RXCRCR;
898  __IO uint32_t TXCRCR;
899  __IO uint32_t I2SCFGR;
900  __IO uint32_t I2SPR;
901 } SPI_TypeDef;
902 
907 typedef struct
908 {
909  __IO uint32_t CR;
910  __IO uint32_t DCR;
911  __IO uint32_t SR;
912  __IO uint32_t FCR;
913  __IO uint32_t DLR;
914  __IO uint32_t CCR;
915  __IO uint32_t AR;
916  __IO uint32_t ABR;
917  __IO uint32_t DR;
918  __IO uint32_t PSMKR;
919  __IO uint32_t PSMAR;
920  __IO uint32_t PIR;
921  __IO uint32_t LPTR;
922 } QUADSPI_TypeDef;
923 
928 typedef struct
929 {
930  __IO uint32_t CR1;
931  __IO uint32_t CR2;
932  __IO uint32_t SMCR;
933  __IO uint32_t DIER;
934  __IO uint32_t SR;
935  __IO uint32_t EGR;
936  __IO uint32_t CCMR1;
937  __IO uint32_t CCMR2;
938  __IO uint32_t CCER;
939  __IO uint32_t CNT;
940  __IO uint32_t PSC;
941  __IO uint32_t ARR;
942  __IO uint32_t RCR;
943  __IO uint32_t CCR1;
944  __IO uint32_t CCR2;
945  __IO uint32_t CCR3;
946  __IO uint32_t CCR4;
947  __IO uint32_t BDTR;
948  __IO uint32_t DCR;
949  __IO uint32_t DMAR;
950  __IO uint32_t OR;
951  __IO uint32_t CCMR3;
952  __IO uint32_t CCR5;
953  __IO uint32_t CCR6;
955 } TIM_TypeDef;
956 
960 typedef struct
961 {
962  __IO uint32_t ISR;
963  __IO uint32_t ICR;
964  __IO uint32_t IER;
965  __IO uint32_t CFGR;
966  __IO uint32_t CR;
967  __IO uint32_t CMP;
968  __IO uint32_t ARR;
969  __IO uint32_t CNT;
970 } LPTIM_TypeDef;
971 
972 
977 typedef struct
978 {
979  __IO uint32_t CR1;
980  __IO uint32_t CR2;
981  __IO uint32_t CR3;
982  __IO uint32_t BRR;
983  __IO uint32_t GTPR;
984  __IO uint32_t RTOR;
985  __IO uint32_t RQR;
986  __IO uint32_t ISR;
987  __IO uint32_t ICR;
988  __IO uint32_t RDR;
989  __IO uint32_t TDR;
990 } USART_TypeDef;
991 
992 
997 typedef struct
998 {
999  __IO uint32_t CR;
1000  __IO uint32_t CFR;
1001  __IO uint32_t SR;
1002 } WWDG_TypeDef;
1003 
1004 
1009 typedef struct
1010 {
1011  __IO uint32_t CR;
1012  __IO uint32_t SR;
1013  __IO uint32_t DR;
1014 } RNG_TypeDef;
1015 
1023 typedef struct
1024 {
1025  __IO uint32_t GOTGCTL;
1026  __IO uint32_t GOTGINT;
1027  __IO uint32_t GAHBCFG;
1028  __IO uint32_t GUSBCFG;
1029  __IO uint32_t GRSTCTL;
1030  __IO uint32_t GINTSTS;
1031  __IO uint32_t GINTMSK;
1032  __IO uint32_t GRXSTSR;
1033  __IO uint32_t GRXSTSP;
1034  __IO uint32_t GRXFSIZ;
1035  __IO uint32_t DIEPTXF0_HNPTXFSIZ;
1036  __IO uint32_t HNPTXSTS;
1037  uint32_t Reserved30[2];
1038  __IO uint32_t GCCFG;
1039  __IO uint32_t CID;
1040  uint32_t Reserved5[3];
1041  __IO uint32_t GHWCFG3;
1042  uint32_t Reserved6;
1043  __IO uint32_t GLPMCFG;
1044  __IO uint32_t GPWRDN;
1045  __IO uint32_t GDFIFOCFG;
1046  __IO uint32_t GADPCTL;
1047  uint32_t Reserved43[39];
1048  __IO uint32_t HPTXFSIZ;
1049  __IO uint32_t DIEPTXF[0x0F];
1050 } USB_OTG_GlobalTypeDef;
1051 
1052 
1056 typedef struct
1057 {
1058  __IO uint32_t DCFG;
1059  __IO uint32_t DCTL;
1060  __IO uint32_t DSTS;
1061  uint32_t Reserved0C;
1062  __IO uint32_t DIEPMSK;
1063  __IO uint32_t DOEPMSK;
1064  __IO uint32_t DAINT;
1065  __IO uint32_t DAINTMSK;
1066  uint32_t Reserved20;
1067  uint32_t Reserved9;
1068  __IO uint32_t DVBUSDIS;
1069  __IO uint32_t DVBUSPULSE;
1070  __IO uint32_t DTHRCTL;
1071  __IO uint32_t DIEPEMPMSK;
1072  __IO uint32_t DEACHINT;
1073  __IO uint32_t DEACHMSK;
1074  uint32_t Reserved40;
1075  __IO uint32_t DINEP1MSK;
1076  uint32_t Reserved44[15];
1077  __IO uint32_t DOUTEP1MSK;
1078 } USB_OTG_DeviceTypeDef;
1079 
1080 
1084 typedef struct
1085 {
1086  __IO uint32_t DIEPCTL;
1087  uint32_t Reserved04;
1088  __IO uint32_t DIEPINT;
1089  uint32_t Reserved0C;
1090  __IO uint32_t DIEPTSIZ;
1091  __IO uint32_t DIEPDMA;
1092  __IO uint32_t DTXFSTS;
1093  uint32_t Reserved18;
1094 } USB_OTG_INEndpointTypeDef;
1095 
1096 
1100 typedef struct
1101 {
1102  __IO uint32_t DOEPCTL;
1103  uint32_t Reserved04;
1104  __IO uint32_t DOEPINT;
1105  uint32_t Reserved0C;
1106  __IO uint32_t DOEPTSIZ;
1107  __IO uint32_t DOEPDMA;
1108  uint32_t Reserved18[2];
1109 } USB_OTG_OUTEndpointTypeDef;
1110 
1111 
1115 typedef struct
1116 {
1117  __IO uint32_t HCFG;
1118  __IO uint32_t HFIR;
1119  __IO uint32_t HFNUM;
1120  uint32_t Reserved40C;
1121  __IO uint32_t HPTXSTS;
1122  __IO uint32_t HAINT;
1123  __IO uint32_t HAINTMSK;
1124 } USB_OTG_HostTypeDef;
1125 
1129 typedef struct
1130 {
1131  __IO uint32_t HCCHAR;
1132  __IO uint32_t HCSPLT;
1133  __IO uint32_t HCINT;
1134  __IO uint32_t HCINTMSK;
1135  __IO uint32_t HCTSIZ;
1136  __IO uint32_t HCDMA;
1137  uint32_t Reserved[2];
1138 } USB_OTG_HostChannelTypeDef;
1149 #define RAMITCM_BASE 0x00000000U
1150 #define FLASHITCM_BASE 0x00200000U
1151 #define FLASHAXI_BASE 0x08000000U
1152 #define RAMDTCM_BASE 0x20000000U
1153 #define PERIPH_BASE 0x40000000U
1154 #define BKPSRAM_BASE 0x40024000U
1155 #define QSPI_BASE 0x90000000U
1156 #define FMC_R_BASE 0xA0000000U
1157 #define QSPI_R_BASE 0xA0001000U
1158 #define SRAM1_BASE 0x20010000U
1159 #define SRAM2_BASE 0x2004C000U
1160 #define FLASH_END 0x080FFFFFU
1162 /* Legacy define */
1163 #define FLASH_BASE FLASHAXI_BASE
1164 
1166 #define APB1PERIPH_BASE PERIPH_BASE
1167 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
1168 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
1169 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
1170 
1172 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
1173 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
1174 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
1175 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
1176 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
1177 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
1178 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
1179 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
1180 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
1181 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
1182 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
1183 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
1184 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
1185 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
1186 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
1187 #define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U)
1188 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
1189 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
1190 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
1191 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
1192 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
1193 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
1194 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
1195 #define I2C4_BASE (APB1PERIPH_BASE + 0x6000U)
1196 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
1197 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
1198 #define CEC_BASE (APB1PERIPH_BASE + 0x6C00U)
1199 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
1200 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
1201 #define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
1202 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
1203 
1205 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
1206 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
1207 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
1208 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
1209 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
1210 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
1211 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
1212 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
1213 #define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U)
1214 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1215 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
1216 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
1217 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
1218 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
1219 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
1220 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
1221 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
1222 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
1223 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
1224 #define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U)
1225 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
1226 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
1227 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004U)
1228 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024U)
1229 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
1230 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
1231 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
1232 
1233 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
1234 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
1235 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
1236 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
1237 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
1238 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
1239 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
1240 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
1241 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
1242 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
1243 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
1244 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1245 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
1246 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
1247 #define UID_BASE 0x1FF0F420U
1248 #define FLASHSIZE_BASE 0x1FF0F442U
1249 #define PACKAGESIZE_BASE 0x1FFF7BF0U
1250 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
1251 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
1252 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
1253 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
1254 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
1255 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
1256 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
1257 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
1258 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
1259 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
1260 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
1261 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
1262 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
1263 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
1264 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
1265 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
1266 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
1267 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
1268 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
1269 #define ETH_MAC_BASE (ETH_BASE)
1270 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
1271 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
1272 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
1273 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
1274 
1275 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
1276 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
1277 
1278 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
1279 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
1280 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
1281 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
1282 
1283 /* Debug MCU registers base address */
1284 #define DBGMCU_BASE 0xE0042000U
1285 
1287 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
1288 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
1289 
1290 #define USB_OTG_GLOBAL_BASE 0x000U
1291 #define USB_OTG_DEVICE_BASE 0x800U
1292 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
1293 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
1294 #define USB_OTG_EP_REG_SIZE 0x20U
1295 #define USB_OTG_HOST_BASE 0x400U
1296 #define USB_OTG_HOST_PORT_BASE 0x440U
1297 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
1298 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
1299 #define USB_OTG_PCGCCTL_BASE 0xE00U
1300 #define USB_OTG_FIFO_BASE 0x1000U
1301 #define USB_OTG_FIFO_SIZE 0x1000U
1302 
1310 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1311 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1312 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1313 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1314 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1315 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1316 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1317 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1318 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1319 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1320 #define RTC ((RTC_TypeDef *) RTC_BASE)
1321 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1322 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1323 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1324 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1325 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
1326 #define USART2 ((USART_TypeDef *) USART2_BASE)
1327 #define USART3 ((USART_TypeDef *) USART3_BASE)
1328 #define UART4 ((USART_TypeDef *) UART4_BASE)
1329 #define UART5 ((USART_TypeDef *) UART5_BASE)
1330 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1331 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1332 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1333 #define I2C4 ((I2C_TypeDef *) I2C4_BASE)
1334 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1335 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1336 #define CEC ((CEC_TypeDef *) CEC_BASE)
1337 #define PWR ((PWR_TypeDef *) PWR_BASE)
1338 #define DAC ((DAC_TypeDef *) DAC_BASE)
1339 #define UART7 ((USART_TypeDef *) UART7_BASE)
1340 #define UART8 ((USART_TypeDef *) UART8_BASE)
1341 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1342 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1343 #define USART1 ((USART_TypeDef *) USART1_BASE)
1344 #define USART6 ((USART_TypeDef *) USART6_BASE)
1345 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1346 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1347 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1348 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1349 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
1350 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1351 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1352 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1353 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1354 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1355 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1356 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1357 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1358 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
1359 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1360 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
1361 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1362 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1363 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
1364 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
1365 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
1366 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
1367 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
1368 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1369 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1370 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1371 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1372 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1373 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1374 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1375 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1376 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1377 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
1378 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
1379 #define CRC ((CRC_TypeDef *) CRC_BASE)
1380 #define RCC ((RCC_TypeDef *) RCC_BASE)
1381 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1382 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1383 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1384 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1385 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1386 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1387 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1388 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1389 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1390 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1391 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1392 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1393 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1394 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1395 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1396 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1397 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1398 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1399 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1400 #define ETH ((ETH_TypeDef *) ETH_BASE)
1401 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1402 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1403 #define RNG ((RNG_TypeDef *) RNG_BASE)
1404 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1405 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1406 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1407 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1408 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1409 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1410 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1411 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1412 
1425 /******************************************************************************/
1426 /* Peripheral Registers_Bits_Definition */
1427 /******************************************************************************/
1428 
1429 /******************************************************************************/
1430 /* */
1431 /* Analog to Digital Converter */
1432 /* */
1433 /******************************************************************************/
1434 /******************** Bit definition for ADC_SR register ********************/
1435 #define ADC_SR_AWD 0x00000001U
1436 #define ADC_SR_EOC 0x00000002U
1437 #define ADC_SR_JEOC 0x00000004U
1438 #define ADC_SR_JSTRT 0x00000008U
1439 #define ADC_SR_STRT 0x00000010U
1440 #define ADC_SR_OVR 0x00000020U
1442 /******************* Bit definition for ADC_CR1 register ********************/
1443 #define ADC_CR1_AWDCH 0x0000001FU
1444 #define ADC_CR1_AWDCH_0 0x00000001U
1445 #define ADC_CR1_AWDCH_1 0x00000002U
1446 #define ADC_CR1_AWDCH_2 0x00000004U
1447 #define ADC_CR1_AWDCH_3 0x00000008U
1448 #define ADC_CR1_AWDCH_4 0x00000010U
1449 #define ADC_CR1_EOCIE 0x00000020U
1450 #define ADC_CR1_AWDIE 0x00000040U
1451 #define ADC_CR1_JEOCIE 0x00000080U
1452 #define ADC_CR1_SCAN 0x00000100U
1453 #define ADC_CR1_AWDSGL 0x00000200U
1454 #define ADC_CR1_JAUTO 0x00000400U
1455 #define ADC_CR1_DISCEN 0x00000800U
1456 #define ADC_CR1_JDISCEN 0x00001000U
1457 #define ADC_CR1_DISCNUM 0x0000E000U
1458 #define ADC_CR1_DISCNUM_0 0x00002000U
1459 #define ADC_CR1_DISCNUM_1 0x00004000U
1460 #define ADC_CR1_DISCNUM_2 0x00008000U
1461 #define ADC_CR1_JAWDEN 0x00400000U
1462 #define ADC_CR1_AWDEN 0x00800000U
1463 #define ADC_CR1_RES 0x03000000U
1464 #define ADC_CR1_RES_0 0x01000000U
1465 #define ADC_CR1_RES_1 0x02000000U
1466 #define ADC_CR1_OVRIE 0x04000000U
1468 /******************* Bit definition for ADC_CR2 register ********************/
1469 #define ADC_CR2_ADON 0x00000001U
1470 #define ADC_CR2_CONT 0x00000002U
1471 #define ADC_CR2_DMA 0x00000100U
1472 #define ADC_CR2_DDS 0x00000200U
1473 #define ADC_CR2_EOCS 0x00000400U
1474 #define ADC_CR2_ALIGN 0x00000800U
1475 #define ADC_CR2_JEXTSEL 0x000F0000U
1476 #define ADC_CR2_JEXTSEL_0 0x00010000U
1477 #define ADC_CR2_JEXTSEL_1 0x00020000U
1478 #define ADC_CR2_JEXTSEL_2 0x00040000U
1479 #define ADC_CR2_JEXTSEL_3 0x00080000U
1480 #define ADC_CR2_JEXTEN 0x00300000U
1481 #define ADC_CR2_JEXTEN_0 0x00100000U
1482 #define ADC_CR2_JEXTEN_1 0x00200000U
1483 #define ADC_CR2_JSWSTART 0x00400000U
1484 #define ADC_CR2_EXTSEL 0x0F000000U
1485 #define ADC_CR2_EXTSEL_0 0x01000000U
1486 #define ADC_CR2_EXTSEL_1 0x02000000U
1487 #define ADC_CR2_EXTSEL_2 0x04000000U
1488 #define ADC_CR2_EXTSEL_3 0x08000000U
1489 #define ADC_CR2_EXTEN 0x30000000U
1490 #define ADC_CR2_EXTEN_0 0x10000000U
1491 #define ADC_CR2_EXTEN_1 0x20000000U
1492 #define ADC_CR2_SWSTART 0x40000000U
1494 /****************** Bit definition for ADC_SMPR1 register *******************/
1495 #define ADC_SMPR1_SMP10 0x00000007U
1496 #define ADC_SMPR1_SMP10_0 0x00000001U
1497 #define ADC_SMPR1_SMP10_1 0x00000002U
1498 #define ADC_SMPR1_SMP10_2 0x00000004U
1499 #define ADC_SMPR1_SMP11 0x00000038U
1500 #define ADC_SMPR1_SMP11_0 0x00000008U
1501 #define ADC_SMPR1_SMP11_1 0x00000010U
1502 #define ADC_SMPR1_SMP11_2 0x00000020U
1503 #define ADC_SMPR1_SMP12 0x000001C0U
1504 #define ADC_SMPR1_SMP12_0 0x00000040U
1505 #define ADC_SMPR1_SMP12_1 0x00000080U
1506 #define ADC_SMPR1_SMP12_2 0x00000100U
1507 #define ADC_SMPR1_SMP13 0x00000E00U
1508 #define ADC_SMPR1_SMP13_0 0x00000200U
1509 #define ADC_SMPR1_SMP13_1 0x00000400U
1510 #define ADC_SMPR1_SMP13_2 0x00000800U
1511 #define ADC_SMPR1_SMP14 0x00007000U
1512 #define ADC_SMPR1_SMP14_0 0x00001000U
1513 #define ADC_SMPR1_SMP14_1 0x00002000U
1514 #define ADC_SMPR1_SMP14_2 0x00004000U
1515 #define ADC_SMPR1_SMP15 0x00038000U
1516 #define ADC_SMPR1_SMP15_0 0x00008000U
1517 #define ADC_SMPR1_SMP15_1 0x00010000U
1518 #define ADC_SMPR1_SMP15_2 0x00020000U
1519 #define ADC_SMPR1_SMP16 0x001C0000U
1520 #define ADC_SMPR1_SMP16_0 0x00040000U
1521 #define ADC_SMPR1_SMP16_1 0x00080000U
1522 #define ADC_SMPR1_SMP16_2 0x00100000U
1523 #define ADC_SMPR1_SMP17 0x00E00000U
1524 #define ADC_SMPR1_SMP17_0 0x00200000U
1525 #define ADC_SMPR1_SMP17_1 0x00400000U
1526 #define ADC_SMPR1_SMP17_2 0x00800000U
1527 #define ADC_SMPR1_SMP18 0x07000000U
1528 #define ADC_SMPR1_SMP18_0 0x01000000U
1529 #define ADC_SMPR1_SMP18_1 0x02000000U
1530 #define ADC_SMPR1_SMP18_2 0x04000000U
1532 /****************** Bit definition for ADC_SMPR2 register *******************/
1533 #define ADC_SMPR2_SMP0 0x00000007U
1534 #define ADC_SMPR2_SMP0_0 0x00000001U
1535 #define ADC_SMPR2_SMP0_1 0x00000002U
1536 #define ADC_SMPR2_SMP0_2 0x00000004U
1537 #define ADC_SMPR2_SMP1 0x00000038U
1538 #define ADC_SMPR2_SMP1_0 0x00000008U
1539 #define ADC_SMPR2_SMP1_1 0x00000010U
1540 #define ADC_SMPR2_SMP1_2 0x00000020U
1541 #define ADC_SMPR2_SMP2 0x000001C0U
1542 #define ADC_SMPR2_SMP2_0 0x00000040U
1543 #define ADC_SMPR2_SMP2_1 0x00000080U
1544 #define ADC_SMPR2_SMP2_2 0x00000100U
1545 #define ADC_SMPR2_SMP3 0x00000E00U
1546 #define ADC_SMPR2_SMP3_0 0x00000200U
1547 #define ADC_SMPR2_SMP3_1 0x00000400U
1548 #define ADC_SMPR2_SMP3_2 0x00000800U
1549 #define ADC_SMPR2_SMP4 0x00007000U
1550 #define ADC_SMPR2_SMP4_0 0x00001000U
1551 #define ADC_SMPR2_SMP4_1 0x00002000U
1552 #define ADC_SMPR2_SMP4_2 0x00004000U
1553 #define ADC_SMPR2_SMP5 0x00038000U
1554 #define ADC_SMPR2_SMP5_0 0x00008000U
1555 #define ADC_SMPR2_SMP5_1 0x00010000U
1556 #define ADC_SMPR2_SMP5_2 0x00020000U
1557 #define ADC_SMPR2_SMP6 0x001C0000U
1558 #define ADC_SMPR2_SMP6_0 0x00040000U
1559 #define ADC_SMPR2_SMP6_1 0x00080000U
1560 #define ADC_SMPR2_SMP6_2 0x00100000U
1561 #define ADC_SMPR2_SMP7 0x00E00000U
1562 #define ADC_SMPR2_SMP7_0 0x00200000U
1563 #define ADC_SMPR2_SMP7_1 0x00400000U
1564 #define ADC_SMPR2_SMP7_2 0x00800000U
1565 #define ADC_SMPR2_SMP8 0x07000000U
1566 #define ADC_SMPR2_SMP8_0 0x01000000U
1567 #define ADC_SMPR2_SMP8_1 0x02000000U
1568 #define ADC_SMPR2_SMP8_2 0x04000000U
1569 #define ADC_SMPR2_SMP9 0x38000000U
1570 #define ADC_SMPR2_SMP9_0 0x08000000U
1571 #define ADC_SMPR2_SMP9_1 0x10000000U
1572 #define ADC_SMPR2_SMP9_2 0x20000000U
1574 /****************** Bit definition for ADC_JOFR1 register *******************/
1575 #define ADC_JOFR1_JOFFSET1 0x0FFFU
1577 /****************** Bit definition for ADC_JOFR2 register *******************/
1578 #define ADC_JOFR2_JOFFSET2 0x0FFFU
1580 /****************** Bit definition for ADC_JOFR3 register *******************/
1581 #define ADC_JOFR3_JOFFSET3 0x0FFFU
1583 /****************** Bit definition for ADC_JOFR4 register *******************/
1584 #define ADC_JOFR4_JOFFSET4 0x0FFFU
1586 /******************* Bit definition for ADC_HTR register ********************/
1587 #define ADC_HTR_HT 0x0FFFU
1589 /******************* Bit definition for ADC_LTR register ********************/
1590 #define ADC_LTR_LT 0x0FFFU
1592 /******************* Bit definition for ADC_SQR1 register *******************/
1593 #define ADC_SQR1_SQ13 0x0000001FU
1594 #define ADC_SQR1_SQ13_0 0x00000001U
1595 #define ADC_SQR1_SQ13_1 0x00000002U
1596 #define ADC_SQR1_SQ13_2 0x00000004U
1597 #define ADC_SQR1_SQ13_3 0x00000008U
1598 #define ADC_SQR1_SQ13_4 0x00000010U
1599 #define ADC_SQR1_SQ14 0x000003E0U
1600 #define ADC_SQR1_SQ14_0 0x00000020U
1601 #define ADC_SQR1_SQ14_1 0x00000040U
1602 #define ADC_SQR1_SQ14_2 0x00000080U
1603 #define ADC_SQR1_SQ14_3 0x00000100U
1604 #define ADC_SQR1_SQ14_4 0x00000200U
1605 #define ADC_SQR1_SQ15 0x00007C00U
1606 #define ADC_SQR1_SQ15_0 0x00000400U
1607 #define ADC_SQR1_SQ15_1 0x00000800U
1608 #define ADC_SQR1_SQ15_2 0x00001000U
1609 #define ADC_SQR1_SQ15_3 0x00002000U
1610 #define ADC_SQR1_SQ15_4 0x00004000U
1611 #define ADC_SQR1_SQ16 0x000F8000U
1612 #define ADC_SQR1_SQ16_0 0x00008000U
1613 #define ADC_SQR1_SQ16_1 0x00010000U
1614 #define ADC_SQR1_SQ16_2 0x00020000U
1615 #define ADC_SQR1_SQ16_3 0x00040000U
1616 #define ADC_SQR1_SQ16_4 0x00080000U
1617 #define ADC_SQR1_L 0x00F00000U
1618 #define ADC_SQR1_L_0 0x00100000U
1619 #define ADC_SQR1_L_1 0x00200000U
1620 #define ADC_SQR1_L_2 0x00400000U
1621 #define ADC_SQR1_L_3 0x00800000U
1623 /******************* Bit definition for ADC_SQR2 register *******************/
1624 #define ADC_SQR2_SQ7 0x0000001FU
1625 #define ADC_SQR2_SQ7_0 0x00000001U
1626 #define ADC_SQR2_SQ7_1 0x00000002U
1627 #define ADC_SQR2_SQ7_2 0x00000004U
1628 #define ADC_SQR2_SQ7_3 0x00000008U
1629 #define ADC_SQR2_SQ7_4 0x00000010U
1630 #define ADC_SQR2_SQ8 0x000003E0U
1631 #define ADC_SQR2_SQ8_0 0x00000020U
1632 #define ADC_SQR2_SQ8_1 0x00000040U
1633 #define ADC_SQR2_SQ8_2 0x00000080U
1634 #define ADC_SQR2_SQ8_3 0x00000100U
1635 #define ADC_SQR2_SQ8_4 0x00000200U
1636 #define ADC_SQR2_SQ9 0x00007C00U
1637 #define ADC_SQR2_SQ9_0 0x00000400U
1638 #define ADC_SQR2_SQ9_1 0x00000800U
1639 #define ADC_SQR2_SQ9_2 0x00001000U
1640 #define ADC_SQR2_SQ9_3 0x00002000U
1641 #define ADC_SQR2_SQ9_4 0x00004000U
1642 #define ADC_SQR2_SQ10 0x000F8000U
1643 #define ADC_SQR2_SQ10_0 0x00008000U
1644 #define ADC_SQR2_SQ10_1 0x00010000U
1645 #define ADC_SQR2_SQ10_2 0x00020000U
1646 #define ADC_SQR2_SQ10_3 0x00040000U
1647 #define ADC_SQR2_SQ10_4 0x00080000U
1648 #define ADC_SQR2_SQ11 0x01F00000U
1649 #define ADC_SQR2_SQ11_0 0x00100000U
1650 #define ADC_SQR2_SQ11_1 0x00200000U
1651 #define ADC_SQR2_SQ11_2 0x00400000U
1652 #define ADC_SQR2_SQ11_3 0x00800000U
1653 #define ADC_SQR2_SQ11_4 0x01000000U
1654 #define ADC_SQR2_SQ12 0x3E000000U
1655 #define ADC_SQR2_SQ12_0 0x02000000U
1656 #define ADC_SQR2_SQ12_1 0x04000000U
1657 #define ADC_SQR2_SQ12_2 0x08000000U
1658 #define ADC_SQR2_SQ12_3 0x10000000U
1659 #define ADC_SQR2_SQ12_4 0x20000000U
1661 /******************* Bit definition for ADC_SQR3 register *******************/
1662 #define ADC_SQR3_SQ1 0x0000001FU
1663 #define ADC_SQR3_SQ1_0 0x00000001U
1664 #define ADC_SQR3_SQ1_1 0x00000002U
1665 #define ADC_SQR3_SQ1_2 0x00000004U
1666 #define ADC_SQR3_SQ1_3 0x00000008U
1667 #define ADC_SQR3_SQ1_4 0x00000010U
1668 #define ADC_SQR3_SQ2 0x000003E0U
1669 #define ADC_SQR3_SQ2_0 0x00000020U
1670 #define ADC_SQR3_SQ2_1 0x00000040U
1671 #define ADC_SQR3_SQ2_2 0x00000080U
1672 #define ADC_SQR3_SQ2_3 0x00000100U
1673 #define ADC_SQR3_SQ2_4 0x00000200U
1674 #define ADC_SQR3_SQ3 0x00007C00U
1675 #define ADC_SQR3_SQ3_0 0x00000400U
1676 #define ADC_SQR3_SQ3_1 0x00000800U
1677 #define ADC_SQR3_SQ3_2 0x00001000U
1678 #define ADC_SQR3_SQ3_3 0x00002000U
1679 #define ADC_SQR3_SQ3_4 0x00004000U
1680 #define ADC_SQR3_SQ4 0x000F8000U
1681 #define ADC_SQR3_SQ4_0 0x00008000U
1682 #define ADC_SQR3_SQ4_1 0x00010000U
1683 #define ADC_SQR3_SQ4_2 0x00020000U
1684 #define ADC_SQR3_SQ4_3 0x00040000U
1685 #define ADC_SQR3_SQ4_4 0x00080000U
1686 #define ADC_SQR3_SQ5 0x01F00000U
1687 #define ADC_SQR3_SQ5_0 0x00100000U
1688 #define ADC_SQR3_SQ5_1 0x00200000U
1689 #define ADC_SQR3_SQ5_2 0x00400000U
1690 #define ADC_SQR3_SQ5_3 0x00800000U
1691 #define ADC_SQR3_SQ5_4 0x01000000U
1692 #define ADC_SQR3_SQ6 0x3E000000U
1693 #define ADC_SQR3_SQ6_0 0x02000000U
1694 #define ADC_SQR3_SQ6_1 0x04000000U
1695 #define ADC_SQR3_SQ6_2 0x08000000U
1696 #define ADC_SQR3_SQ6_3 0x10000000U
1697 #define ADC_SQR3_SQ6_4 0x20000000U
1699 /******************* Bit definition for ADC_JSQR register *******************/
1700 #define ADC_JSQR_JSQ1 0x0000001FU
1701 #define ADC_JSQR_JSQ1_0 0x00000001U
1702 #define ADC_JSQR_JSQ1_1 0x00000002U
1703 #define ADC_JSQR_JSQ1_2 0x00000004U
1704 #define ADC_JSQR_JSQ1_3 0x00000008U
1705 #define ADC_JSQR_JSQ1_4 0x00000010U
1706 #define ADC_JSQR_JSQ2 0x000003E0U
1707 #define ADC_JSQR_JSQ2_0 0x00000020U
1708 #define ADC_JSQR_JSQ2_1 0x00000040U
1709 #define ADC_JSQR_JSQ2_2 0x00000080U
1710 #define ADC_JSQR_JSQ2_3 0x00000100U
1711 #define ADC_JSQR_JSQ2_4 0x00000200U
1712 #define ADC_JSQR_JSQ3 0x00007C00U
1713 #define ADC_JSQR_JSQ3_0 0x00000400U
1714 #define ADC_JSQR_JSQ3_1 0x00000800U
1715 #define ADC_JSQR_JSQ3_2 0x00001000U
1716 #define ADC_JSQR_JSQ3_3 0x00002000U
1717 #define ADC_JSQR_JSQ3_4 0x00004000U
1718 #define ADC_JSQR_JSQ4 0x000F8000U
1719 #define ADC_JSQR_JSQ4_0 0x00008000U
1720 #define ADC_JSQR_JSQ4_1 0x00010000U
1721 #define ADC_JSQR_JSQ4_2 0x00020000U
1722 #define ADC_JSQR_JSQ4_3 0x00040000U
1723 #define ADC_JSQR_JSQ4_4 0x00080000U
1724 #define ADC_JSQR_JL 0x00300000U
1725 #define ADC_JSQR_JL_0 0x00100000U
1726 #define ADC_JSQR_JL_1 0x00200000U
1728 /******************* Bit definition for ADC_JDR1 register *******************/
1729 #define ADC_JDR1_JDATA ((uint16_t)0xFFFFU)
1731 /******************* Bit definition for ADC_JDR2 register *******************/
1732 #define ADC_JDR2_JDATA ((uint16_t)0xFFFFU)
1734 /******************* Bit definition for ADC_JDR3 register *******************/
1735 #define ADC_JDR3_JDATA ((uint16_t)0xFFFFU)
1737 /******************* Bit definition for ADC_JDR4 register *******************/
1738 #define ADC_JDR4_JDATA ((uint16_t)0xFFFFU)
1740 /******************** Bit definition for ADC_DR register ********************/
1741 #define ADC_DR_DATA 0x0000FFFFU
1742 #define ADC_DR_ADC2DATA 0xFFFF0000U
1744 /******************* Bit definition for ADC_CSR register ********************/
1745 #define ADC_CSR_AWD1 0x00000001U
1746 #define ADC_CSR_EOC1 0x00000002U
1747 #define ADC_CSR_JEOC1 0x00000004U
1748 #define ADC_CSR_JSTRT1 0x00000008U
1749 #define ADC_CSR_STRT1 0x00000010U
1750 #define ADC_CSR_OVR1 0x00000020U
1751 #define ADC_CSR_AWD2 0x00000100U
1752 #define ADC_CSR_EOC2 0x00000200U
1753 #define ADC_CSR_JEOC2 0x00000400U
1754 #define ADC_CSR_JSTRT2 0x00000800U
1755 #define ADC_CSR_STRT2 0x00001000U
1756 #define ADC_CSR_OVR2 0x00002000U
1757 #define ADC_CSR_AWD3 0x00010000U
1758 #define ADC_CSR_EOC3 0x00020000U
1759 #define ADC_CSR_JEOC3 0x00040000U
1760 #define ADC_CSR_JSTRT3 0x00080000U
1761 #define ADC_CSR_STRT3 0x00100000U
1762 #define ADC_CSR_OVR3 0x00200000U
1764 /* Legacy defines */
1765 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1766 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
1767 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
1768 
1769 
1770 /******************* Bit definition for ADC_CCR register ********************/
1771 #define ADC_CCR_MULTI 0x0000001FU
1772 #define ADC_CCR_MULTI_0 0x00000001U
1773 #define ADC_CCR_MULTI_1 0x00000002U
1774 #define ADC_CCR_MULTI_2 0x00000004U
1775 #define ADC_CCR_MULTI_3 0x00000008U
1776 #define ADC_CCR_MULTI_4 0x00000010U
1777 #define ADC_CCR_DELAY 0x00000F00U
1778 #define ADC_CCR_DELAY_0 0x00000100U
1779 #define ADC_CCR_DELAY_1 0x00000200U
1780 #define ADC_CCR_DELAY_2 0x00000400U
1781 #define ADC_CCR_DELAY_3 0x00000800U
1782 #define ADC_CCR_DDS 0x00002000U
1783 #define ADC_CCR_DMA 0x0000C000U
1784 #define ADC_CCR_DMA_0 0x00004000U
1785 #define ADC_CCR_DMA_1 0x00008000U
1786 #define ADC_CCR_ADCPRE 0x00030000U
1787 #define ADC_CCR_ADCPRE_0 0x00010000U
1788 #define ADC_CCR_ADCPRE_1 0x00020000U
1789 #define ADC_CCR_VBATE 0x00400000U
1790 #define ADC_CCR_TSVREFE 0x00800000U
1792 /******************* Bit definition for ADC_CDR register ********************/
1793 #define ADC_CDR_DATA1 0x0000FFFFU
1794 #define ADC_CDR_DATA2 0xFFFF0000U
1796 /******************************************************************************/
1797 /* */
1798 /* Controller Area Network */
1799 /* */
1800 /******************************************************************************/
1802 /******************* Bit definition for CAN_MCR register ********************/
1803 #define CAN_MCR_INRQ 0x00000001U
1804 #define CAN_MCR_SLEEP 0x00000002U
1805 #define CAN_MCR_TXFP 0x00000004U
1806 #define CAN_MCR_RFLM 0x00000008U
1807 #define CAN_MCR_NART 0x00000010U
1808 #define CAN_MCR_AWUM 0x00000020U
1809 #define CAN_MCR_ABOM 0x00000040U
1810 #define CAN_MCR_TTCM 0x00000080U
1811 #define CAN_MCR_RESET 0x00008000U
1813 /******************* Bit definition for CAN_MSR register ********************/
1814 #define CAN_MSR_INAK 0x00000001U
1815 #define CAN_MSR_SLAK 0x00000002U
1816 #define CAN_MSR_ERRI 0x00000004U
1817 #define CAN_MSR_WKUI 0x00000008U
1818 #define CAN_MSR_SLAKI 0x00000010U
1819 #define CAN_MSR_TXM 0x00000100U
1820 #define CAN_MSR_RXM 0x00000200U
1821 #define CAN_MSR_SAMP 0x00000400U
1822 #define CAN_MSR_RX 0x00000800U
1824 /******************* Bit definition for CAN_TSR register ********************/
1825 #define CAN_TSR_RQCP0 0x00000001U
1826 #define CAN_TSR_TXOK0 0x00000002U
1827 #define CAN_TSR_ALST0 0x00000004U
1828 #define CAN_TSR_TERR0 0x00000008U
1829 #define CAN_TSR_ABRQ0 0x00000080U
1830 #define CAN_TSR_RQCP1 0x00000100U
1831 #define CAN_TSR_TXOK1 0x00000200U
1832 #define CAN_TSR_ALST1 0x00000400U
1833 #define CAN_TSR_TERR1 0x00000800U
1834 #define CAN_TSR_ABRQ1 0x00008000U
1835 #define CAN_TSR_RQCP2 0x00010000U
1836 #define CAN_TSR_TXOK2 0x00020000U
1837 #define CAN_TSR_ALST2 0x00040000U
1838 #define CAN_TSR_TERR2 0x00080000U
1839 #define CAN_TSR_ABRQ2 0x00800000U
1840 #define CAN_TSR_CODE 0x03000000U
1842 #define CAN_TSR_TME 0x1C000000U
1843 #define CAN_TSR_TME0 0x04000000U
1844 #define CAN_TSR_TME1 0x08000000U
1845 #define CAN_TSR_TME2 0x10000000U
1847 #define CAN_TSR_LOW 0xE0000000U
1848 #define CAN_TSR_LOW0 0x20000000U
1849 #define CAN_TSR_LOW1 0x40000000U
1850 #define CAN_TSR_LOW2 0x80000000U
1852 /******************* Bit definition for CAN_RF0R register *******************/
1853 #define CAN_RF0R_FMP0 0x00000003U
1854 #define CAN_RF0R_FULL0 0x00000008U
1855 #define CAN_RF0R_FOVR0 0x00000010U
1856 #define CAN_RF0R_RFOM0 0x00000020U
1858 /******************* Bit definition for CAN_RF1R register *******************/
1859 #define CAN_RF1R_FMP1 0x00000003U
1860 #define CAN_RF1R_FULL1 0x00000008U
1861 #define CAN_RF1R_FOVR1 0x00000010U
1862 #define CAN_RF1R_RFOM1 0x00000020U
1864 /******************** Bit definition for CAN_IER register *******************/
1865 #define CAN_IER_TMEIE 0x00000001U
1866 #define CAN_IER_FMPIE0 0x00000002U
1867 #define CAN_IER_FFIE0 0x00000004U
1868 #define CAN_IER_FOVIE0 0x00000008U
1869 #define CAN_IER_FMPIE1 0x00000010U
1870 #define CAN_IER_FFIE1 0x00000020U
1871 #define CAN_IER_FOVIE1 0x00000040U
1872 #define CAN_IER_EWGIE 0x00000100U
1873 #define CAN_IER_EPVIE 0x00000200U
1874 #define CAN_IER_BOFIE 0x00000400U
1875 #define CAN_IER_LECIE 0x00000800U
1876 #define CAN_IER_ERRIE 0x00008000U
1877 #define CAN_IER_WKUIE 0x00010000U
1878 #define CAN_IER_SLKIE 0x00020000U
1880 /******************** Bit definition for CAN_ESR register *******************/
1881 #define CAN_ESR_EWGF 0x00000001U
1882 #define CAN_ESR_EPVF 0x00000002U
1883 #define CAN_ESR_BOFF 0x00000004U
1885 #define CAN_ESR_LEC 0x00000070U
1886 #define CAN_ESR_LEC_0 0x00000010U
1887 #define CAN_ESR_LEC_1 0x00000020U
1888 #define CAN_ESR_LEC_2 0x00000040U
1890 #define CAN_ESR_TEC 0x00FF0000U
1891 #define CAN_ESR_REC 0xFF000000U
1893 /******************* Bit definition for CAN_BTR register ********************/
1894 #define CAN_BTR_BRP 0x000003FFU
1895 #define CAN_BTR_TS1 0x000F0000U
1896 #define CAN_BTR_TS1_0 0x00010000U
1897 #define CAN_BTR_TS1_1 0x00020000U
1898 #define CAN_BTR_TS1_2 0x00040000U
1899 #define CAN_BTR_TS1_3 0x00080000U
1900 #define CAN_BTR_TS2 0x00700000U
1901 #define CAN_BTR_TS2_0 0x00100000U
1902 #define CAN_BTR_TS2_1 0x00200000U
1903 #define CAN_BTR_TS2_2 0x00400000U
1904 #define CAN_BTR_SJW 0x03000000U
1905 #define CAN_BTR_SJW_0 0x01000000U
1906 #define CAN_BTR_SJW_1 0x02000000U
1907 #define CAN_BTR_LBKM 0x40000000U
1908 #define CAN_BTR_SILM 0x80000000U
1911 /****************** Bit definition for CAN_TI0R register ********************/
1912 #define CAN_TI0R_TXRQ 0x00000001U
1913 #define CAN_TI0R_RTR 0x00000002U
1914 #define CAN_TI0R_IDE 0x00000004U
1915 #define CAN_TI0R_EXID 0x001FFFF8U
1916 #define CAN_TI0R_STID 0xFFE00000U
1918 /****************** Bit definition for CAN_TDT0R register *******************/
1919 #define CAN_TDT0R_DLC 0x0000000FU
1920 #define CAN_TDT0R_TGT 0x00000100U
1921 #define CAN_TDT0R_TIME 0xFFFF0000U
1923 /****************** Bit definition for CAN_TDL0R register *******************/
1924 #define CAN_TDL0R_DATA0 0x000000FFU
1925 #define CAN_TDL0R_DATA1 0x0000FF00U
1926 #define CAN_TDL0R_DATA2 0x00FF0000U
1927 #define CAN_TDL0R_DATA3 0xFF000000U
1929 /****************** Bit definition for CAN_TDH0R register *******************/
1930 #define CAN_TDH0R_DATA4 0x000000FFU
1931 #define CAN_TDH0R_DATA5 0x0000FF00U
1932 #define CAN_TDH0R_DATA6 0x00FF0000U
1933 #define CAN_TDH0R_DATA7 0xFF000000U
1935 /******************* Bit definition for CAN_TI1R register *******************/
1936 #define CAN_TI1R_TXRQ 0x00000001U
1937 #define CAN_TI1R_RTR 0x00000002U
1938 #define CAN_TI1R_IDE 0x00000004U
1939 #define CAN_TI1R_EXID 0x001FFFF8U
1940 #define CAN_TI1R_STID 0xFFE00000U
1942 /******************* Bit definition for CAN_TDT1R register ******************/
1943 #define CAN_TDT1R_DLC 0x0000000FU
1944 #define CAN_TDT1R_TGT 0x00000100U
1945 #define CAN_TDT1R_TIME 0xFFFF0000U
1947 /******************* Bit definition for CAN_TDL1R register ******************/
1948 #define CAN_TDL1R_DATA0 0x000000FFU
1949 #define CAN_TDL1R_DATA1 0x0000FF00U
1950 #define CAN_TDL1R_DATA2 0x00FF0000U
1951 #define CAN_TDL1R_DATA3 0xFF000000U
1953 /******************* Bit definition for CAN_TDH1R register ******************/
1954 #define CAN_TDH1R_DATA4 0x000000FFU
1955 #define CAN_TDH1R_DATA5 0x0000FF00U
1956 #define CAN_TDH1R_DATA6 0x00FF0000U
1957 #define CAN_TDH1R_DATA7 0xFF000000U
1959 /******************* Bit definition for CAN_TI2R register *******************/
1960 #define CAN_TI2R_TXRQ 0x00000001U
1961 #define CAN_TI2R_RTR 0x00000002U
1962 #define CAN_TI2R_IDE 0x00000004U
1963 #define CAN_TI2R_EXID 0x001FFFF8U
1964 #define CAN_TI2R_STID 0xFFE00000U
1966 /******************* Bit definition for CAN_TDT2R register ******************/
1967 #define CAN_TDT2R_DLC 0x0000000FU
1968 #define CAN_TDT2R_TGT 0x00000100U
1969 #define CAN_TDT2R_TIME 0xFFFF0000U
1971 /******************* Bit definition for CAN_TDL2R register ******************/
1972 #define CAN_TDL2R_DATA0 0x000000FFU
1973 #define CAN_TDL2R_DATA1 0x0000FF00U
1974 #define CAN_TDL2R_DATA2 0x00FF0000U
1975 #define CAN_TDL2R_DATA3 0xFF000000U
1977 /******************* Bit definition for CAN_TDH2R register ******************/
1978 #define CAN_TDH2R_DATA4 0x000000FFU
1979 #define CAN_TDH2R_DATA5 0x0000FF00U
1980 #define CAN_TDH2R_DATA6 0x00FF0000U
1981 #define CAN_TDH2R_DATA7 0xFF000000U
1983 /******************* Bit definition for CAN_RI0R register *******************/
1984 #define CAN_RI0R_RTR 0x00000002U
1985 #define CAN_RI0R_IDE 0x00000004U
1986 #define CAN_RI0R_EXID 0x001FFFF8U
1987 #define CAN_RI0R_STID 0xFFE00000U
1989 /******************* Bit definition for CAN_RDT0R register ******************/
1990 #define CAN_RDT0R_DLC 0x0000000FU
1991 #define CAN_RDT0R_FMI 0x0000FF00U
1992 #define CAN_RDT0R_TIME 0xFFFF0000U
1994 /******************* Bit definition for CAN_RDL0R register ******************/
1995 #define CAN_RDL0R_DATA0 0x000000FFU
1996 #define CAN_RDL0R_DATA1 0x0000FF00U
1997 #define CAN_RDL0R_DATA2 0x00FF0000U
1998 #define CAN_RDL0R_DATA3 0xFF000000U
2000 /******************* Bit definition for CAN_RDH0R register ******************/
2001 #define CAN_RDH0R_DATA4 0x000000FFU
2002 #define CAN_RDH0R_DATA5 0x0000FF00U
2003 #define CAN_RDH0R_DATA6 0x00FF0000U
2004 #define CAN_RDH0R_DATA7 0xFF000000U
2006 /******************* Bit definition for CAN_RI1R register *******************/
2007 #define CAN_RI1R_RTR 0x00000002U
2008 #define CAN_RI1R_IDE 0x00000004U
2009 #define CAN_RI1R_EXID 0x001FFFF8U
2010 #define CAN_RI1R_STID 0xFFE00000U
2012 /******************* Bit definition for CAN_RDT1R register ******************/
2013 #define CAN_RDT1R_DLC 0x0000000FU
2014 #define CAN_RDT1R_FMI 0x0000FF00U
2015 #define CAN_RDT1R_TIME 0xFFFF0000U
2017 /******************* Bit definition for CAN_RDL1R register ******************/
2018 #define CAN_RDL1R_DATA0 0x000000FFU
2019 #define CAN_RDL1R_DATA1 0x0000FF00U
2020 #define CAN_RDL1R_DATA2 0x00FF0000U
2021 #define CAN_RDL1R_DATA3 0xFF000000U
2023 /******************* Bit definition for CAN_RDH1R register ******************/
2024 #define CAN_RDH1R_DATA4 0x000000FFU
2025 #define CAN_RDH1R_DATA5 0x0000FF00U
2026 #define CAN_RDH1R_DATA6 0x00FF0000U
2027 #define CAN_RDH1R_DATA7 0xFF000000U
2030 /******************* Bit definition for CAN_FMR register ********************/
2031 #define CAN_FMR_FINIT ((uint8_t)0x01U)
2032 #define CAN_FMR_CAN2SB 0x00003F00U
2034 /******************* Bit definition for CAN_FM1R register *******************/
2035 #define CAN_FM1R_FBM 0x3FFFU
2036 #define CAN_FM1R_FBM0 0x0001U
2037 #define CAN_FM1R_FBM1 0x0002U
2038 #define CAN_FM1R_FBM2 0x0004U
2039 #define CAN_FM1R_FBM3 0x0008U
2040 #define CAN_FM1R_FBM4 0x0010U
2041 #define CAN_FM1R_FBM5 0x0020U
2042 #define CAN_FM1R_FBM6 0x0040U
2043 #define CAN_FM1R_FBM7 0x0080U
2044 #define CAN_FM1R_FBM8 0x0100U
2045 #define CAN_FM1R_FBM9 0x0200U
2046 #define CAN_FM1R_FBM10 0x0400U
2047 #define CAN_FM1R_FBM11 0x0800U
2048 #define CAN_FM1R_FBM12 0x1000U
2049 #define CAN_FM1R_FBM13 0x2000U
2051 /******************* Bit definition for CAN_FS1R register *******************/
2052 #define CAN_FS1R_FSC 0x00003FFFU
2053 #define CAN_FS1R_FSC0 0x00000001U
2054 #define CAN_FS1R_FSC1 0x00000002U
2055 #define CAN_FS1R_FSC2 0x00000004U
2056 #define CAN_FS1R_FSC3 0x00000008U
2057 #define CAN_FS1R_FSC4 0x00000010U
2058 #define CAN_FS1R_FSC5 0x00000020U
2059 #define CAN_FS1R_FSC6 0x00000040U
2060 #define CAN_FS1R_FSC7 0x00000080U
2061 #define CAN_FS1R_FSC8 0x00000100U
2062 #define CAN_FS1R_FSC9 0x00000200U
2063 #define CAN_FS1R_FSC10 0x00000400U
2064 #define CAN_FS1R_FSC11 0x00000800U
2065 #define CAN_FS1R_FSC12 0x00001000U
2066 #define CAN_FS1R_FSC13 0x00002000U
2068 /****************** Bit definition for CAN_FFA1R register *******************/
2069 #define CAN_FFA1R_FFA 0x00003FFFU
2070 #define CAN_FFA1R_FFA0 0x00000001U
2071 #define CAN_FFA1R_FFA1 0x00000002U
2072 #define CAN_FFA1R_FFA2 0x00000004U
2073 #define CAN_FFA1R_FFA3 0x00000008U
2074 #define CAN_FFA1R_FFA4 0x00000010U
2075 #define CAN_FFA1R_FFA5 0x00000020U
2076 #define CAN_FFA1R_FFA6 0x00000040U
2077 #define CAN_FFA1R_FFA7 0x00000080U
2078 #define CAN_FFA1R_FFA8 0x00000100U
2079 #define CAN_FFA1R_FFA9 0x00000200U
2080 #define CAN_FFA1R_FFA10 0x00000400U
2081 #define CAN_FFA1R_FFA11 0x00000800U
2082 #define CAN_FFA1R_FFA12 0x00001000U
2083 #define CAN_FFA1R_FFA13 0x00002000U
2085 /******************* Bit definition for CAN_FA1R register *******************/
2086 #define CAN_FA1R_FACT 0x00003FFFU
2087 #define CAN_FA1R_FACT0 0x00000001U
2088 #define CAN_FA1R_FACT1 0x00000002U
2089 #define CAN_FA1R_FACT2 0x00000004U
2090 #define CAN_FA1R_FACT3 0x00000008U
2091 #define CAN_FA1R_FACT4 0x00000010U
2092 #define CAN_FA1R_FACT5 0x00000020U
2093 #define CAN_FA1R_FACT6 0x00000040U
2094 #define CAN_FA1R_FACT7 0x00000080U
2095 #define CAN_FA1R_FACT8 0x00000100U
2096 #define CAN_FA1R_FACT9 0x00000200U
2097 #define CAN_FA1R_FACT10 0x00000400U
2098 #define CAN_FA1R_FACT11 0x00000800U
2099 #define CAN_FA1R_FACT12 0x00001000U
2100 #define CAN_FA1R_FACT13 0x00002000U
2102 /******************* Bit definition for CAN_F0R1 register *******************/
2103 #define CAN_F0R1_FB0 0x00000001U
2104 #define CAN_F0R1_FB1 0x00000002U
2105 #define CAN_F0R1_FB2 0x00000004U
2106 #define CAN_F0R1_FB3 0x00000008U
2107 #define CAN_F0R1_FB4 0x00000010U
2108 #define CAN_F0R1_FB5 0x00000020U
2109 #define CAN_F0R1_FB6 0x00000040U
2110 #define CAN_F0R1_FB7 0x00000080U
2111 #define CAN_F0R1_FB8 0x00000100U
2112 #define CAN_F0R1_FB9 0x00000200U
2113 #define CAN_F0R1_FB10 0x00000400U
2114 #define CAN_F0R1_FB11 0x00000800U
2115 #define CAN_F0R1_FB12 0x00001000U
2116 #define CAN_F0R1_FB13 0x00002000U
2117 #define CAN_F0R1_FB14 0x00004000U
2118 #define CAN_F0R1_FB15 0x00008000U
2119 #define CAN_F0R1_FB16 0x00010000U
2120 #define CAN_F0R1_FB17 0x00020000U
2121 #define CAN_F0R1_FB18 0x00040000U
2122 #define CAN_F0R1_FB19 0x00080000U
2123 #define CAN_F0R1_FB20 0x00100000U
2124 #define CAN_F0R1_FB21 0x00200000U
2125 #define CAN_F0R1_FB22 0x00400000U
2126 #define CAN_F0R1_FB23 0x00800000U
2127 #define CAN_F0R1_FB24 0x01000000U
2128 #define CAN_F0R1_FB25 0x02000000U
2129 #define CAN_F0R1_FB26 0x04000000U
2130 #define CAN_F0R1_FB27 0x08000000U
2131 #define CAN_F0R1_FB28 0x10000000U
2132 #define CAN_F0R1_FB29 0x20000000U
2133 #define CAN_F0R1_FB30 0x40000000U
2134 #define CAN_F0R1_FB31 0x80000000U
2136 /******************* Bit definition for CAN_F1R1 register *******************/
2137 #define CAN_F1R1_FB0 0x00000001U
2138 #define CAN_F1R1_FB1 0x00000002U
2139 #define CAN_F1R1_FB2 0x00000004U
2140 #define CAN_F1R1_FB3 0x00000008U
2141 #define CAN_F1R1_FB4 0x00000010U
2142 #define CAN_F1R1_FB5 0x00000020U
2143 #define CAN_F1R1_FB6 0x00000040U
2144 #define CAN_F1R1_FB7 0x00000080U
2145 #define CAN_F1R1_FB8 0x00000100U
2146 #define CAN_F1R1_FB9 0x00000200U
2147 #define CAN_F1R1_FB10 0x00000400U
2148 #define CAN_F1R1_FB11 0x00000800U
2149 #define CAN_F1R1_FB12 0x00001000U
2150 #define CAN_F1R1_FB13 0x00002000U
2151 #define CAN_F1R1_FB14 0x00004000U
2152 #define CAN_F1R1_FB15 0x00008000U
2153 #define CAN_F1R1_FB16 0x00010000U
2154 #define CAN_F1R1_FB17 0x00020000U
2155 #define CAN_F1R1_FB18 0x00040000U
2156 #define CAN_F1R1_FB19 0x00080000U
2157 #define CAN_F1R1_FB20 0x00100000U
2158 #define CAN_F1R1_FB21 0x00200000U
2159 #define CAN_F1R1_FB22 0x00400000U
2160 #define CAN_F1R1_FB23 0x00800000U
2161 #define CAN_F1R1_FB24 0x01000000U
2162 #define CAN_F1R1_FB25 0x02000000U
2163 #define CAN_F1R1_FB26 0x04000000U
2164 #define CAN_F1R1_FB27 0x08000000U
2165 #define CAN_F1R1_FB28 0x10000000U
2166 #define CAN_F1R1_FB29 0x20000000U
2167 #define CAN_F1R1_FB30 0x40000000U
2168 #define CAN_F1R1_FB31 0x80000000U
2170 /******************* Bit definition for CAN_F2R1 register *******************/
2171 #define CAN_F2R1_FB0 0x00000001U
2172 #define CAN_F2R1_FB1 0x00000002U
2173 #define CAN_F2R1_FB2 0x00000004U
2174 #define CAN_F2R1_FB3 0x00000008U
2175 #define CAN_F2R1_FB4 0x00000010U
2176 #define CAN_F2R1_FB5 0x00000020U
2177 #define CAN_F2R1_FB6 0x00000040U
2178 #define CAN_F2R1_FB7 0x00000080U
2179 #define CAN_F2R1_FB8 0x00000100U
2180 #define CAN_F2R1_FB9 0x00000200U
2181 #define CAN_F2R1_FB10 0x00000400U
2182 #define CAN_F2R1_FB11 0x00000800U
2183 #define CAN_F2R1_FB12 0x00001000U
2184 #define CAN_F2R1_FB13 0x00002000U
2185 #define CAN_F2R1_FB14 0x00004000U
2186 #define CAN_F2R1_FB15 0x00008000U
2187 #define CAN_F2R1_FB16 0x00010000U
2188 #define CAN_F2R1_FB17 0x00020000U
2189 #define CAN_F2R1_FB18 0x00040000U
2190 #define CAN_F2R1_FB19 0x00080000U
2191 #define CAN_F2R1_FB20 0x00100000U
2192 #define CAN_F2R1_FB21 0x00200000U
2193 #define CAN_F2R1_FB22 0x00400000U
2194 #define CAN_F2R1_FB23 0x00800000U
2195 #define CAN_F2R1_FB24 0x01000000U
2196 #define CAN_F2R1_FB25 0x02000000U
2197 #define CAN_F2R1_FB26 0x04000000U
2198 #define CAN_F2R1_FB27 0x08000000U
2199 #define CAN_F2R1_FB28 0x10000000U
2200 #define CAN_F2R1_FB29 0x20000000U
2201 #define CAN_F2R1_FB30 0x40000000U
2202 #define CAN_F2R1_FB31 0x80000000U
2204 /******************* Bit definition for CAN_F3R1 register *******************/
2205 #define CAN_F3R1_FB0 0x00000001U
2206 #define CAN_F3R1_FB1 0x00000002U
2207 #define CAN_F3R1_FB2 0x00000004U
2208 #define CAN_F3R1_FB3 0x00000008U
2209 #define CAN_F3R1_FB4 0x00000010U
2210 #define CAN_F3R1_FB5 0x00000020U
2211 #define CAN_F3R1_FB6 0x00000040U
2212 #define CAN_F3R1_FB7 0x00000080U
2213 #define CAN_F3R1_FB8 0x00000100U
2214 #define CAN_F3R1_FB9 0x00000200U
2215 #define CAN_F3R1_FB10 0x00000400U
2216 #define CAN_F3R1_FB11 0x00000800U
2217 #define CAN_F3R1_FB12 0x00001000U
2218 #define CAN_F3R1_FB13 0x00002000U
2219 #define CAN_F3R1_FB14 0x00004000U
2220 #define CAN_F3R1_FB15 0x00008000U
2221 #define CAN_F3R1_FB16 0x00010000U
2222 #define CAN_F3R1_FB17 0x00020000U
2223 #define CAN_F3R1_FB18 0x00040000U
2224 #define CAN_F3R1_FB19 0x00080000U
2225 #define CAN_F3R1_FB20 0x00100000U
2226 #define CAN_F3R1_FB21 0x00200000U
2227 #define CAN_F3R1_FB22 0x00400000U
2228 #define CAN_F3R1_FB23 0x00800000U
2229 #define CAN_F3R1_FB24 0x01000000U
2230 #define CAN_F3R1_FB25 0x02000000U
2231 #define CAN_F3R1_FB26 0x04000000U
2232 #define CAN_F3R1_FB27 0x08000000U
2233 #define CAN_F3R1_FB28 0x10000000U
2234 #define CAN_F3R1_FB29 0x20000000U
2235 #define CAN_F3R1_FB30 0x40000000U
2236 #define CAN_F3R1_FB31 0x80000000U
2238 /******************* Bit definition for CAN_F4R1 register *******************/
2239 #define CAN_F4R1_FB0 0x00000001U
2240 #define CAN_F4R1_FB1 0x00000002U
2241 #define CAN_F4R1_FB2 0x00000004U
2242 #define CAN_F4R1_FB3 0x00000008U
2243 #define CAN_F4R1_FB4 0x00000010U
2244 #define CAN_F4R1_FB5 0x00000020U
2245 #define CAN_F4R1_FB6 0x00000040U
2246 #define CAN_F4R1_FB7 0x00000080U
2247 #define CAN_F4R1_FB8 0x00000100U
2248 #define CAN_F4R1_FB9 0x00000200U
2249 #define CAN_F4R1_FB10 0x00000400U
2250 #define CAN_F4R1_FB11 0x00000800U
2251 #define CAN_F4R1_FB12 0x00001000U
2252 #define CAN_F4R1_FB13 0x00002000U
2253 #define CAN_F4R1_FB14 0x00004000U
2254 #define CAN_F4R1_FB15 0x00008000U
2255 #define CAN_F4R1_FB16 0x00010000U
2256 #define CAN_F4R1_FB17 0x00020000U
2257 #define CAN_F4R1_FB18 0x00040000U
2258 #define CAN_F4R1_FB19 0x00080000U
2259 #define CAN_F4R1_FB20 0x00100000U
2260 #define CAN_F4R1_FB21 0x00200000U
2261 #define CAN_F4R1_FB22 0x00400000U
2262 #define CAN_F4R1_FB23 0x00800000U
2263 #define CAN_F4R1_FB24 0x01000000U
2264 #define CAN_F4R1_FB25 0x02000000U
2265 #define CAN_F4R1_FB26 0x04000000U
2266 #define CAN_F4R1_FB27 0x08000000U
2267 #define CAN_F4R1_FB28 0x10000000U
2268 #define CAN_F4R1_FB29 0x20000000U
2269 #define CAN_F4R1_FB30 0x40000000U
2270 #define CAN_F4R1_FB31 0x80000000U
2272 /******************* Bit definition for CAN_F5R1 register *******************/
2273 #define CAN_F5R1_FB0 0x00000001U
2274 #define CAN_F5R1_FB1 0x00000002U
2275 #define CAN_F5R1_FB2 0x00000004U
2276 #define CAN_F5R1_FB3 0x00000008U
2277 #define CAN_F5R1_FB4 0x00000010U
2278 #define CAN_F5R1_FB5 0x00000020U
2279 #define CAN_F5R1_FB6 0x00000040U
2280 #define CAN_F5R1_FB7 0x00000080U
2281 #define CAN_F5R1_FB8 0x00000100U
2282 #define CAN_F5R1_FB9 0x00000200U
2283 #define CAN_F5R1_FB10 0x00000400U
2284 #define CAN_F5R1_FB11 0x00000800U
2285 #define CAN_F5R1_FB12 0x00001000U
2286 #define CAN_F5R1_FB13 0x00002000U
2287 #define CAN_F5R1_FB14 0x00004000U
2288 #define CAN_F5R1_FB15 0x00008000U
2289 #define CAN_F5R1_FB16 0x00010000U
2290 #define CAN_F5R1_FB17 0x00020000U
2291 #define CAN_F5R1_FB18 0x00040000U
2292 #define CAN_F5R1_FB19 0x00080000U
2293 #define CAN_F5R1_FB20 0x00100000U
2294 #define CAN_F5R1_FB21 0x00200000U
2295 #define CAN_F5R1_FB22 0x00400000U
2296 #define CAN_F5R1_FB23 0x00800000U
2297 #define CAN_F5R1_FB24 0x01000000U
2298 #define CAN_F5R1_FB25 0x02000000U
2299 #define CAN_F5R1_FB26 0x04000000U
2300 #define CAN_F5R1_FB27 0x08000000U
2301 #define CAN_F5R1_FB28 0x10000000U
2302 #define CAN_F5R1_FB29 0x20000000U
2303 #define CAN_F5R1_FB30 0x40000000U
2304 #define CAN_F5R1_FB31 0x80000000U
2306 /******************* Bit definition for CAN_F6R1 register *******************/
2307 #define CAN_F6R1_FB0 0x00000001U
2308 #define CAN_F6R1_FB1 0x00000002U
2309 #define CAN_F6R1_FB2 0x00000004U
2310 #define CAN_F6R1_FB3 0x00000008U
2311 #define CAN_F6R1_FB4 0x00000010U
2312 #define CAN_F6R1_FB5 0x00000020U
2313 #define CAN_F6R1_FB6 0x00000040U
2314 #define CAN_F6R1_FB7 0x00000080U
2315 #define CAN_F6R1_FB8 0x00000100U
2316 #define CAN_F6R1_FB9 0x00000200U
2317 #define CAN_F6R1_FB10 0x00000400U
2318 #define CAN_F6R1_FB11 0x00000800U
2319 #define CAN_F6R1_FB12 0x00001000U
2320 #define CAN_F6R1_FB13 0x00002000U
2321 #define CAN_F6R1_FB14 0x00004000U
2322 #define CAN_F6R1_FB15 0x00008000U
2323 #define CAN_F6R1_FB16 0x00010000U
2324 #define CAN_F6R1_FB17 0x00020000U
2325 #define CAN_F6R1_FB18 0x00040000U
2326 #define CAN_F6R1_FB19 0x00080000U
2327 #define CAN_F6R1_FB20 0x00100000U
2328 #define CAN_F6R1_FB21 0x00200000U
2329 #define CAN_F6R1_FB22 0x00400000U
2330 #define CAN_F6R1_FB23 0x00800000U
2331 #define CAN_F6R1_FB24 0x01000000U
2332 #define CAN_F6R1_FB25 0x02000000U
2333 #define CAN_F6R1_FB26 0x04000000U
2334 #define CAN_F6R1_FB27 0x08000000U
2335 #define CAN_F6R1_FB28 0x10000000U
2336 #define CAN_F6R1_FB29 0x20000000U
2337 #define CAN_F6R1_FB30 0x40000000U
2338 #define CAN_F6R1_FB31 0x80000000U
2340 /******************* Bit definition for CAN_F7R1 register *******************/
2341 #define CAN_F7R1_FB0 0x00000001U
2342 #define CAN_F7R1_FB1 0x00000002U
2343 #define CAN_F7R1_FB2 0x00000004U
2344 #define CAN_F7R1_FB3 0x00000008U
2345 #define CAN_F7R1_FB4 0x00000010U
2346 #define CAN_F7R1_FB5 0x00000020U
2347 #define CAN_F7R1_FB6 0x00000040U
2348 #define CAN_F7R1_FB7 0x00000080U
2349 #define CAN_F7R1_FB8 0x00000100U
2350 #define CAN_F7R1_FB9 0x00000200U
2351 #define CAN_F7R1_FB10 0x00000400U
2352 #define CAN_F7R1_FB11 0x00000800U
2353 #define CAN_F7R1_FB12 0x00001000U
2354 #define CAN_F7R1_FB13 0x00002000U
2355 #define CAN_F7R1_FB14 0x00004000U
2356 #define CAN_F7R1_FB15 0x00008000U
2357 #define CAN_F7R1_FB16 0x00010000U
2358 #define CAN_F7R1_FB17 0x00020000U
2359 #define CAN_F7R1_FB18 0x00040000U
2360 #define CAN_F7R1_FB19 0x00080000U
2361 #define CAN_F7R1_FB20 0x00100000U
2362 #define CAN_F7R1_FB21 0x00200000U
2363 #define CAN_F7R1_FB22 0x00400000U
2364 #define CAN_F7R1_FB23 0x00800000U
2365 #define CAN_F7R1_FB24 0x01000000U
2366 #define CAN_F7R1_FB25 0x02000000U
2367 #define CAN_F7R1_FB26 0x04000000U
2368 #define CAN_F7R1_FB27 0x08000000U
2369 #define CAN_F7R1_FB28 0x10000000U
2370 #define CAN_F7R1_FB29 0x20000000U
2371 #define CAN_F7R1_FB30 0x40000000U
2372 #define CAN_F7R1_FB31 0x80000000U
2374 /******************* Bit definition for CAN_F8R1 register *******************/
2375 #define CAN_F8R1_FB0 0x00000001U
2376 #define CAN_F8R1_FB1 0x00000002U
2377 #define CAN_F8R1_FB2 0x00000004U
2378 #define CAN_F8R1_FB3 0x00000008U
2379 #define CAN_F8R1_FB4 0x00000010U
2380 #define CAN_F8R1_FB5 0x00000020U
2381 #define CAN_F8R1_FB6 0x00000040U
2382 #define CAN_F8R1_FB7 0x00000080U
2383 #define CAN_F8R1_FB8 0x00000100U
2384 #define CAN_F8R1_FB9 0x00000200U
2385 #define CAN_F8R1_FB10 0x00000400U
2386 #define CAN_F8R1_FB11 0x00000800U
2387 #define CAN_F8R1_FB12 0x00001000U
2388 #define CAN_F8R1_FB13 0x00002000U
2389 #define CAN_F8R1_FB14 0x00004000U
2390 #define CAN_F8R1_FB15 0x00008000U
2391 #define CAN_F8R1_FB16 0x00010000U
2392 #define CAN_F8R1_FB17 0x00020000U
2393 #define CAN_F8R1_FB18 0x00040000U
2394 #define CAN_F8R1_FB19 0x00080000U
2395 #define CAN_F8R1_FB20 0x00100000U
2396 #define CAN_F8R1_FB21 0x00200000U
2397 #define CAN_F8R1_FB22 0x00400000U
2398 #define CAN_F8R1_FB23 0x00800000U
2399 #define CAN_F8R1_FB24 0x01000000U
2400 #define CAN_F8R1_FB25 0x02000000U
2401 #define CAN_F8R1_FB26 0x04000000U
2402 #define CAN_F8R1_FB27 0x08000000U
2403 #define CAN_F8R1_FB28 0x10000000U
2404 #define CAN_F8R1_FB29 0x20000000U
2405 #define CAN_F8R1_FB30 0x40000000U
2406 #define CAN_F8R1_FB31 0x80000000U
2408 /******************* Bit definition for CAN_F9R1 register *******************/
2409 #define CAN_F9R1_FB0 0x00000001U
2410 #define CAN_F9R1_FB1 0x00000002U
2411 #define CAN_F9R1_FB2 0x00000004U
2412 #define CAN_F9R1_FB3 0x00000008U
2413 #define CAN_F9R1_FB4 0x00000010U
2414 #define CAN_F9R1_FB5 0x00000020U
2415 #define CAN_F9R1_FB6 0x00000040U
2416 #define CAN_F9R1_FB7 0x00000080U
2417 #define CAN_F9R1_FB8 0x00000100U
2418 #define CAN_F9R1_FB9 0x00000200U
2419 #define CAN_F9R1_FB10 0x00000400U
2420 #define CAN_F9R1_FB11 0x00000800U
2421 #define CAN_F9R1_FB12 0x00001000U
2422 #define CAN_F9R1_FB13 0x00002000U
2423 #define CAN_F9R1_FB14 0x00004000U
2424 #define CAN_F9R1_FB15 0x00008000U
2425 #define CAN_F9R1_FB16 0x00010000U
2426 #define CAN_F9R1_FB17 0x00020000U
2427 #define CAN_F9R1_FB18 0x00040000U
2428 #define CAN_F9R1_FB19 0x00080000U
2429 #define CAN_F9R1_FB20 0x00100000U
2430 #define CAN_F9R1_FB21 0x00200000U
2431 #define CAN_F9R1_FB22 0x00400000U
2432 #define CAN_F9R1_FB23 0x00800000U
2433 #define CAN_F9R1_FB24 0x01000000U
2434 #define CAN_F9R1_FB25 0x02000000U
2435 #define CAN_F9R1_FB26 0x04000000U
2436 #define CAN_F9R1_FB27 0x08000000U
2437 #define CAN_F9R1_FB28 0x10000000U
2438 #define CAN_F9R1_FB29 0x20000000U
2439 #define CAN_F9R1_FB30 0x40000000U
2440 #define CAN_F9R1_FB31 0x80000000U
2442 /******************* Bit definition for CAN_F10R1 register ******************/
2443 #define CAN_F10R1_FB0 0x00000001U
2444 #define CAN_F10R1_FB1 0x00000002U
2445 #define CAN_F10R1_FB2 0x00000004U
2446 #define CAN_F10R1_FB3 0x00000008U
2447 #define CAN_F10R1_FB4 0x00000010U
2448 #define CAN_F10R1_FB5 0x00000020U
2449 #define CAN_F10R1_FB6 0x00000040U
2450 #define CAN_F10R1_FB7 0x00000080U
2451 #define CAN_F10R1_FB8 0x00000100U
2452 #define CAN_F10R1_FB9 0x00000200U
2453 #define CAN_F10R1_FB10 0x00000400U
2454 #define CAN_F10R1_FB11 0x00000800U
2455 #define CAN_F10R1_FB12 0x00001000U
2456 #define CAN_F10R1_FB13 0x00002000U
2457 #define CAN_F10R1_FB14 0x00004000U
2458 #define CAN_F10R1_FB15 0x00008000U
2459 #define CAN_F10R1_FB16 0x00010000U
2460 #define CAN_F10R1_FB17 0x00020000U
2461 #define CAN_F10R1_FB18 0x00040000U
2462 #define CAN_F10R1_FB19 0x00080000U
2463 #define CAN_F10R1_FB20 0x00100000U
2464 #define CAN_F10R1_FB21 0x00200000U
2465 #define CAN_F10R1_FB22 0x00400000U
2466 #define CAN_F10R1_FB23 0x00800000U
2467 #define CAN_F10R1_FB24 0x01000000U
2468 #define CAN_F10R1_FB25 0x02000000U
2469 #define CAN_F10R1_FB26 0x04000000U
2470 #define CAN_F10R1_FB27 0x08000000U
2471 #define CAN_F10R1_FB28 0x10000000U
2472 #define CAN_F10R1_FB29 0x20000000U
2473 #define CAN_F10R1_FB30 0x40000000U
2474 #define CAN_F10R1_FB31 0x80000000U
2476 /******************* Bit definition for CAN_F11R1 register ******************/
2477 #define CAN_F11R1_FB0 0x00000001U
2478 #define CAN_F11R1_FB1 0x00000002U
2479 #define CAN_F11R1_FB2 0x00000004U
2480 #define CAN_F11R1_FB3 0x00000008U
2481 #define CAN_F11R1_FB4 0x00000010U
2482 #define CAN_F11R1_FB5 0x00000020U
2483 #define CAN_F11R1_FB6 0x00000040U
2484 #define CAN_F11R1_FB7 0x00000080U
2485 #define CAN_F11R1_FB8 0x00000100U
2486 #define CAN_F11R1_FB9 0x00000200U
2487 #define CAN_F11R1_FB10 0x00000400U
2488 #define CAN_F11R1_FB11 0x00000800U
2489 #define CAN_F11R1_FB12 0x00001000U
2490 #define CAN_F11R1_FB13 0x00002000U
2491 #define CAN_F11R1_FB14 0x00004000U
2492 #define CAN_F11R1_FB15 0x00008000U
2493 #define CAN_F11R1_FB16 0x00010000U
2494 #define CAN_F11R1_FB17 0x00020000U
2495 #define CAN_F11R1_FB18 0x00040000U
2496 #define CAN_F11R1_FB19 0x00080000U
2497 #define CAN_F11R1_FB20 0x00100000U
2498 #define CAN_F11R1_FB21 0x00200000U
2499 #define CAN_F11R1_FB22 0x00400000U
2500 #define CAN_F11R1_FB23 0x00800000U
2501 #define CAN_F11R1_FB24 0x01000000U
2502 #define CAN_F11R1_FB25 0x02000000U
2503 #define CAN_F11R1_FB26 0x04000000U
2504 #define CAN_F11R1_FB27 0x08000000U
2505 #define CAN_F11R1_FB28 0x10000000U
2506 #define CAN_F11R1_FB29 0x20000000U
2507 #define CAN_F11R1_FB30 0x40000000U
2508 #define CAN_F11R1_FB31 0x80000000U
2510 /******************* Bit definition for CAN_F12R1 register ******************/
2511 #define CAN_F12R1_FB0 0x00000001U
2512 #define CAN_F12R1_FB1 0x00000002U
2513 #define CAN_F12R1_FB2 0x00000004U
2514 #define CAN_F12R1_FB3 0x00000008U
2515 #define CAN_F12R1_FB4 0x00000010U
2516 #define CAN_F12R1_FB5 0x00000020U
2517 #define CAN_F12R1_FB6 0x00000040U
2518 #define CAN_F12R1_FB7 0x00000080U
2519 #define CAN_F12R1_FB8 0x00000100U
2520 #define CAN_F12R1_FB9 0x00000200U
2521 #define CAN_F12R1_FB10 0x00000400U
2522 #define CAN_F12R1_FB11 0x00000800U
2523 #define CAN_F12R1_FB12 0x00001000U
2524 #define CAN_F12R1_FB13 0x00002000U
2525 #define CAN_F12R1_FB14 0x00004000U
2526 #define CAN_F12R1_FB15 0x00008000U
2527 #define CAN_F12R1_FB16 0x00010000U
2528 #define CAN_F12R1_FB17 0x00020000U
2529 #define CAN_F12R1_FB18 0x00040000U
2530 #define CAN_F12R1_FB19 0x00080000U
2531 #define CAN_F12R1_FB20 0x00100000U
2532 #define CAN_F12R1_FB21 0x00200000U
2533 #define CAN_F12R1_FB22 0x00400000U
2534 #define CAN_F12R1_FB23 0x00800000U
2535 #define CAN_F12R1_FB24 0x01000000U
2536 #define CAN_F12R1_FB25 0x02000000U
2537 #define CAN_F12R1_FB26 0x04000000U
2538 #define CAN_F12R1_FB27 0x08000000U
2539 #define CAN_F12R1_FB28 0x10000000U
2540 #define CAN_F12R1_FB29 0x20000000U
2541 #define CAN_F12R1_FB30 0x40000000U
2542 #define CAN_F12R1_FB31 0x80000000U
2544 /******************* Bit definition for CAN_F13R1 register ******************/
2545 #define CAN_F13R1_FB0 0x00000001U
2546 #define CAN_F13R1_FB1 0x00000002U
2547 #define CAN_F13R1_FB2 0x00000004U
2548 #define CAN_F13R1_FB3 0x00000008U
2549 #define CAN_F13R1_FB4 0x00000010U
2550 #define CAN_F13R1_FB5 0x00000020U
2551 #define CAN_F13R1_FB6 0x00000040U
2552 #define CAN_F13R1_FB7 0x00000080U
2553 #define CAN_F13R1_FB8 0x00000100U
2554 #define CAN_F13R1_FB9 0x00000200U
2555 #define CAN_F13R1_FB10 0x00000400U
2556 #define CAN_F13R1_FB11 0x00000800U
2557 #define CAN_F13R1_FB12 0x00001000U
2558 #define CAN_F13R1_FB13 0x00002000U
2559 #define CAN_F13R1_FB14 0x00004000U
2560 #define CAN_F13R1_FB15 0x00008000U
2561 #define CAN_F13R1_FB16 0x00010000U
2562 #define CAN_F13R1_FB17 0x00020000U
2563 #define CAN_F13R1_FB18 0x00040000U
2564 #define CAN_F13R1_FB19 0x00080000U
2565 #define CAN_F13R1_FB20 0x00100000U
2566 #define CAN_F13R1_FB21 0x00200000U
2567 #define CAN_F13R1_FB22 0x00400000U
2568 #define CAN_F13R1_FB23 0x00800000U
2569 #define CAN_F13R1_FB24 0x01000000U
2570 #define CAN_F13R1_FB25 0x02000000U
2571 #define CAN_F13R1_FB26 0x04000000U
2572 #define CAN_F13R1_FB27 0x08000000U
2573 #define CAN_F13R1_FB28 0x10000000U
2574 #define CAN_F13R1_FB29 0x20000000U
2575 #define CAN_F13R1_FB30 0x40000000U
2576 #define CAN_F13R1_FB31 0x80000000U
2578 /******************* Bit definition for CAN_F0R2 register *******************/
2579 #define CAN_F0R2_FB0 0x00000001U
2580 #define CAN_F0R2_FB1 0x00000002U
2581 #define CAN_F0R2_FB2 0x00000004U
2582 #define CAN_F0R2_FB3 0x00000008U
2583 #define CAN_F0R2_FB4 0x00000010U
2584 #define CAN_F0R2_FB5 0x00000020U
2585 #define CAN_F0R2_FB6 0x00000040U
2586 #define CAN_F0R2_FB7 0x00000080U
2587 #define CAN_F0R2_FB8 0x00000100U
2588 #define CAN_F0R2_FB9 0x00000200U
2589 #define CAN_F0R2_FB10 0x00000400U
2590 #define CAN_F0R2_FB11 0x00000800U
2591 #define CAN_F0R2_FB12 0x00001000U
2592 #define CAN_F0R2_FB13 0x00002000U
2593 #define CAN_F0R2_FB14 0x00004000U
2594 #define CAN_F0R2_FB15 0x00008000U
2595 #define CAN_F0R2_FB16 0x00010000U
2596 #define CAN_F0R2_FB17 0x00020000U
2597 #define CAN_F0R2_FB18 0x00040000U
2598 #define CAN_F0R2_FB19 0x00080000U
2599 #define CAN_F0R2_FB20 0x00100000U
2600 #define CAN_F0R2_FB21 0x00200000U
2601 #define CAN_F0R2_FB22 0x00400000U
2602 #define CAN_F0R2_FB23 0x00800000U
2603 #define CAN_F0R2_FB24 0x01000000U
2604 #define CAN_F0R2_FB25 0x02000000U
2605 #define CAN_F0R2_FB26 0x04000000U
2606 #define CAN_F0R2_FB27 0x08000000U
2607 #define CAN_F0R2_FB28 0x10000000U
2608 #define CAN_F0R2_FB29 0x20000000U
2609 #define CAN_F0R2_FB30 0x40000000U
2610 #define CAN_F0R2_FB31 0x80000000U
2612 /******************* Bit definition for CAN_F1R2 register *******************/
2613 #define CAN_F1R2_FB0 0x00000001U
2614 #define CAN_F1R2_FB1 0x00000002U
2615 #define CAN_F1R2_FB2 0x00000004U
2616 #define CAN_F1R2_FB3 0x00000008U
2617 #define CAN_F1R2_FB4 0x00000010U
2618 #define CAN_F1R2_FB5 0x00000020U
2619 #define CAN_F1R2_FB6 0x00000040U
2620 #define CAN_F1R2_FB7 0x00000080U
2621 #define CAN_F1R2_FB8 0x00000100U
2622 #define CAN_F1R2_FB9 0x00000200U
2623 #define CAN_F1R2_FB10 0x00000400U
2624 #define CAN_F1R2_FB11 0x00000800U
2625 #define CAN_F1R2_FB12 0x00001000U
2626 #define CAN_F1R2_FB13 0x00002000U
2627 #define CAN_F1R2_FB14 0x00004000U
2628 #define CAN_F1R2_FB15 0x00008000U
2629 #define CAN_F1R2_FB16 0x00010000U
2630 #define CAN_F1R2_FB17 0x00020000U
2631 #define CAN_F1R2_FB18 0x00040000U
2632 #define CAN_F1R2_FB19 0x00080000U
2633 #define CAN_F1R2_FB20 0x00100000U
2634 #define CAN_F1R2_FB21 0x00200000U
2635 #define CAN_F1R2_FB22 0x00400000U
2636 #define CAN_F1R2_FB23 0x00800000U
2637 #define CAN_F1R2_FB24 0x01000000U
2638 #define CAN_F1R2_FB25 0x02000000U
2639 #define CAN_F1R2_FB26 0x04000000U
2640 #define CAN_F1R2_FB27 0x08000000U
2641 #define CAN_F1R2_FB28 0x10000000U
2642 #define CAN_F1R2_FB29 0x20000000U
2643 #define CAN_F1R2_FB30 0x40000000U
2644 #define CAN_F1R2_FB31 0x80000000U
2646 /******************* Bit definition for CAN_F2R2 register *******************/
2647 #define CAN_F2R2_FB0 0x00000001U
2648 #define CAN_F2R2_FB1 0x00000002U
2649 #define CAN_F2R2_FB2 0x00000004U
2650 #define CAN_F2R2_FB3 0x00000008U
2651 #define CAN_F2R2_FB4 0x00000010U
2652 #define CAN_F2R2_FB5 0x00000020U
2653 #define CAN_F2R2_FB6 0x00000040U
2654 #define CAN_F2R2_FB7 0x00000080U
2655 #define CAN_F2R2_FB8 0x00000100U
2656 #define CAN_F2R2_FB9 0x00000200U
2657 #define CAN_F2R2_FB10 0x00000400U
2658 #define CAN_F2R2_FB11 0x00000800U
2659 #define CAN_F2R2_FB12 0x00001000U
2660 #define CAN_F2R2_FB13 0x00002000U
2661 #define CAN_F2R2_FB14 0x00004000U
2662 #define CAN_F2R2_FB15 0x00008000U
2663 #define CAN_F2R2_FB16 0x00010000U
2664 #define CAN_F2R2_FB17 0x00020000U
2665 #define CAN_F2R2_FB18 0x00040000U
2666 #define CAN_F2R2_FB19 0x00080000U
2667 #define CAN_F2R2_FB20 0x00100000U
2668 #define CAN_F2R2_FB21 0x00200000U
2669 #define CAN_F2R2_FB22 0x00400000U
2670 #define CAN_F2R2_FB23 0x00800000U
2671 #define CAN_F2R2_FB24 0x01000000U
2672 #define CAN_F2R2_FB25 0x02000000U
2673 #define CAN_F2R2_FB26 0x04000000U
2674 #define CAN_F2R2_FB27 0x08000000U
2675 #define CAN_F2R2_FB28 0x10000000U
2676 #define CAN_F2R2_FB29 0x20000000U
2677 #define CAN_F2R2_FB30 0x40000000U
2678 #define CAN_F2R2_FB31 0x80000000U
2680 /******************* Bit definition for CAN_F3R2 register *******************/
2681 #define CAN_F3R2_FB0 0x00000001U
2682 #define CAN_F3R2_FB1 0x00000002U
2683 #define CAN_F3R2_FB2 0x00000004U
2684 #define CAN_F3R2_FB3 0x00000008U
2685 #define CAN_F3R2_FB4 0x00000010U
2686 #define CAN_F3R2_FB5 0x00000020U
2687 #define CAN_F3R2_FB6 0x00000040U
2688 #define CAN_F3R2_FB7 0x00000080U
2689 #define CAN_F3R2_FB8 0x00000100U
2690 #define CAN_F3R2_FB9 0x00000200U
2691 #define CAN_F3R2_FB10 0x00000400U
2692 #define CAN_F3R2_FB11 0x00000800U
2693 #define CAN_F3R2_FB12 0x00001000U
2694 #define CAN_F3R2_FB13 0x00002000U
2695 #define CAN_F3R2_FB14 0x00004000U
2696 #define CAN_F3R2_FB15 0x00008000U
2697 #define CAN_F3R2_FB16 0x00010000U
2698 #define CAN_F3R2_FB17 0x00020000U
2699 #define CAN_F3R2_FB18 0x00040000U
2700 #define CAN_F3R2_FB19 0x00080000U
2701 #define CAN_F3R2_FB20 0x00100000U
2702 #define CAN_F3R2_FB21 0x00200000U
2703 #define CAN_F3R2_FB22 0x00400000U
2704 #define CAN_F3R2_FB23 0x00800000U
2705 #define CAN_F3R2_FB24 0x01000000U
2706 #define CAN_F3R2_FB25 0x02000000U
2707 #define CAN_F3R2_FB26 0x04000000U
2708 #define CAN_F3R2_FB27 0x08000000U
2709 #define CAN_F3R2_FB28 0x10000000U
2710 #define CAN_F3R2_FB29 0x20000000U
2711 #define CAN_F3R2_FB30 0x40000000U
2712 #define CAN_F3R2_FB31 0x80000000U
2714 /******************* Bit definition for CAN_F4R2 register *******************/
2715 #define CAN_F4R2_FB0 0x00000001U
2716 #define CAN_F4R2_FB1 0x00000002U
2717 #define CAN_F4R2_FB2 0x00000004U
2718 #define CAN_F4R2_FB3 0x00000008U
2719 #define CAN_F4R2_FB4 0x00000010U
2720 #define CAN_F4R2_FB5 0x00000020U
2721 #define CAN_F4R2_FB6 0x00000040U
2722 #define CAN_F4R2_FB7 0x00000080U
2723 #define CAN_F4R2_FB8 0x00000100U
2724 #define CAN_F4R2_FB9 0x00000200U
2725 #define CAN_F4R2_FB10 0x00000400U
2726 #define CAN_F4R2_FB11 0x00000800U
2727 #define CAN_F4R2_FB12 0x00001000U
2728 #define CAN_F4R2_FB13 0x00002000U
2729 #define CAN_F4R2_FB14 0x00004000U
2730 #define CAN_F4R2_FB15 0x00008000U
2731 #define CAN_F4R2_FB16 0x00010000U
2732 #define CAN_F4R2_FB17 0x00020000U
2733 #define CAN_F4R2_FB18 0x00040000U
2734 #define CAN_F4R2_FB19 0x00080000U
2735 #define CAN_F4R2_FB20 0x00100000U
2736 #define CAN_F4R2_FB21 0x00200000U
2737 #define CAN_F4R2_FB22 0x00400000U
2738 #define CAN_F4R2_FB23 0x00800000U
2739 #define CAN_F4R2_FB24 0x01000000U
2740 #define CAN_F4R2_FB25 0x02000000U
2741 #define CAN_F4R2_FB26 0x04000000U
2742 #define CAN_F4R2_FB27 0x08000000U
2743 #define CAN_F4R2_FB28 0x10000000U
2744 #define CAN_F4R2_FB29 0x20000000U
2745 #define CAN_F4R2_FB30 0x40000000U
2746 #define CAN_F4R2_FB31 0x80000000U
2748 /******************* Bit definition for CAN_F5R2 register *******************/
2749 #define CAN_F5R2_FB0 0x00000001U
2750 #define CAN_F5R2_FB1 0x00000002U
2751 #define CAN_F5R2_FB2 0x00000004U
2752 #define CAN_F5R2_FB3 0x00000008U
2753 #define CAN_F5R2_FB4 0x00000010U
2754 #define CAN_F5R2_FB5 0x00000020U
2755 #define CAN_F5R2_FB6 0x00000040U
2756 #define CAN_F5R2_FB7 0x00000080U
2757 #define CAN_F5R2_FB8 0x00000100U
2758 #define CAN_F5R2_FB9 0x00000200U
2759 #define CAN_F5R2_FB10 0x00000400U
2760 #define CAN_F5R2_FB11 0x00000800U
2761 #define CAN_F5R2_FB12 0x00001000U
2762 #define CAN_F5R2_FB13 0x00002000U
2763 #define CAN_F5R2_FB14 0x00004000U
2764 #define CAN_F5R2_FB15 0x00008000U
2765 #define CAN_F5R2_FB16 0x00010000U
2766 #define CAN_F5R2_FB17 0x00020000U
2767 #define CAN_F5R2_FB18 0x00040000U
2768 #define CAN_F5R2_FB19 0x00080000U
2769 #define CAN_F5R2_FB20 0x00100000U
2770 #define CAN_F5R2_FB21 0x00200000U
2771 #define CAN_F5R2_FB22 0x00400000U
2772 #define CAN_F5R2_FB23 0x00800000U
2773 #define CAN_F5R2_FB24 0x01000000U
2774 #define CAN_F5R2_FB25 0x02000000U
2775 #define CAN_F5R2_FB26 0x04000000U
2776 #define CAN_F5R2_FB27 0x08000000U
2777 #define CAN_F5R2_FB28 0x10000000U
2778 #define CAN_F5R2_FB29 0x20000000U
2779 #define CAN_F5R2_FB30 0x40000000U
2780 #define CAN_F5R2_FB31 0x80000000U
2782 /******************* Bit definition for CAN_F6R2 register *******************/
2783 #define CAN_F6R2_FB0 0x00000001U
2784 #define CAN_F6R2_FB1 0x00000002U
2785 #define CAN_F6R2_FB2 0x00000004U
2786 #define CAN_F6R2_FB3 0x00000008U
2787 #define CAN_F6R2_FB4 0x00000010U
2788 #define CAN_F6R2_FB5 0x00000020U
2789 #define CAN_F6R2_FB6 0x00000040U
2790 #define CAN_F6R2_FB7 0x00000080U
2791 #define CAN_F6R2_FB8 0x00000100U
2792 #define CAN_F6R2_FB9 0x00000200U
2793 #define CAN_F6R2_FB10 0x00000400U
2794 #define CAN_F6R2_FB11 0x00000800U
2795 #define CAN_F6R2_FB12 0x00001000U
2796 #define CAN_F6R2_FB13 0x00002000U
2797 #define CAN_F6R2_FB14 0x00004000U
2798 #define CAN_F6R2_FB15 0x00008000U
2799 #define CAN_F6R2_FB16 0x00010000U
2800 #define CAN_F6R2_FB17 0x00020000U
2801 #define CAN_F6R2_FB18 0x00040000U
2802 #define CAN_F6R2_FB19 0x00080000U
2803 #define CAN_F6R2_FB20 0x00100000U
2804 #define CAN_F6R2_FB21 0x00200000U
2805 #define CAN_F6R2_FB22 0x00400000U
2806 #define CAN_F6R2_FB23 0x00800000U
2807 #define CAN_F6R2_FB24 0x01000000U
2808 #define CAN_F6R2_FB25 0x02000000U
2809 #define CAN_F6R2_FB26 0x04000000U
2810 #define CAN_F6R2_FB27 0x08000000U
2811 #define CAN_F6R2_FB28 0x10000000U
2812 #define CAN_F6R2_FB29 0x20000000U
2813 #define CAN_F6R2_FB30 0x40000000U
2814 #define CAN_F6R2_FB31 0x80000000U
2816 /******************* Bit definition for CAN_F7R2 register *******************/
2817 #define CAN_F7R2_FB0 0x00000001U
2818 #define CAN_F7R2_FB1 0x00000002U
2819 #define CAN_F7R2_FB2 0x00000004U
2820 #define CAN_F7R2_FB3 0x00000008U
2821 #define CAN_F7R2_FB4 0x00000010U
2822 #define CAN_F7R2_FB5 0x00000020U
2823 #define CAN_F7R2_FB6 0x00000040U
2824 #define CAN_F7R2_FB7 0x00000080U
2825 #define CAN_F7R2_FB8 0x00000100U
2826 #define CAN_F7R2_FB9 0x00000200U
2827 #define CAN_F7R2_FB10 0x00000400U
2828 #define CAN_F7R2_FB11 0x00000800U
2829 #define CAN_F7R2_FB12 0x00001000U
2830 #define CAN_F7R2_FB13 0x00002000U
2831 #define CAN_F7R2_FB14 0x00004000U
2832 #define CAN_F7R2_FB15 0x00008000U
2833 #define CAN_F7R2_FB16 0x00010000U
2834 #define CAN_F7R2_FB17 0x00020000U
2835 #define CAN_F7R2_FB18 0x00040000U
2836 #define CAN_F7R2_FB19 0x00080000U
2837 #define CAN_F7R2_FB20 0x00100000U
2838 #define CAN_F7R2_FB21 0x00200000U
2839 #define CAN_F7R2_FB22 0x00400000U
2840 #define CAN_F7R2_FB23 0x00800000U
2841 #define CAN_F7R2_FB24 0x01000000U
2842 #define CAN_F7R2_FB25 0x02000000U
2843 #define CAN_F7R2_FB26 0x04000000U
2844 #define CAN_F7R2_FB27 0x08000000U
2845 #define CAN_F7R2_FB28 0x10000000U
2846 #define CAN_F7R2_FB29 0x20000000U
2847 #define CAN_F7R2_FB30 0x40000000U
2848 #define CAN_F7R2_FB31 0x80000000U
2850 /******************* Bit definition for CAN_F8R2 register *******************/
2851 #define CAN_F8R2_FB0 0x00000001U
2852 #define CAN_F8R2_FB1 0x00000002U
2853 #define CAN_F8R2_FB2 0x00000004U
2854 #define CAN_F8R2_FB3 0x00000008U
2855 #define CAN_F8R2_FB4 0x00000010U
2856 #define CAN_F8R2_FB5 0x00000020U
2857 #define CAN_F8R2_FB6 0x00000040U
2858 #define CAN_F8R2_FB7 0x00000080U
2859 #define CAN_F8R2_FB8 0x00000100U
2860 #define CAN_F8R2_FB9 0x00000200U
2861 #define CAN_F8R2_FB10 0x00000400U
2862 #define CAN_F8R2_FB11 0x00000800U
2863 #define CAN_F8R2_FB12 0x00001000U
2864 #define CAN_F8R2_FB13 0x00002000U
2865 #define CAN_F8R2_FB14 0x00004000U
2866 #define CAN_F8R2_FB15 0x00008000U
2867 #define CAN_F8R2_FB16 0x00010000U
2868 #define CAN_F8R2_FB17 0x00020000U
2869 #define CAN_F8R2_FB18 0x00040000U
2870 #define CAN_F8R2_FB19 0x00080000U
2871 #define CAN_F8R2_FB20 0x00100000U
2872 #define CAN_F8R2_FB21 0x00200000U
2873 #define CAN_F8R2_FB22 0x00400000U
2874 #define CAN_F8R2_FB23 0x00800000U
2875 #define CAN_F8R2_FB24 0x01000000U
2876 #define CAN_F8R2_FB25 0x02000000U
2877 #define CAN_F8R2_FB26 0x04000000U
2878 #define CAN_F8R2_FB27 0x08000000U
2879 #define CAN_F8R2_FB28 0x10000000U
2880 #define CAN_F8R2_FB29 0x20000000U
2881 #define CAN_F8R2_FB30 0x40000000U
2882 #define CAN_F8R2_FB31 0x80000000U
2884 /******************* Bit definition for CAN_F9R2 register *******************/
2885 #define CAN_F9R2_FB0 0x00000001U
2886 #define CAN_F9R2_FB1 0x00000002U
2887 #define CAN_F9R2_FB2 0x00000004U
2888 #define CAN_F9R2_FB3 0x00000008U
2889 #define CAN_F9R2_FB4 0x00000010U
2890 #define CAN_F9R2_FB5 0x00000020U
2891 #define CAN_F9R2_FB6 0x00000040U
2892 #define CAN_F9R2_FB7 0x00000080U
2893 #define CAN_F9R2_FB8 0x00000100U
2894 #define CAN_F9R2_FB9 0x00000200U
2895 #define CAN_F9R2_FB10 0x00000400U
2896 #define CAN_F9R2_FB11 0x00000800U
2897 #define CAN_F9R2_FB12 0x00001000U
2898 #define CAN_F9R2_FB13 0x00002000U
2899 #define CAN_F9R2_FB14 0x00004000U
2900 #define CAN_F9R2_FB15 0x00008000U
2901 #define CAN_F9R2_FB16 0x00010000U
2902 #define CAN_F9R2_FB17 0x00020000U
2903 #define CAN_F9R2_FB18 0x00040000U
2904 #define CAN_F9R2_FB19 0x00080000U
2905 #define CAN_F9R2_FB20 0x00100000U
2906 #define CAN_F9R2_FB21 0x00200000U
2907 #define CAN_F9R2_FB22 0x00400000U
2908 #define CAN_F9R2_FB23 0x00800000U
2909 #define CAN_F9R2_FB24 0x01000000U
2910 #define CAN_F9R2_FB25 0x02000000U
2911 #define CAN_F9R2_FB26 0x04000000U
2912 #define CAN_F9R2_FB27 0x08000000U
2913 #define CAN_F9R2_FB28 0x10000000U
2914 #define CAN_F9R2_FB29 0x20000000U
2915 #define CAN_F9R2_FB30 0x40000000U
2916 #define CAN_F9R2_FB31 0x80000000U
2918 /******************* Bit definition for CAN_F10R2 register ******************/
2919 #define CAN_F10R2_FB0 0x00000001U
2920 #define CAN_F10R2_FB1 0x00000002U
2921 #define CAN_F10R2_FB2 0x00000004U
2922 #define CAN_F10R2_FB3 0x00000008U
2923 #define CAN_F10R2_FB4 0x00000010U
2924 #define CAN_F10R2_FB5 0x00000020U
2925 #define CAN_F10R2_FB6 0x00000040U
2926 #define CAN_F10R2_FB7 0x00000080U
2927 #define CAN_F10R2_FB8 0x00000100U
2928 #define CAN_F10R2_FB9 0x00000200U
2929 #define CAN_F10R2_FB10 0x00000400U
2930 #define CAN_F10R2_FB11 0x00000800U
2931 #define CAN_F10R2_FB12 0x00001000U
2932 #define CAN_F10R2_FB13 0x00002000U
2933 #define CAN_F10R2_FB14 0x00004000U
2934 #define CAN_F10R2_FB15 0x00008000U
2935 #define CAN_F10R2_FB16 0x00010000U
2936 #define CAN_F10R2_FB17 0x00020000U
2937 #define CAN_F10R2_FB18 0x00040000U
2938 #define CAN_F10R2_FB19 0x00080000U
2939 #define CAN_F10R2_FB20 0x00100000U
2940 #define CAN_F10R2_FB21 0x00200000U
2941 #define CAN_F10R2_FB22 0x00400000U
2942 #define CAN_F10R2_FB23 0x00800000U
2943 #define CAN_F10R2_FB24 0x01000000U
2944 #define CAN_F10R2_FB25 0x02000000U
2945 #define CAN_F10R2_FB26 0x04000000U
2946 #define CAN_F10R2_FB27 0x08000000U
2947 #define CAN_F10R2_FB28 0x10000000U
2948 #define CAN_F10R2_FB29 0x20000000U
2949 #define CAN_F10R2_FB30 0x40000000U
2950 #define CAN_F10R2_FB31 0x80000000U
2952 /******************* Bit definition for CAN_F11R2 register ******************/
2953 #define CAN_F11R2_FB0 0x00000001U
2954 #define CAN_F11R2_FB1 0x00000002U
2955 #define CAN_F11R2_FB2 0x00000004U
2956 #define CAN_F11R2_FB3 0x00000008U
2957 #define CAN_F11R2_FB4 0x00000010U
2958 #define CAN_F11R2_FB5 0x00000020U
2959 #define CAN_F11R2_FB6 0x00000040U
2960 #define CAN_F11R2_FB7 0x00000080U
2961 #define CAN_F11R2_FB8 0x00000100U
2962 #define CAN_F11R2_FB9 0x00000200U
2963 #define CAN_F11R2_FB10 0x00000400U
2964 #define CAN_F11R2_FB11 0x00000800U
2965 #define CAN_F11R2_FB12 0x00001000U
2966 #define CAN_F11R2_FB13 0x00002000U
2967 #define CAN_F11R2_FB14 0x00004000U
2968 #define CAN_F11R2_FB15 0x00008000U
2969 #define CAN_F11R2_FB16 0x00010000U
2970 #define CAN_F11R2_FB17 0x00020000U
2971 #define CAN_F11R2_FB18 0x00040000U
2972 #define CAN_F11R2_FB19 0x00080000U
2973 #define CAN_F11R2_FB20 0x00100000U
2974 #define CAN_F11R2_FB21 0x00200000U
2975 #define CAN_F11R2_FB22 0x00400000U
2976 #define CAN_F11R2_FB23 0x00800000U
2977 #define CAN_F11R2_FB24 0x01000000U
2978 #define CAN_F11R2_FB25 0x02000000U
2979 #define CAN_F11R2_FB26 0x04000000U
2980 #define CAN_F11R2_FB27 0x08000000U
2981 #define CAN_F11R2_FB28 0x10000000U
2982 #define CAN_F11R2_FB29 0x20000000U
2983 #define CAN_F11R2_FB30 0x40000000U
2984 #define CAN_F11R2_FB31 0x80000000U
2986 /******************* Bit definition for CAN_F12R2 register ******************/
2987 #define CAN_F12R2_FB0 0x00000001U
2988 #define CAN_F12R2_FB1 0x00000002U
2989 #define CAN_F12R2_FB2 0x00000004U
2990 #define CAN_F12R2_FB3 0x00000008U
2991 #define CAN_F12R2_FB4 0x00000010U
2992 #define CAN_F12R2_FB5 0x00000020U
2993 #define CAN_F12R2_FB6 0x00000040U
2994 #define CAN_F12R2_FB7 0x00000080U
2995 #define CAN_F12R2_FB8 0x00000100U
2996 #define CAN_F12R2_FB9 0x00000200U
2997 #define CAN_F12R2_FB10 0x00000400U
2998 #define CAN_F12R2_FB11 0x00000800U
2999 #define CAN_F12R2_FB12 0x00001000U
3000 #define CAN_F12R2_FB13 0x00002000U
3001 #define CAN_F12R2_FB14 0x00004000U
3002 #define CAN_F12R2_FB15 0x00008000U
3003 #define CAN_F12R2_FB16 0x00010000U
3004 #define CAN_F12R2_FB17 0x00020000U
3005 #define CAN_F12R2_FB18 0x00040000U
3006 #define CAN_F12R2_FB19 0x00080000U
3007 #define CAN_F12R2_FB20 0x00100000U
3008 #define CAN_F12R2_FB21 0x00200000U
3009 #define CAN_F12R2_FB22 0x00400000U
3010 #define CAN_F12R2_FB23 0x00800000U
3011 #define CAN_F12R2_FB24 0x01000000U
3012 #define CAN_F12R2_FB25 0x02000000U
3013 #define CAN_F12R2_FB26 0x04000000U
3014 #define CAN_F12R2_FB27 0x08000000U
3015 #define CAN_F12R2_FB28 0x10000000U
3016 #define CAN_F12R2_FB29 0x20000000U
3017 #define CAN_F12R2_FB30 0x40000000U
3018 #define CAN_F12R2_FB31 0x80000000U
3020 /******************* Bit definition for CAN_F13R2 register ******************/
3021 #define CAN_F13R2_FB0 0x00000001U
3022 #define CAN_F13R2_FB1 0x00000002U
3023 #define CAN_F13R2_FB2 0x00000004U
3024 #define CAN_F13R2_FB3 0x00000008U
3025 #define CAN_F13R2_FB4 0x00000010U
3026 #define CAN_F13R2_FB5 0x00000020U
3027 #define CAN_F13R2_FB6 0x00000040U
3028 #define CAN_F13R2_FB7 0x00000080U
3029 #define CAN_F13R2_FB8 0x00000100U
3030 #define CAN_F13R2_FB9 0x00000200U
3031 #define CAN_F13R2_FB10 0x00000400U
3032 #define CAN_F13R2_FB11 0x00000800U
3033 #define CAN_F13R2_FB12 0x00001000U
3034 #define CAN_F13R2_FB13 0x00002000U
3035 #define CAN_F13R2_FB14 0x00004000U
3036 #define CAN_F13R2_FB15 0x00008000U
3037 #define CAN_F13R2_FB16 0x00010000U
3038 #define CAN_F13R2_FB17 0x00020000U
3039 #define CAN_F13R2_FB18 0x00040000U
3040 #define CAN_F13R2_FB19 0x00080000U
3041 #define CAN_F13R2_FB20 0x00100000U
3042 #define CAN_F13R2_FB21 0x00200000U
3043 #define CAN_F13R2_FB22 0x00400000U
3044 #define CAN_F13R2_FB23 0x00800000U
3045 #define CAN_F13R2_FB24 0x01000000U
3046 #define CAN_F13R2_FB25 0x02000000U
3047 #define CAN_F13R2_FB26 0x04000000U
3048 #define CAN_F13R2_FB27 0x08000000U
3049 #define CAN_F13R2_FB28 0x10000000U
3050 #define CAN_F13R2_FB29 0x20000000U
3051 #define CAN_F13R2_FB30 0x40000000U
3052 #define CAN_F13R2_FB31 0x80000000U
3054 /******************************************************************************/
3055 /* */
3056 /* HDMI-CEC (CEC) */
3057 /* */
3058 /******************************************************************************/
3059 
3060 /******************* Bit definition for CEC_CR register *********************/
3061 #define CEC_CR_CECEN 0x00000001U
3062 #define CEC_CR_TXSOM 0x00000002U
3063 #define CEC_CR_TXEOM 0x00000004U
3065 /******************* Bit definition for CEC_CFGR register *******************/
3066 #define CEC_CFGR_SFT 0x00000007U
3067 #define CEC_CFGR_RXTOL 0x00000008U
3068 #define CEC_CFGR_BRESTP 0x00000010U
3069 #define CEC_CFGR_BREGEN 0x00000020U
3070 #define CEC_CFGR_LBPEGEN 0x00000040U
3071 #define CEC_CFGR_BRDNOGEN 0x00000080U
3072 #define CEC_CFGR_SFTOPT 0x00000100U
3073 #define CEC_CFGR_OAR 0x7FFF0000U
3074 #define CEC_CFGR_LSTN 0x80000000U
3076 /******************* Bit definition for CEC_TXDR register *******************/
3077 #define CEC_TXDR_TXD 0x000000FFU
3079 /******************* Bit definition for CEC_RXDR register *******************/
3080 #define CEC_TXDR_RXD 0x000000FFU
3082 /******************* Bit definition for CEC_ISR register ********************/
3083 #define CEC_ISR_RXBR 0x00000001U
3084 #define CEC_ISR_RXEND 0x00000002U
3085 #define CEC_ISR_RXOVR 0x00000004U
3086 #define CEC_ISR_BRE 0x00000008U
3087 #define CEC_ISR_SBPE 0x00000010U
3088 #define CEC_ISR_LBPE 0x00000020U
3089 #define CEC_ISR_RXACKE 0x00000040U
3090 #define CEC_ISR_ARBLST 0x00000080U
3091 #define CEC_ISR_TXBR 0x00000100U
3092 #define CEC_ISR_TXEND 0x00000200U
3093 #define CEC_ISR_TXUDR 0x00000400U
3094 #define CEC_ISR_TXERR 0x00000800U
3095 #define CEC_ISR_TXACKE 0x00001000U
3097 /******************* Bit definition for CEC_IER register ********************/
3098 #define CEC_IER_RXBRIE 0x00000001U
3099 #define CEC_IER_RXENDIE 0x00000002U
3100 #define CEC_IER_RXOVRIE 0x00000004U
3101 #define CEC_IER_BREIE 0x00000008U
3102 #define CEC_IER_SBPEIE 0x00000010U
3103 #define CEC_IER_LBPEIE 0x00000020U
3104 #define CEC_IER_RXACKEIE 0x00000040U
3105 #define CEC_IER_ARBLSTIE 0x00000080U
3106 #define CEC_IER_TXBRIE 0x00000100U
3107 #define CEC_IER_TXENDIE 0x00000200U
3108 #define CEC_IER_TXUDRIE 0x00000400U
3109 #define CEC_IER_TXERRIE 0x00000800U
3110 #define CEC_IER_TXACKEIE 0x00001000U
3112 /******************************************************************************/
3113 /* */
3114 /* CRC calculation unit */
3115 /* */
3116 /******************************************************************************/
3117 /******************* Bit definition for CRC_DR register *********************/
3118 #define CRC_DR_DR 0xFFFFFFFFU
3120 /******************* Bit definition for CRC_IDR register ********************/
3121 #define CRC_IDR_IDR 0x000000FFU
3123 /******************** Bit definition for CRC_CR register ********************/
3124 #define CRC_CR_RESET 0x00000001U
3125 #define CRC_CR_POLYSIZE 0x00000018U
3126 #define CRC_CR_POLYSIZE_0 0x00000008U
3127 #define CRC_CR_POLYSIZE_1 0x00000010U
3128 #define CRC_CR_REV_IN 0x00000060U
3129 #define CRC_CR_REV_IN_0 0x00000020U
3130 #define CRC_CR_REV_IN_1 0x00000040U
3131 #define CRC_CR_REV_OUT 0x00000080U
3133 /******************* Bit definition for CRC_INIT register *******************/
3134 #define CRC_INIT_INIT 0xFFFFFFFFU
3136 /******************* Bit definition for CRC_POL register ********************/
3137 #define CRC_POL_POL 0xFFFFFFFFU
3140 /******************************************************************************/
3141 /* */
3142 /* Digital to Analog Converter */
3143 /* */
3144 /******************************************************************************/
3145 /******************** Bit definition for DAC_CR register ********************/
3146 #define DAC_CR_EN1 0x00000001U
3147 #define DAC_CR_BOFF1 0x00000002U
3148 #define DAC_CR_TEN1 0x00000004U
3149 #define DAC_CR_TSEL1 0x00000038U
3150 #define DAC_CR_TSEL1_0 0x00000008U
3151 #define DAC_CR_TSEL1_1 0x00000010U
3152 #define DAC_CR_TSEL1_2 0x00000020U
3153 #define DAC_CR_WAVE1 0x000000C0U
3154 #define DAC_CR_WAVE1_0 0x00000040U
3155 #define DAC_CR_WAVE1_1 0x00000080U
3156 #define DAC_CR_MAMP1 0x00000F00U
3157 #define DAC_CR_MAMP1_0 0x00000100U
3158 #define DAC_CR_MAMP1_1 0x00000200U
3159 #define DAC_CR_MAMP1_2 0x00000400U
3160 #define DAC_CR_MAMP1_3 0x00000800U
3161 #define DAC_CR_DMAEN1 0x00001000U
3162 #define DAC_CR_DMAUDRIE1 0x00002000U
3163 #define DAC_CR_EN2 0x00010000U
3164 #define DAC_CR_BOFF2 0x00020000U
3165 #define DAC_CR_TEN2 0x00040000U
3166 #define DAC_CR_TSEL2 0x00380000U
3167 #define DAC_CR_TSEL2_0 0x00080000U
3168 #define DAC_CR_TSEL2_1 0x00100000U
3169 #define DAC_CR_TSEL2_2 0x00200000U
3170 #define DAC_CR_WAVE2 0x00C00000U
3171 #define DAC_CR_WAVE2_0 0x00400000U
3172 #define DAC_CR_WAVE2_1 0x00800000U
3173 #define DAC_CR_MAMP2 0x0F000000U
3174 #define DAC_CR_MAMP2_0 0x01000000U
3175 #define DAC_CR_MAMP2_1 0x02000000U
3176 #define DAC_CR_MAMP2_2 0x04000000U
3177 #define DAC_CR_MAMP2_3 0x08000000U
3178 #define DAC_CR_DMAEN2 0x10000000U
3179 #define DAC_CR_DMAUDRIE2 0x20000000U
3181 /***************** Bit definition for DAC_SWTRIGR register ******************/
3182 #define DAC_SWTRIGR_SWTRIG1 0x01U
3183 #define DAC_SWTRIGR_SWTRIG2 0x02U
3185 /***************** Bit definition for DAC_DHR12R1 register ******************/
3186 #define DAC_DHR12R1_DACC1DHR 0x0FFFU
3188 /***************** Bit definition for DAC_DHR12L1 register ******************/
3189 #define DAC_DHR12L1_DACC1DHR 0xFFF0U
3191 /****************** Bit definition for DAC_DHR8R1 register ******************/
3192 #define DAC_DHR8R1_DACC1DHR 0xFFU
3194 /***************** Bit definition for DAC_DHR12R2 register ******************/
3195 #define DAC_DHR12R2_DACC2DHR 0x0FFFU
3197 /***************** Bit definition for DAC_DHR12L2 register ******************/
3198 #define DAC_DHR12L2_DACC2DHR 0xFFF0U
3200 /****************** Bit definition for DAC_DHR8R2 register ******************/
3201 #define DAC_DHR8R2_DACC2DHR 0xFFU
3203 /***************** Bit definition for DAC_DHR12RD register ******************/
3204 #define DAC_DHR12RD_DACC1DHR 0x00000FFFU
3205 #define DAC_DHR12RD_DACC2DHR 0x0FFF0000U
3207 /***************** Bit definition for DAC_DHR12LD register ******************/
3208 #define DAC_DHR12LD_DACC1DHR 0x0000FFF0U
3209 #define DAC_DHR12LD_DACC2DHR 0xFFF00000U
3211 /****************** Bit definition for DAC_DHR8RD register ******************/
3212 #define DAC_DHR8RD_DACC1DHR 0x00FFU
3213 #define DAC_DHR8RD_DACC2DHR 0xFF00U
3215 /******************* Bit definition for DAC_DOR1 register *******************/
3216 #define DAC_DOR1_DACC1DOR 0x0FFFU
3218 /******************* Bit definition for DAC_DOR2 register *******************/
3219 #define DAC_DOR2_DACC2DOR 0x0FFFU
3221 /******************** Bit definition for DAC_SR register ********************/
3222 #define DAC_SR_DMAUDR1 0x00002000U
3223 #define DAC_SR_DMAUDR2 0x20000000U
3226 /******************************************************************************/
3227 /* */
3228 /* Debug MCU */
3229 /* */
3230 /******************************************************************************/
3231 
3232 /******************************************************************************/
3233 /* */
3234 /* DCMI */
3235 /* */
3236 /******************************************************************************/
3237 /******************** Bits definition for DCMI_CR register ******************/
3238 #define DCMI_CR_CAPTURE 0x00000001U
3239 #define DCMI_CR_CM 0x00000002U
3240 #define DCMI_CR_CROP 0x00000004U
3241 #define DCMI_CR_JPEG 0x00000008U
3242 #define DCMI_CR_ESS 0x00000010U
3243 #define DCMI_CR_PCKPOL 0x00000020U
3244 #define DCMI_CR_HSPOL 0x00000040U
3245 #define DCMI_CR_VSPOL 0x00000080U
3246 #define DCMI_CR_FCRC_0 0x00000100U
3247 #define DCMI_CR_FCRC_1 0x00000200U
3248 #define DCMI_CR_EDM_0 0x00000400U
3249 #define DCMI_CR_EDM_1 0x00000800U
3250 #define DCMI_CR_CRE 0x00001000U
3251 #define DCMI_CR_ENABLE 0x00004000U
3252 #define DCMI_CR_BSM 0x00030000U
3253 #define DCMI_CR_BSM_0 0x00010000U
3254 #define DCMI_CR_BSM_1 0x00020000U
3255 #define DCMI_CR_OEBS 0x00040000U
3256 #define DCMI_CR_LSM 0x00080000U
3257 #define DCMI_CR_OELS 0x00100000U
3258 
3259 /******************** Bits definition for DCMI_SR register ******************/
3260 #define DCMI_SR_HSYNC 0x00000001U
3261 #define DCMI_SR_VSYNC 0x00000002U
3262 #define DCMI_SR_FNE 0x00000004U
3263 
3264 /******************** Bits definition for DCMI_RIS register ****************/
3265 #define DCMI_RIS_FRAME_RIS 0x00000001U
3266 #define DCMI_RIS_OVR_RIS 0x00000002U
3267 #define DCMI_RIS_ERR_RIS 0x00000004U
3268 #define DCMI_RIS_VSYNC_RIS 0x00000008U
3269 #define DCMI_RIS_LINE_RIS 0x00000010U
3270 
3271 /* Legacy defines */
3272 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
3273 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
3274 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
3275 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
3276 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
3277 
3278 /******************** Bits definition for DCMI_IER register *****************/
3279 #define DCMI_IER_FRAME_IE 0x00000001U
3280 #define DCMI_IER_OVR_IE 0x00000002U
3281 #define DCMI_IER_ERR_IE 0x00000004U
3282 #define DCMI_IER_VSYNC_IE 0x00000008U
3283 #define DCMI_IER_LINE_IE 0x00000010U
3284 
3285 /* Legacy define */
3286 #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
3287 
3288 /******************** Bits definition for DCMI_MIS register *****************/
3289 #define DCMI_MIS_FRAME_MIS 0x00000001U
3290 #define DCMI_MIS_OVR_MIS 0x00000002U
3291 #define DCMI_MIS_ERR_MIS 0x00000004U
3292 #define DCMI_MIS_VSYNC_MIS 0x00000008U
3293 #define DCMI_MIS_LINE_MIS 0x00000010U
3294 
3295 /* Legacy defines */
3296 #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
3297 #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
3298 #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
3299 #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
3300 #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
3301 
3302 /******************** Bits definition for DCMI_ICR register *****************/
3303 #define DCMI_ICR_FRAME_ISC 0x00000001U
3304 #define DCMI_ICR_OVR_ISC 0x00000002U
3305 #define DCMI_ICR_ERR_ISC 0x00000004U
3306 #define DCMI_ICR_VSYNC_ISC 0x00000008U
3307 #define DCMI_ICR_LINE_ISC 0x00000010U
3308 
3309 /* Legacy defines */
3310 #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
3311 
3312 /******************** Bits definition for DCMI_ESCR register ******************/
3313 #define DCMI_ESCR_FSC 0x000000FFU
3314 #define DCMI_ESCR_LSC 0x0000FF00U
3315 #define DCMI_ESCR_LEC 0x00FF0000U
3316 #define DCMI_ESCR_FEC 0xFF000000U
3317 
3318 /******************** Bits definition for DCMI_ESUR register ******************/
3319 #define DCMI_ESUR_FSU 0x000000FFU
3320 #define DCMI_ESUR_LSU 0x0000FF00U
3321 #define DCMI_ESUR_LEU 0x00FF0000U
3322 #define DCMI_ESUR_FEU 0xFF000000U
3323 
3324 /******************** Bits definition for DCMI_CWSTRT register ******************/
3325 #define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
3326 #define DCMI_CWSTRT_VST 0x1FFF0000U
3327 
3328 /******************** Bits definition for DCMI_CWSIZE register ******************/
3329 #define DCMI_CWSIZE_CAPCNT 0x00003FFFU
3330 #define DCMI_CWSIZE_VLINE 0x3FFF0000U
3331 
3332 /******************** Bits definition for DCMI_DR register ******************/
3333 #define DCMI_DR_BYTE0 0x000000FFU
3334 #define DCMI_DR_BYTE1 0x0000FF00U
3335 #define DCMI_DR_BYTE2 0x00FF0000U
3336 #define DCMI_DR_BYTE3 0xFF000000U
3337 
3338 /******************************************************************************/
3339 /* */
3340 /* DMA Controller */
3341 /* */
3342 /******************************************************************************/
3343 /******************** Bits definition for DMA_SxCR register *****************/
3344 #define DMA_SxCR_CHSEL 0x0E000000U
3345 #define DMA_SxCR_CHSEL_0 0x02000000U
3346 #define DMA_SxCR_CHSEL_1 0x04000000U
3347 #define DMA_SxCR_CHSEL_2 0x08000000U
3348 #define DMA_SxCR_MBURST 0x01800000U
3349 #define DMA_SxCR_MBURST_0 0x00800000U
3350 #define DMA_SxCR_MBURST_1 0x01000000U
3351 #define DMA_SxCR_PBURST 0x00600000U
3352 #define DMA_SxCR_PBURST_0 0x00200000U
3353 #define DMA_SxCR_PBURST_1 0x00400000U
3354 #define DMA_SxCR_CT 0x00080000U
3355 #define DMA_SxCR_DBM 0x00040000U
3356 #define DMA_SxCR_PL 0x00030000U
3357 #define DMA_SxCR_PL_0 0x00010000U
3358 #define DMA_SxCR_PL_1 0x00020000U
3359 #define DMA_SxCR_PINCOS 0x00008000U
3360 #define DMA_SxCR_MSIZE 0x00006000U
3361 #define DMA_SxCR_MSIZE_0 0x00002000U
3362 #define DMA_SxCR_MSIZE_1 0x00004000U
3363 #define DMA_SxCR_PSIZE 0x00001800U
3364 #define DMA_SxCR_PSIZE_0 0x00000800U
3365 #define DMA_SxCR_PSIZE_1 0x00001000U
3366 #define DMA_SxCR_MINC 0x00000400U
3367 #define DMA_SxCR_PINC 0x00000200U
3368 #define DMA_SxCR_CIRC 0x00000100U
3369 #define DMA_SxCR_DIR 0x000000C0U
3370 #define DMA_SxCR_DIR_0 0x00000040U
3371 #define DMA_SxCR_DIR_1 0x00000080U
3372 #define DMA_SxCR_PFCTRL 0x00000020U
3373 #define DMA_SxCR_TCIE 0x00000010U
3374 #define DMA_SxCR_HTIE 0x00000008U
3375 #define DMA_SxCR_TEIE 0x00000004U
3376 #define DMA_SxCR_DMEIE 0x00000002U
3377 #define DMA_SxCR_EN 0x00000001U
3378 
3379 /******************** Bits definition for DMA_SxCNDTR register **************/
3380 #define DMA_SxNDT 0x0000FFFFU
3381 #define DMA_SxNDT_0 0x00000001U
3382 #define DMA_SxNDT_1 0x00000002U
3383 #define DMA_SxNDT_2 0x00000004U
3384 #define DMA_SxNDT_3 0x00000008U
3385 #define DMA_SxNDT_4 0x00000010U
3386 #define DMA_SxNDT_5 0x00000020U
3387 #define DMA_SxNDT_6 0x00000040U
3388 #define DMA_SxNDT_7 0x00000080U
3389 #define DMA_SxNDT_8 0x00000100U
3390 #define DMA_SxNDT_9 0x00000200U
3391 #define DMA_SxNDT_10 0x00000400U
3392 #define DMA_SxNDT_11 0x00000800U
3393 #define DMA_SxNDT_12 0x00001000U
3394 #define DMA_SxNDT_13 0x00002000U
3395 #define DMA_SxNDT_14 0x00004000U
3396 #define DMA_SxNDT_15 0x00008000U
3397 
3398 /******************** Bits definition for DMA_SxFCR register ****************/
3399 #define DMA_SxFCR_FEIE 0x00000080U
3400 #define DMA_SxFCR_FS 0x00000038U
3401 #define DMA_SxFCR_FS_0 0x00000008U
3402 #define DMA_SxFCR_FS_1 0x00000010U
3403 #define DMA_SxFCR_FS_2 0x00000020U
3404 #define DMA_SxFCR_DMDIS 0x00000004U
3405 #define DMA_SxFCR_FTH 0x00000003U
3406 #define DMA_SxFCR_FTH_0 0x00000001U
3407 #define DMA_SxFCR_FTH_1 0x00000002U
3408 
3409 /******************** Bits definition for DMA_LISR register *****************/
3410 #define DMA_LISR_TCIF3 0x08000000U
3411 #define DMA_LISR_HTIF3 0x04000000U
3412 #define DMA_LISR_TEIF3 0x02000000U
3413 #define DMA_LISR_DMEIF3 0x01000000U
3414 #define DMA_LISR_FEIF3 0x00400000U
3415 #define DMA_LISR_TCIF2 0x00200000U
3416 #define DMA_LISR_HTIF2 0x00100000U
3417 #define DMA_LISR_TEIF2 0x00080000U
3418 #define DMA_LISR_DMEIF2 0x00040000U
3419 #define DMA_LISR_FEIF2 0x00010000U
3420 #define DMA_LISR_TCIF1 0x00000800U
3421 #define DMA_LISR_HTIF1 0x00000400U
3422 #define DMA_LISR_TEIF1 0x00000200U
3423 #define DMA_LISR_DMEIF1 0x00000100U
3424 #define DMA_LISR_FEIF1 0x00000040U
3425 #define DMA_LISR_TCIF0 0x00000020U
3426 #define DMA_LISR_HTIF0 0x00000010U
3427 #define DMA_LISR_TEIF0 0x00000008U
3428 #define DMA_LISR_DMEIF0 0x00000004U
3429 #define DMA_LISR_FEIF0 0x00000001U
3430 
3431 /******************** Bits definition for DMA_HISR register *****************/
3432 #define DMA_HISR_TCIF7 0x08000000U
3433 #define DMA_HISR_HTIF7 0x04000000U
3434 #define DMA_HISR_TEIF7 0x02000000U
3435 #define DMA_HISR_DMEIF7 0x01000000U
3436 #define DMA_HISR_FEIF7 0x00400000U
3437 #define DMA_HISR_TCIF6 0x00200000U
3438 #define DMA_HISR_HTIF6 0x00100000U
3439 #define DMA_HISR_TEIF6 0x00080000U
3440 #define DMA_HISR_DMEIF6 0x00040000U
3441 #define DMA_HISR_FEIF6 0x00010000U
3442 #define DMA_HISR_TCIF5 0x00000800U
3443 #define DMA_HISR_HTIF5 0x00000400U
3444 #define DMA_HISR_TEIF5 0x00000200U
3445 #define DMA_HISR_DMEIF5 0x00000100U
3446 #define DMA_HISR_FEIF5 0x00000040U
3447 #define DMA_HISR_TCIF4 0x00000020U
3448 #define DMA_HISR_HTIF4 0x00000010U
3449 #define DMA_HISR_TEIF4 0x00000008U
3450 #define DMA_HISR_DMEIF4 0x00000004U
3451 #define DMA_HISR_FEIF4 0x00000001U
3452 
3453 /******************** Bits definition for DMA_LIFCR register ****************/
3454 #define DMA_LIFCR_CTCIF3 0x08000000U
3455 #define DMA_LIFCR_CHTIF3 0x04000000U
3456 #define DMA_LIFCR_CTEIF3 0x02000000U
3457 #define DMA_LIFCR_CDMEIF3 0x01000000U
3458 #define DMA_LIFCR_CFEIF3 0x00400000U
3459 #define DMA_LIFCR_CTCIF2 0x00200000U
3460 #define DMA_LIFCR_CHTIF2 0x00100000U
3461 #define DMA_LIFCR_CTEIF2 0x00080000U
3462 #define DMA_LIFCR_CDMEIF2 0x00040000U
3463 #define DMA_LIFCR_CFEIF2 0x00010000U
3464 #define DMA_LIFCR_CTCIF1 0x00000800U
3465 #define DMA_LIFCR_CHTIF1 0x00000400U
3466 #define DMA_LIFCR_CTEIF1 0x00000200U
3467 #define DMA_LIFCR_CDMEIF1 0x00000100U
3468 #define DMA_LIFCR_CFEIF1 0x00000040U
3469 #define DMA_LIFCR_CTCIF0 0x00000020U
3470 #define DMA_LIFCR_CHTIF0 0x00000010U
3471 #define DMA_LIFCR_CTEIF0 0x00000008U
3472 #define DMA_LIFCR_CDMEIF0 0x00000004U
3473 #define DMA_LIFCR_CFEIF0 0x00000001U
3474 
3475 /******************** Bits definition for DMA_HIFCR register ****************/
3476 #define DMA_HIFCR_CTCIF7 0x08000000U
3477 #define DMA_HIFCR_CHTIF7 0x04000000U
3478 #define DMA_HIFCR_CTEIF7 0x02000000U
3479 #define DMA_HIFCR_CDMEIF7 0x01000000U
3480 #define DMA_HIFCR_CFEIF7 0x00400000U
3481 #define DMA_HIFCR_CTCIF6 0x00200000U
3482 #define DMA_HIFCR_CHTIF6 0x00100000U
3483 #define DMA_HIFCR_CTEIF6 0x00080000U
3484 #define DMA_HIFCR_CDMEIF6 0x00040000U
3485 #define DMA_HIFCR_CFEIF6 0x00010000U
3486 #define DMA_HIFCR_CTCIF5 0x00000800U
3487 #define DMA_HIFCR_CHTIF5 0x00000400U
3488 #define DMA_HIFCR_CTEIF5 0x00000200U
3489 #define DMA_HIFCR_CDMEIF5 0x00000100U
3490 #define DMA_HIFCR_CFEIF5 0x00000040U
3491 #define DMA_HIFCR_CTCIF4 0x00000020U
3492 #define DMA_HIFCR_CHTIF4 0x00000010U
3493 #define DMA_HIFCR_CTEIF4 0x00000008U
3494 #define DMA_HIFCR_CDMEIF4 0x00000004U
3495 #define DMA_HIFCR_CFEIF4 0x00000001U
3496 
3497 /******************************************************************************/
3498 /* */
3499 /* AHB Master DMA2D Controller (DMA2D) */
3500 /* */
3501 /******************************************************************************/
3502 
3503 /******************** Bit definition for DMA2D_CR register ******************/
3504 
3505 #define DMA2D_CR_START 0x00000001U
3506 #define DMA2D_CR_SUSP 0x00000002U
3507 #define DMA2D_CR_ABORT 0x00000004U
3508 #define DMA2D_CR_TEIE 0x00000100U
3509 #define DMA2D_CR_TCIE 0x00000200U
3510 #define DMA2D_CR_TWIE 0x00000400U
3511 #define DMA2D_CR_CAEIE 0x00000800U
3512 #define DMA2D_CR_CTCIE 0x00001000U
3513 #define DMA2D_CR_CEIE 0x00002000U
3514 #define DMA2D_CR_MODE 0x00030000U
3515 #define DMA2D_CR_MODE_0 0x00010000U
3516 #define DMA2D_CR_MODE_1 0x00020000U
3518 /******************** Bit definition for DMA2D_ISR register *****************/
3519 
3520 #define DMA2D_ISR_TEIF 0x00000001U
3521 #define DMA2D_ISR_TCIF 0x00000002U
3522 #define DMA2D_ISR_TWIF 0x00000004U
3523 #define DMA2D_ISR_CAEIF 0x00000008U
3524 #define DMA2D_ISR_CTCIF 0x00000010U
3525 #define DMA2D_ISR_CEIF 0x00000020U
3527 /******************** Bit definition for DMA2D_IFCR register ****************/
3528 
3529 #define DMA2D_IFCR_CTEIF 0x00000001U
3530 #define DMA2D_IFCR_CTCIF 0x00000002U
3531 #define DMA2D_IFCR_CTWIF 0x00000004U
3532 #define DMA2D_IFCR_CAECIF 0x00000008U
3533 #define DMA2D_IFCR_CCTCIF 0x00000010U
3534 #define DMA2D_IFCR_CCEIF 0x00000020U
3536 /* Legacy defines */
3537 #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF
3538 #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF
3539 #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF
3540 #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF
3541 #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF
3542 #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF
3544 /******************** Bit definition for DMA2D_FGMAR register ***************/
3545 
3546 #define DMA2D_FGMAR_MA 0xFFFFFFFFU
3548 /******************** Bit definition for DMA2D_FGOR register ****************/
3549 
3550 #define DMA2D_FGOR_LO 0x00003FFFU
3552 /******************** Bit definition for DMA2D_BGMAR register ***************/
3553 
3554 #define DMA2D_BGMAR_MA 0xFFFFFFFFU
3556 /******************** Bit definition for DMA2D_BGOR register ****************/
3557 
3558 #define DMA2D_BGOR_LO 0x00003FFFU
3560 /******************** Bit definition for DMA2D_FGPFCCR register *************/
3561 
3562 #define DMA2D_FGPFCCR_CM 0x0000000FU
3563 #define DMA2D_FGPFCCR_CM_0 0x00000001U
3564 #define DMA2D_FGPFCCR_CM_1 0x00000002U
3565 #define DMA2D_FGPFCCR_CM_2 0x00000004U
3566 #define DMA2D_FGPFCCR_CM_3 0x00000008U
3567 #define DMA2D_FGPFCCR_CCM 0x00000010U
3568 #define DMA2D_FGPFCCR_START 0x00000020U
3569 #define DMA2D_FGPFCCR_CS 0x0000FF00U
3570 #define DMA2D_FGPFCCR_AM 0x00030000U
3571 #define DMA2D_FGPFCCR_AM_0 0x00010000U
3572 #define DMA2D_FGPFCCR_AM_1 0x00020000U
3573 #define DMA2D_FGPFCCR_ALPHA 0xFF000000U
3575 /******************** Bit definition for DMA2D_FGCOLR register **************/
3576 
3577 #define DMA2D_FGCOLR_BLUE 0x000000FFU
3578 #define DMA2D_FGCOLR_GREEN 0x0000FF00U
3579 #define DMA2D_FGCOLR_RED 0x00FF0000U
3581 /******************** Bit definition for DMA2D_BGPFCCR register *************/
3582 
3583 #define DMA2D_BGPFCCR_CM 0x0000000FU
3584 #define DMA2D_BGPFCCR_CM_0 0x00000001U
3585 #define DMA2D_BGPFCCR_CM_1 0x00000002U
3586 #define DMA2D_BGPFCCR_CM_2 0x00000004U
3587 #define DMA2D_FGPFCCR_CM_3 0x00000008U
3588 #define DMA2D_BGPFCCR_CCM 0x00000010U
3589 #define DMA2D_BGPFCCR_START 0x00000020U
3590 #define DMA2D_BGPFCCR_CS 0x0000FF00U
3591 #define DMA2D_BGPFCCR_AM 0x00030000U
3592 #define DMA2D_BGPFCCR_AM_0 0x00010000U
3593 #define DMA2D_BGPFCCR_AM_1 0x00020000U
3594 #define DMA2D_BGPFCCR_ALPHA 0xFF000000U
3596 /******************** Bit definition for DMA2D_BGCOLR register **************/
3597 
3598 #define DMA2D_BGCOLR_BLUE 0x000000FFU
3599 #define DMA2D_BGCOLR_GREEN 0x0000FF00U
3600 #define DMA2D_BGCOLR_RED 0x00FF0000U
3602 /******************** Bit definition for DMA2D_FGCMAR register **************/
3603 
3604 #define DMA2D_FGCMAR_MA 0xFFFFFFFFU
3606 /******************** Bit definition for DMA2D_BGCMAR register **************/
3607 
3608 #define DMA2D_BGCMAR_MA 0xFFFFFFFFU
3610 /******************** Bit definition for DMA2D_OPFCCR register **************/
3611 
3612 #define DMA2D_OPFCCR_CM 0x00000007U
3613 #define DMA2D_OPFCCR_CM_0 0x00000001U
3614 #define DMA2D_OPFCCR_CM_1 0x00000002U
3615 #define DMA2D_OPFCCR_CM_2 0x00000004U
3617 /******************** Bit definition for DMA2D_OCOLR register ***************/
3618 
3621 #define DMA2D_OCOLR_BLUE_1 0x000000FFU
3622 #define DMA2D_OCOLR_GREEN_1 0x0000FF00U
3623 #define DMA2D_OCOLR_RED_1 0x00FF0000U
3624 #define DMA2D_OCOLR_ALPHA_1 0xFF000000U
3627 #define DMA2D_OCOLR_BLUE_2 0x0000001FU
3628 #define DMA2D_OCOLR_GREEN_2 0x000007E0U
3629 #define DMA2D_OCOLR_RED_2 0x0000F800U
3632 #define DMA2D_OCOLR_BLUE_3 0x0000001FU
3633 #define DMA2D_OCOLR_GREEN_3 0x000003E0U
3634 #define DMA2D_OCOLR_RED_3 0x00007C00U
3635 #define DMA2D_OCOLR_ALPHA_3 0x00008000U
3638 #define DMA2D_OCOLR_BLUE_4 0x0000000FU
3639 #define DMA2D_OCOLR_GREEN_4 0x000000F0U
3640 #define DMA2D_OCOLR_RED_4 0x00000F00U
3641 #define DMA2D_OCOLR_ALPHA_4 0x0000F000U
3643 /******************** Bit definition for DMA2D_OMAR register ****************/
3644 
3645 #define DMA2D_OMAR_MA 0xFFFFFFFFU
3647 /******************** Bit definition for DMA2D_OOR register *****************/
3648 
3649 #define DMA2D_OOR_LO 0x00003FFFU
3651 /******************** Bit definition for DMA2D_NLR register *****************/
3652 
3653 #define DMA2D_NLR_NL 0x0000FFFFU
3654 #define DMA2D_NLR_PL 0x3FFF0000U
3656 /******************** Bit definition for DMA2D_LWR register *****************/
3657 
3658 #define DMA2D_LWR_LW 0x0000FFFFU
3660 /******************** Bit definition for DMA2D_AMTCR register ***************/
3661 
3662 #define DMA2D_AMTCR_EN 0x00000001U
3663 #define DMA2D_AMTCR_DT 0x0000FF00U
3666 /******************** Bit definition for DMA2D_FGCLUT register **************/
3667 
3668 /******************** Bit definition for DMA2D_BGCLUT register **************/
3669 
3670 
3671 /******************************************************************************/
3672 /* */
3673 /* External Interrupt/Event Controller */
3674 /* */
3675 /******************************************************************************/
3676 /******************* Bit definition for EXTI_IMR register *******************/
3677 #define EXTI_IMR_MR0 0x00000001U
3678 #define EXTI_IMR_MR1 0x00000002U
3679 #define EXTI_IMR_MR2 0x00000004U
3680 #define EXTI_IMR_MR3 0x00000008U
3681 #define EXTI_IMR_MR4 0x00000010U
3682 #define EXTI_IMR_MR5 0x00000020U
3683 #define EXTI_IMR_MR6 0x00000040U
3684 #define EXTI_IMR_MR7 0x00000080U
3685 #define EXTI_IMR_MR8 0x00000100U
3686 #define EXTI_IMR_MR9 0x00000200U
3687 #define EXTI_IMR_MR10 0x00000400U
3688 #define EXTI_IMR_MR11 0x00000800U
3689 #define EXTI_IMR_MR12 0x00001000U
3690 #define EXTI_IMR_MR13 0x00002000U
3691 #define EXTI_IMR_MR14 0x00004000U
3692 #define EXTI_IMR_MR15 0x00008000U
3693 #define EXTI_IMR_MR16 0x00010000U
3694 #define EXTI_IMR_MR17 0x00020000U
3695 #define EXTI_IMR_MR18 0x00040000U
3696 #define EXTI_IMR_MR19 0x00080000U
3697 #define EXTI_IMR_MR20 0x00100000U
3698 #define EXTI_IMR_MR21 0x00200000U
3699 #define EXTI_IMR_MR22 0x00400000U
3700 #define EXTI_IMR_MR23 0x00800000U
3702 /* Reference Defines */
3703 #define EXTI_IMR_IM0 EXTI_IMR_MR0
3704 #define EXTI_IMR_IM1 EXTI_IMR_MR1
3705 #define EXTI_IMR_IM2 EXTI_IMR_MR2
3706 #define EXTI_IMR_IM3 EXTI_IMR_MR3
3707 #define EXTI_IMR_IM4 EXTI_IMR_MR4
3708 #define EXTI_IMR_IM5 EXTI_IMR_MR5
3709 #define EXTI_IMR_IM6 EXTI_IMR_MR6
3710 #define EXTI_IMR_IM7 EXTI_IMR_MR7
3711 #define EXTI_IMR_IM8 EXTI_IMR_MR8
3712 #define EXTI_IMR_IM9 EXTI_IMR_MR9
3713 #define EXTI_IMR_IM10 EXTI_IMR_MR10
3714 #define EXTI_IMR_IM11 EXTI_IMR_MR11
3715 #define EXTI_IMR_IM12 EXTI_IMR_MR12
3716 #define EXTI_IMR_IM13 EXTI_IMR_MR13
3717 #define EXTI_IMR_IM14 EXTI_IMR_MR14
3718 #define EXTI_IMR_IM15 EXTI_IMR_MR15
3719 #define EXTI_IMR_IM16 EXTI_IMR_MR16
3720 #define EXTI_IMR_IM17 EXTI_IMR_MR17
3721 #define EXTI_IMR_IM18 EXTI_IMR_MR18
3722 #define EXTI_IMR_IM19 EXTI_IMR_MR19
3723 #define EXTI_IMR_IM20 EXTI_IMR_MR20
3724 #define EXTI_IMR_IM21 EXTI_IMR_MR21
3725 #define EXTI_IMR_IM22 EXTI_IMR_MR22
3726 #define EXTI_IMR_IM23 EXTI_IMR_MR23
3727 
3728 #define EXTI_IMR_IM 0x00FFFFFFU
3730 /******************* Bit definition for EXTI_EMR register *******************/
3731 #define EXTI_EMR_MR0 0x00000001U
3732 #define EXTI_EMR_MR1 0x00000002U
3733 #define EXTI_EMR_MR2 0x00000004U
3734 #define EXTI_EMR_MR3 0x00000008U
3735 #define EXTI_EMR_MR4 0x00000010U
3736 #define EXTI_EMR_MR5 0x00000020U
3737 #define EXTI_EMR_MR6 0x00000040U
3738 #define EXTI_EMR_MR7 0x00000080U
3739 #define EXTI_EMR_MR8 0x00000100U
3740 #define EXTI_EMR_MR9 0x00000200U
3741 #define EXTI_EMR_MR10 0x00000400U
3742 #define EXTI_EMR_MR11 0x00000800U
3743 #define EXTI_EMR_MR12 0x00001000U
3744 #define EXTI_EMR_MR13 0x00002000U
3745 #define EXTI_EMR_MR14 0x00004000U
3746 #define EXTI_EMR_MR15 0x00008000U
3747 #define EXTI_EMR_MR16 0x00010000U
3748 #define EXTI_EMR_MR17 0x00020000U
3749 #define EXTI_EMR_MR18 0x00040000U
3750 #define EXTI_EMR_MR19 0x00080000U
3751 #define EXTI_EMR_MR20 0x00100000U
3752 #define EXTI_EMR_MR21 0x00200000U
3753 #define EXTI_EMR_MR22 0x00400000U
3754 #define EXTI_EMR_MR23 0x00800000U
3756 /* Reference Defines */
3757 #define EXTI_EMR_EM0 EXTI_EMR_MR0
3758 #define EXTI_EMR_EM1 EXTI_EMR_MR1
3759 #define EXTI_EMR_EM2 EXTI_EMR_MR2
3760 #define EXTI_EMR_EM3 EXTI_EMR_MR3
3761 #define EXTI_EMR_EM4 EXTI_EMR_MR4
3762 #define EXTI_EMR_EM5 EXTI_EMR_MR5
3763 #define EXTI_EMR_EM6 EXTI_EMR_MR6
3764 #define EXTI_EMR_EM7 EXTI_EMR_MR7
3765 #define EXTI_EMR_EM8 EXTI_EMR_MR8
3766 #define EXTI_EMR_EM9 EXTI_EMR_MR9
3767 #define EXTI_EMR_EM10 EXTI_EMR_MR10
3768 #define EXTI_EMR_EM11 EXTI_EMR_MR11
3769 #define EXTI_EMR_EM12 EXTI_EMR_MR12
3770 #define EXTI_EMR_EM13 EXTI_EMR_MR13
3771 #define EXTI_EMR_EM14 EXTI_EMR_MR14
3772 #define EXTI_EMR_EM15 EXTI_EMR_MR15
3773 #define EXTI_EMR_EM16 EXTI_EMR_MR16
3774 #define EXTI_EMR_EM17 EXTI_EMR_MR17
3775 #define EXTI_EMR_EM18 EXTI_EMR_MR18
3776 #define EXTI_EMR_EM19 EXTI_EMR_MR19
3777 #define EXTI_EMR_EM20 EXTI_EMR_MR20
3778 #define EXTI_EMR_EM21 EXTI_EMR_MR21
3779 #define EXTI_EMR_EM22 EXTI_EMR_MR22
3780 #define EXTI_EMR_EM23 EXTI_EMR_MR23
3781 
3782 
3783 /****************** Bit definition for EXTI_RTSR register *******************/
3784 #define EXTI_RTSR_TR0 0x00000001U
3785 #define EXTI_RTSR_TR1 0x00000002U
3786 #define EXTI_RTSR_TR2 0x00000004U
3787 #define EXTI_RTSR_TR3 0x00000008U
3788 #define EXTI_RTSR_TR4 0x00000010U
3789 #define EXTI_RTSR_TR5 0x00000020U
3790 #define EXTI_RTSR_TR6 0x00000040U
3791 #define EXTI_RTSR_TR7 0x00000080U
3792 #define EXTI_RTSR_TR8 0x00000100U
3793 #define EXTI_RTSR_TR9 0x00000200U
3794 #define EXTI_RTSR_TR10 0x00000400U
3795 #define EXTI_RTSR_TR11 0x00000800U
3796 #define EXTI_RTSR_TR12 0x00001000U
3797 #define EXTI_RTSR_TR13 0x00002000U
3798 #define EXTI_RTSR_TR14 0x00004000U
3799 #define EXTI_RTSR_TR15 0x00008000U
3800 #define EXTI_RTSR_TR16 0x00010000U
3801 #define EXTI_RTSR_TR17 0x00020000U
3802 #define EXTI_RTSR_TR18 0x00040000U
3803 #define EXTI_RTSR_TR19 0x00080000U
3804 #define EXTI_RTSR_TR20 0x00100000U
3805 #define EXTI_RTSR_TR21 0x00200000U
3806 #define EXTI_RTSR_TR22 0x00400000U
3807 #define EXTI_RTSR_TR23 0x00800000U
3809 /****************** Bit definition for EXTI_FTSR register *******************/
3810 #define EXTI_FTSR_TR0 0x00000001U
3811 #define EXTI_FTSR_TR1 0x00000002U
3812 #define EXTI_FTSR_TR2 0x00000004U
3813 #define EXTI_FTSR_TR3 0x00000008U
3814 #define EXTI_FTSR_TR4 0x00000010U
3815 #define EXTI_FTSR_TR5 0x00000020U
3816 #define EXTI_FTSR_TR6 0x00000040U
3817 #define EXTI_FTSR_TR7 0x00000080U
3818 #define EXTI_FTSR_TR8 0x00000100U
3819 #define EXTI_FTSR_TR9 0x00000200U
3820 #define EXTI_FTSR_TR10 0x00000400U
3821 #define EXTI_FTSR_TR11 0x00000800U
3822 #define EXTI_FTSR_TR12 0x00001000U
3823 #define EXTI_FTSR_TR13 0x00002000U
3824 #define EXTI_FTSR_TR14 0x00004000U
3825 #define EXTI_FTSR_TR15 0x00008000U
3826 #define EXTI_FTSR_TR16 0x00010000U
3827 #define EXTI_FTSR_TR17 0x00020000U
3828 #define EXTI_FTSR_TR18 0x00040000U
3829 #define EXTI_FTSR_TR19 0x00080000U
3830 #define EXTI_FTSR_TR20 0x00100000U
3831 #define EXTI_FTSR_TR21 0x00200000U
3832 #define EXTI_FTSR_TR22 0x00400000U
3833 #define EXTI_FTSR_TR23 0x00800000U
3835 /****************** Bit definition for EXTI_SWIER register ******************/
3836 #define EXTI_SWIER_SWIER0 0x00000001U
3837 #define EXTI_SWIER_SWIER1 0x00000002U
3838 #define EXTI_SWIER_SWIER2 0x00000004U
3839 #define EXTI_SWIER_SWIER3 0x00000008U
3840 #define EXTI_SWIER_SWIER4 0x00000010U
3841 #define EXTI_SWIER_SWIER5 0x00000020U
3842 #define EXTI_SWIER_SWIER6 0x00000040U
3843 #define EXTI_SWIER_SWIER7 0x00000080U
3844 #define EXTI_SWIER_SWIER8 0x00000100U
3845 #define EXTI_SWIER_SWIER9 0x00000200U
3846 #define EXTI_SWIER_SWIER10 0x00000400U
3847 #define EXTI_SWIER_SWIER11 0x00000800U
3848 #define EXTI_SWIER_SWIER12 0x00001000U
3849 #define EXTI_SWIER_SWIER13 0x00002000U
3850 #define EXTI_SWIER_SWIER14 0x00004000U
3851 #define EXTI_SWIER_SWIER15 0x00008000U
3852 #define EXTI_SWIER_SWIER16 0x00010000U
3853 #define EXTI_SWIER_SWIER17 0x00020000U
3854 #define EXTI_SWIER_SWIER18 0x00040000U
3855 #define EXTI_SWIER_SWIER19 0x00080000U
3856 #define EXTI_SWIER_SWIER20 0x00100000U
3857 #define EXTI_SWIER_SWIER21 0x00200000U
3858 #define EXTI_SWIER_SWIER22 0x00400000U
3859 #define EXTI_SWIER_SWIER23 0x00800000U
3861 /******************* Bit definition for EXTI_PR register ********************/
3862 #define EXTI_PR_PR0 0x00000001U
3863 #define EXTI_PR_PR1 0x00000002U
3864 #define EXTI_PR_PR2 0x00000004U
3865 #define EXTI_PR_PR3 0x00000008U
3866 #define EXTI_PR_PR4 0x00000010U
3867 #define EXTI_PR_PR5 0x00000020U
3868 #define EXTI_PR_PR6 0x00000040U
3869 #define EXTI_PR_PR7 0x00000080U
3870 #define EXTI_PR_PR8 0x00000100U
3871 #define EXTI_PR_PR9 0x00000200U
3872 #define EXTI_PR_PR10 0x00000400U
3873 #define EXTI_PR_PR11 0x00000800U
3874 #define EXTI_PR_PR12 0x00001000U
3875 #define EXTI_PR_PR13 0x00002000U
3876 #define EXTI_PR_PR14 0x00004000U
3877 #define EXTI_PR_PR15 0x00008000U
3878 #define EXTI_PR_PR16 0x00010000U
3879 #define EXTI_PR_PR17 0x00020000U
3880 #define EXTI_PR_PR18 0x00040000U
3881 #define EXTI_PR_PR19 0x00080000U
3882 #define EXTI_PR_PR20 0x00100000U
3883 #define EXTI_PR_PR21 0x00200000U
3884 #define EXTI_PR_PR22 0x00400000U
3885 #define EXTI_PR_PR23 0x00800000U
3887 /******************************************************************************/
3888 /* */
3889 /* FLASH */
3890 /* */
3891 /******************************************************************************/
3892 /*
3893 * @brief FLASH Total Sectors Number
3894 */
3895 #define FLASH_SECTOR_TOTAL 8
3896 
3897 /******************* Bits definition for FLASH_ACR register *****************/
3898 #define FLASH_ACR_LATENCY 0x0000000FU
3899 #define FLASH_ACR_LATENCY_0WS 0x00000000U
3900 #define FLASH_ACR_LATENCY_1WS 0x00000001U
3901 #define FLASH_ACR_LATENCY_2WS 0x00000002U
3902 #define FLASH_ACR_LATENCY_3WS 0x00000003U
3903 #define FLASH_ACR_LATENCY_4WS 0x00000004U
3904 #define FLASH_ACR_LATENCY_5WS 0x00000005U
3905 #define FLASH_ACR_LATENCY_6WS 0x00000006U
3906 #define FLASH_ACR_LATENCY_7WS 0x00000007U
3907 #define FLASH_ACR_LATENCY_8WS 0x00000008U
3908 #define FLASH_ACR_LATENCY_9WS 0x00000009U
3909 #define FLASH_ACR_LATENCY_10WS 0x0000000AU
3910 #define FLASH_ACR_LATENCY_11WS 0x0000000BU
3911 #define FLASH_ACR_LATENCY_12WS 0x0000000CU
3912 #define FLASH_ACR_LATENCY_13WS 0x0000000DU
3913 #define FLASH_ACR_LATENCY_14WS 0x0000000EU
3914 #define FLASH_ACR_LATENCY_15WS 0x0000000FU
3915 #define FLASH_ACR_PRFTEN 0x00000100U
3916 #define FLASH_ACR_ARTEN 0x00000200U
3917 #define FLASH_ACR_ARTRST 0x00000800U
3918 
3919 /******************* Bits definition for FLASH_SR register ******************/
3920 #define FLASH_SR_EOP 0x00000001U
3921 #define FLASH_SR_OPERR 0x00000002U
3922 #define FLASH_SR_WRPERR 0x00000010U
3923 #define FLASH_SR_PGAERR 0x00000020U
3924 #define FLASH_SR_PGPERR 0x00000040U
3925 #define FLASH_SR_ERSERR 0x00000080U
3926 #define FLASH_SR_BSY 0x00010000U
3927 
3928 /******************* Bits definition for FLASH_CR register ******************/
3929 #define FLASH_CR_PG 0x00000001U
3930 #define FLASH_CR_SER 0x00000002U
3931 #define FLASH_CR_MER 0x00000004U
3932 #define FLASH_CR_SNB 0x00000078U
3933 #define FLASH_CR_SNB_0 0x00000008U
3934 #define FLASH_CR_SNB_1 0x00000010U
3935 #define FLASH_CR_SNB_2 0x00000020U
3936 #define FLASH_CR_SNB_3 0x00000040U
3937 #define FLASH_CR_PSIZE 0x00000300U
3938 #define FLASH_CR_PSIZE_0 0x00000100U
3939 #define FLASH_CR_PSIZE_1 0x00000200U
3940 #define FLASH_CR_STRT 0x00010000U
3941 #define FLASH_CR_EOPIE 0x01000000U
3942 #define FLASH_CR_ERRIE 0x02000000U
3943 #define FLASH_CR_LOCK 0x80000000U
3944 
3945 /******************* Bits definition for FLASH_OPTCR register ***************/
3946 #define FLASH_OPTCR_OPTLOCK 0x00000001U
3947 #define FLASH_OPTCR_OPTSTRT 0x00000002U
3948 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
3949 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
3950 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
3951 #define FLASH_OPTCR_WWDG_SW 0x00000010U
3952 #define FLASH_OPTCR_IWDG_SW 0x00000020U
3953 #define FLASH_OPTCR_nRST_STOP 0x00000040U
3954 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
3955 #define FLASH_OPTCR_RDP 0x0000FF00U
3956 #define FLASH_OPTCR_RDP_0 0x00000100U
3957 #define FLASH_OPTCR_RDP_1 0x00000200U
3958 #define FLASH_OPTCR_RDP_2 0x00000400U
3959 #define FLASH_OPTCR_RDP_3 0x00000800U
3960 #define FLASH_OPTCR_RDP_4 0x00001000U
3961 #define FLASH_OPTCR_RDP_5 0x00002000U
3962 #define FLASH_OPTCR_RDP_6 0x00004000U
3963 #define FLASH_OPTCR_RDP_7 0x00008000U
3964 #define FLASH_OPTCR_nWRP 0x00FF0000U
3965 #define FLASH_OPTCR_nWRP_0 0x00010000U
3966 #define FLASH_OPTCR_nWRP_1 0x00020000U
3967 #define FLASH_OPTCR_nWRP_2 0x00040000U
3968 #define FLASH_OPTCR_nWRP_3 0x00080000U
3969 #define FLASH_OPTCR_nWRP_4 0x00100000U
3970 #define FLASH_OPTCR_nWRP_5 0x00200000U
3971 #define FLASH_OPTCR_nWRP_6 0x00400000U
3972 #define FLASH_OPTCR_nWRP_7 0x00800000U
3973 #define FLASH_OPTCR_IWDG_STDBY 0x40000000U
3974 #define FLASH_OPTCR_IWDG_STOP 0x80000000U
3975 
3976 /******************* Bits definition for FLASH_OPTCR1 register ***************/
3977 #define FLASH_OPTCR1_BOOT_ADD0 0x0000FFFFU
3978 #define FLASH_OPTCR1_BOOT_ADD1 0xFFFF0000U
3979 
3980 /******************************************************************************/
3981 /* */
3982 /* Flexible Memory Controller */
3983 /* */
3984 /******************************************************************************/
3985 /****************** Bit definition for FMC_BCR1 register *******************/
3986 #define FMC_BCR1_MBKEN 0x00000001U
3987 #define FMC_BCR1_MUXEN 0x00000002U
3988 #define FMC_BCR1_MTYP 0x0000000CU
3989 #define FMC_BCR1_MTYP_0 0x00000004U
3990 #define FMC_BCR1_MTYP_1 0x00000008U
3991 #define FMC_BCR1_MWID 0x00000030U
3992 #define FMC_BCR1_MWID_0 0x00000010U
3993 #define FMC_BCR1_MWID_1 0x00000020U
3994 #define FMC_BCR1_FACCEN 0x00000040U
3995 #define FMC_BCR1_BURSTEN 0x00000100U
3996 #define FMC_BCR1_WAITPOL 0x00000200U
3997 #define FMC_BCR1_WRAPMOD 0x00000400U
3998 #define FMC_BCR1_WAITCFG 0x00000800U
3999 #define FMC_BCR1_WREN 0x00001000U
4000 #define FMC_BCR1_WAITEN 0x00002000U
4001 #define FMC_BCR1_EXTMOD 0x00004000U
4002 #define FMC_BCR1_ASYNCWAIT 0x00008000U
4003 #define FMC_BCR1_CPSIZE 0x00070000U
4004 #define FMC_BCR1_CPSIZE_0 0x00010000U
4005 #define FMC_BCR1_CPSIZE_1 0x00020000U
4006 #define FMC_BCR1_CPSIZE_2 0x00040000U
4007 #define FMC_BCR1_CBURSTRW 0x00080000U
4008 #define FMC_BCR1_CCLKEN 0x00100000U
4009 #define FMC_BCR1_WFDIS 0x00200000U
4011 /****************** Bit definition for FMC_BCR2 register *******************/
4012 #define FMC_BCR2_MBKEN 0x00000001U
4013 #define FMC_BCR2_MUXEN 0x00000002U
4014 #define FMC_BCR2_MTYP 0x0000000CU
4015 #define FMC_BCR2_MTYP_0 0x00000004U
4016 #define FMC_BCR2_MTYP_1 0x00000008U
4017 #define FMC_BCR2_MWID 0x00000030U
4018 #define FMC_BCR2_MWID_0 0x00000010U
4019 #define FMC_BCR2_MWID_1 0x00000020U
4020 #define FMC_BCR2_FACCEN 0x00000040U
4021 #define FMC_BCR2_BURSTEN 0x00000100U
4022 #define FMC_BCR2_WAITPOL 0x00000200U
4023 #define FMC_BCR2_WRAPMOD 0x00000400U
4024 #define FMC_BCR2_WAITCFG 0x00000800U
4025 #define FMC_BCR2_WREN 0x00001000U
4026 #define FMC_BCR2_WAITEN 0x00002000U
4027 #define FMC_BCR2_EXTMOD 0x00004000U
4028 #define FMC_BCR2_ASYNCWAIT 0x00008000U
4029 #define FMC_BCR2_CPSIZE 0x00070000U
4030 #define FMC_BCR2_CPSIZE_0 0x00010000U
4031 #define FMC_BCR2_CPSIZE_1 0x00020000U
4032 #define FMC_BCR2_CPSIZE_2 0x00040000U
4033 #define FMC_BCR2_CBURSTRW 0x00080000U
4035 /****************** Bit definition for FMC_BCR3 register *******************/
4036 #define FMC_BCR3_MBKEN 0x00000001U
4037 #define FMC_BCR3_MUXEN 0x00000002U
4038 #define FMC_BCR3_MTYP 0x0000000CU
4039 #define FMC_BCR3_MTYP_0 0x00000004U
4040 #define FMC_BCR3_MTYP_1 0x00000008U
4041 #define FMC_BCR3_MWID 0x00000030U
4042 #define FMC_BCR3_MWID_0 0x00000010U
4043 #define FMC_BCR3_MWID_1 0x00000020U
4044 #define FMC_BCR3_FACCEN 0x00000040U
4045 #define FMC_BCR3_BURSTEN 0x00000100U
4046 #define FMC_BCR3_WAITPOL 0x00000200U
4047 #define FMC_BCR3_WRAPMOD 0x00000400U
4048 #define FMC_BCR3_WAITCFG 0x00000800U
4049 #define FMC_BCR3_WREN 0x00001000U
4050 #define FMC_BCR3_WAITEN 0x00002000U
4051 #define FMC_BCR3_EXTMOD 0x00004000U
4052 #define FMC_BCR3_ASYNCWAIT 0x00008000U
4053 #define FMC_BCR3_CPSIZE 0x00070000U
4054 #define FMC_BCR3_CPSIZE_0 0x00010000U
4055 #define FMC_BCR3_CPSIZE_1 0x00020000U
4056 #define FMC_BCR3_CPSIZE_2 0x00040000U
4057 #define FMC_BCR3_CBURSTRW 0x00080000U
4059 /****************** Bit definition for FMC_BCR4 register *******************/
4060 #define FMC_BCR4_MBKEN 0x00000001U
4061 #define FMC_BCR4_MUXEN 0x00000002U
4062 #define FMC_BCR4_MTYP 0x0000000CU
4063 #define FMC_BCR4_MTYP_0 0x00000004U
4064 #define FMC_BCR4_MTYP_1 0x00000008U
4065 #define FMC_BCR4_MWID 0x00000030U
4066 #define FMC_BCR4_MWID_0 0x00000010U
4067 #define FMC_BCR4_MWID_1 0x00000020U
4068 #define FMC_BCR4_FACCEN 0x00000040U
4069 #define FMC_BCR4_BURSTEN 0x00000100U
4070 #define FMC_BCR4_WAITPOL 0x00000200U
4071 #define FMC_BCR4_WRAPMOD 0x00000400U
4072 #define FMC_BCR4_WAITCFG 0x00000800U
4073 #define FMC_BCR4_WREN 0x00001000U
4074 #define FMC_BCR4_WAITEN 0x00002000U
4075 #define FMC_BCR4_EXTMOD 0x00004000U
4076 #define FMC_BCR4_ASYNCWAIT 0x00008000U
4077 #define FMC_BCR4_CPSIZE 0x00070000U
4078 #define FMC_BCR4_CPSIZE_0 0x00010000U
4079 #define FMC_BCR4_CPSIZE_1 0x00020000U
4080 #define FMC_BCR4_CPSIZE_2 0x00040000U
4081 #define FMC_BCR4_CBURSTRW 0x00080000U
4083 /****************** Bit definition for FMC_BTR1 register ******************/
4084 #define FMC_BTR1_ADDSET 0x0000000FU
4085 #define FMC_BTR1_ADDSET_0 0x00000001U
4086 #define FMC_BTR1_ADDSET_1 0x00000002U
4087 #define FMC_BTR1_ADDSET_2 0x00000004U
4088 #define FMC_BTR1_ADDSET_3 0x00000008U
4089 #define FMC_BTR1_ADDHLD 0x000000F0U
4090 #define FMC_BTR1_ADDHLD_0 0x00000010U
4091 #define FMC_BTR1_ADDHLD_1 0x00000020U
4092 #define FMC_BTR1_ADDHLD_2 0x00000040U
4093 #define FMC_BTR1_ADDHLD_3 0x00000080U
4094 #define FMC_BTR1_DATAST 0x0000FF00U
4095 #define FMC_BTR1_DATAST_0 0x00000100U
4096 #define FMC_BTR1_DATAST_1 0x00000200U
4097 #define FMC_BTR1_DATAST_2 0x00000400U
4098 #define FMC_BTR1_DATAST_3 0x00000800U
4099 #define FMC_BTR1_DATAST_4 0x00001000U
4100 #define FMC_BTR1_DATAST_5 0x00002000U
4101 #define FMC_BTR1_DATAST_6 0x00004000U
4102 #define FMC_BTR1_DATAST_7 0x00008000U
4103 #define FMC_BTR1_BUSTURN 0x000F0000U
4104 #define FMC_BTR1_BUSTURN_0 0x00010000U
4105 #define FMC_BTR1_BUSTURN_1 0x00020000U
4106 #define FMC_BTR1_BUSTURN_2 0x00040000U
4107 #define FMC_BTR1_BUSTURN_3 0x00080000U
4108 #define FMC_BTR1_CLKDIV 0x00F00000U
4109 #define FMC_BTR1_CLKDIV_0 0x00100000U
4110 #define FMC_BTR1_CLKDIV_1 0x00200000U
4111 #define FMC_BTR1_CLKDIV_2 0x00400000U
4112 #define FMC_BTR1_CLKDIV_3 0x00800000U
4113 #define FMC_BTR1_DATLAT 0x0F000000U
4114 #define FMC_BTR1_DATLAT_0 0x01000000U
4115 #define FMC_BTR1_DATLAT_1 0x02000000U
4116 #define FMC_BTR1_DATLAT_2 0x04000000U
4117 #define FMC_BTR1_DATLAT_3 0x08000000U
4118 #define FMC_BTR1_ACCMOD 0x30000000U
4119 #define FMC_BTR1_ACCMOD_0 0x10000000U
4120 #define FMC_BTR1_ACCMOD_1 0x20000000U
4122 /****************** Bit definition for FMC_BTR2 register *******************/
4123 #define FMC_BTR2_ADDSET 0x0000000FU
4124 #define FMC_BTR2_ADDSET_0 0x00000001U
4125 #define FMC_BTR2_ADDSET_1 0x00000002U
4126 #define FMC_BTR2_ADDSET_2 0x00000004U
4127 #define FMC_BTR2_ADDSET_3 0x00000008U
4128 #define FMC_BTR2_ADDHLD 0x000000F0U
4129 #define FMC_BTR2_ADDHLD_0 0x00000010U
4130 #define FMC_BTR2_ADDHLD_1 0x00000020U
4131 #define FMC_BTR2_ADDHLD_2 0x00000040U
4132 #define FMC_BTR2_ADDHLD_3 0x00000080U
4133 #define FMC_BTR2_DATAST 0x0000FF00U
4134 #define FMC_BTR2_DATAST_0 0x00000100U
4135 #define FMC_BTR2_DATAST_1 0x00000200U
4136 #define FMC_BTR2_DATAST_2 0x00000400U
4137 #define FMC_BTR2_DATAST_3 0x00000800U
4138 #define FMC_BTR2_DATAST_4 0x00001000U
4139 #define FMC_BTR2_DATAST_5 0x00002000U
4140 #define FMC_BTR2_DATAST_6 0x00004000U
4141 #define FMC_BTR2_DATAST_7 0x00008000U
4142 #define FMC_BTR2_BUSTURN 0x000F0000U
4143 #define FMC_BTR2_BUSTURN_0 0x00010000U
4144 #define FMC_BTR2_BUSTURN_1 0x00020000U
4145 #define FMC_BTR2_BUSTURN_2 0x00040000U
4146 #define FMC_BTR2_BUSTURN_3 0x00080000U
4147 #define FMC_BTR2_CLKDIV 0x00F00000U
4148 #define FMC_BTR2_CLKDIV_0 0x00100000U
4149 #define FMC_BTR2_CLKDIV_1 0x00200000U
4150 #define FMC_BTR2_CLKDIV_2 0x00400000U
4151 #define FMC_BTR2_CLKDIV_3 0x00800000U
4152 #define FMC_BTR2_DATLAT 0x0F000000U
4153 #define FMC_BTR2_DATLAT_0 0x01000000U
4154 #define FMC_BTR2_DATLAT_1 0x02000000U
4155 #define FMC_BTR2_DATLAT_2 0x04000000U
4156 #define FMC_BTR2_DATLAT_3 0x08000000U
4157 #define FMC_BTR2_ACCMOD 0x30000000U
4158 #define FMC_BTR2_ACCMOD_0 0x10000000U
4159 #define FMC_BTR2_ACCMOD_1 0x20000000U
4161 /******************* Bit definition for FMC_BTR3 register *******************/
4162 #define FMC_BTR3_ADDSET 0x0000000FU
4163 #define FMC_BTR3_ADDSET_0 0x00000001U
4164 #define FMC_BTR3_ADDSET_1 0x00000002U
4165 #define FMC_BTR3_ADDSET_2 0x00000004U
4166 #define FMC_BTR3_ADDSET_3 0x00000008U
4167 #define FMC_BTR3_ADDHLD 0x000000F0U
4168 #define FMC_BTR3_ADDHLD_0 0x00000010U
4169 #define FMC_BTR3_ADDHLD_1 0x00000020U
4170 #define FMC_BTR3_ADDHLD_2 0x00000040U
4171 #define FMC_BTR3_ADDHLD_3 0x00000080U
4172 #define FMC_BTR3_DATAST 0x0000FF00U
4173 #define FMC_BTR3_DATAST_0 0x00000100U
4174 #define FMC_BTR3_DATAST_1 0x00000200U
4175 #define FMC_BTR3_DATAST_2 0x00000400U
4176 #define FMC_BTR3_DATAST_3 0x00000800U
4177 #define FMC_BTR3_DATAST_4 0x00001000U
4178 #define FMC_BTR3_DATAST_5 0x00002000U
4179 #define FMC_BTR3_DATAST_6 0x00004000U
4180 #define FMC_BTR3_DATAST_7 0x00008000U
4181 #define FMC_BTR3_BUSTURN 0x000F0000U
4182 #define FMC_BTR3_BUSTURN_0 0x00010000U
4183 #define FMC_BTR3_BUSTURN_1 0x00020000U
4184 #define FMC_BTR3_BUSTURN_2 0x00040000U
4185 #define FMC_BTR3_BUSTURN_3 0x00080000U
4186 #define FMC_BTR3_CLKDIV 0x00F00000U
4187 #define FMC_BTR3_CLKDIV_0 0x00100000U
4188 #define FMC_BTR3_CLKDIV_1 0x00200000U
4189 #define FMC_BTR3_CLKDIV_2 0x00400000U
4190 #define FMC_BTR3_CLKDIV_3 0x00800000U
4191 #define FMC_BTR3_DATLAT 0x0F000000U
4192 #define FMC_BTR3_DATLAT_0 0x01000000U
4193 #define FMC_BTR3_DATLAT_1 0x02000000U
4194 #define FMC_BTR3_DATLAT_2 0x04000000U
4195 #define FMC_BTR3_DATLAT_3 0x08000000U
4196 #define FMC_BTR3_ACCMOD 0x30000000U
4197 #define FMC_BTR3_ACCMOD_0 0x10000000U
4198 #define FMC_BTR3_ACCMOD_1 0x20000000U
4200 /****************** Bit definition for FMC_BTR4 register *******************/
4201 #define FMC_BTR4_ADDSET 0x0000000FU
4202 #define FMC_BTR4_ADDSET_0 0x00000001U
4203 #define FMC_BTR4_ADDSET_1 0x00000002U
4204 #define FMC_BTR4_ADDSET_2 0x00000004U
4205 #define FMC_BTR4_ADDSET_3 0x00000008U
4206 #define FMC_BTR4_ADDHLD 0x000000F0U
4207 #define FMC_BTR4_ADDHLD_0 0x00000010U
4208 #define FMC_BTR4_ADDHLD_1 0x00000020U
4209 #define FMC_BTR4_ADDHLD_2 0x00000040U
4210 #define FMC_BTR4_ADDHLD_3 0x00000080U
4211 #define FMC_BTR4_DATAST 0x0000FF00U
4212 #define FMC_BTR4_DATAST_0 0x00000100U
4213 #define FMC_BTR4_DATAST_1 0x00000200U
4214 #define FMC_BTR4_DATAST_2 0x00000400U
4215 #define FMC_BTR4_DATAST_3 0x00000800U
4216 #define FMC_BTR4_DATAST_4 0x00001000U
4217 #define FMC_BTR4_DATAST_5 0x00002000U
4218 #define FMC_BTR4_DATAST_6 0x00004000U
4219 #define FMC_BTR4_DATAST_7 0x00008000U
4220 #define FMC_BTR4_BUSTURN 0x000F0000U
4221 #define FMC_BTR4_BUSTURN_0 0x00010000U
4222 #define FMC_BTR4_BUSTURN_1 0x00020000U
4223 #define FMC_BTR4_BUSTURN_2 0x00040000U
4224 #define FMC_BTR4_BUSTURN_3 0x00080000U
4225 #define FMC_BTR4_CLKDIV 0x00F00000U
4226 #define FMC_BTR4_CLKDIV_0 0x00100000U
4227 #define FMC_BTR4_CLKDIV_1 0x00200000U
4228 #define FMC_BTR4_CLKDIV_2 0x00400000U
4229 #define FMC_BTR4_CLKDIV_3 0x00800000U
4230 #define FMC_BTR4_DATLAT 0x0F000000U
4231 #define FMC_BTR4_DATLAT_0 0x01000000U
4232 #define FMC_BTR4_DATLAT_1 0x02000000U
4233 #define FMC_BTR4_DATLAT_2 0x04000000U
4234 #define FMC_BTR4_DATLAT_3 0x08000000U
4235 #define FMC_BTR4_ACCMOD 0x30000000U
4236 #define FMC_BTR4_ACCMOD_0 0x10000000U
4237 #define FMC_BTR4_ACCMOD_1 0x20000000U
4239 /****************** Bit definition for FMC_BWTR1 register ******************/
4240 #define FMC_BWTR1_ADDSET 0x0000000FU
4241 #define FMC_BWTR1_ADDSET_0 0x00000001U
4242 #define FMC_BWTR1_ADDSET_1 0x00000002U
4243 #define FMC_BWTR1_ADDSET_2 0x00000004U
4244 #define FMC_BWTR1_ADDSET_3 0x00000008U
4245 #define FMC_BWTR1_ADDHLD 0x000000F0U
4246 #define FMC_BWTR1_ADDHLD_0 0x00000010U
4247 #define FMC_BWTR1_ADDHLD_1 0x00000020U
4248 #define FMC_BWTR1_ADDHLD_2 0x00000040U
4249 #define FMC_BWTR1_ADDHLD_3 0x00000080U
4250 #define FMC_BWTR1_DATAST 0x0000FF00U
4251 #define FMC_BWTR1_DATAST_0 0x00000100U
4252 #define FMC_BWTR1_DATAST_1 0x00000200U
4253 #define FMC_BWTR1_DATAST_2 0x00000400U
4254 #define FMC_BWTR1_DATAST_3 0x00000800U
4255 #define FMC_BWTR1_DATAST_4 0x00001000U
4256 #define FMC_BWTR1_DATAST_5 0x00002000U
4257 #define FMC_BWTR1_DATAST_6 0x00004000U
4258 #define FMC_BWTR1_DATAST_7 0x00008000U
4259 #define FMC_BWTR1_BUSTURN 0x000F0000U
4260 #define FMC_BWTR1_BUSTURN_0 0x00010000U
4261 #define FMC_BWTR1_BUSTURN_1 0x00020000U
4262 #define FMC_BWTR1_BUSTURN_2 0x00040000U
4263 #define FMC_BWTR1_BUSTURN_3 0x00080000U
4264 #define FMC_BWTR1_ACCMOD 0x30000000U
4265 #define FMC_BWTR1_ACCMOD_0 0x10000000U
4266 #define FMC_BWTR1_ACCMOD_1 0x20000000U
4268 /****************** Bit definition for FMC_BWTR2 register ******************/
4269 #define FMC_BWTR2_ADDSET 0x0000000FU
4270 #define FMC_BWTR2_ADDSET_0 0x00000001U
4271 #define FMC_BWTR2_ADDSET_1 0x00000002U
4272 #define FMC_BWTR2_ADDSET_2 0x00000004U
4273 #define FMC_BWTR2_ADDSET_3 0x00000008U
4274 #define FMC_BWTR2_ADDHLD 0x000000F0U
4275 #define FMC_BWTR2_ADDHLD_0 0x00000010U
4276 #define FMC_BWTR2_ADDHLD_1 0x00000020U
4277 #define FMC_BWTR2_ADDHLD_2 0x00000040U
4278 #define FMC_BWTR2_ADDHLD_3 0x00000080U
4279 #define FMC_BWTR2_DATAST 0x0000FF00U
4280 #define FMC_BWTR2_DATAST_0 0x00000100U
4281 #define FMC_BWTR2_DATAST_1 0x00000200U
4282 #define FMC_BWTR2_DATAST_2 0x00000400U
4283 #define FMC_BWTR2_DATAST_3 0x00000800U
4284 #define FMC_BWTR2_DATAST_4 0x00001000U
4285 #define FMC_BWTR2_DATAST_5 0x00002000U
4286 #define FMC_BWTR2_DATAST_6 0x00004000U
4287 #define FMC_BWTR2_DATAST_7 0x00008000U
4288 #define FMC_BWTR2_BUSTURN 0x000F0000U
4289 #define FMC_BWTR2_BUSTURN_0 0x00010000U
4290 #define FMC_BWTR2_BUSTURN_1 0x00020000U
4291 #define FMC_BWTR2_BUSTURN_2 0x00040000U
4292 #define FMC_BWTR2_BUSTURN_3 0x00080000U
4293 #define FMC_BWTR2_ACCMOD 0x30000000U
4294 #define FMC_BWTR2_ACCMOD_0 0x10000000U
4295 #define FMC_BWTR2_ACCMOD_1 0x20000000U
4297 /****************** Bit definition for FMC_BWTR3 register ******************/
4298 #define FMC_BWTR3_ADDSET 0x0000000FU
4299 #define FMC_BWTR3_ADDSET_0 0x00000001U
4300 #define FMC_BWTR3_ADDSET_1 0x00000002U
4301 #define FMC_BWTR3_ADDSET_2 0x00000004U
4302 #define FMC_BWTR3_ADDSET_3 0x00000008U
4303 #define FMC_BWTR3_ADDHLD 0x000000F0U
4304 #define FMC_BWTR3_ADDHLD_0 0x00000010U
4305 #define FMC_BWTR3_ADDHLD_1 0x00000020U
4306 #define FMC_BWTR3_ADDHLD_2 0x00000040U
4307 #define FMC_BWTR3_ADDHLD_3 0x00000080U
4308 #define FMC_BWTR3_DATAST 0x0000FF00U
4309 #define FMC_BWTR3_DATAST_0 0x00000100U
4310 #define FMC_BWTR3_DATAST_1 0x00000200U
4311 #define FMC_BWTR3_DATAST_2 0x00000400U
4312 #define FMC_BWTR3_DATAST_3 0x00000800U
4313 #define FMC_BWTR3_DATAST_4 0x00001000U
4314 #define FMC_BWTR3_DATAST_5 0x00002000U
4315 #define FMC_BWTR3_DATAST_6 0x00004000U
4316 #define FMC_BWTR3_DATAST_7 0x00008000U
4317 #define FMC_BWTR3_BUSTURN 0x000F0000U
4318 #define FMC_BWTR3_BUSTURN_0 0x00010000U
4319 #define FMC_BWTR3_BUSTURN_1 0x00020000U
4320 #define FMC_BWTR3_BUSTURN_2 0x00040000U
4321 #define FMC_BWTR3_BUSTURN_3 0x00080000U
4322 #define FMC_BWTR3_ACCMOD 0x30000000U
4323 #define FMC_BWTR3_ACCMOD_0 0x10000000U
4324 #define FMC_BWTR3_ACCMOD_1 0x20000000U
4326 /****************** Bit definition for FMC_BWTR4 register ******************/
4327 #define FMC_BWTR4_ADDSET 0x0000000FU
4328 #define FMC_BWTR4_ADDSET_0 0x00000001U
4329 #define FMC_BWTR4_ADDSET_1 0x00000002U
4330 #define FMC_BWTR4_ADDSET_2 0x00000004U
4331 #define FMC_BWTR4_ADDSET_3 0x00000008U
4332 #define FMC_BWTR4_ADDHLD 0x000000F0U
4333 #define FMC_BWTR4_ADDHLD_0 0x00000010U
4334 #define FMC_BWTR4_ADDHLD_1 0x00000020U
4335 #define FMC_BWTR4_ADDHLD_2 0x00000040U
4336 #define FMC_BWTR4_ADDHLD_3 0x00000080U
4337 #define FMC_BWTR4_DATAST 0x0000FF00U
4338 #define FMC_BWTR4_DATAST_0 0x00000100U
4339 #define FMC_BWTR4_DATAST_1 0x00000200U
4340 #define FMC_BWTR4_DATAST_2 0x00000400U
4341 #define FMC_BWTR4_DATAST_3 0x00000800U
4342 #define FMC_BWTR4_DATAST_4 0x00001000U
4343 #define FMC_BWTR4_DATAST_5 0x00002000U
4344 #define FMC_BWTR4_DATAST_6 0x00004000U
4345 #define FMC_BWTR4_DATAST_7 0x00008000U
4346 #define FMC_BWTR4_BUSTURN 0x000F0000U
4347 #define FMC_BWTR4_BUSTURN_0 0x00010000U
4348 #define FMC_BWTR4_BUSTURN_1 0x00020000U
4349 #define FMC_BWTR4_BUSTURN_2 0x00040000U
4350 #define FMC_BWTR4_BUSTURN_3 0x00080000U
4351 #define FMC_BWTR4_ACCMOD 0x30000000U
4352 #define FMC_BWTR4_ACCMOD_0 0x10000000U
4353 #define FMC_BWTR4_ACCMOD_1 0x20000000U
4355 /****************** Bit definition for FMC_PCR register *******************/
4356 #define FMC_PCR_PWAITEN 0x00000002U
4357 #define FMC_PCR_PBKEN 0x00000004U
4358 #define FMC_PCR_PTYP 0x00000008U
4359 #define FMC_PCR_PWID 0x00000030U
4360 #define FMC_PCR_PWID_0 0x00000010U
4361 #define FMC_PCR_PWID_1 0x00000020U
4362 #define FMC_PCR_ECCEN 0x00000040U
4363 #define FMC_PCR_TCLR 0x00001E00U
4364 #define FMC_PCR_TCLR_0 0x00000200U
4365 #define FMC_PCR_TCLR_1 0x00000400U
4366 #define FMC_PCR_TCLR_2 0x00000800U
4367 #define FMC_PCR_TCLR_3 0x00001000U
4368 #define FMC_PCR_TAR 0x0001E000U
4369 #define FMC_PCR_TAR_0 0x00002000U
4370 #define FMC_PCR_TAR_1 0x00004000U
4371 #define FMC_PCR_TAR_2 0x00008000U
4372 #define FMC_PCR_TAR_3 0x00010000U
4373 #define FMC_PCR_ECCPS 0x000E0000U
4374 #define FMC_PCR_ECCPS_0 0x00020000U
4375 #define FMC_PCR_ECCPS_1 0x00040000U
4376 #define FMC_PCR_ECCPS_2 0x00080000U
4378 /******************* Bit definition for FMC_SR register *******************/
4379 #define FMC_SR_IRS 0x01U
4380 #define FMC_SR_ILS 0x02U
4381 #define FMC_SR_IFS 0x04U
4382 #define FMC_SR_IREN 0x08U
4383 #define FMC_SR_ILEN 0x10U
4384 #define FMC_SR_IFEN 0x20U
4385 #define FMC_SR_FEMPT 0x40U
4387 /****************** Bit definition for FMC_PMEM register ******************/
4388 #define FMC_PMEM_MEMSET3 0x000000FFU
4389 #define FMC_PMEM_MEMSET3_0 0x00000001U
4390 #define FMC_PMEM_MEMSET3_1 0x00000002U
4391 #define FMC_PMEM_MEMSET3_2 0x00000004U
4392 #define FMC_PMEM_MEMSET3_3 0x00000008U
4393 #define FMC_PMEM_MEMSET3_4 0x00000010U
4394 #define FMC_PMEM_MEMSET3_5 0x00000020U
4395 #define FMC_PMEM_MEMSET3_6 0x00000040U
4396 #define FMC_PMEM_MEMSET3_7 0x00000080U
4397 #define FMC_PMEM_MEMWAIT3 0x0000FF00U
4398 #define FMC_PMEM_MEMWAIT3_0 0x00000100U
4399 #define FMC_PMEM_MEMWAIT3_1 0x00000200U
4400 #define FMC_PMEM_MEMWAIT3_2 0x00000400U
4401 #define FMC_PMEM_MEMWAIT3_3 0x00000800U
4402 #define FMC_PMEM_MEMWAIT3_4 0x00001000U
4403 #define FMC_PMEM_MEMWAIT3_5 0x00002000U
4404 #define FMC_PMEM_MEMWAIT3_6 0x00004000U
4405 #define FMC_PMEM_MEMWAIT3_7 0x00008000U
4406 #define FMC_PMEM_MEMHOLD3 0x00FF0000U
4407 #define FMC_PMEM_MEMHOLD3_0 0x00010000U
4408 #define FMC_PMEM_MEMHOLD3_1 0x00020000U
4409 #define FMC_PMEM_MEMHOLD3_2 0x00040000U
4410 #define FMC_PMEM_MEMHOLD3_3 0x00080000U
4411 #define FMC_PMEM_MEMHOLD3_4 0x00100000U
4412 #define FMC_PMEM_MEMHOLD3_5 0x00200000U
4413 #define FMC_PMEM_MEMHOLD3_6 0x00400000U
4414 #define FMC_PMEM_MEMHOLD3_7 0x00800000U
4415 #define FMC_PMEM_MEMHIZ3 0xFF000000U
4416 #define FMC_PMEM_MEMHIZ3_0 0x01000000U
4417 #define FMC_PMEM_MEMHIZ3_1 0x02000000U
4418 #define FMC_PMEM_MEMHIZ3_2 0x04000000U
4419 #define FMC_PMEM_MEMHIZ3_3 0x08000000U
4420 #define FMC_PMEM_MEMHIZ3_4 0x10000000U
4421 #define FMC_PMEM_MEMHIZ3_5 0x20000000U
4422 #define FMC_PMEM_MEMHIZ3_6 0x40000000U
4423 #define FMC_PMEM_MEMHIZ3_7 0x80000000U
4425 /****************** Bit definition for FMC_PATT register ******************/
4426 #define FMC_PATT_ATTSET3 0x000000FFU
4427 #define FMC_PATT_ATTSET3_0 0x00000001U
4428 #define FMC_PATT_ATTSET3_1 0x00000002U
4429 #define FMC_PATT_ATTSET3_2 0x00000004U
4430 #define FMC_PATT_ATTSET3_3 0x00000008U
4431 #define FMC_PATT_ATTSET3_4 0x00000010U
4432 #define FMC_PATT_ATTSET3_5 0x00000020U
4433 #define FMC_PATT_ATTSET3_6 0x00000040U
4434 #define FMC_PATT_ATTSET3_7 0x00000080U
4435 #define FMC_PATT_ATTWAIT3 0x0000FF00U
4436 #define FMC_PATT_ATTWAIT3_0 0x00000100U
4437 #define FMC_PATT_ATTWAIT3_1 0x00000200U
4438 #define FMC_PATT_ATTWAIT3_2 0x00000400U
4439 #define FMC_PATT_ATTWAIT3_3 0x00000800U
4440 #define FMC_PATT_ATTWAIT3_4 0x00001000U
4441 #define FMC_PATT_ATTWAIT3_5 0x00002000U
4442 #define FMC_PATT_ATTWAIT3_6 0x00004000U
4443 #define FMC_PATT_ATTWAIT3_7 0x00008000U
4444 #define FMC_PATT_ATTHOLD3 0x00FF0000U
4445 #define FMC_PATT_ATTHOLD3_0 0x00010000U
4446 #define FMC_PATT_ATTHOLD3_1 0x00020000U
4447 #define FMC_PATT_ATTHOLD3_2 0x00040000U
4448 #define FMC_PATT_ATTHOLD3_3 0x00080000U
4449 #define FMC_PATT_ATTHOLD3_4 0x00100000U
4450 #define FMC_PATT_ATTHOLD3_5 0x00200000U
4451 #define FMC_PATT_ATTHOLD3_6 0x00400000U
4452 #define FMC_PATT_ATTHOLD3_7 0x00800000U
4453 #define FMC_PATT_ATTHIZ3 0xFF000000U
4454 #define FMC_PATT_ATTHIZ3_0 0x01000000U
4455 #define FMC_PATT_ATTHIZ3_1 0x02000000U
4456 #define FMC_PATT_ATTHIZ3_2 0x04000000U
4457 #define FMC_PATT_ATTHIZ3_3 0x08000000U
4458 #define FMC_PATT_ATTHIZ3_4 0x10000000U
4459 #define FMC_PATT_ATTHIZ3_5 0x20000000U
4460 #define FMC_PATT_ATTHIZ3_6 0x40000000U
4461 #define FMC_PATT_ATTHIZ3_7 0x80000000U
4463 /****************** Bit definition for FMC_ECCR register ******************/
4464 #define FMC_ECCR_ECC3 0xFFFFFFFFU
4466 /****************** Bit definition for FMC_SDCR1 register ******************/
4467 #define FMC_SDCR1_NC 0x00000003U
4468 #define FMC_SDCR1_NC_0 0x00000001U
4469 #define FMC_SDCR1_NC_1 0x00000002U
4470 #define FMC_SDCR1_NR 0x0000000CU
4471 #define FMC_SDCR1_NR_0 0x00000004U
4472 #define FMC_SDCR1_NR_1 0x00000008U
4473 #define FMC_SDCR1_MWID 0x00000030U
4474 #define FMC_SDCR1_MWID_0 0x00000010U
4475 #define FMC_SDCR1_MWID_1 0x00000020U
4476 #define FMC_SDCR1_NB 0x00000040U
4477 #define FMC_SDCR1_CAS 0x00000180U
4478 #define FMC_SDCR1_CAS_0 0x00000080U
4479 #define FMC_SDCR1_CAS_1 0x00000100U
4480 #define FMC_SDCR1_WP 0x00000200U
4481 #define FMC_SDCR1_SDCLK 0x00000C00U
4482 #define FMC_SDCR1_SDCLK_0 0x00000400U
4483 #define FMC_SDCR1_SDCLK_1 0x00000800U
4484 #define FMC_SDCR1_RBURST 0x00001000U
4485 #define FMC_SDCR1_RPIPE 0x00006000U
4486 #define FMC_SDCR1_RPIPE_0 0x00002000U
4487 #define FMC_SDCR1_RPIPE_1 0x00004000U
4489 /****************** Bit definition for FMC_SDCR2 register ******************/
4490 #define FMC_SDCR2_NC 0x00000003U
4491 #define FMC_SDCR2_NC_0 0x00000001U
4492 #define FMC_SDCR2_NC_1 0x00000002U
4493 #define FMC_SDCR2_NR 0x0000000CU
4494 #define FMC_SDCR2_NR_0 0x00000004U
4495 #define FMC_SDCR2_NR_1 0x00000008U
4496 #define FMC_SDCR2_MWID 0x00000030U
4497 #define FMC_SDCR2_MWID_0 0x00000010U
4498 #define FMC_SDCR2_MWID_1 0x00000020U
4499 #define FMC_SDCR2_NB 0x00000040U
4500 #define FMC_SDCR2_CAS 0x00000180U
4501 #define FMC_SDCR2_CAS_0 0x00000080U
4502 #define FMC_SDCR2_CAS_1 0x00000100U
4503 #define FMC_SDCR2_WP 0x00000200U
4504 #define FMC_SDCR2_SDCLK 0x00000C00U
4505 #define FMC_SDCR2_SDCLK_0 0x00000400U
4506 #define FMC_SDCR2_SDCLK_1 0x00000800U
4507 #define FMC_SDCR2_RBURST 0x00001000U
4508 #define FMC_SDCR2_RPIPE 0x00006000U
4509 #define FMC_SDCR2_RPIPE_0 0x00002000U
4510 #define FMC_SDCR2_RPIPE_1 0x00004000U
4512 /****************** Bit definition for FMC_SDTR1 register ******************/
4513 #define FMC_SDTR1_TMRD 0x0000000FU
4514 #define FMC_SDTR1_TMRD_0 0x00000001U
4515 #define FMC_SDTR1_TMRD_1 0x00000002U
4516 #define FMC_SDTR1_TMRD_2 0x00000004U
4517 #define FMC_SDTR1_TMRD_3 0x00000008U
4518 #define FMC_SDTR1_TXSR 0x000000F0U
4519 #define FMC_SDTR1_TXSR_0 0x00000010U
4520 #define FMC_SDTR1_TXSR_1 0x00000020U
4521 #define FMC_SDTR1_TXSR_2 0x00000040U
4522 #define FMC_SDTR1_TXSR_3 0x00000080U
4523 #define FMC_SDTR1_TRAS 0x00000F00U
4524 #define FMC_SDTR1_TRAS_0 0x00000100U
4525 #define FMC_SDTR1_TRAS_1 0x00000200U
4526 #define FMC_SDTR1_TRAS_2 0x00000400U
4527 #define FMC_SDTR1_TRAS_3 0x00000800U
4528 #define FMC_SDTR1_TRC 0x0000F000U
4529 #define FMC_SDTR1_TRC_0 0x00001000U
4530 #define FMC_SDTR1_TRC_1 0x00002000U
4531 #define FMC_SDTR1_TRC_2 0x00004000U
4532 #define FMC_SDTR1_TWR 0x000F0000U
4533 #define FMC_SDTR1_TWR_0 0x00010000U
4534 #define FMC_SDTR1_TWR_1 0x00020000U
4535 #define FMC_SDTR1_TWR_2 0x00040000U
4536 #define FMC_SDTR1_TRP 0x00F00000U
4537 #define FMC_SDTR1_TRP_0 0x00100000U
4538 #define FMC_SDTR1_TRP_1 0x00200000U
4539 #define FMC_SDTR1_TRP_2 0x00400000U
4540 #define FMC_SDTR1_TRCD 0x0F000000U
4541 #define FMC_SDTR1_TRCD_0 0x01000000U
4542 #define FMC_SDTR1_TRCD_1 0x02000000U
4543 #define FMC_SDTR1_TRCD_2 0x04000000U
4545 /****************** Bit definition for FMC_SDTR2 register ******************/
4546 #define FMC_SDTR2_TMRD 0x0000000FU
4547 #define FMC_SDTR2_TMRD_0 0x00000001U
4548 #define FMC_SDTR2_TMRD_1 0x00000002U
4549 #define FMC_SDTR2_TMRD_2 0x00000004U
4550 #define FMC_SDTR2_TMRD_3 0x00000008U
4551 #define FMC_SDTR2_TXSR 0x000000F0U
4552 #define FMC_SDTR2_TXSR_0 0x00000010U
4553 #define FMC_SDTR2_TXSR_1 0x00000020U
4554 #define FMC_SDTR2_TXSR_2 0x00000040U
4555 #define FMC_SDTR2_TXSR_3 0x00000080U
4556 #define FMC_SDTR2_TRAS 0x00000F00U
4557 #define FMC_SDTR2_TRAS_0 0x00000100U
4558 #define FMC_SDTR2_TRAS_1 0x00000200U
4559 #define FMC_SDTR2_TRAS_2 0x00000400U
4560 #define FMC_SDTR2_TRAS_3 0x00000800U
4561 #define FMC_SDTR2_TRC 0x0000F000U
4562 #define FMC_SDTR2_TRC_0 0x00001000U
4563 #define FMC_SDTR2_TRC_1 0x00002000U
4564 #define FMC_SDTR2_TRC_2 0x00004000U
4565 #define FMC_SDTR2_TWR 0x000F0000U
4566 #define FMC_SDTR2_TWR_0 0x00010000U
4567 #define FMC_SDTR2_TWR_1 0x00020000U
4568 #define FMC_SDTR2_TWR_2 0x00040000U
4569 #define FMC_SDTR2_TRP 0x00F00000U
4570 #define FMC_SDTR2_TRP_0 0x00100000U
4571 #define FMC_SDTR2_TRP_1 0x00200000U
4572 #define FMC_SDTR2_TRP_2 0x00400000U
4573 #define FMC_SDTR2_TRCD 0x0F000000U
4574 #define FMC_SDTR2_TRCD_0 0x01000000U
4575 #define FMC_SDTR2_TRCD_1 0x02000000U
4576 #define FMC_SDTR2_TRCD_2 0x04000000U
4578 /****************** Bit definition for FMC_SDCMR register ******************/
4579 #define FMC_SDCMR_MODE 0x00000007U
4580 #define FMC_SDCMR_MODE_0 0x00000001U
4581 #define FMC_SDCMR_MODE_1 0x00000002U
4582 #define FMC_SDCMR_MODE_2 0x00000003U
4583 #define FMC_SDCMR_CTB2 0x00000008U
4584 #define FMC_SDCMR_CTB1 0x00000010U
4585 #define FMC_SDCMR_NRFS 0x000001E0U
4586 #define FMC_SDCMR_NRFS_0 0x00000020U
4587 #define FMC_SDCMR_NRFS_1 0x00000040U
4588 #define FMC_SDCMR_NRFS_2 0x00000080U
4589 #define FMC_SDCMR_NRFS_3 0x00000100U
4590 #define FMC_SDCMR_MRD 0x003FFE00U
4592 /****************** Bit definition for FMC_SDRTR register ******************/
4593 #define FMC_SDRTR_CRE 0x00000001U
4594 #define FMC_SDRTR_COUNT 0x00003FFEU
4595 #define FMC_SDRTR_REIE 0x00004000U
4597 /****************** Bit definition for FMC_SDSR register ******************/
4598 #define FMC_SDSR_RE 0x00000001U
4599 #define FMC_SDSR_MODES1 0x00000006U
4600 #define FMC_SDSR_MODES1_0 0x00000002U
4601 #define FMC_SDSR_MODES1_1 0x00000004U
4602 #define FMC_SDSR_MODES2 0x00000018U
4603 #define FMC_SDSR_MODES2_0 0x00000008U
4604 #define FMC_SDSR_MODES2_1 0x00000010U
4605 #define FMC_SDSR_BUSY 0x00000020U
4607 /******************************************************************************/
4608 /* */
4609 /* General Purpose I/O */
4610 /* */
4611 /******************************************************************************/
4612 /****************** Bits definition for GPIO_MODER register *****************/
4613 #define GPIO_MODER_MODER0 0x00000003U
4614 #define GPIO_MODER_MODER0_0 0x00000001U
4615 #define GPIO_MODER_MODER0_1 0x00000002U
4616 #define GPIO_MODER_MODER1 0x0000000CU
4617 #define GPIO_MODER_MODER1_0 0x00000004U
4618 #define GPIO_MODER_MODER1_1 0x00000008U
4619 #define GPIO_MODER_MODER2 0x00000030U
4620 #define GPIO_MODER_MODER2_0 0x00000010U
4621 #define GPIO_MODER_MODER2_1 0x00000020U
4622 #define GPIO_MODER_MODER3 0x000000C0U
4623 #define GPIO_MODER_MODER3_0 0x00000040U
4624 #define GPIO_MODER_MODER3_1 0x00000080U
4625 #define GPIO_MODER_MODER4 0x00000300U
4626 #define GPIO_MODER_MODER4_0 0x00000100U
4627 #define GPIO_MODER_MODER4_1 0x00000200U
4628 #define GPIO_MODER_MODER5 0x00000C00U
4629 #define GPIO_MODER_MODER5_0 0x00000400U
4630 #define GPIO_MODER_MODER5_1 0x00000800U
4631 #define GPIO_MODER_MODER6 0x00003000U
4632 #define GPIO_MODER_MODER6_0 0x00001000U
4633 #define GPIO_MODER_MODER6_1 0x00002000U
4634 #define GPIO_MODER_MODER7 0x0000C000U
4635 #define GPIO_MODER_MODER7_0 0x00004000U
4636 #define GPIO_MODER_MODER7_1 0x00008000U
4637 #define GPIO_MODER_MODER8 0x00030000U
4638 #define GPIO_MODER_MODER8_0 0x00010000U
4639 #define GPIO_MODER_MODER8_1 0x00020000U
4640 #define GPIO_MODER_MODER9 0x000C0000U
4641 #define GPIO_MODER_MODER9_0 0x00040000U
4642 #define GPIO_MODER_MODER9_1 0x00080000U
4643 #define GPIO_MODER_MODER10 0x00300000U
4644 #define GPIO_MODER_MODER10_0 0x00100000U
4645 #define GPIO_MODER_MODER10_1 0x00200000U
4646 #define GPIO_MODER_MODER11 0x00C00000U
4647 #define GPIO_MODER_MODER11_0 0x00400000U
4648 #define GPIO_MODER_MODER11_1 0x00800000U
4649 #define GPIO_MODER_MODER12 0x03000000U
4650 #define GPIO_MODER_MODER12_0 0x01000000U
4651 #define GPIO_MODER_MODER12_1 0x02000000U
4652 #define GPIO_MODER_MODER13 0x0C000000U
4653 #define GPIO_MODER_MODER13_0 0x04000000U
4654 #define GPIO_MODER_MODER13_1 0x08000000U
4655 #define GPIO_MODER_MODER14 0x30000000U
4656 #define GPIO_MODER_MODER14_0 0x10000000U
4657 #define GPIO_MODER_MODER14_1 0x20000000U
4658 #define GPIO_MODER_MODER15 0xC0000000U
4659 #define GPIO_MODER_MODER15_0 0x40000000U
4660 #define GPIO_MODER_MODER15_1 0x80000000U
4661 
4662 /****************** Bits definition for GPIO_OTYPER register ****************/
4663 #define GPIO_OTYPER_OT_0 0x00000001U
4664 #define GPIO_OTYPER_OT_1 0x00000002U
4665 #define GPIO_OTYPER_OT_2 0x00000004U
4666 #define GPIO_OTYPER_OT_3 0x00000008U
4667 #define GPIO_OTYPER_OT_4 0x00000010U
4668 #define GPIO_OTYPER_OT_5 0x00000020U
4669 #define GPIO_OTYPER_OT_6 0x00000040U
4670 #define GPIO_OTYPER_OT_7 0x00000080U
4671 #define GPIO_OTYPER_OT_8 0x00000100U
4672 #define GPIO_OTYPER_OT_9 0x00000200U
4673 #define GPIO_OTYPER_OT_10 0x00000400U
4674 #define GPIO_OTYPER_OT_11 0x00000800U
4675 #define GPIO_OTYPER_OT_12 0x00001000U
4676 #define GPIO_OTYPER_OT_13 0x00002000U
4677 #define GPIO_OTYPER_OT_14 0x00004000U
4678 #define GPIO_OTYPER_OT_15 0x00008000U
4679 
4680 /****************** Bits definition for GPIO_OSPEEDR register ***************/
4681 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
4682 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
4683 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
4684 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
4685 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
4686 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
4687 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
4688 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
4689 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
4690 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
4691 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
4692 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
4693 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
4694 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
4695 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
4696 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
4697 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
4698 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
4699 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
4700 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
4701 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
4702 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
4703 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
4704 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
4705 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
4706 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
4707 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
4708 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
4709 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
4710 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
4711 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
4712 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
4713 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
4714 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
4715 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
4716 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
4717 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
4718 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
4719 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
4720 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
4721 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
4722 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
4723 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
4724 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
4725 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
4726 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
4727 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
4728 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
4729 
4730 /****************** Bits definition for GPIO_PUPDR register *****************/
4731 #define GPIO_PUPDR_PUPDR0 0x00000003U
4732 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
4733 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
4734 #define GPIO_PUPDR_PUPDR1 0x0000000CU
4735 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
4736 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
4737 #define GPIO_PUPDR_PUPDR2 0x00000030U
4738 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
4739 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
4740 #define GPIO_PUPDR_PUPDR3 0x000000C0U
4741 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
4742 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
4743 #define GPIO_PUPDR_PUPDR4 0x00000300U
4744 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
4745 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
4746 #define GPIO_PUPDR_PUPDR5 0x00000C00U
4747 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
4748 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
4749 #define GPIO_PUPDR_PUPDR6 0x00003000U
4750 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
4751 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
4752 #define GPIO_PUPDR_PUPDR7 0x0000C000U
4753 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
4754 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
4755 #define GPIO_PUPDR_PUPDR8 0x00030000U
4756 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
4757 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
4758 #define GPIO_PUPDR_PUPDR9 0x000C0000U
4759 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
4760 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
4761 #define GPIO_PUPDR_PUPDR10 0x00300000U
4762 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
4763 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
4764 #define GPIO_PUPDR_PUPDR11 0x00C00000U
4765 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
4766 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
4767 #define GPIO_PUPDR_PUPDR12 0x03000000U
4768 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
4769 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
4770 #define GPIO_PUPDR_PUPDR13 0x0C000000U
4771 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
4772 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
4773 #define GPIO_PUPDR_PUPDR14 0x30000000U
4774 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
4775 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
4776 #define GPIO_PUPDR_PUPDR15 0xC0000000U
4777 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
4778 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
4779 
4780 /****************** Bits definition for GPIO_IDR register *******************/
4781 #define GPIO_IDR_IDR_0 0x00000001U
4782 #define GPIO_IDR_IDR_1 0x00000002U
4783 #define GPIO_IDR_IDR_2 0x00000004U
4784 #define GPIO_IDR_IDR_3 0x00000008U
4785 #define GPIO_IDR_IDR_4 0x00000010U
4786 #define GPIO_IDR_IDR_5 0x00000020U
4787 #define GPIO_IDR_IDR_6 0x00000040U
4788 #define GPIO_IDR_IDR_7 0x00000080U
4789 #define GPIO_IDR_IDR_8 0x00000100U
4790 #define GPIO_IDR_IDR_9 0x00000200U
4791 #define GPIO_IDR_IDR_10 0x00000400U
4792 #define GPIO_IDR_IDR_11 0x00000800U
4793 #define GPIO_IDR_IDR_12 0x00001000U
4794 #define GPIO_IDR_IDR_13 0x00002000U
4795 #define GPIO_IDR_IDR_14 0x00004000U
4796 #define GPIO_IDR_IDR_15 0x00008000U
4797 
4798 /****************** Bits definition for GPIO_ODR register *******************/
4799 #define GPIO_ODR_ODR_0 0x00000001U
4800 #define GPIO_ODR_ODR_1 0x00000002U
4801 #define GPIO_ODR_ODR_2 0x00000004U
4802 #define GPIO_ODR_ODR_3 0x00000008U
4803 #define GPIO_ODR_ODR_4 0x00000010U
4804 #define GPIO_ODR_ODR_5 0x00000020U
4805 #define GPIO_ODR_ODR_6 0x00000040U
4806 #define GPIO_ODR_ODR_7 0x00000080U
4807 #define GPIO_ODR_ODR_8 0x00000100U
4808 #define GPIO_ODR_ODR_9 0x00000200U
4809 #define GPIO_ODR_ODR_10 0x00000400U
4810 #define GPIO_ODR_ODR_11 0x00000800U
4811 #define GPIO_ODR_ODR_12 0x00001000U
4812 #define GPIO_ODR_ODR_13 0x00002000U
4813 #define GPIO_ODR_ODR_14 0x00004000U
4814 #define GPIO_ODR_ODR_15 0x00008000U
4815 
4816 /****************** Bits definition for GPIO_BSRR register ******************/
4817 #define GPIO_BSRR_BS_0 0x00000001U
4818 #define GPIO_BSRR_BS_1 0x00000002U
4819 #define GPIO_BSRR_BS_2 0x00000004U
4820 #define GPIO_BSRR_BS_3 0x00000008U
4821 #define GPIO_BSRR_BS_4 0x00000010U
4822 #define GPIO_BSRR_BS_5 0x00000020U
4823 #define GPIO_BSRR_BS_6 0x00000040U
4824 #define GPIO_BSRR_BS_7 0x00000080U
4825 #define GPIO_BSRR_BS_8 0x00000100U
4826 #define GPIO_BSRR_BS_9 0x00000200U
4827 #define GPIO_BSRR_BS_10 0x00000400U
4828 #define GPIO_BSRR_BS_11 0x00000800U
4829 #define GPIO_BSRR_BS_12 0x00001000U
4830 #define GPIO_BSRR_BS_13 0x00002000U
4831 #define GPIO_BSRR_BS_14 0x00004000U
4832 #define GPIO_BSRR_BS_15 0x00008000U
4833 #define GPIO_BSRR_BR_0 0x00010000U
4834 #define GPIO_BSRR_BR_1 0x00020000U
4835 #define GPIO_BSRR_BR_2 0x00040000U
4836 #define GPIO_BSRR_BR_3 0x00080000U
4837 #define GPIO_BSRR_BR_4 0x00100000U
4838 #define GPIO_BSRR_BR_5 0x00200000U
4839 #define GPIO_BSRR_BR_6 0x00400000U
4840 #define GPIO_BSRR_BR_7 0x00800000U
4841 #define GPIO_BSRR_BR_8 0x01000000U
4842 #define GPIO_BSRR_BR_9 0x02000000U
4843 #define GPIO_BSRR_BR_10 0x04000000U
4844 #define GPIO_BSRR_BR_11 0x08000000U
4845 #define GPIO_BSRR_BR_12 0x10000000U
4846 #define GPIO_BSRR_BR_13 0x20000000U
4847 #define GPIO_BSRR_BR_14 0x40000000U
4848 #define GPIO_BSRR_BR_15 0x80000000U
4849 
4850 /****************** Bit definition for GPIO_LCKR register *********************/
4851 #define GPIO_LCKR_LCK0 0x00000001U
4852 #define GPIO_LCKR_LCK1 0x00000002U
4853 #define GPIO_LCKR_LCK2 0x00000004U
4854 #define GPIO_LCKR_LCK3 0x00000008U
4855 #define GPIO_LCKR_LCK4 0x00000010U
4856 #define GPIO_LCKR_LCK5 0x00000020U
4857 #define GPIO_LCKR_LCK6 0x00000040U
4858 #define GPIO_LCKR_LCK7 0x00000080U
4859 #define GPIO_LCKR_LCK8 0x00000100U
4860 #define GPIO_LCKR_LCK9 0x00000200U
4861 #define GPIO_LCKR_LCK10 0x00000400U
4862 #define GPIO_LCKR_LCK11 0x00000800U
4863 #define GPIO_LCKR_LCK12 0x00001000U
4864 #define GPIO_LCKR_LCK13 0x00002000U
4865 #define GPIO_LCKR_LCK14 0x00004000U
4866 #define GPIO_LCKR_LCK15 0x00008000U
4867 #define GPIO_LCKR_LCKK 0x00010000U
4868 
4869 
4870 /******************************************************************************/
4871 /* */
4872 /* Inter-integrated Circuit Interface (I2C) */
4873 /* */
4874 /******************************************************************************/
4875 /******************* Bit definition for I2C_CR1 register *******************/
4876 #define I2C_CR1_PE 0x00000001U
4877 #define I2C_CR1_TXIE 0x00000002U
4878 #define I2C_CR1_RXIE 0x00000004U
4879 #define I2C_CR1_ADDRIE 0x00000008U
4880 #define I2C_CR1_NACKIE 0x00000010U
4881 #define I2C_CR1_STOPIE 0x00000020U
4882 #define I2C_CR1_TCIE 0x00000040U
4883 #define I2C_CR1_ERRIE 0x00000080U
4884 #define I2C_CR1_DNF 0x00000F00U
4885 #define I2C_CR1_ANFOFF 0x00001000U
4886 #define I2C_CR1_TXDMAEN 0x00004000U
4887 #define I2C_CR1_RXDMAEN 0x00008000U
4888 #define I2C_CR1_SBC 0x00010000U
4889 #define I2C_CR1_NOSTRETCH 0x00020000U
4890 #define I2C_CR1_GCEN 0x00080000U
4891 #define I2C_CR1_SMBHEN 0x00100000U
4892 #define I2C_CR1_SMBDEN 0x00200000U
4893 #define I2C_CR1_ALERTEN 0x00400000U
4894 #define I2C_CR1_PECEN 0x00800000U
4896 /* Legacy define */
4897 #define I2C_CR1_DFN I2C_CR1_DNF
4899 /****************** Bit definition for I2C_CR2 register ********************/
4900 #define I2C_CR2_SADD 0x000003FFU
4901 #define I2C_CR2_RD_WRN 0x00000400U
4902 #define I2C_CR2_ADD10 0x00000800U
4903 #define I2C_CR2_HEAD10R 0x00001000U
4904 #define I2C_CR2_START 0x00002000U
4905 #define I2C_CR2_STOP 0x00004000U
4906 #define I2C_CR2_NACK 0x00008000U
4907 #define I2C_CR2_NBYTES 0x00FF0000U
4908 #define I2C_CR2_RELOAD 0x01000000U
4909 #define I2C_CR2_AUTOEND 0x02000000U
4910 #define I2C_CR2_PECBYTE 0x04000000U
4912 /******************* Bit definition for I2C_OAR1 register ******************/
4913 #define I2C_OAR1_OA1 0x000003FFU
4914 #define I2C_OAR1_OA1MODE 0x00000400U
4915 #define I2C_OAR1_OA1EN 0x00008000U
4917 /******************* Bit definition for I2C_OAR2 register ******************/
4918 #define I2C_OAR2_OA2 0x000000FEU
4919 #define I2C_OAR2_OA2MSK 0x00000700U
4920 #define I2C_OAR2_OA2NOMASK 0x00000000U
4921 #define I2C_OAR2_OA2MASK01 0x00000100U
4922 #define I2C_OAR2_OA2MASK02 0x00000200U
4923 #define I2C_OAR2_OA2MASK03 0x00000300U
4924 #define I2C_OAR2_OA2MASK04 0x00000400U
4925 #define I2C_OAR2_OA2MASK05 0x00000500U
4926 #define I2C_OAR2_OA2MASK06 0x00000600U
4927 #define I2C_OAR2_OA2MASK07 0x00000700U
4928 #define I2C_OAR2_OA2EN 0x00008000U
4930 /******************* Bit definition for I2C_TIMINGR register *******************/
4931 #define I2C_TIMINGR_SCLL 0x000000FFU
4932 #define I2C_TIMINGR_SCLH 0x0000FF00U
4933 #define I2C_TIMINGR_SDADEL 0x000F0000U
4934 #define I2C_TIMINGR_SCLDEL 0x00F00000U
4935 #define I2C_TIMINGR_PRESC 0xF0000000U
4937 /******************* Bit definition for I2C_TIMEOUTR register *******************/
4938 #define I2C_TIMEOUTR_TIMEOUTA 0x00000FFFU
4939 #define I2C_TIMEOUTR_TIDLE 0x00001000U
4940 #define I2C_TIMEOUTR_TIMOUTEN 0x00008000U
4941 #define I2C_TIMEOUTR_TIMEOUTB 0x0FFF0000U
4942 #define I2C_TIMEOUTR_TEXTEN 0x80000000U
4944 /****************** Bit definition for I2C_ISR register *********************/
4945 #define I2C_ISR_TXE 0x00000001U
4946 #define I2C_ISR_TXIS 0x00000002U
4947 #define I2C_ISR_RXNE 0x00000004U
4948 #define I2C_ISR_ADDR 0x00000008U
4949 #define I2C_ISR_NACKF 0x00000010U
4950 #define I2C_ISR_STOPF 0x00000020U
4951 #define I2C_ISR_TC 0x00000040U
4952 #define I2C_ISR_TCR 0x00000080U
4953 #define I2C_ISR_BERR 0x00000100U
4954 #define I2C_ISR_ARLO 0x00000200U
4955 #define I2C_ISR_OVR 0x00000400U
4956 #define I2C_ISR_PECERR 0x00000800U
4957 #define I2C_ISR_TIMEOUT 0x00001000U
4958 #define I2C_ISR_ALERT 0x00002000U
4959 #define I2C_ISR_BUSY 0x00008000U
4960 #define I2C_ISR_DIR 0x00010000U
4961 #define I2C_ISR_ADDCODE 0x00FE0000U
4963 /****************** Bit definition for I2C_ICR register *********************/
4964 #define I2C_ICR_ADDRCF 0x00000008U
4965 #define I2C_ICR_NACKCF 0x00000010U
4966 #define I2C_ICR_STOPCF 0x00000020U
4967 #define I2C_ICR_BERRCF 0x00000100U
4968 #define I2C_ICR_ARLOCF 0x00000200U
4969 #define I2C_ICR_OVRCF 0x00000400U
4970 #define I2C_ICR_PECCF 0x00000800U
4971 #define I2C_ICR_TIMOUTCF 0x00001000U
4972 #define I2C_ICR_ALERTCF 0x00002000U
4974 /****************** Bit definition for I2C_PECR register *********************/
4975 #define I2C_PECR_PEC 0x000000FFU
4977 /****************** Bit definition for I2C_RXDR register *********************/
4978 #define I2C_RXDR_RXDATA 0x000000FFU
4980 /****************** Bit definition for I2C_TXDR register *********************/
4981 #define I2C_TXDR_TXDATA 0x000000FFU
4984 /******************************************************************************/
4985 /* */
4986 /* Independent WATCHDOG */
4987 /* */
4988 /******************************************************************************/
4989 /******************* Bit definition for IWDG_KR register ********************/
4990 #define IWDG_KR_KEY 0xFFFFU
4992 /******************* Bit definition for IWDG_PR register ********************/
4993 #define IWDG_PR_PR 0x07U
4994 #define IWDG_PR_PR_0 0x01U
4995 #define IWDG_PR_PR_1 0x02U
4996 #define IWDG_PR_PR_2 0x04U
4998 /******************* Bit definition for IWDG_RLR register *******************/
4999 #define IWDG_RLR_RL 0x0FFFU
5001 /******************* Bit definition for IWDG_SR register ********************/
5002 #define IWDG_SR_PVU 0x01U
5003 #define IWDG_SR_RVU 0x02U
5004 #define IWDG_SR_WVU 0x04U
5006 /******************* Bit definition for IWDG_KR register ********************/
5007 #define IWDG_WINR_WIN 0x0FFFU
5009 /******************************************************************************/
5010 /* */
5011 /* LCD-TFT Display Controller (LTDC) */
5012 /* */
5013 /******************************************************************************/
5014 
5015 /******************** Bit definition for LTDC_SSCR register *****************/
5016 
5017 #define LTDC_SSCR_VSH 0x000007FFU
5018 #define LTDC_SSCR_HSW 0x0FFF0000U
5020 /******************** Bit definition for LTDC_BPCR register *****************/
5021 
5022 #define LTDC_BPCR_AVBP 0x000007FFU
5023 #define LTDC_BPCR_AHBP 0x0FFF0000U
5025 /******************** Bit definition for LTDC_AWCR register *****************/
5026 
5027 #define LTDC_AWCR_AAH 0x000007FFU
5028 #define LTDC_AWCR_AAW 0x0FFF0000U
5030 /******************** Bit definition for LTDC_TWCR register *****************/
5031 
5032 #define LTDC_TWCR_TOTALH 0x000007FFU
5033 #define LTDC_TWCR_TOTALW 0x0FFF0000U
5035 /******************** Bit definition for LTDC_GCR register ******************/
5036 
5037 #define LTDC_GCR_LTDCEN 0x00000001U
5038 #define LTDC_GCR_DBW 0x00000070U
5039 #define LTDC_GCR_DGW 0x00000700U
5040 #define LTDC_GCR_DRW 0x00007000U
5041 #define LTDC_GCR_DEN 0x00010000U
5042 #define LTDC_GCR_PCPOL 0x10000000U
5043 #define LTDC_GCR_DEPOL 0x20000000U
5044 #define LTDC_GCR_VSPOL 0x40000000U
5045 #define LTDC_GCR_HSPOL 0x80000000U
5047 /* Legacy define */
5048 #define LTDC_GCR_DTEN LTDC_GCR_DEN
5049 
5050 /******************** Bit definition for LTDC_SRCR register *****************/
5051 
5052 #define LTDC_SRCR_IMR 0x00000001U
5053 #define LTDC_SRCR_VBR 0x00000002U
5055 /******************** Bit definition for LTDC_BCCR register *****************/
5056 
5057 #define LTDC_BCCR_BCBLUE 0x000000FFU
5058 #define LTDC_BCCR_BCGREEN 0x0000FF00U
5059 #define LTDC_BCCR_BCRED 0x00FF0000U
5061 /******************** Bit definition for LTDC_IER register ******************/
5062 
5063 #define LTDC_IER_LIE 0x00000001U
5064 #define LTDC_IER_FUIE 0x00000002U
5065 #define LTDC_IER_TERRIE 0x00000004U
5066 #define LTDC_IER_RRIE 0x00000008U
5068 /******************** Bit definition for LTDC_ISR register ******************/
5069 
5070 #define LTDC_ISR_LIF 0x00000001U
5071 #define LTDC_ISR_FUIF 0x00000002U
5072 #define LTDC_ISR_TERRIF 0x00000004U
5073 #define LTDC_ISR_RRIF 0x00000008U
5075 /******************** Bit definition for LTDC_ICR register ******************/
5076 
5077 #define LTDC_ICR_CLIF 0x00000001U
5078 #define LTDC_ICR_CFUIF 0x00000002U
5079 #define LTDC_ICR_CTERRIF 0x00000004U
5080 #define LTDC_ICR_CRRIF 0x00000008U
5082 /******************** Bit definition for LTDC_LIPCR register ****************/
5083 
5084 #define LTDC_LIPCR_LIPOS 0x000007FFU
5086 /******************** Bit definition for LTDC_CPSR register *****************/
5087 
5088 #define LTDC_CPSR_CYPOS 0x0000FFFFU
5089 #define LTDC_CPSR_CXPOS 0xFFFF0000U
5091 /******************** Bit definition for LTDC_CDSR register *****************/
5092 
5093 #define LTDC_CDSR_VDES 0x00000001U
5094 #define LTDC_CDSR_HDES 0x00000002U
5095 #define LTDC_CDSR_VSYNCS 0x00000004U
5096 #define LTDC_CDSR_HSYNCS 0x00000008U
5098 /******************** Bit definition for LTDC_LxCR register *****************/
5099 
5100 #define LTDC_LxCR_LEN 0x00000001U
5101 #define LTDC_LxCR_COLKEN 0x00000002U
5102 #define LTDC_LxCR_CLUTEN 0x00000010U
5104 /******************** Bit definition for LTDC_LxWHPCR register **************/
5105 
5106 #define LTDC_LxWHPCR_WHSTPOS 0x00000FFFU
5107 #define LTDC_LxWHPCR_WHSPPOS 0xFFFF0000U
5109 /******************** Bit definition for LTDC_LxWVPCR register **************/
5110 
5111 #define LTDC_LxWVPCR_WVSTPOS 0x00000FFFU
5112 #define LTDC_LxWVPCR_WVSPPOS 0xFFFF0000U
5114 /******************** Bit definition for LTDC_LxCKCR register ***************/
5115 
5116 #define LTDC_LxCKCR_CKBLUE 0x000000FFU
5117 #define LTDC_LxCKCR_CKGREEN 0x0000FF00U
5118 #define LTDC_LxCKCR_CKRED 0x00FF0000U
5120 /******************** Bit definition for LTDC_LxPFCR register ***************/
5121 
5122 #define LTDC_LxPFCR_PF 0x00000007U
5124 /******************** Bit definition for LTDC_LxCACR register ***************/
5125 
5126 #define LTDC_LxCACR_CONSTA 0x000000FFU
5128 /******************** Bit definition for LTDC_LxDCCR register ***************/
5129 
5130 #define LTDC_LxDCCR_DCBLUE 0x000000FFU
5131 #define LTDC_LxDCCR_DCGREEN 0x0000FF00U
5132 #define LTDC_LxDCCR_DCRED 0x00FF0000U
5133 #define LTDC_LxDCCR_DCALPHA 0xFF000000U
5135 /******************** Bit definition for LTDC_LxBFCR register ***************/
5136 
5137 #define LTDC_LxBFCR_BF2 0x00000007U
5138 #define LTDC_LxBFCR_BF1 0x00000700U
5140 /******************** Bit definition for LTDC_LxCFBAR register **************/
5141 
5142 #define LTDC_LxCFBAR_CFBADD 0xFFFFFFFFU
5144 /******************** Bit definition for LTDC_LxCFBLR register **************/
5145 
5146 #define LTDC_LxCFBLR_CFBLL 0x00001FFFU
5147 #define LTDC_LxCFBLR_CFBP 0x1FFF0000U
5149 /******************** Bit definition for LTDC_LxCFBLNR register *************/
5150 
5151 #define LTDC_LxCFBLNR_CFBLNBR 0x000007FFU
5153 /******************** Bit definition for LTDC_LxCLUTWR register *************/
5154 
5155 #define LTDC_LxCLUTWR_BLUE 0x000000FFU
5156 #define LTDC_LxCLUTWR_GREEN 0x0000FF00U
5157 #define LTDC_LxCLUTWR_RED 0x00FF0000U
5158 #define LTDC_LxCLUTWR_CLUTADD 0xFF000000U
5160 /******************************************************************************/
5161 /* */
5162 /* Power Control */
5163 /* */
5164 /******************************************************************************/
5165 /******************** Bit definition for PWR_CR1 register ********************/
5166 #define PWR_CR1_LPDS 0x00000001U
5167 #define PWR_CR1_PDDS 0x00000002U
5168 #define PWR_CR1_CSBF 0x00000008U
5169 #define PWR_CR1_PVDE 0x00000010U
5170 #define PWR_CR1_PLS 0x000000E0U
5171 #define PWR_CR1_PLS_0 0x00000020U
5172 #define PWR_CR1_PLS_1 0x00000040U
5173 #define PWR_CR1_PLS_2 0x00000080U
5176 #define PWR_CR1_PLS_LEV0 0x00000000U
5177 #define PWR_CR1_PLS_LEV1 0x00000020U
5178 #define PWR_CR1_PLS_LEV2 0x00000040U
5179 #define PWR_CR1_PLS_LEV3 0x00000060U
5180 #define PWR_CR1_PLS_LEV4 0x00000080U
5181 #define PWR_CR1_PLS_LEV5 0x000000A0U
5182 #define PWR_CR1_PLS_LEV6 0x000000C0U
5183 #define PWR_CR1_PLS_LEV7 0x000000E0U
5184 #define PWR_CR1_DBP 0x00000100U
5185 #define PWR_CR1_FPDS 0x00000200U
5186 #define PWR_CR1_LPUDS 0x00000400U
5187 #define PWR_CR1_MRUDS 0x00000800U
5188 #define PWR_CR1_ADCDC1 0x00002000U
5189 #define PWR_CR1_VOS 0x0000C000U
5190 #define PWR_CR1_VOS_0 0x00004000U
5191 #define PWR_CR1_VOS_1 0x00008000U
5192 #define PWR_CR1_ODEN 0x00010000U
5193 #define PWR_CR1_ODSWEN 0x00020000U
5194 #define PWR_CR1_UDEN 0x000C0000U
5195 #define PWR_CR1_UDEN_0 0x00040000U
5196 #define PWR_CR1_UDEN_1 0x00080000U
5198 /******************* Bit definition for PWR_CSR1 register ********************/
5199 #define PWR_CSR1_WUIF 0x00000001U
5200 #define PWR_CSR1_SBF 0x00000002U
5201 #define PWR_CSR1_PVDO 0x00000004U
5202 #define PWR_CSR1_BRR 0x00000008U
5203 #define PWR_CSR1_EIWUP 0x00000100U
5204 #define PWR_CSR1_BRE 0x00000200U
5205 #define PWR_CSR1_VOSRDY 0x00004000U
5206 #define PWR_CSR1_ODRDY 0x00010000U
5207 #define PWR_CSR1_ODSWRDY 0x00020000U
5208 #define PWR_CSR1_UDRDY 0x000C0000U
5210 /* Legacy define */
5211 #define PWR_CSR1_UDSWRDY PWR_CSR1_UDRDY
5212 
5213 /******************** Bit definition for PWR_CR2 register ********************/
5214 #define PWR_CR2_CWUPF1 0x00000001U
5215 #define PWR_CR2_CWUPF2 0x00000002U
5216 #define PWR_CR2_CWUPF3 0x00000004U
5217 #define PWR_CR2_CWUPF4 0x00000008U
5218 #define PWR_CR2_CWUPF5 0x00000010U
5219 #define PWR_CR2_CWUPF6 0x00000020U
5220 #define PWR_CR2_WUPP1 0x00000100U
5221 #define PWR_CR2_WUPP2 0x00000200U
5222 #define PWR_CR2_WUPP3 0x00000400U
5223 #define PWR_CR2_WUPP4 0x00000800U
5224 #define PWR_CR2_WUPP5 0x00001000U
5225 #define PWR_CR2_WUPP6 0x00002000U
5227 /******************* Bit definition for PWR_CSR2 register ********************/
5228 #define PWR_CSR2_WUPF1 0x00000001U
5229 #define PWR_CSR2_WUPF2 0x00000002U
5230 #define PWR_CSR2_WUPF3 0x00000004U
5231 #define PWR_CSR2_WUPF4 0x00000008U
5232 #define PWR_CSR2_WUPF5 0x00000010U
5233 #define PWR_CSR2_WUPF6 0x00000020U
5234 #define PWR_CSR2_EWUP1 0x00000100U
5235 #define PWR_CSR2_EWUP2 0x00000200U
5236 #define PWR_CSR2_EWUP3 0x00000400U
5237 #define PWR_CSR2_EWUP4 0x00000800U
5238 #define PWR_CSR2_EWUP5 0x00001000U
5239 #define PWR_CSR2_EWUP6 0x00002000U
5241 /******************************************************************************/
5242 /* */
5243 /* QUADSPI */
5244 /* */
5245 /******************************************************************************/
5246 /* QUADSPI IP version */
5247 #define QSPI1_V1_0
5248 /***************** Bit definition for QUADSPI_CR register *******************/
5249 #define QUADSPI_CR_EN 0x00000001U
5250 #define QUADSPI_CR_ABORT 0x00000002U
5251 #define QUADSPI_CR_DMAEN 0x00000004U
5252 #define QUADSPI_CR_TCEN 0x00000008U
5253 #define QUADSPI_CR_SSHIFT 0x00000010U
5254 #define QUADSPI_CR_DFM 0x00000040U
5255 #define QUADSPI_CR_FSEL 0x00000080U
5256 #define QUADSPI_CR_FTHRES 0x00001F00U
5257 #define QUADSPI_CR_FTHRES_0 0x00000100U
5258 #define QUADSPI_CR_FTHRES_1 0x00000200U
5259 #define QUADSPI_CR_FTHRES_2 0x00000400U
5260 #define QUADSPI_CR_FTHRES_3 0x00000800U
5261 #define QUADSPI_CR_FTHRES_4 0x00001000U
5262 #define QUADSPI_CR_TEIE 0x00010000U
5263 #define QUADSPI_CR_TCIE 0x00020000U
5264 #define QUADSPI_CR_FTIE 0x00040000U
5265 #define QUADSPI_CR_SMIE 0x00080000U
5266 #define QUADSPI_CR_TOIE 0x00100000U
5267 #define QUADSPI_CR_APMS 0x00400000U
5268 #define QUADSPI_CR_PMM 0x00800000U
5269 #define QUADSPI_CR_PRESCALER 0xFF000000U
5270 #define QUADSPI_CR_PRESCALER_0 0x01000000U
5271 #define QUADSPI_CR_PRESCALER_1 0x02000000U
5272 #define QUADSPI_CR_PRESCALER_2 0x04000000U
5273 #define QUADSPI_CR_PRESCALER_3 0x08000000U
5274 #define QUADSPI_CR_PRESCALER_4 0x10000000U
5275 #define QUADSPI_CR_PRESCALER_5 0x20000000U
5276 #define QUADSPI_CR_PRESCALER_6 0x40000000U
5277 #define QUADSPI_CR_PRESCALER_7 0x80000000U
5279 /***************** Bit definition for QUADSPI_DCR register ******************/
5280 #define QUADSPI_DCR_CKMODE 0x00000001U
5281 #define QUADSPI_DCR_CSHT 0x00000700U
5282 #define QUADSPI_DCR_CSHT_0 0x00000100U
5283 #define QUADSPI_DCR_CSHT_1 0x00000200U
5284 #define QUADSPI_DCR_CSHT_2 0x00000400U
5285 #define QUADSPI_DCR_FSIZE 0x001F0000U
5286 #define QUADSPI_DCR_FSIZE_0 0x00010000U
5287 #define QUADSPI_DCR_FSIZE_1 0x00020000U
5288 #define QUADSPI_DCR_FSIZE_2 0x00040000U
5289 #define QUADSPI_DCR_FSIZE_3 0x00080000U
5290 #define QUADSPI_DCR_FSIZE_4 0x00100000U
5292 /****************** Bit definition for QUADSPI_SR register *******************/
5293 #define QUADSPI_SR_TEF 0x00000001U
5294 #define QUADSPI_SR_TCF 0x00000002U
5295 #define QUADSPI_SR_FTF 0x00000004U
5296 #define QUADSPI_SR_SMF 0x00000008U
5297 #define QUADSPI_SR_TOF 0x00000010U
5298 #define QUADSPI_SR_BUSY 0x00000020U
5299 #define QUADSPI_SR_FLEVEL 0x00001F00U
5300 #define QUADSPI_SR_FLEVEL_0 0x00000100U
5301 #define QUADSPI_SR_FLEVEL_1 0x00000200U
5302 #define QUADSPI_SR_FLEVEL_2 0x00000400U
5303 #define QUADSPI_SR_FLEVEL_3 0x00000800U
5304 #define QUADSPI_SR_FLEVEL_4 0x00001000U
5306 /****************** Bit definition for QUADSPI_FCR register ******************/
5307 #define QUADSPI_FCR_CTEF 0x00000001U
5308 #define QUADSPI_FCR_CTCF 0x00000002U
5309 #define QUADSPI_FCR_CSMF 0x00000008U
5310 #define QUADSPI_FCR_CTOF 0x00000010U
5312 /****************** Bit definition for QUADSPI_DLR register ******************/
5313 #define QUADSPI_DLR_DL 0xFFFFFFFFU
5315 /****************** Bit definition for QUADSPI_CCR register ******************/
5316 #define QUADSPI_CCR_INSTRUCTION 0x000000FFU
5317 #define QUADSPI_CCR_INSTRUCTION_0 0x00000001U
5318 #define QUADSPI_CCR_INSTRUCTION_1 0x00000002U
5319 #define QUADSPI_CCR_INSTRUCTION_2 0x00000004U
5320 #define QUADSPI_CCR_INSTRUCTION_3 0x00000008U
5321 #define QUADSPI_CCR_INSTRUCTION_4 0x00000010U
5322 #define QUADSPI_CCR_INSTRUCTION_5 0x00000020U
5323 #define QUADSPI_CCR_INSTRUCTION_6 0x00000040U
5324 #define QUADSPI_CCR_INSTRUCTION_7 0x00000080U
5325 #define QUADSPI_CCR_IMODE 0x00000300U
5326 #define QUADSPI_CCR_IMODE_0 0x00000100U
5327 #define QUADSPI_CCR_IMODE_1 0x00000200U
5328 #define QUADSPI_CCR_ADMODE 0x00000C00U
5329 #define QUADSPI_CCR_ADMODE_0 0x00000400U
5330 #define QUADSPI_CCR_ADMODE_1 0x00000800U
5331 #define QUADSPI_CCR_ADSIZE 0x00003000U
5332 #define QUADSPI_CCR_ADSIZE_0 0x00001000U
5333 #define QUADSPI_CCR_ADSIZE_1 0x00002000U
5334 #define QUADSPI_CCR_ABMODE 0x0000C000U
5335 #define QUADSPI_CCR_ABMODE_0 0x00004000U
5336 #define QUADSPI_CCR_ABMODE_1 0x00008000U
5337 #define QUADSPI_CCR_ABSIZE 0x00030000U
5338 #define QUADSPI_CCR_ABSIZE_0 0x00010000U
5339 #define QUADSPI_CCR_ABSIZE_1 0x00020000U
5340 #define QUADSPI_CCR_DCYC 0x007C0000U
5341 #define QUADSPI_CCR_DCYC_0 0x00040000U
5342 #define QUADSPI_CCR_DCYC_1 0x00080000U
5343 #define QUADSPI_CCR_DCYC_2 0x00100000U
5344 #define QUADSPI_CCR_DCYC_3 0x00200000U
5345 #define QUADSPI_CCR_DCYC_4 0x00400000U
5346 #define QUADSPI_CCR_DMODE 0x03000000U
5347 #define QUADSPI_CCR_DMODE_0 0x01000000U
5348 #define QUADSPI_CCR_DMODE_1 0x02000000U
5349 #define QUADSPI_CCR_FMODE 0x0C000000U
5350 #define QUADSPI_CCR_FMODE_0 0x04000000U
5351 #define QUADSPI_CCR_FMODE_1 0x08000000U
5352 #define QUADSPI_CCR_SIOO 0x10000000U
5353 #define QUADSPI_CCR_DHHC 0x40000000U
5354 #define QUADSPI_CCR_DDRM 0x80000000U
5355 /****************** Bit definition for QUADSPI_AR register *******************/
5356 #define QUADSPI_AR_ADDRESS 0xFFFFFFFFU
5358 /****************** Bit definition for QUADSPI_ABR register ******************/
5359 #define QUADSPI_ABR_ALTERNATE 0xFFFFFFFFU
5361 /****************** Bit definition for QUADSPI_DR register *******************/
5362 #define QUADSPI_DR_DATA 0xFFFFFFFFU
5364 /****************** Bit definition for QUADSPI_PSMKR register ****************/
5365 #define QUADSPI_PSMKR_MASK 0xFFFFFFFFU
5367 /****************** Bit definition for QUADSPI_PSMAR register ****************/
5368 #define QUADSPI_PSMAR_MATCH 0xFFFFFFFFU
5370 /****************** Bit definition for QUADSPI_PIR register *****************/
5371 #define QUADSPI_PIR_INTERVAL 0x0000FFFFU
5373 /****************** Bit definition for QUADSPI_LPTR register *****************/
5374 #define QUADSPI_LPTR_TIMEOUT 0x0000FFFFU
5376 /******************************************************************************/
5377 /* */
5378 /* Reset and Clock Control */
5379 /* */
5380 /******************************************************************************/
5381 /******************** Bit definition for RCC_CR register ********************/
5382 #define RCC_CR_HSION 0x00000001U
5383 #define RCC_CR_HSIRDY 0x00000002U
5384 #define RCC_CR_HSITRIM 0x000000F8U
5385 #define RCC_CR_HSITRIM_0 0x00000008U
5386 #define RCC_CR_HSITRIM_1 0x00000010U
5387 #define RCC_CR_HSITRIM_2 0x00000020U
5388 #define RCC_CR_HSITRIM_3 0x00000040U
5389 #define RCC_CR_HSITRIM_4 0x00000080U
5390 #define RCC_CR_HSICAL 0x0000FF00U
5391 #define RCC_CR_HSICAL_0 0x00000100U
5392 #define RCC_CR_HSICAL_1 0x00000200U
5393 #define RCC_CR_HSICAL_2 0x00000400U
5394 #define RCC_CR_HSICAL_3 0x00000800U
5395 #define RCC_CR_HSICAL_4 0x00001000U
5396 #define RCC_CR_HSICAL_5 0x00002000U
5397 #define RCC_CR_HSICAL_6 0x00004000U
5398 #define RCC_CR_HSICAL_7 0x00008000U
5399 #define RCC_CR_HSEON 0x00010000U
5400 #define RCC_CR_HSERDY 0x00020000U
5401 #define RCC_CR_HSEBYP 0x00040000U
5402 #define RCC_CR_CSSON 0x00080000U
5403 #define RCC_CR_PLLON 0x01000000U
5404 #define RCC_CR_PLLRDY 0x02000000U
5405 #define RCC_CR_PLLI2SON 0x04000000U
5406 #define RCC_CR_PLLI2SRDY 0x08000000U
5407 #define RCC_CR_PLLSAION 0x10000000U
5408 #define RCC_CR_PLLSAIRDY 0x20000000U
5409 
5410 /******************** Bit definition for RCC_PLLCFGR register ***************/
5411 #define RCC_PLLCFGR_PLLM 0x0000003FU
5412 #define RCC_PLLCFGR_PLLM_0 0x00000001U
5413 #define RCC_PLLCFGR_PLLM_1 0x00000002U
5414 #define RCC_PLLCFGR_PLLM_2 0x00000004U
5415 #define RCC_PLLCFGR_PLLM_3 0x00000008U
5416 #define RCC_PLLCFGR_PLLM_4 0x00000010U
5417 #define RCC_PLLCFGR_PLLM_5 0x00000020U
5418 #define RCC_PLLCFGR_PLLN 0x00007FC0U
5419 #define RCC_PLLCFGR_PLLN_0 0x00000040U
5420 #define RCC_PLLCFGR_PLLN_1 0x00000080U
5421 #define RCC_PLLCFGR_PLLN_2 0x00000100U
5422 #define RCC_PLLCFGR_PLLN_3 0x00000200U
5423 #define RCC_PLLCFGR_PLLN_4 0x00000400U
5424 #define RCC_PLLCFGR_PLLN_5 0x00000800U
5425 #define RCC_PLLCFGR_PLLN_6 0x00001000U
5426 #define RCC_PLLCFGR_PLLN_7 0x00002000U
5427 #define RCC_PLLCFGR_PLLN_8 0x00004000U
5428 #define RCC_PLLCFGR_PLLP 0x00030000U
5429 #define RCC_PLLCFGR_PLLP_0 0x00010000U
5430 #define RCC_PLLCFGR_PLLP_1 0x00020000U
5431 #define RCC_PLLCFGR_PLLSRC 0x00400000U
5432 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
5433 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
5434 #define RCC_PLLCFGR_PLLQ 0x0F000000U
5435 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
5436 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
5437 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
5438 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
5439 
5440 
5441 /******************** Bit definition for RCC_CFGR register ******************/
5443 #define RCC_CFGR_SW 0x00000003U
5444 #define RCC_CFGR_SW_0 0x00000001U
5445 #define RCC_CFGR_SW_1 0x00000002U
5446 #define RCC_CFGR_SW_HSI 0x00000000U
5447 #define RCC_CFGR_SW_HSE 0x00000001U
5448 #define RCC_CFGR_SW_PLL 0x00000002U
5451 #define RCC_CFGR_SWS 0x0000000CU
5452 #define RCC_CFGR_SWS_0 0x00000004U
5453 #define RCC_CFGR_SWS_1 0x00000008U
5454 #define RCC_CFGR_SWS_HSI 0x00000000U
5455 #define RCC_CFGR_SWS_HSE 0x00000004U
5456 #define RCC_CFGR_SWS_PLL 0x00000008U
5459 #define RCC_CFGR_HPRE 0x000000F0U
5460 #define RCC_CFGR_HPRE_0 0x00000010U
5461 #define RCC_CFGR_HPRE_1 0x00000020U
5462 #define RCC_CFGR_HPRE_2 0x00000040U
5463 #define RCC_CFGR_HPRE_3 0x00000080U
5465 #define RCC_CFGR_HPRE_DIV1 0x00000000U
5466 #define RCC_CFGR_HPRE_DIV2 0x00000080U
5467 #define RCC_CFGR_HPRE_DIV4 0x00000090U
5468 #define RCC_CFGR_HPRE_DIV8 0x000000A0U
5469 #define RCC_CFGR_HPRE_DIV16 0x000000B0U
5470 #define RCC_CFGR_HPRE_DIV64 0x000000C0U
5471 #define RCC_CFGR_HPRE_DIV128 0x000000D0U
5472 #define RCC_CFGR_HPRE_DIV256 0x000000E0U
5473 #define RCC_CFGR_HPRE_DIV512 0x000000F0U
5476 #define RCC_CFGR_PPRE1 0x00001C00U
5477 #define RCC_CFGR_PPRE1_0 0x00000400U
5478 #define RCC_CFGR_PPRE1_1 0x00000800U
5479 #define RCC_CFGR_PPRE1_2 0x00001000U
5481 #define RCC_CFGR_PPRE1_DIV1 0x00000000U
5482 #define RCC_CFGR_PPRE1_DIV2 0x00001000U
5483 #define RCC_CFGR_PPRE1_DIV4 0x00001400U
5484 #define RCC_CFGR_PPRE1_DIV8 0x00001800U
5485 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U
5488 #define RCC_CFGR_PPRE2 0x0000E000U
5489 #define RCC_CFGR_PPRE2_0 0x00002000U
5490 #define RCC_CFGR_PPRE2_1 0x00004000U
5491 #define RCC_CFGR_PPRE2_2 0x00008000U
5493 #define RCC_CFGR_PPRE2_DIV1 0x00000000U
5494 #define RCC_CFGR_PPRE2_DIV2 0x00008000U
5495 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U
5496 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U
5497 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U
5500 #define RCC_CFGR_RTCPRE 0x001F0000U
5501 #define RCC_CFGR_RTCPRE_0 0x00010000U
5502 #define RCC_CFGR_RTCPRE_1 0x00020000U
5503 #define RCC_CFGR_RTCPRE_2 0x00040000U
5504 #define RCC_CFGR_RTCPRE_3 0x00080000U
5505 #define RCC_CFGR_RTCPRE_4 0x00100000U
5506 
5508 #define RCC_CFGR_MCO1 0x00600000U
5509 #define RCC_CFGR_MCO1_0 0x00200000U
5510 #define RCC_CFGR_MCO1_1 0x00400000U
5511 
5512 #define RCC_CFGR_I2SSRC 0x00800000U
5513 
5514 #define RCC_CFGR_MCO1PRE 0x07000000U
5515 #define RCC_CFGR_MCO1PRE_0 0x01000000U
5516 #define RCC_CFGR_MCO1PRE_1 0x02000000U
5517 #define RCC_CFGR_MCO1PRE_2 0x04000000U
5518 
5519 #define RCC_CFGR_MCO2PRE 0x38000000U
5520 #define RCC_CFGR_MCO2PRE_0 0x08000000U
5521 #define RCC_CFGR_MCO2PRE_1 0x10000000U
5522 #define RCC_CFGR_MCO2PRE_2 0x20000000U
5523 
5524 #define RCC_CFGR_MCO2 0xC0000000U
5525 #define RCC_CFGR_MCO2_0 0x40000000U
5526 #define RCC_CFGR_MCO2_1 0x80000000U
5527 
5528 /******************** Bit definition for RCC_CIR register *******************/
5529 #define RCC_CIR_LSIRDYF 0x00000001U
5530 #define RCC_CIR_LSERDYF 0x00000002U
5531 #define RCC_CIR_HSIRDYF 0x00000004U
5532 #define RCC_CIR_HSERDYF 0x00000008U
5533 #define RCC_CIR_PLLRDYF 0x00000010U
5534 #define RCC_CIR_PLLI2SRDYF 0x00000020U
5535 #define RCC_CIR_PLLSAIRDYF 0x00000040U
5536 #define RCC_CIR_CSSF 0x00000080U
5537 #define RCC_CIR_LSIRDYIE 0x00000100U
5538 #define RCC_CIR_LSERDYIE 0x00000200U
5539 #define RCC_CIR_HSIRDYIE 0x00000400U
5540 #define RCC_CIR_HSERDYIE 0x00000800U
5541 #define RCC_CIR_PLLRDYIE 0x00001000U
5542 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
5543 #define RCC_CIR_PLLSAIRDYIE 0x00004000U
5544 #define RCC_CIR_LSIRDYC 0x00010000U
5545 #define RCC_CIR_LSERDYC 0x00020000U
5546 #define RCC_CIR_HSIRDYC 0x00040000U
5547 #define RCC_CIR_HSERDYC 0x00080000U
5548 #define RCC_CIR_PLLRDYC 0x00100000U
5549 #define RCC_CIR_PLLI2SRDYC 0x00200000U
5550 #define RCC_CIR_PLLSAIRDYC 0x00400000U
5551 #define RCC_CIR_CSSC 0x00800000U
5552 
5553 /******************** Bit definition for RCC_AHB1RSTR register **************/
5554 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
5555 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
5556 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
5557 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
5558 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
5559 #define RCC_AHB1RSTR_GPIOFRST 0x00000020U
5560 #define RCC_AHB1RSTR_GPIOGRST 0x00000040U
5561 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
5562 #define RCC_AHB1RSTR_GPIOIRST 0x00000100U
5563 #define RCC_AHB1RSTR_GPIOJRST 0x00000200U
5564 #define RCC_AHB1RSTR_GPIOKRST 0x00000400U
5565 #define RCC_AHB1RSTR_CRCRST 0x00001000U
5566 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
5567 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
5568 #define RCC_AHB1RSTR_DMA2DRST 0x00800000U
5569 #define RCC_AHB1RSTR_ETHMACRST 0x02000000U
5570 #define RCC_AHB1RSTR_OTGHRST 0x20000000U
5571 
5572 /******************** Bit definition for RCC_AHB2RSTR register **************/
5573 #define RCC_AHB2RSTR_DCMIRST 0x00000001U
5574 #define RCC_AHB2RSTR_RNGRST 0x00000040U
5575 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
5576 
5577 /******************** Bit definition for RCC_AHB3RSTR register **************/
5578 
5579 #define RCC_AHB3RSTR_FMCRST 0x00000001U
5580 #define RCC_AHB3RSTR_QSPIRST 0x00000002U
5581 
5582 /******************** Bit definition for RCC_APB1RSTR register **************/
5583 #define RCC_APB1RSTR_TIM2RST 0x00000001U
5584 #define RCC_APB1RSTR_TIM3RST 0x00000002U
5585 #define RCC_APB1RSTR_TIM4RST 0x00000004U
5586 #define RCC_APB1RSTR_TIM5RST 0x00000008U
5587 #define RCC_APB1RSTR_TIM6RST 0x00000010U
5588 #define RCC_APB1RSTR_TIM7RST 0x00000020U
5589 #define RCC_APB1RSTR_TIM12RST 0x00000040U
5590 #define RCC_APB1RSTR_TIM13RST 0x00000080U
5591 #define RCC_APB1RSTR_TIM14RST 0x00000100U
5592 #define RCC_APB1RSTR_LPTIM1RST 0x00000200U
5593 #define RCC_APB1RSTR_WWDGRST 0x00000800U
5594 #define RCC_APB1RSTR_SPI2RST 0x00004000U
5595 #define RCC_APB1RSTR_SPI3RST 0x00008000U
5596 #define RCC_APB1RSTR_SPDIFRXRST 0x00010000U
5597 #define RCC_APB1RSTR_USART2RST 0x00020000U
5598 #define RCC_APB1RSTR_USART3RST 0x00040000U
5599 #define RCC_APB1RSTR_UART4RST 0x00080000U
5600 #define RCC_APB1RSTR_UART5RST 0x00100000U
5601 #define RCC_APB1RSTR_I2C1RST 0x00200000U
5602 #define RCC_APB1RSTR_I2C2RST 0x00400000U
5603 #define RCC_APB1RSTR_I2C3RST 0x00800000U
5604 #define RCC_APB1RSTR_I2C4RST 0x01000000U
5605 #define RCC_APB1RSTR_CAN1RST 0x02000000U
5606 #define RCC_APB1RSTR_CAN2RST 0x04000000U
5607 #define RCC_APB1RSTR_CECRST 0x08000000U
5608 #define RCC_APB1RSTR_PWRRST 0x10000000U
5609 #define RCC_APB1RSTR_DACRST 0x20000000U
5610 #define RCC_APB1RSTR_UART7RST 0x40000000U
5611 #define RCC_APB1RSTR_UART8RST 0x80000000U
5612 
5613 /******************** Bit definition for RCC_APB2RSTR register **************/
5614 #define RCC_APB2RSTR_TIM1RST 0x00000001U
5615 #define RCC_APB2RSTR_TIM8RST 0x00000002U
5616 #define RCC_APB2RSTR_USART1RST 0x00000010U
5617 #define RCC_APB2RSTR_USART6RST 0x00000020U
5618 #define RCC_APB2RSTR_ADCRST 0x00000100U
5619 #define RCC_APB2RSTR_SDMMC1RST 0x00000800U
5620 #define RCC_APB2RSTR_SPI1RST 0x00001000U
5621 #define RCC_APB2RSTR_SPI4RST 0x00002000U
5622 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
5623 #define RCC_APB2RSTR_TIM9RST 0x00010000U
5624 #define RCC_APB2RSTR_TIM10RST 0x00020000U
5625 #define RCC_APB2RSTR_TIM11RST 0x00040000U
5626 #define RCC_APB2RSTR_SPI5RST 0x00100000U
5627 #define RCC_APB2RSTR_SPI6RST 0x00200000U
5628 #define RCC_APB2RSTR_SAI1RST 0x00400000U
5629 #define RCC_APB2RSTR_SAI2RST 0x00800000U
5630 #define RCC_APB2RSTR_LTDCRST 0x04000000U
5631 
5632 /******************** Bit definition for RCC_AHB1ENR register ***************/
5633 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
5634 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
5635 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
5636 #define RCC_AHB1ENR_GPIODEN 0x00000008U
5637 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
5638 #define RCC_AHB1ENR_GPIOFEN 0x00000020U
5639 #define RCC_AHB1ENR_GPIOGEN 0x00000040U
5640 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
5641 #define RCC_AHB1ENR_GPIOIEN 0x00000100U
5642 #define RCC_AHB1ENR_GPIOJEN 0x00000200U
5643 #define RCC_AHB1ENR_GPIOKEN 0x00000400U
5644 #define RCC_AHB1ENR_CRCEN 0x00001000U
5645 #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
5646 #define RCC_AHB1ENR_DTCMRAMEN 0x00100000U
5647 #define RCC_AHB1ENR_DMA1EN 0x00200000U
5648 #define RCC_AHB1ENR_DMA2EN 0x00400000U
5649 #define RCC_AHB1ENR_DMA2DEN 0x00800000U
5650 #define RCC_AHB1ENR_ETHMACEN 0x02000000U
5651 #define RCC_AHB1ENR_ETHMACTXEN 0x04000000U
5652 #define RCC_AHB1ENR_ETHMACRXEN 0x08000000U
5653 #define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U
5654 #define RCC_AHB1ENR_OTGHSEN 0x20000000U
5655 #define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
5656 
5657 /******************** Bit definition for RCC_AHB2ENR register ***************/
5658 #define RCC_AHB2ENR_DCMIEN 0x00000001U
5659 #define RCC_AHB2ENR_RNGEN 0x00000040U
5660 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
5661 
5662 /******************** Bit definition for RCC_AHB3ENR register ***************/
5663 #define RCC_AHB3ENR_FMCEN 0x00000001U
5664 #define RCC_AHB3ENR_QSPIEN 0x00000002U
5665 
5666 /******************** Bit definition for RCC_APB1ENR register ***************/
5667 #define RCC_APB1ENR_TIM2EN 0x00000001U
5668 #define RCC_APB1ENR_TIM3EN 0x00000002U
5669 #define RCC_APB1ENR_TIM4EN 0x00000004U
5670 #define RCC_APB1ENR_TIM5EN 0x00000008U
5671 #define RCC_APB1ENR_TIM6EN 0x00000010U
5672 #define RCC_APB1ENR_TIM7EN 0x00000020U
5673 #define RCC_APB1ENR_TIM12EN 0x00000040U
5674 #define RCC_APB1ENR_TIM13EN 0x00000080U
5675 #define RCC_APB1ENR_TIM14EN 0x00000100U
5676 #define RCC_APB1ENR_LPTIM1EN 0x00000200U
5677 #define RCC_APB1ENR_WWDGEN 0x00000800U
5678 #define RCC_APB1ENR_SPI2EN 0x00004000U
5679 #define RCC_APB1ENR_SPI3EN 0x00008000U
5680 #define RCC_APB1ENR_SPDIFRXEN 0x00010000U
5681 #define RCC_APB1ENR_USART2EN 0x00020000U
5682 #define RCC_APB1ENR_USART3EN 0x00040000U
5683 #define RCC_APB1ENR_UART4EN 0x00080000U
5684 #define RCC_APB1ENR_UART5EN 0x00100000U
5685 #define RCC_APB1ENR_I2C1EN 0x00200000U
5686 #define RCC_APB1ENR_I2C2EN 0x00400000U
5687 #define RCC_APB1ENR_I2C3EN 0x00800000U
5688 #define RCC_APB1ENR_I2C4EN 0x01000000U
5689 #define RCC_APB1ENR_CAN1EN 0x02000000U
5690 #define RCC_APB1ENR_CAN2EN 0x04000000U
5691 #define RCC_APB1ENR_CECEN 0x08000000U
5692 #define RCC_APB1ENR_PWREN 0x10000000U
5693 #define RCC_APB1ENR_DACEN 0x20000000U
5694 #define RCC_APB1ENR_UART7EN 0x40000000U
5695 #define RCC_APB1ENR_UART8EN 0x80000000U
5696 
5697 /******************** Bit definition for RCC_APB2ENR register ***************/
5698 #define RCC_APB2ENR_TIM1EN 0x00000001U
5699 #define RCC_APB2ENR_TIM8EN 0x00000002U
5700 #define RCC_APB2ENR_USART1EN 0x00000010U
5701 #define RCC_APB2ENR_USART6EN 0x00000020U
5702 #define RCC_APB2ENR_ADC1EN 0x00000100U
5703 #define RCC_APB2ENR_ADC2EN 0x00000200U
5704 #define RCC_APB2ENR_ADC3EN 0x00000400U
5705 #define RCC_APB2ENR_SDMMC1EN 0x00000800U
5706 #define RCC_APB2ENR_SPI1EN 0x00001000U
5707 #define RCC_APB2ENR_SPI4EN 0x00002000U
5708 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
5709 #define RCC_APB2ENR_TIM9EN 0x00010000U
5710 #define RCC_APB2ENR_TIM10EN 0x00020000U
5711 #define RCC_APB2ENR_TIM11EN 0x00040000U
5712 #define RCC_APB2ENR_SPI5EN 0x00100000U
5713 #define RCC_APB2ENR_SPI6EN 0x00200000U
5714 #define RCC_APB2ENR_SAI1EN 0x00400000U
5715 #define RCC_APB2ENR_SAI2EN 0x00800000U
5716 #define RCC_APB2ENR_LTDCEN 0x04000000U
5717 
5718 /******************** Bit definition for RCC_AHB1LPENR register *************/
5719 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
5720 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
5721 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
5722 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
5723 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
5724 #define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
5725 #define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
5726 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
5727 #define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
5728 #define RCC_AHB1LPENR_GPIOJLPEN 0x00000200U
5729 #define RCC_AHB1LPENR_GPIOKLPEN 0x00000400U
5730 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
5731 #define RCC_AHB1LPENR_AXILPEN 0x00002000U
5732 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
5733 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
5734 #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
5735 #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
5736 #define RCC_AHB1LPENR_DTCMLPEN 0x00100000U
5737 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
5738 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
5739 #define RCC_AHB1LPENR_DMA2DLPEN 0x00800000U
5740 #define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U
5741 #define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U
5742 #define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U
5743 #define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U
5744 #define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
5745 #define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
5746 
5747 /******************** Bit definition for RCC_AHB2LPENR register *************/
5748 #define RCC_AHB2LPENR_DCMILPEN 0x00000001U
5749 #define RCC_AHB2LPENR_RNGLPEN 0x00000040U
5750 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
5751 
5752 /******************** Bit definition for RCC_AHB3LPENR register *************/
5753 #define RCC_AHB3LPENR_FMCLPEN 0x00000001U
5754 #define RCC_AHB3LPENR_QSPILPEN 0x00000002U
5755 /******************** Bit definition for RCC_APB1LPENR register *************/
5756 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
5757 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
5758 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
5759 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
5760 #define RCC_APB1LPENR_TIM6LPEN 0x00000010U
5761 #define RCC_APB1LPENR_TIM7LPEN 0x00000020U
5762 #define RCC_APB1LPENR_TIM12LPEN 0x00000040U
5763 #define RCC_APB1LPENR_TIM13LPEN 0x00000080U
5764 #define RCC_APB1LPENR_TIM14LPEN 0x00000100U
5765 #define RCC_APB1LPENR_LPTIM1LPEN 0x00000200U
5766 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
5767 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
5768 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
5769 #define RCC_APB1LPENR_SPDIFRXLPEN 0x00010000U
5770 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
5771 #define RCC_APB1LPENR_USART3LPEN 0x00040000U
5772 #define RCC_APB1LPENR_UART4LPEN 0x00080000U
5773 #define RCC_APB1LPENR_UART5LPEN 0x00100000U
5774 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
5775 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
5776 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
5777 #define RCC_APB1LPENR_I2C4LPEN 0x01000000U
5778 #define RCC_APB1LPENR_CAN1LPEN 0x02000000U
5779 #define RCC_APB1LPENR_CAN2LPEN 0x04000000U
5780 #define RCC_APB1LPENR_CECLPEN 0x08000000U
5781 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
5782 #define RCC_APB1LPENR_DACLPEN 0x20000000U
5783 #define RCC_APB1LPENR_UART7LPEN 0x40000000U
5784 #define RCC_APB1LPENR_UART8LPEN 0x80000000U
5785 
5786 /******************** Bit definition for RCC_APB2LPENR register *************/
5787 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
5788 #define RCC_APB2LPENR_TIM8LPEN 0x00000002U
5789 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
5790 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
5791 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
5792 #define RCC_APB2LPENR_ADC2LPEN 0x00000200U
5793 #define RCC_APB2LPENR_ADC3LPEN 0x00000400U
5794 #define RCC_APB2LPENR_SDMMC1LPEN 0x00000800U
5795 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
5796 #define RCC_APB2LPENR_SPI4LPEN 0x00002000U
5797 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
5798 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
5799 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
5800 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
5801 #define RCC_APB2LPENR_SPI5LPEN 0x00100000U
5802 #define RCC_APB2LPENR_SPI6LPEN 0x00200000U
5803 #define RCC_APB2LPENR_SAI1LPEN 0x00400000U
5804 #define RCC_APB2LPENR_SAI2LPEN 0x00800000U
5805 #define RCC_APB2LPENR_LTDCLPEN 0x04000000U
5806 
5807 /******************** Bit definition for RCC_BDCR register ******************/
5808 #define RCC_BDCR_LSEON 0x00000001U
5809 #define RCC_BDCR_LSERDY 0x00000002U
5810 #define RCC_BDCR_LSEBYP 0x00000004U
5811 #define RCC_BDCR_LSEDRV 0x00000018U
5812 #define RCC_BDCR_LSEDRV_0 0x00000008U
5813 #define RCC_BDCR_LSEDRV_1 0x00000010U
5814 #define RCC_BDCR_RTCSEL 0x00000300U
5815 #define RCC_BDCR_RTCSEL_0 0x00000100U
5816 #define RCC_BDCR_RTCSEL_1 0x00000200U
5817 #define RCC_BDCR_RTCEN 0x00008000U
5818 #define RCC_BDCR_BDRST 0x00010000U
5819 
5820 /******************** Bit definition for RCC_CSR register *******************/
5821 #define RCC_CSR_LSION 0x00000001U
5822 #define RCC_CSR_LSIRDY 0x00000002U
5823 #define RCC_CSR_RMVF 0x01000000U
5824 #define RCC_CSR_BORRSTF 0x02000000U
5825 #define RCC_CSR_PINRSTF 0x04000000U
5826 #define RCC_CSR_PORRSTF 0x08000000U
5827 #define RCC_CSR_SFTRSTF 0x10000000U
5828 #define RCC_CSR_IWDGRSTF 0x20000000U
5829 #define RCC_CSR_WWDGRSTF 0x40000000U
5830 #define RCC_CSR_LPWRRSTF 0x80000000U
5831 
5832 /******************** Bit definition for RCC_SSCGR register *****************/
5833 #define RCC_SSCGR_MODPER 0x00001FFFU
5834 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
5835 #define RCC_SSCGR_SPREADSEL 0x40000000U
5836 #define RCC_SSCGR_SSCGEN 0x80000000U
5837 
5838 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
5839 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
5840 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
5841 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
5842 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
5843 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
5844 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
5845 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
5846 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
5847 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
5848 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
5849 #define RCC_PLLI2SCFGR_PLLI2SP 0x00030000U
5850 #define RCC_PLLI2SCFGR_PLLI2SP_0 0x00010000U
5851 #define RCC_PLLI2SCFGR_PLLI2SP_1 0x00020000U
5852 #define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
5853 #define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
5854 #define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
5855 #define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
5856 #define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
5857 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
5858 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
5859 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
5860 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
5861 
5862 /******************** Bit definition for RCC_PLLSAICFGR register ************/
5863 #define RCC_PLLSAICFGR_PLLSAIN 0x00007FC0U
5864 #define RCC_PLLSAICFGR_PLLSAIN_0 0x00000040U
5865 #define RCC_PLLSAICFGR_PLLSAIN_1 0x00000080U
5866 #define RCC_PLLSAICFGR_PLLSAIN_2 0x00000100U
5867 #define RCC_PLLSAICFGR_PLLSAIN_3 0x00000200U
5868 #define RCC_PLLSAICFGR_PLLSAIN_4 0x00000400U
5869 #define RCC_PLLSAICFGR_PLLSAIN_5 0x00000800U
5870 #define RCC_PLLSAICFGR_PLLSAIN_6 0x00001000U
5871 #define RCC_PLLSAICFGR_PLLSAIN_7 0x00002000U
5872 #define RCC_PLLSAICFGR_PLLSAIN_8 0x00004000U
5873 #define RCC_PLLSAICFGR_PLLSAIP 0x00030000U
5874 #define RCC_PLLSAICFGR_PLLSAIP_0 0x00010000U
5875 #define RCC_PLLSAICFGR_PLLSAIP_1 0x00020000U
5876 #define RCC_PLLSAICFGR_PLLSAIQ 0x0F000000U
5877 #define RCC_PLLSAICFGR_PLLSAIQ_0 0x01000000U
5878 #define RCC_PLLSAICFGR_PLLSAIQ_1 0x02000000U
5879 #define RCC_PLLSAICFGR_PLLSAIQ_2 0x04000000U
5880 #define RCC_PLLSAICFGR_PLLSAIQ_3 0x08000000U
5881 #define RCC_PLLSAICFGR_PLLSAIR 0x70000000U
5882 #define RCC_PLLSAICFGR_PLLSAIR_0 0x10000000U
5883 #define RCC_PLLSAICFGR_PLLSAIR_1 0x20000000U
5884 #define RCC_PLLSAICFGR_PLLSAIR_2 0x40000000U
5885 
5886 /******************** Bit definition for RCC_DCKCFGR1 register ***************/
5887 #define RCC_DCKCFGR1_PLLI2SDIVQ 0x0000001FU
5888 #define RCC_DCKCFGR1_PLLI2SDIVQ_0 0x00000001U
5889 #define RCC_DCKCFGR1_PLLI2SDIVQ_1 0x00000002U
5890 #define RCC_DCKCFGR1_PLLI2SDIVQ_2 0x00000004U
5891 #define RCC_DCKCFGR1_PLLI2SDIVQ_3 0x00000008U
5892 #define RCC_DCKCFGR1_PLLI2SDIVQ_4 0x00000010U
5893 
5894 #define RCC_DCKCFGR1_PLLSAIDIVQ 0x00001F00U
5895 #define RCC_DCKCFGR1_PLLSAIDIVQ_0 0x00000100U
5896 #define RCC_DCKCFGR1_PLLSAIDIVQ_1 0x00000200U
5897 #define RCC_DCKCFGR1_PLLSAIDIVQ_2 0x00000400U
5898 #define RCC_DCKCFGR1_PLLSAIDIVQ_3 0x00000800U
5899 #define RCC_DCKCFGR1_PLLSAIDIVQ_4 0x00001000U
5900 
5901 #define RCC_DCKCFGR1_PLLSAIDIVR 0x00030000U
5902 #define RCC_DCKCFGR1_PLLSAIDIVR_0 0x00010000U
5903 #define RCC_DCKCFGR1_PLLSAIDIVR_1 0x00020000U
5904 
5905 #define RCC_DCKCFGR1_SAI1SEL 0x00300000U
5906 #define RCC_DCKCFGR1_SAI1SEL_0 0x00100000U
5907 #define RCC_DCKCFGR1_SAI1SEL_1 0x00200000U
5908 
5909 #define RCC_DCKCFGR1_SAI2SEL 0x00C00000U
5910 #define RCC_DCKCFGR1_SAI2SEL_0 0x00400000U
5911 #define RCC_DCKCFGR1_SAI2SEL_1 0x00800000U
5912 
5913 #define RCC_DCKCFGR1_TIMPRE 0x01000000U
5914 
5915 /******************** Bit definition for RCC_DCKCFGR2 register ***************/
5916 #define RCC_DCKCFGR2_USART1SEL 0x00000003U
5917 #define RCC_DCKCFGR2_USART1SEL_0 0x00000001U
5918 #define RCC_DCKCFGR2_USART1SEL_1 0x00000002U
5919 #define RCC_DCKCFGR2_USART2SEL 0x0000000CU
5920 #define RCC_DCKCFGR2_USART2SEL_0 0x00000004U
5921 #define RCC_DCKCFGR2_USART2SEL_1 0x00000008U
5922 #define RCC_DCKCFGR2_USART3SEL 0x00000030U
5923 #define RCC_DCKCFGR2_USART3SEL_0 0x00000010U
5924 #define RCC_DCKCFGR2_USART3SEL_1 0x00000020U
5925 #define RCC_DCKCFGR2_UART4SEL 0x000000C0U
5926 #define RCC_DCKCFGR2_UART4SEL_0 0x00000040U
5927 #define RCC_DCKCFGR2_UART4SEL_1 0x00000080U
5928 #define RCC_DCKCFGR2_UART5SEL 0x00000300U
5929 #define RCC_DCKCFGR2_UART5SEL_0 0x00000100U
5930 #define RCC_DCKCFGR2_UART5SEL_1 0x00000200U
5931 #define RCC_DCKCFGR2_USART6SEL 0x00000C00U
5932 #define RCC_DCKCFGR2_USART6SEL_0 0x00000400U
5933 #define RCC_DCKCFGR2_USART6SEL_1 0x00000800U
5934 #define RCC_DCKCFGR2_UART7SEL 0x00003000U
5935 #define RCC_DCKCFGR2_UART7SEL_0 0x00001000U
5936 #define RCC_DCKCFGR2_UART7SEL_1 0x00002000U
5937 #define RCC_DCKCFGR2_UART8SEL 0x0000C000U
5938 #define RCC_DCKCFGR2_UART8SEL_0 0x00004000U
5939 #define RCC_DCKCFGR2_UART8SEL_1 0x00008000U
5940 #define RCC_DCKCFGR2_I2C1SEL 0x00030000U
5941 #define RCC_DCKCFGR2_I2C1SEL_0 0x00010000U
5942 #define RCC_DCKCFGR2_I2C1SEL_1 0x00020000U
5943 #define RCC_DCKCFGR2_I2C2SEL 0x000C0000U
5944 #define RCC_DCKCFGR2_I2C2SEL_0 0x00040000U
5945 #define RCC_DCKCFGR2_I2C2SEL_1 0x00080000U
5946 #define RCC_DCKCFGR2_I2C3SEL 0x00300000U
5947 #define RCC_DCKCFGR2_I2C3SEL_0 0x00100000U
5948 #define RCC_DCKCFGR2_I2C3SEL_1 0x00200000U
5949 #define RCC_DCKCFGR2_I2C4SEL 0x00C00000U
5950 #define RCC_DCKCFGR2_I2C4SEL_0 0x00400000U
5951 #define RCC_DCKCFGR2_I2C4SEL_1 0x00800000U
5952 #define RCC_DCKCFGR2_LPTIM1SEL 0x03000000U
5953 #define RCC_DCKCFGR2_LPTIM1SEL_0 0x01000000U
5954 #define RCC_DCKCFGR2_LPTIM1SEL_1 0x02000000U
5955 #define RCC_DCKCFGR2_CECSEL 0x04000000U
5956 #define RCC_DCKCFGR2_CK48MSEL 0x08000000U
5957 #define RCC_DCKCFGR2_SDMMC1SEL 0x10000000U
5958 
5959 /******************************************************************************/
5960 /* */
5961 /* RNG */
5962 /* */
5963 /******************************************************************************/
5964 /******************** Bits definition for RNG_CR register *******************/
5965 #define RNG_CR_RNGEN 0x00000004U
5966 #define RNG_CR_IE 0x00000008U
5967 
5968 /******************** Bits definition for RNG_SR register *******************/
5969 #define RNG_SR_DRDY 0x00000001U
5970 #define RNG_SR_CECS 0x00000002U
5971 #define RNG_SR_SECS 0x00000004U
5972 #define RNG_SR_CEIS 0x00000020U
5973 #define RNG_SR_SEIS 0x00000040U
5974 
5975 /******************************************************************************/
5976 /* */
5977 /* Real-Time Clock (RTC) */
5978 /* */
5979 /******************************************************************************/
5980 /******************** Bits definition for RTC_TR register *******************/
5981 #define RTC_TR_PM 0x00400000U
5982 #define RTC_TR_HT 0x00300000U
5983 #define RTC_TR_HT_0 0x00100000U
5984 #define RTC_TR_HT_1 0x00200000U
5985 #define RTC_TR_HU 0x000F0000U
5986 #define RTC_TR_HU_0 0x00010000U
5987 #define RTC_TR_HU_1 0x00020000U
5988 #define RTC_TR_HU_2 0x00040000U
5989 #define RTC_TR_HU_3 0x00080000U
5990 #define RTC_TR_MNT 0x00007000U
5991 #define RTC_TR_MNT_0 0x00001000U
5992 #define RTC_TR_MNT_1 0x00002000U
5993 #define RTC_TR_MNT_2 0x00004000U
5994 #define RTC_TR_MNU 0x00000F00U
5995 #define RTC_TR_MNU_0 0x00000100U
5996 #define RTC_TR_MNU_1 0x00000200U
5997 #define RTC_TR_MNU_2 0x00000400U
5998 #define RTC_TR_MNU_3 0x00000800U
5999 #define RTC_TR_ST 0x00000070U
6000 #define RTC_TR_ST_0 0x00000010U
6001 #define RTC_TR_ST_1 0x00000020U
6002 #define RTC_TR_ST_2 0x00000040U
6003 #define RTC_TR_SU 0x0000000FU
6004 #define RTC_TR_SU_0 0x00000001U
6005 #define RTC_TR_SU_1 0x00000002U
6006 #define RTC_TR_SU_2 0x00000004U
6007 #define RTC_TR_SU_3 0x00000008U
6008 
6009 /******************** Bits definition for RTC_DR register *******************/
6010 #define RTC_DR_YT 0x00F00000U
6011 #define RTC_DR_YT_0 0x00100000U
6012 #define RTC_DR_YT_1 0x00200000U
6013 #define RTC_DR_YT_2 0x00400000U
6014 #define RTC_DR_YT_3 0x00800000U
6015 #define RTC_DR_YU 0x000F0000U
6016 #define RTC_DR_YU_0 0x00010000U
6017 #define RTC_DR_YU_1 0x00020000U
6018 #define RTC_DR_YU_2 0x00040000U
6019 #define RTC_DR_YU_3 0x00080000U
6020 #define RTC_DR_WDU 0x0000E000U
6021 #define RTC_DR_WDU_0 0x00002000U
6022 #define RTC_DR_WDU_1 0x00004000U
6023 #define RTC_DR_WDU_2 0x00008000U
6024 #define RTC_DR_MT 0x00001000U
6025 #define RTC_DR_MU 0x00000F00U
6026 #define RTC_DR_MU_0 0x00000100U
6027 #define RTC_DR_MU_1 0x00000200U
6028 #define RTC_DR_MU_2 0x00000400U
6029 #define RTC_DR_MU_3 0x00000800U
6030 #define RTC_DR_DT 0x00000030U
6031 #define RTC_DR_DT_0 0x00000010U
6032 #define RTC_DR_DT_1 0x00000020U
6033 #define RTC_DR_DU 0x0000000FU
6034 #define RTC_DR_DU_0 0x00000001U
6035 #define RTC_DR_DU_1 0x00000002U
6036 #define RTC_DR_DU_2 0x00000004U
6037 #define RTC_DR_DU_3 0x00000008U
6038 
6039 /******************** Bits definition for RTC_CR register *******************/
6040 #define RTC_CR_ITSE 0x01000000U
6041 #define RTC_CR_COE 0x00800000U
6042 #define RTC_CR_OSEL 0x00600000U
6043 #define RTC_CR_OSEL_0 0x00200000U
6044 #define RTC_CR_OSEL_1 0x00400000U
6045 #define RTC_CR_POL 0x00100000U
6046 #define RTC_CR_COSEL 0x00080000U
6047 #define RTC_CR_BCK 0x00040000U
6048 #define RTC_CR_SUB1H 0x00020000U
6049 #define RTC_CR_ADD1H 0x00010000U
6050 #define RTC_CR_TSIE 0x00008000U
6051 #define RTC_CR_WUTIE 0x00004000U
6052 #define RTC_CR_ALRBIE 0x00002000U
6053 #define RTC_CR_ALRAIE 0x00001000U
6054 #define RTC_CR_TSE 0x00000800U
6055 #define RTC_CR_WUTE 0x00000400U
6056 #define RTC_CR_ALRBE 0x00000200U
6057 #define RTC_CR_ALRAE 0x00000100U
6058 #define RTC_CR_FMT 0x00000040U
6059 #define RTC_CR_BYPSHAD 0x00000020U
6060 #define RTC_CR_REFCKON 0x00000010U
6061 #define RTC_CR_TSEDGE 0x00000008U
6062 #define RTC_CR_WUCKSEL 0x00000007U
6063 #define RTC_CR_WUCKSEL_0 0x00000001U
6064 #define RTC_CR_WUCKSEL_1 0x00000002U
6065 #define RTC_CR_WUCKSEL_2 0x00000004U
6066 
6067 /******************** Bits definition for RTC_ISR register ******************/
6068 #define RTC_ISR_ITSF 0x00020000U
6069 #define RTC_ISR_RECALPF 0x00010000U
6070 #define RTC_ISR_TAMP3F 0x00008000U
6071 #define RTC_ISR_TAMP2F 0x00004000U
6072 #define RTC_ISR_TAMP1F 0x00002000U
6073 #define RTC_ISR_TSOVF 0x00001000U
6074 #define RTC_ISR_TSF 0x00000800U
6075 #define RTC_ISR_WUTF 0x00000400U
6076 #define RTC_ISR_ALRBF 0x00000200U
6077 #define RTC_ISR_ALRAF 0x00000100U
6078 #define RTC_ISR_INIT 0x00000080U
6079 #define RTC_ISR_INITF 0x00000040U
6080 #define RTC_ISR_RSF 0x00000020U
6081 #define RTC_ISR_INITS 0x00000010U
6082 #define RTC_ISR_SHPF 0x00000008U
6083 #define RTC_ISR_WUTWF 0x00000004U
6084 #define RTC_ISR_ALRBWF 0x00000002U
6085 #define RTC_ISR_ALRAWF 0x00000001U
6086 
6087 /******************** Bits definition for RTC_PRER register *****************/
6088 #define RTC_PRER_PREDIV_A 0x007F0000U
6089 #define RTC_PRER_PREDIV_S 0x00007FFFU
6090 
6091 /******************** Bits definition for RTC_WUTR register *****************/
6092 #define RTC_WUTR_WUT 0x0000FFFFU
6093 
6094 /******************** Bits definition for RTC_ALRMAR register ***************/
6095 #define RTC_ALRMAR_MSK4 0x80000000U
6096 #define RTC_ALRMAR_WDSEL 0x40000000U
6097 #define RTC_ALRMAR_DT 0x30000000U
6098 #define RTC_ALRMAR_DT_0 0x10000000U
6099 #define RTC_ALRMAR_DT_1 0x20000000U
6100 #define RTC_ALRMAR_DU 0x0F000000U
6101 #define RTC_ALRMAR_DU_0 0x01000000U
6102 #define RTC_ALRMAR_DU_1 0x02000000U
6103 #define RTC_ALRMAR_DU_2 0x04000000U
6104 #define RTC_ALRMAR_DU_3 0x08000000U
6105 #define RTC_ALRMAR_MSK3 0x00800000U
6106 #define RTC_ALRMAR_PM 0x00400000U
6107 #define RTC_ALRMAR_HT 0x00300000U
6108 #define RTC_ALRMAR_HT_0 0x00100000U
6109 #define RTC_ALRMAR_HT_1 0x00200000U
6110 #define RTC_ALRMAR_HU 0x000F0000U
6111 #define RTC_ALRMAR_HU_0 0x00010000U
6112 #define RTC_ALRMAR_HU_1 0x00020000U
6113 #define RTC_ALRMAR_HU_2 0x00040000U
6114 #define RTC_ALRMAR_HU_3 0x00080000U
6115 #define RTC_ALRMAR_MSK2 0x00008000U
6116 #define RTC_ALRMAR_MNT 0x00007000U
6117 #define RTC_ALRMAR_MNT_0 0x00001000U
6118 #define RTC_ALRMAR_MNT_1 0x00002000U
6119 #define RTC_ALRMAR_MNT_2 0x00004000U
6120 #define RTC_ALRMAR_MNU 0x00000F00U
6121 #define RTC_ALRMAR_MNU_0 0x00000100U
6122 #define RTC_ALRMAR_MNU_1 0x00000200U
6123 #define RTC_ALRMAR_MNU_2 0x00000400U
6124 #define RTC_ALRMAR_MNU_3 0x00000800U
6125 #define RTC_ALRMAR_MSK1 0x00000080U
6126 #define RTC_ALRMAR_ST 0x00000070U
6127 #define RTC_ALRMAR_ST_0 0x00000010U
6128 #define RTC_ALRMAR_ST_1 0x00000020U
6129 #define RTC_ALRMAR_ST_2 0x00000040U
6130 #define RTC_ALRMAR_SU 0x0000000FU
6131 #define RTC_ALRMAR_SU_0 0x00000001U
6132 #define RTC_ALRMAR_SU_1 0x00000002U
6133 #define RTC_ALRMAR_SU_2 0x00000004U
6134 #define RTC_ALRMAR_SU_3 0x00000008U
6135 
6136 /******************** Bits definition for RTC_ALRMBR register ***************/
6137 #define RTC_ALRMBR_MSK4 0x80000000U
6138 #define RTC_ALRMBR_WDSEL 0x40000000U
6139 #define RTC_ALRMBR_DT 0x30000000U
6140 #define RTC_ALRMBR_DT_0 0x10000000U
6141 #define RTC_ALRMBR_DT_1 0x20000000U
6142 #define RTC_ALRMBR_DU 0x0F000000U
6143 #define RTC_ALRMBR_DU_0 0x01000000U
6144 #define RTC_ALRMBR_DU_1 0x02000000U
6145 #define RTC_ALRMBR_DU_2 0x04000000U
6146 #define RTC_ALRMBR_DU_3 0x08000000U
6147 #define RTC_ALRMBR_MSK3 0x00800000U
6148 #define RTC_ALRMBR_PM 0x00400000U
6149 #define RTC_ALRMBR_HT 0x00300000U
6150 #define RTC_ALRMBR_HT_0 0x00100000U
6151 #define RTC_ALRMBR_HT_1 0x00200000U
6152 #define RTC_ALRMBR_HU 0x000F0000U
6153 #define RTC_ALRMBR_HU_0 0x00010000U
6154 #define RTC_ALRMBR_HU_1 0x00020000U
6155 #define RTC_ALRMBR_HU_2 0x00040000U
6156 #define RTC_ALRMBR_HU_3 0x00080000U
6157 #define RTC_ALRMBR_MSK2 0x00008000U
6158 #define RTC_ALRMBR_MNT 0x00007000U
6159 #define RTC_ALRMBR_MNT_0 0x00001000U
6160 #define RTC_ALRMBR_MNT_1 0x00002000U
6161 #define RTC_ALRMBR_MNT_2 0x00004000U
6162 #define RTC_ALRMBR_MNU 0x00000F00U
6163 #define RTC_ALRMBR_MNU_0 0x00000100U
6164 #define RTC_ALRMBR_MNU_1 0x00000200U
6165 #define RTC_ALRMBR_MNU_2 0x00000400U
6166 #define RTC_ALRMBR_MNU_3 0x00000800U
6167 #define RTC_ALRMBR_MSK1 0x00000080U
6168 #define RTC_ALRMBR_ST 0x00000070U
6169 #define RTC_ALRMBR_ST_0 0x00000010U
6170 #define RTC_ALRMBR_ST_1 0x00000020U
6171 #define RTC_ALRMBR_ST_2 0x00000040U
6172 #define RTC_ALRMBR_SU 0x0000000FU
6173 #define RTC_ALRMBR_SU_0 0x00000001U
6174 #define RTC_ALRMBR_SU_1 0x00000002U
6175 #define RTC_ALRMBR_SU_2 0x00000004U
6176 #define RTC_ALRMBR_SU_3 0x00000008U
6177 
6178 /******************** Bits definition for RTC_WPR register ******************/
6179 #define RTC_WPR_KEY 0x000000FFU
6180 
6181 /******************** Bits definition for RTC_SSR register ******************/
6182 #define RTC_SSR_SS 0x0000FFFFU
6183 
6184 /******************** Bits definition for RTC_SHIFTR register ***************/
6185 #define RTC_SHIFTR_SUBFS 0x00007FFFU
6186 #define RTC_SHIFTR_ADD1S 0x80000000U
6187 
6188 /******************** Bits definition for RTC_TSTR register *****************/
6189 #define RTC_TSTR_PM 0x00400000U
6190 #define RTC_TSTR_HT 0x00300000U
6191 #define RTC_TSTR_HT_0 0x00100000U
6192 #define RTC_TSTR_HT_1 0x00200000U
6193 #define RTC_TSTR_HU 0x000F0000U
6194 #define RTC_TSTR_HU_0 0x00010000U
6195 #define RTC_TSTR_HU_1 0x00020000U
6196 #define RTC_TSTR_HU_2 0x00040000U
6197 #define RTC_TSTR_HU_3 0x00080000U
6198 #define RTC_TSTR_MNT 0x00007000U
6199 #define RTC_TSTR_MNT_0 0x00001000U
6200 #define RTC_TSTR_MNT_1 0x00002000U
6201 #define RTC_TSTR_MNT_2 0x00004000U
6202 #define RTC_TSTR_MNU 0x00000F00U
6203 #define RTC_TSTR_MNU_0 0x00000100U
6204 #define RTC_TSTR_MNU_1 0x00000200U
6205 #define RTC_TSTR_MNU_2 0x00000400U
6206 #define RTC_TSTR_MNU_3 0x00000800U
6207 #define RTC_TSTR_ST 0x00000070U
6208 #define RTC_TSTR_ST_0 0x00000010U
6209 #define RTC_TSTR_ST_1 0x00000020U
6210 #define RTC_TSTR_ST_2 0x00000040U
6211 #define RTC_TSTR_SU 0x0000000FU
6212 #define RTC_TSTR_SU_0 0x00000001U
6213 #define RTC_TSTR_SU_1 0x00000002U
6214 #define RTC_TSTR_SU_2 0x00000004U
6215 #define RTC_TSTR_SU_3 0x00000008U
6216 
6217 /******************** Bits definition for RTC_TSDR register *****************/
6218 #define RTC_TSDR_WDU 0x0000E000U
6219 #define RTC_TSDR_WDU_0 0x00002000U
6220 #define RTC_TSDR_WDU_1 0x00004000U
6221 #define RTC_TSDR_WDU_2 0x00008000U
6222 #define RTC_TSDR_MT 0x00001000U
6223 #define RTC_TSDR_MU 0x00000F00U
6224 #define RTC_TSDR_MU_0 0x00000100U
6225 #define RTC_TSDR_MU_1 0x00000200U
6226 #define RTC_TSDR_MU_2 0x00000400U
6227 #define RTC_TSDR_MU_3 0x00000800U
6228 #define RTC_TSDR_DT 0x00000030U
6229 #define RTC_TSDR_DT_0 0x00000010U
6230 #define RTC_TSDR_DT_1 0x00000020U
6231 #define RTC_TSDR_DU 0x0000000FU
6232 #define RTC_TSDR_DU_0 0x00000001U
6233 #define RTC_TSDR_DU_1 0x00000002U
6234 #define RTC_TSDR_DU_2 0x00000004U
6235 #define RTC_TSDR_DU_3 0x00000008U
6236 
6237 /******************** Bits definition for RTC_TSSSR register ****************/
6238 #define RTC_TSSSR_SS 0x0000FFFFU
6239 
6240 /******************** Bits definition for RTC_CAL register *****************/
6241 #define RTC_CALR_CALP 0x00008000U
6242 #define RTC_CALR_CALW8 0x00004000U
6243 #define RTC_CALR_CALW16 0x00002000U
6244 #define RTC_CALR_CALM 0x000001FFU
6245 #define RTC_CALR_CALM_0 0x00000001U
6246 #define RTC_CALR_CALM_1 0x00000002U
6247 #define RTC_CALR_CALM_2 0x00000004U
6248 #define RTC_CALR_CALM_3 0x00000008U
6249 #define RTC_CALR_CALM_4 0x00000010U
6250 #define RTC_CALR_CALM_5 0x00000020U
6251 #define RTC_CALR_CALM_6 0x00000040U
6252 #define RTC_CALR_CALM_7 0x00000080U
6253 #define RTC_CALR_CALM_8 0x00000100U
6254 
6255 /******************** Bits definition for RTC_TAMPCR register ****************/
6256 #define RTC_TAMPCR_TAMP3MF 0x01000000U
6257 #define RTC_TAMPCR_TAMP3NOERASE 0x00800000U
6258 #define RTC_TAMPCR_TAMP3IE 0x00400000U
6259 #define RTC_TAMPCR_TAMP2MF 0x00200000U
6260 #define RTC_TAMPCR_TAMP2NOERASE 0x00100000U
6261 #define RTC_TAMPCR_TAMP2IE 0x00080000U
6262 #define RTC_TAMPCR_TAMP1MF 0x00040000U
6263 #define RTC_TAMPCR_TAMP1NOERASE 0x00020000U
6264 #define RTC_TAMPCR_TAMP1IE 0x00010000U
6265 #define RTC_TAMPCR_TAMPPUDIS 0x00008000U
6266 #define RTC_TAMPCR_TAMPPRCH 0x00006000U
6267 #define RTC_TAMPCR_TAMPPRCH_0 0x00002000U
6268 #define RTC_TAMPCR_TAMPPRCH_1 0x00004000U
6269 #define RTC_TAMPCR_TAMPFLT 0x00001800U
6270 #define RTC_TAMPCR_TAMPFLT_0 0x00000800U
6271 #define RTC_TAMPCR_TAMPFLT_1 0x00001000U
6272 #define RTC_TAMPCR_TAMPFREQ 0x00000700U
6273 #define RTC_TAMPCR_TAMPFREQ_0 0x00000100U
6274 #define RTC_TAMPCR_TAMPFREQ_1 0x00000200U
6275 #define RTC_TAMPCR_TAMPFREQ_2 0x00000400U
6276 #define RTC_TAMPCR_TAMPTS 0x00000080U
6277 #define RTC_TAMPCR_TAMP3TRG 0x00000040U
6278 #define RTC_TAMPCR_TAMP3E 0x00000020U
6279 #define RTC_TAMPCR_TAMP2TRG 0x00000010U
6280 #define RTC_TAMPCR_TAMP2E 0x00000008U
6281 #define RTC_TAMPCR_TAMPIE 0x00000004U
6282 #define RTC_TAMPCR_TAMP1TRG 0x00000002U
6283 #define RTC_TAMPCR_TAMP1E 0x00000001U
6284 
6285 /* Legacy defines */
6286 #define RTC_TAMPCR_TAMP3_TRG RTC_TAMPCR_TAMP3TRG
6287 #define RTC_TAMPCR_TAMP2_TRG RTC_TAMPCR_TAMP2TRG
6288 #define RTC_TAMPCR_TAMP1_TRG RTC_TAMPCR_TAMP1TRG
6289 
6290 /******************** Bits definition for RTC_ALRMASSR register *************/
6291 #define RTC_ALRMASSR_MASKSS 0x0F000000U
6292 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
6293 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
6294 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
6295 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
6296 #define RTC_ALRMASSR_SS 0x00007FFFU
6297 
6298 /******************** Bits definition for RTC_ALRMBSSR register *************/
6299 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
6300 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
6301 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
6302 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
6303 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
6304 #define RTC_ALRMBSSR_SS 0x00007FFFU
6305 
6306 /******************** Bits definition for RTC_OR register ****************/
6307 #define RTC_OR_TSINSEL 0x00000006U
6308 #define RTC_OR_TSINSEL_0 0x00000002U
6309 #define RTC_OR_TSINSEL_1 0x00000004U
6310 #define RTC_OR_ALARMTYPE 0x00000008U
6311 
6312 /******************** Bits definition for RTC_BKP0R register ****************/
6313 #define RTC_BKP0R 0xFFFFFFFFU
6314 
6315 /******************** Bits definition for RTC_BKP1R register ****************/
6316 #define RTC_BKP1R 0xFFFFFFFFU
6317 
6318 /******************** Bits definition for RTC_BKP2R register ****************/
6319 #define RTC_BKP2R 0xFFFFFFFFU
6320 
6321 /******************** Bits definition for RTC_BKP3R register ****************/
6322 #define RTC_BKP3R 0xFFFFFFFFU
6323 
6324 /******************** Bits definition for RTC_BKP4R register ****************/
6325 #define RTC_BKP4R 0xFFFFFFFFU
6326 
6327 /******************** Bits definition for RTC_BKP5R register ****************/
6328 #define RTC_BKP5R 0xFFFFFFFFU
6329 
6330 /******************** Bits definition for RTC_BKP6R register ****************/
6331 #define RTC_BKP6R 0xFFFFFFFFU
6332 
6333 /******************** Bits definition for RTC_BKP7R register ****************/
6334 #define RTC_BKP7R 0xFFFFFFFFU
6335 
6336 /******************** Bits definition for RTC_BKP8R register ****************/
6337 #define RTC_BKP8R 0xFFFFFFFFU
6338 
6339 /******************** Bits definition for RTC_BKP9R register ****************/
6340 #define RTC_BKP9R 0xFFFFFFFFU
6341 
6342 /******************** Bits definition for RTC_BKP10R register ***************/
6343 #define RTC_BKP10R 0xFFFFFFFFU
6344 
6345 /******************** Bits definition for RTC_BKP11R register ***************/
6346 #define RTC_BKP11R 0xFFFFFFFFU
6347 
6348 /******************** Bits definition for RTC_BKP12R register ***************/
6349 #define RTC_BKP12R 0xFFFFFFFFU
6350 
6351 /******************** Bits definition for RTC_BKP13R register ***************/
6352 #define RTC_BKP13R 0xFFFFFFFFU
6353 
6354 /******************** Bits definition for RTC_BKP14R register ***************/
6355 #define RTC_BKP14R 0xFFFFFFFFU
6356 
6357 /******************** Bits definition for RTC_BKP15R register ***************/
6358 #define RTC_BKP15R 0xFFFFFFFFU
6359 
6360 /******************** Bits definition for RTC_BKP16R register ***************/
6361 #define RTC_BKP16R 0xFFFFFFFFU
6362 
6363 /******************** Bits definition for RTC_BKP17R register ***************/
6364 #define RTC_BKP17R 0xFFFFFFFFU
6365 
6366 /******************** Bits definition for RTC_BKP18R register ***************/
6367 #define RTC_BKP18R 0xFFFFFFFFU
6368 
6369 /******************** Bits definition for RTC_BKP19R register ***************/
6370 #define RTC_BKP19R 0xFFFFFFFFU
6371 
6372 /******************** Bits definition for RTC_BKP20R register ***************/
6373 #define RTC_BKP20R 0xFFFFFFFFU
6374 
6375 /******************** Bits definition for RTC_BKP21R register ***************/
6376 #define RTC_BKP21R 0xFFFFFFFFU
6377 
6378 /******************** Bits definition for RTC_BKP22R register ***************/
6379 #define RTC_BKP22R 0xFFFFFFFFU
6380 
6381 /******************** Bits definition for RTC_BKP23R register ***************/
6382 #define RTC_BKP23R 0xFFFFFFFFU
6383 
6384 /******************** Bits definition for RTC_BKP24R register ***************/
6385 #define RTC_BKP24R 0xFFFFFFFFU
6386 
6387 /******************** Bits definition for RTC_BKP25R register ***************/
6388 #define RTC_BKP25R 0xFFFFFFFFU
6389 
6390 /******************** Bits definition for RTC_BKP26R register ***************/
6391 #define RTC_BKP26R 0xFFFFFFFFU
6392 
6393 /******************** Bits definition for RTC_BKP27R register ***************/
6394 #define RTC_BKP27R 0xFFFFFFFFU
6395 
6396 /******************** Bits definition for RTC_BKP28R register ***************/
6397 #define RTC_BKP28R 0xFFFFFFFFU
6398 
6399 /******************** Bits definition for RTC_BKP29R register ***************/
6400 #define RTC_BKP29R 0xFFFFFFFFU
6401 
6402 /******************** Bits definition for RTC_BKP30R register ***************/
6403 #define RTC_BKP30R 0xFFFFFFFFU
6404 
6405 /******************** Bits definition for RTC_BKP31R register ***************/
6406 #define RTC_BKP31R 0xFFFFFFFFU
6407 
6408 /******************** Number of backup registers ******************************/
6409 #define RTC_BKP_NUMBER 0x00000020U
6410 
6411 
6412 /******************************************************************************/
6413 /* */
6414 /* Serial Audio Interface */
6415 /* */
6416 /******************************************************************************/
6417 /******************** Bit definition for SAI_GCR register *******************/
6418 #define SAI_GCR_SYNCIN 0x00000003U
6419 #define SAI_GCR_SYNCIN_0 0x00000001U
6420 #define SAI_GCR_SYNCIN_1 0x00000002U
6422 #define SAI_GCR_SYNCOUT 0x00000030U
6423 #define SAI_GCR_SYNCOUT_0 0x00000010U
6424 #define SAI_GCR_SYNCOUT_1 0x00000020U
6426 /******************* Bit definition for SAI_xCR1 register *******************/
6427 #define SAI_xCR1_MODE 0x00000003U
6428 #define SAI_xCR1_MODE_0 0x00000001U
6429 #define SAI_xCR1_MODE_1 0x00000002U
6431 #define SAI_xCR1_PRTCFG 0x0000000CU
6432 #define SAI_xCR1_PRTCFG_0 0x00000004U
6433 #define SAI_xCR1_PRTCFG_1 0x00000008U
6435 #define SAI_xCR1_DS 0x000000E0U
6436 #define SAI_xCR1_DS_0 0x00000020U
6437 #define SAI_xCR1_DS_1 0x00000040U
6438 #define SAI_xCR1_DS_2 0x00000080U
6440 #define SAI_xCR1_LSBFIRST 0x00000100U
6441 #define SAI_xCR1_CKSTR 0x00000200U
6443 #define SAI_xCR1_SYNCEN 0x00000C00U
6444 #define SAI_xCR1_SYNCEN_0 0x00000400U
6445 #define SAI_xCR1_SYNCEN_1 0x00000800U
6447 #define SAI_xCR1_MONO 0x00001000U
6448 #define SAI_xCR1_OUTDRIV 0x00002000U
6449 #define SAI_xCR1_SAIEN 0x00010000U
6450 #define SAI_xCR1_DMAEN 0x00020000U
6451 #define SAI_xCR1_NODIV 0x00080000U
6453 #define SAI_xCR1_MCKDIV 0x00F00000U
6454 #define SAI_xCR1_MCKDIV_0 0x00100000U
6455 #define SAI_xCR1_MCKDIV_1 0x00200000U
6456 #define SAI_xCR1_MCKDIV_2 0x00400000U
6457 #define SAI_xCR1_MCKDIV_3 0x00800000U
6459 /******************* Bit definition for SAI_xCR2 register *******************/
6460 #define SAI_xCR2_FTH 0x00000007U
6461 #define SAI_xCR2_FTH_0 0x00000001U
6462 #define SAI_xCR2_FTH_1 0x00000002U
6463 #define SAI_xCR2_FTH_2 0x00000004U
6465 #define SAI_xCR2_FFLUSH 0x00000008U
6466 #define SAI_xCR2_TRIS 0x00000010U
6467 #define SAI_xCR2_MUTE 0x00000020U
6468 #define SAI_xCR2_MUTEVAL 0x00000040U
6470 #define SAI_xCR2_MUTECNT 0x00001F80U
6471 #define SAI_xCR2_MUTECNT_0 0x00000080U
6472 #define SAI_xCR2_MUTECNT_1 0x00000100U
6473 #define SAI_xCR2_MUTECNT_2 0x00000200U
6474 #define SAI_xCR2_MUTECNT_3 0x00000400U
6475 #define SAI_xCR2_MUTECNT_4 0x00000800U
6476 #define SAI_xCR2_MUTECNT_5 0x00001000U
6478 #define SAI_xCR2_CPL 0x00002000U
6480 #define SAI_xCR2_COMP 0x0000C000U
6481 #define SAI_xCR2_COMP_0 0x00004000U
6482 #define SAI_xCR2_COMP_1 0x00008000U
6484 /****************** Bit definition for SAI_xFRCR register *******************/
6485 #define SAI_xFRCR_FRL 0x000000FFU
6486 #define SAI_xFRCR_FRL_0 0x00000001U
6487 #define SAI_xFRCR_FRL_1 0x00000002U
6488 #define SAI_xFRCR_FRL_2 0x00000004U
6489 #define SAI_xFRCR_FRL_3 0x00000008U
6490 #define SAI_xFRCR_FRL_4 0x00000010U
6491 #define SAI_xFRCR_FRL_5 0x00000020U
6492 #define SAI_xFRCR_FRL_6 0x00000040U
6493 #define SAI_xFRCR_FRL_7 0x00000080U
6495 #define SAI_xFRCR_FSALL 0x00007F00U
6496 #define SAI_xFRCR_FSALL_0 0x00000100U
6497 #define SAI_xFRCR_FSALL_1 0x00000200U
6498 #define SAI_xFRCR_FSALL_2 0x00000400U
6499 #define SAI_xFRCR_FSALL_3 0x00000800U
6500 #define SAI_xFRCR_FSALL_4 0x00001000U
6501 #define SAI_xFRCR_FSALL_5 0x00002000U
6502 #define SAI_xFRCR_FSALL_6 0x00004000U
6504 #define SAI_xFRCR_FSDEF 0x00010000U
6505 #define SAI_xFRCR_FSPOL 0x00020000U
6506 #define SAI_xFRCR_FSOFF 0x00040000U
6508 /* Legacy define */
6509 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
6510 
6511 /****************** Bit definition for SAI_xSLOTR register *******************/
6512 #define SAI_xSLOTR_FBOFF 0x0000001FU
6513 #define SAI_xSLOTR_FBOFF_0 0x00000001U
6514 #define SAI_xSLOTR_FBOFF_1 0x00000002U
6515 #define SAI_xSLOTR_FBOFF_2 0x00000004U
6516 #define SAI_xSLOTR_FBOFF_3 0x00000008U
6517 #define SAI_xSLOTR_FBOFF_4 0x00000010U
6519 #define SAI_xSLOTR_SLOTSZ 0x000000C0U
6520 #define SAI_xSLOTR_SLOTSZ_0 0x00000040U
6521 #define SAI_xSLOTR_SLOTSZ_1 0x00000080U
6523 #define SAI_xSLOTR_NBSLOT 0x00000F00U
6524 #define SAI_xSLOTR_NBSLOT_0 0x00000100U
6525 #define SAI_xSLOTR_NBSLOT_1 0x00000200U
6526 #define SAI_xSLOTR_NBSLOT_2 0x00000400U
6527 #define SAI_xSLOTR_NBSLOT_3 0x00000800U
6529 #define SAI_xSLOTR_SLOTEN 0xFFFF0000U
6531 /******************* Bit definition for SAI_xIMR register *******************/
6532 #define SAI_xIMR_OVRUDRIE 0x00000001U
6533 #define SAI_xIMR_MUTEDETIE 0x00000002U
6534 #define SAI_xIMR_WCKCFGIE 0x00000004U
6535 #define SAI_xIMR_FREQIE 0x00000008U
6536 #define SAI_xIMR_CNRDYIE 0x00000010U
6537 #define SAI_xIMR_AFSDETIE 0x00000020U
6538 #define SAI_xIMR_LFSDETIE 0x00000040U
6540 /******************** Bit definition for SAI_xSR register *******************/
6541 #define SAI_xSR_OVRUDR 0x00000001U
6542 #define SAI_xSR_MUTEDET 0x00000002U
6543 #define SAI_xSR_WCKCFG 0x00000004U
6544 #define SAI_xSR_FREQ 0x00000008U
6545 #define SAI_xSR_CNRDY 0x00000010U
6546 #define SAI_xSR_AFSDET 0x00000020U
6547 #define SAI_xSR_LFSDET 0x00000040U
6549 #define SAI_xSR_FLVL 0x00070000U
6550 #define SAI_xSR_FLVL_0 0x00010000U
6551 #define SAI_xSR_FLVL_1 0x00020000U
6552 #define SAI_xSR_FLVL_2 0x00040000U
6554 /****************** Bit definition for SAI_xCLRFR register ******************/
6555 #define SAI_xCLRFR_COVRUDR 0x00000001U
6556 #define SAI_xCLRFR_CMUTEDET 0x00000002U
6557 #define SAI_xCLRFR_CWCKCFG 0x00000004U
6558 #define SAI_xCLRFR_CFREQ 0x00000008U
6559 #define SAI_xCLRFR_CCNRDY 0x00000010U
6560 #define SAI_xCLRFR_CAFSDET 0x00000020U
6561 #define SAI_xCLRFR_CLFSDET 0x00000040U
6563 /****************** Bit definition for SAI_xDR register *********************/
6564 #define SAI_xDR_DATA 0xFFFFFFFFU
6565 
6566 /******************************************************************************/
6567 /* */
6568 /* SPDIF-RX Interface */
6569 /* */
6570 /******************************************************************************/
6571 /******************** Bit definition for SPDIF_CR register *******************/
6572 #define SPDIFRX_CR_SPDIFEN 0x00000003U
6573 #define SPDIFRX_CR_RXDMAEN 0x00000004U
6574 #define SPDIFRX_CR_RXSTEO 0x00000008U
6575 #define SPDIFRX_CR_DRFMT 0x00000030U
6576 #define SPDIFRX_CR_PMSK 0x00000040U
6577 #define SPDIFRX_CR_VMSK 0x00000080U
6578 #define SPDIFRX_CR_CUMSK 0x00000100U
6579 #define SPDIFRX_CR_PTMSK 0x00000200U
6580 #define SPDIFRX_CR_CBDMAEN 0x00000400U
6581 #define SPDIFRX_CR_CHSEL 0x00000800U
6582 #define SPDIFRX_CR_NBTR 0x00003000U
6583 #define SPDIFRX_CR_WFA 0x00004000U
6584 #define SPDIFRX_CR_INSEL 0x00070000U
6586 /******************* Bit definition for SPDIFRX_IMR register *******************/
6587 #define SPDIFRX_IMR_RXNEIE 0x00000001U
6588 #define SPDIFRX_IMR_CSRNEIE 0x00000002U
6589 #define SPDIFRX_IMR_PERRIE 0x00000004U
6590 #define SPDIFRX_IMR_OVRIE 0x00000008U
6591 #define SPDIFRX_IMR_SBLKIE 0x00000010U
6592 #define SPDIFRX_IMR_SYNCDIE 0x00000020U
6593 #define SPDIFRX_IMR_IFEIE 0x00000040U
6595 /******************* Bit definition for SPDIFRX_SR register *******************/
6596 #define SPDIFRX_SR_RXNE 0x00000001U
6597 #define SPDIFRX_SR_CSRNE 0x00000002U
6598 #define SPDIFRX_SR_PERR 0x00000004U
6599 #define SPDIFRX_SR_OVR 0x00000008U
6600 #define SPDIFRX_SR_SBD 0x00000010U
6601 #define SPDIFRX_SR_SYNCD 0x00000020U
6602 #define SPDIFRX_SR_FERR 0x00000040U
6603 #define SPDIFRX_SR_SERR 0x00000080U
6604 #define SPDIFRX_SR_TERR 0x00000100U
6605 #define SPDIFRX_SR_WIDTH5 0x7FFF0000U
6607 /******************* Bit definition for SPDIFRX_IFCR register *******************/
6608 #define SPDIFRX_IFCR_PERRCF 0x00000004U
6609 #define SPDIFRX_IFCR_OVRCF 0x00000008U
6610 #define SPDIFRX_IFCR_SBDCF 0x00000010U
6611 #define SPDIFRX_IFCR_SYNCDCF 0x00000020U
6613 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
6614 #define SPDIFRX_DR0_DR 0x00FFFFFFU
6615 #define SPDIFRX_DR0_PE 0x01000000U
6616 #define SPDIFRX_DR0_V 0x02000000U
6617 #define SPDIFRX_DR0_U 0x04000000U
6618 #define SPDIFRX_DR0_C 0x08000000U
6619 #define SPDIFRX_DR0_PT 0x30000000U
6621 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
6622 #define SPDIFRX_DR1_DR 0xFFFFFF00U
6623 #define SPDIFRX_DR1_PT 0x00000030U
6624 #define SPDIFRX_DR1_C 0x00000008U
6625 #define SPDIFRX_DR1_U 0x00000004U
6626 #define SPDIFRX_DR1_V 0x00000002U
6627 #define SPDIFRX_DR1_PE 0x00000001U
6629 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
6630 #define SPDIFRX_DR1_DRNL1 0xFFFF0000U
6631 #define SPDIFRX_DR1_DRNL2 0x0000FFFFU
6633 /******************* Bit definition for SPDIFRX_CSR register *******************/
6634 #define SPDIFRX_CSR_USR 0x0000FFFFU
6635 #define SPDIFRX_CSR_CS 0x00FF0000U
6636 #define SPDIFRX_CSR_SOB 0x01000000U
6638 /******************* Bit definition for SPDIFRX_DIR register *******************/
6639 #define SPDIFRX_DIR_THI 0x000013FFU
6640 #define SPDIFRX_DIR_TLO 0x1FFF0000U
6643 /******************************************************************************/
6644 /* */
6645 /* SD host Interface */
6646 /* */
6647 /******************************************************************************/
6648 /****************** Bit definition for SDMMC_POWER register ******************/
6649 #define SDMMC_POWER_PWRCTRL 0x03U
6650 #define SDMMC_POWER_PWRCTRL_0 0x01U
6651 #define SDMMC_POWER_PWRCTRL_1 0x02U
6653 /****************** Bit definition for SDMMC_CLKCR register ******************/
6654 #define SDMMC_CLKCR_CLKDIV 0x00FFU
6655 #define SDMMC_CLKCR_CLKEN 0x0100U
6656 #define SDMMC_CLKCR_PWRSAV 0x0200U
6657 #define SDMMC_CLKCR_BYPASS 0x0400U
6659 #define SDMMC_CLKCR_WIDBUS 0x1800U
6660 #define SDMMC_CLKCR_WIDBUS_0 0x0800U
6661 #define SDMMC_CLKCR_WIDBUS_1 0x1000U
6663 #define SDMMC_CLKCR_NEGEDGE 0x2000U
6664 #define SDMMC_CLKCR_HWFC_EN 0x4000U
6666 /******************* Bit definition for SDMMC_ARG register *******************/
6667 #define SDMMC_ARG_CMDARG 0xFFFFFFFFU
6669 /******************* Bit definition for SDMMC_CMD register *******************/
6670 #define SDMMC_CMD_CMDINDEX 0x003FU
6672 #define SDMMC_CMD_WAITRESP 0x00C0U
6673 #define SDMMC_CMD_WAITRESP_0 0x0040U
6674 #define SDMMC_CMD_WAITRESP_1 0x0080U
6676 #define SDMMC_CMD_WAITINT 0x0100U
6677 #define SDMMC_CMD_WAITPEND 0x0200U
6678 #define SDMMC_CMD_CPSMEN 0x0400U
6679 #define SDMMC_CMD_SDIOSUSPEND 0x0800U
6681 /***************** Bit definition for SDMMC_RESPCMD register *****************/
6682 #define SDMMC_RESPCMD_RESPCMD 0x3FU
6684 /****************** Bit definition for SDMMC_RESP0 register ******************/
6685 #define SDMMC_RESP0_CARDSTATUS0 0xFFFFFFFFU
6687 /****************** Bit definition for SDMMC_RESP1 register ******************/
6688 #define SDMMC_RESP1_CARDSTATUS1 0xFFFFFFFFU
6690 /****************** Bit definition for SDMMC_RESP2 register ******************/
6691 #define SDMMC_RESP2_CARDSTATUS2 0xFFFFFFFFU
6693 /****************** Bit definition for SDMMC_RESP3 register ******************/
6694 #define SDMMC_RESP3_CARDSTATUS3 0xFFFFFFFFU
6696 /****************** Bit definition for SDMMC_RESP4 register ******************/
6697 #define SDMMC_RESP4_CARDSTATUS4 0xFFFFFFFFU
6699 /****************** Bit definition for SDMMC_DTIMER register *****************/
6700 #define SDMMC_DTIMER_DATATIME 0xFFFFFFFFU
6702 /****************** Bit definition for SDMMC_DLEN register *******************/
6703 #define SDMMC_DLEN_DATALENGTH 0x01FFFFFFU
6705 /****************** Bit definition for SDMMC_DCTRL register ******************/
6706 #define SDMMC_DCTRL_DTEN 0x0001U
6707 #define SDMMC_DCTRL_DTDIR 0x0002U
6708 #define SDMMC_DCTRL_DTMODE 0x0004U
6709 #define SDMMC_DCTRL_DMAEN 0x0008U
6711 #define SDMMC_DCTRL_DBLOCKSIZE 0x00F0U
6712 #define SDMMC_DCTRL_DBLOCKSIZE_0 0x0010U
6713 #define SDMMC_DCTRL_DBLOCKSIZE_1 0x0020U
6714 #define SDMMC_DCTRL_DBLOCKSIZE_2 0x0040U
6715 #define SDMMC_DCTRL_DBLOCKSIZE_3 0x0080U
6717 #define SDMMC_DCTRL_RWSTART 0x0100U
6718 #define SDMMC_DCTRL_RWSTOP 0x0200U
6719 #define SDMMC_DCTRL_RWMOD 0x0400U
6720 #define SDMMC_DCTRL_SDIOEN 0x0800U
6722 /****************** Bit definition for SDMMC_DCOUNT register *****************/
6723 #define SDMMC_DCOUNT_DATACOUNT 0x01FFFFFFU
6725 /****************** Bit definition for SDMMC_STA registe ********************/
6726 #define SDMMC_STA_CCRCFAIL 0x00000001U
6727 #define SDMMC_STA_DCRCFAIL 0x00000002U
6728 #define SDMMC_STA_CTIMEOUT 0x00000004U
6729 #define SDMMC_STA_DTIMEOUT 0x00000008U
6730 #define SDMMC_STA_TXUNDERR 0x00000010U
6731 #define SDMMC_STA_RXOVERR 0x00000020U
6732 #define SDMMC_STA_CMDREND 0x00000040U
6733 #define SDMMC_STA_CMDSENT 0x00000080U
6734 #define SDMMC_STA_DATAEND 0x00000100U
6735 #define SDMMC_STA_DBCKEND 0x00000400U
6736 #define SDMMC_STA_CMDACT 0x00000800U
6737 #define SDMMC_STA_TXACT 0x00001000U
6738 #define SDMMC_STA_RXACT 0x00002000U
6739 #define SDMMC_STA_TXFIFOHE 0x00004000U
6740 #define SDMMC_STA_RXFIFOHF 0x00008000U
6741 #define SDMMC_STA_TXFIFOF 0x00010000U
6742 #define SDMMC_STA_RXFIFOF 0x00020000U
6743 #define SDMMC_STA_TXFIFOE 0x00040000U
6744 #define SDMMC_STA_RXFIFOE 0x00080000U
6745 #define SDMMC_STA_TXDAVL 0x00100000U
6746 #define SDMMC_STA_RXDAVL 0x00200000U
6747 #define SDMMC_STA_SDIOIT 0x00400000U
6749 /******************* Bit definition for SDMMC_ICR register *******************/
6750 #define SDMMC_ICR_CCRCFAILC 0x00000001U
6751 #define SDMMC_ICR_DCRCFAILC 0x00000002U
6752 #define SDMMC_ICR_CTIMEOUTC 0x00000004U
6753 #define SDMMC_ICR_DTIMEOUTC 0x00000008U
6754 #define SDMMC_ICR_TXUNDERRC 0x00000010U
6755 #define SDMMC_ICR_RXOVERRC 0x00000020U
6756 #define SDMMC_ICR_CMDRENDC 0x00000040U
6757 #define SDMMC_ICR_CMDSENTC 0x00000080U
6758 #define SDMMC_ICR_DATAENDC 0x00000100U
6759 #define SDMMC_ICR_DBCKENDC 0x00000400U
6760 #define SDMMC_ICR_SDIOITC 0x00400000U
6762 /****************** Bit definition for SDMMC_MASK register *******************/
6763 #define SDMMC_MASK_CCRCFAILIE 0x00000001U
6764 #define SDMMC_MASK_DCRCFAILIE 0x00000002U
6765 #define SDMMC_MASK_CTIMEOUTIE 0x00000004U
6766 #define SDMMC_MASK_DTIMEOUTIE 0x00000008U
6767 #define SDMMC_MASK_TXUNDERRIE 0x00000010U
6768 #define SDMMC_MASK_RXOVERRIE 0x00000020U
6769 #define SDMMC_MASK_CMDRENDIE 0x00000040U
6770 #define SDMMC_MASK_CMDSENTIE 0x00000080U
6771 #define SDMMC_MASK_DATAENDIE 0x00000100U
6772 #define SDMMC_MASK_DBCKENDIE 0x00000400U
6773 #define SDMMC_MASK_CMDACTIE 0x00000800U
6774 #define SDMMC_MASK_TXACTIE 0x00001000U
6775 #define SDMMC_MASK_RXACTIE 0x00002000U
6776 #define SDMMC_MASK_TXFIFOHEIE 0x00004000U
6777 #define SDMMC_MASK_RXFIFOHFIE 0x00008000U
6778 #define SDMMC_MASK_TXFIFOFIE 0x00010000U
6779 #define SDMMC_MASK_RXFIFOFIE 0x00020000U
6780 #define SDMMC_MASK_TXFIFOEIE 0x00040000U
6781 #define SDMMC_MASK_RXFIFOEIE 0x00080000U
6782 #define SDMMC_MASK_TXDAVLIE 0x00100000U
6783 #define SDMMC_MASK_RXDAVLIE 0x00200000U
6784 #define SDMMC_MASK_SDIOITIE 0x00400000U
6786 /***************** Bit definition for SDMMC_FIFOCNT register *****************/
6787 #define SDMMC_FIFOCNT_FIFOCOUNT 0x00FFFFFFU
6789 /****************** Bit definition for SDMMC_FIFO register *******************/
6790 #define SDMMC_FIFO_FIFODATA 0xFFFFFFFFU
6792 /******************************************************************************/
6793 /* */
6794 /* Serial Peripheral Interface (SPI) */
6795 /* */
6796 /******************************************************************************/
6797 /******************* Bit definition for SPI_CR1 register ********************/
6798 #define SPI_CR1_CPHA 0x00000001U
6799 #define SPI_CR1_CPOL 0x00000002U
6800 #define SPI_CR1_MSTR 0x00000004U
6801 #define SPI_CR1_BR 0x00000038U
6802 #define SPI_CR1_BR_0 0x00000008U
6803 #define SPI_CR1_BR_1 0x00000010U
6804 #define SPI_CR1_BR_2 0x00000020U
6805 #define SPI_CR1_SPE 0x00000040U
6806 #define SPI_CR1_LSBFIRST 0x00000080U
6807 #define SPI_CR1_SSI 0x00000100U
6808 #define SPI_CR1_SSM 0x00000200U
6809 #define SPI_CR1_RXONLY 0x00000400U
6810 #define SPI_CR1_CRCL 0x00000800U
6811 #define SPI_CR1_CRCNEXT 0x00001000U
6812 #define SPI_CR1_CRCEN 0x00002000U
6813 #define SPI_CR1_BIDIOE 0x00004000U
6814 #define SPI_CR1_BIDIMODE 0x00008000U
6816 /******************* Bit definition for SPI_CR2 register ********************/
6817 #define SPI_CR2_RXDMAEN 0x00000001U
6818 #define SPI_CR2_TXDMAEN 0x00000002U
6819 #define SPI_CR2_SSOE 0x00000004U
6820 #define SPI_CR2_NSSP 0x00000008U
6821 #define SPI_CR2_FRF 0x00000010U
6822 #define SPI_CR2_ERRIE 0x00000020U
6823 #define SPI_CR2_RXNEIE 0x00000040U
6824 #define SPI_CR2_TXEIE 0x00000080U
6825 #define SPI_CR2_DS 0x00000F00U
6826 #define SPI_CR2_DS_0 0x00000100U
6827 #define SPI_CR2_DS_1 0x00000200U
6828 #define SPI_CR2_DS_2 0x00000400U
6829 #define SPI_CR2_DS_3 0x00000800U
6830 #define SPI_CR2_FRXTH 0x00001000U
6831 #define SPI_CR2_LDMARX 0x00002000U
6832 #define SPI_CR2_LDMATX 0x00004000U
6834 /******************** Bit definition for SPI_SR register ********************/
6835 #define SPI_SR_RXNE 0x00000001U
6836 #define SPI_SR_TXE 0x00000002U
6837 #define SPI_SR_CHSIDE 0x00000004U
6838 #define SPI_SR_UDR 0x00000008U
6839 #define SPI_SR_CRCERR 0x00000010U
6840 #define SPI_SR_MODF 0x00000020U
6841 #define SPI_SR_OVR 0x00000040U
6842 #define SPI_SR_BSY 0x00000080U
6843 #define SPI_SR_FRE 0x00000100U
6844 #define SPI_SR_FRLVL 0x00000600U
6845 #define SPI_SR_FRLVL_0 0x00000200U
6846 #define SPI_SR_FRLVL_1 0x00000400U
6847 #define SPI_SR_FTLVL 0x00001800U
6848 #define SPI_SR_FTLVL_0 0x00000800U
6849 #define SPI_SR_FTLVL_1 0x00001000U
6851 /******************** Bit definition for SPI_DR register ********************/
6852 #define SPI_DR_DR 0xFFFFU
6854 /******************* Bit definition for SPI_CRCPR register ******************/
6855 #define SPI_CRCPR_CRCPOLY 0xFFFFU
6857 /****************** Bit definition for SPI_RXCRCR register ******************/
6858 #define SPI_RXCRCR_RXCRC 0xFFFFU
6860 /****************** Bit definition for SPI_TXCRCR register ******************/
6861 #define SPI_TXCRCR_TXCRC 0xFFFFU
6863 /****************** Bit definition for SPI_I2SCFGR register *****************/
6864 #define SPI_I2SCFGR_CHLEN 0x00000001U
6865 #define SPI_I2SCFGR_DATLEN 0x00000006U
6866 #define SPI_I2SCFGR_DATLEN_0 0x00000002U
6867 #define SPI_I2SCFGR_DATLEN_1 0x00000004U
6868 #define SPI_I2SCFGR_CKPOL 0x00000008U
6869 #define SPI_I2SCFGR_I2SSTD 0x00000030U
6870 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U
6871 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U
6872 #define SPI_I2SCFGR_PCMSYNC 0x00000080U
6873 #define SPI_I2SCFGR_I2SCFG 0x00000300U
6874 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U
6875 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U
6876 #define SPI_I2SCFGR_I2SE 0x00000400U
6877 #define SPI_I2SCFGR_I2SMOD 0x00000800U
6878 #define SPI_I2SCFGR_ASTRTEN 0x00001000U
6880 /****************** Bit definition for SPI_I2SPR register *******************/
6881 #define SPI_I2SPR_I2SDIV 0x00FFU
6882 #define SPI_I2SPR_ODD 0x0100U
6883 #define SPI_I2SPR_MCKOE 0x0200U
6886 /******************************************************************************/
6887 /* */
6888 /* SYSCFG */
6889 /* */
6890 /******************************************************************************/
6891 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
6892 #define SYSCFG_MEMRMP_MEM_BOOT 0x00000001U
6895 #define SYSCFG_MEMRMP_SWP_FMC 0x00000C00U
6896 #define SYSCFG_MEMRMP_SWP_FMC_0 0x00000400U
6897 #define SYSCFG_MEMRMP_SWP_FMC_1 0x00000800U
6898 
6899 /****************** Bit definition for SYSCFG_PMC register ******************/
6900 
6901 #define SYSCFG_PMC_ADCxDC2 0x00070000U
6902 #define SYSCFG_PMC_ADC1DC2 0x00010000U
6903 #define SYSCFG_PMC_ADC2DC2 0x00020000U
6904 #define SYSCFG_PMC_ADC3DC2 0x00040000U
6906 #define SYSCFG_PMC_MII_RMII_SEL 0x00800000U
6908 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
6909 #define SYSCFG_EXTICR1_EXTI0 0x000FU
6910 #define SYSCFG_EXTICR1_EXTI1 0x00F0U
6911 #define SYSCFG_EXTICR1_EXTI2 0x0F00U
6912 #define SYSCFG_EXTICR1_EXTI3 0xF000U
6916 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
6917 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
6918 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
6919 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
6920 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
6921 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
6922 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
6923 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
6924 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U
6925 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U
6926 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU
6931 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
6932 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
6933 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
6934 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
6935 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
6936 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
6937 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
6938 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
6939 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U
6940 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U
6941 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U
6946 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
6947 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
6948 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
6949 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
6950 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
6951 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
6952 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
6953 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
6954 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U
6955 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U
6956 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U
6961 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
6962 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
6963 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
6964 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
6965 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
6966 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
6967 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
6968 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
6969 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U
6970 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U
6971 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U
6973 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
6974 #define SYSCFG_EXTICR2_EXTI4 0x000FU
6975 #define SYSCFG_EXTICR2_EXTI5 0x00F0U
6976 #define SYSCFG_EXTICR2_EXTI6 0x0F00U
6977 #define SYSCFG_EXTICR2_EXTI7 0xF000U
6981 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
6982 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
6983 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
6984 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
6985 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
6986 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
6987 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
6988 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
6989 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U
6990 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U
6991 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU
6996 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
6997 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
6998 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
6999 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
7000 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
7001 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
7002 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
7003 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
7004 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U
7005 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U
7006 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U
7011 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
7012 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
7013 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
7014 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
7015 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
7016 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
7017 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
7018 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
7019 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U
7020 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U
7021 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U
7026 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
7027 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
7028 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
7029 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
7030 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
7031 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
7032 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
7033 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
7034 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U
7035 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U
7036 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U
7038 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
7039 #define SYSCFG_EXTICR3_EXTI8 0x000FU
7040 #define SYSCFG_EXTICR3_EXTI9 0x00F0U
7041 #define SYSCFG_EXTICR3_EXTI10 0x0F00U
7042 #define SYSCFG_EXTICR3_EXTI11 0xF000U
7047 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
7048 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
7049 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
7050 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
7051 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
7052 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
7053 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
7054 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
7055 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U
7056 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U
7061 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
7062 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
7063 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
7064 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
7065 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
7066 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
7067 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
7068 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
7069 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U
7070 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U
7075 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
7076 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
7077 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
7078 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
7079 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
7080 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
7081 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
7082 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
7083 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U
7084 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U
7089 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
7090 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
7091 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
7092 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
7093 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
7094 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
7095 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
7096 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
7097 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U
7098 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U
7101 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
7102 #define SYSCFG_EXTICR4_EXTI12 0x000FU
7103 #define SYSCFG_EXTICR4_EXTI13 0x00F0U
7104 #define SYSCFG_EXTICR4_EXTI14 0x0F00U
7105 #define SYSCFG_EXTICR4_EXTI15 0xF000U
7109 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
7110 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
7111 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
7112 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
7113 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
7114 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
7115 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
7116 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
7117 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U
7118 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U
7123 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
7124 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
7125 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
7126 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
7127 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
7128 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
7129 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
7130 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
7131 #define SYSCFG_EXTICR4_EXTI13_PI 0x0080U
7132 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0090U
7137 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
7138 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
7139 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
7140 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
7141 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
7142 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
7143 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
7144 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
7145 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U
7146 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U
7151 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
7152 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
7153 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
7154 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
7155 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
7156 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
7157 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
7158 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
7159 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U
7160 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U
7163 /****************** Bit definition for SYSCFG_CMPCR register ****************/
7164 #define SYSCFG_CMPCR_CMP_PD 0x00000001U
7165 #define SYSCFG_CMPCR_READY 0x00000100U
7167 /******************************************************************************/
7168 /* */
7169 /* TIM */
7170 /* */
7171 /******************************************************************************/
7172 /******************* Bit definition for TIM_CR1 register ********************/
7173 #define TIM_CR1_CEN 0x0001U
7174 #define TIM_CR1_UDIS 0x0002U
7175 #define TIM_CR1_URS 0x0004U
7176 #define TIM_CR1_OPM 0x0008U
7177 #define TIM_CR1_DIR 0x0010U
7179 #define TIM_CR1_CMS 0x0060U
7180 #define TIM_CR1_CMS_0 0x0020U
7181 #define TIM_CR1_CMS_1 0x0040U
7183 #define TIM_CR1_ARPE 0x0080U
7185 #define TIM_CR1_CKD 0x0300U
7186 #define TIM_CR1_CKD_0 0x0100U
7187 #define TIM_CR1_CKD_1 0x0200U
7188 #define TIM_CR1_UIFREMAP 0x0800U
7190 /******************* Bit definition for TIM_CR2 register ********************/
7191 #define TIM_CR2_CCPC 0x00000001U
7192 #define TIM_CR2_CCUS 0x00000004U
7193 #define TIM_CR2_CCDS 0x00000008U
7195 #define TIM_CR2_OIS5 0x00010000U
7196 #define TIM_CR2_OIS6 0x00040000U
7198 #define TIM_CR2_MMS 0x0070U
7199 #define TIM_CR2_MMS_0 0x0010U
7200 #define TIM_CR2_MMS_1 0x0020U
7201 #define TIM_CR2_MMS_2 0x0040U
7203 #define TIM_CR2_MMS2 0x00F00000U
7204 #define TIM_CR2_MMS2_0 0x00100000U
7205 #define TIM_CR2_MMS2_1 0x00200000U
7206 #define TIM_CR2_MMS2_2 0x00400000U
7207 #define TIM_CR2_MMS2_3 0x00800000U
7209 #define TIM_CR2_TI1S 0x0080U
7210 #define TIM_CR2_OIS1 0x0100U
7211 #define TIM_CR2_OIS1N 0x0200U
7212 #define TIM_CR2_OIS2 0x0400U
7213 #define TIM_CR2_OIS2N 0x0800U
7214 #define TIM_CR2_OIS3 0x1000U
7215 #define TIM_CR2_OIS3N 0x2000U
7216 #define TIM_CR2_OIS4 0x4000U
7218 /******************* Bit definition for TIM_SMCR register *******************/
7219 #define TIM_SMCR_SMS 0x00010007U
7220 #define TIM_SMCR_SMS_0 0x00000001U
7221 #define TIM_SMCR_SMS_1 0x00000002U
7222 #define TIM_SMCR_SMS_2 0x00000004U
7223 #define TIM_SMCR_SMS_3 0x00010000U
7224 #define TIM_SMCR_OCCS 0x00000008U
7226 #define TIM_SMCR_TS 0x0070U
7227 #define TIM_SMCR_TS_0 0x0010U
7228 #define TIM_SMCR_TS_1 0x0020U
7229 #define TIM_SMCR_TS_2 0x0040U
7231 #define TIM_SMCR_MSM 0x0080U
7233 #define TIM_SMCR_ETF 0x0F00U
7234 #define TIM_SMCR_ETF_0 0x0100U
7235 #define TIM_SMCR_ETF_1 0x0200U
7236 #define TIM_SMCR_ETF_2 0x0400U
7237 #define TIM_SMCR_ETF_3 0x0800U
7239 #define TIM_SMCR_ETPS 0x3000U
7240 #define TIM_SMCR_ETPS_0 0x1000U
7241 #define TIM_SMCR_ETPS_1 0x2000U
7243 #define TIM_SMCR_ECE 0x4000U
7244 #define TIM_SMCR_ETP 0x8000U
7246 /******************* Bit definition for TIM_DIER register *******************/
7247 #define TIM_DIER_UIE 0x0001U
7248 #define TIM_DIER_CC1IE 0x0002U
7249 #define TIM_DIER_CC2IE 0x0004U
7250 #define TIM_DIER_CC3IE 0x0008U
7251 #define TIM_DIER_CC4IE 0x0010U
7252 #define TIM_DIER_COMIE 0x0020U
7253 #define TIM_DIER_TIE 0x0040U
7254 #define TIM_DIER_BIE 0x0080U
7255 #define TIM_DIER_UDE 0x0100U
7256 #define TIM_DIER_CC1DE 0x0200U
7257 #define TIM_DIER_CC2DE 0x0400U
7258 #define TIM_DIER_CC3DE 0x0800U
7259 #define TIM_DIER_CC4DE 0x1000U
7260 #define TIM_DIER_COMDE 0x2000U
7261 #define TIM_DIER_TDE 0x4000U
7263 /******************** Bit definition for TIM_SR register ********************/
7264 #define TIM_SR_UIF 0x0001U
7265 #define TIM_SR_CC1IF 0x0002U
7266 #define TIM_SR_CC2IF 0x0004U
7267 #define TIM_SR_CC3IF 0x0008U
7268 #define TIM_SR_CC4IF 0x0010U
7269 #define TIM_SR_COMIF 0x0020U
7270 #define TIM_SR_TIF 0x0040U
7271 #define TIM_SR_BIF 0x0080U
7272 #define TIM_SR_B2IF 0x0100U
7273 #define TIM_SR_CC1OF 0x0200U
7274 #define TIM_SR_CC2OF 0x0400U
7275 #define TIM_SR_CC3OF 0x0800U
7276 #define TIM_SR_CC4OF 0x1000U
7278 /******************* Bit definition for TIM_EGR register ********************/
7279 #define TIM_EGR_UG 0x00000001U
7280 #define TIM_EGR_CC1G 0x00000002U
7281 #define TIM_EGR_CC2G 0x00000004U
7282 #define TIM_EGR_CC3G 0x00000008U
7283 #define TIM_EGR_CC4G 0x00000010U
7284 #define TIM_EGR_COMG 0x00000020U
7285 #define TIM_EGR_TG 0x00000040U
7286 #define TIM_EGR_BG 0x00000080U
7287 #define TIM_EGR_B2G 0x00000100U
7289 /****************** Bit definition for TIM_CCMR1 register *******************/
7290 #define TIM_CCMR1_CC1S 0x00000003U
7291 #define TIM_CCMR1_CC1S_0 0x00000001U
7292 #define TIM_CCMR1_CC1S_1 0x00000002U
7294 #define TIM_CCMR1_OC1FE 0x00000004U
7295 #define TIM_CCMR1_OC1PE 0x00000008U
7297 #define TIM_CCMR1_OC1M 0x00010070U
7298 #define TIM_CCMR1_OC1M_0 0x00000010U
7299 #define TIM_CCMR1_OC1M_1 0x00000020U
7300 #define TIM_CCMR1_OC1M_2 0x00000040U
7301 #define TIM_CCMR1_OC1M_3 0x00010000U
7303 #define TIM_CCMR1_OC1CE 0x00000080U
7305 #define TIM_CCMR1_CC2S 0x00000300U
7306 #define TIM_CCMR1_CC2S_0 0x00000100U
7307 #define TIM_CCMR1_CC2S_1 0x00000200U
7309 #define TIM_CCMR1_OC2FE 0x00000400U
7310 #define TIM_CCMR1_OC2PE 0x00000800U
7312 #define TIM_CCMR1_OC2M 0x01007000U
7313 #define TIM_CCMR1_OC2M_0 0x00001000U
7314 #define TIM_CCMR1_OC2M_1 0x00002000U
7315 #define TIM_CCMR1_OC2M_2 0x00004000U
7316 #define TIM_CCMR1_OC2M_3 0x01000000U
7318 #define TIM_CCMR1_OC2CE 0x00008000U
7320 /*----------------------------------------------------------------------------*/
7321 
7322 #define TIM_CCMR1_IC1PSC 0x000CU
7323 #define TIM_CCMR1_IC1PSC_0 0x0004U
7324 #define TIM_CCMR1_IC1PSC_1 0x0008U
7326 #define TIM_CCMR1_IC1F 0x00F0U
7327 #define TIM_CCMR1_IC1F_0 0x0010U
7328 #define TIM_CCMR1_IC1F_1 0x0020U
7329 #define TIM_CCMR1_IC1F_2 0x0040U
7330 #define TIM_CCMR1_IC1F_3 0x0080U
7332 #define TIM_CCMR1_IC2PSC 0x0C00U
7333 #define TIM_CCMR1_IC2PSC_0 0x0400U
7334 #define TIM_CCMR1_IC2PSC_1 0x0800U
7336 #define TIM_CCMR1_IC2F 0xF000U
7337 #define TIM_CCMR1_IC2F_0 0x1000U
7338 #define TIM_CCMR1_IC2F_1 0x2000U
7339 #define TIM_CCMR1_IC2F_2 0x4000U
7340 #define TIM_CCMR1_IC2F_3 0x8000U
7342 /****************** Bit definition for TIM_CCMR2 register *******************/
7343 #define TIM_CCMR2_CC3S 0x00000003U
7344 #define TIM_CCMR2_CC3S_0 0x00000001U
7345 #define TIM_CCMR2_CC3S_1 0x00000002U
7347 #define TIM_CCMR2_OC3FE 0x00000004U
7348 #define TIM_CCMR2_OC3PE 0x00000008U
7350 #define TIM_CCMR2_OC3M 0x00010070U
7351 #define TIM_CCMR2_OC3M_0 0x00000010U
7352 #define TIM_CCMR2_OC3M_1 0x00000020U
7353 #define TIM_CCMR2_OC3M_2 0x00000040U
7354 #define TIM_CCMR2_OC3M_3 0x00010000U
7358 #define TIM_CCMR2_OC3CE 0x00000080U
7360 #define TIM_CCMR2_CC4S 0x00000300U
7361 #define TIM_CCMR2_CC4S_0 0x00000100U
7362 #define TIM_CCMR2_CC4S_1 0x00000200U
7364 #define TIM_CCMR2_OC4FE 0x00000400U
7365 #define TIM_CCMR2_OC4PE 0x00000800U
7367 #define TIM_CCMR2_OC4M 0x01007000U
7368 #define TIM_CCMR2_OC4M_0 0x00001000U
7369 #define TIM_CCMR2_OC4M_1 0x00002000U
7370 #define TIM_CCMR2_OC4M_2 0x00004000U
7371 #define TIM_CCMR2_OC4M_3 0x01000000U
7373 #define TIM_CCMR2_OC4CE 0x8000U
7375 /*----------------------------------------------------------------------------*/
7376 
7377 #define TIM_CCMR2_IC3PSC 0x000CU
7378 #define TIM_CCMR2_IC3PSC_0 0x0004U
7379 #define TIM_CCMR2_IC3PSC_1 0x0008U
7381 #define TIM_CCMR2_IC3F 0x00F0U
7382 #define TIM_CCMR2_IC3F_0 0x0010U
7383 #define TIM_CCMR2_IC3F_1 0x0020U
7384 #define TIM_CCMR2_IC3F_2 0x0040U
7385 #define TIM_CCMR2_IC3F_3 0x0080U
7387 #define TIM_CCMR2_IC4PSC 0x0C00U
7388 #define TIM_CCMR2_IC4PSC_0 0x0400U
7389 #define TIM_CCMR2_IC4PSC_1 0x0800U
7391 #define TIM_CCMR2_IC4F 0xF000U
7392 #define TIM_CCMR2_IC4F_0 0x1000U
7393 #define TIM_CCMR2_IC4F_1 0x2000U
7394 #define TIM_CCMR2_IC4F_2 0x4000U
7395 #define TIM_CCMR2_IC4F_3 0x8000U
7397 /******************* Bit definition for TIM_CCER register *******************/
7398 #define TIM_CCER_CC1E 0x00000001U
7399 #define TIM_CCER_CC1P 0x00000002U
7400 #define TIM_CCER_CC1NE 0x00000004U
7401 #define TIM_CCER_CC1NP 0x00000008U
7402 #define TIM_CCER_CC2E 0x00000010U
7403 #define TIM_CCER_CC2P 0x00000020U
7404 #define TIM_CCER_CC2NE 0x00000040U
7405 #define TIM_CCER_CC2NP 0x00000080U
7406 #define TIM_CCER_CC3E 0x00000100U
7407 #define TIM_CCER_CC3P 0x00000200U
7408 #define TIM_CCER_CC3NE 0x00000400U
7409 #define TIM_CCER_CC3NP 0x00000800U
7410 #define TIM_CCER_CC4E 0x00001000U
7411 #define TIM_CCER_CC4P 0x00002000U
7412 #define TIM_CCER_CC4NP 0x00008000U
7413 #define TIM_CCER_CC5E 0x00010000U
7414 #define TIM_CCER_CC5P 0x00020000U
7415 #define TIM_CCER_CC6E 0x00100000U
7416 #define TIM_CCER_CC6P 0x00200000U
7419 /******************* Bit definition for TIM_CNT register ********************/
7420 #define TIM_CNT_CNT 0xFFFFU
7422 /******************* Bit definition for TIM_PSC register ********************/
7423 #define TIM_PSC_PSC 0xFFFFU
7425 /******************* Bit definition for TIM_ARR register ********************/
7426 #define TIM_ARR_ARR 0xFFFFU
7428 /******************* Bit definition for TIM_RCR register ********************/
7429 #define TIM_RCR_REP ((uint8_t)0xFFU)
7431 /******************* Bit definition for TIM_CCR1 register *******************/
7432 #define TIM_CCR1_CCR1 0xFFFFU
7434 /******************* Bit definition for TIM_CCR2 register *******************/
7435 #define TIM_CCR2_CCR2 0xFFFFU
7437 /******************* Bit definition for TIM_CCR3 register *******************/
7438 #define TIM_CCR3_CCR3 0xFFFFU
7440 /******************* Bit definition for TIM_CCR4 register *******************/
7441 #define TIM_CCR4_CCR4 0xFFFFU
7443 /******************* Bit definition for TIM_BDTR register *******************/
7444 #define TIM_BDTR_DTG 0x000000FFU
7445 #define TIM_BDTR_DTG_0 0x00000001U
7446 #define TIM_BDTR_DTG_1 0x00000002U
7447 #define TIM_BDTR_DTG_2 0x00000004U
7448 #define TIM_BDTR_DTG_3 0x00000008U
7449 #define TIM_BDTR_DTG_4 0x00000010U
7450 #define TIM_BDTR_DTG_5 0x00000020U
7451 #define TIM_BDTR_DTG_6 0x00000040U
7452 #define TIM_BDTR_DTG_7 0x00000080U
7454 #define TIM_BDTR_LOCK 0x00000300U
7455 #define TIM_BDTR_LOCK_0 0x00000100U
7456 #define TIM_BDTR_LOCK_1 0x00000200U
7458 #define TIM_BDTR_OSSI 0x00000400U
7459 #define TIM_BDTR_OSSR 0x00000800U
7460 #define TIM_BDTR_BKE 0x00001000U
7461 #define TIM_BDTR_BKP 0x00002000U
7462 #define TIM_BDTR_AOE 0x00004000U
7463 #define TIM_BDTR_MOE 0x00008000U
7464 #define TIM_BDTR_BKF 0x000F0000U
7465 #define TIM_BDTR_BK2F 0x00F00000U
7466 #define TIM_BDTR_BK2E 0x01000000U
7467 #define TIM_BDTR_BK2P 0x02000000U
7469 /******************* Bit definition for TIM_DCR register ********************/
7470 #define TIM_DCR_DBA 0x001FU
7471 #define TIM_DCR_DBA_0 0x0001U
7472 #define TIM_DCR_DBA_1 0x0002U
7473 #define TIM_DCR_DBA_2 0x0004U
7474 #define TIM_DCR_DBA_3 0x0008U
7475 #define TIM_DCR_DBA_4 0x0010U
7477 #define TIM_DCR_DBL 0x1F00U
7478 #define TIM_DCR_DBL_0 0x0100U
7479 #define TIM_DCR_DBL_1 0x0200U
7480 #define TIM_DCR_DBL_2 0x0400U
7481 #define TIM_DCR_DBL_3 0x0800U
7482 #define TIM_DCR_DBL_4 0x1000U
7484 /******************* Bit definition for TIM_DMAR register *******************/
7485 #define TIM_DMAR_DMAB 0xFFFFU
7487 /******************* Bit definition for TIM_OR regiter *********************/
7488 #define TIM_OR_TI4_RMP 0x00C0U
7489 #define TIM_OR_TI4_RMP_0 0x0040U
7490 #define TIM_OR_TI4_RMP_1 0x0080U
7491 #define TIM_OR_ITR1_RMP 0x0C00U
7492 #define TIM_OR_ITR1_RMP_0 0x0400U
7493 #define TIM_OR_ITR1_RMP_1 0x0800U
7495 /****************** Bit definition for TIM_CCMR3 register *******************/
7496 #define TIM_CCMR3_OC5FE 0x00000004U
7497 #define TIM_CCMR3_OC5PE 0x00000008U
7499 #define TIM_CCMR3_OC5M 0x00010070U
7500 #define TIM_CCMR3_OC5M_0 0x00000010U
7501 #define TIM_CCMR3_OC5M_1 0x00000020U
7502 #define TIM_CCMR3_OC5M_2 0x00000040U
7503 #define TIM_CCMR3_OC5M_3 0x00010000U
7505 #define TIM_CCMR3_OC5CE 0x00000080U
7507 #define TIM_CCMR3_OC6FE 0x00000400U
7508 #define TIM_CCMR3_OC6PE 0x00000800U
7510 #define TIM_CCMR3_OC6M 0x01007000U
7511 #define TIM_CCMR3_OC6M_0 0x00001000U
7512 #define TIM_CCMR3_OC6M_1 0x00002000U
7513 #define TIM_CCMR3_OC6M_2 0x00004000U
7514 #define TIM_CCMR3_OC6M_3 0x01000000U
7516 #define TIM_CCMR3_OC6CE 0x00008000U
7518 /******************* Bit definition for TIM_CCR5 register *******************/
7519 #define TIM_CCR5_CCR5 0xFFFFFFFFU
7520 #define TIM_CCR5_GC5C1 0x20000000U
7521 #define TIM_CCR5_GC5C2 0x40000000U
7522 #define TIM_CCR5_GC5C3 0x80000000U
7524 /******************* Bit definition for TIM_CCR6 register *******************/
7525 #define TIM_CCR6_CCR6 ((uint16_t)0xFFFFU)
7528 /******************************************************************************/
7529 /* */
7530 /* Low Power Timer (LPTIM) */
7531 /* */
7532 /******************************************************************************/
7533 /****************** Bit definition for LPTIM_ISR register *******************/
7534 #define LPTIM_ISR_CMPM 0x00000001U
7535 #define LPTIM_ISR_ARRM 0x00000002U
7536 #define LPTIM_ISR_EXTTRIG 0x00000004U
7537 #define LPTIM_ISR_CMPOK 0x00000008U
7538 #define LPTIM_ISR_ARROK 0x00000010U
7539 #define LPTIM_ISR_UP 0x00000020U
7540 #define LPTIM_ISR_DOWN 0x00000040U
7542 /****************** Bit definition for LPTIM_ICR register *******************/
7543 #define LPTIM_ICR_CMPMCF 0x00000001U
7544 #define LPTIM_ICR_ARRMCF 0x00000002U
7545 #define LPTIM_ICR_EXTTRIGCF 0x00000004U
7546 #define LPTIM_ICR_CMPOKCF 0x00000008U
7547 #define LPTIM_ICR_ARROKCF 0x00000010U
7548 #define LPTIM_ICR_UPCF 0x00000020U
7549 #define LPTIM_ICR_DOWNCF 0x00000040U
7551 /****************** Bit definition for LPTIM_IER register *******************/
7552 #define LPTIM_IER_CMPMIE 0x00000001U
7553 #define LPTIM_IER_ARRMIE 0x00000002U
7554 #define LPTIM_IER_EXTTRIGIE 0x00000004U
7555 #define LPTIM_IER_CMPOKIE 0x00000008U
7556 #define LPTIM_IER_ARROKIE 0x00000010U
7557 #define LPTIM_IER_UPIE 0x00000020U
7558 #define LPTIM_IER_DOWNIE 0x00000040U
7560 /****************** Bit definition for LPTIM_CFGR register*******************/
7561 #define LPTIM_CFGR_CKSEL 0x00000001U
7563 #define LPTIM_CFGR_CKPOL 0x00000006U
7564 #define LPTIM_CFGR_CKPOL_0 0x00000002U
7565 #define LPTIM_CFGR_CKPOL_1 0x00000004U
7567 #define LPTIM_CFGR_CKFLT 0x00000018U
7568 #define LPTIM_CFGR_CKFLT_0 0x00000008U
7569 #define LPTIM_CFGR_CKFLT_1 0x00000010U
7571 #define LPTIM_CFGR_TRGFLT 0x000000C0U
7572 #define LPTIM_CFGR_TRGFLT_0 0x00000040U
7573 #define LPTIM_CFGR_TRGFLT_1 0x00000080U
7575 #define LPTIM_CFGR_PRESC 0x00000E00U
7576 #define LPTIM_CFGR_PRESC_0 0x00000200U
7577 #define LPTIM_CFGR_PRESC_1 0x00000400U
7578 #define LPTIM_CFGR_PRESC_2 0x00000800U
7580 #define LPTIM_CFGR_TRIGSEL 0x0000E000U
7581 #define LPTIM_CFGR_TRIGSEL_0 0x00002000U
7582 #define LPTIM_CFGR_TRIGSEL_1 0x00004000U
7583 #define LPTIM_CFGR_TRIGSEL_2 0x00008000U
7585 #define LPTIM_CFGR_TRIGEN 0x00060000U
7586 #define LPTIM_CFGR_TRIGEN_0 0x00020000U
7587 #define LPTIM_CFGR_TRIGEN_1 0x00040000U
7589 #define LPTIM_CFGR_TIMOUT 0x00080000U
7590 #define LPTIM_CFGR_WAVE 0x00100000U
7591 #define LPTIM_CFGR_WAVPOL 0x00200000U
7592 #define LPTIM_CFGR_PRELOAD 0x00400000U
7593 #define LPTIM_CFGR_COUNTMODE 0x00800000U
7594 #define LPTIM_CFGR_ENC 0x01000000U
7596 /****************** Bit definition for LPTIM_CR register ********************/
7597 #define LPTIM_CR_ENABLE 0x00000001U
7598 #define LPTIM_CR_SNGSTRT 0x00000002U
7599 #define LPTIM_CR_CNTSTRT 0x00000004U
7601 /****************** Bit definition for LPTIM_CMP register *******************/
7602 #define LPTIM_CMP_CMP 0x0000FFFFU
7604 /****************** Bit definition for LPTIM_ARR register *******************/
7605 #define LPTIM_ARR_ARR 0x0000FFFFU
7607 /****************** Bit definition for LPTIM_CNT register *******************/
7608 #define LPTIM_CNT_CNT 0x0000FFFFU
7609 /******************************************************************************/
7610 /* */
7611 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
7612 /* */
7613 /******************************************************************************/
7614 /****************** Bit definition for USART_CR1 register *******************/
7615 #define USART_CR1_UE 0x00000001U
7616 #define USART_CR1_RE 0x00000004U
7617 #define USART_CR1_TE 0x00000008U
7618 #define USART_CR1_IDLEIE 0x00000010U
7619 #define USART_CR1_RXNEIE 0x00000020U
7620 #define USART_CR1_TCIE 0x00000040U
7621 #define USART_CR1_TXEIE 0x00000080U
7622 #define USART_CR1_PEIE 0x00000100U
7623 #define USART_CR1_PS 0x00000200U
7624 #define USART_CR1_PCE 0x00000400U
7625 #define USART_CR1_WAKE 0x00000800U
7626 #define USART_CR1_M 0x10001000U
7627 #define USART_CR1_M_0 0x00001000U
7628 #define USART_CR1_MME 0x00002000U
7629 #define USART_CR1_CMIE 0x00004000U
7630 #define USART_CR1_OVER8 0x00008000U
7631 #define USART_CR1_DEDT 0x001F0000U
7632 #define USART_CR1_DEDT_0 0x00010000U
7633 #define USART_CR1_DEDT_1 0x00020000U
7634 #define USART_CR1_DEDT_2 0x00040000U
7635 #define USART_CR1_DEDT_3 0x00080000U
7636 #define USART_CR1_DEDT_4 0x00100000U
7637 #define USART_CR1_DEAT 0x03E00000U
7638 #define USART_CR1_DEAT_0 0x00200000U
7639 #define USART_CR1_DEAT_1 0x00400000U
7640 #define USART_CR1_DEAT_2 0x00800000U
7641 #define USART_CR1_DEAT_3 0x01000000U
7642 #define USART_CR1_DEAT_4 0x02000000U
7643 #define USART_CR1_RTOIE 0x04000000U
7644 #define USART_CR1_EOBIE 0x08000000U
7645 #define USART_CR1_M_1 0x10000000U
7647 /****************** Bit definition for USART_CR2 register *******************/
7648 #define USART_CR2_ADDM7 0x00000010U
7649 #define USART_CR2_LBDL 0x00000020U
7650 #define USART_CR2_LBDIE 0x00000040U
7651 #define USART_CR2_LBCL 0x00000100U
7652 #define USART_CR2_CPHA 0x00000200U
7653 #define USART_CR2_CPOL 0x00000400U
7654 #define USART_CR2_CLKEN 0x00000800U
7655 #define USART_CR2_STOP 0x00003000U
7656 #define USART_CR2_STOP_0 0x00001000U
7657 #define USART_CR2_STOP_1 0x00002000U
7658 #define USART_CR2_LINEN 0x00004000U
7659 #define USART_CR2_SWAP 0x00008000U
7660 #define USART_CR2_RXINV 0x00010000U
7661 #define USART_CR2_TXINV 0x00020000U
7662 #define USART_CR2_DATAINV 0x00040000U
7663 #define USART_CR2_MSBFIRST 0x00080000U
7664 #define USART_CR2_ABREN 0x00100000U
7665 #define USART_CR2_ABRMODE 0x00600000U
7666 #define USART_CR2_ABRMODE_0 0x00200000U
7667 #define USART_CR2_ABRMODE_1 0x00400000U
7668 #define USART_CR2_RTOEN 0x00800000U
7669 #define USART_CR2_ADD 0xFF000000U
7671 /****************** Bit definition for USART_CR3 register *******************/
7672 #define USART_CR3_EIE 0x00000001U
7673 #define USART_CR3_IREN 0x00000002U
7674 #define USART_CR3_IRLP 0x00000004U
7675 #define USART_CR3_HDSEL 0x00000008U
7676 #define USART_CR3_NACK 0x00000010U
7677 #define USART_CR3_SCEN 0x00000020U
7678 #define USART_CR3_DMAR 0x00000040U
7679 #define USART_CR3_DMAT 0x00000080U
7680 #define USART_CR3_RTSE 0x00000100U
7681 #define USART_CR3_CTSE 0x00000200U
7682 #define USART_CR3_CTSIE 0x00000400U
7683 #define USART_CR3_ONEBIT 0x00000800U
7684 #define USART_CR3_OVRDIS 0x00001000U
7685 #define USART_CR3_DDRE 0x00002000U
7686 #define USART_CR3_DEM 0x00004000U
7687 #define USART_CR3_DEP 0x00008000U
7688 #define USART_CR3_SCARCNT 0x000E0000U
7689 #define USART_CR3_SCARCNT_0 0x00020000U
7690 #define USART_CR3_SCARCNT_1 0x00040000U
7691 #define USART_CR3_SCARCNT_2 0x00080000U
7694 /****************** Bit definition for USART_BRR register *******************/
7695 #define USART_BRR_DIV_FRACTION 0x000FU
7696 #define USART_BRR_DIV_MANTISSA 0xFFF0U
7698 /****************** Bit definition for USART_GTPR register ******************/
7699 #define USART_GTPR_PSC 0x00FFU
7700 #define USART_GTPR_GT 0xFF00U
7703 /******************* Bit definition for USART_RTOR register *****************/
7704 #define USART_RTOR_RTO 0x00FFFFFFU
7705 #define USART_RTOR_BLEN 0xFF000000U
7707 /******************* Bit definition for USART_RQR register ******************/
7708 #define USART_RQR_ABRRQ 0x0001U
7709 #define USART_RQR_SBKRQ 0x0002U
7710 #define USART_RQR_MMRQ 0x0004U
7711 #define USART_RQR_RXFRQ 0x0008U
7712 #define USART_RQR_TXFRQ 0x0010U
7714 /******************* Bit definition for USART_ISR register ******************/
7715 #define USART_ISR_PE 0x00000001U
7716 #define USART_ISR_FE 0x00000002U
7717 #define USART_ISR_NE 0x00000004U
7718 #define USART_ISR_ORE 0x00000008U
7719 #define USART_ISR_IDLE 0x00000010U
7720 #define USART_ISR_RXNE 0x00000020U
7721 #define USART_ISR_TC 0x00000040U
7722 #define USART_ISR_TXE 0x00000080U
7723 #define USART_ISR_LBDF 0x00000100U
7724 #define USART_ISR_CTSIF 0x00000200U
7725 #define USART_ISR_CTS 0x00000400U
7726 #define USART_ISR_RTOF 0x00000800U
7727 #define USART_ISR_EOBF 0x00001000U
7728 #define USART_ISR_ABRE 0x00004000U
7729 #define USART_ISR_ABRF 0x00008000U
7730 #define USART_ISR_BUSY 0x00010000U
7731 #define USART_ISR_CMF 0x00020000U
7732 #define USART_ISR_SBKF 0x00040000U
7733 #define USART_ISR_RWU 0x00080000U
7734 #define USART_ISR_WUF 0x00100000U
7735 #define USART_ISR_TEACK 0x00200000U
7736 #define USART_ISR_REACK 0x00400000U
7738 /* Legacy define */
7739 #define USART_ISR_LBD USART_ISR_LBDF
7740 
7741 /******************* Bit definition for USART_ICR register ******************/
7742 #define USART_ICR_PECF 0x00000001U
7743 #define USART_ICR_FECF 0x00000002U
7744 #define USART_ICR_NCF 0x00000004U
7745 #define USART_ICR_ORECF 0x00000008U
7746 #define USART_ICR_IDLECF 0x00000010U
7747 #define USART_ICR_TCCF 0x00000040U
7748 #define USART_ICR_LBDCF 0x00000100U
7749 #define USART_ICR_CTSCF 0x00000200U
7750 #define USART_ICR_RTOCF 0x00000800U
7751 #define USART_ICR_EOBCF 0x00001000U
7752 #define USART_ICR_CMCF 0x00020000U
7753 #define USART_ICR_WUCF 0x00100000U
7755 /******************* Bit definition for USART_RDR register ******************/
7756 #define USART_RDR_RDR 0x01FFU
7758 /******************* Bit definition for USART_TDR register ******************/
7759 #define USART_TDR_TDR 0x01FFU
7761 /******************************************************************************/
7762 /* */
7763 /* Window WATCHDOG */
7764 /* */
7765 /******************************************************************************/
7766 /******************* Bit definition for WWDG_CR register ********************/
7767 #define WWDG_CR_T 0x7FU
7768 #define WWDG_CR_T_0 0x01U
7769 #define WWDG_CR_T_1 0x02U
7770 #define WWDG_CR_T_2 0x04U
7771 #define WWDG_CR_T_3 0x08U
7772 #define WWDG_CR_T_4 0x10U
7773 #define WWDG_CR_T_5 0x20U
7774 #define WWDG_CR_T_6 0x40U
7776 /* Legacy defines */
7777 #define WWDG_CR_T0 WWDG_CR_T_0
7778 #define WWDG_CR_T1 WWDG_CR_T_1
7779 #define WWDG_CR_T2 WWDG_CR_T_2
7780 #define WWDG_CR_T3 WWDG_CR_T_3
7781 #define WWDG_CR_T4 WWDG_CR_T_4
7782 #define WWDG_CR_T5 WWDG_CR_T_5
7783 #define WWDG_CR_T6 WWDG_CR_T_6
7785 #define WWDG_CR_WDGA 0x80U
7787 /******************* Bit definition for WWDG_CFR register *******************/
7788 #define WWDG_CFR_W 0x007FU
7789 #define WWDG_CFR_W_0 0x0001U
7790 #define WWDG_CFR_W_1 0x0002U
7791 #define WWDG_CFR_W_2 0x0004U
7792 #define WWDG_CFR_W_3 0x0008U
7793 #define WWDG_CFR_W_4 0x0010U
7794 #define WWDG_CFR_W_5 0x0020U
7795 #define WWDG_CFR_W_6 0x0040U
7797 /* Legacy defines */
7798 #define WWDG_CFR_W0 WWDG_CFR_W_0
7799 #define WWDG_CFR_W1 WWDG_CFR_W_1
7800 #define WWDG_CFR_W2 WWDG_CFR_W_2
7801 #define WWDG_CFR_W3 WWDG_CFR_W_3
7802 #define WWDG_CFR_W4 WWDG_CFR_W_4
7803 #define WWDG_CFR_W5 WWDG_CFR_W_5
7804 #define WWDG_CFR_W6 WWDG_CFR_W_6
7806 #define WWDG_CFR_WDGTB 0x0180U
7807 #define WWDG_CFR_WDGTB_0 0x0080U
7808 #define WWDG_CFR_WDGTB_1 0x0100U
7810 /* Legacy defines */
7811 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
7812 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
7814 #define WWDG_CFR_EWI 0x0200U
7816 /******************* Bit definition for WWDG_SR register ********************/
7817 #define WWDG_SR_EWIF 0x01U
7819 /******************************************************************************/
7820 /* */
7821 /* DBG */
7822 /* */
7823 /******************************************************************************/
7824 /******************** Bit definition for DBGMCU_IDCODE register *************/
7825 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
7826 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
7827 
7828 /******************** Bit definition for DBGMCU_CR register *****************/
7829 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
7830 #define DBGMCU_CR_DBG_STOP 0x00000002U
7831 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
7832 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
7833 
7834 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
7835 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U
7836 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U
7838 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
7839 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
7840 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
7841 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
7842 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
7843 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
7844 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
7845 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
7846 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
7847 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
7848 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
7849 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
7850 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
7851 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
7852 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
7853 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
7854 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
7855 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
7856 
7857 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
7858 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
7859 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
7860 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
7861 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
7862 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
7863 
7864 /******************************************************************************/
7865 /* */
7866 /* Ethernet MAC Registers bits definitions */
7867 /* */
7868 /******************************************************************************/
7869 /* Bit definition for Ethernet MAC Control Register register */
7870 #define ETH_MACCR_WD 0x00800000U /* Watchdog disable */
7871 #define ETH_MACCR_JD 0x00400000U /* Jabber disable */
7872 #define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */
7873 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
7874 #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
7875 #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
7876 #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
7877 #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
7878 #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
7879 #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
7880 #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
7881 #define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */
7882 #define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */
7883 #define ETH_MACCR_ROD 0x00002000U /* Receive own disable */
7884 #define ETH_MACCR_LM 0x00001000U /* loopback mode */
7885 #define ETH_MACCR_DM 0x00000800U /* Duplex mode */
7886 #define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */
7887 #define ETH_MACCR_RD 0x00000200U /* Retry disable */
7888 #define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */
7889 #define ETH_MACCR_BL 0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling
7890  a transmission attempt during retries after a collision: 0 =< r <2^k */
7891 #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
7892 #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
7893 #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
7894 #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
7895 #define ETH_MACCR_DC 0x00000010U /* Defferal check */
7896 #define ETH_MACCR_TE 0x00000008U /* Transmitter enable */
7897 #define ETH_MACCR_RE 0x00000004U /* Receiver enable */
7898 
7899 /* Bit definition for Ethernet MAC Frame Filter Register */
7900 #define ETH_MACFFR_RA 0x80000000U /* Receive all */
7901 #define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */
7902 #define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */
7903 #define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */
7904 #define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */
7905 #define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */
7906 #define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
7907 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
7908 #define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */
7909 #define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */
7910 #define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */
7911 #define ETH_MACFFR_HM 0x00000004U /* Hash multicast */
7912 #define ETH_MACFFR_HU 0x00000002U /* Hash unicast */
7913 #define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */
7914 
7915 /* Bit definition for Ethernet MAC Hash Table High Register */
7916 #define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */
7917 
7918 /* Bit definition for Ethernet MAC Hash Table Low Register */
7919 #define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */
7920 
7921 /* Bit definition for Ethernet MAC MII Address Register */
7922 #define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */
7923 #define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */
7924 #define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */
7925 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
7926 #define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
7927 #define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
7928 #define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
7929 #define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
7930 #define ETH_MACMIIAR_MW 0x00000002U /* MII write */
7931 #define ETH_MACMIIAR_MB 0x00000001U /* MII busy */
7932 
7933 /* Bit definition for Ethernet MAC MII Data Register */
7934 #define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */
7935 
7936 /* Bit definition for Ethernet MAC Flow Control Register */
7937 #define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */
7938 #define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */
7939 #define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */
7940 #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
7941 #define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */
7942 #define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */
7943 #define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */
7944 #define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */
7945 #define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */
7946 #define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */
7947 #define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */
7948 
7949 /* Bit definition for Ethernet MAC VLAN Tag Register */
7950 #define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */
7951 #define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */
7952 
7953 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
7954 #define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */
7955 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
7956  Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
7957 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
7958  Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
7959  Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
7960  Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
7961  Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
7962  RSVD - Filter1 Command - RSVD - Filter0 Command
7963  Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
7964  Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
7965  Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
7966 
7967 /* Bit definition for Ethernet MAC PMT Control and Status Register */
7968 #define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
7969 #define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */
7970 #define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */
7971 #define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */
7972 #define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */
7973 #define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */
7974 #define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */
7975 
7976 /* Bit definition for Ethernet MAC Status Register */
7977 #define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */
7978 #define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */
7979 #define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */
7980 #define ETH_MACSR_MMCS 0x00000010U /* MMC status */
7981 #define ETH_MACSR_PMTS 0x00000008U /* PMT status */
7982 
7983 /* Bit definition for Ethernet MAC Interrupt Mask Register */
7984 #define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */
7985 #define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */
7986 
7987 /* Bit definition for Ethernet MAC Address0 High Register */
7988 #define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */
7989 
7990 /* Bit definition for Ethernet MAC Address0 Low Register */
7991 #define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */
7992 
7993 /* Bit definition for Ethernet MAC Address1 High Register */
7994 #define ETH_MACA1HR_AE 0x80000000U /* Address enable */
7995 #define ETH_MACA1HR_SA 0x40000000U /* Source address */
7996 #define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
7997  #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
7998  #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
7999  #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
8000  #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
8001  #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
8002  #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
8003 #define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */
8004 
8005 /* Bit definition for Ethernet MAC Address1 Low Register */
8006 #define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */
8007 
8008 /* Bit definition for Ethernet MAC Address2 High Register */
8009 #define ETH_MACA2HR_AE 0x80000000U /* Address enable */
8010 #define ETH_MACA2HR_SA 0x40000000U /* Source address */
8011 #define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */
8012  #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
8013  #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
8014  #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
8015  #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
8016  #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
8017  #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
8018 #define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */
8019 
8020 /* Bit definition for Ethernet MAC Address2 Low Register */
8021 #define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */
8022 
8023 /* Bit definition for Ethernet MAC Address3 High Register */
8024 #define ETH_MACA3HR_AE 0x80000000U /* Address enable */
8025 #define ETH_MACA3HR_SA 0x40000000U /* Source address */
8026 #define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */
8027  #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
8028  #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
8029  #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
8030  #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
8031  #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
8032  #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
8033 #define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */
8034 
8035 /* Bit definition for Ethernet MAC Address3 Low Register */
8036 #define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */
8037 
8038 /******************************************************************************/
8039 /* Ethernet MMC Registers bits definition */
8040 /******************************************************************************/
8041 
8042 /* Bit definition for Ethernet MMC Contol Register */
8043 #define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */
8044 #define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */
8045 #define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */
8046 #define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */
8047 #define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */
8048 #define ETH_MMCCR_CR 0x00000001U /* Counters Reset */
8049 
8050 /* Bit definition for Ethernet MMC Receive Interrupt Register */
8051 #define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
8052 #define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
8053 #define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
8054 
8055 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
8056 #define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
8057 #define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
8058 #define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
8059 
8060 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
8061 #define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
8062 #define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
8063 #define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
8064 
8065 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
8066 #define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
8067 #define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
8068 #define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
8069 
8070 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
8071 #define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
8072 
8073 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
8074 #define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
8075 
8076 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
8077 #define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */
8078 
8079 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
8080 #define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */
8081 
8082 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
8083 #define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
8084 
8085 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
8086 #define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */
8087 
8088 /******************************************************************************/
8089 /* Ethernet PTP Registers bits definition */
8090 /******************************************************************************/
8091 
8092 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
8093 #define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */
8094 #define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */
8095 #define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */
8096 #define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */
8097 #define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */
8098 #define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
8099 #define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
8100 #define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */
8101 #define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */
8102 
8103 #define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */
8104 #define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */
8105 #define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */
8106 #define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */
8107 #define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */
8108 #define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */
8109 
8110 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
8111 #define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */
8112 
8113 /* Bit definition for Ethernet PTP Time Stamp High Register */
8114 #define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */
8115 
8116 /* Bit definition for Ethernet PTP Time Stamp Low Register */
8117 #define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */
8118 #define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */
8119 
8120 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
8121 #define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */
8122 
8123 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
8124 #define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */
8125 #define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */
8126 
8127 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
8128 #define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */
8129 
8130 /* Bit definition for Ethernet PTP Target Time High Register */
8131 #define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */
8132 
8133 /* Bit definition for Ethernet PTP Target Time Low Register */
8134 #define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */
8135 
8136 /* Bit definition for Ethernet PTP Time Stamp Status Register */
8137 #define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */
8138 #define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */
8139 
8140 /******************************************************************************/
8141 /* Ethernet DMA Registers bits definition */
8142 /******************************************************************************/
8143 
8144 /* Bit definition for Ethernet DMA Bus Mode Register */
8145 #define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */
8146 #define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */
8147 #define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */
8148 #define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */
8149  #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
8150  #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
8151  #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
8152  #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
8153  #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
8154  #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
8155  #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
8156  #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
8157  #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
8158  #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
8159  #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
8160  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
8161 #define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */
8162 #define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */
8163  #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
8164  #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
8165  #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
8166  #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
8167 #define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */
8168  #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
8169  #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
8170  #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
8171  #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
8172  #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
8173  #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
8174  #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
8175  #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
8176  #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
8177  #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
8178  #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
8179  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
8180 #define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */
8181 #define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */
8182 #define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */
8183 #define ETH_DMABMR_SR 0x00000001U /* Software reset */
8184 
8185 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
8186 #define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */
8187 
8188 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
8189 #define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */
8190 
8191 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
8192 #define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */
8193 
8194 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
8195 #define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */
8196 
8197 /* Bit definition for Ethernet DMA Status Register */
8198 #define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */
8199 #define ETH_DMASR_PMTS 0x10000000U /* PMT status */
8200 #define ETH_DMASR_MMCS 0x08000000U /* MMC status */
8201 #define ETH_DMASR_EBS 0x03800000U /* Error bits status */
8202  /* combination with EBS[2:0] for GetFlagStatus function */
8203  #define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */
8204  #define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
8205  #define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
8206 #define ETH_DMASR_TPS 0x00700000U /* Transmit process state */
8207  #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
8208  #define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */
8209  #define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */
8210  #define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */
8211  #define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */
8212  #define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */
8213 #define ETH_DMASR_RPS 0x000E0000U /* Receive process state */
8214  #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
8215  #define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */
8216  #define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */
8217  #define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */
8218  #define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */
8219  #define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */
8220 #define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */
8221 #define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */
8222 #define ETH_DMASR_ERS 0x00004000U /* Early receive status */
8223 #define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */
8224 #define ETH_DMASR_ETS 0x00000400U /* Early transmit status */
8225 #define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */
8226 #define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */
8227 #define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */
8228 #define ETH_DMASR_RS 0x00000040U /* Receive status */
8229 #define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */
8230 #define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */
8231 #define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */
8232 #define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */
8233 #define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */
8234 #define ETH_DMASR_TS 0x00000001U /* Transmit status */
8235 
8236 /* Bit definition for Ethernet DMA Operation Mode Register */
8237 #define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
8238 #define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */
8239 #define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */
8240 #define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */
8241 #define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */
8242 #define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */
8243  #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
8244  #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
8245  #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
8246  #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
8247  #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
8248  #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
8249  #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
8250  #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
8251 #define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */
8252 #define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */
8253 #define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */
8254 #define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */
8255  #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
8256  #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
8257  #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
8258  #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
8259 #define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */
8260 #define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */
8261 
8262 /* Bit definition for Ethernet DMA Interrupt Enable Register */
8263 #define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */
8264 #define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */
8265 #define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */
8266 #define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */
8267 #define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */
8268 #define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */
8269 #define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */
8270 #define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */
8271 #define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */
8272 #define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */
8273 #define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */
8274 #define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */
8275 #define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */
8276 #define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */
8277 #define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */
8278 
8279 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
8280 #define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */
8281 #define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */
8282 #define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */
8283 #define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */
8284 
8285 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
8286 #define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */
8287 
8288 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
8289 #define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */
8290 
8291 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
8292 #define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */
8293 
8294 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
8295 #define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */
8296 
8297 /******************************************************************************/
8298 /* */
8299 /* USB_OTG */
8300 /* */
8301 /******************************************************************************/
8302 /******************** Bit definition for USB_OTG_GOTGCTL register ********************/
8303 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U
8304 #define USB_OTG_GOTGCTL_SRQ 0x00000002U
8305 #define USB_OTG_GOTGCTL_VBVALOEN 0x00000004U
8306 #define USB_OTG_GOTGCTL_VBVALOVAL 0x00000008U
8307 #define USB_OTG_GOTGCTL_AVALOEN 0x00000010U
8308 #define USB_OTG_GOTGCTL_AVALOVAL 0x00000020U
8309 #define USB_OTG_GOTGCTL_BVALOEN 0x00000040U
8310 #define USB_OTG_GOTGCTL_BVALOVAL 0x00000080U
8311 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U
8312 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U
8313 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U
8314 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U
8315 #define USB_OTG_GOTGCTL_EHEN 0x00001000U
8316 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U
8317 #define USB_OTG_GOTGCTL_DBCT 0x00020000U
8318 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U
8319 #define USB_OTG_GOTGCTL_BSESVLD 0x00080000U
8320 #define USB_OTG_GOTGCTL_OTGVER 0x00100000U
8322 /******************** Bit definition for USB_OTG_HCFG register ********************/
8323 #define USB_OTG_HCFG_FSLSPCS 0x00000003U
8324 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U
8325 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U
8326 #define USB_OTG_HCFG_FSLSS 0x00000004U
8328 /******************** Bit definition for USB_OTG_DCFG register ********************/
8329 #define USB_OTG_DCFG_DSPD 0x00000003U
8330 #define USB_OTG_DCFG_DSPD_0 0x00000001U
8331 #define USB_OTG_DCFG_DSPD_1 0x00000002U
8332 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U
8334 #define USB_OTG_DCFG_DAD 0x000007F0U
8335 #define USB_OTG_DCFG_DAD_0 0x00000010U
8336 #define USB_OTG_DCFG_DAD_1 0x00000020U
8337 #define USB_OTG_DCFG_DAD_2 0x00000040U
8338 #define USB_OTG_DCFG_DAD_3 0x00000080U
8339 #define USB_OTG_DCFG_DAD_4 0x00000100U
8340 #define USB_OTG_DCFG_DAD_5 0x00000200U
8341 #define USB_OTG_DCFG_DAD_6 0x00000400U
8343 #define USB_OTG_DCFG_PFIVL 0x00001800U
8344 #define USB_OTG_DCFG_PFIVL_0 0x00000800U
8345 #define USB_OTG_DCFG_PFIVL_1 0x00001000U
8347 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U
8348 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U
8349 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U
8351 /******************** Bit definition for USB_OTG_PCGCR register ********************/
8352 #define USB_OTG_PCGCR_STPPCLK 0x00000001U
8353 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U
8354 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U
8356 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
8357 #define USB_OTG_GOTGINT_SEDET 0x00000004U
8358 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U
8359 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U
8360 #define USB_OTG_GOTGINT_HNGDET 0x00020000U
8361 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U
8362 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U
8363 #define USB_OTG_GOTGINT_IDCHNG 0x00100000U
8365 /******************** Bit definition for USB_OTG_DCTL register ********************/
8366 #define USB_OTG_DCTL_RWUSIG 0x00000001U
8367 #define USB_OTG_DCTL_SDIS 0x00000002U
8368 #define USB_OTG_DCTL_GINSTS 0x00000004U
8369 #define USB_OTG_DCTL_GONSTS 0x00000008U
8371 #define USB_OTG_DCTL_TCTL 0x00000070U
8372 #define USB_OTG_DCTL_TCTL_0 0x00000010U
8373 #define USB_OTG_DCTL_TCTL_1 0x00000020U
8374 #define USB_OTG_DCTL_TCTL_2 0x00000040U
8375 #define USB_OTG_DCTL_SGINAK 0x00000080U
8376 #define USB_OTG_DCTL_CGINAK 0x00000100U
8377 #define USB_OTG_DCTL_SGONAK 0x00000200U
8378 #define USB_OTG_DCTL_CGONAK 0x00000400U
8379 #define USB_OTG_DCTL_POPRGDNE 0x00000800U
8381 /******************** Bit definition for USB_OTG_HFIR register ********************/
8382 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU
8384 /******************** Bit definition for USB_OTG_HFNUM register ********************/
8385 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU
8386 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U
8388 /******************** Bit definition for USB_OTG_DSTS register ********************/
8389 #define USB_OTG_DSTS_SUSPSTS 0x00000001U
8391 #define USB_OTG_DSTS_ENUMSPD 0x00000006U
8392 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U
8393 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U
8394 #define USB_OTG_DSTS_EERR 0x00000008U
8395 #define USB_OTG_DSTS_FNSOF 0x003FFF00U
8397 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
8398 #define USB_OTG_GAHBCFG_GINT 0x00000001U
8399 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU
8400 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U
8401 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U
8402 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U
8403 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U
8404 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U
8405 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U
8406 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U
8408 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
8409 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U
8410 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U
8411 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U
8412 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U
8413 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U
8414 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U
8415 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U
8416 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U
8417 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U
8418 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U
8419 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U
8420 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U
8421 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U
8422 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U
8423 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U
8424 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U
8425 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U
8426 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U
8427 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U
8428 #define USB_OTG_GUSBCFG_PCCI 0x00800000U
8429 #define USB_OTG_GUSBCFG_PTCI 0x01000000U
8430 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U
8431 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U
8432 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U
8433 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U
8435 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
8436 #define USB_OTG_GRSTCTL_CSRST 0x00000001U
8437 #define USB_OTG_GRSTCTL_HSRST 0x00000002U
8438 #define USB_OTG_GRSTCTL_FCRST 0x00000004U
8439 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U
8440 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U
8441 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U
8442 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U
8443 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U
8444 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U
8445 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U
8446 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U
8447 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U
8448 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U
8450 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
8451 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U
8452 #define USB_OTG_DIEPMSK_EPDM 0x00000002U
8453 #define USB_OTG_DIEPMSK_TOM 0x00000008U
8454 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U
8455 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U
8456 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U
8457 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U
8458 #define USB_OTG_DIEPMSK_BIM 0x00000200U
8460 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
8461 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU
8462 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U
8463 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U
8464 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U
8465 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U
8466 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U
8467 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U
8468 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U
8469 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U
8470 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U
8472 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U
8473 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U
8474 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U
8475 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U
8476 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U
8477 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U
8478 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U
8479 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U
8480 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U
8482 /******************** Bit definition for USB_OTG_HAINT register ********************/
8483 #define USB_OTG_HAINT_HAINT 0x0000FFFFU
8485 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
8486 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U
8487 #define USB_OTG_DOEPMSK_EPDM 0x00000002U
8488 #define USB_OTG_DOEPMSK_STUPM 0x00000008U
8489 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U
8490 #define USB_OTG_DOEPMSK_OTEPSPRM 0x00000020U
8491 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U
8492 #define USB_OTG_DOEPMSK_OPEM 0x00000100U
8493 #define USB_OTG_DOEPMSK_BOIM 0x00000200U
8495 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
8496 #define USB_OTG_GINTSTS_CMOD 0x00000001U
8497 #define USB_OTG_GINTSTS_MMIS 0x00000002U
8498 #define USB_OTG_GINTSTS_OTGINT 0x00000004U
8499 #define USB_OTG_GINTSTS_SOF 0x00000008U
8500 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U
8501 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U
8502 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U
8503 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U
8504 #define USB_OTG_GINTSTS_ESUSP 0x00000400U
8505 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U
8506 #define USB_OTG_GINTSTS_USBRST 0x00001000U
8507 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U
8508 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U
8509 #define USB_OTG_GINTSTS_EOPF 0x00008000U
8510 #define USB_OTG_GINTSTS_IEPINT 0x00040000U
8511 #define USB_OTG_GINTSTS_OEPINT 0x00080000U
8512 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U
8513 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U
8514 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U
8515 #define USB_OTG_GINTSTS_RSTDET 0x00800000U
8516 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U
8517 #define USB_OTG_GINTSTS_HCINT 0x02000000U
8518 #define USB_OTG_GINTSTS_PTXFE 0x04000000U
8519 #define USB_OTG_GINTSTS_LPMINT 0x08000000U
8520 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U
8521 #define USB_OTG_GINTSTS_DISCINT 0x20000000U
8522 #define USB_OTG_GINTSTS_SRQINT 0x40000000U
8523 #define USB_OTG_GINTSTS_WKUINT 0x80000000U
8525 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
8526 #define USB_OTG_GINTMSK_MMISM 0x00000002U
8527 #define USB_OTG_GINTMSK_OTGINT 0x00000004U
8528 #define USB_OTG_GINTMSK_SOFM 0x00000008U
8529 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U
8530 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U
8531 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U
8532 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U
8533 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U
8534 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U
8535 #define USB_OTG_GINTMSK_USBRST 0x00001000U
8536 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U
8537 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U
8538 #define USB_OTG_GINTMSK_EOPFM 0x00008000U
8539 #define USB_OTG_GINTMSK_EPMISM 0x00020000U
8540 #define USB_OTG_GINTMSK_IEPINT 0x00040000U
8541 #define USB_OTG_GINTMSK_OEPINT 0x00080000U
8542 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U
8543 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U
8544 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U
8545 #define USB_OTG_GINTMSK_RSTDEM 0x00800000U
8546 #define USB_OTG_GINTMSK_PRTIM 0x01000000U
8547 #define USB_OTG_GINTMSK_HCIM 0x02000000U
8548 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U
8549 #define USB_OTG_GINTMSK_LPMINTM 0x08000000U
8550 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U
8551 #define USB_OTG_GINTMSK_DISCINT 0x20000000U
8552 #define USB_OTG_GINTMSK_SRQIM 0x40000000U
8553 #define USB_OTG_GINTMSK_WUIM 0x80000000U
8555 /******************** Bit definition for USB_OTG_DAINT register ********************/
8556 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU
8557 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U
8559 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
8560 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU
8562 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
8563 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU
8564 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U
8565 #define USB_OTG_GRXSTSP_DPID 0x00018000U
8566 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U
8568 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
8569 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU
8570 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U
8572 /******************** Bit definition for OTG register ********************/
8573 
8574 #define USB_OTG_CHNUM 0x0000000FU
8575 #define USB_OTG_CHNUM_0 0x00000001U
8576 #define USB_OTG_CHNUM_1 0x00000002U
8577 #define USB_OTG_CHNUM_2 0x00000004U
8578 #define USB_OTG_CHNUM_3 0x00000008U
8579 #define USB_OTG_BCNT 0x00007FF0U
8581 #define USB_OTG_DPID 0x00018000U
8582 #define USB_OTG_DPID_0 0x00008000U
8583 #define USB_OTG_DPID_1 0x00010000U
8585 #define USB_OTG_PKTSTS 0x001E0000U
8586 #define USB_OTG_PKTSTS_0 0x00020000U
8587 #define USB_OTG_PKTSTS_1 0x00040000U
8588 #define USB_OTG_PKTSTS_2 0x00080000U
8589 #define USB_OTG_PKTSTS_3 0x00100000U
8591 #define USB_OTG_EPNUM 0x0000000FU
8592 #define USB_OTG_EPNUM_0 0x00000001U
8593 #define USB_OTG_EPNUM_1 0x00000002U
8594 #define USB_OTG_EPNUM_2 0x00000004U
8595 #define USB_OTG_EPNUM_3 0x00000008U
8597 #define USB_OTG_FRMNUM 0x01E00000U
8598 #define USB_OTG_FRMNUM_0 0x00200000U
8599 #define USB_OTG_FRMNUM_1 0x00400000U
8600 #define USB_OTG_FRMNUM_2 0x00800000U
8601 #define USB_OTG_FRMNUM_3 0x01000000U
8603 /******************** Bit definition for OTG register ********************/
8604 
8605 #define USB_OTG_CHNUM 0x0000000FU
8606 #define USB_OTG_CHNUM_0 0x00000001U
8607 #define USB_OTG_CHNUM_1 0x00000002U
8608 #define USB_OTG_CHNUM_2 0x00000004U
8609 #define USB_OTG_CHNUM_3 0x00000008U
8610 #define USB_OTG_BCNT 0x00007FF0U
8612 #define USB_OTG_DPID 0x00018000U
8613 #define USB_OTG_DPID_0 0x00008000U
8614 #define USB_OTG_DPID_1 0x00010000U
8616 #define USB_OTG_PKTSTS 0x001E0000U
8617 #define USB_OTG_PKTSTS_0 0x00020000U
8618 #define USB_OTG_PKTSTS_1 0x00040000U
8619 #define USB_OTG_PKTSTS_2 0x00080000U
8620 #define USB_OTG_PKTSTS_3 0x00100000U
8622 #define USB_OTG_EPNUM 0x0000000FU
8623 #define USB_OTG_EPNUM_0 0x00000001U
8624 #define USB_OTG_EPNUM_1 0x00000002U
8625 #define USB_OTG_EPNUM_2 0x00000004U
8626 #define USB_OTG_EPNUM_3 0x00000008U
8628 #define USB_OTG_FRMNUM 0x01E00000U
8629 #define USB_OTG_FRMNUM_0 0x00200000U
8630 #define USB_OTG_FRMNUM_1 0x00400000U
8631 #define USB_OTG_FRMNUM_2 0x00800000U
8632 #define USB_OTG_FRMNUM_3 0x01000000U
8634 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
8635 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU
8637 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
8638 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU
8640 /******************** Bit definition for OTG register ********************/
8641 #define USB_OTG_NPTXFSA 0x0000FFFFU
8642 #define USB_OTG_NPTXFD 0xFFFF0000U
8643 #define USB_OTG_TX0FSA 0x0000FFFFU
8644 #define USB_OTG_TX0FD 0xFFFF0000U
8646 /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
8647 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU
8649 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
8650 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU
8652 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U
8653 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U
8654 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U
8655 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U
8656 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U
8657 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U
8658 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U
8659 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U
8660 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U
8662 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U
8663 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U
8664 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U
8665 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U
8666 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U
8667 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U
8668 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U
8669 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U
8671 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
8672 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U
8673 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U
8675 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU
8676 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U
8677 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U
8678 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U
8679 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U
8680 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U
8681 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U
8682 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U
8683 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U
8684 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U
8685 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U
8687 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U
8688 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U
8689 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U
8690 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U
8691 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U
8692 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U
8693 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U
8694 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U
8695 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U
8696 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U
8697 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U
8699 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
8700 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU
8702 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
8703 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U
8704 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U
8706 /******************** Bit definition for USB_OTG_GCCFG register ********************/
8707 #define USB_OTG_GCCFG_PWRDWN 0x00010000U
8708 #define USB_OTG_GCCFG_VBDEN 0x00200000U
8710 /******************** Bit definition for USB_OTG_GPWRDN) register ********************/
8711 #define USB_OTG_GPWRDN_ADPMEN 0x00000001U
8712 #define USB_OTG_GPWRDN_ADPIF 0x00800000U
8714 /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
8715 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U
8716 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U
8718 /******************** Bit definition for USB_OTG_CID register ********************/
8719 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU
8721 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
8722 #define USB_OTG_GLPMCFG_LPMEN 0x00000001U
8723 #define USB_OTG_GLPMCFG_LPMACK 0x00000002U
8724 #define USB_OTG_GLPMCFG_BESL 0x0000003CU
8725 #define USB_OTG_GLPMCFG_REMWAKE 0x00000040U
8726 #define USB_OTG_GLPMCFG_L1SSEN 0x00000080U
8727 #define USB_OTG_GLPMCFG_BESLTHRS 0x00000F00U
8728 #define USB_OTG_GLPMCFG_L1DSEN 0x00001000U
8729 #define USB_OTG_GLPMCFG_LPMRSP 0x00006000U
8730 #define USB_OTG_GLPMCFG_SLPSTS 0x00008000U
8731 #define USB_OTG_GLPMCFG_L1RSMOK 0x00010000U
8732 #define USB_OTG_GLPMCFG_LPMCHIDX 0x001E0000U
8733 #define USB_OTG_GLPMCFG_LPMRCNT 0x00E00000U
8734 #define USB_OTG_GLPMCFG_SNDLPM 0x01000000U
8735 #define USB_OTG_GLPMCFG_LPMRCNTSTS 0x0E000000U
8736 #define USB_OTG_GLPMCFG_ENBESL 0x10000000U
8738 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
8739 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U
8740 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U
8741 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U
8742 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U
8743 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U
8744 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U
8745 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U
8746 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U
8747 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U
8749 /******************** Bit definition for USB_OTG_HPRT register ********************/
8750 #define USB_OTG_HPRT_PCSTS 0x00000001U
8751 #define USB_OTG_HPRT_PCDET 0x00000002U
8752 #define USB_OTG_HPRT_PENA 0x00000004U
8753 #define USB_OTG_HPRT_PENCHNG 0x00000008U
8754 #define USB_OTG_HPRT_POCA 0x00000010U
8755 #define USB_OTG_HPRT_POCCHNG 0x00000020U
8756 #define USB_OTG_HPRT_PRES 0x00000040U
8757 #define USB_OTG_HPRT_PSUSP 0x00000080U
8758 #define USB_OTG_HPRT_PRST 0x00000100U
8760 #define USB_OTG_HPRT_PLSTS 0x00000C00U
8761 #define USB_OTG_HPRT_PLSTS_0 0x00000400U
8762 #define USB_OTG_HPRT_PLSTS_1 0x00000800U
8763 #define USB_OTG_HPRT_PPWR 0x00001000U
8765 #define USB_OTG_HPRT_PTCTL 0x0001E000U
8766 #define USB_OTG_HPRT_PTCTL_0 0x00002000U
8767 #define USB_OTG_HPRT_PTCTL_1 0x00004000U
8768 #define USB_OTG_HPRT_PTCTL_2 0x00008000U
8769 #define USB_OTG_HPRT_PTCTL_3 0x00010000U
8771 #define USB_OTG_HPRT_PSPD 0x00060000U
8772 #define USB_OTG_HPRT_PSPD_0 0x00020000U
8773 #define USB_OTG_HPRT_PSPD_1 0x00040000U
8775 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
8776 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U
8777 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U
8778 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U
8779 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U
8780 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U
8781 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U
8782 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U
8783 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U
8784 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U
8785 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U
8786 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U
8788 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
8789 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU
8790 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U
8792 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
8793 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU
8794 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U
8795 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U
8796 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U
8798 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U
8799 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U
8800 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U
8801 #define USB_OTG_DIEPCTL_STALL 0x00200000U
8803 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U
8804 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U
8805 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U
8806 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U
8807 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U
8808 #define USB_OTG_DIEPCTL_CNAK 0x04000000U
8809 #define USB_OTG_DIEPCTL_SNAK 0x08000000U
8810 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U
8811 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U
8812 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U
8813 #define USB_OTG_DIEPCTL_EPENA 0x80000000U
8815 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
8816 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU
8818 #define USB_OTG_HCCHAR_EPNUM 0x00007800U
8819 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U
8820 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U
8821 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U
8822 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U
8823 #define USB_OTG_HCCHAR_EPDIR 0x00008000U
8824 #define USB_OTG_HCCHAR_LSDEV 0x00020000U
8826 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U
8827 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U
8828 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U
8830 #define USB_OTG_HCCHAR_MC 0x00300000U
8831 #define USB_OTG_HCCHAR_MC_0 0x00100000U
8832 #define USB_OTG_HCCHAR_MC_1 0x00200000U
8834 #define USB_OTG_HCCHAR_DAD 0x1FC00000U
8835 #define USB_OTG_HCCHAR_DAD_0 0x00400000U
8836 #define USB_OTG_HCCHAR_DAD_1 0x00800000U
8837 #define USB_OTG_HCCHAR_DAD_2 0x01000000U
8838 #define USB_OTG_HCCHAR_DAD_3 0x02000000U
8839 #define USB_OTG_HCCHAR_DAD_4 0x04000000U
8840 #define USB_OTG_HCCHAR_DAD_5 0x08000000U
8841 #define USB_OTG_HCCHAR_DAD_6 0x10000000U
8842 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U
8843 #define USB_OTG_HCCHAR_CHDIS 0x40000000U
8844 #define USB_OTG_HCCHAR_CHENA 0x80000000U
8846 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
8847 
8848 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU
8849 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U
8850 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U
8851 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U
8852 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U
8853 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U
8854 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U
8855 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U
8857 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U
8858 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U
8859 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U
8860 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U
8861 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U
8862 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U
8863 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U
8864 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U
8866 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U
8867 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U
8868 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U
8869 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U
8870 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U
8872 /******************** Bit definition for USB_OTG_HCINT register ********************/
8873 #define USB_OTG_HCINT_XFRC 0x00000001U
8874 #define USB_OTG_HCINT_CHH 0x00000002U
8875 #define USB_OTG_HCINT_AHBERR 0x00000004U
8876 #define USB_OTG_HCINT_STALL 0x00000008U
8877 #define USB_OTG_HCINT_NAK 0x00000010U
8878 #define USB_OTG_HCINT_ACK 0x00000020U
8879 #define USB_OTG_HCINT_NYET 0x00000040U
8880 #define USB_OTG_HCINT_TXERR 0x00000080U
8881 #define USB_OTG_HCINT_BBERR 0x00000100U
8882 #define USB_OTG_HCINT_FRMOR 0x00000200U
8883 #define USB_OTG_HCINT_DTERR 0x00000400U
8885 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
8886 #define USB_OTG_DIEPINT_XFRC 0x00000001U
8887 #define USB_OTG_DIEPINT_EPDISD 0x00000002U
8888 #define USB_OTG_DIEPINT_TOC 0x00000008U
8889 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U
8890 #define USB_OTG_DIEPINT_INEPNE 0x00000040U
8891 #define USB_OTG_DIEPINT_TXFE 0x00000080U
8892 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U
8893 #define USB_OTG_DIEPINT_BNA 0x00000200U
8894 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U
8895 #define USB_OTG_DIEPINT_BERR 0x00001000U
8896 #define USB_OTG_DIEPINT_NAK 0x00002000U
8898 /******************** Bit definition for USB_OTG_HCINTMSK register ********************/
8899 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U
8900 #define USB_OTG_HCINTMSK_CHHM 0x00000002U
8901 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U
8902 #define USB_OTG_HCINTMSK_STALLM 0x00000008U
8903 #define USB_OTG_HCINTMSK_NAKM 0x00000010U
8904 #define USB_OTG_HCINTMSK_ACKM 0x00000020U
8905 #define USB_OTG_HCINTMSK_NYET 0x00000040U
8906 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U
8907 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U
8908 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U
8909 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U
8911 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
8912 
8913 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU
8914 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U
8915 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U
8916 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
8917 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU
8918 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U
8919 #define USB_OTG_HCTSIZ_DOPING 0x80000000U
8920 #define USB_OTG_HCTSIZ_DPID 0x60000000U
8921 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U
8922 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U
8924 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
8925 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU
8927 /******************** Bit definition for USB_OTG_HCDMA register ********************/
8928 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU
8930 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
8931 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU
8933 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
8934 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU
8935 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U
8937 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
8938 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU
8939 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U
8940 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U
8941 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U
8942 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U
8943 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U
8944 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U
8945 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U
8946 #define USB_OTG_DOEPCTL_SNPM 0x00100000U
8947 #define USB_OTG_DOEPCTL_STALL 0x00200000U
8948 #define USB_OTG_DOEPCTL_CNAK 0x04000000U
8949 #define USB_OTG_DOEPCTL_SNAK 0x08000000U
8950 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U
8951 #define USB_OTG_DOEPCTL_EPENA 0x80000000U
8953 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
8954 #define USB_OTG_DOEPINT_XFRC 0x00000001U
8955 #define USB_OTG_DOEPINT_EPDISD 0x00000002U
8956 #define USB_OTG_DOEPINT_STUP 0x00000008U
8957 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U
8958 #define USB_OTG_DOEPINT_OTEPSPR 0x00000020U
8959 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U
8960 #define USB_OTG_DOEPINT_NYET 0x00004000U
8962 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
8963 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU
8964 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U
8966 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U
8967 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U
8968 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U
8970 /******************** Bit definition for PCGCCTL register ********************/
8971 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U
8972 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U
8973 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U
8989 /******************************* ADC Instances ********************************/
8990 #define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
8991  ((__INSTANCE__) == ADC2) || \
8992  ((__INSTANCE__) == ADC3))
8993 
8994 /******************************* CAN Instances ********************************/
8995 #define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
8996  ((__INSTANCE__) == CAN2))
8997 /******************************* CRC Instances ********************************/
8998 #define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
8999 
9000 /******************************* DAC Instances ********************************/
9001 #define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)
9002 
9003 /******************************* DCMI Instances *******************************/
9004 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
9005 
9006 
9007 /******************************* DMA2D Instances *******************************/
9008 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
9009 
9010 /******************************** DMA Instances *******************************/
9011 #define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
9012  ((__INSTANCE__) == DMA1_Stream1) || \
9013  ((__INSTANCE__) == DMA1_Stream2) || \
9014  ((__INSTANCE__) == DMA1_Stream3) || \
9015  ((__INSTANCE__) == DMA1_Stream4) || \
9016  ((__INSTANCE__) == DMA1_Stream5) || \
9017  ((__INSTANCE__) == DMA1_Stream6) || \
9018  ((__INSTANCE__) == DMA1_Stream7) || \
9019  ((__INSTANCE__) == DMA2_Stream0) || \
9020  ((__INSTANCE__) == DMA2_Stream1) || \
9021  ((__INSTANCE__) == DMA2_Stream2) || \
9022  ((__INSTANCE__) == DMA2_Stream3) || \
9023  ((__INSTANCE__) == DMA2_Stream4) || \
9024  ((__INSTANCE__) == DMA2_Stream5) || \
9025  ((__INSTANCE__) == DMA2_Stream6) || \
9026  ((__INSTANCE__) == DMA2_Stream7))
9027 
9028 /******************************* GPIO Instances *******************************/
9029 #define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
9030  ((__INSTANCE__) == GPIOB) || \
9031  ((__INSTANCE__) == GPIOC) || \
9032  ((__INSTANCE__) == GPIOD) || \
9033  ((__INSTANCE__) == GPIOE) || \
9034  ((__INSTANCE__) == GPIOF) || \
9035  ((__INSTANCE__) == GPIOG) || \
9036  ((__INSTANCE__) == GPIOH) || \
9037  ((__INSTANCE__) == GPIOI) || \
9038  ((__INSTANCE__) == GPIOJ) || \
9039  ((__INSTANCE__) == GPIOK))
9040 
9041 #define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
9042  ((__INSTANCE__) == GPIOB) || \
9043  ((__INSTANCE__) == GPIOC) || \
9044  ((__INSTANCE__) == GPIOD) || \
9045  ((__INSTANCE__) == GPIOE) || \
9046  ((__INSTANCE__) == GPIOF) || \
9047  ((__INSTANCE__) == GPIOG) || \
9048  ((__INSTANCE__) == GPIOH) || \
9049  ((__INSTANCE__) == GPIOI) || \
9050  ((__INSTANCE__) == GPIOJ) || \
9051  ((__INSTANCE__) == GPIOK))
9052 
9053 /****************************** CEC Instances *********************************/
9054 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
9055 
9056 /****************************** QSPI Instances *********************************/
9057 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
9058 
9059 
9060 /******************************** I2C Instances *******************************/
9061 #define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
9062  ((__INSTANCE__) == I2C2) || \
9063  ((__INSTANCE__) == I2C3) || \
9064  ((__INSTANCE__) == I2C4))
9065 
9066 /******************************** I2S Instances *******************************/
9067 #define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
9068  ((__INSTANCE__) == SPI2) || \
9069  ((__INSTANCE__) == SPI3))
9070 
9071 /******************************* LPTIM Instances ********************************/
9072 #define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
9073 
9074 /****************************** LTDC Instances ********************************/
9075 #define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)
9076 
9077 
9078 
9079 /******************************* RNG Instances ********************************/
9080 #define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
9081 
9082 /****************************** RTC Instances *********************************/
9083 #define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)
9084 
9085 /******************************* SAI Instances ********************************/
9086 #define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
9087  ((__PERIPH__) == SAI1_Block_B) || \
9088  ((__PERIPH__) == SAI2_Block_A) || \
9089  ((__PERIPH__) == SAI2_Block_B))
9090 /* Legacy define */
9091 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
9092 
9093 /******************************** SDMMC Instances *******************************/
9094 #define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SDMMC1)
9095 
9096 /****************************** SPDIFRX Instances *********************************/
9097 #define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
9098 
9099 /******************************** SPI Instances *******************************/
9100 #define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
9101  ((__INSTANCE__) == SPI2) || \
9102  ((__INSTANCE__) == SPI3) || \
9103  ((__INSTANCE__) == SPI4) || \
9104  ((__INSTANCE__) == SPI5) || \
9105  ((__INSTANCE__) == SPI6))
9106 
9107 /****************** TIM Instances : All supported instances *******************/
9108 #define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9109  ((__INSTANCE__) == TIM2) || \
9110  ((__INSTANCE__) == TIM3) || \
9111  ((__INSTANCE__) == TIM4) || \
9112  ((__INSTANCE__) == TIM5) || \
9113  ((__INSTANCE__) == TIM6) || \
9114  ((__INSTANCE__) == TIM7) || \
9115  ((__INSTANCE__) == TIM8) || \
9116  ((__INSTANCE__) == TIM9) || \
9117  ((__INSTANCE__) == TIM10) || \
9118  ((__INSTANCE__) == TIM11) || \
9119  ((__INSTANCE__) == TIM12) || \
9120  ((__INSTANCE__) == TIM13) || \
9121  ((__INSTANCE__) == TIM14))
9122 
9123 /************* TIM Instances : at least 1 capture/compare channel *************/
9124 #define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9125  ((__INSTANCE__) == TIM2) || \
9126  ((__INSTANCE__) == TIM3) || \
9127  ((__INSTANCE__) == TIM4) || \
9128  ((__INSTANCE__) == TIM5) || \
9129  ((__INSTANCE__) == TIM8) || \
9130  ((__INSTANCE__) == TIM9) || \
9131  ((__INSTANCE__) == TIM10) || \
9132  ((__INSTANCE__) == TIM11) || \
9133  ((__INSTANCE__) == TIM12) || \
9134  ((__INSTANCE__) == TIM13) || \
9135  ((__INSTANCE__) == TIM14))
9136 
9137 /************ TIM Instances : at least 2 capture/compare channels *************/
9138 #define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9139  ((__INSTANCE__) == TIM2) || \
9140  ((__INSTANCE__) == TIM3) || \
9141  ((__INSTANCE__) == TIM4) || \
9142  ((__INSTANCE__) == TIM5) || \
9143  ((__INSTANCE__) == TIM8) || \
9144  ((__INSTANCE__) == TIM9) || \
9145  ((__INSTANCE__) == TIM12))
9146 
9147 /************ TIM Instances : at least 3 capture/compare channels *************/
9148 #define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9149  ((__INSTANCE__) == TIM2) || \
9150  ((__INSTANCE__) == TIM3) || \
9151  ((__INSTANCE__) == TIM4) || \
9152  ((__INSTANCE__) == TIM5) || \
9153  ((__INSTANCE__) == TIM8))
9154 
9155 /************ TIM Instances : at least 4 capture/compare channels *************/
9156 #define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9157  ((__INSTANCE__) == TIM2) || \
9158  ((__INSTANCE__) == TIM3) || \
9159  ((__INSTANCE__) == TIM4) || \
9160  ((__INSTANCE__) == TIM5) || \
9161  ((__INSTANCE__) == TIM8))
9162 
9163 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
9164 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
9165  (((__INSTANCE__) == TIM1) || \
9166  ((__INSTANCE__) == TIM8))
9167 
9168 /****************** TIM Instances : supporting OCxREF clear *******************/
9169 #define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
9170  (((__INSTANCE__) == TIM1) || \
9171  ((__INSTANCE__) == TIM2) || \
9172  ((__INSTANCE__) == TIM3) || \
9173  ((__INSTANCE__) == TIM4) || \
9174  ((__INSTANCE__) == TIM8))
9175 
9176 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
9177 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
9178  (((__INSTANCE__) == TIM1) || \
9179  ((__INSTANCE__) == TIM2) || \
9180  ((__INSTANCE__) == TIM3) || \
9181  ((__INSTANCE__) == TIM4) || \
9182  ((__INSTANCE__) == TIM5) || \
9183  ((__INSTANCE__) == TIM8))
9184 
9185 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
9186 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
9187  (((__INSTANCE__) == TIM1) || \
9188  ((__INSTANCE__) == TIM2) || \
9189  ((__INSTANCE__) == TIM3) || \
9190  ((__INSTANCE__) == TIM4) || \
9191  ((__INSTANCE__) == TIM5) || \
9192  ((__INSTANCE__) == TIM8))
9193 /****************** TIM Instances : at least 5 capture/compare channels *******/
9194 #define IS_TIM_CC5_INSTANCE(__INSTANCE__)\
9195  (((__INSTANCE__) == TIM1) || \
9196  ((__INSTANCE__) == TIM8) )
9197 
9198 /****************** TIM Instances : at least 6 capture/compare channels *******/
9199 #define IS_TIM_CC6_INSTANCE(__INSTANCE__)\
9200  (((__INSTANCE__) == TIM1) || \
9201  ((__INSTANCE__) == TIM8))
9202 
9203 
9204 /******************** TIM Instances : Advanced-control timers *****************/
9205 #define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9206  ((__INSTANCE__) == TIM8))
9207 
9208 /****************** TIM Instances : supporting 2 break inputs *****************/
9209 #define IS_TIM_BREAK_INSTANCE(__INSTANCE__)\
9210  (((__INSTANCE__) == TIM1) || \
9211  ((__INSTANCE__) == TIM8))
9212 
9213 /******************* TIM Instances : Timer input XOR function *****************/
9214 #define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9215  ((__INSTANCE__) == TIM2) || \
9216  ((__INSTANCE__) == TIM3) || \
9217  ((__INSTANCE__) == TIM4) || \
9218  ((__INSTANCE__) == TIM5) || \
9219  ((__INSTANCE__) == TIM8))
9220 
9221 /****************** TIM Instances : DMA requests generation (UDE) *************/
9222 #define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9223  ((__INSTANCE__) == TIM2) || \
9224  ((__INSTANCE__) == TIM3) || \
9225  ((__INSTANCE__) == TIM4) || \
9226  ((__INSTANCE__) == TIM5) || \
9227  ((__INSTANCE__) == TIM6) || \
9228  ((__INSTANCE__) == TIM7) || \
9229  ((__INSTANCE__) == TIM8))
9230 
9231 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
9232 #define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9233  ((__INSTANCE__) == TIM2) || \
9234  ((__INSTANCE__) == TIM3) || \
9235  ((__INSTANCE__) == TIM4) || \
9236  ((__INSTANCE__) == TIM5) || \
9237  ((__INSTANCE__) == TIM8))
9238 
9239 /************ TIM Instances : DMA requests generation (COMDE) *****************/
9240 #define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9241  ((__INSTANCE__) == TIM2) || \
9242  ((__INSTANCE__) == TIM3) || \
9243  ((__INSTANCE__) == TIM4) || \
9244  ((__INSTANCE__) == TIM5) || \
9245  ((__INSTANCE__) == TIM8))
9246 
9247 /******************** TIM Instances : DMA burst feature ***********************/
9248 #define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9249  ((__INSTANCE__) == TIM2) || \
9250  ((__INSTANCE__) == TIM3) || \
9251  ((__INSTANCE__) == TIM4) || \
9252  ((__INSTANCE__) == TIM5) || \
9253  ((__INSTANCE__) == TIM8))
9254 
9255 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
9256 #define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9257  ((__INSTANCE__) == TIM2) || \
9258  ((__INSTANCE__) == TIM3) || \
9259  ((__INSTANCE__) == TIM4) || \
9260  ((__INSTANCE__) == TIM5) || \
9261  ((__INSTANCE__) == TIM6) || \
9262  ((__INSTANCE__) == TIM7) || \
9263  ((__INSTANCE__) == TIM8) || \
9264  ((__INSTANCE__) == TIM13) || \
9265  ((__INSTANCE__) == TIM14))
9266 
9267 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
9268 #define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9269  ((__INSTANCE__) == TIM2) || \
9270  ((__INSTANCE__) == TIM3) || \
9271  ((__INSTANCE__) == TIM4) || \
9272  ((__INSTANCE__) == TIM5) || \
9273  ((__INSTANCE__) == TIM8) || \
9274  ((__INSTANCE__) == TIM9) || \
9275  ((__INSTANCE__) == TIM12))
9276 
9277 /********************** TIM Instances : 32 bit Counter ************************/
9278 #define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)(((__INSTANCE__) == TIM2) || \
9279  ((__INSTANCE__) == TIM5))
9280 
9281 /***************** TIM Instances : external trigger input available ************/
9282 #define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9283  ((__INSTANCE__) == TIM2) || \
9284  ((__INSTANCE__) == TIM3) || \
9285  ((__INSTANCE__) == TIM4) || \
9286  ((__INSTANCE__) == TIM5) || \
9287  ((__INSTANCE__) == TIM8))
9288 
9289 /****************** TIM Instances : remapping capability **********************/
9290 #define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
9291  ((__INSTANCE__) == TIM5) || \
9292  ((__INSTANCE__) == TIM11))
9293 
9294 /******************* TIM Instances : output(s) available **********************/
9295 #define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
9296  ((((__INSTANCE__) == TIM1) && \
9297  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9298  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9299  ((__CHANNEL__) == TIM_CHANNEL_3) || \
9300  ((__CHANNEL__) == TIM_CHANNEL_4))) \
9301  || \
9302  (((__INSTANCE__) == TIM2) && \
9303  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9304  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9305  ((__CHANNEL__) == TIM_CHANNEL_3) || \
9306  ((__CHANNEL__) == TIM_CHANNEL_4))) \
9307  || \
9308  (((__INSTANCE__) == TIM3) && \
9309  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9310  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9311  ((__CHANNEL__) == TIM_CHANNEL_3) || \
9312  ((__CHANNEL__) == TIM_CHANNEL_4))) \
9313  || \
9314  (((__INSTANCE__) == TIM4) && \
9315  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9316  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9317  ((__CHANNEL__) == TIM_CHANNEL_3) || \
9318  ((__CHANNEL__) == TIM_CHANNEL_4))) \
9319  || \
9320  (((__INSTANCE__) == TIM5) && \
9321  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9322  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9323  ((__CHANNEL__) == TIM_CHANNEL_3) || \
9324  ((__CHANNEL__) == TIM_CHANNEL_4))) \
9325  || \
9326  (((__INSTANCE__) == TIM8) && \
9327  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9328  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9329  ((__CHANNEL__) == TIM_CHANNEL_3) || \
9330  ((__CHANNEL__) == TIM_CHANNEL_4))) \
9331  || \
9332  (((__INSTANCE__) == TIM9) && \
9333  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9334  ((__CHANNEL__) == TIM_CHANNEL_2))) \
9335  || \
9336  (((__INSTANCE__) == TIM10) && \
9337  (((__CHANNEL__) == TIM_CHANNEL_1))) \
9338  || \
9339  (((__INSTANCE__) == TIM11) && \
9340  (((__CHANNEL__) == TIM_CHANNEL_1))) \
9341  || \
9342  (((__INSTANCE__) == TIM12) && \
9343  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9344  ((__CHANNEL__) == TIM_CHANNEL_2))) \
9345  || \
9346  (((__INSTANCE__) == TIM13) && \
9347  (((__CHANNEL__) == TIM_CHANNEL_1))) \
9348  || \
9349  (((__INSTANCE__) == TIM14) && \
9350  (((__CHANNEL__) == TIM_CHANNEL_1))))
9351 
9352 /************ TIM Instances : complementary output(s) available ***************/
9353 #define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
9354  ((((__INSTANCE__) == TIM1) && \
9355  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9356  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9357  ((__CHANNEL__) == TIM_CHANNEL_3))) \
9358  || \
9359  (((__INSTANCE__) == TIM8) && \
9360  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9361  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9362  ((__CHANNEL__) == TIM_CHANNEL_3))))
9363 
9364 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
9365 #define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
9366  (((__INSTANCE__) == TIM1) || \
9367  ((__INSTANCE__) == TIM8) )
9368 
9369 /****************** TIM Instances : supporting synchronization ****************/
9370 #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
9371  (((__INSTANCE__) == TIM1) || \
9372  ((__INSTANCE__) == TIM2) || \
9373  ((__INSTANCE__) == TIM3) || \
9374  ((__INSTANCE__) == TIM4) || \
9375  ((__INSTANCE__) == TIM5) || \
9376  ((__INSTANCE__) == TIM6) || \
9377  ((__INSTANCE__) == TIM7) || \
9378  ((__INSTANCE__) == TIM8))
9379 
9380 /******************** USART Instances : Synchronous mode **********************/
9381 #define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9382  ((__INSTANCE__) == USART2) || \
9383  ((__INSTANCE__) == USART3) || \
9384  ((__INSTANCE__) == USART6))
9385 
9386 /******************** UART Instances : Asynchronous mode **********************/
9387 #define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9388  ((__INSTANCE__) == USART2) || \
9389  ((__INSTANCE__) == USART3) || \
9390  ((__INSTANCE__) == UART4) || \
9391  ((__INSTANCE__) == UART5) || \
9392  ((__INSTANCE__) == USART6) || \
9393  ((__INSTANCE__) == UART7) || \
9394  ((__INSTANCE__) == UART8))
9395 
9396 /****************** UART Instances : Driver Enable *****************/
9397 #define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9398  ((__INSTANCE__) == USART2) || \
9399  ((__INSTANCE__) == USART3) || \
9400  ((__INSTANCE__) == UART4) || \
9401  ((__INSTANCE__) == UART5) || \
9402  ((__INSTANCE__) == USART6) || \
9403  ((__INSTANCE__) == UART7) || \
9404  ((__INSTANCE__) == UART8))
9405 
9406 /****************** UART Instances : Hardware Flow control ********************/
9407 #define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9408  ((__INSTANCE__) == USART2) || \
9409  ((__INSTANCE__) == USART3) || \
9410  ((__INSTANCE__) == UART4) || \
9411  ((__INSTANCE__) == UART5) || \
9412  ((__INSTANCE__) == USART6) || \
9413  ((__INSTANCE__) == UART7) || \
9414  ((__INSTANCE__) == UART8))
9415 
9416 /********************* UART Instances : Smart card mode ***********************/
9417 #define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9418  ((__INSTANCE__) == USART2) || \
9419  ((__INSTANCE__) == USART3) || \
9420  ((__INSTANCE__) == USART6))
9421 
9422 /*********************** UART Instances : IRDA mode ***************************/
9423 #define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9424  ((__INSTANCE__) == USART2) || \
9425  ((__INSTANCE__) == USART3) || \
9426  ((__INSTANCE__) == UART4) || \
9427  ((__INSTANCE__) == UART5) || \
9428  ((__INSTANCE__) == USART6) || \
9429  ((__INSTANCE__) == UART7) || \
9430  ((__INSTANCE__) == UART8))
9431 
9432 /****************************** IWDG Instances ********************************/
9433 #define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)
9434 
9435 /****************************** WWDG Instances ********************************/
9436 #define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)
9437 
9438 
9439 /******************************************************************************/
9440 /* For a painless codes migration between the STM32F7xx device product */
9441 /* lines, the aliases defined below are put in place to overcome the */
9442 /* differences in the interrupt handlers and IRQn definitions. */
9443 /* No need to update developed interrupt code when moving across */
9444 /* product lines within the same STM32F7 Family */
9445 /******************************************************************************/
9446 
9447 /* Aliases for __IRQn */
9448 #define HASH_RNG_IRQn RNG_IRQn
9449 
9450 /* Aliases for __IRQHandler */
9451 #define HASH_RNG_IRQHandler RNG_IRQHandler
9452 
9465 #ifdef __cplusplus
9466 }
9467 #endif /* __cplusplus */
9468 
9469 #endif /* __STM32F746xx_H */
9470 
9471 
9472 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RESERVED
#define RESERVED
Definition: usbh_cdc.h:68
LTDC_TypeDef
LCD-TFT Display Controller.
Definition: stm32f746xx.h:661
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition: stm32f745xx.h:253
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f745xx.h:613
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f745xx.h:841
SPI5_IRQn
Definition: stm32f746xx.h:163
DMA1_Stream2_IRQn
Definition: stm32f746xx.h:92
CAN2_SCE_IRQn
Definition: stm32f746xx.h:145
OTG_FS_WKUP_IRQn
Definition: stm32f746xx.h:121
LTDC_Layer_TypeDef::CACR
__IO uint32_t CACR
Definition: stm32f746xx.h:693
SVCall_IRQn
Definition: stm32f746xx.h:74
DMA2_Stream6_IRQn
Definition: stm32f746xx.h:148
OTG_HS_EP1_IN_IRQn
Definition: stm32f746xx.h:154
DMA2_Stream7_IRQn
Definition: stm32f746xx.h:149
EXTI4_IRQn
Definition: stm32f746xx.h:89
TIM4_IRQn
Definition: stm32f746xx.h:109
LPTIM1_IRQn
Definition: stm32f746xx.h:171
SAI2_IRQn
Definition: stm32f746xx.h:169
ADC_IRQn
Definition: stm32f746xx.h:97
CAN1_SCE_IRQn
Definition: stm32f746xx.h:101
EXTI1_IRQn
Definition: stm32f746xx.h:86
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f745xx.h:519
DMA2_Stream1_IRQn
Definition: stm32f746xx.h:136
LTDC_TypeDef::CDSR
__IO uint32_t CDSR
Definition: stm32f746xx.h:679
I2C4_EV_IRQn
Definition: stm32f746xx.h:173
EXTI15_10_IRQn
Definition: stm32f746xx.h:119
SPDIFRX_TypeDef
SPDIF-RX Interface.
Definition: stm32f745xx.h:797
CEC_TypeDef
HDMI-CEC.
Definition: stm32f745xx.h:305
SPI4_IRQn
Definition: stm32f746xx.h:162
UART5_IRQn
Definition: stm32f746xx.h:132
SAI1_IRQn
Definition: stm32f746xx.h:165
TIM1_TRG_COM_TIM11_IRQn
Definition: stm32f746xx.h:105
FMC_Bank3_TypeDef
Flexible Memory Controller Bank3.
Definition: stm32f745xx.h:568
CRC_TypeDef
CRC calculation unit.
Definition: stm32f745xx.h:320
LTDC_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32f746xx.h:676
EXTI9_5_IRQn
Definition: stm32f746xx.h:102
DIR
Definition: ff.h:151
CAN1_RX1_IRQn
Definition: stm32f746xx.h:100
DMA2_Stream0_IRQn
Definition: stm32f746xx.h:135
CEC_IRQn
Definition: stm32f746xx.h:172
USB_OTG_INEndpointTypeDef
USB_OTG_IN_Endpoint-Specific_Register.
Definition: stm32f745xx.h:1035
SDMMC1_IRQn
Definition: stm32f746xx.h:128
LTDC_Layer_TypeDef::CKCR
__IO uint32_t CKCR
Definition: stm32f746xx.h:691
I2C2_ER_IRQn
Definition: stm32f746xx.h:113
DMA2_Stream4_IRQn
Definition: stm32f746xx.h:139
EXTI3_IRQn
Definition: stm32f746xx.h:88
CAN2_RX1_IRQn
Definition: stm32f746xx.h:144
FMC_Bank1E_TypeDef
Flexible Memory Controller Bank1E.
Definition: stm32f745xx.h:559
DMA_TypeDef
Definition: stm32f745xx.h:400
TAMP_STAMP_IRQn
Definition: stm32f746xx.h:81
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f745xx.h:948
UART4_IRQn
Definition: stm32f746xx.h:131
DMA1_Stream6_IRQn
Definition: stm32f746xx.h:96
RTC_Alarm_IRQn
Definition: stm32f746xx.h:120
__I
#define __I
Definition: core_cm0.h:210
LTDC_TypeDef::BPCR
__IO uint32_t BPCR
Definition: stm32f746xx.h:665
DMA1_Stream5_IRQn
Definition: stm32f746xx.h:95
SPI2_IRQn
Definition: stm32f746xx.h:115
LTDC_Layer_TypeDef
LCD-TFT Display layer x Controller.
Definition: stm32f746xx.h:686
LTDC_Layer_TypeDef::CFBAR
__IO uint32_t CFBAR
Definition: stm32f746xx.h:697
LTDC_TypeDef::LIPCR
__IO uint32_t LIPCR
Definition: stm32f746xx.h:677
USB_OTG_GlobalTypeDef
USB_OTG_Core_Registers.
Definition: stm32f745xx.h:974
DMA1_Stream1_IRQn
Definition: stm32f746xx.h:91
PendSV_IRQn
Definition: stm32f746xx.h:76
UART7_IRQn
Definition: stm32f746xx.h:160
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f745xx.h:596
BusFault_IRQn
Definition: stm32f746xx.h:72
LTDC_TypeDef::SSCR
__IO uint32_t SSCR
Definition: stm32f746xx.h:664
I2C2_EV_IRQn
Definition: stm32f746xx.h:112
TIM8_TRG_COM_TIM14_IRQn
Definition: stm32f746xx.h:124
QUADSPI_TypeDef
QUAD Serial Peripheral Interface.
Definition: stm32f745xx.h:858
CAN2_TX_IRQn
Definition: stm32f746xx.h:142
I2C1_EV_IRQn
Definition: stm32f746xx.h:110
CAN_TypeDef
Controller Area Network.
Definition: stm32f745xx.h:275
LPTIM_TypeDef
LPTIMIMER.
Definition: stm32f745xx.h:911
FMC_IRQn
Definition: stm32f746xx.h:127
LTDC_Layer_TypeDef::WHPCR
__IO uint32_t WHPCR
Definition: stm32f746xx.h:689
DCMI_IRQn
Definition: stm32f746xx.h:157
TIM7_IRQn
Definition: stm32f746xx.h:134
DMA2D_TypeDef
DMA2D Controller.
Definition: stm32f745xx.h:413
RCC_IRQn
Definition: stm32f746xx.h:84
I2C3_EV_IRQn
Definition: stm32f746xx.h:151
__IO
#define __IO
Definition: core_cm0.h:213
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32f745xx.h:204
SysTick_IRQn
Definition: stm32f746xx.h:77
SAI_TypeDef
Serial Audio Interface.
Definition: stm32f745xx.h:776
DMA1_Stream0_IRQn
Definition: stm32f746xx.h:90
USB_OTG_HostTypeDef
USB_OTG_Host_Mode_Register_Structures.
Definition: stm32f745xx.h:1066
IRQn_Type
IRQn_Type
STM32F7xx Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f746xx.h:67
QUADSPI_IRQn
Definition: stm32f746xx.h:170
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition: stm32f745xx.h:241
ETH_TypeDef
Ethernet MAC.
Definition: stm32f745xx.h:445
TIM2_IRQn
Definition: stm32f746xx.h:107
SPI3_IRQn
Definition: stm32f746xx.h:130
LTDC_TypeDef::GCR
__IO uint32_t GCR
Definition: stm32f746xx.h:668
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f745xx.h:928
LTDC_Layer_TypeDef::DCCR
__IO uint32_t DCCR
Definition: stm32f746xx.h:694
TIM_TypeDef
TIM.
Definition: stm32f745xx.h:879
DMA1_Stream7_IRQn
Definition: stm32f746xx.h:126
DMA2_Stream5_IRQn
Definition: stm32f746xx.h:147
LTDC_TypeDef::AWCR
__IO uint32_t AWCR
Definition: stm32f746xx.h:666
USART1_IRQn
Definition: stm32f746xx.h:116
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f745xx.h:390
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32f745xx.h:336
USB_OTG_HostChannelTypeDef
USB_OTG_Host_Channel_Specific_Registers.
Definition: stm32f745xx.h:1080
OTG_HS_WKUP_IRQn
Definition: stm32f746xx.h:155
I2C4_ER_IRQn
Definition: stm32f746xx.h:174
FLASH_TypeDef
FLASH Registers.
Definition: stm32f745xx.h:533
DMA2_Stream2_IRQn
Definition: stm32f746xx.h:137
PWR_TypeDef
Power Control.
Definition: stm32f745xx.h:660
PVD_IRQn
Definition: stm32f746xx.h:80
ETH_IRQn
Definition: stm32f746xx.h:140
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f745xx.h:645
LTDC_TypeDef::IER
__IO uint32_t IER
Definition: stm32f746xx.h:674
FPU_IRQn
Definition: stm32f746xx.h:159
LTDC_Layer_TypeDef::WVPCR
__IO uint32_t WVPCR
Definition: stm32f746xx.h:690
OTG_HS_EP1_OUT_IRQn
Definition: stm32f746xx.h:153
LTDC_TypeDef::SRCR
__IO uint32_t SRCR
Definition: stm32f746xx.h:670
ADC_Common_TypeDef
Definition: stm32f745xx.h:228
DMA1_Stream3_IRQn
Definition: stm32f746xx.h:93
RTC_WKUP_IRQn
Definition: stm32f746xx.h:82
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f745xx.h:673
LTDC_TypeDef::CPSR
__IO uint32_t CPSR
Definition: stm32f746xx.h:678
WWDG_IRQn
Definition: stm32f746xx.h:79
CAN2_RX0_IRQn
Definition: stm32f746xx.h:143
TIM8_BRK_TIM12_IRQn
Definition: stm32f746xx.h:122
DMA2D_IRQn
Definition: stm32f746xx.h:168
I2C3_ER_IRQn
Definition: stm32f746xx.h:152
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition: stm32f745xx.h:265
CAN1_TX_IRQn
Definition: stm32f746xx.h:98
DebugMonitor_IRQn
Definition: stm32f746xx.h:75
FMC_Bank1_TypeDef
Flexible Memory Controller.
Definition: stm32f745xx.h:550
DMA1_Stream4_IRQn
Definition: stm32f746xx.h:94
TIM6_DAC_IRQn
Definition: stm32f746xx.h:133
SPDIF_RX_IRQn
Definition: stm32f746xx.h:175
RTC_TypeDef
Real-Time Clock.
Definition: stm32f745xx.h:715
ETH_WKUP_IRQn
Definition: stm32f746xx.h:141
DCMI_TypeDef
DCMI.
Definition: stm32f745xx.h:371
I2C1_ER_IRQn
Definition: stm32f746xx.h:111
FMC_Bank5_6_TypeDef
Flexible Memory Controller Bank5_6.
Definition: stm32f745xx.h:582
OTG_HS_IRQn
Definition: stm32f746xx.h:156
TIM1_CC_IRQn
Definition: stm32f746xx.h:106
LTDC_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f746xx.h:675
RNG_IRQn
Definition: stm32f746xx.h:158
FLASH_IRQn
Definition: stm32f746xx.h:83
DMA2_Stream3_IRQn
Definition: stm32f746xx.h:138
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f745xx.h:626
TIM8_UP_TIM13_IRQn
Definition: stm32f746xx.h:123
RNG_TypeDef
RNG.
Definition: stm32f745xx.h:960
LTDC_Layer_TypeDef::CR
__IO uint32_t CR
Definition: stm32f746xx.h:688
SPI6_IRQn
Definition: stm32f746xx.h:164
LTDC_TypeDef::TWCR
__IO uint32_t TWCR
Definition: stm32f746xx.h:667
TIM1_BRK_TIM9_IRQn
Definition: stm32f746xx.h:103
TIM1_UP_TIM10_IRQn
Definition: stm32f746xx.h:104
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f745xx.h:359
SPI1_IRQn
Definition: stm32f746xx.h:114
TIM3_IRQn
Definition: stm32f746xx.h:108
LTDC_TypeDef::BCCR
__IO uint32_t BCCR
Definition: stm32f746xx.h:672
NonMaskableInt_IRQn
Definition: stm32f746xx.h:70
SDMMC_TypeDef
SD host Interface.
Definition: stm32f745xx.h:813
TIM8_CC_IRQn
Definition: stm32f746xx.h:125
SAI_Block_TypeDef
Definition: stm32f745xx.h:781
EXTI0_IRQn
Definition: stm32f746xx.h:85
LTDC_IRQn
Definition: stm32f746xx.h:166
LTDC_Layer_TypeDef::BFCR
__IO uint32_t BFCR
Definition: stm32f746xx.h:695
EXTI2_IRQn
Definition: stm32f746xx.h:87
USB_OTG_OUTEndpointTypeDef
USB_OTG_OUT_Endpoint-Specific_Registers.
Definition: stm32f745xx.h:1051
LTDC_ER_IRQn
Definition: stm32f746xx.h:167
USART3_IRQn
Definition: stm32f746xx.h:118
USART2_IRQn
Definition: stm32f746xx.h:117
LTDC_Layer_TypeDef::CFBLR
__IO uint32_t CFBLR
Definition: stm32f746xx.h:698
UART8_IRQn
Definition: stm32f746xx.h:161
LTDC_Layer_TypeDef::CFBLNR
__IO uint32_t CFBLNR
Definition: stm32f746xx.h:699
OTG_FS_IRQn
Definition: stm32f746xx.h:146
UsageFault_IRQn
Definition: stm32f746xx.h:73
MemoryManagement_IRQn
Definition: stm32f746xx.h:71
USB_OTG_DeviceTypeDef
USB_OTG_device_Registers.
Definition: stm32f745xx.h:1007
TIM5_IRQn
Definition: stm32f746xx.h:129
LTDC_Layer_TypeDef::PFCR
__IO uint32_t PFCR
Definition: stm32f746xx.h:692
USART6_IRQn
Definition: stm32f746xx.h:150
CAN1_RX0_IRQn
Definition: stm32f746xx.h:99
LTDC_Layer_TypeDef::CLUTWR
__IO uint32_t CLUTWR
Definition: stm32f746xx.h:701
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