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STM32F769IDiscovery
1.00
uDANTE Audio Networking with STM32F7 DISCO board
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STM32F769IDiscovery
1.00
uDANTE Audio Networking with STM32F7 DISCO board
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Reset and Clock Control. More...
#include <stm32f745xx.h>
Data Fields | |
| __IO uint32_t | CR |
| __IO uint32_t | PLLCFGR |
| __IO uint32_t | CFGR |
| __IO uint32_t | CIR |
| __IO uint32_t | AHB1RSTR |
| __IO uint32_t | AHB2RSTR |
| __IO uint32_t | AHB3RSTR |
| uint32_t | RESERVED0 |
| __IO uint32_t | APB1RSTR |
| __IO uint32_t | APB2RSTR |
| uint32_t | RESERVED1 [2] |
| __IO uint32_t | AHB1ENR |
| __IO uint32_t | AHB2ENR |
| __IO uint32_t | AHB3ENR |
| uint32_t | RESERVED2 |
| __IO uint32_t | APB1ENR |
| __IO uint32_t | APB2ENR |
| uint32_t | RESERVED3 [2] |
| __IO uint32_t | AHB1LPENR |
| __IO uint32_t | AHB2LPENR |
| __IO uint32_t | AHB3LPENR |
| uint32_t | RESERVED4 |
| __IO uint32_t | APB1LPENR |
| __IO uint32_t | APB2LPENR |
| uint32_t | RESERVED5 [2] |
| __IO uint32_t | BDCR |
| __IO uint32_t | CSR |
| uint32_t | RESERVED6 [2] |
| __IO uint32_t | SSCGR |
| __IO uint32_t | PLLI2SCFGR |
| __IO uint32_t | PLLSAICFGR |
| __IO uint32_t | DCKCFGR1 |
| __IO uint32_t | DCKCFGR2 |
Reset and Clock Control.
Definition at line 673 of file stm32f745xx.h.
| __IO uint32_t AHB1ENR |
RCC AHB1 peripheral clock register, Address offset: 0x30
Definition at line 686 of file stm32f745xx.h.
| __IO uint32_t AHB1LPENR |
RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50
Definition at line 693 of file stm32f745xx.h.
| __IO uint32_t AHB1RSTR |
RCC AHB1 peripheral reset register, Address offset: 0x10
Definition at line 679 of file stm32f745xx.h.
| __IO uint32_t AHB2ENR |
RCC AHB2 peripheral clock register, Address offset: 0x34
Definition at line 687 of file stm32f745xx.h.
| __IO uint32_t AHB2LPENR |
RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54
Definition at line 694 of file stm32f745xx.h.
| __IO uint32_t AHB2RSTR |
RCC AHB2 peripheral reset register, Address offset: 0x14
Definition at line 680 of file stm32f745xx.h.
| __IO uint32_t AHB3ENR |
RCC AHB3 peripheral clock register, Address offset: 0x38
Definition at line 688 of file stm32f745xx.h.
| __IO uint32_t AHB3LPENR |
RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58
Definition at line 695 of file stm32f745xx.h.
| __IO uint32_t AHB3RSTR |
RCC AHB3 peripheral reset register, Address offset: 0x18
Definition at line 681 of file stm32f745xx.h.
| __IO uint32_t APB1ENR |
RCC APB1 peripheral clock enable register, Address offset: 0x40
Definition at line 690 of file stm32f745xx.h.
| __IO uint32_t APB1LPENR |
RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60
Definition at line 697 of file stm32f745xx.h.
| __IO uint32_t APB1RSTR |
RCC APB1 peripheral reset register, Address offset: 0x20
Definition at line 683 of file stm32f745xx.h.
| __IO uint32_t APB2ENR |
RCC APB2 peripheral clock enable register, Address offset: 0x44
Definition at line 691 of file stm32f745xx.h.
| __IO uint32_t APB2LPENR |
RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64
Definition at line 698 of file stm32f745xx.h.
| __IO uint32_t APB2RSTR |
RCC APB2 peripheral reset register, Address offset: 0x24
Definition at line 684 of file stm32f745xx.h.
| __IO uint32_t BDCR |
RCC Backup domain control register, Address offset: 0x70
Definition at line 700 of file stm32f745xx.h.
| __IO uint32_t CFGR |
RCC clock configuration register, Address offset: 0x08
Definition at line 677 of file stm32f745xx.h.
| __IO uint32_t CIR |
RCC clock interrupt register, Address offset: 0x0C
Definition at line 678 of file stm32f745xx.h.
| __IO uint32_t CR |
RCC clock control register, Address offset: 0x00
Definition at line 675 of file stm32f745xx.h.
| __IO uint32_t CSR |
RCC clock control & status register, Address offset: 0x74
Definition at line 701 of file stm32f745xx.h.
| __IO uint32_t DCKCFGR1 |
RCC Dedicated Clocks configuration register1, Address offset: 0x8C
Definition at line 706 of file stm32f745xx.h.
| __IO uint32_t DCKCFGR2 |
RCC Dedicated Clocks configuration register 2, Address offset: 0x90
Definition at line 707 of file stm32f745xx.h.
| __IO uint32_t PLLCFGR |
RCC PLL configuration register, Address offset: 0x04
Definition at line 676 of file stm32f745xx.h.
| __IO uint32_t PLLI2SCFGR |
RCC PLLI2S configuration register, Address offset: 0x84
Definition at line 704 of file stm32f745xx.h.
| __IO uint32_t PLLSAICFGR |
RCC PLLSAI configuration register, Address offset: 0x88
Definition at line 705 of file stm32f745xx.h.
| uint32_t RESERVED0 |
Reserved, 0x1C
Definition at line 682 of file stm32f745xx.h.
| uint32_t RESERVED1 |
Reserved, 0x28-0x2C
Definition at line 685 of file stm32f745xx.h.
| uint32_t RESERVED2 |
Reserved, 0x3C
Definition at line 689 of file stm32f745xx.h.
| uint32_t RESERVED3 |
Reserved, 0x48-0x4C
Definition at line 692 of file stm32f745xx.h.
| uint32_t RESERVED4 |
Reserved, 0x5C
Definition at line 696 of file stm32f745xx.h.
| uint32_t RESERVED5 |
Reserved, 0x68-0x6C
Definition at line 699 of file stm32f745xx.h.
| uint32_t RESERVED6 |
Reserved, 0x78-0x7C
Definition at line 702 of file stm32f745xx.h.
| __IO uint32_t SSCGR |
RCC spread spectrum clock generation register, Address offset: 0x80
Definition at line 703 of file stm32f745xx.h.
1.8.11
