STM32F769IDiscovery  1.00
uDANTE Audio Networking with STM32F7 DISCO board
stm32f756xx.h
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1 
52 #ifndef __STM32F756xx_H
53 #define __STM32F756xx_H
54 
55 #ifdef __cplusplus
56  extern "C" {
57 #endif /* __cplusplus */
58 
67 typedef enum
68 {
69 /****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/
70  NonMaskableInt_IRQn = -14,
71  MemoryManagement_IRQn = -12,
72  BusFault_IRQn = -11,
73  UsageFault_IRQn = -10,
74  SVCall_IRQn = -5,
75  DebugMonitor_IRQn = -4,
76  PendSV_IRQn = -2,
77  SysTick_IRQn = -1,
78 /****** STM32 specific Interrupt Numbers **********************************************************************/
79  WWDG_IRQn = 0,
80  PVD_IRQn = 1,
81  TAMP_STAMP_IRQn = 2,
82  RTC_WKUP_IRQn = 3,
83  FLASH_IRQn = 4,
84  RCC_IRQn = 5,
85  EXTI0_IRQn = 6,
86  EXTI1_IRQn = 7,
87  EXTI2_IRQn = 8,
88  EXTI3_IRQn = 9,
89  EXTI4_IRQn = 10,
90  DMA1_Stream0_IRQn = 11,
91  DMA1_Stream1_IRQn = 12,
92  DMA1_Stream2_IRQn = 13,
93  DMA1_Stream3_IRQn = 14,
94  DMA1_Stream4_IRQn = 15,
95  DMA1_Stream5_IRQn = 16,
96  DMA1_Stream6_IRQn = 17,
97  ADC_IRQn = 18,
98  CAN1_TX_IRQn = 19,
99  CAN1_RX0_IRQn = 20,
100  CAN1_RX1_IRQn = 21,
101  CAN1_SCE_IRQn = 22,
102  EXTI9_5_IRQn = 23,
103  TIM1_BRK_TIM9_IRQn = 24,
104  TIM1_UP_TIM10_IRQn = 25,
105  TIM1_TRG_COM_TIM11_IRQn = 26,
106  TIM1_CC_IRQn = 27,
107  TIM2_IRQn = 28,
108  TIM3_IRQn = 29,
109  TIM4_IRQn = 30,
110  I2C1_EV_IRQn = 31,
111  I2C1_ER_IRQn = 32,
112  I2C2_EV_IRQn = 33,
113  I2C2_ER_IRQn = 34,
114  SPI1_IRQn = 35,
115  SPI2_IRQn = 36,
116  USART1_IRQn = 37,
117  USART2_IRQn = 38,
118  USART3_IRQn = 39,
119  EXTI15_10_IRQn = 40,
120  RTC_Alarm_IRQn = 41,
121  OTG_FS_WKUP_IRQn = 42,
122  TIM8_BRK_TIM12_IRQn = 43,
123  TIM8_UP_TIM13_IRQn = 44,
124  TIM8_TRG_COM_TIM14_IRQn = 45,
125  TIM8_CC_IRQn = 46,
126  DMA1_Stream7_IRQn = 47,
127  FMC_IRQn = 48,
128  SDMMC1_IRQn = 49,
129  TIM5_IRQn = 50,
130  SPI3_IRQn = 51,
131  UART4_IRQn = 52,
132  UART5_IRQn = 53,
133  TIM6_DAC_IRQn = 54,
134  TIM7_IRQn = 55,
135  DMA2_Stream0_IRQn = 56,
136  DMA2_Stream1_IRQn = 57,
137  DMA2_Stream2_IRQn = 58,
138  DMA2_Stream3_IRQn = 59,
139  DMA2_Stream4_IRQn = 60,
140  ETH_IRQn = 61,
141  ETH_WKUP_IRQn = 62,
142  CAN2_TX_IRQn = 63,
143  CAN2_RX0_IRQn = 64,
144  CAN2_RX1_IRQn = 65,
145  CAN2_SCE_IRQn = 66,
146  OTG_FS_IRQn = 67,
147  DMA2_Stream5_IRQn = 68,
148  DMA2_Stream6_IRQn = 69,
149  DMA2_Stream7_IRQn = 70,
150  USART6_IRQn = 71,
151  I2C3_EV_IRQn = 72,
152  I2C3_ER_IRQn = 73,
153  OTG_HS_EP1_OUT_IRQn = 74,
154  OTG_HS_EP1_IN_IRQn = 75,
155  OTG_HS_WKUP_IRQn = 76,
156  OTG_HS_IRQn = 77,
157  DCMI_IRQn = 78,
158  CRYP_IRQn = 79,
159  HASH_RNG_IRQn = 80,
160  FPU_IRQn = 81,
161  UART7_IRQn = 82,
162  UART8_IRQn = 83,
163  SPI4_IRQn = 84,
164  SPI5_IRQn = 85,
165  SPI6_IRQn = 86,
166  SAI1_IRQn = 87,
167  LTDC_IRQn = 88,
168  LTDC_ER_IRQn = 89,
169  DMA2D_IRQn = 90,
170  SAI2_IRQn = 91,
171  QUADSPI_IRQn = 92,
172  LPTIM1_IRQn = 93,
173  CEC_IRQn = 94,
174  I2C4_EV_IRQn = 95,
175  I2C4_ER_IRQn = 96,
176  SPDIF_RX_IRQn = 97,
177 } IRQn_Type;
178 
186 #define __CM7_REV 0x0001U
187 #define __MPU_PRESENT 1
188 #define __NVIC_PRIO_BITS 4
189 #define __Vendor_SysTickConfig 0
190 #define __FPU_PRESENT 1
191 #define __ICACHE_PRESENT 1
192 #define __DCACHE_PRESENT 1
193 #include "core_cm7.h"
196 #include "system_stm32f7xx.h"
197 #include <stdint.h>
198 
207 typedef struct
208 {
209  __IO uint32_t SR;
210  __IO uint32_t CR1;
211  __IO uint32_t CR2;
212  __IO uint32_t SMPR1;
213  __IO uint32_t SMPR2;
214  __IO uint32_t JOFR1;
215  __IO uint32_t JOFR2;
216  __IO uint32_t JOFR3;
217  __IO uint32_t JOFR4;
218  __IO uint32_t HTR;
219  __IO uint32_t LTR;
220  __IO uint32_t SQR1;
221  __IO uint32_t SQR2;
222  __IO uint32_t SQR3;
223  __IO uint32_t JSQR;
224  __IO uint32_t JDR1;
225  __IO uint32_t JDR2;
226  __IO uint32_t JDR3;
227  __IO uint32_t JDR4;
228  __IO uint32_t DR;
229 } ADC_TypeDef;
230 
231 typedef struct
232 {
233  __IO uint32_t CSR;
234  __IO uint32_t CCR;
235  __IO uint32_t CDR;
237 } ADC_Common_TypeDef;
238 
239 
244 typedef struct
245 {
246  __IO uint32_t TIR;
247  __IO uint32_t TDTR;
248  __IO uint32_t TDLR;
249  __IO uint32_t TDHR;
250 } CAN_TxMailBox_TypeDef;
251 
256 typedef struct
257 {
258  __IO uint32_t RIR;
259  __IO uint32_t RDTR;
260  __IO uint32_t RDLR;
261  __IO uint32_t RDHR;
262 } CAN_FIFOMailBox_TypeDef;
263 
268 typedef struct
269 {
270  __IO uint32_t FR1;
271  __IO uint32_t FR2;
272 } CAN_FilterRegister_TypeDef;
273 
278 typedef struct
279 {
280  __IO uint32_t MCR;
281  __IO uint32_t MSR;
282  __IO uint32_t TSR;
283  __IO uint32_t RF0R;
284  __IO uint32_t RF1R;
285  __IO uint32_t IER;
286  __IO uint32_t ESR;
287  __IO uint32_t BTR;
288  uint32_t RESERVED0[88];
289  CAN_TxMailBox_TypeDef sTxMailBox[3];
290  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
291  uint32_t RESERVED1[12];
292  __IO uint32_t FMR;
293  __IO uint32_t FM1R;
294  uint32_t RESERVED2;
295  __IO uint32_t FS1R;
296  uint32_t RESERVED3;
297  __IO uint32_t FFA1R;
298  uint32_t RESERVED4;
299  __IO uint32_t FA1R;
300  uint32_t RESERVED5[8];
301  CAN_FilterRegister_TypeDef sFilterRegister[28];
302 } CAN_TypeDef;
303 
308 typedef struct
309 {
310  __IO uint32_t CR;
311  __IO uint32_t CFGR;
312  __IO uint32_t TXDR;
313  __IO uint32_t RXDR;
314  __IO uint32_t ISR;
315  __IO uint32_t IER;
316 }CEC_TypeDef;
317 
318 
323 typedef struct
324 {
325  __IO uint32_t DR;
326  __IO uint8_t IDR;
327  uint8_t RESERVED0;
328  uint16_t RESERVED1;
329  __IO uint32_t CR;
330  uint32_t RESERVED2;
331  __IO uint32_t INIT;
332  __IO uint32_t POL;
333 } CRC_TypeDef;
334 
339 typedef struct
340 {
341  __IO uint32_t CR;
342  __IO uint32_t SWTRIGR;
343  __IO uint32_t DHR12R1;
344  __IO uint32_t DHR12L1;
345  __IO uint32_t DHR8R1;
346  __IO uint32_t DHR12R2;
347  __IO uint32_t DHR12L2;
348  __IO uint32_t DHR8R2;
349  __IO uint32_t DHR12RD;
350  __IO uint32_t DHR12LD;
351  __IO uint32_t DHR8RD;
352  __IO uint32_t DOR1;
353  __IO uint32_t DOR2;
354  __IO uint32_t SR;
355 } DAC_TypeDef;
356 
357 
362 typedef struct
363 {
364  __IO uint32_t IDCODE;
365  __IO uint32_t CR;
366  __IO uint32_t APB1FZ;
367  __IO uint32_t APB2FZ;
368 }DBGMCU_TypeDef;
369 
374 typedef struct
375 {
376  __IO uint32_t CR;
377  __IO uint32_t SR;
378  __IO uint32_t RISR;
379  __IO uint32_t IER;
380  __IO uint32_t MISR;
381  __IO uint32_t ICR;
382  __IO uint32_t ESCR;
383  __IO uint32_t ESUR;
384  __IO uint32_t CWSTRTR;
385  __IO uint32_t CWSIZER;
386  __IO uint32_t DR;
387 } DCMI_TypeDef;
388 
393 typedef struct
394 {
395  __IO uint32_t CR;
396  __IO uint32_t NDTR;
397  __IO uint32_t PAR;
398  __IO uint32_t M0AR;
399  __IO uint32_t M1AR;
400  __IO uint32_t FCR;
401 } DMA_Stream_TypeDef;
402 
403 typedef struct
404 {
405  __IO uint32_t LISR;
406  __IO uint32_t HISR;
407  __IO uint32_t LIFCR;
408  __IO uint32_t HIFCR;
409 } DMA_TypeDef;
410 
411 
416 typedef struct
417 {
418  __IO uint32_t CR;
419  __IO uint32_t ISR;
420  __IO uint32_t IFCR;
421  __IO uint32_t FGMAR;
422  __IO uint32_t FGOR;
423  __IO uint32_t BGMAR;
424  __IO uint32_t BGOR;
425  __IO uint32_t FGPFCCR;
426  __IO uint32_t FGCOLR;
427  __IO uint32_t BGPFCCR;
428  __IO uint32_t BGCOLR;
429  __IO uint32_t FGCMAR;
430  __IO uint32_t BGCMAR;
431  __IO uint32_t OPFCCR;
432  __IO uint32_t OCOLR;
433  __IO uint32_t OMAR;
434  __IO uint32_t OOR;
435  __IO uint32_t NLR;
436  __IO uint32_t LWR;
437  __IO uint32_t AMTCR;
438  uint32_t RESERVED[236];
439  __IO uint32_t FGCLUT[256];
440  __IO uint32_t BGCLUT[256];
441 } DMA2D_TypeDef;
442 
443 
448 typedef struct
449 {
450  __IO uint32_t MACCR;
451  __IO uint32_t MACFFR;
452  __IO uint32_t MACHTHR;
453  __IO uint32_t MACHTLR;
454  __IO uint32_t MACMIIAR;
455  __IO uint32_t MACMIIDR;
456  __IO uint32_t MACFCR;
457  __IO uint32_t MACVLANTR; /* 8 */
458  uint32_t RESERVED0[2];
459  __IO uint32_t MACRWUFFR; /* 11 */
460  __IO uint32_t MACPMTCSR;
461  uint32_t RESERVED1[2];
462  __IO uint32_t MACSR; /* 15 */
463  __IO uint32_t MACIMR;
464  __IO uint32_t MACA0HR;
465  __IO uint32_t MACA0LR;
466  __IO uint32_t MACA1HR;
467  __IO uint32_t MACA1LR;
468  __IO uint32_t MACA2HR;
469  __IO uint32_t MACA2LR;
470  __IO uint32_t MACA3HR;
471  __IO uint32_t MACA3LR; /* 24 */
472  uint32_t RESERVED2[40];
473  __IO uint32_t MMCCR; /* 65 */
474  __IO uint32_t MMCRIR;
475  __IO uint32_t MMCTIR;
476  __IO uint32_t MMCRIMR;
477  __IO uint32_t MMCTIMR; /* 69 */
478  uint32_t RESERVED3[14];
479  __IO uint32_t MMCTGFSCCR; /* 84 */
480  __IO uint32_t MMCTGFMSCCR;
481  uint32_t RESERVED4[5];
482  __IO uint32_t MMCTGFCR;
483  uint32_t RESERVED5[10];
484  __IO uint32_t MMCRFCECR;
485  __IO uint32_t MMCRFAECR;
486  uint32_t RESERVED6[10];
487  __IO uint32_t MMCRGUFCR;
488  uint32_t RESERVED7[334];
489  __IO uint32_t PTPTSCR;
490  __IO uint32_t PTPSSIR;
491  __IO uint32_t PTPTSHR;
492  __IO uint32_t PTPTSLR;
493  __IO uint32_t PTPTSHUR;
494  __IO uint32_t PTPTSLUR;
495  __IO uint32_t PTPTSAR;
496  __IO uint32_t PTPTTHR;
497  __IO uint32_t PTPTTLR;
498  __IO uint32_t RESERVED8;
499  __IO uint32_t PTPTSSR;
500  uint32_t RESERVED9[565];
501  __IO uint32_t DMABMR;
502  __IO uint32_t DMATPDR;
503  __IO uint32_t DMARPDR;
504  __IO uint32_t DMARDLAR;
505  __IO uint32_t DMATDLAR;
506  __IO uint32_t DMASR;
507  __IO uint32_t DMAOMR;
508  __IO uint32_t DMAIER;
509  __IO uint32_t DMAMFBOCR;
510  __IO uint32_t DMARSWTR;
511  uint32_t RESERVED10[8];
512  __IO uint32_t DMACHTDR;
513  __IO uint32_t DMACHRDR;
514  __IO uint32_t DMACHTBAR;
515  __IO uint32_t DMACHRBAR;
516 } ETH_TypeDef;
517 
522 typedef struct
523 {
524  __IO uint32_t IMR;
525  __IO uint32_t EMR;
526  __IO uint32_t RTSR;
527  __IO uint32_t FTSR;
528  __IO uint32_t SWIER;
529  __IO uint32_t PR;
530 } EXTI_TypeDef;
531 
536 typedef struct
537 {
538  __IO uint32_t ACR;
539  __IO uint32_t KEYR;
540  __IO uint32_t OPTKEYR;
541  __IO uint32_t SR;
542  __IO uint32_t CR;
543  __IO uint32_t OPTCR;
544  __IO uint32_t OPTCR1;
545 } FLASH_TypeDef;
546 
547 
548 
553 typedef struct
554 {
555  __IO uint32_t BTCR[8];
556 } FMC_Bank1_TypeDef;
557 
562 typedef struct
563 {
564  __IO uint32_t BWTR[7];
565 } FMC_Bank1E_TypeDef;
566 
571 typedef struct
572 {
573  __IO uint32_t PCR;
574  __IO uint32_t SR;
575  __IO uint32_t PMEM;
576  __IO uint32_t PATT;
577  uint32_t RESERVED0;
578  __IO uint32_t ECCR;
579 } FMC_Bank3_TypeDef;
580 
585 typedef struct
586 {
587  __IO uint32_t SDCR[2];
588  __IO uint32_t SDTR[2];
589  __IO uint32_t SDCMR;
590  __IO uint32_t SDRTR;
591  __IO uint32_t SDSR;
592 } FMC_Bank5_6_TypeDef;
593 
594 
599 typedef struct
600 {
601  __IO uint32_t MODER;
602  __IO uint32_t OTYPER;
603  __IO uint32_t OSPEEDR;
604  __IO uint32_t PUPDR;
605  __IO uint32_t IDR;
606  __IO uint32_t ODR;
607  __IO uint32_t BSRR;
608  __IO uint32_t LCKR;
609  __IO uint32_t AFR[2];
610 } GPIO_TypeDef;
611 
616 typedef struct
617 {
618  __IO uint32_t MEMRMP;
619  __IO uint32_t PMC;
620  __IO uint32_t EXTICR[4];
621  uint32_t RESERVED[2];
622  __IO uint32_t CMPCR;
623 } SYSCFG_TypeDef;
624 
629 typedef struct
630 {
631  __IO uint32_t CR1;
632  __IO uint32_t CR2;
633  __IO uint32_t OAR1;
634  __IO uint32_t OAR2;
635  __IO uint32_t TIMINGR;
636  __IO uint32_t TIMEOUTR;
637  __IO uint32_t ISR;
638  __IO uint32_t ICR;
639  __IO uint32_t PECR;
640  __IO uint32_t RXDR;
641  __IO uint32_t TXDR;
642 } I2C_TypeDef;
643 
648 typedef struct
649 {
650  __IO uint32_t KR;
651  __IO uint32_t PR;
652  __IO uint32_t RLR;
653  __IO uint32_t SR;
654  __IO uint32_t WINR;
655 } IWDG_TypeDef;
656 
657 
662 typedef struct
663 {
664  uint32_t RESERVED0[2];
665  __IO uint32_t SSCR;
666  __IO uint32_t BPCR;
667  __IO uint32_t AWCR;
668  __IO uint32_t TWCR;
669  __IO uint32_t GCR;
670  uint32_t RESERVED1[2];
671  __IO uint32_t SRCR;
672  uint32_t RESERVED2[1];
673  __IO uint32_t BCCR;
674  uint32_t RESERVED3[1];
675  __IO uint32_t IER;
676  __IO uint32_t ISR;
677  __IO uint32_t ICR;
678  __IO uint32_t LIPCR;
679  __IO uint32_t CPSR;
680  __IO uint32_t CDSR;
681 } LTDC_TypeDef;
682 
687 typedef struct
688 {
689  __IO uint32_t CR;
690  __IO uint32_t WHPCR;
691  __IO uint32_t WVPCR;
692  __IO uint32_t CKCR;
693  __IO uint32_t PFCR;
694  __IO uint32_t CACR;
695  __IO uint32_t DCCR;
696  __IO uint32_t BFCR;
697  uint32_t RESERVED0[2];
698  __IO uint32_t CFBAR;
699  __IO uint32_t CFBLR;
700  __IO uint32_t CFBLNR;
701  uint32_t RESERVED1[3];
702  __IO uint32_t CLUTWR;
704 } LTDC_Layer_TypeDef;
705 
710 typedef struct
711 {
712  __IO uint32_t CR1;
713  __IO uint32_t CSR1;
714  __IO uint32_t CR2;
715  __IO uint32_t CSR2;
716 } PWR_TypeDef;
717 
718 
723 typedef struct
724 {
725  __IO uint32_t CR;
726  __IO uint32_t PLLCFGR;
727  __IO uint32_t CFGR;
728  __IO uint32_t CIR;
729  __IO uint32_t AHB1RSTR;
730  __IO uint32_t AHB2RSTR;
731  __IO uint32_t AHB3RSTR;
732  uint32_t RESERVED0;
733  __IO uint32_t APB1RSTR;
734  __IO uint32_t APB2RSTR;
735  uint32_t RESERVED1[2];
736  __IO uint32_t AHB1ENR;
737  __IO uint32_t AHB2ENR;
738  __IO uint32_t AHB3ENR;
739  uint32_t RESERVED2;
740  __IO uint32_t APB1ENR;
741  __IO uint32_t APB2ENR;
742  uint32_t RESERVED3[2];
743  __IO uint32_t AHB1LPENR;
744  __IO uint32_t AHB2LPENR;
745  __IO uint32_t AHB3LPENR;
746  uint32_t RESERVED4;
747  __IO uint32_t APB1LPENR;
748  __IO uint32_t APB2LPENR;
749  uint32_t RESERVED5[2];
750  __IO uint32_t BDCR;
751  __IO uint32_t CSR;
752  uint32_t RESERVED6[2];
753  __IO uint32_t SSCGR;
754  __IO uint32_t PLLI2SCFGR;
755  __IO uint32_t PLLSAICFGR;
756  __IO uint32_t DCKCFGR1;
757  __IO uint32_t DCKCFGR2;
759 } RCC_TypeDef;
760 
765 typedef struct
766 {
767  __IO uint32_t TR;
768  __IO uint32_t DR;
769  __IO uint32_t CR;
770  __IO uint32_t ISR;
771  __IO uint32_t PRER;
772  __IO uint32_t WUTR;
773  uint32_t reserved;
774  __IO uint32_t ALRMAR;
775  __IO uint32_t ALRMBR;
776  __IO uint32_t WPR;
777  __IO uint32_t SSR;
778  __IO uint32_t SHIFTR;
779  __IO uint32_t TSTR;
780  __IO uint32_t TSDR;
781  __IO uint32_t TSSSR;
782  __IO uint32_t CALR;
783  __IO uint32_t TAMPCR;
784  __IO uint32_t ALRMASSR;
785  __IO uint32_t ALRMBSSR;
786  __IO uint32_t OR;
787  __IO uint32_t BKP0R;
788  __IO uint32_t BKP1R;
789  __IO uint32_t BKP2R;
790  __IO uint32_t BKP3R;
791  __IO uint32_t BKP4R;
792  __IO uint32_t BKP5R;
793  __IO uint32_t BKP6R;
794  __IO uint32_t BKP7R;
795  __IO uint32_t BKP8R;
796  __IO uint32_t BKP9R;
797  __IO uint32_t BKP10R;
798  __IO uint32_t BKP11R;
799  __IO uint32_t BKP12R;
800  __IO uint32_t BKP13R;
801  __IO uint32_t BKP14R;
802  __IO uint32_t BKP15R;
803  __IO uint32_t BKP16R;
804  __IO uint32_t BKP17R;
805  __IO uint32_t BKP18R;
806  __IO uint32_t BKP19R;
807  __IO uint32_t BKP20R;
808  __IO uint32_t BKP21R;
809  __IO uint32_t BKP22R;
810  __IO uint32_t BKP23R;
811  __IO uint32_t BKP24R;
812  __IO uint32_t BKP25R;
813  __IO uint32_t BKP26R;
814  __IO uint32_t BKP27R;
815  __IO uint32_t BKP28R;
816  __IO uint32_t BKP29R;
817  __IO uint32_t BKP30R;
818  __IO uint32_t BKP31R;
819 } RTC_TypeDef;
820 
821 
826 typedef struct
827 {
828  __IO uint32_t GCR;
829 } SAI_TypeDef;
830 
831 typedef struct
832 {
833  __IO uint32_t CR1;
834  __IO uint32_t CR2;
835  __IO uint32_t FRCR;
836  __IO uint32_t SLOTR;
837  __IO uint32_t IMR;
838  __IO uint32_t SR;
839  __IO uint32_t CLRFR;
840  __IO uint32_t DR;
841 } SAI_Block_TypeDef;
842 
847 typedef struct
848 {
849  __IO uint32_t CR;
850  __IO uint32_t IMR;
851  __IO uint32_t SR;
852  __IO uint32_t IFCR;
853  __IO uint32_t DR;
854  __IO uint32_t CSR;
855  __IO uint32_t DIR;
856 } SPDIFRX_TypeDef;
857 
858 
863 typedef struct
864 {
865  __IO uint32_t POWER;
866  __IO uint32_t CLKCR;
867  __IO uint32_t ARG;
868  __IO uint32_t CMD;
869  __I uint32_t RESPCMD;
870  __I uint32_t RESP1;
871  __I uint32_t RESP2;
872  __I uint32_t RESP3;
873  __I uint32_t RESP4;
874  __IO uint32_t DTIMER;
875  __IO uint32_t DLEN;
876  __IO uint32_t DCTRL;
877  __I uint32_t DCOUNT;
878  __I uint32_t STA;
879  __IO uint32_t ICR;
880  __IO uint32_t MASK;
881  uint32_t RESERVED0[2];
882  __I uint32_t FIFOCNT;
883  uint32_t RESERVED1[13];
884  __IO uint32_t FIFO;
885 } SDMMC_TypeDef;
886 
891 typedef struct
892 {
893  __IO uint32_t CR1;
894  __IO uint32_t CR2;
895  __IO uint32_t SR;
896  __IO uint32_t DR;
897  __IO uint32_t CRCPR;
898  __IO uint32_t RXCRCR;
899  __IO uint32_t TXCRCR;
900  __IO uint32_t I2SCFGR;
901  __IO uint32_t I2SPR;
902 } SPI_TypeDef;
903 
908 typedef struct
909 {
910  __IO uint32_t CR;
911  __IO uint32_t DCR;
912  __IO uint32_t SR;
913  __IO uint32_t FCR;
914  __IO uint32_t DLR;
915  __IO uint32_t CCR;
916  __IO uint32_t AR;
917  __IO uint32_t ABR;
918  __IO uint32_t DR;
919  __IO uint32_t PSMKR;
920  __IO uint32_t PSMAR;
921  __IO uint32_t PIR;
922  __IO uint32_t LPTR;
923 } QUADSPI_TypeDef;
924 
929 typedef struct
930 {
931  __IO uint32_t CR1;
932  __IO uint32_t CR2;
933  __IO uint32_t SMCR;
934  __IO uint32_t DIER;
935  __IO uint32_t SR;
936  __IO uint32_t EGR;
937  __IO uint32_t CCMR1;
938  __IO uint32_t CCMR2;
939  __IO uint32_t CCER;
940  __IO uint32_t CNT;
941  __IO uint32_t PSC;
942  __IO uint32_t ARR;
943  __IO uint32_t RCR;
944  __IO uint32_t CCR1;
945  __IO uint32_t CCR2;
946  __IO uint32_t CCR3;
947  __IO uint32_t CCR4;
948  __IO uint32_t BDTR;
949  __IO uint32_t DCR;
950  __IO uint32_t DMAR;
951  __IO uint32_t OR;
952  __IO uint32_t CCMR3;
953  __IO uint32_t CCR5;
954  __IO uint32_t CCR6;
956 } TIM_TypeDef;
957 
961 typedef struct
962 {
963  __IO uint32_t ISR;
964  __IO uint32_t ICR;
965  __IO uint32_t IER;
966  __IO uint32_t CFGR;
967  __IO uint32_t CR;
968  __IO uint32_t CMP;
969  __IO uint32_t ARR;
970  __IO uint32_t CNT;
971 } LPTIM_TypeDef;
972 
973 
978 typedef struct
979 {
980  __IO uint32_t CR1;
981  __IO uint32_t CR2;
982  __IO uint32_t CR3;
983  __IO uint32_t BRR;
984  __IO uint32_t GTPR;
985  __IO uint32_t RTOR;
986  __IO uint32_t RQR;
987  __IO uint32_t ISR;
988  __IO uint32_t ICR;
989  __IO uint32_t RDR;
990  __IO uint32_t TDR;
991 } USART_TypeDef;
992 
993 
998 typedef struct
999 {
1000  __IO uint32_t CR;
1001  __IO uint32_t CFR;
1002  __IO uint32_t SR;
1003 } WWDG_TypeDef;
1004 
1009 typedef struct
1010 {
1011  __IO uint32_t CR;
1012  __IO uint32_t SR;
1013  __IO uint32_t DR;
1014  __IO uint32_t DOUT;
1015  __IO uint32_t DMACR;
1016  __IO uint32_t IMSCR;
1017  __IO uint32_t RISR;
1018  __IO uint32_t MISR;
1019  __IO uint32_t K0LR;
1020  __IO uint32_t K0RR;
1021  __IO uint32_t K1LR;
1022  __IO uint32_t K1RR;
1023  __IO uint32_t K2LR;
1024  __IO uint32_t K2RR;
1025  __IO uint32_t K3LR;
1026  __IO uint32_t K3RR;
1027  __IO uint32_t IV0LR;
1028  __IO uint32_t IV0RR;
1029  __IO uint32_t IV1LR;
1030  __IO uint32_t IV1RR;
1031  __IO uint32_t CSGCMCCM0R;
1032  __IO uint32_t CSGCMCCM1R;
1033  __IO uint32_t CSGCMCCM2R;
1034  __IO uint32_t CSGCMCCM3R;
1035  __IO uint32_t CSGCMCCM4R;
1036  __IO uint32_t CSGCMCCM5R;
1037  __IO uint32_t CSGCMCCM6R;
1038  __IO uint32_t CSGCMCCM7R;
1039  __IO uint32_t CSGCM0R;
1040  __IO uint32_t CSGCM1R;
1041  __IO uint32_t CSGCM2R;
1042  __IO uint32_t CSGCM3R;
1043  __IO uint32_t CSGCM4R;
1044  __IO uint32_t CSGCM5R;
1045  __IO uint32_t CSGCM6R;
1046  __IO uint32_t CSGCM7R;
1047 } CRYP_TypeDef;
1048 
1053 typedef struct
1054 {
1055  __IO uint32_t CR;
1056  __IO uint32_t DIN;
1057  __IO uint32_t STR;
1058  __IO uint32_t HR[5];
1059  __IO uint32_t IMR;
1060  __IO uint32_t SR;
1061  uint32_t RESERVED[52];
1062  __IO uint32_t CSR[54];
1063 } HASH_TypeDef;
1064 
1069 typedef struct
1070 {
1071  __IO uint32_t HR[8];
1072 } HASH_DIGEST_TypeDef;
1073 
1078 typedef struct
1079 {
1080  __IO uint32_t CR;
1081  __IO uint32_t SR;
1082  __IO uint32_t DR;
1083 } RNG_TypeDef;
1084 
1092 typedef struct
1093 {
1094  __IO uint32_t GOTGCTL;
1095  __IO uint32_t GOTGINT;
1096  __IO uint32_t GAHBCFG;
1097  __IO uint32_t GUSBCFG;
1098  __IO uint32_t GRSTCTL;
1099  __IO uint32_t GINTSTS;
1100  __IO uint32_t GINTMSK;
1101  __IO uint32_t GRXSTSR;
1102  __IO uint32_t GRXSTSP;
1103  __IO uint32_t GRXFSIZ;
1104  __IO uint32_t DIEPTXF0_HNPTXFSIZ;
1105  __IO uint32_t HNPTXSTS;
1106  uint32_t Reserved30[2];
1107  __IO uint32_t GCCFG;
1108  __IO uint32_t CID;
1109  uint32_t Reserved5[3];
1110  __IO uint32_t GHWCFG3;
1111  uint32_t Reserved6;
1112  __IO uint32_t GLPMCFG;
1113  __IO uint32_t GPWRDN;
1114  __IO uint32_t GDFIFOCFG;
1115  __IO uint32_t GADPCTL;
1116  uint32_t Reserved43[39];
1117  __IO uint32_t HPTXFSIZ;
1118  __IO uint32_t DIEPTXF[0x0F];
1119 } USB_OTG_GlobalTypeDef;
1120 
1121 
1125 typedef struct
1126 {
1127  __IO uint32_t DCFG;
1128  __IO uint32_t DCTL;
1129  __IO uint32_t DSTS;
1130  uint32_t Reserved0C;
1131  __IO uint32_t DIEPMSK;
1132  __IO uint32_t DOEPMSK;
1133  __IO uint32_t DAINT;
1134  __IO uint32_t DAINTMSK;
1135  uint32_t Reserved20;
1136  uint32_t Reserved9;
1137  __IO uint32_t DVBUSDIS;
1138  __IO uint32_t DVBUSPULSE;
1139  __IO uint32_t DTHRCTL;
1140  __IO uint32_t DIEPEMPMSK;
1141  __IO uint32_t DEACHINT;
1142  __IO uint32_t DEACHMSK;
1143  uint32_t Reserved40;
1144  __IO uint32_t DINEP1MSK;
1145  uint32_t Reserved44[15];
1146  __IO uint32_t DOUTEP1MSK;
1147 } USB_OTG_DeviceTypeDef;
1148 
1149 
1153 typedef struct
1154 {
1155  __IO uint32_t DIEPCTL;
1156  uint32_t Reserved04;
1157  __IO uint32_t DIEPINT;
1158  uint32_t Reserved0C;
1159  __IO uint32_t DIEPTSIZ;
1160  __IO uint32_t DIEPDMA;
1161  __IO uint32_t DTXFSTS;
1162  uint32_t Reserved18;
1163 } USB_OTG_INEndpointTypeDef;
1164 
1165 
1169 typedef struct
1170 {
1171  __IO uint32_t DOEPCTL;
1172  uint32_t Reserved04;
1173  __IO uint32_t DOEPINT;
1174  uint32_t Reserved0C;
1175  __IO uint32_t DOEPTSIZ;
1176  __IO uint32_t DOEPDMA;
1177  uint32_t Reserved18[2];
1178 } USB_OTG_OUTEndpointTypeDef;
1179 
1180 
1184 typedef struct
1185 {
1186  __IO uint32_t HCFG;
1187  __IO uint32_t HFIR;
1188  __IO uint32_t HFNUM;
1189  uint32_t Reserved40C;
1190  __IO uint32_t HPTXSTS;
1191  __IO uint32_t HAINT;
1192  __IO uint32_t HAINTMSK;
1193 } USB_OTG_HostTypeDef;
1194 
1198 typedef struct
1199 {
1200  __IO uint32_t HCCHAR;
1201  __IO uint32_t HCSPLT;
1202  __IO uint32_t HCINT;
1203  __IO uint32_t HCINTMSK;
1204  __IO uint32_t HCTSIZ;
1205  __IO uint32_t HCDMA;
1206  uint32_t Reserved[2];
1207 } USB_OTG_HostChannelTypeDef;
1218 #define RAMITCM_BASE 0x00000000U
1219 #define FLASHITCM_BASE 0x00200000U
1220 #define FLASHAXI_BASE 0x08000000U
1221 #define RAMDTCM_BASE 0x20000000U
1222 #define PERIPH_BASE 0x40000000U
1223 #define BKPSRAM_BASE 0x40024000U
1224 #define QSPI_BASE 0x90000000U
1225 #define FMC_R_BASE 0xA0000000U
1226 #define QSPI_R_BASE 0xA0001000U
1227 #define SRAM1_BASE 0x20010000U
1228 #define SRAM2_BASE 0x2004C000U
1229 #define FLASH_END 0x080FFFFFU
1231 /* Legacy define */
1232 #define FLASH_BASE FLASHAXI_BASE
1233 
1235 #define APB1PERIPH_BASE PERIPH_BASE
1236 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
1237 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
1238 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
1239 
1241 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
1242 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
1243 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
1244 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
1245 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
1246 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
1247 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
1248 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
1249 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
1250 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
1251 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
1252 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
1253 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
1254 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
1255 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
1256 #define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U)
1257 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
1258 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
1259 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
1260 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
1261 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
1262 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
1263 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
1264 #define I2C4_BASE (APB1PERIPH_BASE + 0x6000U)
1265 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
1266 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
1267 #define CEC_BASE (APB1PERIPH_BASE + 0x6C00U)
1268 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
1269 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
1270 #define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
1271 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
1272 
1274 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
1275 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
1276 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
1277 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
1278 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
1279 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
1280 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
1281 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
1282 #define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U)
1283 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1284 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
1285 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
1286 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
1287 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
1288 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
1289 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
1290 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
1291 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
1292 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
1293 #define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U)
1294 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
1295 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
1296 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004U)
1297 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024U)
1298 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
1299 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
1300 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
1301 
1302 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
1303 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
1304 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
1305 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
1306 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
1307 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
1308 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
1309 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
1310 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
1311 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
1312 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
1313 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1314 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
1315 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
1316 #define UID_BASE 0x1FF0F420U
1317 #define FLASHSIZE_BASE 0x1FF0F442U
1318 #define PACKAGESIZE_BASE 0x1FFF7BF0U
1319 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
1320 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
1321 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
1322 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
1323 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
1324 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
1325 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
1326 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
1327 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
1328 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
1329 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
1330 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
1331 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
1332 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
1333 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
1334 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
1335 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
1336 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
1337 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
1338 #define ETH_MAC_BASE (ETH_BASE)
1339 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
1340 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
1341 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
1342 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
1343 
1344 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
1345 #define CRYP_BASE (AHB2PERIPH_BASE + 0x60000U)
1346 #define HASH_BASE (AHB2PERIPH_BASE + 0x60400U)
1347 #define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710U)
1348 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
1349 
1350 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
1351 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
1352 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
1353 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
1354 
1355 /* Debug MCU registers base address */
1356 #define DBGMCU_BASE 0xE0042000U
1357 
1359 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
1360 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
1361 
1362 #define USB_OTG_GLOBAL_BASE 0x000U
1363 #define USB_OTG_DEVICE_BASE 0x800U
1364 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
1365 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
1366 #define USB_OTG_EP_REG_SIZE 0x20U
1367 #define USB_OTG_HOST_BASE 0x400U
1368 #define USB_OTG_HOST_PORT_BASE 0x440U
1369 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
1370 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
1371 #define USB_OTG_PCGCCTL_BASE 0xE00U
1372 #define USB_OTG_FIFO_BASE 0x1000U
1373 #define USB_OTG_FIFO_SIZE 0x1000U
1374 
1382 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1383 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1384 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1385 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1386 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1387 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1388 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1389 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1390 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1391 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1392 #define RTC ((RTC_TypeDef *) RTC_BASE)
1393 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1394 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1395 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1396 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1397 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
1398 #define USART2 ((USART_TypeDef *) USART2_BASE)
1399 #define USART3 ((USART_TypeDef *) USART3_BASE)
1400 #define UART4 ((USART_TypeDef *) UART4_BASE)
1401 #define UART5 ((USART_TypeDef *) UART5_BASE)
1402 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1403 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1404 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1405 #define I2C4 ((I2C_TypeDef *) I2C4_BASE)
1406 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1407 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1408 #define CEC ((CEC_TypeDef *) CEC_BASE)
1409 #define PWR ((PWR_TypeDef *) PWR_BASE)
1410 #define DAC ((DAC_TypeDef *) DAC_BASE)
1411 #define UART7 ((USART_TypeDef *) UART7_BASE)
1412 #define UART8 ((USART_TypeDef *) UART8_BASE)
1413 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1414 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1415 #define USART1 ((USART_TypeDef *) USART1_BASE)
1416 #define USART6 ((USART_TypeDef *) USART6_BASE)
1417 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1418 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1419 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1420 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1421 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
1422 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1423 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1424 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1425 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1426 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1427 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1428 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1429 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1430 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
1431 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1432 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
1433 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1434 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1435 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
1436 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
1437 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
1438 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
1439 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
1440 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1441 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1442 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1443 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1444 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1445 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1446 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1447 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1448 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1449 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
1450 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
1451 #define CRC ((CRC_TypeDef *) CRC_BASE)
1452 #define RCC ((RCC_TypeDef *) RCC_BASE)
1453 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1454 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1455 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1456 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1457 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1458 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1459 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1460 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1461 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1462 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1463 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1464 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1465 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1466 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1467 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1468 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1469 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1470 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1471 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1472 #define ETH ((ETH_TypeDef *) ETH_BASE)
1473 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1474 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1475 #define CRYP ((CRYP_TypeDef *) CRYP_BASE)
1476 #define HASH ((HASH_TypeDef *) HASH_BASE)
1477 #define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
1478 #define RNG ((RNG_TypeDef *) RNG_BASE)
1479 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1480 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1481 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1482 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1483 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1484 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1485 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1486 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1487 
1500 /******************************************************************************/
1501 /* Peripheral Registers_Bits_Definition */
1502 /******************************************************************************/
1503 
1504 /******************************************************************************/
1505 /* */
1506 /* Analog to Digital Converter */
1507 /* */
1508 /******************************************************************************/
1509 /******************** Bit definition for ADC_SR register ********************/
1510 #define ADC_SR_AWD 0x00000001U
1511 #define ADC_SR_EOC 0x00000002U
1512 #define ADC_SR_JEOC 0x00000004U
1513 #define ADC_SR_JSTRT 0x00000008U
1514 #define ADC_SR_STRT 0x00000010U
1515 #define ADC_SR_OVR 0x00000020U
1517 /******************* Bit definition for ADC_CR1 register ********************/
1518 #define ADC_CR1_AWDCH 0x0000001FU
1519 #define ADC_CR1_AWDCH_0 0x00000001U
1520 #define ADC_CR1_AWDCH_1 0x00000002U
1521 #define ADC_CR1_AWDCH_2 0x00000004U
1522 #define ADC_CR1_AWDCH_3 0x00000008U
1523 #define ADC_CR1_AWDCH_4 0x00000010U
1524 #define ADC_CR1_EOCIE 0x00000020U
1525 #define ADC_CR1_AWDIE 0x00000040U
1526 #define ADC_CR1_JEOCIE 0x00000080U
1527 #define ADC_CR1_SCAN 0x00000100U
1528 #define ADC_CR1_AWDSGL 0x00000200U
1529 #define ADC_CR1_JAUTO 0x00000400U
1530 #define ADC_CR1_DISCEN 0x00000800U
1531 #define ADC_CR1_JDISCEN 0x00001000U
1532 #define ADC_CR1_DISCNUM 0x0000E000U
1533 #define ADC_CR1_DISCNUM_0 0x00002000U
1534 #define ADC_CR1_DISCNUM_1 0x00004000U
1535 #define ADC_CR1_DISCNUM_2 0x00008000U
1536 #define ADC_CR1_JAWDEN 0x00400000U
1537 #define ADC_CR1_AWDEN 0x00800000U
1538 #define ADC_CR1_RES 0x03000000U
1539 #define ADC_CR1_RES_0 0x01000000U
1540 #define ADC_CR1_RES_1 0x02000000U
1541 #define ADC_CR1_OVRIE 0x04000000U
1543 /******************* Bit definition for ADC_CR2 register ********************/
1544 #define ADC_CR2_ADON 0x00000001U
1545 #define ADC_CR2_CONT 0x00000002U
1546 #define ADC_CR2_DMA 0x00000100U
1547 #define ADC_CR2_DDS 0x00000200U
1548 #define ADC_CR2_EOCS 0x00000400U
1549 #define ADC_CR2_ALIGN 0x00000800U
1550 #define ADC_CR2_JEXTSEL 0x000F0000U
1551 #define ADC_CR2_JEXTSEL_0 0x00010000U
1552 #define ADC_CR2_JEXTSEL_1 0x00020000U
1553 #define ADC_CR2_JEXTSEL_2 0x00040000U
1554 #define ADC_CR2_JEXTSEL_3 0x00080000U
1555 #define ADC_CR2_JEXTEN 0x00300000U
1556 #define ADC_CR2_JEXTEN_0 0x00100000U
1557 #define ADC_CR2_JEXTEN_1 0x00200000U
1558 #define ADC_CR2_JSWSTART 0x00400000U
1559 #define ADC_CR2_EXTSEL 0x0F000000U
1560 #define ADC_CR2_EXTSEL_0 0x01000000U
1561 #define ADC_CR2_EXTSEL_1 0x02000000U
1562 #define ADC_CR2_EXTSEL_2 0x04000000U
1563 #define ADC_CR2_EXTSEL_3 0x08000000U
1564 #define ADC_CR2_EXTEN 0x30000000U
1565 #define ADC_CR2_EXTEN_0 0x10000000U
1566 #define ADC_CR2_EXTEN_1 0x20000000U
1567 #define ADC_CR2_SWSTART 0x40000000U
1569 /****************** Bit definition for ADC_SMPR1 register *******************/
1570 #define ADC_SMPR1_SMP10 0x00000007U
1571 #define ADC_SMPR1_SMP10_0 0x00000001U
1572 #define ADC_SMPR1_SMP10_1 0x00000002U
1573 #define ADC_SMPR1_SMP10_2 0x00000004U
1574 #define ADC_SMPR1_SMP11 0x00000038U
1575 #define ADC_SMPR1_SMP11_0 0x00000008U
1576 #define ADC_SMPR1_SMP11_1 0x00000010U
1577 #define ADC_SMPR1_SMP11_2 0x00000020U
1578 #define ADC_SMPR1_SMP12 0x000001C0U
1579 #define ADC_SMPR1_SMP12_0 0x00000040U
1580 #define ADC_SMPR1_SMP12_1 0x00000080U
1581 #define ADC_SMPR1_SMP12_2 0x00000100U
1582 #define ADC_SMPR1_SMP13 0x00000E00U
1583 #define ADC_SMPR1_SMP13_0 0x00000200U
1584 #define ADC_SMPR1_SMP13_1 0x00000400U
1585 #define ADC_SMPR1_SMP13_2 0x00000800U
1586 #define ADC_SMPR1_SMP14 0x00007000U
1587 #define ADC_SMPR1_SMP14_0 0x00001000U
1588 #define ADC_SMPR1_SMP14_1 0x00002000U
1589 #define ADC_SMPR1_SMP14_2 0x00004000U
1590 #define ADC_SMPR1_SMP15 0x00038000U
1591 #define ADC_SMPR1_SMP15_0 0x00008000U
1592 #define ADC_SMPR1_SMP15_1 0x00010000U
1593 #define ADC_SMPR1_SMP15_2 0x00020000U
1594 #define ADC_SMPR1_SMP16 0x001C0000U
1595 #define ADC_SMPR1_SMP16_0 0x00040000U
1596 #define ADC_SMPR1_SMP16_1 0x00080000U
1597 #define ADC_SMPR1_SMP16_2 0x00100000U
1598 #define ADC_SMPR1_SMP17 0x00E00000U
1599 #define ADC_SMPR1_SMP17_0 0x00200000U
1600 #define ADC_SMPR1_SMP17_1 0x00400000U
1601 #define ADC_SMPR1_SMP17_2 0x00800000U
1602 #define ADC_SMPR1_SMP18 0x07000000U
1603 #define ADC_SMPR1_SMP18_0 0x01000000U
1604 #define ADC_SMPR1_SMP18_1 0x02000000U
1605 #define ADC_SMPR1_SMP18_2 0x04000000U
1607 /****************** Bit definition for ADC_SMPR2 register *******************/
1608 #define ADC_SMPR2_SMP0 0x00000007U
1609 #define ADC_SMPR2_SMP0_0 0x00000001U
1610 #define ADC_SMPR2_SMP0_1 0x00000002U
1611 #define ADC_SMPR2_SMP0_2 0x00000004U
1612 #define ADC_SMPR2_SMP1 0x00000038U
1613 #define ADC_SMPR2_SMP1_0 0x00000008U
1614 #define ADC_SMPR2_SMP1_1 0x00000010U
1615 #define ADC_SMPR2_SMP1_2 0x00000020U
1616 #define ADC_SMPR2_SMP2 0x000001C0U
1617 #define ADC_SMPR2_SMP2_0 0x00000040U
1618 #define ADC_SMPR2_SMP2_1 0x00000080U
1619 #define ADC_SMPR2_SMP2_2 0x00000100U
1620 #define ADC_SMPR2_SMP3 0x00000E00U
1621 #define ADC_SMPR2_SMP3_0 0x00000200U
1622 #define ADC_SMPR2_SMP3_1 0x00000400U
1623 #define ADC_SMPR2_SMP3_2 0x00000800U
1624 #define ADC_SMPR2_SMP4 0x00007000U
1625 #define ADC_SMPR2_SMP4_0 0x00001000U
1626 #define ADC_SMPR2_SMP4_1 0x00002000U
1627 #define ADC_SMPR2_SMP4_2 0x00004000U
1628 #define ADC_SMPR2_SMP5 0x00038000U
1629 #define ADC_SMPR2_SMP5_0 0x00008000U
1630 #define ADC_SMPR2_SMP5_1 0x00010000U
1631 #define ADC_SMPR2_SMP5_2 0x00020000U
1632 #define ADC_SMPR2_SMP6 0x001C0000U
1633 #define ADC_SMPR2_SMP6_0 0x00040000U
1634 #define ADC_SMPR2_SMP6_1 0x00080000U
1635 #define ADC_SMPR2_SMP6_2 0x00100000U
1636 #define ADC_SMPR2_SMP7 0x00E00000U
1637 #define ADC_SMPR2_SMP7_0 0x00200000U
1638 #define ADC_SMPR2_SMP7_1 0x00400000U
1639 #define ADC_SMPR2_SMP7_2 0x00800000U
1640 #define ADC_SMPR2_SMP8 0x07000000U
1641 #define ADC_SMPR2_SMP8_0 0x01000000U
1642 #define ADC_SMPR2_SMP8_1 0x02000000U
1643 #define ADC_SMPR2_SMP8_2 0x04000000U
1644 #define ADC_SMPR2_SMP9 0x38000000U
1645 #define ADC_SMPR2_SMP9_0 0x08000000U
1646 #define ADC_SMPR2_SMP9_1 0x10000000U
1647 #define ADC_SMPR2_SMP9_2 0x20000000U
1649 /****************** Bit definition for ADC_JOFR1 register *******************/
1650 #define ADC_JOFR1_JOFFSET1 0x0FFFU
1652 /****************** Bit definition for ADC_JOFR2 register *******************/
1653 #define ADC_JOFR2_JOFFSET2 0x0FFFU
1655 /****************** Bit definition for ADC_JOFR3 register *******************/
1656 #define ADC_JOFR3_JOFFSET3 0x0FFFU
1658 /****************** Bit definition for ADC_JOFR4 register *******************/
1659 #define ADC_JOFR4_JOFFSET4 0x0FFFU
1661 /******************* Bit definition for ADC_HTR register ********************/
1662 #define ADC_HTR_HT 0x0FFFU
1664 /******************* Bit definition for ADC_LTR register ********************/
1665 #define ADC_LTR_LT 0x0FFFU
1667 /******************* Bit definition for ADC_SQR1 register *******************/
1668 #define ADC_SQR1_SQ13 0x0000001FU
1669 #define ADC_SQR1_SQ13_0 0x00000001U
1670 #define ADC_SQR1_SQ13_1 0x00000002U
1671 #define ADC_SQR1_SQ13_2 0x00000004U
1672 #define ADC_SQR1_SQ13_3 0x00000008U
1673 #define ADC_SQR1_SQ13_4 0x00000010U
1674 #define ADC_SQR1_SQ14 0x000003E0U
1675 #define ADC_SQR1_SQ14_0 0x00000020U
1676 #define ADC_SQR1_SQ14_1 0x00000040U
1677 #define ADC_SQR1_SQ14_2 0x00000080U
1678 #define ADC_SQR1_SQ14_3 0x00000100U
1679 #define ADC_SQR1_SQ14_4 0x00000200U
1680 #define ADC_SQR1_SQ15 0x00007C00U
1681 #define ADC_SQR1_SQ15_0 0x00000400U
1682 #define ADC_SQR1_SQ15_1 0x00000800U
1683 #define ADC_SQR1_SQ15_2 0x00001000U
1684 #define ADC_SQR1_SQ15_3 0x00002000U
1685 #define ADC_SQR1_SQ15_4 0x00004000U
1686 #define ADC_SQR1_SQ16 0x000F8000U
1687 #define ADC_SQR1_SQ16_0 0x00008000U
1688 #define ADC_SQR1_SQ16_1 0x00010000U
1689 #define ADC_SQR1_SQ16_2 0x00020000U
1690 #define ADC_SQR1_SQ16_3 0x00040000U
1691 #define ADC_SQR1_SQ16_4 0x00080000U
1692 #define ADC_SQR1_L 0x00F00000U
1693 #define ADC_SQR1_L_0 0x00100000U
1694 #define ADC_SQR1_L_1 0x00200000U
1695 #define ADC_SQR1_L_2 0x00400000U
1696 #define ADC_SQR1_L_3 0x00800000U
1698 /******************* Bit definition for ADC_SQR2 register *******************/
1699 #define ADC_SQR2_SQ7 0x0000001FU
1700 #define ADC_SQR2_SQ7_0 0x00000001U
1701 #define ADC_SQR2_SQ7_1 0x00000002U
1702 #define ADC_SQR2_SQ7_2 0x00000004U
1703 #define ADC_SQR2_SQ7_3 0x00000008U
1704 #define ADC_SQR2_SQ7_4 0x00000010U
1705 #define ADC_SQR2_SQ8 0x000003E0U
1706 #define ADC_SQR2_SQ8_0 0x00000020U
1707 #define ADC_SQR2_SQ8_1 0x00000040U
1708 #define ADC_SQR2_SQ8_2 0x00000080U
1709 #define ADC_SQR2_SQ8_3 0x00000100U
1710 #define ADC_SQR2_SQ8_4 0x00000200U
1711 #define ADC_SQR2_SQ9 0x00007C00U
1712 #define ADC_SQR2_SQ9_0 0x00000400U
1713 #define ADC_SQR2_SQ9_1 0x00000800U
1714 #define ADC_SQR2_SQ9_2 0x00001000U
1715 #define ADC_SQR2_SQ9_3 0x00002000U
1716 #define ADC_SQR2_SQ9_4 0x00004000U
1717 #define ADC_SQR2_SQ10 0x000F8000U
1718 #define ADC_SQR2_SQ10_0 0x00008000U
1719 #define ADC_SQR2_SQ10_1 0x00010000U
1720 #define ADC_SQR2_SQ10_2 0x00020000U
1721 #define ADC_SQR2_SQ10_3 0x00040000U
1722 #define ADC_SQR2_SQ10_4 0x00080000U
1723 #define ADC_SQR2_SQ11 0x01F00000U
1724 #define ADC_SQR2_SQ11_0 0x00100000U
1725 #define ADC_SQR2_SQ11_1 0x00200000U
1726 #define ADC_SQR2_SQ11_2 0x00400000U
1727 #define ADC_SQR2_SQ11_3 0x00800000U
1728 #define ADC_SQR2_SQ11_4 0x01000000U
1729 #define ADC_SQR2_SQ12 0x3E000000U
1730 #define ADC_SQR2_SQ12_0 0x02000000U
1731 #define ADC_SQR2_SQ12_1 0x04000000U
1732 #define ADC_SQR2_SQ12_2 0x08000000U
1733 #define ADC_SQR2_SQ12_3 0x10000000U
1734 #define ADC_SQR2_SQ12_4 0x20000000U
1736 /******************* Bit definition for ADC_SQR3 register *******************/
1737 #define ADC_SQR3_SQ1 0x0000001FU
1738 #define ADC_SQR3_SQ1_0 0x00000001U
1739 #define ADC_SQR3_SQ1_1 0x00000002U
1740 #define ADC_SQR3_SQ1_2 0x00000004U
1741 #define ADC_SQR3_SQ1_3 0x00000008U
1742 #define ADC_SQR3_SQ1_4 0x00000010U
1743 #define ADC_SQR3_SQ2 0x000003E0U
1744 #define ADC_SQR3_SQ2_0 0x00000020U
1745 #define ADC_SQR3_SQ2_1 0x00000040U
1746 #define ADC_SQR3_SQ2_2 0x00000080U
1747 #define ADC_SQR3_SQ2_3 0x00000100U
1748 #define ADC_SQR3_SQ2_4 0x00000200U
1749 #define ADC_SQR3_SQ3 0x00007C00U
1750 #define ADC_SQR3_SQ3_0 0x00000400U
1751 #define ADC_SQR3_SQ3_1 0x00000800U
1752 #define ADC_SQR3_SQ3_2 0x00001000U
1753 #define ADC_SQR3_SQ3_3 0x00002000U
1754 #define ADC_SQR3_SQ3_4 0x00004000U
1755 #define ADC_SQR3_SQ4 0x000F8000U
1756 #define ADC_SQR3_SQ4_0 0x00008000U
1757 #define ADC_SQR3_SQ4_1 0x00010000U
1758 #define ADC_SQR3_SQ4_2 0x00020000U
1759 #define ADC_SQR3_SQ4_3 0x00040000U
1760 #define ADC_SQR3_SQ4_4 0x00080000U
1761 #define ADC_SQR3_SQ5 0x01F00000U
1762 #define ADC_SQR3_SQ5_0 0x00100000U
1763 #define ADC_SQR3_SQ5_1 0x00200000U
1764 #define ADC_SQR3_SQ5_2 0x00400000U
1765 #define ADC_SQR3_SQ5_3 0x00800000U
1766 #define ADC_SQR3_SQ5_4 0x01000000U
1767 #define ADC_SQR3_SQ6 0x3E000000U
1768 #define ADC_SQR3_SQ6_0 0x02000000U
1769 #define ADC_SQR3_SQ6_1 0x04000000U
1770 #define ADC_SQR3_SQ6_2 0x08000000U
1771 #define ADC_SQR3_SQ6_3 0x10000000U
1772 #define ADC_SQR3_SQ6_4 0x20000000U
1774 /******************* Bit definition for ADC_JSQR register *******************/
1775 #define ADC_JSQR_JSQ1 0x0000001FU
1776 #define ADC_JSQR_JSQ1_0 0x00000001U
1777 #define ADC_JSQR_JSQ1_1 0x00000002U
1778 #define ADC_JSQR_JSQ1_2 0x00000004U
1779 #define ADC_JSQR_JSQ1_3 0x00000008U
1780 #define ADC_JSQR_JSQ1_4 0x00000010U
1781 #define ADC_JSQR_JSQ2 0x000003E0U
1782 #define ADC_JSQR_JSQ2_0 0x00000020U
1783 #define ADC_JSQR_JSQ2_1 0x00000040U
1784 #define ADC_JSQR_JSQ2_2 0x00000080U
1785 #define ADC_JSQR_JSQ2_3 0x00000100U
1786 #define ADC_JSQR_JSQ2_4 0x00000200U
1787 #define ADC_JSQR_JSQ3 0x00007C00U
1788 #define ADC_JSQR_JSQ3_0 0x00000400U
1789 #define ADC_JSQR_JSQ3_1 0x00000800U
1790 #define ADC_JSQR_JSQ3_2 0x00001000U
1791 #define ADC_JSQR_JSQ3_3 0x00002000U
1792 #define ADC_JSQR_JSQ3_4 0x00004000U
1793 #define ADC_JSQR_JSQ4 0x000F8000U
1794 #define ADC_JSQR_JSQ4_0 0x00008000U
1795 #define ADC_JSQR_JSQ4_1 0x00010000U
1796 #define ADC_JSQR_JSQ4_2 0x00020000U
1797 #define ADC_JSQR_JSQ4_3 0x00040000U
1798 #define ADC_JSQR_JSQ4_4 0x00080000U
1799 #define ADC_JSQR_JL 0x00300000U
1800 #define ADC_JSQR_JL_0 0x00100000U
1801 #define ADC_JSQR_JL_1 0x00200000U
1803 /******************* Bit definition for ADC_JDR1 register *******************/
1804 #define ADC_JDR1_JDATA ((uint16_t)0xFFFFU)
1806 /******************* Bit definition for ADC_JDR2 register *******************/
1807 #define ADC_JDR2_JDATA ((uint16_t)0xFFFFU)
1809 /******************* Bit definition for ADC_JDR3 register *******************/
1810 #define ADC_JDR3_JDATA ((uint16_t)0xFFFFU)
1812 /******************* Bit definition for ADC_JDR4 register *******************/
1813 #define ADC_JDR4_JDATA ((uint16_t)0xFFFFU)
1815 /******************** Bit definition for ADC_DR register ********************/
1816 #define ADC_DR_DATA 0x0000FFFFU
1817 #define ADC_DR_ADC2DATA 0xFFFF0000U
1819 /******************* Bit definition for ADC_CSR register ********************/
1820 #define ADC_CSR_AWD1 0x00000001U
1821 #define ADC_CSR_EOC1 0x00000002U
1822 #define ADC_CSR_JEOC1 0x00000004U
1823 #define ADC_CSR_JSTRT1 0x00000008U
1824 #define ADC_CSR_STRT1 0x00000010U
1825 #define ADC_CSR_OVR1 0x00000020U
1826 #define ADC_CSR_AWD2 0x00000100U
1827 #define ADC_CSR_EOC2 0x00000200U
1828 #define ADC_CSR_JEOC2 0x00000400U
1829 #define ADC_CSR_JSTRT2 0x00000800U
1830 #define ADC_CSR_STRT2 0x00001000U
1831 #define ADC_CSR_OVR2 0x00002000U
1832 #define ADC_CSR_AWD3 0x00010000U
1833 #define ADC_CSR_EOC3 0x00020000U
1834 #define ADC_CSR_JEOC3 0x00040000U
1835 #define ADC_CSR_JSTRT3 0x00080000U
1836 #define ADC_CSR_STRT3 0x00100000U
1837 #define ADC_CSR_OVR3 0x00200000U
1839 /* Legacy defines */
1840 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1841 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
1842 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
1843 
1844 
1845 /******************* Bit definition for ADC_CCR register ********************/
1846 #define ADC_CCR_MULTI 0x0000001FU
1847 #define ADC_CCR_MULTI_0 0x00000001U
1848 #define ADC_CCR_MULTI_1 0x00000002U
1849 #define ADC_CCR_MULTI_2 0x00000004U
1850 #define ADC_CCR_MULTI_3 0x00000008U
1851 #define ADC_CCR_MULTI_4 0x00000010U
1852 #define ADC_CCR_DELAY 0x00000F00U
1853 #define ADC_CCR_DELAY_0 0x00000100U
1854 #define ADC_CCR_DELAY_1 0x00000200U
1855 #define ADC_CCR_DELAY_2 0x00000400U
1856 #define ADC_CCR_DELAY_3 0x00000800U
1857 #define ADC_CCR_DDS 0x00002000U
1858 #define ADC_CCR_DMA 0x0000C000U
1859 #define ADC_CCR_DMA_0 0x00004000U
1860 #define ADC_CCR_DMA_1 0x00008000U
1861 #define ADC_CCR_ADCPRE 0x00030000U
1862 #define ADC_CCR_ADCPRE_0 0x00010000U
1863 #define ADC_CCR_ADCPRE_1 0x00020000U
1864 #define ADC_CCR_VBATE 0x00400000U
1865 #define ADC_CCR_TSVREFE 0x00800000U
1867 /******************* Bit definition for ADC_CDR register ********************/
1868 #define ADC_CDR_DATA1 0x0000FFFFU
1869 #define ADC_CDR_DATA2 0xFFFF0000U
1871 /******************************************************************************/
1872 /* */
1873 /* Controller Area Network */
1874 /* */
1875 /******************************************************************************/
1877 /******************* Bit definition for CAN_MCR register ********************/
1878 #define CAN_MCR_INRQ 0x00000001U
1879 #define CAN_MCR_SLEEP 0x00000002U
1880 #define CAN_MCR_TXFP 0x00000004U
1881 #define CAN_MCR_RFLM 0x00000008U
1882 #define CAN_MCR_NART 0x00000010U
1883 #define CAN_MCR_AWUM 0x00000020U
1884 #define CAN_MCR_ABOM 0x00000040U
1885 #define CAN_MCR_TTCM 0x00000080U
1886 #define CAN_MCR_RESET 0x00008000U
1888 /******************* Bit definition for CAN_MSR register ********************/
1889 #define CAN_MSR_INAK 0x00000001U
1890 #define CAN_MSR_SLAK 0x00000002U
1891 #define CAN_MSR_ERRI 0x00000004U
1892 #define CAN_MSR_WKUI 0x00000008U
1893 #define CAN_MSR_SLAKI 0x00000010U
1894 #define CAN_MSR_TXM 0x00000100U
1895 #define CAN_MSR_RXM 0x00000200U
1896 #define CAN_MSR_SAMP 0x00000400U
1897 #define CAN_MSR_RX 0x00000800U
1899 /******************* Bit definition for CAN_TSR register ********************/
1900 #define CAN_TSR_RQCP0 0x00000001U
1901 #define CAN_TSR_TXOK0 0x00000002U
1902 #define CAN_TSR_ALST0 0x00000004U
1903 #define CAN_TSR_TERR0 0x00000008U
1904 #define CAN_TSR_ABRQ0 0x00000080U
1905 #define CAN_TSR_RQCP1 0x00000100U
1906 #define CAN_TSR_TXOK1 0x00000200U
1907 #define CAN_TSR_ALST1 0x00000400U
1908 #define CAN_TSR_TERR1 0x00000800U
1909 #define CAN_TSR_ABRQ1 0x00008000U
1910 #define CAN_TSR_RQCP2 0x00010000U
1911 #define CAN_TSR_TXOK2 0x00020000U
1912 #define CAN_TSR_ALST2 0x00040000U
1913 #define CAN_TSR_TERR2 0x00080000U
1914 #define CAN_TSR_ABRQ2 0x00800000U
1915 #define CAN_TSR_CODE 0x03000000U
1917 #define CAN_TSR_TME 0x1C000000U
1918 #define CAN_TSR_TME0 0x04000000U
1919 #define CAN_TSR_TME1 0x08000000U
1920 #define CAN_TSR_TME2 0x10000000U
1922 #define CAN_TSR_LOW 0xE0000000U
1923 #define CAN_TSR_LOW0 0x20000000U
1924 #define CAN_TSR_LOW1 0x40000000U
1925 #define CAN_TSR_LOW2 0x80000000U
1927 /******************* Bit definition for CAN_RF0R register *******************/
1928 #define CAN_RF0R_FMP0 0x00000003U
1929 #define CAN_RF0R_FULL0 0x00000008U
1930 #define CAN_RF0R_FOVR0 0x00000010U
1931 #define CAN_RF0R_RFOM0 0x00000020U
1933 /******************* Bit definition for CAN_RF1R register *******************/
1934 #define CAN_RF1R_FMP1 0x00000003U
1935 #define CAN_RF1R_FULL1 0x00000008U
1936 #define CAN_RF1R_FOVR1 0x00000010U
1937 #define CAN_RF1R_RFOM1 0x00000020U
1939 /******************** Bit definition for CAN_IER register *******************/
1940 #define CAN_IER_TMEIE 0x00000001U
1941 #define CAN_IER_FMPIE0 0x00000002U
1942 #define CAN_IER_FFIE0 0x00000004U
1943 #define CAN_IER_FOVIE0 0x00000008U
1944 #define CAN_IER_FMPIE1 0x00000010U
1945 #define CAN_IER_FFIE1 0x00000020U
1946 #define CAN_IER_FOVIE1 0x00000040U
1947 #define CAN_IER_EWGIE 0x00000100U
1948 #define CAN_IER_EPVIE 0x00000200U
1949 #define CAN_IER_BOFIE 0x00000400U
1950 #define CAN_IER_LECIE 0x00000800U
1951 #define CAN_IER_ERRIE 0x00008000U
1952 #define CAN_IER_WKUIE 0x00010000U
1953 #define CAN_IER_SLKIE 0x00020000U
1955 /******************** Bit definition for CAN_ESR register *******************/
1956 #define CAN_ESR_EWGF 0x00000001U
1957 #define CAN_ESR_EPVF 0x00000002U
1958 #define CAN_ESR_BOFF 0x00000004U
1960 #define CAN_ESR_LEC 0x00000070U
1961 #define CAN_ESR_LEC_0 0x00000010U
1962 #define CAN_ESR_LEC_1 0x00000020U
1963 #define CAN_ESR_LEC_2 0x00000040U
1965 #define CAN_ESR_TEC 0x00FF0000U
1966 #define CAN_ESR_REC 0xFF000000U
1968 /******************* Bit definition for CAN_BTR register ********************/
1969 #define CAN_BTR_BRP 0x000003FFU
1970 #define CAN_BTR_TS1 0x000F0000U
1971 #define CAN_BTR_TS1_0 0x00010000U
1972 #define CAN_BTR_TS1_1 0x00020000U
1973 #define CAN_BTR_TS1_2 0x00040000U
1974 #define CAN_BTR_TS1_3 0x00080000U
1975 #define CAN_BTR_TS2 0x00700000U
1976 #define CAN_BTR_TS2_0 0x00100000U
1977 #define CAN_BTR_TS2_1 0x00200000U
1978 #define CAN_BTR_TS2_2 0x00400000U
1979 #define CAN_BTR_SJW 0x03000000U
1980 #define CAN_BTR_SJW_0 0x01000000U
1981 #define CAN_BTR_SJW_1 0x02000000U
1982 #define CAN_BTR_LBKM 0x40000000U
1983 #define CAN_BTR_SILM 0x80000000U
1986 /****************** Bit definition for CAN_TI0R register ********************/
1987 #define CAN_TI0R_TXRQ 0x00000001U
1988 #define CAN_TI0R_RTR 0x00000002U
1989 #define CAN_TI0R_IDE 0x00000004U
1990 #define CAN_TI0R_EXID 0x001FFFF8U
1991 #define CAN_TI0R_STID 0xFFE00000U
1993 /****************** Bit definition for CAN_TDT0R register *******************/
1994 #define CAN_TDT0R_DLC 0x0000000FU
1995 #define CAN_TDT0R_TGT 0x00000100U
1996 #define CAN_TDT0R_TIME 0xFFFF0000U
1998 /****************** Bit definition for CAN_TDL0R register *******************/
1999 #define CAN_TDL0R_DATA0 0x000000FFU
2000 #define CAN_TDL0R_DATA1 0x0000FF00U
2001 #define CAN_TDL0R_DATA2 0x00FF0000U
2002 #define CAN_TDL0R_DATA3 0xFF000000U
2004 /****************** Bit definition for CAN_TDH0R register *******************/
2005 #define CAN_TDH0R_DATA4 0x000000FFU
2006 #define CAN_TDH0R_DATA5 0x0000FF00U
2007 #define CAN_TDH0R_DATA6 0x00FF0000U
2008 #define CAN_TDH0R_DATA7 0xFF000000U
2010 /******************* Bit definition for CAN_TI1R register *******************/
2011 #define CAN_TI1R_TXRQ 0x00000001U
2012 #define CAN_TI1R_RTR 0x00000002U
2013 #define CAN_TI1R_IDE 0x00000004U
2014 #define CAN_TI1R_EXID 0x001FFFF8U
2015 #define CAN_TI1R_STID 0xFFE00000U
2017 /******************* Bit definition for CAN_TDT1R register ******************/
2018 #define CAN_TDT1R_DLC 0x0000000FU
2019 #define CAN_TDT1R_TGT 0x00000100U
2020 #define CAN_TDT1R_TIME 0xFFFF0000U
2022 /******************* Bit definition for CAN_TDL1R register ******************/
2023 #define CAN_TDL1R_DATA0 0x000000FFU
2024 #define CAN_TDL1R_DATA1 0x0000FF00U
2025 #define CAN_TDL1R_DATA2 0x00FF0000U
2026 #define CAN_TDL1R_DATA3 0xFF000000U
2028 /******************* Bit definition for CAN_TDH1R register ******************/
2029 #define CAN_TDH1R_DATA4 0x000000FFU
2030 #define CAN_TDH1R_DATA5 0x0000FF00U
2031 #define CAN_TDH1R_DATA6 0x00FF0000U
2032 #define CAN_TDH1R_DATA7 0xFF000000U
2034 /******************* Bit definition for CAN_TI2R register *******************/
2035 #define CAN_TI2R_TXRQ 0x00000001U
2036 #define CAN_TI2R_RTR 0x00000002U
2037 #define CAN_TI2R_IDE 0x00000004U
2038 #define CAN_TI2R_EXID 0x001FFFF8U
2039 #define CAN_TI2R_STID 0xFFE00000U
2041 /******************* Bit definition for CAN_TDT2R register ******************/
2042 #define CAN_TDT2R_DLC 0x0000000FU
2043 #define CAN_TDT2R_TGT 0x00000100U
2044 #define CAN_TDT2R_TIME 0xFFFF0000U
2046 /******************* Bit definition for CAN_TDL2R register ******************/
2047 #define CAN_TDL2R_DATA0 0x000000FFU
2048 #define CAN_TDL2R_DATA1 0x0000FF00U
2049 #define CAN_TDL2R_DATA2 0x00FF0000U
2050 #define CAN_TDL2R_DATA3 0xFF000000U
2052 /******************* Bit definition for CAN_TDH2R register ******************/
2053 #define CAN_TDH2R_DATA4 0x000000FFU
2054 #define CAN_TDH2R_DATA5 0x0000FF00U
2055 #define CAN_TDH2R_DATA6 0x00FF0000U
2056 #define CAN_TDH2R_DATA7 0xFF000000U
2058 /******************* Bit definition for CAN_RI0R register *******************/
2059 #define CAN_RI0R_RTR 0x00000002U
2060 #define CAN_RI0R_IDE 0x00000004U
2061 #define CAN_RI0R_EXID 0x001FFFF8U
2062 #define CAN_RI0R_STID 0xFFE00000U
2064 /******************* Bit definition for CAN_RDT0R register ******************/
2065 #define CAN_RDT0R_DLC 0x0000000FU
2066 #define CAN_RDT0R_FMI 0x0000FF00U
2067 #define CAN_RDT0R_TIME 0xFFFF0000U
2069 /******************* Bit definition for CAN_RDL0R register ******************/
2070 #define CAN_RDL0R_DATA0 0x000000FFU
2071 #define CAN_RDL0R_DATA1 0x0000FF00U
2072 #define CAN_RDL0R_DATA2 0x00FF0000U
2073 #define CAN_RDL0R_DATA3 0xFF000000U
2075 /******************* Bit definition for CAN_RDH0R register ******************/
2076 #define CAN_RDH0R_DATA4 0x000000FFU
2077 #define CAN_RDH0R_DATA5 0x0000FF00U
2078 #define CAN_RDH0R_DATA6 0x00FF0000U
2079 #define CAN_RDH0R_DATA7 0xFF000000U
2081 /******************* Bit definition for CAN_RI1R register *******************/
2082 #define CAN_RI1R_RTR 0x00000002U
2083 #define CAN_RI1R_IDE 0x00000004U
2084 #define CAN_RI1R_EXID 0x001FFFF8U
2085 #define CAN_RI1R_STID 0xFFE00000U
2087 /******************* Bit definition for CAN_RDT1R register ******************/
2088 #define CAN_RDT1R_DLC 0x0000000FU
2089 #define CAN_RDT1R_FMI 0x0000FF00U
2090 #define CAN_RDT1R_TIME 0xFFFF0000U
2092 /******************* Bit definition for CAN_RDL1R register ******************/
2093 #define CAN_RDL1R_DATA0 0x000000FFU
2094 #define CAN_RDL1R_DATA1 0x0000FF00U
2095 #define CAN_RDL1R_DATA2 0x00FF0000U
2096 #define CAN_RDL1R_DATA3 0xFF000000U
2098 /******************* Bit definition for CAN_RDH1R register ******************/
2099 #define CAN_RDH1R_DATA4 0x000000FFU
2100 #define CAN_RDH1R_DATA5 0x0000FF00U
2101 #define CAN_RDH1R_DATA6 0x00FF0000U
2102 #define CAN_RDH1R_DATA7 0xFF000000U
2105 /******************* Bit definition for CAN_FMR register ********************/
2106 #define CAN_FMR_FINIT ((uint8_t)0x01U)
2107 #define CAN_FMR_CAN2SB 0x00003F00U
2109 /******************* Bit definition for CAN_FM1R register *******************/
2110 #define CAN_FM1R_FBM 0x3FFFU
2111 #define CAN_FM1R_FBM0 0x0001U
2112 #define CAN_FM1R_FBM1 0x0002U
2113 #define CAN_FM1R_FBM2 0x0004U
2114 #define CAN_FM1R_FBM3 0x0008U
2115 #define CAN_FM1R_FBM4 0x0010U
2116 #define CAN_FM1R_FBM5 0x0020U
2117 #define CAN_FM1R_FBM6 0x0040U
2118 #define CAN_FM1R_FBM7 0x0080U
2119 #define CAN_FM1R_FBM8 0x0100U
2120 #define CAN_FM1R_FBM9 0x0200U
2121 #define CAN_FM1R_FBM10 0x0400U
2122 #define CAN_FM1R_FBM11 0x0800U
2123 #define CAN_FM1R_FBM12 0x1000U
2124 #define CAN_FM1R_FBM13 0x2000U
2126 /******************* Bit definition for CAN_FS1R register *******************/
2127 #define CAN_FS1R_FSC 0x00003FFFU
2128 #define CAN_FS1R_FSC0 0x00000001U
2129 #define CAN_FS1R_FSC1 0x00000002U
2130 #define CAN_FS1R_FSC2 0x00000004U
2131 #define CAN_FS1R_FSC3 0x00000008U
2132 #define CAN_FS1R_FSC4 0x00000010U
2133 #define CAN_FS1R_FSC5 0x00000020U
2134 #define CAN_FS1R_FSC6 0x00000040U
2135 #define CAN_FS1R_FSC7 0x00000080U
2136 #define CAN_FS1R_FSC8 0x00000100U
2137 #define CAN_FS1R_FSC9 0x00000200U
2138 #define CAN_FS1R_FSC10 0x00000400U
2139 #define CAN_FS1R_FSC11 0x00000800U
2140 #define CAN_FS1R_FSC12 0x00001000U
2141 #define CAN_FS1R_FSC13 0x00002000U
2143 /****************** Bit definition for CAN_FFA1R register *******************/
2144 #define CAN_FFA1R_FFA 0x00003FFFU
2145 #define CAN_FFA1R_FFA0 0x00000001U
2146 #define CAN_FFA1R_FFA1 0x00000002U
2147 #define CAN_FFA1R_FFA2 0x00000004U
2148 #define CAN_FFA1R_FFA3 0x00000008U
2149 #define CAN_FFA1R_FFA4 0x00000010U
2150 #define CAN_FFA1R_FFA5 0x00000020U
2151 #define CAN_FFA1R_FFA6 0x00000040U
2152 #define CAN_FFA1R_FFA7 0x00000080U
2153 #define CAN_FFA1R_FFA8 0x00000100U
2154 #define CAN_FFA1R_FFA9 0x00000200U
2155 #define CAN_FFA1R_FFA10 0x00000400U
2156 #define CAN_FFA1R_FFA11 0x00000800U
2157 #define CAN_FFA1R_FFA12 0x00001000U
2158 #define CAN_FFA1R_FFA13 0x00002000U
2160 /******************* Bit definition for CAN_FA1R register *******************/
2161 #define CAN_FA1R_FACT 0x00003FFFU
2162 #define CAN_FA1R_FACT0 0x00000001U
2163 #define CAN_FA1R_FACT1 0x00000002U
2164 #define CAN_FA1R_FACT2 0x00000004U
2165 #define CAN_FA1R_FACT3 0x00000008U
2166 #define CAN_FA1R_FACT4 0x00000010U
2167 #define CAN_FA1R_FACT5 0x00000020U
2168 #define CAN_FA1R_FACT6 0x00000040U
2169 #define CAN_FA1R_FACT7 0x00000080U
2170 #define CAN_FA1R_FACT8 0x00000100U
2171 #define CAN_FA1R_FACT9 0x00000200U
2172 #define CAN_FA1R_FACT10 0x00000400U
2173 #define CAN_FA1R_FACT11 0x00000800U
2174 #define CAN_FA1R_FACT12 0x00001000U
2175 #define CAN_FA1R_FACT13 0x00002000U
2177 /******************* Bit definition for CAN_F0R1 register *******************/
2178 #define CAN_F0R1_FB0 0x00000001U
2179 #define CAN_F0R1_FB1 0x00000002U
2180 #define CAN_F0R1_FB2 0x00000004U
2181 #define CAN_F0R1_FB3 0x00000008U
2182 #define CAN_F0R1_FB4 0x00000010U
2183 #define CAN_F0R1_FB5 0x00000020U
2184 #define CAN_F0R1_FB6 0x00000040U
2185 #define CAN_F0R1_FB7 0x00000080U
2186 #define CAN_F0R1_FB8 0x00000100U
2187 #define CAN_F0R1_FB9 0x00000200U
2188 #define CAN_F0R1_FB10 0x00000400U
2189 #define CAN_F0R1_FB11 0x00000800U
2190 #define CAN_F0R1_FB12 0x00001000U
2191 #define CAN_F0R1_FB13 0x00002000U
2192 #define CAN_F0R1_FB14 0x00004000U
2193 #define CAN_F0R1_FB15 0x00008000U
2194 #define CAN_F0R1_FB16 0x00010000U
2195 #define CAN_F0R1_FB17 0x00020000U
2196 #define CAN_F0R1_FB18 0x00040000U
2197 #define CAN_F0R1_FB19 0x00080000U
2198 #define CAN_F0R1_FB20 0x00100000U
2199 #define CAN_F0R1_FB21 0x00200000U
2200 #define CAN_F0R1_FB22 0x00400000U
2201 #define CAN_F0R1_FB23 0x00800000U
2202 #define CAN_F0R1_FB24 0x01000000U
2203 #define CAN_F0R1_FB25 0x02000000U
2204 #define CAN_F0R1_FB26 0x04000000U
2205 #define CAN_F0R1_FB27 0x08000000U
2206 #define CAN_F0R1_FB28 0x10000000U
2207 #define CAN_F0R1_FB29 0x20000000U
2208 #define CAN_F0R1_FB30 0x40000000U
2209 #define CAN_F0R1_FB31 0x80000000U
2211 /******************* Bit definition for CAN_F1R1 register *******************/
2212 #define CAN_F1R1_FB0 0x00000001U
2213 #define CAN_F1R1_FB1 0x00000002U
2214 #define CAN_F1R1_FB2 0x00000004U
2215 #define CAN_F1R1_FB3 0x00000008U
2216 #define CAN_F1R1_FB4 0x00000010U
2217 #define CAN_F1R1_FB5 0x00000020U
2218 #define CAN_F1R1_FB6 0x00000040U
2219 #define CAN_F1R1_FB7 0x00000080U
2220 #define CAN_F1R1_FB8 0x00000100U
2221 #define CAN_F1R1_FB9 0x00000200U
2222 #define CAN_F1R1_FB10 0x00000400U
2223 #define CAN_F1R1_FB11 0x00000800U
2224 #define CAN_F1R1_FB12 0x00001000U
2225 #define CAN_F1R1_FB13 0x00002000U
2226 #define CAN_F1R1_FB14 0x00004000U
2227 #define CAN_F1R1_FB15 0x00008000U
2228 #define CAN_F1R1_FB16 0x00010000U
2229 #define CAN_F1R1_FB17 0x00020000U
2230 #define CAN_F1R1_FB18 0x00040000U
2231 #define CAN_F1R1_FB19 0x00080000U
2232 #define CAN_F1R1_FB20 0x00100000U
2233 #define CAN_F1R1_FB21 0x00200000U
2234 #define CAN_F1R1_FB22 0x00400000U
2235 #define CAN_F1R1_FB23 0x00800000U
2236 #define CAN_F1R1_FB24 0x01000000U
2237 #define CAN_F1R1_FB25 0x02000000U
2238 #define CAN_F1R1_FB26 0x04000000U
2239 #define CAN_F1R1_FB27 0x08000000U
2240 #define CAN_F1R1_FB28 0x10000000U
2241 #define CAN_F1R1_FB29 0x20000000U
2242 #define CAN_F1R1_FB30 0x40000000U
2243 #define CAN_F1R1_FB31 0x80000000U
2245 /******************* Bit definition for CAN_F2R1 register *******************/
2246 #define CAN_F2R1_FB0 0x00000001U
2247 #define CAN_F2R1_FB1 0x00000002U
2248 #define CAN_F2R1_FB2 0x00000004U
2249 #define CAN_F2R1_FB3 0x00000008U
2250 #define CAN_F2R1_FB4 0x00000010U
2251 #define CAN_F2R1_FB5 0x00000020U
2252 #define CAN_F2R1_FB6 0x00000040U
2253 #define CAN_F2R1_FB7 0x00000080U
2254 #define CAN_F2R1_FB8 0x00000100U
2255 #define CAN_F2R1_FB9 0x00000200U
2256 #define CAN_F2R1_FB10 0x00000400U
2257 #define CAN_F2R1_FB11 0x00000800U
2258 #define CAN_F2R1_FB12 0x00001000U
2259 #define CAN_F2R1_FB13 0x00002000U
2260 #define CAN_F2R1_FB14 0x00004000U
2261 #define CAN_F2R1_FB15 0x00008000U
2262 #define CAN_F2R1_FB16 0x00010000U
2263 #define CAN_F2R1_FB17 0x00020000U
2264 #define CAN_F2R1_FB18 0x00040000U
2265 #define CAN_F2R1_FB19 0x00080000U
2266 #define CAN_F2R1_FB20 0x00100000U
2267 #define CAN_F2R1_FB21 0x00200000U
2268 #define CAN_F2R1_FB22 0x00400000U
2269 #define CAN_F2R1_FB23 0x00800000U
2270 #define CAN_F2R1_FB24 0x01000000U
2271 #define CAN_F2R1_FB25 0x02000000U
2272 #define CAN_F2R1_FB26 0x04000000U
2273 #define CAN_F2R1_FB27 0x08000000U
2274 #define CAN_F2R1_FB28 0x10000000U
2275 #define CAN_F2R1_FB29 0x20000000U
2276 #define CAN_F2R1_FB30 0x40000000U
2277 #define CAN_F2R1_FB31 0x80000000U
2279 /******************* Bit definition for CAN_F3R1 register *******************/
2280 #define CAN_F3R1_FB0 0x00000001U
2281 #define CAN_F3R1_FB1 0x00000002U
2282 #define CAN_F3R1_FB2 0x00000004U
2283 #define CAN_F3R1_FB3 0x00000008U
2284 #define CAN_F3R1_FB4 0x00000010U
2285 #define CAN_F3R1_FB5 0x00000020U
2286 #define CAN_F3R1_FB6 0x00000040U
2287 #define CAN_F3R1_FB7 0x00000080U
2288 #define CAN_F3R1_FB8 0x00000100U
2289 #define CAN_F3R1_FB9 0x00000200U
2290 #define CAN_F3R1_FB10 0x00000400U
2291 #define CAN_F3R1_FB11 0x00000800U
2292 #define CAN_F3R1_FB12 0x00001000U
2293 #define CAN_F3R1_FB13 0x00002000U
2294 #define CAN_F3R1_FB14 0x00004000U
2295 #define CAN_F3R1_FB15 0x00008000U
2296 #define CAN_F3R1_FB16 0x00010000U
2297 #define CAN_F3R1_FB17 0x00020000U
2298 #define CAN_F3R1_FB18 0x00040000U
2299 #define CAN_F3R1_FB19 0x00080000U
2300 #define CAN_F3R1_FB20 0x00100000U
2301 #define CAN_F3R1_FB21 0x00200000U
2302 #define CAN_F3R1_FB22 0x00400000U
2303 #define CAN_F3R1_FB23 0x00800000U
2304 #define CAN_F3R1_FB24 0x01000000U
2305 #define CAN_F3R1_FB25 0x02000000U
2306 #define CAN_F3R1_FB26 0x04000000U
2307 #define CAN_F3R1_FB27 0x08000000U
2308 #define CAN_F3R1_FB28 0x10000000U
2309 #define CAN_F3R1_FB29 0x20000000U
2310 #define CAN_F3R1_FB30 0x40000000U
2311 #define CAN_F3R1_FB31 0x80000000U
2313 /******************* Bit definition for CAN_F4R1 register *******************/
2314 #define CAN_F4R1_FB0 0x00000001U
2315 #define CAN_F4R1_FB1 0x00000002U
2316 #define CAN_F4R1_FB2 0x00000004U
2317 #define CAN_F4R1_FB3 0x00000008U
2318 #define CAN_F4R1_FB4 0x00000010U
2319 #define CAN_F4R1_FB5 0x00000020U
2320 #define CAN_F4R1_FB6 0x00000040U
2321 #define CAN_F4R1_FB7 0x00000080U
2322 #define CAN_F4R1_FB8 0x00000100U
2323 #define CAN_F4R1_FB9 0x00000200U
2324 #define CAN_F4R1_FB10 0x00000400U
2325 #define CAN_F4R1_FB11 0x00000800U
2326 #define CAN_F4R1_FB12 0x00001000U
2327 #define CAN_F4R1_FB13 0x00002000U
2328 #define CAN_F4R1_FB14 0x00004000U
2329 #define CAN_F4R1_FB15 0x00008000U
2330 #define CAN_F4R1_FB16 0x00010000U
2331 #define CAN_F4R1_FB17 0x00020000U
2332 #define CAN_F4R1_FB18 0x00040000U
2333 #define CAN_F4R1_FB19 0x00080000U
2334 #define CAN_F4R1_FB20 0x00100000U
2335 #define CAN_F4R1_FB21 0x00200000U
2336 #define CAN_F4R1_FB22 0x00400000U
2337 #define CAN_F4R1_FB23 0x00800000U
2338 #define CAN_F4R1_FB24 0x01000000U
2339 #define CAN_F4R1_FB25 0x02000000U
2340 #define CAN_F4R1_FB26 0x04000000U
2341 #define CAN_F4R1_FB27 0x08000000U
2342 #define CAN_F4R1_FB28 0x10000000U
2343 #define CAN_F4R1_FB29 0x20000000U
2344 #define CAN_F4R1_FB30 0x40000000U
2345 #define CAN_F4R1_FB31 0x80000000U
2347 /******************* Bit definition for CAN_F5R1 register *******************/
2348 #define CAN_F5R1_FB0 0x00000001U
2349 #define CAN_F5R1_FB1 0x00000002U
2350 #define CAN_F5R1_FB2 0x00000004U
2351 #define CAN_F5R1_FB3 0x00000008U
2352 #define CAN_F5R1_FB4 0x00000010U
2353 #define CAN_F5R1_FB5 0x00000020U
2354 #define CAN_F5R1_FB6 0x00000040U
2355 #define CAN_F5R1_FB7 0x00000080U
2356 #define CAN_F5R1_FB8 0x00000100U
2357 #define CAN_F5R1_FB9 0x00000200U
2358 #define CAN_F5R1_FB10 0x00000400U
2359 #define CAN_F5R1_FB11 0x00000800U
2360 #define CAN_F5R1_FB12 0x00001000U
2361 #define CAN_F5R1_FB13 0x00002000U
2362 #define CAN_F5R1_FB14 0x00004000U
2363 #define CAN_F5R1_FB15 0x00008000U
2364 #define CAN_F5R1_FB16 0x00010000U
2365 #define CAN_F5R1_FB17 0x00020000U
2366 #define CAN_F5R1_FB18 0x00040000U
2367 #define CAN_F5R1_FB19 0x00080000U
2368 #define CAN_F5R1_FB20 0x00100000U
2369 #define CAN_F5R1_FB21 0x00200000U
2370 #define CAN_F5R1_FB22 0x00400000U
2371 #define CAN_F5R1_FB23 0x00800000U
2372 #define CAN_F5R1_FB24 0x01000000U
2373 #define CAN_F5R1_FB25 0x02000000U
2374 #define CAN_F5R1_FB26 0x04000000U
2375 #define CAN_F5R1_FB27 0x08000000U
2376 #define CAN_F5R1_FB28 0x10000000U
2377 #define CAN_F5R1_FB29 0x20000000U
2378 #define CAN_F5R1_FB30 0x40000000U
2379 #define CAN_F5R1_FB31 0x80000000U
2381 /******************* Bit definition for CAN_F6R1 register *******************/
2382 #define CAN_F6R1_FB0 0x00000001U
2383 #define CAN_F6R1_FB1 0x00000002U
2384 #define CAN_F6R1_FB2 0x00000004U
2385 #define CAN_F6R1_FB3 0x00000008U
2386 #define CAN_F6R1_FB4 0x00000010U
2387 #define CAN_F6R1_FB5 0x00000020U
2388 #define CAN_F6R1_FB6 0x00000040U
2389 #define CAN_F6R1_FB7 0x00000080U
2390 #define CAN_F6R1_FB8 0x00000100U
2391 #define CAN_F6R1_FB9 0x00000200U
2392 #define CAN_F6R1_FB10 0x00000400U
2393 #define CAN_F6R1_FB11 0x00000800U
2394 #define CAN_F6R1_FB12 0x00001000U
2395 #define CAN_F6R1_FB13 0x00002000U
2396 #define CAN_F6R1_FB14 0x00004000U
2397 #define CAN_F6R1_FB15 0x00008000U
2398 #define CAN_F6R1_FB16 0x00010000U
2399 #define CAN_F6R1_FB17 0x00020000U
2400 #define CAN_F6R1_FB18 0x00040000U
2401 #define CAN_F6R1_FB19 0x00080000U
2402 #define CAN_F6R1_FB20 0x00100000U
2403 #define CAN_F6R1_FB21 0x00200000U
2404 #define CAN_F6R1_FB22 0x00400000U
2405 #define CAN_F6R1_FB23 0x00800000U
2406 #define CAN_F6R1_FB24 0x01000000U
2407 #define CAN_F6R1_FB25 0x02000000U
2408 #define CAN_F6R1_FB26 0x04000000U
2409 #define CAN_F6R1_FB27 0x08000000U
2410 #define CAN_F6R1_FB28 0x10000000U
2411 #define CAN_F6R1_FB29 0x20000000U
2412 #define CAN_F6R1_FB30 0x40000000U
2413 #define CAN_F6R1_FB31 0x80000000U
2415 /******************* Bit definition for CAN_F7R1 register *******************/
2416 #define CAN_F7R1_FB0 0x00000001U
2417 #define CAN_F7R1_FB1 0x00000002U
2418 #define CAN_F7R1_FB2 0x00000004U
2419 #define CAN_F7R1_FB3 0x00000008U
2420 #define CAN_F7R1_FB4 0x00000010U
2421 #define CAN_F7R1_FB5 0x00000020U
2422 #define CAN_F7R1_FB6 0x00000040U
2423 #define CAN_F7R1_FB7 0x00000080U
2424 #define CAN_F7R1_FB8 0x00000100U
2425 #define CAN_F7R1_FB9 0x00000200U
2426 #define CAN_F7R1_FB10 0x00000400U
2427 #define CAN_F7R1_FB11 0x00000800U
2428 #define CAN_F7R1_FB12 0x00001000U
2429 #define CAN_F7R1_FB13 0x00002000U
2430 #define CAN_F7R1_FB14 0x00004000U
2431 #define CAN_F7R1_FB15 0x00008000U
2432 #define CAN_F7R1_FB16 0x00010000U
2433 #define CAN_F7R1_FB17 0x00020000U
2434 #define CAN_F7R1_FB18 0x00040000U
2435 #define CAN_F7R1_FB19 0x00080000U
2436 #define CAN_F7R1_FB20 0x00100000U
2437 #define CAN_F7R1_FB21 0x00200000U
2438 #define CAN_F7R1_FB22 0x00400000U
2439 #define CAN_F7R1_FB23 0x00800000U
2440 #define CAN_F7R1_FB24 0x01000000U
2441 #define CAN_F7R1_FB25 0x02000000U
2442 #define CAN_F7R1_FB26 0x04000000U
2443 #define CAN_F7R1_FB27 0x08000000U
2444 #define CAN_F7R1_FB28 0x10000000U
2445 #define CAN_F7R1_FB29 0x20000000U
2446 #define CAN_F7R1_FB30 0x40000000U
2447 #define CAN_F7R1_FB31 0x80000000U
2449 /******************* Bit definition for CAN_F8R1 register *******************/
2450 #define CAN_F8R1_FB0 0x00000001U
2451 #define CAN_F8R1_FB1 0x00000002U
2452 #define CAN_F8R1_FB2 0x00000004U
2453 #define CAN_F8R1_FB3 0x00000008U
2454 #define CAN_F8R1_FB4 0x00000010U
2455 #define CAN_F8R1_FB5 0x00000020U
2456 #define CAN_F8R1_FB6 0x00000040U
2457 #define CAN_F8R1_FB7 0x00000080U
2458 #define CAN_F8R1_FB8 0x00000100U
2459 #define CAN_F8R1_FB9 0x00000200U
2460 #define CAN_F8R1_FB10 0x00000400U
2461 #define CAN_F8R1_FB11 0x00000800U
2462 #define CAN_F8R1_FB12 0x00001000U
2463 #define CAN_F8R1_FB13 0x00002000U
2464 #define CAN_F8R1_FB14 0x00004000U
2465 #define CAN_F8R1_FB15 0x00008000U
2466 #define CAN_F8R1_FB16 0x00010000U
2467 #define CAN_F8R1_FB17 0x00020000U
2468 #define CAN_F8R1_FB18 0x00040000U
2469 #define CAN_F8R1_FB19 0x00080000U
2470 #define CAN_F8R1_FB20 0x00100000U
2471 #define CAN_F8R1_FB21 0x00200000U
2472 #define CAN_F8R1_FB22 0x00400000U
2473 #define CAN_F8R1_FB23 0x00800000U
2474 #define CAN_F8R1_FB24 0x01000000U
2475 #define CAN_F8R1_FB25 0x02000000U
2476 #define CAN_F8R1_FB26 0x04000000U
2477 #define CAN_F8R1_FB27 0x08000000U
2478 #define CAN_F8R1_FB28 0x10000000U
2479 #define CAN_F8R1_FB29 0x20000000U
2480 #define CAN_F8R1_FB30 0x40000000U
2481 #define CAN_F8R1_FB31 0x80000000U
2483 /******************* Bit definition for CAN_F9R1 register *******************/
2484 #define CAN_F9R1_FB0 0x00000001U
2485 #define CAN_F9R1_FB1 0x00000002U
2486 #define CAN_F9R1_FB2 0x00000004U
2487 #define CAN_F9R1_FB3 0x00000008U
2488 #define CAN_F9R1_FB4 0x00000010U
2489 #define CAN_F9R1_FB5 0x00000020U
2490 #define CAN_F9R1_FB6 0x00000040U
2491 #define CAN_F9R1_FB7 0x00000080U
2492 #define CAN_F9R1_FB8 0x00000100U
2493 #define CAN_F9R1_FB9 0x00000200U
2494 #define CAN_F9R1_FB10 0x00000400U
2495 #define CAN_F9R1_FB11 0x00000800U
2496 #define CAN_F9R1_FB12 0x00001000U
2497 #define CAN_F9R1_FB13 0x00002000U
2498 #define CAN_F9R1_FB14 0x00004000U
2499 #define CAN_F9R1_FB15 0x00008000U
2500 #define CAN_F9R1_FB16 0x00010000U
2501 #define CAN_F9R1_FB17 0x00020000U
2502 #define CAN_F9R1_FB18 0x00040000U
2503 #define CAN_F9R1_FB19 0x00080000U
2504 #define CAN_F9R1_FB20 0x00100000U
2505 #define CAN_F9R1_FB21 0x00200000U
2506 #define CAN_F9R1_FB22 0x00400000U
2507 #define CAN_F9R1_FB23 0x00800000U
2508 #define CAN_F9R1_FB24 0x01000000U
2509 #define CAN_F9R1_FB25 0x02000000U
2510 #define CAN_F9R1_FB26 0x04000000U
2511 #define CAN_F9R1_FB27 0x08000000U
2512 #define CAN_F9R1_FB28 0x10000000U
2513 #define CAN_F9R1_FB29 0x20000000U
2514 #define CAN_F9R1_FB30 0x40000000U
2515 #define CAN_F9R1_FB31 0x80000000U
2517 /******************* Bit definition for CAN_F10R1 register ******************/
2518 #define CAN_F10R1_FB0 0x00000001U
2519 #define CAN_F10R1_FB1 0x00000002U
2520 #define CAN_F10R1_FB2 0x00000004U
2521 #define CAN_F10R1_FB3 0x00000008U
2522 #define CAN_F10R1_FB4 0x00000010U
2523 #define CAN_F10R1_FB5 0x00000020U
2524 #define CAN_F10R1_FB6 0x00000040U
2525 #define CAN_F10R1_FB7 0x00000080U
2526 #define CAN_F10R1_FB8 0x00000100U
2527 #define CAN_F10R1_FB9 0x00000200U
2528 #define CAN_F10R1_FB10 0x00000400U
2529 #define CAN_F10R1_FB11 0x00000800U
2530 #define CAN_F10R1_FB12 0x00001000U
2531 #define CAN_F10R1_FB13 0x00002000U
2532 #define CAN_F10R1_FB14 0x00004000U
2533 #define CAN_F10R1_FB15 0x00008000U
2534 #define CAN_F10R1_FB16 0x00010000U
2535 #define CAN_F10R1_FB17 0x00020000U
2536 #define CAN_F10R1_FB18 0x00040000U
2537 #define CAN_F10R1_FB19 0x00080000U
2538 #define CAN_F10R1_FB20 0x00100000U
2539 #define CAN_F10R1_FB21 0x00200000U
2540 #define CAN_F10R1_FB22 0x00400000U
2541 #define CAN_F10R1_FB23 0x00800000U
2542 #define CAN_F10R1_FB24 0x01000000U
2543 #define CAN_F10R1_FB25 0x02000000U
2544 #define CAN_F10R1_FB26 0x04000000U
2545 #define CAN_F10R1_FB27 0x08000000U
2546 #define CAN_F10R1_FB28 0x10000000U
2547 #define CAN_F10R1_FB29 0x20000000U
2548 #define CAN_F10R1_FB30 0x40000000U
2549 #define CAN_F10R1_FB31 0x80000000U
2551 /******************* Bit definition for CAN_F11R1 register ******************/
2552 #define CAN_F11R1_FB0 0x00000001U
2553 #define CAN_F11R1_FB1 0x00000002U
2554 #define CAN_F11R1_FB2 0x00000004U
2555 #define CAN_F11R1_FB3 0x00000008U
2556 #define CAN_F11R1_FB4 0x00000010U
2557 #define CAN_F11R1_FB5 0x00000020U
2558 #define CAN_F11R1_FB6 0x00000040U
2559 #define CAN_F11R1_FB7 0x00000080U
2560 #define CAN_F11R1_FB8 0x00000100U
2561 #define CAN_F11R1_FB9 0x00000200U
2562 #define CAN_F11R1_FB10 0x00000400U
2563 #define CAN_F11R1_FB11 0x00000800U
2564 #define CAN_F11R1_FB12 0x00001000U
2565 #define CAN_F11R1_FB13 0x00002000U
2566 #define CAN_F11R1_FB14 0x00004000U
2567 #define CAN_F11R1_FB15 0x00008000U
2568 #define CAN_F11R1_FB16 0x00010000U
2569 #define CAN_F11R1_FB17 0x00020000U
2570 #define CAN_F11R1_FB18 0x00040000U
2571 #define CAN_F11R1_FB19 0x00080000U
2572 #define CAN_F11R1_FB20 0x00100000U
2573 #define CAN_F11R1_FB21 0x00200000U
2574 #define CAN_F11R1_FB22 0x00400000U
2575 #define CAN_F11R1_FB23 0x00800000U
2576 #define CAN_F11R1_FB24 0x01000000U
2577 #define CAN_F11R1_FB25 0x02000000U
2578 #define CAN_F11R1_FB26 0x04000000U
2579 #define CAN_F11R1_FB27 0x08000000U
2580 #define CAN_F11R1_FB28 0x10000000U
2581 #define CAN_F11R1_FB29 0x20000000U
2582 #define CAN_F11R1_FB30 0x40000000U
2583 #define CAN_F11R1_FB31 0x80000000U
2585 /******************* Bit definition for CAN_F12R1 register ******************/
2586 #define CAN_F12R1_FB0 0x00000001U
2587 #define CAN_F12R1_FB1 0x00000002U
2588 #define CAN_F12R1_FB2 0x00000004U
2589 #define CAN_F12R1_FB3 0x00000008U
2590 #define CAN_F12R1_FB4 0x00000010U
2591 #define CAN_F12R1_FB5 0x00000020U
2592 #define CAN_F12R1_FB6 0x00000040U
2593 #define CAN_F12R1_FB7 0x00000080U
2594 #define CAN_F12R1_FB8 0x00000100U
2595 #define CAN_F12R1_FB9 0x00000200U
2596 #define CAN_F12R1_FB10 0x00000400U
2597 #define CAN_F12R1_FB11 0x00000800U
2598 #define CAN_F12R1_FB12 0x00001000U
2599 #define CAN_F12R1_FB13 0x00002000U
2600 #define CAN_F12R1_FB14 0x00004000U
2601 #define CAN_F12R1_FB15 0x00008000U
2602 #define CAN_F12R1_FB16 0x00010000U
2603 #define CAN_F12R1_FB17 0x00020000U
2604 #define CAN_F12R1_FB18 0x00040000U
2605 #define CAN_F12R1_FB19 0x00080000U
2606 #define CAN_F12R1_FB20 0x00100000U
2607 #define CAN_F12R1_FB21 0x00200000U
2608 #define CAN_F12R1_FB22 0x00400000U
2609 #define CAN_F12R1_FB23 0x00800000U
2610 #define CAN_F12R1_FB24 0x01000000U
2611 #define CAN_F12R1_FB25 0x02000000U
2612 #define CAN_F12R1_FB26 0x04000000U
2613 #define CAN_F12R1_FB27 0x08000000U
2614 #define CAN_F12R1_FB28 0x10000000U
2615 #define CAN_F12R1_FB29 0x20000000U
2616 #define CAN_F12R1_FB30 0x40000000U
2617 #define CAN_F12R1_FB31 0x80000000U
2619 /******************* Bit definition for CAN_F13R1 register ******************/
2620 #define CAN_F13R1_FB0 0x00000001U
2621 #define CAN_F13R1_FB1 0x00000002U
2622 #define CAN_F13R1_FB2 0x00000004U
2623 #define CAN_F13R1_FB3 0x00000008U
2624 #define CAN_F13R1_FB4 0x00000010U
2625 #define CAN_F13R1_FB5 0x00000020U
2626 #define CAN_F13R1_FB6 0x00000040U
2627 #define CAN_F13R1_FB7 0x00000080U
2628 #define CAN_F13R1_FB8 0x00000100U
2629 #define CAN_F13R1_FB9 0x00000200U
2630 #define CAN_F13R1_FB10 0x00000400U
2631 #define CAN_F13R1_FB11 0x00000800U
2632 #define CAN_F13R1_FB12 0x00001000U
2633 #define CAN_F13R1_FB13 0x00002000U
2634 #define CAN_F13R1_FB14 0x00004000U
2635 #define CAN_F13R1_FB15 0x00008000U
2636 #define CAN_F13R1_FB16 0x00010000U
2637 #define CAN_F13R1_FB17 0x00020000U
2638 #define CAN_F13R1_FB18 0x00040000U
2639 #define CAN_F13R1_FB19 0x00080000U
2640 #define CAN_F13R1_FB20 0x00100000U
2641 #define CAN_F13R1_FB21 0x00200000U
2642 #define CAN_F13R1_FB22 0x00400000U
2643 #define CAN_F13R1_FB23 0x00800000U
2644 #define CAN_F13R1_FB24 0x01000000U
2645 #define CAN_F13R1_FB25 0x02000000U
2646 #define CAN_F13R1_FB26 0x04000000U
2647 #define CAN_F13R1_FB27 0x08000000U
2648 #define CAN_F13R1_FB28 0x10000000U
2649 #define CAN_F13R1_FB29 0x20000000U
2650 #define CAN_F13R1_FB30 0x40000000U
2651 #define CAN_F13R1_FB31 0x80000000U
2653 /******************* Bit definition for CAN_F0R2 register *******************/
2654 #define CAN_F0R2_FB0 0x00000001U
2655 #define CAN_F0R2_FB1 0x00000002U
2656 #define CAN_F0R2_FB2 0x00000004U
2657 #define CAN_F0R2_FB3 0x00000008U
2658 #define CAN_F0R2_FB4 0x00000010U
2659 #define CAN_F0R2_FB5 0x00000020U
2660 #define CAN_F0R2_FB6 0x00000040U
2661 #define CAN_F0R2_FB7 0x00000080U
2662 #define CAN_F0R2_FB8 0x00000100U
2663 #define CAN_F0R2_FB9 0x00000200U
2664 #define CAN_F0R2_FB10 0x00000400U
2665 #define CAN_F0R2_FB11 0x00000800U
2666 #define CAN_F0R2_FB12 0x00001000U
2667 #define CAN_F0R2_FB13 0x00002000U
2668 #define CAN_F0R2_FB14 0x00004000U
2669 #define CAN_F0R2_FB15 0x00008000U
2670 #define CAN_F0R2_FB16 0x00010000U
2671 #define CAN_F0R2_FB17 0x00020000U
2672 #define CAN_F0R2_FB18 0x00040000U
2673 #define CAN_F0R2_FB19 0x00080000U
2674 #define CAN_F0R2_FB20 0x00100000U
2675 #define CAN_F0R2_FB21 0x00200000U
2676 #define CAN_F0R2_FB22 0x00400000U
2677 #define CAN_F0R2_FB23 0x00800000U
2678 #define CAN_F0R2_FB24 0x01000000U
2679 #define CAN_F0R2_FB25 0x02000000U
2680 #define CAN_F0R2_FB26 0x04000000U
2681 #define CAN_F0R2_FB27 0x08000000U
2682 #define CAN_F0R2_FB28 0x10000000U
2683 #define CAN_F0R2_FB29 0x20000000U
2684 #define CAN_F0R2_FB30 0x40000000U
2685 #define CAN_F0R2_FB31 0x80000000U
2687 /******************* Bit definition for CAN_F1R2 register *******************/
2688 #define CAN_F1R2_FB0 0x00000001U
2689 #define CAN_F1R2_FB1 0x00000002U
2690 #define CAN_F1R2_FB2 0x00000004U
2691 #define CAN_F1R2_FB3 0x00000008U
2692 #define CAN_F1R2_FB4 0x00000010U
2693 #define CAN_F1R2_FB5 0x00000020U
2694 #define CAN_F1R2_FB6 0x00000040U
2695 #define CAN_F1R2_FB7 0x00000080U
2696 #define CAN_F1R2_FB8 0x00000100U
2697 #define CAN_F1R2_FB9 0x00000200U
2698 #define CAN_F1R2_FB10 0x00000400U
2699 #define CAN_F1R2_FB11 0x00000800U
2700 #define CAN_F1R2_FB12 0x00001000U
2701 #define CAN_F1R2_FB13 0x00002000U
2702 #define CAN_F1R2_FB14 0x00004000U
2703 #define CAN_F1R2_FB15 0x00008000U
2704 #define CAN_F1R2_FB16 0x00010000U
2705 #define CAN_F1R2_FB17 0x00020000U
2706 #define CAN_F1R2_FB18 0x00040000U
2707 #define CAN_F1R2_FB19 0x00080000U
2708 #define CAN_F1R2_FB20 0x00100000U
2709 #define CAN_F1R2_FB21 0x00200000U
2710 #define CAN_F1R2_FB22 0x00400000U
2711 #define CAN_F1R2_FB23 0x00800000U
2712 #define CAN_F1R2_FB24 0x01000000U
2713 #define CAN_F1R2_FB25 0x02000000U
2714 #define CAN_F1R2_FB26 0x04000000U
2715 #define CAN_F1R2_FB27 0x08000000U
2716 #define CAN_F1R2_FB28 0x10000000U
2717 #define CAN_F1R2_FB29 0x20000000U
2718 #define CAN_F1R2_FB30 0x40000000U
2719 #define CAN_F1R2_FB31 0x80000000U
2721 /******************* Bit definition for CAN_F2R2 register *******************/
2722 #define CAN_F2R2_FB0 0x00000001U
2723 #define CAN_F2R2_FB1 0x00000002U
2724 #define CAN_F2R2_FB2 0x00000004U
2725 #define CAN_F2R2_FB3 0x00000008U
2726 #define CAN_F2R2_FB4 0x00000010U
2727 #define CAN_F2R2_FB5 0x00000020U
2728 #define CAN_F2R2_FB6 0x00000040U
2729 #define CAN_F2R2_FB7 0x00000080U
2730 #define CAN_F2R2_FB8 0x00000100U
2731 #define CAN_F2R2_FB9 0x00000200U
2732 #define CAN_F2R2_FB10 0x00000400U
2733 #define CAN_F2R2_FB11 0x00000800U
2734 #define CAN_F2R2_FB12 0x00001000U
2735 #define CAN_F2R2_FB13 0x00002000U
2736 #define CAN_F2R2_FB14 0x00004000U
2737 #define CAN_F2R2_FB15 0x00008000U
2738 #define CAN_F2R2_FB16 0x00010000U
2739 #define CAN_F2R2_FB17 0x00020000U
2740 #define CAN_F2R2_FB18 0x00040000U
2741 #define CAN_F2R2_FB19 0x00080000U
2742 #define CAN_F2R2_FB20 0x00100000U
2743 #define CAN_F2R2_FB21 0x00200000U
2744 #define CAN_F2R2_FB22 0x00400000U
2745 #define CAN_F2R2_FB23 0x00800000U
2746 #define CAN_F2R2_FB24 0x01000000U
2747 #define CAN_F2R2_FB25 0x02000000U
2748 #define CAN_F2R2_FB26 0x04000000U
2749 #define CAN_F2R2_FB27 0x08000000U
2750 #define CAN_F2R2_FB28 0x10000000U
2751 #define CAN_F2R2_FB29 0x20000000U
2752 #define CAN_F2R2_FB30 0x40000000U
2753 #define CAN_F2R2_FB31 0x80000000U
2755 /******************* Bit definition for CAN_F3R2 register *******************/
2756 #define CAN_F3R2_FB0 0x00000001U
2757 #define CAN_F3R2_FB1 0x00000002U
2758 #define CAN_F3R2_FB2 0x00000004U
2759 #define CAN_F3R2_FB3 0x00000008U
2760 #define CAN_F3R2_FB4 0x00000010U
2761 #define CAN_F3R2_FB5 0x00000020U
2762 #define CAN_F3R2_FB6 0x00000040U
2763 #define CAN_F3R2_FB7 0x00000080U
2764 #define CAN_F3R2_FB8 0x00000100U
2765 #define CAN_F3R2_FB9 0x00000200U
2766 #define CAN_F3R2_FB10 0x00000400U
2767 #define CAN_F3R2_FB11 0x00000800U
2768 #define CAN_F3R2_FB12 0x00001000U
2769 #define CAN_F3R2_FB13 0x00002000U
2770 #define CAN_F3R2_FB14 0x00004000U
2771 #define CAN_F3R2_FB15 0x00008000U
2772 #define CAN_F3R2_FB16 0x00010000U
2773 #define CAN_F3R2_FB17 0x00020000U
2774 #define CAN_F3R2_FB18 0x00040000U
2775 #define CAN_F3R2_FB19 0x00080000U
2776 #define CAN_F3R2_FB20 0x00100000U
2777 #define CAN_F3R2_FB21 0x00200000U
2778 #define CAN_F3R2_FB22 0x00400000U
2779 #define CAN_F3R2_FB23 0x00800000U
2780 #define CAN_F3R2_FB24 0x01000000U
2781 #define CAN_F3R2_FB25 0x02000000U
2782 #define CAN_F3R2_FB26 0x04000000U
2783 #define CAN_F3R2_FB27 0x08000000U
2784 #define CAN_F3R2_FB28 0x10000000U
2785 #define CAN_F3R2_FB29 0x20000000U
2786 #define CAN_F3R2_FB30 0x40000000U
2787 #define CAN_F3R2_FB31 0x80000000U
2789 /******************* Bit definition for CAN_F4R2 register *******************/
2790 #define CAN_F4R2_FB0 0x00000001U
2791 #define CAN_F4R2_FB1 0x00000002U
2792 #define CAN_F4R2_FB2 0x00000004U
2793 #define CAN_F4R2_FB3 0x00000008U
2794 #define CAN_F4R2_FB4 0x00000010U
2795 #define CAN_F4R2_FB5 0x00000020U
2796 #define CAN_F4R2_FB6 0x00000040U
2797 #define CAN_F4R2_FB7 0x00000080U
2798 #define CAN_F4R2_FB8 0x00000100U
2799 #define CAN_F4R2_FB9 0x00000200U
2800 #define CAN_F4R2_FB10 0x00000400U
2801 #define CAN_F4R2_FB11 0x00000800U
2802 #define CAN_F4R2_FB12 0x00001000U
2803 #define CAN_F4R2_FB13 0x00002000U
2804 #define CAN_F4R2_FB14 0x00004000U
2805 #define CAN_F4R2_FB15 0x00008000U
2806 #define CAN_F4R2_FB16 0x00010000U
2807 #define CAN_F4R2_FB17 0x00020000U
2808 #define CAN_F4R2_FB18 0x00040000U
2809 #define CAN_F4R2_FB19 0x00080000U
2810 #define CAN_F4R2_FB20 0x00100000U
2811 #define CAN_F4R2_FB21 0x00200000U
2812 #define CAN_F4R2_FB22 0x00400000U
2813 #define CAN_F4R2_FB23 0x00800000U
2814 #define CAN_F4R2_FB24 0x01000000U
2815 #define CAN_F4R2_FB25 0x02000000U
2816 #define CAN_F4R2_FB26 0x04000000U
2817 #define CAN_F4R2_FB27 0x08000000U
2818 #define CAN_F4R2_FB28 0x10000000U
2819 #define CAN_F4R2_FB29 0x20000000U
2820 #define CAN_F4R2_FB30 0x40000000U
2821 #define CAN_F4R2_FB31 0x80000000U
2823 /******************* Bit definition for CAN_F5R2 register *******************/
2824 #define CAN_F5R2_FB0 0x00000001U
2825 #define CAN_F5R2_FB1 0x00000002U
2826 #define CAN_F5R2_FB2 0x00000004U
2827 #define CAN_F5R2_FB3 0x00000008U
2828 #define CAN_F5R2_FB4 0x00000010U
2829 #define CAN_F5R2_FB5 0x00000020U
2830 #define CAN_F5R2_FB6 0x00000040U
2831 #define CAN_F5R2_FB7 0x00000080U
2832 #define CAN_F5R2_FB8 0x00000100U
2833 #define CAN_F5R2_FB9 0x00000200U
2834 #define CAN_F5R2_FB10 0x00000400U
2835 #define CAN_F5R2_FB11 0x00000800U
2836 #define CAN_F5R2_FB12 0x00001000U
2837 #define CAN_F5R2_FB13 0x00002000U
2838 #define CAN_F5R2_FB14 0x00004000U
2839 #define CAN_F5R2_FB15 0x00008000U
2840 #define CAN_F5R2_FB16 0x00010000U
2841 #define CAN_F5R2_FB17 0x00020000U
2842 #define CAN_F5R2_FB18 0x00040000U
2843 #define CAN_F5R2_FB19 0x00080000U
2844 #define CAN_F5R2_FB20 0x00100000U
2845 #define CAN_F5R2_FB21 0x00200000U
2846 #define CAN_F5R2_FB22 0x00400000U
2847 #define CAN_F5R2_FB23 0x00800000U
2848 #define CAN_F5R2_FB24 0x01000000U
2849 #define CAN_F5R2_FB25 0x02000000U
2850 #define CAN_F5R2_FB26 0x04000000U
2851 #define CAN_F5R2_FB27 0x08000000U
2852 #define CAN_F5R2_FB28 0x10000000U
2853 #define CAN_F5R2_FB29 0x20000000U
2854 #define CAN_F5R2_FB30 0x40000000U
2855 #define CAN_F5R2_FB31 0x80000000U
2857 /******************* Bit definition for CAN_F6R2 register *******************/
2858 #define CAN_F6R2_FB0 0x00000001U
2859 #define CAN_F6R2_FB1 0x00000002U
2860 #define CAN_F6R2_FB2 0x00000004U
2861 #define CAN_F6R2_FB3 0x00000008U
2862 #define CAN_F6R2_FB4 0x00000010U
2863 #define CAN_F6R2_FB5 0x00000020U
2864 #define CAN_F6R2_FB6 0x00000040U
2865 #define CAN_F6R2_FB7 0x00000080U
2866 #define CAN_F6R2_FB8 0x00000100U
2867 #define CAN_F6R2_FB9 0x00000200U
2868 #define CAN_F6R2_FB10 0x00000400U
2869 #define CAN_F6R2_FB11 0x00000800U
2870 #define CAN_F6R2_FB12 0x00001000U
2871 #define CAN_F6R2_FB13 0x00002000U
2872 #define CAN_F6R2_FB14 0x00004000U
2873 #define CAN_F6R2_FB15 0x00008000U
2874 #define CAN_F6R2_FB16 0x00010000U
2875 #define CAN_F6R2_FB17 0x00020000U
2876 #define CAN_F6R2_FB18 0x00040000U
2877 #define CAN_F6R2_FB19 0x00080000U
2878 #define CAN_F6R2_FB20 0x00100000U
2879 #define CAN_F6R2_FB21 0x00200000U
2880 #define CAN_F6R2_FB22 0x00400000U
2881 #define CAN_F6R2_FB23 0x00800000U
2882 #define CAN_F6R2_FB24 0x01000000U
2883 #define CAN_F6R2_FB25 0x02000000U
2884 #define CAN_F6R2_FB26 0x04000000U
2885 #define CAN_F6R2_FB27 0x08000000U
2886 #define CAN_F6R2_FB28 0x10000000U
2887 #define CAN_F6R2_FB29 0x20000000U
2888 #define CAN_F6R2_FB30 0x40000000U
2889 #define CAN_F6R2_FB31 0x80000000U
2891 /******************* Bit definition for CAN_F7R2 register *******************/
2892 #define CAN_F7R2_FB0 0x00000001U
2893 #define CAN_F7R2_FB1 0x00000002U
2894 #define CAN_F7R2_FB2 0x00000004U
2895 #define CAN_F7R2_FB3 0x00000008U
2896 #define CAN_F7R2_FB4 0x00000010U
2897 #define CAN_F7R2_FB5 0x00000020U
2898 #define CAN_F7R2_FB6 0x00000040U
2899 #define CAN_F7R2_FB7 0x00000080U
2900 #define CAN_F7R2_FB8 0x00000100U
2901 #define CAN_F7R2_FB9 0x00000200U
2902 #define CAN_F7R2_FB10 0x00000400U
2903 #define CAN_F7R2_FB11 0x00000800U
2904 #define CAN_F7R2_FB12 0x00001000U
2905 #define CAN_F7R2_FB13 0x00002000U
2906 #define CAN_F7R2_FB14 0x00004000U
2907 #define CAN_F7R2_FB15 0x00008000U
2908 #define CAN_F7R2_FB16 0x00010000U
2909 #define CAN_F7R2_FB17 0x00020000U
2910 #define CAN_F7R2_FB18 0x00040000U
2911 #define CAN_F7R2_FB19 0x00080000U
2912 #define CAN_F7R2_FB20 0x00100000U
2913 #define CAN_F7R2_FB21 0x00200000U
2914 #define CAN_F7R2_FB22 0x00400000U
2915 #define CAN_F7R2_FB23 0x00800000U
2916 #define CAN_F7R2_FB24 0x01000000U
2917 #define CAN_F7R2_FB25 0x02000000U
2918 #define CAN_F7R2_FB26 0x04000000U
2919 #define CAN_F7R2_FB27 0x08000000U
2920 #define CAN_F7R2_FB28 0x10000000U
2921 #define CAN_F7R2_FB29 0x20000000U
2922 #define CAN_F7R2_FB30 0x40000000U
2923 #define CAN_F7R2_FB31 0x80000000U
2925 /******************* Bit definition for CAN_F8R2 register *******************/
2926 #define CAN_F8R2_FB0 0x00000001U
2927 #define CAN_F8R2_FB1 0x00000002U
2928 #define CAN_F8R2_FB2 0x00000004U
2929 #define CAN_F8R2_FB3 0x00000008U
2930 #define CAN_F8R2_FB4 0x00000010U
2931 #define CAN_F8R2_FB5 0x00000020U
2932 #define CAN_F8R2_FB6 0x00000040U
2933 #define CAN_F8R2_FB7 0x00000080U
2934 #define CAN_F8R2_FB8 0x00000100U
2935 #define CAN_F8R2_FB9 0x00000200U
2936 #define CAN_F8R2_FB10 0x00000400U
2937 #define CAN_F8R2_FB11 0x00000800U
2938 #define CAN_F8R2_FB12 0x00001000U
2939 #define CAN_F8R2_FB13 0x00002000U
2940 #define CAN_F8R2_FB14 0x00004000U
2941 #define CAN_F8R2_FB15 0x00008000U
2942 #define CAN_F8R2_FB16 0x00010000U
2943 #define CAN_F8R2_FB17 0x00020000U
2944 #define CAN_F8R2_FB18 0x00040000U
2945 #define CAN_F8R2_FB19 0x00080000U
2946 #define CAN_F8R2_FB20 0x00100000U
2947 #define CAN_F8R2_FB21 0x00200000U
2948 #define CAN_F8R2_FB22 0x00400000U
2949 #define CAN_F8R2_FB23 0x00800000U
2950 #define CAN_F8R2_FB24 0x01000000U
2951 #define CAN_F8R2_FB25 0x02000000U
2952 #define CAN_F8R2_FB26 0x04000000U
2953 #define CAN_F8R2_FB27 0x08000000U
2954 #define CAN_F8R2_FB28 0x10000000U
2955 #define CAN_F8R2_FB29 0x20000000U
2956 #define CAN_F8R2_FB30 0x40000000U
2957 #define CAN_F8R2_FB31 0x80000000U
2959 /******************* Bit definition for CAN_F9R2 register *******************/
2960 #define CAN_F9R2_FB0 0x00000001U
2961 #define CAN_F9R2_FB1 0x00000002U
2962 #define CAN_F9R2_FB2 0x00000004U
2963 #define CAN_F9R2_FB3 0x00000008U
2964 #define CAN_F9R2_FB4 0x00000010U
2965 #define CAN_F9R2_FB5 0x00000020U
2966 #define CAN_F9R2_FB6 0x00000040U
2967 #define CAN_F9R2_FB7 0x00000080U
2968 #define CAN_F9R2_FB8 0x00000100U
2969 #define CAN_F9R2_FB9 0x00000200U
2970 #define CAN_F9R2_FB10 0x00000400U
2971 #define CAN_F9R2_FB11 0x00000800U
2972 #define CAN_F9R2_FB12 0x00001000U
2973 #define CAN_F9R2_FB13 0x00002000U
2974 #define CAN_F9R2_FB14 0x00004000U
2975 #define CAN_F9R2_FB15 0x00008000U
2976 #define CAN_F9R2_FB16 0x00010000U
2977 #define CAN_F9R2_FB17 0x00020000U
2978 #define CAN_F9R2_FB18 0x00040000U
2979 #define CAN_F9R2_FB19 0x00080000U
2980 #define CAN_F9R2_FB20 0x00100000U
2981 #define CAN_F9R2_FB21 0x00200000U
2982 #define CAN_F9R2_FB22 0x00400000U
2983 #define CAN_F9R2_FB23 0x00800000U
2984 #define CAN_F9R2_FB24 0x01000000U
2985 #define CAN_F9R2_FB25 0x02000000U
2986 #define CAN_F9R2_FB26 0x04000000U
2987 #define CAN_F9R2_FB27 0x08000000U
2988 #define CAN_F9R2_FB28 0x10000000U
2989 #define CAN_F9R2_FB29 0x20000000U
2990 #define CAN_F9R2_FB30 0x40000000U
2991 #define CAN_F9R2_FB31 0x80000000U
2993 /******************* Bit definition for CAN_F10R2 register ******************/
2994 #define CAN_F10R2_FB0 0x00000001U
2995 #define CAN_F10R2_FB1 0x00000002U
2996 #define CAN_F10R2_FB2 0x00000004U
2997 #define CAN_F10R2_FB3 0x00000008U
2998 #define CAN_F10R2_FB4 0x00000010U
2999 #define CAN_F10R2_FB5 0x00000020U
3000 #define CAN_F10R2_FB6 0x00000040U
3001 #define CAN_F10R2_FB7 0x00000080U
3002 #define CAN_F10R2_FB8 0x00000100U
3003 #define CAN_F10R2_FB9 0x00000200U
3004 #define CAN_F10R2_FB10 0x00000400U
3005 #define CAN_F10R2_FB11 0x00000800U
3006 #define CAN_F10R2_FB12 0x00001000U
3007 #define CAN_F10R2_FB13 0x00002000U
3008 #define CAN_F10R2_FB14 0x00004000U
3009 #define CAN_F10R2_FB15 0x00008000U
3010 #define CAN_F10R2_FB16 0x00010000U
3011 #define CAN_F10R2_FB17 0x00020000U
3012 #define CAN_F10R2_FB18 0x00040000U
3013 #define CAN_F10R2_FB19 0x00080000U
3014 #define CAN_F10R2_FB20 0x00100000U
3015 #define CAN_F10R2_FB21 0x00200000U
3016 #define CAN_F10R2_FB22 0x00400000U
3017 #define CAN_F10R2_FB23 0x00800000U
3018 #define CAN_F10R2_FB24 0x01000000U
3019 #define CAN_F10R2_FB25 0x02000000U
3020 #define CAN_F10R2_FB26 0x04000000U
3021 #define CAN_F10R2_FB27 0x08000000U
3022 #define CAN_F10R2_FB28 0x10000000U
3023 #define CAN_F10R2_FB29 0x20000000U
3024 #define CAN_F10R2_FB30 0x40000000U
3025 #define CAN_F10R2_FB31 0x80000000U
3027 /******************* Bit definition for CAN_F11R2 register ******************/
3028 #define CAN_F11R2_FB0 0x00000001U
3029 #define CAN_F11R2_FB1 0x00000002U
3030 #define CAN_F11R2_FB2 0x00000004U
3031 #define CAN_F11R2_FB3 0x00000008U
3032 #define CAN_F11R2_FB4 0x00000010U
3033 #define CAN_F11R2_FB5 0x00000020U
3034 #define CAN_F11R2_FB6 0x00000040U
3035 #define CAN_F11R2_FB7 0x00000080U
3036 #define CAN_F11R2_FB8 0x00000100U
3037 #define CAN_F11R2_FB9 0x00000200U
3038 #define CAN_F11R2_FB10 0x00000400U
3039 #define CAN_F11R2_FB11 0x00000800U
3040 #define CAN_F11R2_FB12 0x00001000U
3041 #define CAN_F11R2_FB13 0x00002000U
3042 #define CAN_F11R2_FB14 0x00004000U
3043 #define CAN_F11R2_FB15 0x00008000U
3044 #define CAN_F11R2_FB16 0x00010000U
3045 #define CAN_F11R2_FB17 0x00020000U
3046 #define CAN_F11R2_FB18 0x00040000U
3047 #define CAN_F11R2_FB19 0x00080000U
3048 #define CAN_F11R2_FB20 0x00100000U
3049 #define CAN_F11R2_FB21 0x00200000U
3050 #define CAN_F11R2_FB22 0x00400000U
3051 #define CAN_F11R2_FB23 0x00800000U
3052 #define CAN_F11R2_FB24 0x01000000U
3053 #define CAN_F11R2_FB25 0x02000000U
3054 #define CAN_F11R2_FB26 0x04000000U
3055 #define CAN_F11R2_FB27 0x08000000U
3056 #define CAN_F11R2_FB28 0x10000000U
3057 #define CAN_F11R2_FB29 0x20000000U
3058 #define CAN_F11R2_FB30 0x40000000U
3059 #define CAN_F11R2_FB31 0x80000000U
3061 /******************* Bit definition for CAN_F12R2 register ******************/
3062 #define CAN_F12R2_FB0 0x00000001U
3063 #define CAN_F12R2_FB1 0x00000002U
3064 #define CAN_F12R2_FB2 0x00000004U
3065 #define CAN_F12R2_FB3 0x00000008U
3066 #define CAN_F12R2_FB4 0x00000010U
3067 #define CAN_F12R2_FB5 0x00000020U
3068 #define CAN_F12R2_FB6 0x00000040U
3069 #define CAN_F12R2_FB7 0x00000080U
3070 #define CAN_F12R2_FB8 0x00000100U
3071 #define CAN_F12R2_FB9 0x00000200U
3072 #define CAN_F12R2_FB10 0x00000400U
3073 #define CAN_F12R2_FB11 0x00000800U
3074 #define CAN_F12R2_FB12 0x00001000U
3075 #define CAN_F12R2_FB13 0x00002000U
3076 #define CAN_F12R2_FB14 0x00004000U
3077 #define CAN_F12R2_FB15 0x00008000U
3078 #define CAN_F12R2_FB16 0x00010000U
3079 #define CAN_F12R2_FB17 0x00020000U
3080 #define CAN_F12R2_FB18 0x00040000U
3081 #define CAN_F12R2_FB19 0x00080000U
3082 #define CAN_F12R2_FB20 0x00100000U
3083 #define CAN_F12R2_FB21 0x00200000U
3084 #define CAN_F12R2_FB22 0x00400000U
3085 #define CAN_F12R2_FB23 0x00800000U
3086 #define CAN_F12R2_FB24 0x01000000U
3087 #define CAN_F12R2_FB25 0x02000000U
3088 #define CAN_F12R2_FB26 0x04000000U
3089 #define CAN_F12R2_FB27 0x08000000U
3090 #define CAN_F12R2_FB28 0x10000000U
3091 #define CAN_F12R2_FB29 0x20000000U
3092 #define CAN_F12R2_FB30 0x40000000U
3093 #define CAN_F12R2_FB31 0x80000000U
3095 /******************* Bit definition for CAN_F13R2 register ******************/
3096 #define CAN_F13R2_FB0 0x00000001U
3097 #define CAN_F13R2_FB1 0x00000002U
3098 #define CAN_F13R2_FB2 0x00000004U
3099 #define CAN_F13R2_FB3 0x00000008U
3100 #define CAN_F13R2_FB4 0x00000010U
3101 #define CAN_F13R2_FB5 0x00000020U
3102 #define CAN_F13R2_FB6 0x00000040U
3103 #define CAN_F13R2_FB7 0x00000080U
3104 #define CAN_F13R2_FB8 0x00000100U
3105 #define CAN_F13R2_FB9 0x00000200U
3106 #define CAN_F13R2_FB10 0x00000400U
3107 #define CAN_F13R2_FB11 0x00000800U
3108 #define CAN_F13R2_FB12 0x00001000U
3109 #define CAN_F13R2_FB13 0x00002000U
3110 #define CAN_F13R2_FB14 0x00004000U
3111 #define CAN_F13R2_FB15 0x00008000U
3112 #define CAN_F13R2_FB16 0x00010000U
3113 #define CAN_F13R2_FB17 0x00020000U
3114 #define CAN_F13R2_FB18 0x00040000U
3115 #define CAN_F13R2_FB19 0x00080000U
3116 #define CAN_F13R2_FB20 0x00100000U
3117 #define CAN_F13R2_FB21 0x00200000U
3118 #define CAN_F13R2_FB22 0x00400000U
3119 #define CAN_F13R2_FB23 0x00800000U
3120 #define CAN_F13R2_FB24 0x01000000U
3121 #define CAN_F13R2_FB25 0x02000000U
3122 #define CAN_F13R2_FB26 0x04000000U
3123 #define CAN_F13R2_FB27 0x08000000U
3124 #define CAN_F13R2_FB28 0x10000000U
3125 #define CAN_F13R2_FB29 0x20000000U
3126 #define CAN_F13R2_FB30 0x40000000U
3127 #define CAN_F13R2_FB31 0x80000000U
3129 /******************************************************************************/
3130 /* */
3131 /* HDMI-CEC (CEC) */
3132 /* */
3133 /******************************************************************************/
3134 
3135 /******************* Bit definition for CEC_CR register *********************/
3136 #define CEC_CR_CECEN 0x00000001U
3137 #define CEC_CR_TXSOM 0x00000002U
3138 #define CEC_CR_TXEOM 0x00000004U
3140 /******************* Bit definition for CEC_CFGR register *******************/
3141 #define CEC_CFGR_SFT 0x00000007U
3142 #define CEC_CFGR_RXTOL 0x00000008U
3143 #define CEC_CFGR_BRESTP 0x00000010U
3144 #define CEC_CFGR_BREGEN 0x00000020U
3145 #define CEC_CFGR_LBPEGEN 0x00000040U
3146 #define CEC_CFGR_BRDNOGEN 0x00000080U
3147 #define CEC_CFGR_SFTOPT 0x00000100U
3148 #define CEC_CFGR_OAR 0x7FFF0000U
3149 #define CEC_CFGR_LSTN 0x80000000U
3151 /******************* Bit definition for CEC_TXDR register *******************/
3152 #define CEC_TXDR_TXD 0x000000FFU
3154 /******************* Bit definition for CEC_RXDR register *******************/
3155 #define CEC_TXDR_RXD 0x000000FFU
3157 /******************* Bit definition for CEC_ISR register ********************/
3158 #define CEC_ISR_RXBR 0x00000001U
3159 #define CEC_ISR_RXEND 0x00000002U
3160 #define CEC_ISR_RXOVR 0x00000004U
3161 #define CEC_ISR_BRE 0x00000008U
3162 #define CEC_ISR_SBPE 0x00000010U
3163 #define CEC_ISR_LBPE 0x00000020U
3164 #define CEC_ISR_RXACKE 0x00000040U
3165 #define CEC_ISR_ARBLST 0x00000080U
3166 #define CEC_ISR_TXBR 0x00000100U
3167 #define CEC_ISR_TXEND 0x00000200U
3168 #define CEC_ISR_TXUDR 0x00000400U
3169 #define CEC_ISR_TXERR 0x00000800U
3170 #define CEC_ISR_TXACKE 0x00001000U
3172 /******************* Bit definition for CEC_IER register ********************/
3173 #define CEC_IER_RXBRIE 0x00000001U
3174 #define CEC_IER_RXENDIE 0x00000002U
3175 #define CEC_IER_RXOVRIE 0x00000004U
3176 #define CEC_IER_BREIE 0x00000008U
3177 #define CEC_IER_SBPEIE 0x00000010U
3178 #define CEC_IER_LBPEIE 0x00000020U
3179 #define CEC_IER_RXACKEIE 0x00000040U
3180 #define CEC_IER_ARBLSTIE 0x00000080U
3181 #define CEC_IER_TXBRIE 0x00000100U
3182 #define CEC_IER_TXENDIE 0x00000200U
3183 #define CEC_IER_TXUDRIE 0x00000400U
3184 #define CEC_IER_TXERRIE 0x00000800U
3185 #define CEC_IER_TXACKEIE 0x00001000U
3187 /******************************************************************************/
3188 /* */
3189 /* CRC calculation unit */
3190 /* */
3191 /******************************************************************************/
3192 /******************* Bit definition for CRC_DR register *********************/
3193 #define CRC_DR_DR 0xFFFFFFFFU
3195 /******************* Bit definition for CRC_IDR register ********************/
3196 #define CRC_IDR_IDR 0x000000FFU
3198 /******************** Bit definition for CRC_CR register ********************/
3199 #define CRC_CR_RESET 0x00000001U
3200 #define CRC_CR_POLYSIZE 0x00000018U
3201 #define CRC_CR_POLYSIZE_0 0x00000008U
3202 #define CRC_CR_POLYSIZE_1 0x00000010U
3203 #define CRC_CR_REV_IN 0x00000060U
3204 #define CRC_CR_REV_IN_0 0x00000020U
3205 #define CRC_CR_REV_IN_1 0x00000040U
3206 #define CRC_CR_REV_OUT 0x00000080U
3208 /******************* Bit definition for CRC_INIT register *******************/
3209 #define CRC_INIT_INIT 0xFFFFFFFFU
3211 /******************* Bit definition for CRC_POL register ********************/
3212 #define CRC_POL_POL 0xFFFFFFFFU
3214 /******************************************************************************/
3215 /* */
3216 /* Crypto Processor */
3217 /* */
3218 /******************************************************************************/
3219 /******************* Bits definition for CRYP_CR register ********************/
3220 #define CRYP_CR_ALGODIR 0x00000004U
3221 
3222 #define CRYP_CR_ALGOMODE 0x00080038U
3223 #define CRYP_CR_ALGOMODE_0 0x00000008U
3224 #define CRYP_CR_ALGOMODE_1 0x00000010U
3225 #define CRYP_CR_ALGOMODE_2 0x00000020U
3226 #define CRYP_CR_ALGOMODE_TDES_ECB 0x00000000U
3227 #define CRYP_CR_ALGOMODE_TDES_CBC 0x00000008U
3228 #define CRYP_CR_ALGOMODE_DES_ECB 0x00000010U
3229 #define CRYP_CR_ALGOMODE_DES_CBC 0x00000018U
3230 #define CRYP_CR_ALGOMODE_AES_ECB 0x00000020U
3231 #define CRYP_CR_ALGOMODE_AES_CBC 0x00000028U
3232 #define CRYP_CR_ALGOMODE_AES_CTR 0x00000030U
3233 #define CRYP_CR_ALGOMODE_AES_KEY 0x00000038U
3234 
3235 #define CRYP_CR_DATATYPE 0x000000C0U
3236 #define CRYP_CR_DATATYPE_0 0x00000040U
3237 #define CRYP_CR_DATATYPE_1 0x00000080U
3238 #define CRYP_CR_KEYSIZE 0x00000300U
3239 #define CRYP_CR_KEYSIZE_0 0x00000100U
3240 #define CRYP_CR_KEYSIZE_1 0x00000200U
3241 #define CRYP_CR_FFLUSH 0x00004000U
3242 #define CRYP_CR_CRYPEN 0x00008000U
3243 
3244 #define CRYP_CR_GCM_CCMPH 0x00030000U
3245 #define CRYP_CR_GCM_CCMPH_0 0x00010000U
3246 #define CRYP_CR_GCM_CCMPH_1 0x00020000U
3247 #define CRYP_CR_ALGOMODE_3 0x00080000U
3248 
3249 /****************** Bits definition for CRYP_SR register *********************/
3250 #define CRYP_SR_IFEM 0x00000001U
3251 #define CRYP_SR_IFNF 0x00000002U
3252 #define CRYP_SR_OFNE 0x00000004U
3253 #define CRYP_SR_OFFU 0x00000008U
3254 #define CRYP_SR_BUSY 0x00000010U
3255 /****************** Bits definition for CRYP_DMACR register ******************/
3256 #define CRYP_DMACR_DIEN 0x00000001U
3257 #define CRYP_DMACR_DOEN 0x00000002U
3258 /***************** Bits definition for CRYP_IMSCR register ******************/
3259 #define CRYP_IMSCR_INIM 0x00000001U
3260 #define CRYP_IMSCR_OUTIM 0x00000002U
3261 /****************** Bits definition for CRYP_RISR register *******************/
3262 #define CRYP_RISR_OUTRIS 0x00000001U
3263 #define CRYP_RISR_INRIS 0x00000002U
3264 /****************** Bits definition for CRYP_MISR register *******************/
3265 #define CRYP_MISR_INMIS 0x00000001U
3266 #define CRYP_MISR_OUTMIS 0x00000002U
3267 
3268 /******************************************************************************/
3269 /* */
3270 /* Digital to Analog Converter */
3271 /* */
3272 /******************************************************************************/
3273 /******************** Bit definition for DAC_CR register ********************/
3274 #define DAC_CR_EN1 0x00000001U
3275 #define DAC_CR_BOFF1 0x00000002U
3276 #define DAC_CR_TEN1 0x00000004U
3277 #define DAC_CR_TSEL1 0x00000038U
3278 #define DAC_CR_TSEL1_0 0x00000008U
3279 #define DAC_CR_TSEL1_1 0x00000010U
3280 #define DAC_CR_TSEL1_2 0x00000020U
3281 #define DAC_CR_WAVE1 0x000000C0U
3282 #define DAC_CR_WAVE1_0 0x00000040U
3283 #define DAC_CR_WAVE1_1 0x00000080U
3284 #define DAC_CR_MAMP1 0x00000F00U
3285 #define DAC_CR_MAMP1_0 0x00000100U
3286 #define DAC_CR_MAMP1_1 0x00000200U
3287 #define DAC_CR_MAMP1_2 0x00000400U
3288 #define DAC_CR_MAMP1_3 0x00000800U
3289 #define DAC_CR_DMAEN1 0x00001000U
3290 #define DAC_CR_DMAUDRIE1 0x00002000U
3291 #define DAC_CR_EN2 0x00010000U
3292 #define DAC_CR_BOFF2 0x00020000U
3293 #define DAC_CR_TEN2 0x00040000U
3294 #define DAC_CR_TSEL2 0x00380000U
3295 #define DAC_CR_TSEL2_0 0x00080000U
3296 #define DAC_CR_TSEL2_1 0x00100000U
3297 #define DAC_CR_TSEL2_2 0x00200000U
3298 #define DAC_CR_WAVE2 0x00C00000U
3299 #define DAC_CR_WAVE2_0 0x00400000U
3300 #define DAC_CR_WAVE2_1 0x00800000U
3301 #define DAC_CR_MAMP2 0x0F000000U
3302 #define DAC_CR_MAMP2_0 0x01000000U
3303 #define DAC_CR_MAMP2_1 0x02000000U
3304 #define DAC_CR_MAMP2_2 0x04000000U
3305 #define DAC_CR_MAMP2_3 0x08000000U
3306 #define DAC_CR_DMAEN2 0x10000000U
3307 #define DAC_CR_DMAUDRIE2 0x20000000U
3309 /***************** Bit definition for DAC_SWTRIGR register ******************/
3310 #define DAC_SWTRIGR_SWTRIG1 0x01U
3311 #define DAC_SWTRIGR_SWTRIG2 0x02U
3313 /***************** Bit definition for DAC_DHR12R1 register ******************/
3314 #define DAC_DHR12R1_DACC1DHR 0x0FFFU
3316 /***************** Bit definition for DAC_DHR12L1 register ******************/
3317 #define DAC_DHR12L1_DACC1DHR 0xFFF0U
3319 /****************** Bit definition for DAC_DHR8R1 register ******************/
3320 #define DAC_DHR8R1_DACC1DHR 0xFFU
3322 /***************** Bit definition for DAC_DHR12R2 register ******************/
3323 #define DAC_DHR12R2_DACC2DHR 0x0FFFU
3325 /***************** Bit definition for DAC_DHR12L2 register ******************/
3326 #define DAC_DHR12L2_DACC2DHR 0xFFF0U
3328 /****************** Bit definition for DAC_DHR8R2 register ******************/
3329 #define DAC_DHR8R2_DACC2DHR 0xFFU
3331 /***************** Bit definition for DAC_DHR12RD register ******************/
3332 #define DAC_DHR12RD_DACC1DHR 0x00000FFFU
3333 #define DAC_DHR12RD_DACC2DHR 0x0FFF0000U
3335 /***************** Bit definition for DAC_DHR12LD register ******************/
3336 #define DAC_DHR12LD_DACC1DHR 0x0000FFF0U
3337 #define DAC_DHR12LD_DACC2DHR 0xFFF00000U
3339 /****************** Bit definition for DAC_DHR8RD register ******************/
3340 #define DAC_DHR8RD_DACC1DHR 0x00FFU
3341 #define DAC_DHR8RD_DACC2DHR 0xFF00U
3343 /******************* Bit definition for DAC_DOR1 register *******************/
3344 #define DAC_DOR1_DACC1DOR 0x0FFFU
3346 /******************* Bit definition for DAC_DOR2 register *******************/
3347 #define DAC_DOR2_DACC2DOR 0x0FFFU
3349 /******************** Bit definition for DAC_SR register ********************/
3350 #define DAC_SR_DMAUDR1 0x00002000U
3351 #define DAC_SR_DMAUDR2 0x20000000U
3354 /******************************************************************************/
3355 /* */
3356 /* Debug MCU */
3357 /* */
3358 /******************************************************************************/
3359 
3360 /******************************************************************************/
3361 /* */
3362 /* DCMI */
3363 /* */
3364 /******************************************************************************/
3365 /******************** Bits definition for DCMI_CR register ******************/
3366 #define DCMI_CR_CAPTURE 0x00000001U
3367 #define DCMI_CR_CM 0x00000002U
3368 #define DCMI_CR_CROP 0x00000004U
3369 #define DCMI_CR_JPEG 0x00000008U
3370 #define DCMI_CR_ESS 0x00000010U
3371 #define DCMI_CR_PCKPOL 0x00000020U
3372 #define DCMI_CR_HSPOL 0x00000040U
3373 #define DCMI_CR_VSPOL 0x00000080U
3374 #define DCMI_CR_FCRC_0 0x00000100U
3375 #define DCMI_CR_FCRC_1 0x00000200U
3376 #define DCMI_CR_EDM_0 0x00000400U
3377 #define DCMI_CR_EDM_1 0x00000800U
3378 #define DCMI_CR_CRE 0x00001000U
3379 #define DCMI_CR_ENABLE 0x00004000U
3380 #define DCMI_CR_BSM 0x00030000U
3381 #define DCMI_CR_BSM_0 0x00010000U
3382 #define DCMI_CR_BSM_1 0x00020000U
3383 #define DCMI_CR_OEBS 0x00040000U
3384 #define DCMI_CR_LSM 0x00080000U
3385 #define DCMI_CR_OELS 0x00100000U
3386 
3387 /******************** Bits definition for DCMI_SR register ******************/
3388 #define DCMI_SR_HSYNC 0x00000001U
3389 #define DCMI_SR_VSYNC 0x00000002U
3390 #define DCMI_SR_FNE 0x00000004U
3391 
3392 /******************** Bits definition for DCMI_RIS register ****************/
3393 #define DCMI_RIS_FRAME_RIS 0x00000001U
3394 #define DCMI_RIS_OVR_RIS 0x00000002U
3395 #define DCMI_RIS_ERR_RIS 0x00000004U
3396 #define DCMI_RIS_VSYNC_RIS 0x00000008U
3397 #define DCMI_RIS_LINE_RIS 0x00000010U
3398 
3399 /* Legacy defines */
3400 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
3401 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
3402 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
3403 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
3404 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
3405 
3406 /******************** Bits definition for DCMI_IER register *****************/
3407 #define DCMI_IER_FRAME_IE 0x00000001U
3408 #define DCMI_IER_OVR_IE 0x00000002U
3409 #define DCMI_IER_ERR_IE 0x00000004U
3410 #define DCMI_IER_VSYNC_IE 0x00000008U
3411 #define DCMI_IER_LINE_IE 0x00000010U
3412 
3413 /* Legacy define */
3414 #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
3415 
3416 /******************** Bits definition for DCMI_MIS register *****************/
3417 #define DCMI_MIS_FRAME_MIS 0x00000001U
3418 #define DCMI_MIS_OVR_MIS 0x00000002U
3419 #define DCMI_MIS_ERR_MIS 0x00000004U
3420 #define DCMI_MIS_VSYNC_MIS 0x00000008U
3421 #define DCMI_MIS_LINE_MIS 0x00000010U
3422 
3423 /* Legacy defines */
3424 #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
3425 #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
3426 #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
3427 #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
3428 #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
3429 
3430 /******************** Bits definition for DCMI_ICR register *****************/
3431 #define DCMI_ICR_FRAME_ISC 0x00000001U
3432 #define DCMI_ICR_OVR_ISC 0x00000002U
3433 #define DCMI_ICR_ERR_ISC 0x00000004U
3434 #define DCMI_ICR_VSYNC_ISC 0x00000008U
3435 #define DCMI_ICR_LINE_ISC 0x00000010U
3436 
3437 /* Legacy defines */
3438 #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
3439 
3440 /******************** Bits definition for DCMI_ESCR register ******************/
3441 #define DCMI_ESCR_FSC 0x000000FFU
3442 #define DCMI_ESCR_LSC 0x0000FF00U
3443 #define DCMI_ESCR_LEC 0x00FF0000U
3444 #define DCMI_ESCR_FEC 0xFF000000U
3445 
3446 /******************** Bits definition for DCMI_ESUR register ******************/
3447 #define DCMI_ESUR_FSU 0x000000FFU
3448 #define DCMI_ESUR_LSU 0x0000FF00U
3449 #define DCMI_ESUR_LEU 0x00FF0000U
3450 #define DCMI_ESUR_FEU 0xFF000000U
3451 
3452 /******************** Bits definition for DCMI_CWSTRT register ******************/
3453 #define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
3454 #define DCMI_CWSTRT_VST 0x1FFF0000U
3455 
3456 /******************** Bits definition for DCMI_CWSIZE register ******************/
3457 #define DCMI_CWSIZE_CAPCNT 0x00003FFFU
3458 #define DCMI_CWSIZE_VLINE 0x3FFF0000U
3459 
3460 /******************** Bits definition for DCMI_DR register ******************/
3461 #define DCMI_DR_BYTE0 0x000000FFU
3462 #define DCMI_DR_BYTE1 0x0000FF00U
3463 #define DCMI_DR_BYTE2 0x00FF0000U
3464 #define DCMI_DR_BYTE3 0xFF000000U
3465 
3466 /******************************************************************************/
3467 /* */
3468 /* DMA Controller */
3469 /* */
3470 /******************************************************************************/
3471 /******************** Bits definition for DMA_SxCR register *****************/
3472 #define DMA_SxCR_CHSEL 0x0E000000U
3473 #define DMA_SxCR_CHSEL_0 0x02000000U
3474 #define DMA_SxCR_CHSEL_1 0x04000000U
3475 #define DMA_SxCR_CHSEL_2 0x08000000U
3476 #define DMA_SxCR_MBURST 0x01800000U
3477 #define DMA_SxCR_MBURST_0 0x00800000U
3478 #define DMA_SxCR_MBURST_1 0x01000000U
3479 #define DMA_SxCR_PBURST 0x00600000U
3480 #define DMA_SxCR_PBURST_0 0x00200000U
3481 #define DMA_SxCR_PBURST_1 0x00400000U
3482 #define DMA_SxCR_CT 0x00080000U
3483 #define DMA_SxCR_DBM 0x00040000U
3484 #define DMA_SxCR_PL 0x00030000U
3485 #define DMA_SxCR_PL_0 0x00010000U
3486 #define DMA_SxCR_PL_1 0x00020000U
3487 #define DMA_SxCR_PINCOS 0x00008000U
3488 #define DMA_SxCR_MSIZE 0x00006000U
3489 #define DMA_SxCR_MSIZE_0 0x00002000U
3490 #define DMA_SxCR_MSIZE_1 0x00004000U
3491 #define DMA_SxCR_PSIZE 0x00001800U
3492 #define DMA_SxCR_PSIZE_0 0x00000800U
3493 #define DMA_SxCR_PSIZE_1 0x00001000U
3494 #define DMA_SxCR_MINC 0x00000400U
3495 #define DMA_SxCR_PINC 0x00000200U
3496 #define DMA_SxCR_CIRC 0x00000100U
3497 #define DMA_SxCR_DIR 0x000000C0U
3498 #define DMA_SxCR_DIR_0 0x00000040U
3499 #define DMA_SxCR_DIR_1 0x00000080U
3500 #define DMA_SxCR_PFCTRL 0x00000020U
3501 #define DMA_SxCR_TCIE 0x00000010U
3502 #define DMA_SxCR_HTIE 0x00000008U
3503 #define DMA_SxCR_TEIE 0x00000004U
3504 #define DMA_SxCR_DMEIE 0x00000002U
3505 #define DMA_SxCR_EN 0x00000001U
3506 
3507 /******************** Bits definition for DMA_SxCNDTR register **************/
3508 #define DMA_SxNDT 0x0000FFFFU
3509 #define DMA_SxNDT_0 0x00000001U
3510 #define DMA_SxNDT_1 0x00000002U
3511 #define DMA_SxNDT_2 0x00000004U
3512 #define DMA_SxNDT_3 0x00000008U
3513 #define DMA_SxNDT_4 0x00000010U
3514 #define DMA_SxNDT_5 0x00000020U
3515 #define DMA_SxNDT_6 0x00000040U
3516 #define DMA_SxNDT_7 0x00000080U
3517 #define DMA_SxNDT_8 0x00000100U
3518 #define DMA_SxNDT_9 0x00000200U
3519 #define DMA_SxNDT_10 0x00000400U
3520 #define DMA_SxNDT_11 0x00000800U
3521 #define DMA_SxNDT_12 0x00001000U
3522 #define DMA_SxNDT_13 0x00002000U
3523 #define DMA_SxNDT_14 0x00004000U
3524 #define DMA_SxNDT_15 0x00008000U
3525 
3526 /******************** Bits definition for DMA_SxFCR register ****************/
3527 #define DMA_SxFCR_FEIE 0x00000080U
3528 #define DMA_SxFCR_FS 0x00000038U
3529 #define DMA_SxFCR_FS_0 0x00000008U
3530 #define DMA_SxFCR_FS_1 0x00000010U
3531 #define DMA_SxFCR_FS_2 0x00000020U
3532 #define DMA_SxFCR_DMDIS 0x00000004U
3533 #define DMA_SxFCR_FTH 0x00000003U
3534 #define DMA_SxFCR_FTH_0 0x00000001U
3535 #define DMA_SxFCR_FTH_1 0x00000002U
3536 
3537 /******************** Bits definition for DMA_LISR register *****************/
3538 #define DMA_LISR_TCIF3 0x08000000U
3539 #define DMA_LISR_HTIF3 0x04000000U
3540 #define DMA_LISR_TEIF3 0x02000000U
3541 #define DMA_LISR_DMEIF3 0x01000000U
3542 #define DMA_LISR_FEIF3 0x00400000U
3543 #define DMA_LISR_TCIF2 0x00200000U
3544 #define DMA_LISR_HTIF2 0x00100000U
3545 #define DMA_LISR_TEIF2 0x00080000U
3546 #define DMA_LISR_DMEIF2 0x00040000U
3547 #define DMA_LISR_FEIF2 0x00010000U
3548 #define DMA_LISR_TCIF1 0x00000800U
3549 #define DMA_LISR_HTIF1 0x00000400U
3550 #define DMA_LISR_TEIF1 0x00000200U
3551 #define DMA_LISR_DMEIF1 0x00000100U
3552 #define DMA_LISR_FEIF1 0x00000040U
3553 #define DMA_LISR_TCIF0 0x00000020U
3554 #define DMA_LISR_HTIF0 0x00000010U
3555 #define DMA_LISR_TEIF0 0x00000008U
3556 #define DMA_LISR_DMEIF0 0x00000004U
3557 #define DMA_LISR_FEIF0 0x00000001U
3558 
3559 /******************** Bits definition for DMA_HISR register *****************/
3560 #define DMA_HISR_TCIF7 0x08000000U
3561 #define DMA_HISR_HTIF7 0x04000000U
3562 #define DMA_HISR_TEIF7 0x02000000U
3563 #define DMA_HISR_DMEIF7 0x01000000U
3564 #define DMA_HISR_FEIF7 0x00400000U
3565 #define DMA_HISR_TCIF6 0x00200000U
3566 #define DMA_HISR_HTIF6 0x00100000U
3567 #define DMA_HISR_TEIF6 0x00080000U
3568 #define DMA_HISR_DMEIF6 0x00040000U
3569 #define DMA_HISR_FEIF6 0x00010000U
3570 #define DMA_HISR_TCIF5 0x00000800U
3571 #define DMA_HISR_HTIF5 0x00000400U
3572 #define DMA_HISR_TEIF5 0x00000200U
3573 #define DMA_HISR_DMEIF5 0x00000100U
3574 #define DMA_HISR_FEIF5 0x00000040U
3575 #define DMA_HISR_TCIF4 0x00000020U
3576 #define DMA_HISR_HTIF4 0x00000010U
3577 #define DMA_HISR_TEIF4 0x00000008U
3578 #define DMA_HISR_DMEIF4 0x00000004U
3579 #define DMA_HISR_FEIF4 0x00000001U
3580 
3581 /******************** Bits definition for DMA_LIFCR register ****************/
3582 #define DMA_LIFCR_CTCIF3 0x08000000U
3583 #define DMA_LIFCR_CHTIF3 0x04000000U
3584 #define DMA_LIFCR_CTEIF3 0x02000000U
3585 #define DMA_LIFCR_CDMEIF3 0x01000000U
3586 #define DMA_LIFCR_CFEIF3 0x00400000U
3587 #define DMA_LIFCR_CTCIF2 0x00200000U
3588 #define DMA_LIFCR_CHTIF2 0x00100000U
3589 #define DMA_LIFCR_CTEIF2 0x00080000U
3590 #define DMA_LIFCR_CDMEIF2 0x00040000U
3591 #define DMA_LIFCR_CFEIF2 0x00010000U
3592 #define DMA_LIFCR_CTCIF1 0x00000800U
3593 #define DMA_LIFCR_CHTIF1 0x00000400U
3594 #define DMA_LIFCR_CTEIF1 0x00000200U
3595 #define DMA_LIFCR_CDMEIF1 0x00000100U
3596 #define DMA_LIFCR_CFEIF1 0x00000040U
3597 #define DMA_LIFCR_CTCIF0 0x00000020U
3598 #define DMA_LIFCR_CHTIF0 0x00000010U
3599 #define DMA_LIFCR_CTEIF0 0x00000008U
3600 #define DMA_LIFCR_CDMEIF0 0x00000004U
3601 #define DMA_LIFCR_CFEIF0 0x00000001U
3602 
3603 /******************** Bits definition for DMA_HIFCR register ****************/
3604 #define DMA_HIFCR_CTCIF7 0x08000000U
3605 #define DMA_HIFCR_CHTIF7 0x04000000U
3606 #define DMA_HIFCR_CTEIF7 0x02000000U
3607 #define DMA_HIFCR_CDMEIF7 0x01000000U
3608 #define DMA_HIFCR_CFEIF7 0x00400000U
3609 #define DMA_HIFCR_CTCIF6 0x00200000U
3610 #define DMA_HIFCR_CHTIF6 0x00100000U
3611 #define DMA_HIFCR_CTEIF6 0x00080000U
3612 #define DMA_HIFCR_CDMEIF6 0x00040000U
3613 #define DMA_HIFCR_CFEIF6 0x00010000U
3614 #define DMA_HIFCR_CTCIF5 0x00000800U
3615 #define DMA_HIFCR_CHTIF5 0x00000400U
3616 #define DMA_HIFCR_CTEIF5 0x00000200U
3617 #define DMA_HIFCR_CDMEIF5 0x00000100U
3618 #define DMA_HIFCR_CFEIF5 0x00000040U
3619 #define DMA_HIFCR_CTCIF4 0x00000020U
3620 #define DMA_HIFCR_CHTIF4 0x00000010U
3621 #define DMA_HIFCR_CTEIF4 0x00000008U
3622 #define DMA_HIFCR_CDMEIF4 0x00000004U
3623 #define DMA_HIFCR_CFEIF4 0x00000001U
3624 
3625 /******************************************************************************/
3626 /* */
3627 /* AHB Master DMA2D Controller (DMA2D) */
3628 /* */
3629 /******************************************************************************/
3630 
3631 /******************** Bit definition for DMA2D_CR register ******************/
3632 
3633 #define DMA2D_CR_START 0x00000001U
3634 #define DMA2D_CR_SUSP 0x00000002U
3635 #define DMA2D_CR_ABORT 0x00000004U
3636 #define DMA2D_CR_TEIE 0x00000100U
3637 #define DMA2D_CR_TCIE 0x00000200U
3638 #define DMA2D_CR_TWIE 0x00000400U
3639 #define DMA2D_CR_CAEIE 0x00000800U
3640 #define DMA2D_CR_CTCIE 0x00001000U
3641 #define DMA2D_CR_CEIE 0x00002000U
3642 #define DMA2D_CR_MODE 0x00030000U
3643 #define DMA2D_CR_MODE_0 0x00010000U
3644 #define DMA2D_CR_MODE_1 0x00020000U
3646 /******************** Bit definition for DMA2D_ISR register *****************/
3647 
3648 #define DMA2D_ISR_TEIF 0x00000001U
3649 #define DMA2D_ISR_TCIF 0x00000002U
3650 #define DMA2D_ISR_TWIF 0x00000004U
3651 #define DMA2D_ISR_CAEIF 0x00000008U
3652 #define DMA2D_ISR_CTCIF 0x00000010U
3653 #define DMA2D_ISR_CEIF 0x00000020U
3655 /******************** Bit definition for DMA2D_IFCR register ****************/
3656 
3657 #define DMA2D_IFCR_CTEIF 0x00000001U
3658 #define DMA2D_IFCR_CTCIF 0x00000002U
3659 #define DMA2D_IFCR_CTWIF 0x00000004U
3660 #define DMA2D_IFCR_CAECIF 0x00000008U
3661 #define DMA2D_IFCR_CCTCIF 0x00000010U
3662 #define DMA2D_IFCR_CCEIF 0x00000020U
3664 /* Legacy defines */
3665 #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF
3666 #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF
3667 #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF
3668 #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF
3669 #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF
3670 #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF
3672 /******************** Bit definition for DMA2D_FGMAR register ***************/
3673 
3674 #define DMA2D_FGMAR_MA 0xFFFFFFFFU
3676 /******************** Bit definition for DMA2D_FGOR register ****************/
3677 
3678 #define DMA2D_FGOR_LO 0x00003FFFU
3680 /******************** Bit definition for DMA2D_BGMAR register ***************/
3681 
3682 #define DMA2D_BGMAR_MA 0xFFFFFFFFU
3684 /******************** Bit definition for DMA2D_BGOR register ****************/
3685 
3686 #define DMA2D_BGOR_LO 0x00003FFFU
3688 /******************** Bit definition for DMA2D_FGPFCCR register *************/
3689 
3690 #define DMA2D_FGPFCCR_CM 0x0000000FU
3691 #define DMA2D_FGPFCCR_CM_0 0x00000001U
3692 #define DMA2D_FGPFCCR_CM_1 0x00000002U
3693 #define DMA2D_FGPFCCR_CM_2 0x00000004U
3694 #define DMA2D_FGPFCCR_CM_3 0x00000008U
3695 #define DMA2D_FGPFCCR_CCM 0x00000010U
3696 #define DMA2D_FGPFCCR_START 0x00000020U
3697 #define DMA2D_FGPFCCR_CS 0x0000FF00U
3698 #define DMA2D_FGPFCCR_AM 0x00030000U
3699 #define DMA2D_FGPFCCR_AM_0 0x00010000U
3700 #define DMA2D_FGPFCCR_AM_1 0x00020000U
3701 #define DMA2D_FGPFCCR_ALPHA 0xFF000000U
3703 /******************** Bit definition for DMA2D_FGCOLR register **************/
3704 
3705 #define DMA2D_FGCOLR_BLUE 0x000000FFU
3706 #define DMA2D_FGCOLR_GREEN 0x0000FF00U
3707 #define DMA2D_FGCOLR_RED 0x00FF0000U
3709 /******************** Bit definition for DMA2D_BGPFCCR register *************/
3710 
3711 #define DMA2D_BGPFCCR_CM 0x0000000FU
3712 #define DMA2D_BGPFCCR_CM_0 0x00000001U
3713 #define DMA2D_BGPFCCR_CM_1 0x00000002U
3714 #define DMA2D_BGPFCCR_CM_2 0x00000004U
3715 #define DMA2D_FGPFCCR_CM_3 0x00000008U
3716 #define DMA2D_BGPFCCR_CCM 0x00000010U
3717 #define DMA2D_BGPFCCR_START 0x00000020U
3718 #define DMA2D_BGPFCCR_CS 0x0000FF00U
3719 #define DMA2D_BGPFCCR_AM 0x00030000U
3720 #define DMA2D_BGPFCCR_AM_0 0x00010000U
3721 #define DMA2D_BGPFCCR_AM_1 0x00020000U
3722 #define DMA2D_BGPFCCR_ALPHA 0xFF000000U
3724 /******************** Bit definition for DMA2D_BGCOLR register **************/
3725 
3726 #define DMA2D_BGCOLR_BLUE 0x000000FFU
3727 #define DMA2D_BGCOLR_GREEN 0x0000FF00U
3728 #define DMA2D_BGCOLR_RED 0x00FF0000U
3730 /******************** Bit definition for DMA2D_FGCMAR register **************/
3731 
3732 #define DMA2D_FGCMAR_MA 0xFFFFFFFFU
3734 /******************** Bit definition for DMA2D_BGCMAR register **************/
3735 
3736 #define DMA2D_BGCMAR_MA 0xFFFFFFFFU
3738 /******************** Bit definition for DMA2D_OPFCCR register **************/
3739 
3740 #define DMA2D_OPFCCR_CM 0x00000007U
3741 #define DMA2D_OPFCCR_CM_0 0x00000001U
3742 #define DMA2D_OPFCCR_CM_1 0x00000002U
3743 #define DMA2D_OPFCCR_CM_2 0x00000004U
3745 /******************** Bit definition for DMA2D_OCOLR register ***************/
3746 
3749 #define DMA2D_OCOLR_BLUE_1 0x000000FFU
3750 #define DMA2D_OCOLR_GREEN_1 0x0000FF00U
3751 #define DMA2D_OCOLR_RED_1 0x00FF0000U
3752 #define DMA2D_OCOLR_ALPHA_1 0xFF000000U
3755 #define DMA2D_OCOLR_BLUE_2 0x0000001FU
3756 #define DMA2D_OCOLR_GREEN_2 0x000007E0U
3757 #define DMA2D_OCOLR_RED_2 0x0000F800U
3760 #define DMA2D_OCOLR_BLUE_3 0x0000001FU
3761 #define DMA2D_OCOLR_GREEN_3 0x000003E0U
3762 #define DMA2D_OCOLR_RED_3 0x00007C00U
3763 #define DMA2D_OCOLR_ALPHA_3 0x00008000U
3766 #define DMA2D_OCOLR_BLUE_4 0x0000000FU
3767 #define DMA2D_OCOLR_GREEN_4 0x000000F0U
3768 #define DMA2D_OCOLR_RED_4 0x00000F00U
3769 #define DMA2D_OCOLR_ALPHA_4 0x0000F000U
3771 /******************** Bit definition for DMA2D_OMAR register ****************/
3772 
3773 #define DMA2D_OMAR_MA 0xFFFFFFFFU
3775 /******************** Bit definition for DMA2D_OOR register *****************/
3776 
3777 #define DMA2D_OOR_LO 0x00003FFFU
3779 /******************** Bit definition for DMA2D_NLR register *****************/
3780 
3781 #define DMA2D_NLR_NL 0x0000FFFFU
3782 #define DMA2D_NLR_PL 0x3FFF0000U
3784 /******************** Bit definition for DMA2D_LWR register *****************/
3785 
3786 #define DMA2D_LWR_LW 0x0000FFFFU
3788 /******************** Bit definition for DMA2D_AMTCR register ***************/
3789 
3790 #define DMA2D_AMTCR_EN 0x00000001U
3791 #define DMA2D_AMTCR_DT 0x0000FF00U
3794 /******************** Bit definition for DMA2D_FGCLUT register **************/
3795 
3796 /******************** Bit definition for DMA2D_BGCLUT register **************/
3797 
3798 
3799 /******************************************************************************/
3800 /* */
3801 /* External Interrupt/Event Controller */
3802 /* */
3803 /******************************************************************************/
3804 /******************* Bit definition for EXTI_IMR register *******************/
3805 #define EXTI_IMR_MR0 0x00000001U
3806 #define EXTI_IMR_MR1 0x00000002U
3807 #define EXTI_IMR_MR2 0x00000004U
3808 #define EXTI_IMR_MR3 0x00000008U
3809 #define EXTI_IMR_MR4 0x00000010U
3810 #define EXTI_IMR_MR5 0x00000020U
3811 #define EXTI_IMR_MR6 0x00000040U
3812 #define EXTI_IMR_MR7 0x00000080U
3813 #define EXTI_IMR_MR8 0x00000100U
3814 #define EXTI_IMR_MR9 0x00000200U
3815 #define EXTI_IMR_MR10 0x00000400U
3816 #define EXTI_IMR_MR11 0x00000800U
3817 #define EXTI_IMR_MR12 0x00001000U
3818 #define EXTI_IMR_MR13 0x00002000U
3819 #define EXTI_IMR_MR14 0x00004000U
3820 #define EXTI_IMR_MR15 0x00008000U
3821 #define EXTI_IMR_MR16 0x00010000U
3822 #define EXTI_IMR_MR17 0x00020000U
3823 #define EXTI_IMR_MR18 0x00040000U
3824 #define EXTI_IMR_MR19 0x00080000U
3825 #define EXTI_IMR_MR20 0x00100000U
3826 #define EXTI_IMR_MR21 0x00200000U
3827 #define EXTI_IMR_MR22 0x00400000U
3828 #define EXTI_IMR_MR23 0x00800000U
3830 /* Reference Defines */
3831 #define EXTI_IMR_IM0 EXTI_IMR_MR0
3832 #define EXTI_IMR_IM1 EXTI_IMR_MR1
3833 #define EXTI_IMR_IM2 EXTI_IMR_MR2
3834 #define EXTI_IMR_IM3 EXTI_IMR_MR3
3835 #define EXTI_IMR_IM4 EXTI_IMR_MR4
3836 #define EXTI_IMR_IM5 EXTI_IMR_MR5
3837 #define EXTI_IMR_IM6 EXTI_IMR_MR6
3838 #define EXTI_IMR_IM7 EXTI_IMR_MR7
3839 #define EXTI_IMR_IM8 EXTI_IMR_MR8
3840 #define EXTI_IMR_IM9 EXTI_IMR_MR9
3841 #define EXTI_IMR_IM10 EXTI_IMR_MR10
3842 #define EXTI_IMR_IM11 EXTI_IMR_MR11
3843 #define EXTI_IMR_IM12 EXTI_IMR_MR12
3844 #define EXTI_IMR_IM13 EXTI_IMR_MR13
3845 #define EXTI_IMR_IM14 EXTI_IMR_MR14
3846 #define EXTI_IMR_IM15 EXTI_IMR_MR15
3847 #define EXTI_IMR_IM16 EXTI_IMR_MR16
3848 #define EXTI_IMR_IM17 EXTI_IMR_MR17
3849 #define EXTI_IMR_IM18 EXTI_IMR_MR18
3850 #define EXTI_IMR_IM19 EXTI_IMR_MR19
3851 #define EXTI_IMR_IM20 EXTI_IMR_MR20
3852 #define EXTI_IMR_IM21 EXTI_IMR_MR21
3853 #define EXTI_IMR_IM22 EXTI_IMR_MR22
3854 #define EXTI_IMR_IM23 EXTI_IMR_MR23
3855 
3856 #define EXTI_IMR_IM 0x00FFFFFFU
3858 /******************* Bit definition for EXTI_EMR register *******************/
3859 #define EXTI_EMR_MR0 0x00000001U
3860 #define EXTI_EMR_MR1 0x00000002U
3861 #define EXTI_EMR_MR2 0x00000004U
3862 #define EXTI_EMR_MR3 0x00000008U
3863 #define EXTI_EMR_MR4 0x00000010U
3864 #define EXTI_EMR_MR5 0x00000020U
3865 #define EXTI_EMR_MR6 0x00000040U
3866 #define EXTI_EMR_MR7 0x00000080U
3867 #define EXTI_EMR_MR8 0x00000100U
3868 #define EXTI_EMR_MR9 0x00000200U
3869 #define EXTI_EMR_MR10 0x00000400U
3870 #define EXTI_EMR_MR11 0x00000800U
3871 #define EXTI_EMR_MR12 0x00001000U
3872 #define EXTI_EMR_MR13 0x00002000U
3873 #define EXTI_EMR_MR14 0x00004000U
3874 #define EXTI_EMR_MR15 0x00008000U
3875 #define EXTI_EMR_MR16 0x00010000U
3876 #define EXTI_EMR_MR17 0x00020000U
3877 #define EXTI_EMR_MR18 0x00040000U
3878 #define EXTI_EMR_MR19 0x00080000U
3879 #define EXTI_EMR_MR20 0x00100000U
3880 #define EXTI_EMR_MR21 0x00200000U
3881 #define EXTI_EMR_MR22 0x00400000U
3882 #define EXTI_EMR_MR23 0x00800000U
3884 /* Reference Defines */
3885 #define EXTI_EMR_EM0 EXTI_EMR_MR0
3886 #define EXTI_EMR_EM1 EXTI_EMR_MR1
3887 #define EXTI_EMR_EM2 EXTI_EMR_MR2
3888 #define EXTI_EMR_EM3 EXTI_EMR_MR3
3889 #define EXTI_EMR_EM4 EXTI_EMR_MR4
3890 #define EXTI_EMR_EM5 EXTI_EMR_MR5
3891 #define EXTI_EMR_EM6 EXTI_EMR_MR6
3892 #define EXTI_EMR_EM7 EXTI_EMR_MR7
3893 #define EXTI_EMR_EM8 EXTI_EMR_MR8
3894 #define EXTI_EMR_EM9 EXTI_EMR_MR9
3895 #define EXTI_EMR_EM10 EXTI_EMR_MR10
3896 #define EXTI_EMR_EM11 EXTI_EMR_MR11
3897 #define EXTI_EMR_EM12 EXTI_EMR_MR12
3898 #define EXTI_EMR_EM13 EXTI_EMR_MR13
3899 #define EXTI_EMR_EM14 EXTI_EMR_MR14
3900 #define EXTI_EMR_EM15 EXTI_EMR_MR15
3901 #define EXTI_EMR_EM16 EXTI_EMR_MR16
3902 #define EXTI_EMR_EM17 EXTI_EMR_MR17
3903 #define EXTI_EMR_EM18 EXTI_EMR_MR18
3904 #define EXTI_EMR_EM19 EXTI_EMR_MR19
3905 #define EXTI_EMR_EM20 EXTI_EMR_MR20
3906 #define EXTI_EMR_EM21 EXTI_EMR_MR21
3907 #define EXTI_EMR_EM22 EXTI_EMR_MR22
3908 #define EXTI_EMR_EM23 EXTI_EMR_MR23
3909 
3910 
3911 /****************** Bit definition for EXTI_RTSR register *******************/
3912 #define EXTI_RTSR_TR0 0x00000001U
3913 #define EXTI_RTSR_TR1 0x00000002U
3914 #define EXTI_RTSR_TR2 0x00000004U
3915 #define EXTI_RTSR_TR3 0x00000008U
3916 #define EXTI_RTSR_TR4 0x00000010U
3917 #define EXTI_RTSR_TR5 0x00000020U
3918 #define EXTI_RTSR_TR6 0x00000040U
3919 #define EXTI_RTSR_TR7 0x00000080U
3920 #define EXTI_RTSR_TR8 0x00000100U
3921 #define EXTI_RTSR_TR9 0x00000200U
3922 #define EXTI_RTSR_TR10 0x00000400U
3923 #define EXTI_RTSR_TR11 0x00000800U
3924 #define EXTI_RTSR_TR12 0x00001000U
3925 #define EXTI_RTSR_TR13 0x00002000U
3926 #define EXTI_RTSR_TR14 0x00004000U
3927 #define EXTI_RTSR_TR15 0x00008000U
3928 #define EXTI_RTSR_TR16 0x00010000U
3929 #define EXTI_RTSR_TR17 0x00020000U
3930 #define EXTI_RTSR_TR18 0x00040000U
3931 #define EXTI_RTSR_TR19 0x00080000U
3932 #define EXTI_RTSR_TR20 0x00100000U
3933 #define EXTI_RTSR_TR21 0x00200000U
3934 #define EXTI_RTSR_TR22 0x00400000U
3935 #define EXTI_RTSR_TR23 0x00800000U
3937 /****************** Bit definition for EXTI_FTSR register *******************/
3938 #define EXTI_FTSR_TR0 0x00000001U
3939 #define EXTI_FTSR_TR1 0x00000002U
3940 #define EXTI_FTSR_TR2 0x00000004U
3941 #define EXTI_FTSR_TR3 0x00000008U
3942 #define EXTI_FTSR_TR4 0x00000010U
3943 #define EXTI_FTSR_TR5 0x00000020U
3944 #define EXTI_FTSR_TR6 0x00000040U
3945 #define EXTI_FTSR_TR7 0x00000080U
3946 #define EXTI_FTSR_TR8 0x00000100U
3947 #define EXTI_FTSR_TR9 0x00000200U
3948 #define EXTI_FTSR_TR10 0x00000400U
3949 #define EXTI_FTSR_TR11 0x00000800U
3950 #define EXTI_FTSR_TR12 0x00001000U
3951 #define EXTI_FTSR_TR13 0x00002000U
3952 #define EXTI_FTSR_TR14 0x00004000U
3953 #define EXTI_FTSR_TR15 0x00008000U
3954 #define EXTI_FTSR_TR16 0x00010000U
3955 #define EXTI_FTSR_TR17 0x00020000U
3956 #define EXTI_FTSR_TR18 0x00040000U
3957 #define EXTI_FTSR_TR19 0x00080000U
3958 #define EXTI_FTSR_TR20 0x00100000U
3959 #define EXTI_FTSR_TR21 0x00200000U
3960 #define EXTI_FTSR_TR22 0x00400000U
3961 #define EXTI_FTSR_TR23 0x00800000U
3963 /****************** Bit definition for EXTI_SWIER register ******************/
3964 #define EXTI_SWIER_SWIER0 0x00000001U
3965 #define EXTI_SWIER_SWIER1 0x00000002U
3966 #define EXTI_SWIER_SWIER2 0x00000004U
3967 #define EXTI_SWIER_SWIER3 0x00000008U
3968 #define EXTI_SWIER_SWIER4 0x00000010U
3969 #define EXTI_SWIER_SWIER5 0x00000020U
3970 #define EXTI_SWIER_SWIER6 0x00000040U
3971 #define EXTI_SWIER_SWIER7 0x00000080U
3972 #define EXTI_SWIER_SWIER8 0x00000100U
3973 #define EXTI_SWIER_SWIER9 0x00000200U
3974 #define EXTI_SWIER_SWIER10 0x00000400U
3975 #define EXTI_SWIER_SWIER11 0x00000800U
3976 #define EXTI_SWIER_SWIER12 0x00001000U
3977 #define EXTI_SWIER_SWIER13 0x00002000U
3978 #define EXTI_SWIER_SWIER14 0x00004000U
3979 #define EXTI_SWIER_SWIER15 0x00008000U
3980 #define EXTI_SWIER_SWIER16 0x00010000U
3981 #define EXTI_SWIER_SWIER17 0x00020000U
3982 #define EXTI_SWIER_SWIER18 0x00040000U
3983 #define EXTI_SWIER_SWIER19 0x00080000U
3984 #define EXTI_SWIER_SWIER20 0x00100000U
3985 #define EXTI_SWIER_SWIER21 0x00200000U
3986 #define EXTI_SWIER_SWIER22 0x00400000U
3987 #define EXTI_SWIER_SWIER23 0x00800000U
3989 /******************* Bit definition for EXTI_PR register ********************/
3990 #define EXTI_PR_PR0 0x00000001U
3991 #define EXTI_PR_PR1 0x00000002U
3992 #define EXTI_PR_PR2 0x00000004U
3993 #define EXTI_PR_PR3 0x00000008U
3994 #define EXTI_PR_PR4 0x00000010U
3995 #define EXTI_PR_PR5 0x00000020U
3996 #define EXTI_PR_PR6 0x00000040U
3997 #define EXTI_PR_PR7 0x00000080U
3998 #define EXTI_PR_PR8 0x00000100U
3999 #define EXTI_PR_PR9 0x00000200U
4000 #define EXTI_PR_PR10 0x00000400U
4001 #define EXTI_PR_PR11 0x00000800U
4002 #define EXTI_PR_PR12 0x00001000U
4003 #define EXTI_PR_PR13 0x00002000U
4004 #define EXTI_PR_PR14 0x00004000U
4005 #define EXTI_PR_PR15 0x00008000U
4006 #define EXTI_PR_PR16 0x00010000U
4007 #define EXTI_PR_PR17 0x00020000U
4008 #define EXTI_PR_PR18 0x00040000U
4009 #define EXTI_PR_PR19 0x00080000U
4010 #define EXTI_PR_PR20 0x00100000U
4011 #define EXTI_PR_PR21 0x00200000U
4012 #define EXTI_PR_PR22 0x00400000U
4013 #define EXTI_PR_PR23 0x00800000U
4015 /******************************************************************************/
4016 /* */
4017 /* FLASH */
4018 /* */
4019 /******************************************************************************/
4020 /*
4021 * @brief FLASH Total Sectors Number
4022 */
4023 #define FLASH_SECTOR_TOTAL 8
4024 
4025 /******************* Bits definition for FLASH_ACR register *****************/
4026 #define FLASH_ACR_LATENCY 0x0000000FU
4027 #define FLASH_ACR_LATENCY_0WS 0x00000000U
4028 #define FLASH_ACR_LATENCY_1WS 0x00000001U
4029 #define FLASH_ACR_LATENCY_2WS 0x00000002U
4030 #define FLASH_ACR_LATENCY_3WS 0x00000003U
4031 #define FLASH_ACR_LATENCY_4WS 0x00000004U
4032 #define FLASH_ACR_LATENCY_5WS 0x00000005U
4033 #define FLASH_ACR_LATENCY_6WS 0x00000006U
4034 #define FLASH_ACR_LATENCY_7WS 0x00000007U
4035 #define FLASH_ACR_LATENCY_8WS 0x00000008U
4036 #define FLASH_ACR_LATENCY_9WS 0x00000009U
4037 #define FLASH_ACR_LATENCY_10WS 0x0000000AU
4038 #define FLASH_ACR_LATENCY_11WS 0x0000000BU
4039 #define FLASH_ACR_LATENCY_12WS 0x0000000CU
4040 #define FLASH_ACR_LATENCY_13WS 0x0000000DU
4041 #define FLASH_ACR_LATENCY_14WS 0x0000000EU
4042 #define FLASH_ACR_LATENCY_15WS 0x0000000FU
4043 #define FLASH_ACR_PRFTEN 0x00000100U
4044 #define FLASH_ACR_ARTEN 0x00000200U
4045 #define FLASH_ACR_ARTRST 0x00000800U
4046 
4047 /******************* Bits definition for FLASH_SR register ******************/
4048 #define FLASH_SR_EOP 0x00000001U
4049 #define FLASH_SR_OPERR 0x00000002U
4050 #define FLASH_SR_WRPERR 0x00000010U
4051 #define FLASH_SR_PGAERR 0x00000020U
4052 #define FLASH_SR_PGPERR 0x00000040U
4053 #define FLASH_SR_ERSERR 0x00000080U
4054 #define FLASH_SR_BSY 0x00010000U
4055 
4056 /******************* Bits definition for FLASH_CR register ******************/
4057 #define FLASH_CR_PG 0x00000001U
4058 #define FLASH_CR_SER 0x00000002U
4059 #define FLASH_CR_MER 0x00000004U
4060 #define FLASH_CR_SNB 0x00000078U
4061 #define FLASH_CR_SNB_0 0x00000008U
4062 #define FLASH_CR_SNB_1 0x00000010U
4063 #define FLASH_CR_SNB_2 0x00000020U
4064 #define FLASH_CR_SNB_3 0x00000040U
4065 #define FLASH_CR_PSIZE 0x00000300U
4066 #define FLASH_CR_PSIZE_0 0x00000100U
4067 #define FLASH_CR_PSIZE_1 0x00000200U
4068 #define FLASH_CR_STRT 0x00010000U
4069 #define FLASH_CR_EOPIE 0x01000000U
4070 #define FLASH_CR_ERRIE 0x02000000U
4071 #define FLASH_CR_LOCK 0x80000000U
4072 
4073 /******************* Bits definition for FLASH_OPTCR register ***************/
4074 #define FLASH_OPTCR_OPTLOCK 0x00000001U
4075 #define FLASH_OPTCR_OPTSTRT 0x00000002U
4076 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
4077 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
4078 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
4079 #define FLASH_OPTCR_WWDG_SW 0x00000010U
4080 #define FLASH_OPTCR_IWDG_SW 0x00000020U
4081 #define FLASH_OPTCR_nRST_STOP 0x00000040U
4082 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
4083 #define FLASH_OPTCR_RDP 0x0000FF00U
4084 #define FLASH_OPTCR_RDP_0 0x00000100U
4085 #define FLASH_OPTCR_RDP_1 0x00000200U
4086 #define FLASH_OPTCR_RDP_2 0x00000400U
4087 #define FLASH_OPTCR_RDP_3 0x00000800U
4088 #define FLASH_OPTCR_RDP_4 0x00001000U
4089 #define FLASH_OPTCR_RDP_5 0x00002000U
4090 #define FLASH_OPTCR_RDP_6 0x00004000U
4091 #define FLASH_OPTCR_RDP_7 0x00008000U
4092 #define FLASH_OPTCR_nWRP 0x00FF0000U
4093 #define FLASH_OPTCR_nWRP_0 0x00010000U
4094 #define FLASH_OPTCR_nWRP_1 0x00020000U
4095 #define FLASH_OPTCR_nWRP_2 0x00040000U
4096 #define FLASH_OPTCR_nWRP_3 0x00080000U
4097 #define FLASH_OPTCR_nWRP_4 0x00100000U
4098 #define FLASH_OPTCR_nWRP_5 0x00200000U
4099 #define FLASH_OPTCR_nWRP_6 0x00400000U
4100 #define FLASH_OPTCR_nWRP_7 0x00800000U
4101 #define FLASH_OPTCR_IWDG_STDBY 0x40000000U
4102 #define FLASH_OPTCR_IWDG_STOP 0x80000000U
4103 
4104 /******************* Bits definition for FLASH_OPTCR1 register ***************/
4105 #define FLASH_OPTCR1_BOOT_ADD0 0x0000FFFFU
4106 #define FLASH_OPTCR1_BOOT_ADD1 0xFFFF0000U
4107 
4108 /******************************************************************************/
4109 /* */
4110 /* Flexible Memory Controller */
4111 /* */
4112 /******************************************************************************/
4113 /****************** Bit definition for FMC_BCR1 register *******************/
4114 #define FMC_BCR1_MBKEN 0x00000001U
4115 #define FMC_BCR1_MUXEN 0x00000002U
4116 #define FMC_BCR1_MTYP 0x0000000CU
4117 #define FMC_BCR1_MTYP_0 0x00000004U
4118 #define FMC_BCR1_MTYP_1 0x00000008U
4119 #define FMC_BCR1_MWID 0x00000030U
4120 #define FMC_BCR1_MWID_0 0x00000010U
4121 #define FMC_BCR1_MWID_1 0x00000020U
4122 #define FMC_BCR1_FACCEN 0x00000040U
4123 #define FMC_BCR1_BURSTEN 0x00000100U
4124 #define FMC_BCR1_WAITPOL 0x00000200U
4125 #define FMC_BCR1_WRAPMOD 0x00000400U
4126 #define FMC_BCR1_WAITCFG 0x00000800U
4127 #define FMC_BCR1_WREN 0x00001000U
4128 #define FMC_BCR1_WAITEN 0x00002000U
4129 #define FMC_BCR1_EXTMOD 0x00004000U
4130 #define FMC_BCR1_ASYNCWAIT 0x00008000U
4131 #define FMC_BCR1_CPSIZE 0x00070000U
4132 #define FMC_BCR1_CPSIZE_0 0x00010000U
4133 #define FMC_BCR1_CPSIZE_1 0x00020000U
4134 #define FMC_BCR1_CPSIZE_2 0x00040000U
4135 #define FMC_BCR1_CBURSTRW 0x00080000U
4136 #define FMC_BCR1_CCLKEN 0x00100000U
4137 #define FMC_BCR1_WFDIS 0x00200000U
4139 /****************** Bit definition for FMC_BCR2 register *******************/
4140 #define FMC_BCR2_MBKEN 0x00000001U
4141 #define FMC_BCR2_MUXEN 0x00000002U
4142 #define FMC_BCR2_MTYP 0x0000000CU
4143 #define FMC_BCR2_MTYP_0 0x00000004U
4144 #define FMC_BCR2_MTYP_1 0x00000008U
4145 #define FMC_BCR2_MWID 0x00000030U
4146 #define FMC_BCR2_MWID_0 0x00000010U
4147 #define FMC_BCR2_MWID_1 0x00000020U
4148 #define FMC_BCR2_FACCEN 0x00000040U
4149 #define FMC_BCR2_BURSTEN 0x00000100U
4150 #define FMC_BCR2_WAITPOL 0x00000200U
4151 #define FMC_BCR2_WRAPMOD 0x00000400U
4152 #define FMC_BCR2_WAITCFG 0x00000800U
4153 #define FMC_BCR2_WREN 0x00001000U
4154 #define FMC_BCR2_WAITEN 0x00002000U
4155 #define FMC_BCR2_EXTMOD 0x00004000U
4156 #define FMC_BCR2_ASYNCWAIT 0x00008000U
4157 #define FMC_BCR2_CPSIZE 0x00070000U
4158 #define FMC_BCR2_CPSIZE_0 0x00010000U
4159 #define FMC_BCR2_CPSIZE_1 0x00020000U
4160 #define FMC_BCR2_CPSIZE_2 0x00040000U
4161 #define FMC_BCR2_CBURSTRW 0x00080000U
4163 /****************** Bit definition for FMC_BCR3 register *******************/
4164 #define FMC_BCR3_MBKEN 0x00000001U
4165 #define FMC_BCR3_MUXEN 0x00000002U
4166 #define FMC_BCR3_MTYP 0x0000000CU
4167 #define FMC_BCR3_MTYP_0 0x00000004U
4168 #define FMC_BCR3_MTYP_1 0x00000008U
4169 #define FMC_BCR3_MWID 0x00000030U
4170 #define FMC_BCR3_MWID_0 0x00000010U
4171 #define FMC_BCR3_MWID_1 0x00000020U
4172 #define FMC_BCR3_FACCEN 0x00000040U
4173 #define FMC_BCR3_BURSTEN 0x00000100U
4174 #define FMC_BCR3_WAITPOL 0x00000200U
4175 #define FMC_BCR3_WRAPMOD 0x00000400U
4176 #define FMC_BCR3_WAITCFG 0x00000800U
4177 #define FMC_BCR3_WREN 0x00001000U
4178 #define FMC_BCR3_WAITEN 0x00002000U
4179 #define FMC_BCR3_EXTMOD 0x00004000U
4180 #define FMC_BCR3_ASYNCWAIT 0x00008000U
4181 #define FMC_BCR3_CPSIZE 0x00070000U
4182 #define FMC_BCR3_CPSIZE_0 0x00010000U
4183 #define FMC_BCR3_CPSIZE_1 0x00020000U
4184 #define FMC_BCR3_CPSIZE_2 0x00040000U
4185 #define FMC_BCR3_CBURSTRW 0x00080000U
4187 /****************** Bit definition for FMC_BCR4 register *******************/
4188 #define FMC_BCR4_MBKEN 0x00000001U
4189 #define FMC_BCR4_MUXEN 0x00000002U
4190 #define FMC_BCR4_MTYP 0x0000000CU
4191 #define FMC_BCR4_MTYP_0 0x00000004U
4192 #define FMC_BCR4_MTYP_1 0x00000008U
4193 #define FMC_BCR4_MWID 0x00000030U
4194 #define FMC_BCR4_MWID_0 0x00000010U
4195 #define FMC_BCR4_MWID_1 0x00000020U
4196 #define FMC_BCR4_FACCEN 0x00000040U
4197 #define FMC_BCR4_BURSTEN 0x00000100U
4198 #define FMC_BCR4_WAITPOL 0x00000200U
4199 #define FMC_BCR4_WRAPMOD 0x00000400U
4200 #define FMC_BCR4_WAITCFG 0x00000800U
4201 #define FMC_BCR4_WREN 0x00001000U
4202 #define FMC_BCR4_WAITEN 0x00002000U
4203 #define FMC_BCR4_EXTMOD 0x00004000U
4204 #define FMC_BCR4_ASYNCWAIT 0x00008000U
4205 #define FMC_BCR4_CPSIZE 0x00070000U
4206 #define FMC_BCR4_CPSIZE_0 0x00010000U
4207 #define FMC_BCR4_CPSIZE_1 0x00020000U
4208 #define FMC_BCR4_CPSIZE_2 0x00040000U
4209 #define FMC_BCR4_CBURSTRW 0x00080000U
4211 /****************** Bit definition for FMC_BTR1 register ******************/
4212 #define FMC_BTR1_ADDSET 0x0000000FU
4213 #define FMC_BTR1_ADDSET_0 0x00000001U
4214 #define FMC_BTR1_ADDSET_1 0x00000002U
4215 #define FMC_BTR1_ADDSET_2 0x00000004U
4216 #define FMC_BTR1_ADDSET_3 0x00000008U
4217 #define FMC_BTR1_ADDHLD 0x000000F0U
4218 #define FMC_BTR1_ADDHLD_0 0x00000010U
4219 #define FMC_BTR1_ADDHLD_1 0x00000020U
4220 #define FMC_BTR1_ADDHLD_2 0x00000040U
4221 #define FMC_BTR1_ADDHLD_3 0x00000080U
4222 #define FMC_BTR1_DATAST 0x0000FF00U
4223 #define FMC_BTR1_DATAST_0 0x00000100U
4224 #define FMC_BTR1_DATAST_1 0x00000200U
4225 #define FMC_BTR1_DATAST_2 0x00000400U
4226 #define FMC_BTR1_DATAST_3 0x00000800U
4227 #define FMC_BTR1_DATAST_4 0x00001000U
4228 #define FMC_BTR1_DATAST_5 0x00002000U
4229 #define FMC_BTR1_DATAST_6 0x00004000U
4230 #define FMC_BTR1_DATAST_7 0x00008000U
4231 #define FMC_BTR1_BUSTURN 0x000F0000U
4232 #define FMC_BTR1_BUSTURN_0 0x00010000U
4233 #define FMC_BTR1_BUSTURN_1 0x00020000U
4234 #define FMC_BTR1_BUSTURN_2 0x00040000U
4235 #define FMC_BTR1_BUSTURN_3 0x00080000U
4236 #define FMC_BTR1_CLKDIV 0x00F00000U
4237 #define FMC_BTR1_CLKDIV_0 0x00100000U
4238 #define FMC_BTR1_CLKDIV_1 0x00200000U
4239 #define FMC_BTR1_CLKDIV_2 0x00400000U
4240 #define FMC_BTR1_CLKDIV_3 0x00800000U
4241 #define FMC_BTR1_DATLAT 0x0F000000U
4242 #define FMC_BTR1_DATLAT_0 0x01000000U
4243 #define FMC_BTR1_DATLAT_1 0x02000000U
4244 #define FMC_BTR1_DATLAT_2 0x04000000U
4245 #define FMC_BTR1_DATLAT_3 0x08000000U
4246 #define FMC_BTR1_ACCMOD 0x30000000U
4247 #define FMC_BTR1_ACCMOD_0 0x10000000U
4248 #define FMC_BTR1_ACCMOD_1 0x20000000U
4250 /****************** Bit definition for FMC_BTR2 register *******************/
4251 #define FMC_BTR2_ADDSET 0x0000000FU
4252 #define FMC_BTR2_ADDSET_0 0x00000001U
4253 #define FMC_BTR2_ADDSET_1 0x00000002U
4254 #define FMC_BTR2_ADDSET_2 0x00000004U
4255 #define FMC_BTR2_ADDSET_3 0x00000008U
4256 #define FMC_BTR2_ADDHLD 0x000000F0U
4257 #define FMC_BTR2_ADDHLD_0 0x00000010U
4258 #define FMC_BTR2_ADDHLD_1 0x00000020U
4259 #define FMC_BTR2_ADDHLD_2 0x00000040U
4260 #define FMC_BTR2_ADDHLD_3 0x00000080U
4261 #define FMC_BTR2_DATAST 0x0000FF00U
4262 #define FMC_BTR2_DATAST_0 0x00000100U
4263 #define FMC_BTR2_DATAST_1 0x00000200U
4264 #define FMC_BTR2_DATAST_2 0x00000400U
4265 #define FMC_BTR2_DATAST_3 0x00000800U
4266 #define FMC_BTR2_DATAST_4 0x00001000U
4267 #define FMC_BTR2_DATAST_5 0x00002000U
4268 #define FMC_BTR2_DATAST_6 0x00004000U
4269 #define FMC_BTR2_DATAST_7 0x00008000U
4270 #define FMC_BTR2_BUSTURN 0x000F0000U
4271 #define FMC_BTR2_BUSTURN_0 0x00010000U
4272 #define FMC_BTR2_BUSTURN_1 0x00020000U
4273 #define FMC_BTR2_BUSTURN_2 0x00040000U
4274 #define FMC_BTR2_BUSTURN_3 0x00080000U
4275 #define FMC_BTR2_CLKDIV 0x00F00000U
4276 #define FMC_BTR2_CLKDIV_0 0x00100000U
4277 #define FMC_BTR2_CLKDIV_1 0x00200000U
4278 #define FMC_BTR2_CLKDIV_2 0x00400000U
4279 #define FMC_BTR2_CLKDIV_3 0x00800000U
4280 #define FMC_BTR2_DATLAT 0x0F000000U
4281 #define FMC_BTR2_DATLAT_0 0x01000000U
4282 #define FMC_BTR2_DATLAT_1 0x02000000U
4283 #define FMC_BTR2_DATLAT_2 0x04000000U
4284 #define FMC_BTR2_DATLAT_3 0x08000000U
4285 #define FMC_BTR2_ACCMOD 0x30000000U
4286 #define FMC_BTR2_ACCMOD_0 0x10000000U
4287 #define FMC_BTR2_ACCMOD_1 0x20000000U
4289 /******************* Bit definition for FMC_BTR3 register *******************/
4290 #define FMC_BTR3_ADDSET 0x0000000FU
4291 #define FMC_BTR3_ADDSET_0 0x00000001U
4292 #define FMC_BTR3_ADDSET_1 0x00000002U
4293 #define FMC_BTR3_ADDSET_2 0x00000004U
4294 #define FMC_BTR3_ADDSET_3 0x00000008U
4295 #define FMC_BTR3_ADDHLD 0x000000F0U
4296 #define FMC_BTR3_ADDHLD_0 0x00000010U
4297 #define FMC_BTR3_ADDHLD_1 0x00000020U
4298 #define FMC_BTR3_ADDHLD_2 0x00000040U
4299 #define FMC_BTR3_ADDHLD_3 0x00000080U
4300 #define FMC_BTR3_DATAST 0x0000FF00U
4301 #define FMC_BTR3_DATAST_0 0x00000100U
4302 #define FMC_BTR3_DATAST_1 0x00000200U
4303 #define FMC_BTR3_DATAST_2 0x00000400U
4304 #define FMC_BTR3_DATAST_3 0x00000800U
4305 #define FMC_BTR3_DATAST_4 0x00001000U
4306 #define FMC_BTR3_DATAST_5 0x00002000U
4307 #define FMC_BTR3_DATAST_6 0x00004000U
4308 #define FMC_BTR3_DATAST_7 0x00008000U
4309 #define FMC_BTR3_BUSTURN 0x000F0000U
4310 #define FMC_BTR3_BUSTURN_0 0x00010000U
4311 #define FMC_BTR3_BUSTURN_1 0x00020000U
4312 #define FMC_BTR3_BUSTURN_2 0x00040000U
4313 #define FMC_BTR3_BUSTURN_3 0x00080000U
4314 #define FMC_BTR3_CLKDIV 0x00F00000U
4315 #define FMC_BTR3_CLKDIV_0 0x00100000U
4316 #define FMC_BTR3_CLKDIV_1 0x00200000U
4317 #define FMC_BTR3_CLKDIV_2 0x00400000U
4318 #define FMC_BTR3_CLKDIV_3 0x00800000U
4319 #define FMC_BTR3_DATLAT 0x0F000000U
4320 #define FMC_BTR3_DATLAT_0 0x01000000U
4321 #define FMC_BTR3_DATLAT_1 0x02000000U
4322 #define FMC_BTR3_DATLAT_2 0x04000000U
4323 #define FMC_BTR3_DATLAT_3 0x08000000U
4324 #define FMC_BTR3_ACCMOD 0x30000000U
4325 #define FMC_BTR3_ACCMOD_0 0x10000000U
4326 #define FMC_BTR3_ACCMOD_1 0x20000000U
4328 /****************** Bit definition for FMC_BTR4 register *******************/
4329 #define FMC_BTR4_ADDSET 0x0000000FU
4330 #define FMC_BTR4_ADDSET_0 0x00000001U
4331 #define FMC_BTR4_ADDSET_1 0x00000002U
4332 #define FMC_BTR4_ADDSET_2 0x00000004U
4333 #define FMC_BTR4_ADDSET_3 0x00000008U
4334 #define FMC_BTR4_ADDHLD 0x000000F0U
4335 #define FMC_BTR4_ADDHLD_0 0x00000010U
4336 #define FMC_BTR4_ADDHLD_1 0x00000020U
4337 #define FMC_BTR4_ADDHLD_2 0x00000040U
4338 #define FMC_BTR4_ADDHLD_3 0x00000080U
4339 #define FMC_BTR4_DATAST 0x0000FF00U
4340 #define FMC_BTR4_DATAST_0 0x00000100U
4341 #define FMC_BTR4_DATAST_1 0x00000200U
4342 #define FMC_BTR4_DATAST_2 0x00000400U
4343 #define FMC_BTR4_DATAST_3 0x00000800U
4344 #define FMC_BTR4_DATAST_4 0x00001000U
4345 #define FMC_BTR4_DATAST_5 0x00002000U
4346 #define FMC_BTR4_DATAST_6 0x00004000U
4347 #define FMC_BTR4_DATAST_7 0x00008000U
4348 #define FMC_BTR4_BUSTURN 0x000F0000U
4349 #define FMC_BTR4_BUSTURN_0 0x00010000U
4350 #define FMC_BTR4_BUSTURN_1 0x00020000U
4351 #define FMC_BTR4_BUSTURN_2 0x00040000U
4352 #define FMC_BTR4_BUSTURN_3 0x00080000U
4353 #define FMC_BTR4_CLKDIV 0x00F00000U
4354 #define FMC_BTR4_CLKDIV_0 0x00100000U
4355 #define FMC_BTR4_CLKDIV_1 0x00200000U
4356 #define FMC_BTR4_CLKDIV_2 0x00400000U
4357 #define FMC_BTR4_CLKDIV_3 0x00800000U
4358 #define FMC_BTR4_DATLAT 0x0F000000U
4359 #define FMC_BTR4_DATLAT_0 0x01000000U
4360 #define FMC_BTR4_DATLAT_1 0x02000000U
4361 #define FMC_BTR4_DATLAT_2 0x04000000U
4362 #define FMC_BTR4_DATLAT_3 0x08000000U
4363 #define FMC_BTR4_ACCMOD 0x30000000U
4364 #define FMC_BTR4_ACCMOD_0 0x10000000U
4365 #define FMC_BTR4_ACCMOD_1 0x20000000U
4367 /****************** Bit definition for FMC_BWTR1 register ******************/
4368 #define FMC_BWTR1_ADDSET 0x0000000FU
4369 #define FMC_BWTR1_ADDSET_0 0x00000001U
4370 #define FMC_BWTR1_ADDSET_1 0x00000002U
4371 #define FMC_BWTR1_ADDSET_2 0x00000004U
4372 #define FMC_BWTR1_ADDSET_3 0x00000008U
4373 #define FMC_BWTR1_ADDHLD 0x000000F0U
4374 #define FMC_BWTR1_ADDHLD_0 0x00000010U
4375 #define FMC_BWTR1_ADDHLD_1 0x00000020U
4376 #define FMC_BWTR1_ADDHLD_2 0x00000040U
4377 #define FMC_BWTR1_ADDHLD_3 0x00000080U
4378 #define FMC_BWTR1_DATAST 0x0000FF00U
4379 #define FMC_BWTR1_DATAST_0 0x00000100U
4380 #define FMC_BWTR1_DATAST_1 0x00000200U
4381 #define FMC_BWTR1_DATAST_2 0x00000400U
4382 #define FMC_BWTR1_DATAST_3 0x00000800U
4383 #define FMC_BWTR1_DATAST_4 0x00001000U
4384 #define FMC_BWTR1_DATAST_5 0x00002000U
4385 #define FMC_BWTR1_DATAST_6 0x00004000U
4386 #define FMC_BWTR1_DATAST_7 0x00008000U
4387 #define FMC_BWTR1_BUSTURN 0x000F0000U
4388 #define FMC_BWTR1_BUSTURN_0 0x00010000U
4389 #define FMC_BWTR1_BUSTURN_1 0x00020000U
4390 #define FMC_BWTR1_BUSTURN_2 0x00040000U
4391 #define FMC_BWTR1_BUSTURN_3 0x00080000U
4392 #define FMC_BWTR1_ACCMOD 0x30000000U
4393 #define FMC_BWTR1_ACCMOD_0 0x10000000U
4394 #define FMC_BWTR1_ACCMOD_1 0x20000000U
4396 /****************** Bit definition for FMC_BWTR2 register ******************/
4397 #define FMC_BWTR2_ADDSET 0x0000000FU
4398 #define FMC_BWTR2_ADDSET_0 0x00000001U
4399 #define FMC_BWTR2_ADDSET_1 0x00000002U
4400 #define FMC_BWTR2_ADDSET_2 0x00000004U
4401 #define FMC_BWTR2_ADDSET_3 0x00000008U
4402 #define FMC_BWTR2_ADDHLD 0x000000F0U
4403 #define FMC_BWTR2_ADDHLD_0 0x00000010U
4404 #define FMC_BWTR2_ADDHLD_1 0x00000020U
4405 #define FMC_BWTR2_ADDHLD_2 0x00000040U
4406 #define FMC_BWTR2_ADDHLD_3 0x00000080U
4407 #define FMC_BWTR2_DATAST 0x0000FF00U
4408 #define FMC_BWTR2_DATAST_0 0x00000100U
4409 #define FMC_BWTR2_DATAST_1 0x00000200U
4410 #define FMC_BWTR2_DATAST_2 0x00000400U
4411 #define FMC_BWTR2_DATAST_3 0x00000800U
4412 #define FMC_BWTR2_DATAST_4 0x00001000U
4413 #define FMC_BWTR2_DATAST_5 0x00002000U
4414 #define FMC_BWTR2_DATAST_6 0x00004000U
4415 #define FMC_BWTR2_DATAST_7 0x00008000U
4416 #define FMC_BWTR2_BUSTURN 0x000F0000U
4417 #define FMC_BWTR2_BUSTURN_0 0x00010000U
4418 #define FMC_BWTR2_BUSTURN_1 0x00020000U
4419 #define FMC_BWTR2_BUSTURN_2 0x00040000U
4420 #define FMC_BWTR2_BUSTURN_3 0x00080000U
4421 #define FMC_BWTR2_ACCMOD 0x30000000U
4422 #define FMC_BWTR2_ACCMOD_0 0x10000000U
4423 #define FMC_BWTR2_ACCMOD_1 0x20000000U
4425 /****************** Bit definition for FMC_BWTR3 register ******************/
4426 #define FMC_BWTR3_ADDSET 0x0000000FU
4427 #define FMC_BWTR3_ADDSET_0 0x00000001U
4428 #define FMC_BWTR3_ADDSET_1 0x00000002U
4429 #define FMC_BWTR3_ADDSET_2 0x00000004U
4430 #define FMC_BWTR3_ADDSET_3 0x00000008U
4431 #define FMC_BWTR3_ADDHLD 0x000000F0U
4432 #define FMC_BWTR3_ADDHLD_0 0x00000010U
4433 #define FMC_BWTR3_ADDHLD_1 0x00000020U
4434 #define FMC_BWTR3_ADDHLD_2 0x00000040U
4435 #define FMC_BWTR3_ADDHLD_3 0x00000080U
4436 #define FMC_BWTR3_DATAST 0x0000FF00U
4437 #define FMC_BWTR3_DATAST_0 0x00000100U
4438 #define FMC_BWTR3_DATAST_1 0x00000200U
4439 #define FMC_BWTR3_DATAST_2 0x00000400U
4440 #define FMC_BWTR3_DATAST_3 0x00000800U
4441 #define FMC_BWTR3_DATAST_4 0x00001000U
4442 #define FMC_BWTR3_DATAST_5 0x00002000U
4443 #define FMC_BWTR3_DATAST_6 0x00004000U
4444 #define FMC_BWTR3_DATAST_7 0x00008000U
4445 #define FMC_BWTR3_BUSTURN 0x000F0000U
4446 #define FMC_BWTR3_BUSTURN_0 0x00010000U
4447 #define FMC_BWTR3_BUSTURN_1 0x00020000U
4448 #define FMC_BWTR3_BUSTURN_2 0x00040000U
4449 #define FMC_BWTR3_BUSTURN_3 0x00080000U
4450 #define FMC_BWTR3_ACCMOD 0x30000000U
4451 #define FMC_BWTR3_ACCMOD_0 0x10000000U
4452 #define FMC_BWTR3_ACCMOD_1 0x20000000U
4454 /****************** Bit definition for FMC_BWTR4 register ******************/
4455 #define FMC_BWTR4_ADDSET 0x0000000FU
4456 #define FMC_BWTR4_ADDSET_0 0x00000001U
4457 #define FMC_BWTR4_ADDSET_1 0x00000002U
4458 #define FMC_BWTR4_ADDSET_2 0x00000004U
4459 #define FMC_BWTR4_ADDSET_3 0x00000008U
4460 #define FMC_BWTR4_ADDHLD 0x000000F0U
4461 #define FMC_BWTR4_ADDHLD_0 0x00000010U
4462 #define FMC_BWTR4_ADDHLD_1 0x00000020U
4463 #define FMC_BWTR4_ADDHLD_2 0x00000040U
4464 #define FMC_BWTR4_ADDHLD_3 0x00000080U
4465 #define FMC_BWTR4_DATAST 0x0000FF00U
4466 #define FMC_BWTR4_DATAST_0 0x00000100U
4467 #define FMC_BWTR4_DATAST_1 0x00000200U
4468 #define FMC_BWTR4_DATAST_2 0x00000400U
4469 #define FMC_BWTR4_DATAST_3 0x00000800U
4470 #define FMC_BWTR4_DATAST_4 0x00001000U
4471 #define FMC_BWTR4_DATAST_5 0x00002000U
4472 #define FMC_BWTR4_DATAST_6 0x00004000U
4473 #define FMC_BWTR4_DATAST_7 0x00008000U
4474 #define FMC_BWTR4_BUSTURN 0x000F0000U
4475 #define FMC_BWTR4_BUSTURN_0 0x00010000U
4476 #define FMC_BWTR4_BUSTURN_1 0x00020000U
4477 #define FMC_BWTR4_BUSTURN_2 0x00040000U
4478 #define FMC_BWTR4_BUSTURN_3 0x00080000U
4479 #define FMC_BWTR4_ACCMOD 0x30000000U
4480 #define FMC_BWTR4_ACCMOD_0 0x10000000U
4481 #define FMC_BWTR4_ACCMOD_1 0x20000000U
4483 /****************** Bit definition for FMC_PCR register *******************/
4484 #define FMC_PCR_PWAITEN 0x00000002U
4485 #define FMC_PCR_PBKEN 0x00000004U
4486 #define FMC_PCR_PTYP 0x00000008U
4487 #define FMC_PCR_PWID 0x00000030U
4488 #define FMC_PCR_PWID_0 0x00000010U
4489 #define FMC_PCR_PWID_1 0x00000020U
4490 #define FMC_PCR_ECCEN 0x00000040U
4491 #define FMC_PCR_TCLR 0x00001E00U
4492 #define FMC_PCR_TCLR_0 0x00000200U
4493 #define FMC_PCR_TCLR_1 0x00000400U
4494 #define FMC_PCR_TCLR_2 0x00000800U
4495 #define FMC_PCR_TCLR_3 0x00001000U
4496 #define FMC_PCR_TAR 0x0001E000U
4497 #define FMC_PCR_TAR_0 0x00002000U
4498 #define FMC_PCR_TAR_1 0x00004000U
4499 #define FMC_PCR_TAR_2 0x00008000U
4500 #define FMC_PCR_TAR_3 0x00010000U
4501 #define FMC_PCR_ECCPS 0x000E0000U
4502 #define FMC_PCR_ECCPS_0 0x00020000U
4503 #define FMC_PCR_ECCPS_1 0x00040000U
4504 #define FMC_PCR_ECCPS_2 0x00080000U
4506 /******************* Bit definition for FMC_SR register *******************/
4507 #define FMC_SR_IRS 0x01U
4508 #define FMC_SR_ILS 0x02U
4509 #define FMC_SR_IFS 0x04U
4510 #define FMC_SR_IREN 0x08U
4511 #define FMC_SR_ILEN 0x10U
4512 #define FMC_SR_IFEN 0x20U
4513 #define FMC_SR_FEMPT 0x40U
4515 /****************** Bit definition for FMC_PMEM register ******************/
4516 #define FMC_PMEM_MEMSET3 0x000000FFU
4517 #define FMC_PMEM_MEMSET3_0 0x00000001U
4518 #define FMC_PMEM_MEMSET3_1 0x00000002U
4519 #define FMC_PMEM_MEMSET3_2 0x00000004U
4520 #define FMC_PMEM_MEMSET3_3 0x00000008U
4521 #define FMC_PMEM_MEMSET3_4 0x00000010U
4522 #define FMC_PMEM_MEMSET3_5 0x00000020U
4523 #define FMC_PMEM_MEMSET3_6 0x00000040U
4524 #define FMC_PMEM_MEMSET3_7 0x00000080U
4525 #define FMC_PMEM_MEMWAIT3 0x0000FF00U
4526 #define FMC_PMEM_MEMWAIT3_0 0x00000100U
4527 #define FMC_PMEM_MEMWAIT3_1 0x00000200U
4528 #define FMC_PMEM_MEMWAIT3_2 0x00000400U
4529 #define FMC_PMEM_MEMWAIT3_3 0x00000800U
4530 #define FMC_PMEM_MEMWAIT3_4 0x00001000U
4531 #define FMC_PMEM_MEMWAIT3_5 0x00002000U
4532 #define FMC_PMEM_MEMWAIT3_6 0x00004000U
4533 #define FMC_PMEM_MEMWAIT3_7 0x00008000U
4534 #define FMC_PMEM_MEMHOLD3 0x00FF0000U
4535 #define FMC_PMEM_MEMHOLD3_0 0x00010000U
4536 #define FMC_PMEM_MEMHOLD3_1 0x00020000U
4537 #define FMC_PMEM_MEMHOLD3_2 0x00040000U
4538 #define FMC_PMEM_MEMHOLD3_3 0x00080000U
4539 #define FMC_PMEM_MEMHOLD3_4 0x00100000U
4540 #define FMC_PMEM_MEMHOLD3_5 0x00200000U
4541 #define FMC_PMEM_MEMHOLD3_6 0x00400000U
4542 #define FMC_PMEM_MEMHOLD3_7 0x00800000U
4543 #define FMC_PMEM_MEMHIZ3 0xFF000000U
4544 #define FMC_PMEM_MEMHIZ3_0 0x01000000U
4545 #define FMC_PMEM_MEMHIZ3_1 0x02000000U
4546 #define FMC_PMEM_MEMHIZ3_2 0x04000000U
4547 #define FMC_PMEM_MEMHIZ3_3 0x08000000U
4548 #define FMC_PMEM_MEMHIZ3_4 0x10000000U
4549 #define FMC_PMEM_MEMHIZ3_5 0x20000000U
4550 #define FMC_PMEM_MEMHIZ3_6 0x40000000U
4551 #define FMC_PMEM_MEMHIZ3_7 0x80000000U
4553 /****************** Bit definition for FMC_PATT register ******************/
4554 #define FMC_PATT_ATTSET3 0x000000FFU
4555 #define FMC_PATT_ATTSET3_0 0x00000001U
4556 #define FMC_PATT_ATTSET3_1 0x00000002U
4557 #define FMC_PATT_ATTSET3_2 0x00000004U
4558 #define FMC_PATT_ATTSET3_3 0x00000008U
4559 #define FMC_PATT_ATTSET3_4 0x00000010U
4560 #define FMC_PATT_ATTSET3_5 0x00000020U
4561 #define FMC_PATT_ATTSET3_6 0x00000040U
4562 #define FMC_PATT_ATTSET3_7 0x00000080U
4563 #define FMC_PATT_ATTWAIT3 0x0000FF00U
4564 #define FMC_PATT_ATTWAIT3_0 0x00000100U
4565 #define FMC_PATT_ATTWAIT3_1 0x00000200U
4566 #define FMC_PATT_ATTWAIT3_2 0x00000400U
4567 #define FMC_PATT_ATTWAIT3_3 0x00000800U
4568 #define FMC_PATT_ATTWAIT3_4 0x00001000U
4569 #define FMC_PATT_ATTWAIT3_5 0x00002000U
4570 #define FMC_PATT_ATTWAIT3_6 0x00004000U
4571 #define FMC_PATT_ATTWAIT3_7 0x00008000U
4572 #define FMC_PATT_ATTHOLD3 0x00FF0000U
4573 #define FMC_PATT_ATTHOLD3_0 0x00010000U
4574 #define FMC_PATT_ATTHOLD3_1 0x00020000U
4575 #define FMC_PATT_ATTHOLD3_2 0x00040000U
4576 #define FMC_PATT_ATTHOLD3_3 0x00080000U
4577 #define FMC_PATT_ATTHOLD3_4 0x00100000U
4578 #define FMC_PATT_ATTHOLD3_5 0x00200000U
4579 #define FMC_PATT_ATTHOLD3_6 0x00400000U
4580 #define FMC_PATT_ATTHOLD3_7 0x00800000U
4581 #define FMC_PATT_ATTHIZ3 0xFF000000U
4582 #define FMC_PATT_ATTHIZ3_0 0x01000000U
4583 #define FMC_PATT_ATTHIZ3_1 0x02000000U
4584 #define FMC_PATT_ATTHIZ3_2 0x04000000U
4585 #define FMC_PATT_ATTHIZ3_3 0x08000000U
4586 #define FMC_PATT_ATTHIZ3_4 0x10000000U
4587 #define FMC_PATT_ATTHIZ3_5 0x20000000U
4588 #define FMC_PATT_ATTHIZ3_6 0x40000000U
4589 #define FMC_PATT_ATTHIZ3_7 0x80000000U
4591 /****************** Bit definition for FMC_ECCR register ******************/
4592 #define FMC_ECCR_ECC3 0xFFFFFFFFU
4594 /****************** Bit definition for FMC_SDCR1 register ******************/
4595 #define FMC_SDCR1_NC 0x00000003U
4596 #define FMC_SDCR1_NC_0 0x00000001U
4597 #define FMC_SDCR1_NC_1 0x00000002U
4598 #define FMC_SDCR1_NR 0x0000000CU
4599 #define FMC_SDCR1_NR_0 0x00000004U
4600 #define FMC_SDCR1_NR_1 0x00000008U
4601 #define FMC_SDCR1_MWID 0x00000030U
4602 #define FMC_SDCR1_MWID_0 0x00000010U
4603 #define FMC_SDCR1_MWID_1 0x00000020U
4604 #define FMC_SDCR1_NB 0x00000040U
4605 #define FMC_SDCR1_CAS 0x00000180U
4606 #define FMC_SDCR1_CAS_0 0x00000080U
4607 #define FMC_SDCR1_CAS_1 0x00000100U
4608 #define FMC_SDCR1_WP 0x00000200U
4609 #define FMC_SDCR1_SDCLK 0x00000C00U
4610 #define FMC_SDCR1_SDCLK_0 0x00000400U
4611 #define FMC_SDCR1_SDCLK_1 0x00000800U
4612 #define FMC_SDCR1_RBURST 0x00001000U
4613 #define FMC_SDCR1_RPIPE 0x00006000U
4614 #define FMC_SDCR1_RPIPE_0 0x00002000U
4615 #define FMC_SDCR1_RPIPE_1 0x00004000U
4617 /****************** Bit definition for FMC_SDCR2 register ******************/
4618 #define FMC_SDCR2_NC 0x00000003U
4619 #define FMC_SDCR2_NC_0 0x00000001U
4620 #define FMC_SDCR2_NC_1 0x00000002U
4621 #define FMC_SDCR2_NR 0x0000000CU
4622 #define FMC_SDCR2_NR_0 0x00000004U
4623 #define FMC_SDCR2_NR_1 0x00000008U
4624 #define FMC_SDCR2_MWID 0x00000030U
4625 #define FMC_SDCR2_MWID_0 0x00000010U
4626 #define FMC_SDCR2_MWID_1 0x00000020U
4627 #define FMC_SDCR2_NB 0x00000040U
4628 #define FMC_SDCR2_CAS 0x00000180U
4629 #define FMC_SDCR2_CAS_0 0x00000080U
4630 #define FMC_SDCR2_CAS_1 0x00000100U
4631 #define FMC_SDCR2_WP 0x00000200U
4632 #define FMC_SDCR2_SDCLK 0x00000C00U
4633 #define FMC_SDCR2_SDCLK_0 0x00000400U
4634 #define FMC_SDCR2_SDCLK_1 0x00000800U
4635 #define FMC_SDCR2_RBURST 0x00001000U
4636 #define FMC_SDCR2_RPIPE 0x00006000U
4637 #define FMC_SDCR2_RPIPE_0 0x00002000U
4638 #define FMC_SDCR2_RPIPE_1 0x00004000U
4640 /****************** Bit definition for FMC_SDTR1 register ******************/
4641 #define FMC_SDTR1_TMRD 0x0000000FU
4642 #define FMC_SDTR1_TMRD_0 0x00000001U
4643 #define FMC_SDTR1_TMRD_1 0x00000002U
4644 #define FMC_SDTR1_TMRD_2 0x00000004U
4645 #define FMC_SDTR1_TMRD_3 0x00000008U
4646 #define FMC_SDTR1_TXSR 0x000000F0U
4647 #define FMC_SDTR1_TXSR_0 0x00000010U
4648 #define FMC_SDTR1_TXSR_1 0x00000020U
4649 #define FMC_SDTR1_TXSR_2 0x00000040U
4650 #define FMC_SDTR1_TXSR_3 0x00000080U
4651 #define FMC_SDTR1_TRAS 0x00000F00U
4652 #define FMC_SDTR1_TRAS_0 0x00000100U
4653 #define FMC_SDTR1_TRAS_1 0x00000200U
4654 #define FMC_SDTR1_TRAS_2 0x00000400U
4655 #define FMC_SDTR1_TRAS_3 0x00000800U
4656 #define FMC_SDTR1_TRC 0x0000F000U
4657 #define FMC_SDTR1_TRC_0 0x00001000U
4658 #define FMC_SDTR1_TRC_1 0x00002000U
4659 #define FMC_SDTR1_TRC_2 0x00004000U
4660 #define FMC_SDTR1_TWR 0x000F0000U
4661 #define FMC_SDTR1_TWR_0 0x00010000U
4662 #define FMC_SDTR1_TWR_1 0x00020000U
4663 #define FMC_SDTR1_TWR_2 0x00040000U
4664 #define FMC_SDTR1_TRP 0x00F00000U
4665 #define FMC_SDTR1_TRP_0 0x00100000U
4666 #define FMC_SDTR1_TRP_1 0x00200000U
4667 #define FMC_SDTR1_TRP_2 0x00400000U
4668 #define FMC_SDTR1_TRCD 0x0F000000U
4669 #define FMC_SDTR1_TRCD_0 0x01000000U
4670 #define FMC_SDTR1_TRCD_1 0x02000000U
4671 #define FMC_SDTR1_TRCD_2 0x04000000U
4673 /****************** Bit definition for FMC_SDTR2 register ******************/
4674 #define FMC_SDTR2_TMRD 0x0000000FU
4675 #define FMC_SDTR2_TMRD_0 0x00000001U
4676 #define FMC_SDTR2_TMRD_1 0x00000002U
4677 #define FMC_SDTR2_TMRD_2 0x00000004U
4678 #define FMC_SDTR2_TMRD_3 0x00000008U
4679 #define FMC_SDTR2_TXSR 0x000000F0U
4680 #define FMC_SDTR2_TXSR_0 0x00000010U
4681 #define FMC_SDTR2_TXSR_1 0x00000020U
4682 #define FMC_SDTR2_TXSR_2 0x00000040U
4683 #define FMC_SDTR2_TXSR_3 0x00000080U
4684 #define FMC_SDTR2_TRAS 0x00000F00U
4685 #define FMC_SDTR2_TRAS_0 0x00000100U
4686 #define FMC_SDTR2_TRAS_1 0x00000200U
4687 #define FMC_SDTR2_TRAS_2 0x00000400U
4688 #define FMC_SDTR2_TRAS_3 0x00000800U
4689 #define FMC_SDTR2_TRC 0x0000F000U
4690 #define FMC_SDTR2_TRC_0 0x00001000U
4691 #define FMC_SDTR2_TRC_1 0x00002000U
4692 #define FMC_SDTR2_TRC_2 0x00004000U
4693 #define FMC_SDTR2_TWR 0x000F0000U
4694 #define FMC_SDTR2_TWR_0 0x00010000U
4695 #define FMC_SDTR2_TWR_1 0x00020000U
4696 #define FMC_SDTR2_TWR_2 0x00040000U
4697 #define FMC_SDTR2_TRP 0x00F00000U
4698 #define FMC_SDTR2_TRP_0 0x00100000U
4699 #define FMC_SDTR2_TRP_1 0x00200000U
4700 #define FMC_SDTR2_TRP_2 0x00400000U
4701 #define FMC_SDTR2_TRCD 0x0F000000U
4702 #define FMC_SDTR2_TRCD_0 0x01000000U
4703 #define FMC_SDTR2_TRCD_1 0x02000000U
4704 #define FMC_SDTR2_TRCD_2 0x04000000U
4706 /****************** Bit definition for FMC_SDCMR register ******************/
4707 #define FMC_SDCMR_MODE 0x00000007U
4708 #define FMC_SDCMR_MODE_0 0x00000001U
4709 #define FMC_SDCMR_MODE_1 0x00000002U
4710 #define FMC_SDCMR_MODE_2 0x00000003U
4711 #define FMC_SDCMR_CTB2 0x00000008U
4712 #define FMC_SDCMR_CTB1 0x00000010U
4713 #define FMC_SDCMR_NRFS 0x000001E0U
4714 #define FMC_SDCMR_NRFS_0 0x00000020U
4715 #define FMC_SDCMR_NRFS_1 0x00000040U
4716 #define FMC_SDCMR_NRFS_2 0x00000080U
4717 #define FMC_SDCMR_NRFS_3 0x00000100U
4718 #define FMC_SDCMR_MRD 0x003FFE00U
4720 /****************** Bit definition for FMC_SDRTR register ******************/
4721 #define FMC_SDRTR_CRE 0x00000001U
4722 #define FMC_SDRTR_COUNT 0x00003FFEU
4723 #define FMC_SDRTR_REIE 0x00004000U
4725 /****************** Bit definition for FMC_SDSR register ******************/
4726 #define FMC_SDSR_RE 0x00000001U
4727 #define FMC_SDSR_MODES1 0x00000006U
4728 #define FMC_SDSR_MODES1_0 0x00000002U
4729 #define FMC_SDSR_MODES1_1 0x00000004U
4730 #define FMC_SDSR_MODES2 0x00000018U
4731 #define FMC_SDSR_MODES2_0 0x00000008U
4732 #define FMC_SDSR_MODES2_1 0x00000010U
4733 #define FMC_SDSR_BUSY 0x00000020U
4735 /******************************************************************************/
4736 /* */
4737 /* General Purpose I/O */
4738 /* */
4739 /******************************************************************************/
4740 /****************** Bits definition for GPIO_MODER register *****************/
4741 #define GPIO_MODER_MODER0 0x00000003U
4742 #define GPIO_MODER_MODER0_0 0x00000001U
4743 #define GPIO_MODER_MODER0_1 0x00000002U
4744 #define GPIO_MODER_MODER1 0x0000000CU
4745 #define GPIO_MODER_MODER1_0 0x00000004U
4746 #define GPIO_MODER_MODER1_1 0x00000008U
4747 #define GPIO_MODER_MODER2 0x00000030U
4748 #define GPIO_MODER_MODER2_0 0x00000010U
4749 #define GPIO_MODER_MODER2_1 0x00000020U
4750 #define GPIO_MODER_MODER3 0x000000C0U
4751 #define GPIO_MODER_MODER3_0 0x00000040U
4752 #define GPIO_MODER_MODER3_1 0x00000080U
4753 #define GPIO_MODER_MODER4 0x00000300U
4754 #define GPIO_MODER_MODER4_0 0x00000100U
4755 #define GPIO_MODER_MODER4_1 0x00000200U
4756 #define GPIO_MODER_MODER5 0x00000C00U
4757 #define GPIO_MODER_MODER5_0 0x00000400U
4758 #define GPIO_MODER_MODER5_1 0x00000800U
4759 #define GPIO_MODER_MODER6 0x00003000U
4760 #define GPIO_MODER_MODER6_0 0x00001000U
4761 #define GPIO_MODER_MODER6_1 0x00002000U
4762 #define GPIO_MODER_MODER7 0x0000C000U
4763 #define GPIO_MODER_MODER7_0 0x00004000U
4764 #define GPIO_MODER_MODER7_1 0x00008000U
4765 #define GPIO_MODER_MODER8 0x00030000U
4766 #define GPIO_MODER_MODER8_0 0x00010000U
4767 #define GPIO_MODER_MODER8_1 0x00020000U
4768 #define GPIO_MODER_MODER9 0x000C0000U
4769 #define GPIO_MODER_MODER9_0 0x00040000U
4770 #define GPIO_MODER_MODER9_1 0x00080000U
4771 #define GPIO_MODER_MODER10 0x00300000U
4772 #define GPIO_MODER_MODER10_0 0x00100000U
4773 #define GPIO_MODER_MODER10_1 0x00200000U
4774 #define GPIO_MODER_MODER11 0x00C00000U
4775 #define GPIO_MODER_MODER11_0 0x00400000U
4776 #define GPIO_MODER_MODER11_1 0x00800000U
4777 #define GPIO_MODER_MODER12 0x03000000U
4778 #define GPIO_MODER_MODER12_0 0x01000000U
4779 #define GPIO_MODER_MODER12_1 0x02000000U
4780 #define GPIO_MODER_MODER13 0x0C000000U
4781 #define GPIO_MODER_MODER13_0 0x04000000U
4782 #define GPIO_MODER_MODER13_1 0x08000000U
4783 #define GPIO_MODER_MODER14 0x30000000U
4784 #define GPIO_MODER_MODER14_0 0x10000000U
4785 #define GPIO_MODER_MODER14_1 0x20000000U
4786 #define GPIO_MODER_MODER15 0xC0000000U
4787 #define GPIO_MODER_MODER15_0 0x40000000U
4788 #define GPIO_MODER_MODER15_1 0x80000000U
4789 
4790 /****************** Bits definition for GPIO_OTYPER register ****************/
4791 #define GPIO_OTYPER_OT_0 0x00000001U
4792 #define GPIO_OTYPER_OT_1 0x00000002U
4793 #define GPIO_OTYPER_OT_2 0x00000004U
4794 #define GPIO_OTYPER_OT_3 0x00000008U
4795 #define GPIO_OTYPER_OT_4 0x00000010U
4796 #define GPIO_OTYPER_OT_5 0x00000020U
4797 #define GPIO_OTYPER_OT_6 0x00000040U
4798 #define GPIO_OTYPER_OT_7 0x00000080U
4799 #define GPIO_OTYPER_OT_8 0x00000100U
4800 #define GPIO_OTYPER_OT_9 0x00000200U
4801 #define GPIO_OTYPER_OT_10 0x00000400U
4802 #define GPIO_OTYPER_OT_11 0x00000800U
4803 #define GPIO_OTYPER_OT_12 0x00001000U
4804 #define GPIO_OTYPER_OT_13 0x00002000U
4805 #define GPIO_OTYPER_OT_14 0x00004000U
4806 #define GPIO_OTYPER_OT_15 0x00008000U
4807 
4808 /****************** Bits definition for GPIO_OSPEEDR register ***************/
4809 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
4810 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
4811 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
4812 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
4813 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
4814 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
4815 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
4816 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
4817 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
4818 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
4819 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
4820 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
4821 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
4822 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
4823 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
4824 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
4825 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
4826 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
4827 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
4828 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
4829 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
4830 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
4831 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
4832 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
4833 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
4834 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
4835 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
4836 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
4837 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
4838 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
4839 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
4840 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
4841 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
4842 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
4843 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
4844 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
4845 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
4846 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
4847 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
4848 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
4849 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
4850 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
4851 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
4852 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
4853 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
4854 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
4855 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
4856 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
4857 
4858 /****************** Bits definition for GPIO_PUPDR register *****************/
4859 #define GPIO_PUPDR_PUPDR0 0x00000003U
4860 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
4861 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
4862 #define GPIO_PUPDR_PUPDR1 0x0000000CU
4863 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
4864 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
4865 #define GPIO_PUPDR_PUPDR2 0x00000030U
4866 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
4867 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
4868 #define GPIO_PUPDR_PUPDR3 0x000000C0U
4869 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
4870 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
4871 #define GPIO_PUPDR_PUPDR4 0x00000300U
4872 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
4873 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
4874 #define GPIO_PUPDR_PUPDR5 0x00000C00U
4875 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
4876 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
4877 #define GPIO_PUPDR_PUPDR6 0x00003000U
4878 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
4879 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
4880 #define GPIO_PUPDR_PUPDR7 0x0000C000U
4881 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
4882 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
4883 #define GPIO_PUPDR_PUPDR8 0x00030000U
4884 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
4885 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
4886 #define GPIO_PUPDR_PUPDR9 0x000C0000U
4887 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
4888 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
4889 #define GPIO_PUPDR_PUPDR10 0x00300000U
4890 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
4891 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
4892 #define GPIO_PUPDR_PUPDR11 0x00C00000U
4893 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
4894 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
4895 #define GPIO_PUPDR_PUPDR12 0x03000000U
4896 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
4897 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
4898 #define GPIO_PUPDR_PUPDR13 0x0C000000U
4899 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
4900 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
4901 #define GPIO_PUPDR_PUPDR14 0x30000000U
4902 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
4903 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
4904 #define GPIO_PUPDR_PUPDR15 0xC0000000U
4905 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
4906 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
4907 
4908 /****************** Bits definition for GPIO_IDR register *******************/
4909 #define GPIO_IDR_IDR_0 0x00000001U
4910 #define GPIO_IDR_IDR_1 0x00000002U
4911 #define GPIO_IDR_IDR_2 0x00000004U
4912 #define GPIO_IDR_IDR_3 0x00000008U
4913 #define GPIO_IDR_IDR_4 0x00000010U
4914 #define GPIO_IDR_IDR_5 0x00000020U
4915 #define GPIO_IDR_IDR_6 0x00000040U
4916 #define GPIO_IDR_IDR_7 0x00000080U
4917 #define GPIO_IDR_IDR_8 0x00000100U
4918 #define GPIO_IDR_IDR_9 0x00000200U
4919 #define GPIO_IDR_IDR_10 0x00000400U
4920 #define GPIO_IDR_IDR_11 0x00000800U
4921 #define GPIO_IDR_IDR_12 0x00001000U
4922 #define GPIO_IDR_IDR_13 0x00002000U
4923 #define GPIO_IDR_IDR_14 0x00004000U
4924 #define GPIO_IDR_IDR_15 0x00008000U
4925 
4926 /****************** Bits definition for GPIO_ODR register *******************/
4927 #define GPIO_ODR_ODR_0 0x00000001U
4928 #define GPIO_ODR_ODR_1 0x00000002U
4929 #define GPIO_ODR_ODR_2 0x00000004U
4930 #define GPIO_ODR_ODR_3 0x00000008U
4931 #define GPIO_ODR_ODR_4 0x00000010U
4932 #define GPIO_ODR_ODR_5 0x00000020U
4933 #define GPIO_ODR_ODR_6 0x00000040U
4934 #define GPIO_ODR_ODR_7 0x00000080U
4935 #define GPIO_ODR_ODR_8 0x00000100U
4936 #define GPIO_ODR_ODR_9 0x00000200U
4937 #define GPIO_ODR_ODR_10 0x00000400U
4938 #define GPIO_ODR_ODR_11 0x00000800U
4939 #define GPIO_ODR_ODR_12 0x00001000U
4940 #define GPIO_ODR_ODR_13 0x00002000U
4941 #define GPIO_ODR_ODR_14 0x00004000U
4942 #define GPIO_ODR_ODR_15 0x00008000U
4943 
4944 /****************** Bits definition for GPIO_BSRR register ******************/
4945 #define GPIO_BSRR_BS_0 0x00000001U
4946 #define GPIO_BSRR_BS_1 0x00000002U
4947 #define GPIO_BSRR_BS_2 0x00000004U
4948 #define GPIO_BSRR_BS_3 0x00000008U
4949 #define GPIO_BSRR_BS_4 0x00000010U
4950 #define GPIO_BSRR_BS_5 0x00000020U
4951 #define GPIO_BSRR_BS_6 0x00000040U
4952 #define GPIO_BSRR_BS_7 0x00000080U
4953 #define GPIO_BSRR_BS_8 0x00000100U
4954 #define GPIO_BSRR_BS_9 0x00000200U
4955 #define GPIO_BSRR_BS_10 0x00000400U
4956 #define GPIO_BSRR_BS_11 0x00000800U
4957 #define GPIO_BSRR_BS_12 0x00001000U
4958 #define GPIO_BSRR_BS_13 0x00002000U
4959 #define GPIO_BSRR_BS_14 0x00004000U
4960 #define GPIO_BSRR_BS_15 0x00008000U
4961 #define GPIO_BSRR_BR_0 0x00010000U
4962 #define GPIO_BSRR_BR_1 0x00020000U
4963 #define GPIO_BSRR_BR_2 0x00040000U
4964 #define GPIO_BSRR_BR_3 0x00080000U
4965 #define GPIO_BSRR_BR_4 0x00100000U
4966 #define GPIO_BSRR_BR_5 0x00200000U
4967 #define GPIO_BSRR_BR_6 0x00400000U
4968 #define GPIO_BSRR_BR_7 0x00800000U
4969 #define GPIO_BSRR_BR_8 0x01000000U
4970 #define GPIO_BSRR_BR_9 0x02000000U
4971 #define GPIO_BSRR_BR_10 0x04000000U
4972 #define GPIO_BSRR_BR_11 0x08000000U
4973 #define GPIO_BSRR_BR_12 0x10000000U
4974 #define GPIO_BSRR_BR_13 0x20000000U
4975 #define GPIO_BSRR_BR_14 0x40000000U
4976 #define GPIO_BSRR_BR_15 0x80000000U
4977 
4978 /****************** Bit definition for GPIO_LCKR register *********************/
4979 #define GPIO_LCKR_LCK0 0x00000001U
4980 #define GPIO_LCKR_LCK1 0x00000002U
4981 #define GPIO_LCKR_LCK2 0x00000004U
4982 #define GPIO_LCKR_LCK3 0x00000008U
4983 #define GPIO_LCKR_LCK4 0x00000010U
4984 #define GPIO_LCKR_LCK5 0x00000020U
4985 #define GPIO_LCKR_LCK6 0x00000040U
4986 #define GPIO_LCKR_LCK7 0x00000080U
4987 #define GPIO_LCKR_LCK8 0x00000100U
4988 #define GPIO_LCKR_LCK9 0x00000200U
4989 #define GPIO_LCKR_LCK10 0x00000400U
4990 #define GPIO_LCKR_LCK11 0x00000800U
4991 #define GPIO_LCKR_LCK12 0x00001000U
4992 #define GPIO_LCKR_LCK13 0x00002000U
4993 #define GPIO_LCKR_LCK14 0x00004000U
4994 #define GPIO_LCKR_LCK15 0x00008000U
4995 #define GPIO_LCKR_LCKK 0x00010000U
4996 
4997 /******************************************************************************/
4998 /* */
4999 /* HASH */
5000 /* */
5001 /******************************************************************************/
5002 /****************** Bits definition for HASH_CR register ********************/
5003 #define HASH_CR_INIT 0x00000004U
5004 #define HASH_CR_DMAE 0x00000008U
5005 #define HASH_CR_DATATYPE 0x00000030U
5006 #define HASH_CR_DATATYPE_0 0x00000010U
5007 #define HASH_CR_DATATYPE_1 0x00000020U
5008 #define HASH_CR_MODE 0x00000040U
5009 #define HASH_CR_ALGO 0x00040080U
5010 #define HASH_CR_ALGO_0 0x00000080U
5011 #define HASH_CR_ALGO_1 0x00040000U
5012 #define HASH_CR_NBW 0x00000F00U
5013 #define HASH_CR_NBW_0 0x00000100U
5014 #define HASH_CR_NBW_1 0x00000200U
5015 #define HASH_CR_NBW_2 0x00000400U
5016 #define HASH_CR_NBW_3 0x00000800U
5017 #define HASH_CR_DINNE 0x00001000U
5018 #define HASH_CR_MDMAT 0x00002000U
5019 #define HASH_CR_LKEY 0x00010000U
5020 
5021 /****************** Bits definition for HASH_STR register *******************/
5022 #define HASH_STR_NBLW 0x0000001FU
5023 #define HASH_STR_NBLW_0 0x00000001U
5024 #define HASH_STR_NBLW_1 0x00000002U
5025 #define HASH_STR_NBLW_2 0x00000004U
5026 #define HASH_STR_NBLW_3 0x00000008U
5027 #define HASH_STR_NBLW_4 0x00000010U
5028 #define HASH_STR_DCAL 0x00000100U
5029 
5030 /* legacy defines */
5031 #define HASH_STR_NBW HASH_STR_NBLW
5032 #define HASH_STR_NBW_0 HASH_STR_NBLW_0
5033 #define HASH_STR_NBW_1 HASH_STR_NBLW_1
5034 #define HASH_STR_NBW_2 HASH_STR_NBLW_2
5035 #define HASH_STR_NBW_3 HASH_STR_NBLW_3
5036 #define HASH_STR_NBW_4 HASH_STR_NBLW_4
5037 
5038 /****************** Bits definition for HASH_IMR register *******************/
5039 #define HASH_IMR_DINIE 0x00000001U
5040 #define HASH_IMR_DCIE 0x00000002U
5041 
5042 /* legacy defines */
5043 #define HASH_IMR_DINIM HASH_IMR_DINIE
5044 #define HASH_IMR_DCIM HASH_IMR_DCIE
5045 /****************** Bits definition for HASH_SR register ********************/
5046 #define HASH_SR_DINIS 0x00000001U
5047 #define HASH_SR_DCIS 0x00000002U
5048 #define HASH_SR_DMAS 0x00000004U
5049 #define HASH_SR_BUSY 0x00000008U
5050 
5051 /******************************************************************************/
5052 /* */
5053 /* Inter-integrated Circuit Interface (I2C) */
5054 /* */
5055 /******************************************************************************/
5056 /******************* Bit definition for I2C_CR1 register *******************/
5057 #define I2C_CR1_PE 0x00000001U
5058 #define I2C_CR1_TXIE 0x00000002U
5059 #define I2C_CR1_RXIE 0x00000004U
5060 #define I2C_CR1_ADDRIE 0x00000008U
5061 #define I2C_CR1_NACKIE 0x00000010U
5062 #define I2C_CR1_STOPIE 0x00000020U
5063 #define I2C_CR1_TCIE 0x00000040U
5064 #define I2C_CR1_ERRIE 0x00000080U
5065 #define I2C_CR1_DNF 0x00000F00U
5066 #define I2C_CR1_ANFOFF 0x00001000U
5067 #define I2C_CR1_TXDMAEN 0x00004000U
5068 #define I2C_CR1_RXDMAEN 0x00008000U
5069 #define I2C_CR1_SBC 0x00010000U
5070 #define I2C_CR1_NOSTRETCH 0x00020000U
5071 #define I2C_CR1_GCEN 0x00080000U
5072 #define I2C_CR1_SMBHEN 0x00100000U
5073 #define I2C_CR1_SMBDEN 0x00200000U
5074 #define I2C_CR1_ALERTEN 0x00400000U
5075 #define I2C_CR1_PECEN 0x00800000U
5077 /* Legacy define */
5078 #define I2C_CR1_DFN I2C_CR1_DNF
5080 /****************** Bit definition for I2C_CR2 register ********************/
5081 #define I2C_CR2_SADD 0x000003FFU
5082 #define I2C_CR2_RD_WRN 0x00000400U
5083 #define I2C_CR2_ADD10 0x00000800U
5084 #define I2C_CR2_HEAD10R 0x00001000U
5085 #define I2C_CR2_START 0x00002000U
5086 #define I2C_CR2_STOP 0x00004000U
5087 #define I2C_CR2_NACK 0x00008000U
5088 #define I2C_CR2_NBYTES 0x00FF0000U
5089 #define I2C_CR2_RELOAD 0x01000000U
5090 #define I2C_CR2_AUTOEND 0x02000000U
5091 #define I2C_CR2_PECBYTE 0x04000000U
5093 /******************* Bit definition for I2C_OAR1 register ******************/
5094 #define I2C_OAR1_OA1 0x000003FFU
5095 #define I2C_OAR1_OA1MODE 0x00000400U
5096 #define I2C_OAR1_OA1EN 0x00008000U
5098 /******************* Bit definition for I2C_OAR2 register ******************/
5099 #define I2C_OAR2_OA2 0x000000FEU
5100 #define I2C_OAR2_OA2MSK 0x00000700U
5101 #define I2C_OAR2_OA2NOMASK 0x00000000U
5102 #define I2C_OAR2_OA2MASK01 0x00000100U
5103 #define I2C_OAR2_OA2MASK02 0x00000200U
5104 #define I2C_OAR2_OA2MASK03 0x00000300U
5105 #define I2C_OAR2_OA2MASK04 0x00000400U
5106 #define I2C_OAR2_OA2MASK05 0x00000500U
5107 #define I2C_OAR2_OA2MASK06 0x00000600U
5108 #define I2C_OAR2_OA2MASK07 0x00000700U
5109 #define I2C_OAR2_OA2EN 0x00008000U
5111 /******************* Bit definition for I2C_TIMINGR register *******************/
5112 #define I2C_TIMINGR_SCLL 0x000000FFU
5113 #define I2C_TIMINGR_SCLH 0x0000FF00U
5114 #define I2C_TIMINGR_SDADEL 0x000F0000U
5115 #define I2C_TIMINGR_SCLDEL 0x00F00000U
5116 #define I2C_TIMINGR_PRESC 0xF0000000U
5118 /******************* Bit definition for I2C_TIMEOUTR register *******************/
5119 #define I2C_TIMEOUTR_TIMEOUTA 0x00000FFFU
5120 #define I2C_TIMEOUTR_TIDLE 0x00001000U
5121 #define I2C_TIMEOUTR_TIMOUTEN 0x00008000U
5122 #define I2C_TIMEOUTR_TIMEOUTB 0x0FFF0000U
5123 #define I2C_TIMEOUTR_TEXTEN 0x80000000U
5125 /****************** Bit definition for I2C_ISR register *********************/
5126 #define I2C_ISR_TXE 0x00000001U
5127 #define I2C_ISR_TXIS 0x00000002U
5128 #define I2C_ISR_RXNE 0x00000004U
5129 #define I2C_ISR_ADDR 0x00000008U
5130 #define I2C_ISR_NACKF 0x00000010U
5131 #define I2C_ISR_STOPF 0x00000020U
5132 #define I2C_ISR_TC 0x00000040U
5133 #define I2C_ISR_TCR 0x00000080U
5134 #define I2C_ISR_BERR 0x00000100U
5135 #define I2C_ISR_ARLO 0x00000200U
5136 #define I2C_ISR_OVR 0x00000400U
5137 #define I2C_ISR_PECERR 0x00000800U
5138 #define I2C_ISR_TIMEOUT 0x00001000U
5139 #define I2C_ISR_ALERT 0x00002000U
5140 #define I2C_ISR_BUSY 0x00008000U
5141 #define I2C_ISR_DIR 0x00010000U
5142 #define I2C_ISR_ADDCODE 0x00FE0000U
5144 /****************** Bit definition for I2C_ICR register *********************/
5145 #define I2C_ICR_ADDRCF 0x00000008U
5146 #define I2C_ICR_NACKCF 0x00000010U
5147 #define I2C_ICR_STOPCF 0x00000020U
5148 #define I2C_ICR_BERRCF 0x00000100U
5149 #define I2C_ICR_ARLOCF 0x00000200U
5150 #define I2C_ICR_OVRCF 0x00000400U
5151 #define I2C_ICR_PECCF 0x00000800U
5152 #define I2C_ICR_TIMOUTCF 0x00001000U
5153 #define I2C_ICR_ALERTCF 0x00002000U
5155 /****************** Bit definition for I2C_PECR register *********************/
5156 #define I2C_PECR_PEC 0x000000FFU
5158 /****************** Bit definition for I2C_RXDR register *********************/
5159 #define I2C_RXDR_RXDATA 0x000000FFU
5161 /****************** Bit definition for I2C_TXDR register *********************/
5162 #define I2C_TXDR_TXDATA 0x000000FFU
5165 /******************************************************************************/
5166 /* */
5167 /* Independent WATCHDOG */
5168 /* */
5169 /******************************************************************************/
5170 /******************* Bit definition for IWDG_KR register ********************/
5171 #define IWDG_KR_KEY 0xFFFFU
5173 /******************* Bit definition for IWDG_PR register ********************/
5174 #define IWDG_PR_PR 0x07U
5175 #define IWDG_PR_PR_0 0x01U
5176 #define IWDG_PR_PR_1 0x02U
5177 #define IWDG_PR_PR_2 0x04U
5179 /******************* Bit definition for IWDG_RLR register *******************/
5180 #define IWDG_RLR_RL 0x0FFFU
5182 /******************* Bit definition for IWDG_SR register ********************/
5183 #define IWDG_SR_PVU 0x01U
5184 #define IWDG_SR_RVU 0x02U
5185 #define IWDG_SR_WVU 0x04U
5187 /******************* Bit definition for IWDG_KR register ********************/
5188 #define IWDG_WINR_WIN 0x0FFFU
5190 /******************************************************************************/
5191 /* */
5192 /* LCD-TFT Display Controller (LTDC) */
5193 /* */
5194 /******************************************************************************/
5195 
5196 /******************** Bit definition for LTDC_SSCR register *****************/
5197 
5198 #define LTDC_SSCR_VSH 0x000007FFU
5199 #define LTDC_SSCR_HSW 0x0FFF0000U
5201 /******************** Bit definition for LTDC_BPCR register *****************/
5202 
5203 #define LTDC_BPCR_AVBP 0x000007FFU
5204 #define LTDC_BPCR_AHBP 0x0FFF0000U
5206 /******************** Bit definition for LTDC_AWCR register *****************/
5207 
5208 #define LTDC_AWCR_AAH 0x000007FFU
5209 #define LTDC_AWCR_AAW 0x0FFF0000U
5211 /******************** Bit definition for LTDC_TWCR register *****************/
5212 
5213 #define LTDC_TWCR_TOTALH 0x000007FFU
5214 #define LTDC_TWCR_TOTALW 0x0FFF0000U
5216 /******************** Bit definition for LTDC_GCR register ******************/
5217 
5218 #define LTDC_GCR_LTDCEN 0x00000001U
5219 #define LTDC_GCR_DBW 0x00000070U
5220 #define LTDC_GCR_DGW 0x00000700U
5221 #define LTDC_GCR_DRW 0x00007000U
5222 #define LTDC_GCR_DEN 0x00010000U
5223 #define LTDC_GCR_PCPOL 0x10000000U
5224 #define LTDC_GCR_DEPOL 0x20000000U
5225 #define LTDC_GCR_VSPOL 0x40000000U
5226 #define LTDC_GCR_HSPOL 0x80000000U
5228 /* Legacy define */
5229 #define LTDC_GCR_DTEN LTDC_GCR_DEN
5230 
5231 /******************** Bit definition for LTDC_SRCR register *****************/
5232 
5233 #define LTDC_SRCR_IMR 0x00000001U
5234 #define LTDC_SRCR_VBR 0x00000002U
5236 /******************** Bit definition for LTDC_BCCR register *****************/
5237 
5238 #define LTDC_BCCR_BCBLUE 0x000000FFU
5239 #define LTDC_BCCR_BCGREEN 0x0000FF00U
5240 #define LTDC_BCCR_BCRED 0x00FF0000U
5242 /******************** Bit definition for LTDC_IER register ******************/
5243 
5244 #define LTDC_IER_LIE 0x00000001U
5245 #define LTDC_IER_FUIE 0x00000002U
5246 #define LTDC_IER_TERRIE 0x00000004U
5247 #define LTDC_IER_RRIE 0x00000008U
5249 /******************** Bit definition for LTDC_ISR register ******************/
5250 
5251 #define LTDC_ISR_LIF 0x00000001U
5252 #define LTDC_ISR_FUIF 0x00000002U
5253 #define LTDC_ISR_TERRIF 0x00000004U
5254 #define LTDC_ISR_RRIF 0x00000008U
5256 /******************** Bit definition for LTDC_ICR register ******************/
5257 
5258 #define LTDC_ICR_CLIF 0x00000001U
5259 #define LTDC_ICR_CFUIF 0x00000002U
5260 #define LTDC_ICR_CTERRIF 0x00000004U
5261 #define LTDC_ICR_CRRIF 0x00000008U
5263 /******************** Bit definition for LTDC_LIPCR register ****************/
5264 
5265 #define LTDC_LIPCR_LIPOS 0x000007FFU
5267 /******************** Bit definition for LTDC_CPSR register *****************/
5268 
5269 #define LTDC_CPSR_CYPOS 0x0000FFFFU
5270 #define LTDC_CPSR_CXPOS 0xFFFF0000U
5272 /******************** Bit definition for LTDC_CDSR register *****************/
5273 
5274 #define LTDC_CDSR_VDES 0x00000001U
5275 #define LTDC_CDSR_HDES 0x00000002U
5276 #define LTDC_CDSR_VSYNCS 0x00000004U
5277 #define LTDC_CDSR_HSYNCS 0x00000008U
5279 /******************** Bit definition for LTDC_LxCR register *****************/
5280 
5281 #define LTDC_LxCR_LEN 0x00000001U
5282 #define LTDC_LxCR_COLKEN 0x00000002U
5283 #define LTDC_LxCR_CLUTEN 0x00000010U
5285 /******************** Bit definition for LTDC_LxWHPCR register **************/
5286 
5287 #define LTDC_LxWHPCR_WHSTPOS 0x00000FFFU
5288 #define LTDC_LxWHPCR_WHSPPOS 0xFFFF0000U
5290 /******************** Bit definition for LTDC_LxWVPCR register **************/
5291 
5292 #define LTDC_LxWVPCR_WVSTPOS 0x00000FFFU
5293 #define LTDC_LxWVPCR_WVSPPOS 0xFFFF0000U
5295 /******************** Bit definition for LTDC_LxCKCR register ***************/
5296 
5297 #define LTDC_LxCKCR_CKBLUE 0x000000FFU
5298 #define LTDC_LxCKCR_CKGREEN 0x0000FF00U
5299 #define LTDC_LxCKCR_CKRED 0x00FF0000U
5301 /******************** Bit definition for LTDC_LxPFCR register ***************/
5302 
5303 #define LTDC_LxPFCR_PF 0x00000007U
5305 /******************** Bit definition for LTDC_LxCACR register ***************/
5306 
5307 #define LTDC_LxCACR_CONSTA 0x000000FFU
5309 /******************** Bit definition for LTDC_LxDCCR register ***************/
5310 
5311 #define LTDC_LxDCCR_DCBLUE 0x000000FFU
5312 #define LTDC_LxDCCR_DCGREEN 0x0000FF00U
5313 #define LTDC_LxDCCR_DCRED 0x00FF0000U
5314 #define LTDC_LxDCCR_DCALPHA 0xFF000000U
5316 /******************** Bit definition for LTDC_LxBFCR register ***************/
5317 
5318 #define LTDC_LxBFCR_BF2 0x00000007U
5319 #define LTDC_LxBFCR_BF1 0x00000700U
5321 /******************** Bit definition for LTDC_LxCFBAR register **************/
5322 
5323 #define LTDC_LxCFBAR_CFBADD 0xFFFFFFFFU
5325 /******************** Bit definition for LTDC_LxCFBLR register **************/
5326 
5327 #define LTDC_LxCFBLR_CFBLL 0x00001FFFU
5328 #define LTDC_LxCFBLR_CFBP 0x1FFF0000U
5330 /******************** Bit definition for LTDC_LxCFBLNR register *************/
5331 
5332 #define LTDC_LxCFBLNR_CFBLNBR 0x000007FFU
5334 /******************** Bit definition for LTDC_LxCLUTWR register *************/
5335 
5336 #define LTDC_LxCLUTWR_BLUE 0x000000FFU
5337 #define LTDC_LxCLUTWR_GREEN 0x0000FF00U
5338 #define LTDC_LxCLUTWR_RED 0x00FF0000U
5339 #define LTDC_LxCLUTWR_CLUTADD 0xFF000000U
5341 /******************************************************************************/
5342 /* */
5343 /* Power Control */
5344 /* */
5345 /******************************************************************************/
5346 /******************** Bit definition for PWR_CR1 register ********************/
5347 #define PWR_CR1_LPDS 0x00000001U
5348 #define PWR_CR1_PDDS 0x00000002U
5349 #define PWR_CR1_CSBF 0x00000008U
5350 #define PWR_CR1_PVDE 0x00000010U
5351 #define PWR_CR1_PLS 0x000000E0U
5352 #define PWR_CR1_PLS_0 0x00000020U
5353 #define PWR_CR1_PLS_1 0x00000040U
5354 #define PWR_CR1_PLS_2 0x00000080U
5357 #define PWR_CR1_PLS_LEV0 0x00000000U
5358 #define PWR_CR1_PLS_LEV1 0x00000020U
5359 #define PWR_CR1_PLS_LEV2 0x00000040U
5360 #define PWR_CR1_PLS_LEV3 0x00000060U
5361 #define PWR_CR1_PLS_LEV4 0x00000080U
5362 #define PWR_CR1_PLS_LEV5 0x000000A0U
5363 #define PWR_CR1_PLS_LEV6 0x000000C0U
5364 #define PWR_CR1_PLS_LEV7 0x000000E0U
5365 #define PWR_CR1_DBP 0x00000100U
5366 #define PWR_CR1_FPDS 0x00000200U
5367 #define PWR_CR1_LPUDS 0x00000400U
5368 #define PWR_CR1_MRUDS 0x00000800U
5369 #define PWR_CR1_ADCDC1 0x00002000U
5370 #define PWR_CR1_VOS 0x0000C000U
5371 #define PWR_CR1_VOS_0 0x00004000U
5372 #define PWR_CR1_VOS_1 0x00008000U
5373 #define PWR_CR1_ODEN 0x00010000U
5374 #define PWR_CR1_ODSWEN 0x00020000U
5375 #define PWR_CR1_UDEN 0x000C0000U
5376 #define PWR_CR1_UDEN_0 0x00040000U
5377 #define PWR_CR1_UDEN_1 0x00080000U
5379 /******************* Bit definition for PWR_CSR1 register ********************/
5380 #define PWR_CSR1_WUIF 0x00000001U
5381 #define PWR_CSR1_SBF 0x00000002U
5382 #define PWR_CSR1_PVDO 0x00000004U
5383 #define PWR_CSR1_BRR 0x00000008U
5384 #define PWR_CSR1_EIWUP 0x00000100U
5385 #define PWR_CSR1_BRE 0x00000200U
5386 #define PWR_CSR1_VOSRDY 0x00004000U
5387 #define PWR_CSR1_ODRDY 0x00010000U
5388 #define PWR_CSR1_ODSWRDY 0x00020000U
5389 #define PWR_CSR1_UDRDY 0x000C0000U
5391 /* Legacy define */
5392 #define PWR_CSR1_UDSWRDY PWR_CSR1_UDRDY
5393 
5394 /******************** Bit definition for PWR_CR2 register ********************/
5395 #define PWR_CR2_CWUPF1 0x00000001U
5396 #define PWR_CR2_CWUPF2 0x00000002U
5397 #define PWR_CR2_CWUPF3 0x00000004U
5398 #define PWR_CR2_CWUPF4 0x00000008U
5399 #define PWR_CR2_CWUPF5 0x00000010U
5400 #define PWR_CR2_CWUPF6 0x00000020U
5401 #define PWR_CR2_WUPP1 0x00000100U
5402 #define PWR_CR2_WUPP2 0x00000200U
5403 #define PWR_CR2_WUPP3 0x00000400U
5404 #define PWR_CR2_WUPP4 0x00000800U
5405 #define PWR_CR2_WUPP5 0x00001000U
5406 #define PWR_CR2_WUPP6 0x00002000U
5408 /******************* Bit definition for PWR_CSR2 register ********************/
5409 #define PWR_CSR2_WUPF1 0x00000001U
5410 #define PWR_CSR2_WUPF2 0x00000002U
5411 #define PWR_CSR2_WUPF3 0x00000004U
5412 #define PWR_CSR2_WUPF4 0x00000008U
5413 #define PWR_CSR2_WUPF5 0x00000010U
5414 #define PWR_CSR2_WUPF6 0x00000020U
5415 #define PWR_CSR2_EWUP1 0x00000100U
5416 #define PWR_CSR2_EWUP2 0x00000200U
5417 #define PWR_CSR2_EWUP3 0x00000400U
5418 #define PWR_CSR2_EWUP4 0x00000800U
5419 #define PWR_CSR2_EWUP5 0x00001000U
5420 #define PWR_CSR2_EWUP6 0x00002000U
5422 /******************************************************************************/
5423 /* */
5424 /* QUADSPI */
5425 /* */
5426 /******************************************************************************/
5427 /* QUADSPI IP version */
5428 #define QSPI1_V1_0
5429 /***************** Bit definition for QUADSPI_CR register *******************/
5430 #define QUADSPI_CR_EN 0x00000001U
5431 #define QUADSPI_CR_ABORT 0x00000002U
5432 #define QUADSPI_CR_DMAEN 0x00000004U
5433 #define QUADSPI_CR_TCEN 0x00000008U
5434 #define QUADSPI_CR_SSHIFT 0x00000010U
5435 #define QUADSPI_CR_DFM 0x00000040U
5436 #define QUADSPI_CR_FSEL 0x00000080U
5437 #define QUADSPI_CR_FTHRES 0x00001F00U
5438 #define QUADSPI_CR_FTHRES_0 0x00000100U
5439 #define QUADSPI_CR_FTHRES_1 0x00000200U
5440 #define QUADSPI_CR_FTHRES_2 0x00000400U
5441 #define QUADSPI_CR_FTHRES_3 0x00000800U
5442 #define QUADSPI_CR_FTHRES_4 0x00001000U
5443 #define QUADSPI_CR_TEIE 0x00010000U
5444 #define QUADSPI_CR_TCIE 0x00020000U
5445 #define QUADSPI_CR_FTIE 0x00040000U
5446 #define QUADSPI_CR_SMIE 0x00080000U
5447 #define QUADSPI_CR_TOIE 0x00100000U
5448 #define QUADSPI_CR_APMS 0x00400000U
5449 #define QUADSPI_CR_PMM 0x00800000U
5450 #define QUADSPI_CR_PRESCALER 0xFF000000U
5451 #define QUADSPI_CR_PRESCALER_0 0x01000000U
5452 #define QUADSPI_CR_PRESCALER_1 0x02000000U
5453 #define QUADSPI_CR_PRESCALER_2 0x04000000U
5454 #define QUADSPI_CR_PRESCALER_3 0x08000000U
5455 #define QUADSPI_CR_PRESCALER_4 0x10000000U
5456 #define QUADSPI_CR_PRESCALER_5 0x20000000U
5457 #define QUADSPI_CR_PRESCALER_6 0x40000000U
5458 #define QUADSPI_CR_PRESCALER_7 0x80000000U
5460 /***************** Bit definition for QUADSPI_DCR register ******************/
5461 #define QUADSPI_DCR_CKMODE 0x00000001U
5462 #define QUADSPI_DCR_CSHT 0x00000700U
5463 #define QUADSPI_DCR_CSHT_0 0x00000100U
5464 #define QUADSPI_DCR_CSHT_1 0x00000200U
5465 #define QUADSPI_DCR_CSHT_2 0x00000400U
5466 #define QUADSPI_DCR_FSIZE 0x001F0000U
5467 #define QUADSPI_DCR_FSIZE_0 0x00010000U
5468 #define QUADSPI_DCR_FSIZE_1 0x00020000U
5469 #define QUADSPI_DCR_FSIZE_2 0x00040000U
5470 #define QUADSPI_DCR_FSIZE_3 0x00080000U
5471 #define QUADSPI_DCR_FSIZE_4 0x00100000U
5473 /****************** Bit definition for QUADSPI_SR register *******************/
5474 #define QUADSPI_SR_TEF 0x00000001U
5475 #define QUADSPI_SR_TCF 0x00000002U
5476 #define QUADSPI_SR_FTF 0x00000004U
5477 #define QUADSPI_SR_SMF 0x00000008U
5478 #define QUADSPI_SR_TOF 0x00000010U
5479 #define QUADSPI_SR_BUSY 0x00000020U
5480 #define QUADSPI_SR_FLEVEL 0x00001F00U
5481 #define QUADSPI_SR_FLEVEL_0 0x00000100U
5482 #define QUADSPI_SR_FLEVEL_1 0x00000200U
5483 #define QUADSPI_SR_FLEVEL_2 0x00000400U
5484 #define QUADSPI_SR_FLEVEL_3 0x00000800U
5485 #define QUADSPI_SR_FLEVEL_4 0x00001000U
5487 /****************** Bit definition for QUADSPI_FCR register ******************/
5488 #define QUADSPI_FCR_CTEF 0x00000001U
5489 #define QUADSPI_FCR_CTCF 0x00000002U
5490 #define QUADSPI_FCR_CSMF 0x00000008U
5491 #define QUADSPI_FCR_CTOF 0x00000010U
5493 /****************** Bit definition for QUADSPI_DLR register ******************/
5494 #define QUADSPI_DLR_DL 0xFFFFFFFFU
5496 /****************** Bit definition for QUADSPI_CCR register ******************/
5497 #define QUADSPI_CCR_INSTRUCTION 0x000000FFU
5498 #define QUADSPI_CCR_INSTRUCTION_0 0x00000001U
5499 #define QUADSPI_CCR_INSTRUCTION_1 0x00000002U
5500 #define QUADSPI_CCR_INSTRUCTION_2 0x00000004U
5501 #define QUADSPI_CCR_INSTRUCTION_3 0x00000008U
5502 #define QUADSPI_CCR_INSTRUCTION_4 0x00000010U
5503 #define QUADSPI_CCR_INSTRUCTION_5 0x00000020U
5504 #define QUADSPI_CCR_INSTRUCTION_6 0x00000040U
5505 #define QUADSPI_CCR_INSTRUCTION_7 0x00000080U
5506 #define QUADSPI_CCR_IMODE 0x00000300U
5507 #define QUADSPI_CCR_IMODE_0 0x00000100U
5508 #define QUADSPI_CCR_IMODE_1 0x00000200U
5509 #define QUADSPI_CCR_ADMODE 0x00000C00U
5510 #define QUADSPI_CCR_ADMODE_0 0x00000400U
5511 #define QUADSPI_CCR_ADMODE_1 0x00000800U
5512 #define QUADSPI_CCR_ADSIZE 0x00003000U
5513 #define QUADSPI_CCR_ADSIZE_0 0x00001000U
5514 #define QUADSPI_CCR_ADSIZE_1 0x00002000U
5515 #define QUADSPI_CCR_ABMODE 0x0000C000U
5516 #define QUADSPI_CCR_ABMODE_0 0x00004000U
5517 #define QUADSPI_CCR_ABMODE_1 0x00008000U
5518 #define QUADSPI_CCR_ABSIZE 0x00030000U
5519 #define QUADSPI_CCR_ABSIZE_0 0x00010000U
5520 #define QUADSPI_CCR_ABSIZE_1 0x00020000U
5521 #define QUADSPI_CCR_DCYC 0x007C0000U
5522 #define QUADSPI_CCR_DCYC_0 0x00040000U
5523 #define QUADSPI_CCR_DCYC_1 0x00080000U
5524 #define QUADSPI_CCR_DCYC_2 0x00100000U
5525 #define QUADSPI_CCR_DCYC_3 0x00200000U
5526 #define QUADSPI_CCR_DCYC_4 0x00400000U
5527 #define QUADSPI_CCR_DMODE 0x03000000U
5528 #define QUADSPI_CCR_DMODE_0 0x01000000U
5529 #define QUADSPI_CCR_DMODE_1 0x02000000U
5530 #define QUADSPI_CCR_FMODE 0x0C000000U
5531 #define QUADSPI_CCR_FMODE_0 0x04000000U
5532 #define QUADSPI_CCR_FMODE_1 0x08000000U
5533 #define QUADSPI_CCR_SIOO 0x10000000U
5534 #define QUADSPI_CCR_DHHC 0x40000000U
5535 #define QUADSPI_CCR_DDRM 0x80000000U
5536 /****************** Bit definition for QUADSPI_AR register *******************/
5537 #define QUADSPI_AR_ADDRESS 0xFFFFFFFFU
5539 /****************** Bit definition for QUADSPI_ABR register ******************/
5540 #define QUADSPI_ABR_ALTERNATE 0xFFFFFFFFU
5542 /****************** Bit definition for QUADSPI_DR register *******************/
5543 #define QUADSPI_DR_DATA 0xFFFFFFFFU
5545 /****************** Bit definition for QUADSPI_PSMKR register ****************/
5546 #define QUADSPI_PSMKR_MASK 0xFFFFFFFFU
5548 /****************** Bit definition for QUADSPI_PSMAR register ****************/
5549 #define QUADSPI_PSMAR_MATCH 0xFFFFFFFFU
5551 /****************** Bit definition for QUADSPI_PIR register *****************/
5552 #define QUADSPI_PIR_INTERVAL 0x0000FFFFU
5554 /****************** Bit definition for QUADSPI_LPTR register *****************/
5555 #define QUADSPI_LPTR_TIMEOUT 0x0000FFFFU
5557 /******************************************************************************/
5558 /* */
5559 /* Reset and Clock Control */
5560 /* */
5561 /******************************************************************************/
5562 /******************** Bit definition for RCC_CR register ********************/
5563 #define RCC_CR_HSION 0x00000001U
5564 #define RCC_CR_HSIRDY 0x00000002U
5565 #define RCC_CR_HSITRIM 0x000000F8U
5566 #define RCC_CR_HSITRIM_0 0x00000008U
5567 #define RCC_CR_HSITRIM_1 0x00000010U
5568 #define RCC_CR_HSITRIM_2 0x00000020U
5569 #define RCC_CR_HSITRIM_3 0x00000040U
5570 #define RCC_CR_HSITRIM_4 0x00000080U
5571 #define RCC_CR_HSICAL 0x0000FF00U
5572 #define RCC_CR_HSICAL_0 0x00000100U
5573 #define RCC_CR_HSICAL_1 0x00000200U
5574 #define RCC_CR_HSICAL_2 0x00000400U
5575 #define RCC_CR_HSICAL_3 0x00000800U
5576 #define RCC_CR_HSICAL_4 0x00001000U
5577 #define RCC_CR_HSICAL_5 0x00002000U
5578 #define RCC_CR_HSICAL_6 0x00004000U
5579 #define RCC_CR_HSICAL_7 0x00008000U
5580 #define RCC_CR_HSEON 0x00010000U
5581 #define RCC_CR_HSERDY 0x00020000U
5582 #define RCC_CR_HSEBYP 0x00040000U
5583 #define RCC_CR_CSSON 0x00080000U
5584 #define RCC_CR_PLLON 0x01000000U
5585 #define RCC_CR_PLLRDY 0x02000000U
5586 #define RCC_CR_PLLI2SON 0x04000000U
5587 #define RCC_CR_PLLI2SRDY 0x08000000U
5588 #define RCC_CR_PLLSAION 0x10000000U
5589 #define RCC_CR_PLLSAIRDY 0x20000000U
5590 
5591 /******************** Bit definition for RCC_PLLCFGR register ***************/
5592 #define RCC_PLLCFGR_PLLM 0x0000003FU
5593 #define RCC_PLLCFGR_PLLM_0 0x00000001U
5594 #define RCC_PLLCFGR_PLLM_1 0x00000002U
5595 #define RCC_PLLCFGR_PLLM_2 0x00000004U
5596 #define RCC_PLLCFGR_PLLM_3 0x00000008U
5597 #define RCC_PLLCFGR_PLLM_4 0x00000010U
5598 #define RCC_PLLCFGR_PLLM_5 0x00000020U
5599 #define RCC_PLLCFGR_PLLN 0x00007FC0U
5600 #define RCC_PLLCFGR_PLLN_0 0x00000040U
5601 #define RCC_PLLCFGR_PLLN_1 0x00000080U
5602 #define RCC_PLLCFGR_PLLN_2 0x00000100U
5603 #define RCC_PLLCFGR_PLLN_3 0x00000200U
5604 #define RCC_PLLCFGR_PLLN_4 0x00000400U
5605 #define RCC_PLLCFGR_PLLN_5 0x00000800U
5606 #define RCC_PLLCFGR_PLLN_6 0x00001000U
5607 #define RCC_PLLCFGR_PLLN_7 0x00002000U
5608 #define RCC_PLLCFGR_PLLN_8 0x00004000U
5609 #define RCC_PLLCFGR_PLLP 0x00030000U
5610 #define RCC_PLLCFGR_PLLP_0 0x00010000U
5611 #define RCC_PLLCFGR_PLLP_1 0x00020000U
5612 #define RCC_PLLCFGR_PLLSRC 0x00400000U
5613 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
5614 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
5615 #define RCC_PLLCFGR_PLLQ 0x0F000000U
5616 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
5617 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
5618 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
5619 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
5620 
5621 
5622 /******************** Bit definition for RCC_CFGR register ******************/
5624 #define RCC_CFGR_SW 0x00000003U
5625 #define RCC_CFGR_SW_0 0x00000001U
5626 #define RCC_CFGR_SW_1 0x00000002U
5627 #define RCC_CFGR_SW_HSI 0x00000000U
5628 #define RCC_CFGR_SW_HSE 0x00000001U
5629 #define RCC_CFGR_SW_PLL 0x00000002U
5632 #define RCC_CFGR_SWS 0x0000000CU
5633 #define RCC_CFGR_SWS_0 0x00000004U
5634 #define RCC_CFGR_SWS_1 0x00000008U
5635 #define RCC_CFGR_SWS_HSI 0x00000000U
5636 #define RCC_CFGR_SWS_HSE 0x00000004U
5637 #define RCC_CFGR_SWS_PLL 0x00000008U
5640 #define RCC_CFGR_HPRE 0x000000F0U
5641 #define RCC_CFGR_HPRE_0 0x00000010U
5642 #define RCC_CFGR_HPRE_1 0x00000020U
5643 #define RCC_CFGR_HPRE_2 0x00000040U
5644 #define RCC_CFGR_HPRE_3 0x00000080U
5646 #define RCC_CFGR_HPRE_DIV1 0x00000000U
5647 #define RCC_CFGR_HPRE_DIV2 0x00000080U
5648 #define RCC_CFGR_HPRE_DIV4 0x00000090U
5649 #define RCC_CFGR_HPRE_DIV8 0x000000A0U
5650 #define RCC_CFGR_HPRE_DIV16 0x000000B0U
5651 #define RCC_CFGR_HPRE_DIV64 0x000000C0U
5652 #define RCC_CFGR_HPRE_DIV128 0x000000D0U
5653 #define RCC_CFGR_HPRE_DIV256 0x000000E0U
5654 #define RCC_CFGR_HPRE_DIV512 0x000000F0U
5657 #define RCC_CFGR_PPRE1 0x00001C00U
5658 #define RCC_CFGR_PPRE1_0 0x00000400U
5659 #define RCC_CFGR_PPRE1_1 0x00000800U
5660 #define RCC_CFGR_PPRE1_2 0x00001000U
5662 #define RCC_CFGR_PPRE1_DIV1 0x00000000U
5663 #define RCC_CFGR_PPRE1_DIV2 0x00001000U
5664 #define RCC_CFGR_PPRE1_DIV4 0x00001400U
5665 #define RCC_CFGR_PPRE1_DIV8 0x00001800U
5666 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U
5669 #define RCC_CFGR_PPRE2 0x0000E000U
5670 #define RCC_CFGR_PPRE2_0 0x00002000U
5671 #define RCC_CFGR_PPRE2_1 0x00004000U
5672 #define RCC_CFGR_PPRE2_2 0x00008000U
5674 #define RCC_CFGR_PPRE2_DIV1 0x00000000U
5675 #define RCC_CFGR_PPRE2_DIV2 0x00008000U
5676 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U
5677 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U
5678 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U
5681 #define RCC_CFGR_RTCPRE 0x001F0000U
5682 #define RCC_CFGR_RTCPRE_0 0x00010000U
5683 #define RCC_CFGR_RTCPRE_1 0x00020000U
5684 #define RCC_CFGR_RTCPRE_2 0x00040000U
5685 #define RCC_CFGR_RTCPRE_3 0x00080000U
5686 #define RCC_CFGR_RTCPRE_4 0x00100000U
5687 
5689 #define RCC_CFGR_MCO1 0x00600000U
5690 #define RCC_CFGR_MCO1_0 0x00200000U
5691 #define RCC_CFGR_MCO1_1 0x00400000U
5692 
5693 #define RCC_CFGR_I2SSRC 0x00800000U
5694 
5695 #define RCC_CFGR_MCO1PRE 0x07000000U
5696 #define RCC_CFGR_MCO1PRE_0 0x01000000U
5697 #define RCC_CFGR_MCO1PRE_1 0x02000000U
5698 #define RCC_CFGR_MCO1PRE_2 0x04000000U
5699 
5700 #define RCC_CFGR_MCO2PRE 0x38000000U
5701 #define RCC_CFGR_MCO2PRE_0 0x08000000U
5702 #define RCC_CFGR_MCO2PRE_1 0x10000000U
5703 #define RCC_CFGR_MCO2PRE_2 0x20000000U
5704 
5705 #define RCC_CFGR_MCO2 0xC0000000U
5706 #define RCC_CFGR_MCO2_0 0x40000000U
5707 #define RCC_CFGR_MCO2_1 0x80000000U
5708 
5709 /******************** Bit definition for RCC_CIR register *******************/
5710 #define RCC_CIR_LSIRDYF 0x00000001U
5711 #define RCC_CIR_LSERDYF 0x00000002U
5712 #define RCC_CIR_HSIRDYF 0x00000004U
5713 #define RCC_CIR_HSERDYF 0x00000008U
5714 #define RCC_CIR_PLLRDYF 0x00000010U
5715 #define RCC_CIR_PLLI2SRDYF 0x00000020U
5716 #define RCC_CIR_PLLSAIRDYF 0x00000040U
5717 #define RCC_CIR_CSSF 0x00000080U
5718 #define RCC_CIR_LSIRDYIE 0x00000100U
5719 #define RCC_CIR_LSERDYIE 0x00000200U
5720 #define RCC_CIR_HSIRDYIE 0x00000400U
5721 #define RCC_CIR_HSERDYIE 0x00000800U
5722 #define RCC_CIR_PLLRDYIE 0x00001000U
5723 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
5724 #define RCC_CIR_PLLSAIRDYIE 0x00004000U
5725 #define RCC_CIR_LSIRDYC 0x00010000U
5726 #define RCC_CIR_LSERDYC 0x00020000U
5727 #define RCC_CIR_HSIRDYC 0x00040000U
5728 #define RCC_CIR_HSERDYC 0x00080000U
5729 #define RCC_CIR_PLLRDYC 0x00100000U
5730 #define RCC_CIR_PLLI2SRDYC 0x00200000U
5731 #define RCC_CIR_PLLSAIRDYC 0x00400000U
5732 #define RCC_CIR_CSSC 0x00800000U
5733 
5734 /******************** Bit definition for RCC_AHB1RSTR register **************/
5735 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
5736 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
5737 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
5738 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
5739 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
5740 #define RCC_AHB1RSTR_GPIOFRST 0x00000020U
5741 #define RCC_AHB1RSTR_GPIOGRST 0x00000040U
5742 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
5743 #define RCC_AHB1RSTR_GPIOIRST 0x00000100U
5744 #define RCC_AHB1RSTR_GPIOJRST 0x00000200U
5745 #define RCC_AHB1RSTR_GPIOKRST 0x00000400U
5746 #define RCC_AHB1RSTR_CRCRST 0x00001000U
5747 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
5748 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
5749 #define RCC_AHB1RSTR_DMA2DRST 0x00800000U
5750 #define RCC_AHB1RSTR_ETHMACRST 0x02000000U
5751 #define RCC_AHB1RSTR_OTGHRST 0x20000000U
5752 
5753 /******************** Bit definition for RCC_AHB2RSTR register **************/
5754 #define RCC_AHB2RSTR_DCMIRST 0x00000001U
5755 #define RCC_AHB2RSTR_CRYPRST 0x00000010U
5756 #define RCC_AHB2RSTR_HASHRST 0x00000020U
5757 #define RCC_AHB2RSTR_RNGRST 0x00000040U
5758 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
5759 
5760 /******************** Bit definition for RCC_AHB3RSTR register **************/
5761 
5762 #define RCC_AHB3RSTR_FMCRST 0x00000001U
5763 #define RCC_AHB3RSTR_QSPIRST 0x00000002U
5764 
5765 /******************** Bit definition for RCC_APB1RSTR register **************/
5766 #define RCC_APB1RSTR_TIM2RST 0x00000001U
5767 #define RCC_APB1RSTR_TIM3RST 0x00000002U
5768 #define RCC_APB1RSTR_TIM4RST 0x00000004U
5769 #define RCC_APB1RSTR_TIM5RST 0x00000008U
5770 #define RCC_APB1RSTR_TIM6RST 0x00000010U
5771 #define RCC_APB1RSTR_TIM7RST 0x00000020U
5772 #define RCC_APB1RSTR_TIM12RST 0x00000040U
5773 #define RCC_APB1RSTR_TIM13RST 0x00000080U
5774 #define RCC_APB1RSTR_TIM14RST 0x00000100U
5775 #define RCC_APB1RSTR_LPTIM1RST 0x00000200U
5776 #define RCC_APB1RSTR_WWDGRST 0x00000800U
5777 #define RCC_APB1RSTR_SPI2RST 0x00004000U
5778 #define RCC_APB1RSTR_SPI3RST 0x00008000U
5779 #define RCC_APB1RSTR_SPDIFRXRST 0x00010000U
5780 #define RCC_APB1RSTR_USART2RST 0x00020000U
5781 #define RCC_APB1RSTR_USART3RST 0x00040000U
5782 #define RCC_APB1RSTR_UART4RST 0x00080000U
5783 #define RCC_APB1RSTR_UART5RST 0x00100000U
5784 #define RCC_APB1RSTR_I2C1RST 0x00200000U
5785 #define RCC_APB1RSTR_I2C2RST 0x00400000U
5786 #define RCC_APB1RSTR_I2C3RST 0x00800000U
5787 #define RCC_APB1RSTR_I2C4RST 0x01000000U
5788 #define RCC_APB1RSTR_CAN1RST 0x02000000U
5789 #define RCC_APB1RSTR_CAN2RST 0x04000000U
5790 #define RCC_APB1RSTR_CECRST 0x08000000U
5791 #define RCC_APB1RSTR_PWRRST 0x10000000U
5792 #define RCC_APB1RSTR_DACRST 0x20000000U
5793 #define RCC_APB1RSTR_UART7RST 0x40000000U
5794 #define RCC_APB1RSTR_UART8RST 0x80000000U
5795 
5796 /******************** Bit definition for RCC_APB2RSTR register **************/
5797 #define RCC_APB2RSTR_TIM1RST 0x00000001U
5798 #define RCC_APB2RSTR_TIM8RST 0x00000002U
5799 #define RCC_APB2RSTR_USART1RST 0x00000010U
5800 #define RCC_APB2RSTR_USART6RST 0x00000020U
5801 #define RCC_APB2RSTR_ADCRST 0x00000100U
5802 #define RCC_APB2RSTR_SDMMC1RST 0x00000800U
5803 #define RCC_APB2RSTR_SPI1RST 0x00001000U
5804 #define RCC_APB2RSTR_SPI4RST 0x00002000U
5805 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
5806 #define RCC_APB2RSTR_TIM9RST 0x00010000U
5807 #define RCC_APB2RSTR_TIM10RST 0x00020000U
5808 #define RCC_APB2RSTR_TIM11RST 0x00040000U
5809 #define RCC_APB2RSTR_SPI5RST 0x00100000U
5810 #define RCC_APB2RSTR_SPI6RST 0x00200000U
5811 #define RCC_APB2RSTR_SAI1RST 0x00400000U
5812 #define RCC_APB2RSTR_SAI2RST 0x00800000U
5813 #define RCC_APB2RSTR_LTDCRST 0x04000000U
5814 
5815 /******************** Bit definition for RCC_AHB1ENR register ***************/
5816 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
5817 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
5818 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
5819 #define RCC_AHB1ENR_GPIODEN 0x00000008U
5820 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
5821 #define RCC_AHB1ENR_GPIOFEN 0x00000020U
5822 #define RCC_AHB1ENR_GPIOGEN 0x00000040U
5823 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
5824 #define RCC_AHB1ENR_GPIOIEN 0x00000100U
5825 #define RCC_AHB1ENR_GPIOJEN 0x00000200U
5826 #define RCC_AHB1ENR_GPIOKEN 0x00000400U
5827 #define RCC_AHB1ENR_CRCEN 0x00001000U
5828 #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
5829 #define RCC_AHB1ENR_DTCMRAMEN 0x00100000U
5830 #define RCC_AHB1ENR_DMA1EN 0x00200000U
5831 #define RCC_AHB1ENR_DMA2EN 0x00400000U
5832 #define RCC_AHB1ENR_DMA2DEN 0x00800000U
5833 #define RCC_AHB1ENR_ETHMACEN 0x02000000U
5834 #define RCC_AHB1ENR_ETHMACTXEN 0x04000000U
5835 #define RCC_AHB1ENR_ETHMACRXEN 0x08000000U
5836 #define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U
5837 #define RCC_AHB1ENR_OTGHSEN 0x20000000U
5838 #define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
5839 
5840 /******************** Bit definition for RCC_AHB2ENR register ***************/
5841 #define RCC_AHB2ENR_DCMIEN 0x00000001U
5842 #define RCC_AHB2ENR_CRYPEN 0x00000010U
5843 #define RCC_AHB2ENR_HASHEN 0x00000020U
5844 #define RCC_AHB2ENR_RNGEN 0x00000040U
5845 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
5846 
5847 /******************** Bit definition for RCC_AHB3ENR register ***************/
5848 #define RCC_AHB3ENR_FMCEN 0x00000001U
5849 #define RCC_AHB3ENR_QSPIEN 0x00000002U
5850 
5851 /******************** Bit definition for RCC_APB1ENR register ***************/
5852 #define RCC_APB1ENR_TIM2EN 0x00000001U
5853 #define RCC_APB1ENR_TIM3EN 0x00000002U
5854 #define RCC_APB1ENR_TIM4EN 0x00000004U
5855 #define RCC_APB1ENR_TIM5EN 0x00000008U
5856 #define RCC_APB1ENR_TIM6EN 0x00000010U
5857 #define RCC_APB1ENR_TIM7EN 0x00000020U
5858 #define RCC_APB1ENR_TIM12EN 0x00000040U
5859 #define RCC_APB1ENR_TIM13EN 0x00000080U
5860 #define RCC_APB1ENR_TIM14EN 0x00000100U
5861 #define RCC_APB1ENR_LPTIM1EN 0x00000200U
5862 #define RCC_APB1ENR_WWDGEN 0x00000800U
5863 #define RCC_APB1ENR_SPI2EN 0x00004000U
5864 #define RCC_APB1ENR_SPI3EN 0x00008000U
5865 #define RCC_APB1ENR_SPDIFRXEN 0x00010000U
5866 #define RCC_APB1ENR_USART2EN 0x00020000U
5867 #define RCC_APB1ENR_USART3EN 0x00040000U
5868 #define RCC_APB1ENR_UART4EN 0x00080000U
5869 #define RCC_APB1ENR_UART5EN 0x00100000U
5870 #define RCC_APB1ENR_I2C1EN 0x00200000U
5871 #define RCC_APB1ENR_I2C2EN 0x00400000U
5872 #define RCC_APB1ENR_I2C3EN 0x00800000U
5873 #define RCC_APB1ENR_I2C4EN 0x01000000U
5874 #define RCC_APB1ENR_CAN1EN 0x02000000U
5875 #define RCC_APB1ENR_CAN2EN 0x04000000U
5876 #define RCC_APB1ENR_CECEN 0x08000000U
5877 #define RCC_APB1ENR_PWREN 0x10000000U
5878 #define RCC_APB1ENR_DACEN 0x20000000U
5879 #define RCC_APB1ENR_UART7EN 0x40000000U
5880 #define RCC_APB1ENR_UART8EN 0x80000000U
5881 
5882 /******************** Bit definition for RCC_APB2ENR register ***************/
5883 #define RCC_APB2ENR_TIM1EN 0x00000001U
5884 #define RCC_APB2ENR_TIM8EN 0x00000002U
5885 #define RCC_APB2ENR_USART1EN 0x00000010U
5886 #define RCC_APB2ENR_USART6EN 0x00000020U
5887 #define RCC_APB2ENR_ADC1EN 0x00000100U
5888 #define RCC_APB2ENR_ADC2EN 0x00000200U
5889 #define RCC_APB2ENR_ADC3EN 0x00000400U
5890 #define RCC_APB2ENR_SDMMC1EN 0x00000800U
5891 #define RCC_APB2ENR_SPI1EN 0x00001000U
5892 #define RCC_APB2ENR_SPI4EN 0x00002000U
5893 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
5894 #define RCC_APB2ENR_TIM9EN 0x00010000U
5895 #define RCC_APB2ENR_TIM10EN 0x00020000U
5896 #define RCC_APB2ENR_TIM11EN 0x00040000U
5897 #define RCC_APB2ENR_SPI5EN 0x00100000U
5898 #define RCC_APB2ENR_SPI6EN 0x00200000U
5899 #define RCC_APB2ENR_SAI1EN 0x00400000U
5900 #define RCC_APB2ENR_SAI2EN 0x00800000U
5901 #define RCC_APB2ENR_LTDCEN 0x04000000U
5902 
5903 /******************** Bit definition for RCC_AHB1LPENR register *************/
5904 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
5905 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
5906 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
5907 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
5908 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
5909 #define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
5910 #define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
5911 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
5912 #define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
5913 #define RCC_AHB1LPENR_GPIOJLPEN 0x00000200U
5914 #define RCC_AHB1LPENR_GPIOKLPEN 0x00000400U
5915 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
5916 #define RCC_AHB1LPENR_AXILPEN 0x00002000U
5917 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
5918 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
5919 #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
5920 #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
5921 #define RCC_AHB1LPENR_DTCMLPEN 0x00100000U
5922 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
5923 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
5924 #define RCC_AHB1LPENR_DMA2DLPEN 0x00800000U
5925 #define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U
5926 #define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U
5927 #define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U
5928 #define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U
5929 #define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
5930 #define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
5931 
5932 /******************** Bit definition for RCC_AHB2LPENR register *************/
5933 #define RCC_AHB2LPENR_DCMILPEN 0x00000001U
5934 #define RCC_AHB2LPENR_CRYPLPEN 0x00000010U
5935 #define RCC_AHB2LPENR_HASHLPEN 0x00000020U
5936 #define RCC_AHB2LPENR_RNGLPEN 0x00000040U
5937 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
5938 
5939 /******************** Bit definition for RCC_AHB3LPENR register *************/
5940 #define RCC_AHB3LPENR_FMCLPEN 0x00000001U
5941 #define RCC_AHB3LPENR_QSPILPEN 0x00000002U
5942 /******************** Bit definition for RCC_APB1LPENR register *************/
5943 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
5944 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
5945 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
5946 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
5947 #define RCC_APB1LPENR_TIM6LPEN 0x00000010U
5948 #define RCC_APB1LPENR_TIM7LPEN 0x00000020U
5949 #define RCC_APB1LPENR_TIM12LPEN 0x00000040U
5950 #define RCC_APB1LPENR_TIM13LPEN 0x00000080U
5951 #define RCC_APB1LPENR_TIM14LPEN 0x00000100U
5952 #define RCC_APB1LPENR_LPTIM1LPEN 0x00000200U
5953 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
5954 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
5955 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
5956 #define RCC_APB1LPENR_SPDIFRXLPEN 0x00010000U
5957 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
5958 #define RCC_APB1LPENR_USART3LPEN 0x00040000U
5959 #define RCC_APB1LPENR_UART4LPEN 0x00080000U
5960 #define RCC_APB1LPENR_UART5LPEN 0x00100000U
5961 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
5962 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
5963 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
5964 #define RCC_APB1LPENR_I2C4LPEN 0x01000000U
5965 #define RCC_APB1LPENR_CAN1LPEN 0x02000000U
5966 #define RCC_APB1LPENR_CAN2LPEN 0x04000000U
5967 #define RCC_APB1LPENR_CECLPEN 0x08000000U
5968 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
5969 #define RCC_APB1LPENR_DACLPEN 0x20000000U
5970 #define RCC_APB1LPENR_UART7LPEN 0x40000000U
5971 #define RCC_APB1LPENR_UART8LPEN 0x80000000U
5972 
5973 /******************** Bit definition for RCC_APB2LPENR register *************/
5974 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
5975 #define RCC_APB2LPENR_TIM8LPEN 0x00000002U
5976 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
5977 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
5978 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
5979 #define RCC_APB2LPENR_ADC2LPEN 0x00000200U
5980 #define RCC_APB2LPENR_ADC3LPEN 0x00000400U
5981 #define RCC_APB2LPENR_SDMMC1LPEN 0x00000800U
5982 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
5983 #define RCC_APB2LPENR_SPI4LPEN 0x00002000U
5984 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
5985 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
5986 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
5987 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
5988 #define RCC_APB2LPENR_SPI5LPEN 0x00100000U
5989 #define RCC_APB2LPENR_SPI6LPEN 0x00200000U
5990 #define RCC_APB2LPENR_SAI1LPEN 0x00400000U
5991 #define RCC_APB2LPENR_SAI2LPEN 0x00800000U
5992 #define RCC_APB2LPENR_LTDCLPEN 0x04000000U
5993 
5994 /******************** Bit definition for RCC_BDCR register ******************/
5995 #define RCC_BDCR_LSEON 0x00000001U
5996 #define RCC_BDCR_LSERDY 0x00000002U
5997 #define RCC_BDCR_LSEBYP 0x00000004U
5998 #define RCC_BDCR_LSEDRV 0x00000018U
5999 #define RCC_BDCR_LSEDRV_0 0x00000008U
6000 #define RCC_BDCR_LSEDRV_1 0x00000010U
6001 #define RCC_BDCR_RTCSEL 0x00000300U
6002 #define RCC_BDCR_RTCSEL_0 0x00000100U
6003 #define RCC_BDCR_RTCSEL_1 0x00000200U
6004 #define RCC_BDCR_RTCEN 0x00008000U
6005 #define RCC_BDCR_BDRST 0x00010000U
6006 
6007 /******************** Bit definition for RCC_CSR register *******************/
6008 #define RCC_CSR_LSION 0x00000001U
6009 #define RCC_CSR_LSIRDY 0x00000002U
6010 #define RCC_CSR_RMVF 0x01000000U
6011 #define RCC_CSR_BORRSTF 0x02000000U
6012 #define RCC_CSR_PINRSTF 0x04000000U
6013 #define RCC_CSR_PORRSTF 0x08000000U
6014 #define RCC_CSR_SFTRSTF 0x10000000U
6015 #define RCC_CSR_IWDGRSTF 0x20000000U
6016 #define RCC_CSR_WWDGRSTF 0x40000000U
6017 #define RCC_CSR_LPWRRSTF 0x80000000U
6018 
6019 /******************** Bit definition for RCC_SSCGR register *****************/
6020 #define RCC_SSCGR_MODPER 0x00001FFFU
6021 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
6022 #define RCC_SSCGR_SPREADSEL 0x40000000U
6023 #define RCC_SSCGR_SSCGEN 0x80000000U
6024 
6025 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
6026 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
6027 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
6028 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
6029 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
6030 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
6031 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
6032 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
6033 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
6034 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
6035 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
6036 #define RCC_PLLI2SCFGR_PLLI2SP 0x00030000U
6037 #define RCC_PLLI2SCFGR_PLLI2SP_0 0x00010000U
6038 #define RCC_PLLI2SCFGR_PLLI2SP_1 0x00020000U
6039 #define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
6040 #define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
6041 #define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
6042 #define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
6043 #define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
6044 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
6045 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
6046 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
6047 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
6048 
6049 /******************** Bit definition for RCC_PLLSAICFGR register ************/
6050 #define RCC_PLLSAICFGR_PLLSAIN 0x00007FC0U
6051 #define RCC_PLLSAICFGR_PLLSAIN_0 0x00000040U
6052 #define RCC_PLLSAICFGR_PLLSAIN_1 0x00000080U
6053 #define RCC_PLLSAICFGR_PLLSAIN_2 0x00000100U
6054 #define RCC_PLLSAICFGR_PLLSAIN_3 0x00000200U
6055 #define RCC_PLLSAICFGR_PLLSAIN_4 0x00000400U
6056 #define RCC_PLLSAICFGR_PLLSAIN_5 0x00000800U
6057 #define RCC_PLLSAICFGR_PLLSAIN_6 0x00001000U
6058 #define RCC_PLLSAICFGR_PLLSAIN_7 0x00002000U
6059 #define RCC_PLLSAICFGR_PLLSAIN_8 0x00004000U
6060 #define RCC_PLLSAICFGR_PLLSAIP 0x00030000U
6061 #define RCC_PLLSAICFGR_PLLSAIP_0 0x00010000U
6062 #define RCC_PLLSAICFGR_PLLSAIP_1 0x00020000U
6063 #define RCC_PLLSAICFGR_PLLSAIQ 0x0F000000U
6064 #define RCC_PLLSAICFGR_PLLSAIQ_0 0x01000000U
6065 #define RCC_PLLSAICFGR_PLLSAIQ_1 0x02000000U
6066 #define RCC_PLLSAICFGR_PLLSAIQ_2 0x04000000U
6067 #define RCC_PLLSAICFGR_PLLSAIQ_3 0x08000000U
6068 #define RCC_PLLSAICFGR_PLLSAIR 0x70000000U
6069 #define RCC_PLLSAICFGR_PLLSAIR_0 0x10000000U
6070 #define RCC_PLLSAICFGR_PLLSAIR_1 0x20000000U
6071 #define RCC_PLLSAICFGR_PLLSAIR_2 0x40000000U
6072 
6073 /******************** Bit definition for RCC_DCKCFGR1 register ***************/
6074 #define RCC_DCKCFGR1_PLLI2SDIVQ 0x0000001FU
6075 #define RCC_DCKCFGR1_PLLI2SDIVQ_0 0x00000001U
6076 #define RCC_DCKCFGR1_PLLI2SDIVQ_1 0x00000002U
6077 #define RCC_DCKCFGR1_PLLI2SDIVQ_2 0x00000004U
6078 #define RCC_DCKCFGR1_PLLI2SDIVQ_3 0x00000008U
6079 #define RCC_DCKCFGR1_PLLI2SDIVQ_4 0x00000010U
6080 
6081 #define RCC_DCKCFGR1_PLLSAIDIVQ 0x00001F00U
6082 #define RCC_DCKCFGR1_PLLSAIDIVQ_0 0x00000100U
6083 #define RCC_DCKCFGR1_PLLSAIDIVQ_1 0x00000200U
6084 #define RCC_DCKCFGR1_PLLSAIDIVQ_2 0x00000400U
6085 #define RCC_DCKCFGR1_PLLSAIDIVQ_3 0x00000800U
6086 #define RCC_DCKCFGR1_PLLSAIDIVQ_4 0x00001000U
6087 
6088 #define RCC_DCKCFGR1_PLLSAIDIVR 0x00030000U
6089 #define RCC_DCKCFGR1_PLLSAIDIVR_0 0x00010000U
6090 #define RCC_DCKCFGR1_PLLSAIDIVR_1 0x00020000U
6091 
6092 #define RCC_DCKCFGR1_SAI1SEL 0x00300000U
6093 #define RCC_DCKCFGR1_SAI1SEL_0 0x00100000U
6094 #define RCC_DCKCFGR1_SAI1SEL_1 0x00200000U
6095 
6096 #define RCC_DCKCFGR1_SAI2SEL 0x00C00000U
6097 #define RCC_DCKCFGR1_SAI2SEL_0 0x00400000U
6098 #define RCC_DCKCFGR1_SAI2SEL_1 0x00800000U
6099 
6100 #define RCC_DCKCFGR1_TIMPRE 0x01000000U
6101 
6102 /******************** Bit definition for RCC_DCKCFGR2 register ***************/
6103 #define RCC_DCKCFGR2_USART1SEL 0x00000003U
6104 #define RCC_DCKCFGR2_USART1SEL_0 0x00000001U
6105 #define RCC_DCKCFGR2_USART1SEL_1 0x00000002U
6106 #define RCC_DCKCFGR2_USART2SEL 0x0000000CU
6107 #define RCC_DCKCFGR2_USART2SEL_0 0x00000004U
6108 #define RCC_DCKCFGR2_USART2SEL_1 0x00000008U
6109 #define RCC_DCKCFGR2_USART3SEL 0x00000030U
6110 #define RCC_DCKCFGR2_USART3SEL_0 0x00000010U
6111 #define RCC_DCKCFGR2_USART3SEL_1 0x00000020U
6112 #define RCC_DCKCFGR2_UART4SEL 0x000000C0U
6113 #define RCC_DCKCFGR2_UART4SEL_0 0x00000040U
6114 #define RCC_DCKCFGR2_UART4SEL_1 0x00000080U
6115 #define RCC_DCKCFGR2_UART5SEL 0x00000300U
6116 #define RCC_DCKCFGR2_UART5SEL_0 0x00000100U
6117 #define RCC_DCKCFGR2_UART5SEL_1 0x00000200U
6118 #define RCC_DCKCFGR2_USART6SEL 0x00000C00U
6119 #define RCC_DCKCFGR2_USART6SEL_0 0x00000400U
6120 #define RCC_DCKCFGR2_USART6SEL_1 0x00000800U
6121 #define RCC_DCKCFGR2_UART7SEL 0x00003000U
6122 #define RCC_DCKCFGR2_UART7SEL_0 0x00001000U
6123 #define RCC_DCKCFGR2_UART7SEL_1 0x00002000U
6124 #define RCC_DCKCFGR2_UART8SEL 0x0000C000U
6125 #define RCC_DCKCFGR2_UART8SEL_0 0x00004000U
6126 #define RCC_DCKCFGR2_UART8SEL_1 0x00008000U
6127 #define RCC_DCKCFGR2_I2C1SEL 0x00030000U
6128 #define RCC_DCKCFGR2_I2C1SEL_0 0x00010000U
6129 #define RCC_DCKCFGR2_I2C1SEL_1 0x00020000U
6130 #define RCC_DCKCFGR2_I2C2SEL 0x000C0000U
6131 #define RCC_DCKCFGR2_I2C2SEL_0 0x00040000U
6132 #define RCC_DCKCFGR2_I2C2SEL_1 0x00080000U
6133 #define RCC_DCKCFGR2_I2C3SEL 0x00300000U
6134 #define RCC_DCKCFGR2_I2C3SEL_0 0x00100000U
6135 #define RCC_DCKCFGR2_I2C3SEL_1 0x00200000U
6136 #define RCC_DCKCFGR2_I2C4SEL 0x00C00000U
6137 #define RCC_DCKCFGR2_I2C4SEL_0 0x00400000U
6138 #define RCC_DCKCFGR2_I2C4SEL_1 0x00800000U
6139 #define RCC_DCKCFGR2_LPTIM1SEL 0x03000000U
6140 #define RCC_DCKCFGR2_LPTIM1SEL_0 0x01000000U
6141 #define RCC_DCKCFGR2_LPTIM1SEL_1 0x02000000U
6142 #define RCC_DCKCFGR2_CECSEL 0x04000000U
6143 #define RCC_DCKCFGR2_CK48MSEL 0x08000000U
6144 #define RCC_DCKCFGR2_SDMMC1SEL 0x10000000U
6145 
6146 /******************************************************************************/
6147 /* */
6148 /* RNG */
6149 /* */
6150 /******************************************************************************/
6151 /******************** Bits definition for RNG_CR register *******************/
6152 #define RNG_CR_RNGEN 0x00000004U
6153 #define RNG_CR_IE 0x00000008U
6154 
6155 /******************** Bits definition for RNG_SR register *******************/
6156 #define RNG_SR_DRDY 0x00000001U
6157 #define RNG_SR_CECS 0x00000002U
6158 #define RNG_SR_SECS 0x00000004U
6159 #define RNG_SR_CEIS 0x00000020U
6160 #define RNG_SR_SEIS 0x00000040U
6161 
6162 /******************************************************************************/
6163 /* */
6164 /* Real-Time Clock (RTC) */
6165 /* */
6166 /******************************************************************************/
6167 /******************** Bits definition for RTC_TR register *******************/
6168 #define RTC_TR_PM 0x00400000U
6169 #define RTC_TR_HT 0x00300000U
6170 #define RTC_TR_HT_0 0x00100000U
6171 #define RTC_TR_HT_1 0x00200000U
6172 #define RTC_TR_HU 0x000F0000U
6173 #define RTC_TR_HU_0 0x00010000U
6174 #define RTC_TR_HU_1 0x00020000U
6175 #define RTC_TR_HU_2 0x00040000U
6176 #define RTC_TR_HU_3 0x00080000U
6177 #define RTC_TR_MNT 0x00007000U
6178 #define RTC_TR_MNT_0 0x00001000U
6179 #define RTC_TR_MNT_1 0x00002000U
6180 #define RTC_TR_MNT_2 0x00004000U
6181 #define RTC_TR_MNU 0x00000F00U
6182 #define RTC_TR_MNU_0 0x00000100U
6183 #define RTC_TR_MNU_1 0x00000200U
6184 #define RTC_TR_MNU_2 0x00000400U
6185 #define RTC_TR_MNU_3 0x00000800U
6186 #define RTC_TR_ST 0x00000070U
6187 #define RTC_TR_ST_0 0x00000010U
6188 #define RTC_TR_ST_1 0x00000020U
6189 #define RTC_TR_ST_2 0x00000040U
6190 #define RTC_TR_SU 0x0000000FU
6191 #define RTC_TR_SU_0 0x00000001U
6192 #define RTC_TR_SU_1 0x00000002U
6193 #define RTC_TR_SU_2 0x00000004U
6194 #define RTC_TR_SU_3 0x00000008U
6195 
6196 /******************** Bits definition for RTC_DR register *******************/
6197 #define RTC_DR_YT 0x00F00000U
6198 #define RTC_DR_YT_0 0x00100000U
6199 #define RTC_DR_YT_1 0x00200000U
6200 #define RTC_DR_YT_2 0x00400000U
6201 #define RTC_DR_YT_3 0x00800000U
6202 #define RTC_DR_YU 0x000F0000U
6203 #define RTC_DR_YU_0 0x00010000U
6204 #define RTC_DR_YU_1 0x00020000U
6205 #define RTC_DR_YU_2 0x00040000U
6206 #define RTC_DR_YU_3 0x00080000U
6207 #define RTC_DR_WDU 0x0000E000U
6208 #define RTC_DR_WDU_0 0x00002000U
6209 #define RTC_DR_WDU_1 0x00004000U
6210 #define RTC_DR_WDU_2 0x00008000U
6211 #define RTC_DR_MT 0x00001000U
6212 #define RTC_DR_MU 0x00000F00U
6213 #define RTC_DR_MU_0 0x00000100U
6214 #define RTC_DR_MU_1 0x00000200U
6215 #define RTC_DR_MU_2 0x00000400U
6216 #define RTC_DR_MU_3 0x00000800U
6217 #define RTC_DR_DT 0x00000030U
6218 #define RTC_DR_DT_0 0x00000010U
6219 #define RTC_DR_DT_1 0x00000020U
6220 #define RTC_DR_DU 0x0000000FU
6221 #define RTC_DR_DU_0 0x00000001U
6222 #define RTC_DR_DU_1 0x00000002U
6223 #define RTC_DR_DU_2 0x00000004U
6224 #define RTC_DR_DU_3 0x00000008U
6225 
6226 /******************** Bits definition for RTC_CR register *******************/
6227 #define RTC_CR_ITSE 0x01000000U
6228 #define RTC_CR_COE 0x00800000U
6229 #define RTC_CR_OSEL 0x00600000U
6230 #define RTC_CR_OSEL_0 0x00200000U
6231 #define RTC_CR_OSEL_1 0x00400000U
6232 #define RTC_CR_POL 0x00100000U
6233 #define RTC_CR_COSEL 0x00080000U
6234 #define RTC_CR_BCK 0x00040000U
6235 #define RTC_CR_SUB1H 0x00020000U
6236 #define RTC_CR_ADD1H 0x00010000U
6237 #define RTC_CR_TSIE 0x00008000U
6238 #define RTC_CR_WUTIE 0x00004000U
6239 #define RTC_CR_ALRBIE 0x00002000U
6240 #define RTC_CR_ALRAIE 0x00001000U
6241 #define RTC_CR_TSE 0x00000800U
6242 #define RTC_CR_WUTE 0x00000400U
6243 #define RTC_CR_ALRBE 0x00000200U
6244 #define RTC_CR_ALRAE 0x00000100U
6245 #define RTC_CR_FMT 0x00000040U
6246 #define RTC_CR_BYPSHAD 0x00000020U
6247 #define RTC_CR_REFCKON 0x00000010U
6248 #define RTC_CR_TSEDGE 0x00000008U
6249 #define RTC_CR_WUCKSEL 0x00000007U
6250 #define RTC_CR_WUCKSEL_0 0x00000001U
6251 #define RTC_CR_WUCKSEL_1 0x00000002U
6252 #define RTC_CR_WUCKSEL_2 0x00000004U
6253 
6254 /******************** Bits definition for RTC_ISR register ******************/
6255 #define RTC_ISR_ITSF 0x00020000U
6256 #define RTC_ISR_RECALPF 0x00010000U
6257 #define RTC_ISR_TAMP3F 0x00008000U
6258 #define RTC_ISR_TAMP2F 0x00004000U
6259 #define RTC_ISR_TAMP1F 0x00002000U
6260 #define RTC_ISR_TSOVF 0x00001000U
6261 #define RTC_ISR_TSF 0x00000800U
6262 #define RTC_ISR_WUTF 0x00000400U
6263 #define RTC_ISR_ALRBF 0x00000200U
6264 #define RTC_ISR_ALRAF 0x00000100U
6265 #define RTC_ISR_INIT 0x00000080U
6266 #define RTC_ISR_INITF 0x00000040U
6267 #define RTC_ISR_RSF 0x00000020U
6268 #define RTC_ISR_INITS 0x00000010U
6269 #define RTC_ISR_SHPF 0x00000008U
6270 #define RTC_ISR_WUTWF 0x00000004U
6271 #define RTC_ISR_ALRBWF 0x00000002U
6272 #define RTC_ISR_ALRAWF 0x00000001U
6273 
6274 /******************** Bits definition for RTC_PRER register *****************/
6275 #define RTC_PRER_PREDIV_A 0x007F0000U
6276 #define RTC_PRER_PREDIV_S 0x00007FFFU
6277 
6278 /******************** Bits definition for RTC_WUTR register *****************/
6279 #define RTC_WUTR_WUT 0x0000FFFFU
6280 
6281 /******************** Bits definition for RTC_ALRMAR register ***************/
6282 #define RTC_ALRMAR_MSK4 0x80000000U
6283 #define RTC_ALRMAR_WDSEL 0x40000000U
6284 #define RTC_ALRMAR_DT 0x30000000U
6285 #define RTC_ALRMAR_DT_0 0x10000000U
6286 #define RTC_ALRMAR_DT_1 0x20000000U
6287 #define RTC_ALRMAR_DU 0x0F000000U
6288 #define RTC_ALRMAR_DU_0 0x01000000U
6289 #define RTC_ALRMAR_DU_1 0x02000000U
6290 #define RTC_ALRMAR_DU_2 0x04000000U
6291 #define RTC_ALRMAR_DU_3 0x08000000U
6292 #define RTC_ALRMAR_MSK3 0x00800000U
6293 #define RTC_ALRMAR_PM 0x00400000U
6294 #define RTC_ALRMAR_HT 0x00300000U
6295 #define RTC_ALRMAR_HT_0 0x00100000U
6296 #define RTC_ALRMAR_HT_1 0x00200000U
6297 #define RTC_ALRMAR_HU 0x000F0000U
6298 #define RTC_ALRMAR_HU_0 0x00010000U
6299 #define RTC_ALRMAR_HU_1 0x00020000U
6300 #define RTC_ALRMAR_HU_2 0x00040000U
6301 #define RTC_ALRMAR_HU_3 0x00080000U
6302 #define RTC_ALRMAR_MSK2 0x00008000U
6303 #define RTC_ALRMAR_MNT 0x00007000U
6304 #define RTC_ALRMAR_MNT_0 0x00001000U
6305 #define RTC_ALRMAR_MNT_1 0x00002000U
6306 #define RTC_ALRMAR_MNT_2 0x00004000U
6307 #define RTC_ALRMAR_MNU 0x00000F00U
6308 #define RTC_ALRMAR_MNU_0 0x00000100U
6309 #define RTC_ALRMAR_MNU_1 0x00000200U
6310 #define RTC_ALRMAR_MNU_2 0x00000400U
6311 #define RTC_ALRMAR_MNU_3 0x00000800U
6312 #define RTC_ALRMAR_MSK1 0x00000080U
6313 #define RTC_ALRMAR_ST 0x00000070U
6314 #define RTC_ALRMAR_ST_0 0x00000010U
6315 #define RTC_ALRMAR_ST_1 0x00000020U
6316 #define RTC_ALRMAR_ST_2 0x00000040U
6317 #define RTC_ALRMAR_SU 0x0000000FU
6318 #define RTC_ALRMAR_SU_0 0x00000001U
6319 #define RTC_ALRMAR_SU_1 0x00000002U
6320 #define RTC_ALRMAR_SU_2 0x00000004U
6321 #define RTC_ALRMAR_SU_3 0x00000008U
6322 
6323 /******************** Bits definition for RTC_ALRMBR register ***************/
6324 #define RTC_ALRMBR_MSK4 0x80000000U
6325 #define RTC_ALRMBR_WDSEL 0x40000000U
6326 #define RTC_ALRMBR_DT 0x30000000U
6327 #define RTC_ALRMBR_DT_0 0x10000000U
6328 #define RTC_ALRMBR_DT_1 0x20000000U
6329 #define RTC_ALRMBR_DU 0x0F000000U
6330 #define RTC_ALRMBR_DU_0 0x01000000U
6331 #define RTC_ALRMBR_DU_1 0x02000000U
6332 #define RTC_ALRMBR_DU_2 0x04000000U
6333 #define RTC_ALRMBR_DU_3 0x08000000U
6334 #define RTC_ALRMBR_MSK3 0x00800000U
6335 #define RTC_ALRMBR_PM 0x00400000U
6336 #define RTC_ALRMBR_HT 0x00300000U
6337 #define RTC_ALRMBR_HT_0 0x00100000U
6338 #define RTC_ALRMBR_HT_1 0x00200000U
6339 #define RTC_ALRMBR_HU 0x000F0000U
6340 #define RTC_ALRMBR_HU_0 0x00010000U
6341 #define RTC_ALRMBR_HU_1 0x00020000U
6342 #define RTC_ALRMBR_HU_2 0x00040000U
6343 #define RTC_ALRMBR_HU_3 0x00080000U
6344 #define RTC_ALRMBR_MSK2 0x00008000U
6345 #define RTC_ALRMBR_MNT 0x00007000U
6346 #define RTC_ALRMBR_MNT_0 0x00001000U
6347 #define RTC_ALRMBR_MNT_1 0x00002000U
6348 #define RTC_ALRMBR_MNT_2 0x00004000U
6349 #define RTC_ALRMBR_MNU 0x00000F00U
6350 #define RTC_ALRMBR_MNU_0 0x00000100U
6351 #define RTC_ALRMBR_MNU_1 0x00000200U
6352 #define RTC_ALRMBR_MNU_2 0x00000400U
6353 #define RTC_ALRMBR_MNU_3 0x00000800U
6354 #define RTC_ALRMBR_MSK1 0x00000080U
6355 #define RTC_ALRMBR_ST 0x00000070U
6356 #define RTC_ALRMBR_ST_0 0x00000010U
6357 #define RTC_ALRMBR_ST_1 0x00000020U
6358 #define RTC_ALRMBR_ST_2 0x00000040U
6359 #define RTC_ALRMBR_SU 0x0000000FU
6360 #define RTC_ALRMBR_SU_0 0x00000001U
6361 #define RTC_ALRMBR_SU_1 0x00000002U
6362 #define RTC_ALRMBR_SU_2 0x00000004U
6363 #define RTC_ALRMBR_SU_3 0x00000008U
6364 
6365 /******************** Bits definition for RTC_WPR register ******************/
6366 #define RTC_WPR_KEY 0x000000FFU
6367 
6368 /******************** Bits definition for RTC_SSR register ******************/
6369 #define RTC_SSR_SS 0x0000FFFFU
6370 
6371 /******************** Bits definition for RTC_SHIFTR register ***************/
6372 #define RTC_SHIFTR_SUBFS 0x00007FFFU
6373 #define RTC_SHIFTR_ADD1S 0x80000000U
6374 
6375 /******************** Bits definition for RTC_TSTR register *****************/
6376 #define RTC_TSTR_PM 0x00400000U
6377 #define RTC_TSTR_HT 0x00300000U
6378 #define RTC_TSTR_HT_0 0x00100000U
6379 #define RTC_TSTR_HT_1 0x00200000U
6380 #define RTC_TSTR_HU 0x000F0000U
6381 #define RTC_TSTR_HU_0 0x00010000U
6382 #define RTC_TSTR_HU_1 0x00020000U
6383 #define RTC_TSTR_HU_2 0x00040000U
6384 #define RTC_TSTR_HU_3 0x00080000U
6385 #define RTC_TSTR_MNT 0x00007000U
6386 #define RTC_TSTR_MNT_0 0x00001000U
6387 #define RTC_TSTR_MNT_1 0x00002000U
6388 #define RTC_TSTR_MNT_2 0x00004000U
6389 #define RTC_TSTR_MNU 0x00000F00U
6390 #define RTC_TSTR_MNU_0 0x00000100U
6391 #define RTC_TSTR_MNU_1 0x00000200U
6392 #define RTC_TSTR_MNU_2 0x00000400U
6393 #define RTC_TSTR_MNU_3 0x00000800U
6394 #define RTC_TSTR_ST 0x00000070U
6395 #define RTC_TSTR_ST_0 0x00000010U
6396 #define RTC_TSTR_ST_1 0x00000020U
6397 #define RTC_TSTR_ST_2 0x00000040U
6398 #define RTC_TSTR_SU 0x0000000FU
6399 #define RTC_TSTR_SU_0 0x00000001U
6400 #define RTC_TSTR_SU_1 0x00000002U
6401 #define RTC_TSTR_SU_2 0x00000004U
6402 #define RTC_TSTR_SU_3 0x00000008U
6403 
6404 /******************** Bits definition for RTC_TSDR register *****************/
6405 #define RTC_TSDR_WDU 0x0000E000U
6406 #define RTC_TSDR_WDU_0 0x00002000U
6407 #define RTC_TSDR_WDU_1 0x00004000U
6408 #define RTC_TSDR_WDU_2 0x00008000U
6409 #define RTC_TSDR_MT 0x00001000U
6410 #define RTC_TSDR_MU 0x00000F00U
6411 #define RTC_TSDR_MU_0 0x00000100U
6412 #define RTC_TSDR_MU_1 0x00000200U
6413 #define RTC_TSDR_MU_2 0x00000400U
6414 #define RTC_TSDR_MU_3 0x00000800U
6415 #define RTC_TSDR_DT 0x00000030U
6416 #define RTC_TSDR_DT_0 0x00000010U
6417 #define RTC_TSDR_DT_1 0x00000020U
6418 #define RTC_TSDR_DU 0x0000000FU
6419 #define RTC_TSDR_DU_0 0x00000001U
6420 #define RTC_TSDR_DU_1 0x00000002U
6421 #define RTC_TSDR_DU_2 0x00000004U
6422 #define RTC_TSDR_DU_3 0x00000008U
6423 
6424 /******************** Bits definition for RTC_TSSSR register ****************/
6425 #define RTC_TSSSR_SS 0x0000FFFFU
6426 
6427 /******************** Bits definition for RTC_CAL register *****************/
6428 #define RTC_CALR_CALP 0x00008000U
6429 #define RTC_CALR_CALW8 0x00004000U
6430 #define RTC_CALR_CALW16 0x00002000U
6431 #define RTC_CALR_CALM 0x000001FFU
6432 #define RTC_CALR_CALM_0 0x00000001U
6433 #define RTC_CALR_CALM_1 0x00000002U
6434 #define RTC_CALR_CALM_2 0x00000004U
6435 #define RTC_CALR_CALM_3 0x00000008U
6436 #define RTC_CALR_CALM_4 0x00000010U
6437 #define RTC_CALR_CALM_5 0x00000020U
6438 #define RTC_CALR_CALM_6 0x00000040U
6439 #define RTC_CALR_CALM_7 0x00000080U
6440 #define RTC_CALR_CALM_8 0x00000100U
6441 
6442 /******************** Bits definition for RTC_TAMPCR register ****************/
6443 #define RTC_TAMPCR_TAMP3MF 0x01000000U
6444 #define RTC_TAMPCR_TAMP3NOERASE 0x00800000U
6445 #define RTC_TAMPCR_TAMP3IE 0x00400000U
6446 #define RTC_TAMPCR_TAMP2MF 0x00200000U
6447 #define RTC_TAMPCR_TAMP2NOERASE 0x00100000U
6448 #define RTC_TAMPCR_TAMP2IE 0x00080000U
6449 #define RTC_TAMPCR_TAMP1MF 0x00040000U
6450 #define RTC_TAMPCR_TAMP1NOERASE 0x00020000U
6451 #define RTC_TAMPCR_TAMP1IE 0x00010000U
6452 #define RTC_TAMPCR_TAMPPUDIS 0x00008000U
6453 #define RTC_TAMPCR_TAMPPRCH 0x00006000U
6454 #define RTC_TAMPCR_TAMPPRCH_0 0x00002000U
6455 #define RTC_TAMPCR_TAMPPRCH_1 0x00004000U
6456 #define RTC_TAMPCR_TAMPFLT 0x00001800U
6457 #define RTC_TAMPCR_TAMPFLT_0 0x00000800U
6458 #define RTC_TAMPCR_TAMPFLT_1 0x00001000U
6459 #define RTC_TAMPCR_TAMPFREQ 0x00000700U
6460 #define RTC_TAMPCR_TAMPFREQ_0 0x00000100U
6461 #define RTC_TAMPCR_TAMPFREQ_1 0x00000200U
6462 #define RTC_TAMPCR_TAMPFREQ_2 0x00000400U
6463 #define RTC_TAMPCR_TAMPTS 0x00000080U
6464 #define RTC_TAMPCR_TAMP3TRG 0x00000040U
6465 #define RTC_TAMPCR_TAMP3E 0x00000020U
6466 #define RTC_TAMPCR_TAMP2TRG 0x00000010U
6467 #define RTC_TAMPCR_TAMP2E 0x00000008U
6468 #define RTC_TAMPCR_TAMPIE 0x00000004U
6469 #define RTC_TAMPCR_TAMP1TRG 0x00000002U
6470 #define RTC_TAMPCR_TAMP1E 0x00000001U
6471 
6472 /* Legacy defines */
6473 #define RTC_TAMPCR_TAMP3_TRG RTC_TAMPCR_TAMP3TRG
6474 #define RTC_TAMPCR_TAMP2_TRG RTC_TAMPCR_TAMP2TRG
6475 #define RTC_TAMPCR_TAMP1_TRG RTC_TAMPCR_TAMP1TRG
6476 
6477 /******************** Bits definition for RTC_ALRMASSR register *************/
6478 #define RTC_ALRMASSR_MASKSS 0x0F000000U
6479 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
6480 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
6481 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
6482 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
6483 #define RTC_ALRMASSR_SS 0x00007FFFU
6484 
6485 /******************** Bits definition for RTC_ALRMBSSR register *************/
6486 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
6487 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
6488 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
6489 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
6490 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
6491 #define RTC_ALRMBSSR_SS 0x00007FFFU
6492 
6493 /******************** Bits definition for RTC_OR register ****************/
6494 #define RTC_OR_TSINSEL 0x00000006U
6495 #define RTC_OR_TSINSEL_0 0x00000002U
6496 #define RTC_OR_TSINSEL_1 0x00000004U
6497 #define RTC_OR_ALARMTYPE 0x00000008U
6498 
6499 /******************** Bits definition for RTC_BKP0R register ****************/
6500 #define RTC_BKP0R 0xFFFFFFFFU
6501 
6502 /******************** Bits definition for RTC_BKP1R register ****************/
6503 #define RTC_BKP1R 0xFFFFFFFFU
6504 
6505 /******************** Bits definition for RTC_BKP2R register ****************/
6506 #define RTC_BKP2R 0xFFFFFFFFU
6507 
6508 /******************** Bits definition for RTC_BKP3R register ****************/
6509 #define RTC_BKP3R 0xFFFFFFFFU
6510 
6511 /******************** Bits definition for RTC_BKP4R register ****************/
6512 #define RTC_BKP4R 0xFFFFFFFFU
6513 
6514 /******************** Bits definition for RTC_BKP5R register ****************/
6515 #define RTC_BKP5R 0xFFFFFFFFU
6516 
6517 /******************** Bits definition for RTC_BKP6R register ****************/
6518 #define RTC_BKP6R 0xFFFFFFFFU
6519 
6520 /******************** Bits definition for RTC_BKP7R register ****************/
6521 #define RTC_BKP7R 0xFFFFFFFFU
6522 
6523 /******************** Bits definition for RTC_BKP8R register ****************/
6524 #define RTC_BKP8R 0xFFFFFFFFU
6525 
6526 /******************** Bits definition for RTC_BKP9R register ****************/
6527 #define RTC_BKP9R 0xFFFFFFFFU
6528 
6529 /******************** Bits definition for RTC_BKP10R register ***************/
6530 #define RTC_BKP10R 0xFFFFFFFFU
6531 
6532 /******************** Bits definition for RTC_BKP11R register ***************/
6533 #define RTC_BKP11R 0xFFFFFFFFU
6534 
6535 /******************** Bits definition for RTC_BKP12R register ***************/
6536 #define RTC_BKP12R 0xFFFFFFFFU
6537 
6538 /******************** Bits definition for RTC_BKP13R register ***************/
6539 #define RTC_BKP13R 0xFFFFFFFFU
6540 
6541 /******************** Bits definition for RTC_BKP14R register ***************/
6542 #define RTC_BKP14R 0xFFFFFFFFU
6543 
6544 /******************** Bits definition for RTC_BKP15R register ***************/
6545 #define RTC_BKP15R 0xFFFFFFFFU
6546 
6547 /******************** Bits definition for RTC_BKP16R register ***************/
6548 #define RTC_BKP16R 0xFFFFFFFFU
6549 
6550 /******************** Bits definition for RTC_BKP17R register ***************/
6551 #define RTC_BKP17R 0xFFFFFFFFU
6552 
6553 /******************** Bits definition for RTC_BKP18R register ***************/
6554 #define RTC_BKP18R 0xFFFFFFFFU
6555 
6556 /******************** Bits definition for RTC_BKP19R register ***************/
6557 #define RTC_BKP19R 0xFFFFFFFFU
6558 
6559 /******************** Bits definition for RTC_BKP20R register ***************/
6560 #define RTC_BKP20R 0xFFFFFFFFU
6561 
6562 /******************** Bits definition for RTC_BKP21R register ***************/
6563 #define RTC_BKP21R 0xFFFFFFFFU
6564 
6565 /******************** Bits definition for RTC_BKP22R register ***************/
6566 #define RTC_BKP22R 0xFFFFFFFFU
6567 
6568 /******************** Bits definition for RTC_BKP23R register ***************/
6569 #define RTC_BKP23R 0xFFFFFFFFU
6570 
6571 /******************** Bits definition for RTC_BKP24R register ***************/
6572 #define RTC_BKP24R 0xFFFFFFFFU
6573 
6574 /******************** Bits definition for RTC_BKP25R register ***************/
6575 #define RTC_BKP25R 0xFFFFFFFFU
6576 
6577 /******************** Bits definition for RTC_BKP26R register ***************/
6578 #define RTC_BKP26R 0xFFFFFFFFU
6579 
6580 /******************** Bits definition for RTC_BKP27R register ***************/
6581 #define RTC_BKP27R 0xFFFFFFFFU
6582 
6583 /******************** Bits definition for RTC_BKP28R register ***************/
6584 #define RTC_BKP28R 0xFFFFFFFFU
6585 
6586 /******************** Bits definition for RTC_BKP29R register ***************/
6587 #define RTC_BKP29R 0xFFFFFFFFU
6588 
6589 /******************** Bits definition for RTC_BKP30R register ***************/
6590 #define RTC_BKP30R 0xFFFFFFFFU
6591 
6592 /******************** Bits definition for RTC_BKP31R register ***************/
6593 #define RTC_BKP31R 0xFFFFFFFFU
6594 
6595 /******************** Number of backup registers ******************************/
6596 #define RTC_BKP_NUMBER 0x00000020U
6597 
6598 
6599 /******************************************************************************/
6600 /* */
6601 /* Serial Audio Interface */
6602 /* */
6603 /******************************************************************************/
6604 /******************** Bit definition for SAI_GCR register *******************/
6605 #define SAI_GCR_SYNCIN 0x00000003U
6606 #define SAI_GCR_SYNCIN_0 0x00000001U
6607 #define SAI_GCR_SYNCIN_1 0x00000002U
6609 #define SAI_GCR_SYNCOUT 0x00000030U
6610 #define SAI_GCR_SYNCOUT_0 0x00000010U
6611 #define SAI_GCR_SYNCOUT_1 0x00000020U
6613 /******************* Bit definition for SAI_xCR1 register *******************/
6614 #define SAI_xCR1_MODE 0x00000003U
6615 #define SAI_xCR1_MODE_0 0x00000001U
6616 #define SAI_xCR1_MODE_1 0x00000002U
6618 #define SAI_xCR1_PRTCFG 0x0000000CU
6619 #define SAI_xCR1_PRTCFG_0 0x00000004U
6620 #define SAI_xCR1_PRTCFG_1 0x00000008U
6622 #define SAI_xCR1_DS 0x000000E0U
6623 #define SAI_xCR1_DS_0 0x00000020U
6624 #define SAI_xCR1_DS_1 0x00000040U
6625 #define SAI_xCR1_DS_2 0x00000080U
6627 #define SAI_xCR1_LSBFIRST 0x00000100U
6628 #define SAI_xCR1_CKSTR 0x00000200U
6630 #define SAI_xCR1_SYNCEN 0x00000C00U
6631 #define SAI_xCR1_SYNCEN_0 0x00000400U
6632 #define SAI_xCR1_SYNCEN_1 0x00000800U
6634 #define SAI_xCR1_MONO 0x00001000U
6635 #define SAI_xCR1_OUTDRIV 0x00002000U
6636 #define SAI_xCR1_SAIEN 0x00010000U
6637 #define SAI_xCR1_DMAEN 0x00020000U
6638 #define SAI_xCR1_NODIV 0x00080000U
6640 #define SAI_xCR1_MCKDIV 0x00F00000U
6641 #define SAI_xCR1_MCKDIV_0 0x00100000U
6642 #define SAI_xCR1_MCKDIV_1 0x00200000U
6643 #define SAI_xCR1_MCKDIV_2 0x00400000U
6644 #define SAI_xCR1_MCKDIV_3 0x00800000U
6646 /******************* Bit definition for SAI_xCR2 register *******************/
6647 #define SAI_xCR2_FTH 0x00000007U
6648 #define SAI_xCR2_FTH_0 0x00000001U
6649 #define SAI_xCR2_FTH_1 0x00000002U
6650 #define SAI_xCR2_FTH_2 0x00000004U
6652 #define SAI_xCR2_FFLUSH 0x00000008U
6653 #define SAI_xCR2_TRIS 0x00000010U
6654 #define SAI_xCR2_MUTE 0x00000020U
6655 #define SAI_xCR2_MUTEVAL 0x00000040U
6657 #define SAI_xCR2_MUTECNT 0x00001F80U
6658 #define SAI_xCR2_MUTECNT_0 0x00000080U
6659 #define SAI_xCR2_MUTECNT_1 0x00000100U
6660 #define SAI_xCR2_MUTECNT_2 0x00000200U
6661 #define SAI_xCR2_MUTECNT_3 0x00000400U
6662 #define SAI_xCR2_MUTECNT_4 0x00000800U
6663 #define SAI_xCR2_MUTECNT_5 0x00001000U
6665 #define SAI_xCR2_CPL 0x00002000U
6667 #define SAI_xCR2_COMP 0x0000C000U
6668 #define SAI_xCR2_COMP_0 0x00004000U
6669 #define SAI_xCR2_COMP_1 0x00008000U
6671 /****************** Bit definition for SAI_xFRCR register *******************/
6672 #define SAI_xFRCR_FRL 0x000000FFU
6673 #define SAI_xFRCR_FRL_0 0x00000001U
6674 #define SAI_xFRCR_FRL_1 0x00000002U
6675 #define SAI_xFRCR_FRL_2 0x00000004U
6676 #define SAI_xFRCR_FRL_3 0x00000008U
6677 #define SAI_xFRCR_FRL_4 0x00000010U
6678 #define SAI_xFRCR_FRL_5 0x00000020U
6679 #define SAI_xFRCR_FRL_6 0x00000040U
6680 #define SAI_xFRCR_FRL_7 0x00000080U
6682 #define SAI_xFRCR_FSALL 0x00007F00U
6683 #define SAI_xFRCR_FSALL_0 0x00000100U
6684 #define SAI_xFRCR_FSALL_1 0x00000200U
6685 #define SAI_xFRCR_FSALL_2 0x00000400U
6686 #define SAI_xFRCR_FSALL_3 0x00000800U
6687 #define SAI_xFRCR_FSALL_4 0x00001000U
6688 #define SAI_xFRCR_FSALL_5 0x00002000U
6689 #define SAI_xFRCR_FSALL_6 0x00004000U
6691 #define SAI_xFRCR_FSDEF 0x00010000U
6692 #define SAI_xFRCR_FSPOL 0x00020000U
6693 #define SAI_xFRCR_FSOFF 0x00040000U
6695 /* Legacy define */
6696 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
6697 
6698 /****************** Bit definition for SAI_xSLOTR register *******************/
6699 #define SAI_xSLOTR_FBOFF 0x0000001FU
6700 #define SAI_xSLOTR_FBOFF_0 0x00000001U
6701 #define SAI_xSLOTR_FBOFF_1 0x00000002U
6702 #define SAI_xSLOTR_FBOFF_2 0x00000004U
6703 #define SAI_xSLOTR_FBOFF_3 0x00000008U
6704 #define SAI_xSLOTR_FBOFF_4 0x00000010U
6706 #define SAI_xSLOTR_SLOTSZ 0x000000C0U
6707 #define SAI_xSLOTR_SLOTSZ_0 0x00000040U
6708 #define SAI_xSLOTR_SLOTSZ_1 0x00000080U
6710 #define SAI_xSLOTR_NBSLOT 0x00000F00U
6711 #define SAI_xSLOTR_NBSLOT_0 0x00000100U
6712 #define SAI_xSLOTR_NBSLOT_1 0x00000200U
6713 #define SAI_xSLOTR_NBSLOT_2 0x00000400U
6714 #define SAI_xSLOTR_NBSLOT_3 0x00000800U
6716 #define SAI_xSLOTR_SLOTEN 0xFFFF0000U
6718 /******************* Bit definition for SAI_xIMR register *******************/
6719 #define SAI_xIMR_OVRUDRIE 0x00000001U
6720 #define SAI_xIMR_MUTEDETIE 0x00000002U
6721 #define SAI_xIMR_WCKCFGIE 0x00000004U
6722 #define SAI_xIMR_FREQIE 0x00000008U
6723 #define SAI_xIMR_CNRDYIE 0x00000010U
6724 #define SAI_xIMR_AFSDETIE 0x00000020U
6725 #define SAI_xIMR_LFSDETIE 0x00000040U
6727 /******************** Bit definition for SAI_xSR register *******************/
6728 #define SAI_xSR_OVRUDR 0x00000001U
6729 #define SAI_xSR_MUTEDET 0x00000002U
6730 #define SAI_xSR_WCKCFG 0x00000004U
6731 #define SAI_xSR_FREQ 0x00000008U
6732 #define SAI_xSR_CNRDY 0x00000010U
6733 #define SAI_xSR_AFSDET 0x00000020U
6734 #define SAI_xSR_LFSDET 0x00000040U
6736 #define SAI_xSR_FLVL 0x00070000U
6737 #define SAI_xSR_FLVL_0 0x00010000U
6738 #define SAI_xSR_FLVL_1 0x00020000U
6739 #define SAI_xSR_FLVL_2 0x00040000U
6741 /****************** Bit definition for SAI_xCLRFR register ******************/
6742 #define SAI_xCLRFR_COVRUDR 0x00000001U
6743 #define SAI_xCLRFR_CMUTEDET 0x00000002U
6744 #define SAI_xCLRFR_CWCKCFG 0x00000004U
6745 #define SAI_xCLRFR_CFREQ 0x00000008U
6746 #define SAI_xCLRFR_CCNRDY 0x00000010U
6747 #define SAI_xCLRFR_CAFSDET 0x00000020U
6748 #define SAI_xCLRFR_CLFSDET 0x00000040U
6750 /****************** Bit definition for SAI_xDR register *********************/
6751 #define SAI_xDR_DATA 0xFFFFFFFFU
6752 
6753 /******************************************************************************/
6754 /* */
6755 /* SPDIF-RX Interface */
6756 /* */
6757 /******************************************************************************/
6758 /******************** Bit definition for SPDIF_CR register *******************/
6759 #define SPDIFRX_CR_SPDIFEN 0x00000003U
6760 #define SPDIFRX_CR_RXDMAEN 0x00000004U
6761 #define SPDIFRX_CR_RXSTEO 0x00000008U
6762 #define SPDIFRX_CR_DRFMT 0x00000030U
6763 #define SPDIFRX_CR_PMSK 0x00000040U
6764 #define SPDIFRX_CR_VMSK 0x00000080U
6765 #define SPDIFRX_CR_CUMSK 0x00000100U
6766 #define SPDIFRX_CR_PTMSK 0x00000200U
6767 #define SPDIFRX_CR_CBDMAEN 0x00000400U
6768 #define SPDIFRX_CR_CHSEL 0x00000800U
6769 #define SPDIFRX_CR_NBTR 0x00003000U
6770 #define SPDIFRX_CR_WFA 0x00004000U
6771 #define SPDIFRX_CR_INSEL 0x00070000U
6773 /******************* Bit definition for SPDIFRX_IMR register *******************/
6774 #define SPDIFRX_IMR_RXNEIE 0x00000001U
6775 #define SPDIFRX_IMR_CSRNEIE 0x00000002U
6776 #define SPDIFRX_IMR_PERRIE 0x00000004U
6777 #define SPDIFRX_IMR_OVRIE 0x00000008U
6778 #define SPDIFRX_IMR_SBLKIE 0x00000010U
6779 #define SPDIFRX_IMR_SYNCDIE 0x00000020U
6780 #define SPDIFRX_IMR_IFEIE 0x00000040U
6782 /******************* Bit definition for SPDIFRX_SR register *******************/
6783 #define SPDIFRX_SR_RXNE 0x00000001U
6784 #define SPDIFRX_SR_CSRNE 0x00000002U
6785 #define SPDIFRX_SR_PERR 0x00000004U
6786 #define SPDIFRX_SR_OVR 0x00000008U
6787 #define SPDIFRX_SR_SBD 0x00000010U
6788 #define SPDIFRX_SR_SYNCD 0x00000020U
6789 #define SPDIFRX_SR_FERR 0x00000040U
6790 #define SPDIFRX_SR_SERR 0x00000080U
6791 #define SPDIFRX_SR_TERR 0x00000100U
6792 #define SPDIFRX_SR_WIDTH5 0x7FFF0000U
6794 /******************* Bit definition for SPDIFRX_IFCR register *******************/
6795 #define SPDIFRX_IFCR_PERRCF 0x00000004U
6796 #define SPDIFRX_IFCR_OVRCF 0x00000008U
6797 #define SPDIFRX_IFCR_SBDCF 0x00000010U
6798 #define SPDIFRX_IFCR_SYNCDCF 0x00000020U
6800 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
6801 #define SPDIFRX_DR0_DR 0x00FFFFFFU
6802 #define SPDIFRX_DR0_PE 0x01000000U
6803 #define SPDIFRX_DR0_V 0x02000000U
6804 #define SPDIFRX_DR0_U 0x04000000U
6805 #define SPDIFRX_DR0_C 0x08000000U
6806 #define SPDIFRX_DR0_PT 0x30000000U
6808 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
6809 #define SPDIFRX_DR1_DR 0xFFFFFF00U
6810 #define SPDIFRX_DR1_PT 0x00000030U
6811 #define SPDIFRX_DR1_C 0x00000008U
6812 #define SPDIFRX_DR1_U 0x00000004U
6813 #define SPDIFRX_DR1_V 0x00000002U
6814 #define SPDIFRX_DR1_PE 0x00000001U
6816 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
6817 #define SPDIFRX_DR1_DRNL1 0xFFFF0000U
6818 #define SPDIFRX_DR1_DRNL2 0x0000FFFFU
6820 /******************* Bit definition for SPDIFRX_CSR register *******************/
6821 #define SPDIFRX_CSR_USR 0x0000FFFFU
6822 #define SPDIFRX_CSR_CS 0x00FF0000U
6823 #define SPDIFRX_CSR_SOB 0x01000000U
6825 /******************* Bit definition for SPDIFRX_DIR register *******************/
6826 #define SPDIFRX_DIR_THI 0x000013FFU
6827 #define SPDIFRX_DIR_TLO 0x1FFF0000U
6830 /******************************************************************************/
6831 /* */
6832 /* SD host Interface */
6833 /* */
6834 /******************************************************************************/
6835 /****************** Bit definition for SDMMC_POWER register ******************/
6836 #define SDMMC_POWER_PWRCTRL 0x03U
6837 #define SDMMC_POWER_PWRCTRL_0 0x01U
6838 #define SDMMC_POWER_PWRCTRL_1 0x02U
6840 /****************** Bit definition for SDMMC_CLKCR register ******************/
6841 #define SDMMC_CLKCR_CLKDIV 0x00FFU
6842 #define SDMMC_CLKCR_CLKEN 0x0100U
6843 #define SDMMC_CLKCR_PWRSAV 0x0200U
6844 #define SDMMC_CLKCR_BYPASS 0x0400U
6846 #define SDMMC_CLKCR_WIDBUS 0x1800U
6847 #define SDMMC_CLKCR_WIDBUS_0 0x0800U
6848 #define SDMMC_CLKCR_WIDBUS_1 0x1000U
6850 #define SDMMC_CLKCR_NEGEDGE 0x2000U
6851 #define SDMMC_CLKCR_HWFC_EN 0x4000U
6853 /******************* Bit definition for SDMMC_ARG register *******************/
6854 #define SDMMC_ARG_CMDARG 0xFFFFFFFFU
6856 /******************* Bit definition for SDMMC_CMD register *******************/
6857 #define SDMMC_CMD_CMDINDEX 0x003FU
6859 #define SDMMC_CMD_WAITRESP 0x00C0U
6860 #define SDMMC_CMD_WAITRESP_0 0x0040U
6861 #define SDMMC_CMD_WAITRESP_1 0x0080U
6863 #define SDMMC_CMD_WAITINT 0x0100U
6864 #define SDMMC_CMD_WAITPEND 0x0200U
6865 #define SDMMC_CMD_CPSMEN 0x0400U
6866 #define SDMMC_CMD_SDIOSUSPEND 0x0800U
6868 /***************** Bit definition for SDMMC_RESPCMD register *****************/
6869 #define SDMMC_RESPCMD_RESPCMD 0x3FU
6871 /****************** Bit definition for SDMMC_RESP0 register ******************/
6872 #define SDMMC_RESP0_CARDSTATUS0 0xFFFFFFFFU
6874 /****************** Bit definition for SDMMC_RESP1 register ******************/
6875 #define SDMMC_RESP1_CARDSTATUS1 0xFFFFFFFFU
6877 /****************** Bit definition for SDMMC_RESP2 register ******************/
6878 #define SDMMC_RESP2_CARDSTATUS2 0xFFFFFFFFU
6880 /****************** Bit definition for SDMMC_RESP3 register ******************/
6881 #define SDMMC_RESP3_CARDSTATUS3 0xFFFFFFFFU
6883 /****************** Bit definition for SDMMC_RESP4 register ******************/
6884 #define SDMMC_RESP4_CARDSTATUS4 0xFFFFFFFFU
6886 /****************** Bit definition for SDMMC_DTIMER register *****************/
6887 #define SDMMC_DTIMER_DATATIME 0xFFFFFFFFU
6889 /****************** Bit definition for SDMMC_DLEN register *******************/
6890 #define SDMMC_DLEN_DATALENGTH 0x01FFFFFFU
6892 /****************** Bit definition for SDMMC_DCTRL register ******************/
6893 #define SDMMC_DCTRL_DTEN 0x0001U
6894 #define SDMMC_DCTRL_DTDIR 0x0002U
6895 #define SDMMC_DCTRL_DTMODE 0x0004U
6896 #define SDMMC_DCTRL_DMAEN 0x0008U
6898 #define SDMMC_DCTRL_DBLOCKSIZE 0x00F0U
6899 #define SDMMC_DCTRL_DBLOCKSIZE_0 0x0010U
6900 #define SDMMC_DCTRL_DBLOCKSIZE_1 0x0020U
6901 #define SDMMC_DCTRL_DBLOCKSIZE_2 0x0040U
6902 #define SDMMC_DCTRL_DBLOCKSIZE_3 0x0080U
6904 #define SDMMC_DCTRL_RWSTART 0x0100U
6905 #define SDMMC_DCTRL_RWSTOP 0x0200U
6906 #define SDMMC_DCTRL_RWMOD 0x0400U
6907 #define SDMMC_DCTRL_SDIOEN 0x0800U
6909 /****************** Bit definition for SDMMC_DCOUNT register *****************/
6910 #define SDMMC_DCOUNT_DATACOUNT 0x01FFFFFFU
6912 /****************** Bit definition for SDMMC_STA registe ********************/
6913 #define SDMMC_STA_CCRCFAIL 0x00000001U
6914 #define SDMMC_STA_DCRCFAIL 0x00000002U
6915 #define SDMMC_STA_CTIMEOUT 0x00000004U
6916 #define SDMMC_STA_DTIMEOUT 0x00000008U
6917 #define SDMMC_STA_TXUNDERR 0x00000010U
6918 #define SDMMC_STA_RXOVERR 0x00000020U
6919 #define SDMMC_STA_CMDREND 0x00000040U
6920 #define SDMMC_STA_CMDSENT 0x00000080U
6921 #define SDMMC_STA_DATAEND 0x00000100U
6922 #define SDMMC_STA_DBCKEND 0x00000400U
6923 #define SDMMC_STA_CMDACT 0x00000800U
6924 #define SDMMC_STA_TXACT 0x00001000U
6925 #define SDMMC_STA_RXACT 0x00002000U
6926 #define SDMMC_STA_TXFIFOHE 0x00004000U
6927 #define SDMMC_STA_RXFIFOHF 0x00008000U
6928 #define SDMMC_STA_TXFIFOF 0x00010000U
6929 #define SDMMC_STA_RXFIFOF 0x00020000U
6930 #define SDMMC_STA_TXFIFOE 0x00040000U
6931 #define SDMMC_STA_RXFIFOE 0x00080000U
6932 #define SDMMC_STA_TXDAVL 0x00100000U
6933 #define SDMMC_STA_RXDAVL 0x00200000U
6934 #define SDMMC_STA_SDIOIT 0x00400000U
6936 /******************* Bit definition for SDMMC_ICR register *******************/
6937 #define SDMMC_ICR_CCRCFAILC 0x00000001U
6938 #define SDMMC_ICR_DCRCFAILC 0x00000002U
6939 #define SDMMC_ICR_CTIMEOUTC 0x00000004U
6940 #define SDMMC_ICR_DTIMEOUTC 0x00000008U
6941 #define SDMMC_ICR_TXUNDERRC 0x00000010U
6942 #define SDMMC_ICR_RXOVERRC 0x00000020U
6943 #define SDMMC_ICR_CMDRENDC 0x00000040U
6944 #define SDMMC_ICR_CMDSENTC 0x00000080U
6945 #define SDMMC_ICR_DATAENDC 0x00000100U
6946 #define SDMMC_ICR_DBCKENDC 0x00000400U
6947 #define SDMMC_ICR_SDIOITC 0x00400000U
6949 /****************** Bit definition for SDMMC_MASK register *******************/
6950 #define SDMMC_MASK_CCRCFAILIE 0x00000001U
6951 #define SDMMC_MASK_DCRCFAILIE 0x00000002U
6952 #define SDMMC_MASK_CTIMEOUTIE 0x00000004U
6953 #define SDMMC_MASK_DTIMEOUTIE 0x00000008U
6954 #define SDMMC_MASK_TXUNDERRIE 0x00000010U
6955 #define SDMMC_MASK_RXOVERRIE 0x00000020U
6956 #define SDMMC_MASK_CMDRENDIE 0x00000040U
6957 #define SDMMC_MASK_CMDSENTIE 0x00000080U
6958 #define SDMMC_MASK_DATAENDIE 0x00000100U
6959 #define SDMMC_MASK_DBCKENDIE 0x00000400U
6960 #define SDMMC_MASK_CMDACTIE 0x00000800U
6961 #define SDMMC_MASK_TXACTIE 0x00001000U
6962 #define SDMMC_MASK_RXACTIE 0x00002000U
6963 #define SDMMC_MASK_TXFIFOHEIE 0x00004000U
6964 #define SDMMC_MASK_RXFIFOHFIE 0x00008000U
6965 #define SDMMC_MASK_TXFIFOFIE 0x00010000U
6966 #define SDMMC_MASK_RXFIFOFIE 0x00020000U
6967 #define SDMMC_MASK_TXFIFOEIE 0x00040000U
6968 #define SDMMC_MASK_RXFIFOEIE 0x00080000U
6969 #define SDMMC_MASK_TXDAVLIE 0x00100000U
6970 #define SDMMC_MASK_RXDAVLIE 0x00200000U
6971 #define SDMMC_MASK_SDIOITIE 0x00400000U
6973 /***************** Bit definition for SDMMC_FIFOCNT register *****************/
6974 #define SDMMC_FIFOCNT_FIFOCOUNT 0x00FFFFFFU
6976 /****************** Bit definition for SDMMC_FIFO register *******************/
6977 #define SDMMC_FIFO_FIFODATA 0xFFFFFFFFU
6979 /******************************************************************************/
6980 /* */
6981 /* Serial Peripheral Interface (SPI) */
6982 /* */
6983 /******************************************************************************/
6984 /******************* Bit definition for SPI_CR1 register ********************/
6985 #define SPI_CR1_CPHA 0x00000001U
6986 #define SPI_CR1_CPOL 0x00000002U
6987 #define SPI_CR1_MSTR 0x00000004U
6988 #define SPI_CR1_BR 0x00000038U
6989 #define SPI_CR1_BR_0 0x00000008U
6990 #define SPI_CR1_BR_1 0x00000010U
6991 #define SPI_CR1_BR_2 0x00000020U
6992 #define SPI_CR1_SPE 0x00000040U
6993 #define SPI_CR1_LSBFIRST 0x00000080U
6994 #define SPI_CR1_SSI 0x00000100U
6995 #define SPI_CR1_SSM 0x00000200U
6996 #define SPI_CR1_RXONLY 0x00000400U
6997 #define SPI_CR1_CRCL 0x00000800U
6998 #define SPI_CR1_CRCNEXT 0x00001000U
6999 #define SPI_CR1_CRCEN 0x00002000U
7000 #define SPI_CR1_BIDIOE 0x00004000U
7001 #define SPI_CR1_BIDIMODE 0x00008000U
7003 /******************* Bit definition for SPI_CR2 register ********************/
7004 #define SPI_CR2_RXDMAEN 0x00000001U
7005 #define SPI_CR2_TXDMAEN 0x00000002U
7006 #define SPI_CR2_SSOE 0x00000004U
7007 #define SPI_CR2_NSSP 0x00000008U
7008 #define SPI_CR2_FRF 0x00000010U
7009 #define SPI_CR2_ERRIE 0x00000020U
7010 #define SPI_CR2_RXNEIE 0x00000040U
7011 #define SPI_CR2_TXEIE 0x00000080U
7012 #define SPI_CR2_DS 0x00000F00U
7013 #define SPI_CR2_DS_0 0x00000100U
7014 #define SPI_CR2_DS_1 0x00000200U
7015 #define SPI_CR2_DS_2 0x00000400U
7016 #define SPI_CR2_DS_3 0x00000800U
7017 #define SPI_CR2_FRXTH 0x00001000U
7018 #define SPI_CR2_LDMARX 0x00002000U
7019 #define SPI_CR2_LDMATX 0x00004000U
7021 /******************** Bit definition for SPI_SR register ********************/
7022 #define SPI_SR_RXNE 0x00000001U
7023 #define SPI_SR_TXE 0x00000002U
7024 #define SPI_SR_CHSIDE 0x00000004U
7025 #define SPI_SR_UDR 0x00000008U
7026 #define SPI_SR_CRCERR 0x00000010U
7027 #define SPI_SR_MODF 0x00000020U
7028 #define SPI_SR_OVR 0x00000040U
7029 #define SPI_SR_BSY 0x00000080U
7030 #define SPI_SR_FRE 0x00000100U
7031 #define SPI_SR_FRLVL 0x00000600U
7032 #define SPI_SR_FRLVL_0 0x00000200U
7033 #define SPI_SR_FRLVL_1 0x00000400U
7034 #define SPI_SR_FTLVL 0x00001800U
7035 #define SPI_SR_FTLVL_0 0x00000800U
7036 #define SPI_SR_FTLVL_1 0x00001000U
7038 /******************** Bit definition for SPI_DR register ********************/
7039 #define SPI_DR_DR 0xFFFFU
7041 /******************* Bit definition for SPI_CRCPR register ******************/
7042 #define SPI_CRCPR_CRCPOLY 0xFFFFU
7044 /****************** Bit definition for SPI_RXCRCR register ******************/
7045 #define SPI_RXCRCR_RXCRC 0xFFFFU
7047 /****************** Bit definition for SPI_TXCRCR register ******************/
7048 #define SPI_TXCRCR_TXCRC 0xFFFFU
7050 /****************** Bit definition for SPI_I2SCFGR register *****************/
7051 #define SPI_I2SCFGR_CHLEN 0x00000001U
7052 #define SPI_I2SCFGR_DATLEN 0x00000006U
7053 #define SPI_I2SCFGR_DATLEN_0 0x00000002U
7054 #define SPI_I2SCFGR_DATLEN_1 0x00000004U
7055 #define SPI_I2SCFGR_CKPOL 0x00000008U
7056 #define SPI_I2SCFGR_I2SSTD 0x00000030U
7057 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U
7058 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U
7059 #define SPI_I2SCFGR_PCMSYNC 0x00000080U
7060 #define SPI_I2SCFGR_I2SCFG 0x00000300U
7061 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U
7062 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U
7063 #define SPI_I2SCFGR_I2SE 0x00000400U
7064 #define SPI_I2SCFGR_I2SMOD 0x00000800U
7065 #define SPI_I2SCFGR_ASTRTEN 0x00001000U
7067 /****************** Bit definition for SPI_I2SPR register *******************/
7068 #define SPI_I2SPR_I2SDIV 0x00FFU
7069 #define SPI_I2SPR_ODD 0x0100U
7070 #define SPI_I2SPR_MCKOE 0x0200U
7073 /******************************************************************************/
7074 /* */
7075 /* SYSCFG */
7076 /* */
7077 /******************************************************************************/
7078 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
7079 #define SYSCFG_MEMRMP_MEM_BOOT 0x00000001U
7082 #define SYSCFG_MEMRMP_SWP_FMC 0x00000C00U
7083 #define SYSCFG_MEMRMP_SWP_FMC_0 0x00000400U
7084 #define SYSCFG_MEMRMP_SWP_FMC_1 0x00000800U
7085 
7086 /****************** Bit definition for SYSCFG_PMC register ******************/
7087 
7088 #define SYSCFG_PMC_ADCxDC2 0x00070000U
7089 #define SYSCFG_PMC_ADC1DC2 0x00010000U
7090 #define SYSCFG_PMC_ADC2DC2 0x00020000U
7091 #define SYSCFG_PMC_ADC3DC2 0x00040000U
7093 #define SYSCFG_PMC_MII_RMII_SEL 0x00800000U
7095 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
7096 #define SYSCFG_EXTICR1_EXTI0 0x000FU
7097 #define SYSCFG_EXTICR1_EXTI1 0x00F0U
7098 #define SYSCFG_EXTICR1_EXTI2 0x0F00U
7099 #define SYSCFG_EXTICR1_EXTI3 0xF000U
7103 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
7104 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
7105 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
7106 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
7107 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
7108 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
7109 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
7110 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
7111 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U
7112 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U
7113 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU
7118 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
7119 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
7120 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
7121 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
7122 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
7123 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
7124 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
7125 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
7126 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U
7127 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U
7128 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U
7133 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
7134 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
7135 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
7136 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
7137 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
7138 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
7139 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
7140 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
7141 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U
7142 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U
7143 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U
7148 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
7149 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
7150 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
7151 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
7152 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
7153 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
7154 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
7155 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
7156 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U
7157 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U
7158 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U
7160 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
7161 #define SYSCFG_EXTICR2_EXTI4 0x000FU
7162 #define SYSCFG_EXTICR2_EXTI5 0x00F0U
7163 #define SYSCFG_EXTICR2_EXTI6 0x0F00U
7164 #define SYSCFG_EXTICR2_EXTI7 0xF000U
7168 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
7169 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
7170 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
7171 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
7172 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
7173 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
7174 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
7175 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
7176 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U
7177 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U
7178 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU
7183 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
7184 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
7185 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
7186 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
7187 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
7188 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
7189 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
7190 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
7191 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U
7192 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U
7193 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U
7198 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
7199 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
7200 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
7201 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
7202 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
7203 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
7204 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
7205 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
7206 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U
7207 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U
7208 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U
7213 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
7214 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
7215 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
7216 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
7217 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
7218 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
7219 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
7220 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
7221 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U
7222 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U
7223 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U
7225 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
7226 #define SYSCFG_EXTICR3_EXTI8 0x000FU
7227 #define SYSCFG_EXTICR3_EXTI9 0x00F0U
7228 #define SYSCFG_EXTICR3_EXTI10 0x0F00U
7229 #define SYSCFG_EXTICR3_EXTI11 0xF000U
7234 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
7235 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
7236 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
7237 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
7238 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
7239 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
7240 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
7241 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
7242 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U
7243 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U
7248 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
7249 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
7250 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
7251 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
7252 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
7253 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
7254 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
7255 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
7256 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U
7257 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U
7262 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
7263 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
7264 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
7265 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
7266 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
7267 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
7268 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
7269 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
7270 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U
7271 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U
7276 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
7277 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
7278 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
7279 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
7280 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
7281 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
7282 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
7283 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
7284 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U
7285 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U
7288 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
7289 #define SYSCFG_EXTICR4_EXTI12 0x000FU
7290 #define SYSCFG_EXTICR4_EXTI13 0x00F0U
7291 #define SYSCFG_EXTICR4_EXTI14 0x0F00U
7292 #define SYSCFG_EXTICR4_EXTI15 0xF000U
7296 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
7297 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
7298 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
7299 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
7300 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
7301 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
7302 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
7303 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
7304 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U
7305 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U
7310 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
7311 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
7312 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
7313 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
7314 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
7315 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
7316 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
7317 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
7318 #define SYSCFG_EXTICR4_EXTI13_PI 0x0080U
7319 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0090U
7324 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
7325 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
7326 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
7327 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
7328 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
7329 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
7330 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
7331 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
7332 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U
7333 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U
7338 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
7339 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
7340 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
7341 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
7342 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
7343 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
7344 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
7345 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
7346 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U
7347 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U
7350 /****************** Bit definition for SYSCFG_CMPCR register ****************/
7351 #define SYSCFG_CMPCR_CMP_PD 0x00000001U
7352 #define SYSCFG_CMPCR_READY 0x00000100U
7354 /******************************************************************************/
7355 /* */
7356 /* TIM */
7357 /* */
7358 /******************************************************************************/
7359 /******************* Bit definition for TIM_CR1 register ********************/
7360 #define TIM_CR1_CEN 0x0001U
7361 #define TIM_CR1_UDIS 0x0002U
7362 #define TIM_CR1_URS 0x0004U
7363 #define TIM_CR1_OPM 0x0008U
7364 #define TIM_CR1_DIR 0x0010U
7366 #define TIM_CR1_CMS 0x0060U
7367 #define TIM_CR1_CMS_0 0x0020U
7368 #define TIM_CR1_CMS_1 0x0040U
7370 #define TIM_CR1_ARPE 0x0080U
7372 #define TIM_CR1_CKD 0x0300U
7373 #define TIM_CR1_CKD_0 0x0100U
7374 #define TIM_CR1_CKD_1 0x0200U
7375 #define TIM_CR1_UIFREMAP 0x0800U
7377 /******************* Bit definition for TIM_CR2 register ********************/
7378 #define TIM_CR2_CCPC 0x00000001U
7379 #define TIM_CR2_CCUS 0x00000004U
7380 #define TIM_CR2_CCDS 0x00000008U
7382 #define TIM_CR2_OIS5 0x00010000U
7383 #define TIM_CR2_OIS6 0x00040000U
7385 #define TIM_CR2_MMS 0x0070U
7386 #define TIM_CR2_MMS_0 0x0010U
7387 #define TIM_CR2_MMS_1 0x0020U
7388 #define TIM_CR2_MMS_2 0x0040U
7390 #define TIM_CR2_MMS2 0x00F00000U
7391 #define TIM_CR2_MMS2_0 0x00100000U
7392 #define TIM_CR2_MMS2_1 0x00200000U
7393 #define TIM_CR2_MMS2_2 0x00400000U
7394 #define TIM_CR2_MMS2_3 0x00800000U
7396 #define TIM_CR2_TI1S 0x0080U
7397 #define TIM_CR2_OIS1 0x0100U
7398 #define TIM_CR2_OIS1N 0x0200U
7399 #define TIM_CR2_OIS2 0x0400U
7400 #define TIM_CR2_OIS2N 0x0800U
7401 #define TIM_CR2_OIS3 0x1000U
7402 #define TIM_CR2_OIS3N 0x2000U
7403 #define TIM_CR2_OIS4 0x4000U
7405 /******************* Bit definition for TIM_SMCR register *******************/
7406 #define TIM_SMCR_SMS 0x00010007U
7407 #define TIM_SMCR_SMS_0 0x00000001U
7408 #define TIM_SMCR_SMS_1 0x00000002U
7409 #define TIM_SMCR_SMS_2 0x00000004U
7410 #define TIM_SMCR_SMS_3 0x00010000U
7411 #define TIM_SMCR_OCCS 0x00000008U
7413 #define TIM_SMCR_TS 0x0070U
7414 #define TIM_SMCR_TS_0 0x0010U
7415 #define TIM_SMCR_TS_1 0x0020U
7416 #define TIM_SMCR_TS_2 0x0040U
7418 #define TIM_SMCR_MSM 0x0080U
7420 #define TIM_SMCR_ETF 0x0F00U
7421 #define TIM_SMCR_ETF_0 0x0100U
7422 #define TIM_SMCR_ETF_1 0x0200U
7423 #define TIM_SMCR_ETF_2 0x0400U
7424 #define TIM_SMCR_ETF_3 0x0800U
7426 #define TIM_SMCR_ETPS 0x3000U
7427 #define TIM_SMCR_ETPS_0 0x1000U
7428 #define TIM_SMCR_ETPS_1 0x2000U
7430 #define TIM_SMCR_ECE 0x4000U
7431 #define TIM_SMCR_ETP 0x8000U
7433 /******************* Bit definition for TIM_DIER register *******************/
7434 #define TIM_DIER_UIE 0x0001U
7435 #define TIM_DIER_CC1IE 0x0002U
7436 #define TIM_DIER_CC2IE 0x0004U
7437 #define TIM_DIER_CC3IE 0x0008U
7438 #define TIM_DIER_CC4IE 0x0010U
7439 #define TIM_DIER_COMIE 0x0020U
7440 #define TIM_DIER_TIE 0x0040U
7441 #define TIM_DIER_BIE 0x0080U
7442 #define TIM_DIER_UDE 0x0100U
7443 #define TIM_DIER_CC1DE 0x0200U
7444 #define TIM_DIER_CC2DE 0x0400U
7445 #define TIM_DIER_CC3DE 0x0800U
7446 #define TIM_DIER_CC4DE 0x1000U
7447 #define TIM_DIER_COMDE 0x2000U
7448 #define TIM_DIER_TDE 0x4000U
7450 /******************** Bit definition for TIM_SR register ********************/
7451 #define TIM_SR_UIF 0x0001U
7452 #define TIM_SR_CC1IF 0x0002U
7453 #define TIM_SR_CC2IF 0x0004U
7454 #define TIM_SR_CC3IF 0x0008U
7455 #define TIM_SR_CC4IF 0x0010U
7456 #define TIM_SR_COMIF 0x0020U
7457 #define TIM_SR_TIF 0x0040U
7458 #define TIM_SR_BIF 0x0080U
7459 #define TIM_SR_B2IF 0x0100U
7460 #define TIM_SR_CC1OF 0x0200U
7461 #define TIM_SR_CC2OF 0x0400U
7462 #define TIM_SR_CC3OF 0x0800U
7463 #define TIM_SR_CC4OF 0x1000U
7465 /******************* Bit definition for TIM_EGR register ********************/
7466 #define TIM_EGR_UG 0x00000001U
7467 #define TIM_EGR_CC1G 0x00000002U
7468 #define TIM_EGR_CC2G 0x00000004U
7469 #define TIM_EGR_CC3G 0x00000008U
7470 #define TIM_EGR_CC4G 0x00000010U
7471 #define TIM_EGR_COMG 0x00000020U
7472 #define TIM_EGR_TG 0x00000040U
7473 #define TIM_EGR_BG 0x00000080U
7474 #define TIM_EGR_B2G 0x00000100U
7476 /****************** Bit definition for TIM_CCMR1 register *******************/
7477 #define TIM_CCMR1_CC1S 0x00000003U
7478 #define TIM_CCMR1_CC1S_0 0x00000001U
7479 #define TIM_CCMR1_CC1S_1 0x00000002U
7481 #define TIM_CCMR1_OC1FE 0x00000004U
7482 #define TIM_CCMR1_OC1PE 0x00000008U
7484 #define TIM_CCMR1_OC1M 0x00010070U
7485 #define TIM_CCMR1_OC1M_0 0x00000010U
7486 #define TIM_CCMR1_OC1M_1 0x00000020U
7487 #define TIM_CCMR1_OC1M_2 0x00000040U
7488 #define TIM_CCMR1_OC1M_3 0x00010000U
7490 #define TIM_CCMR1_OC1CE 0x00000080U
7492 #define TIM_CCMR1_CC2S 0x00000300U
7493 #define TIM_CCMR1_CC2S_0 0x00000100U
7494 #define TIM_CCMR1_CC2S_1 0x00000200U
7496 #define TIM_CCMR1_OC2FE 0x00000400U
7497 #define TIM_CCMR1_OC2PE 0x00000800U
7499 #define TIM_CCMR1_OC2M 0x01007000U
7500 #define TIM_CCMR1_OC2M_0 0x00001000U
7501 #define TIM_CCMR1_OC2M_1 0x00002000U
7502 #define TIM_CCMR1_OC2M_2 0x00004000U
7503 #define TIM_CCMR1_OC2M_3 0x01000000U
7505 #define TIM_CCMR1_OC2CE 0x00008000U
7507 /*----------------------------------------------------------------------------*/
7508 
7509 #define TIM_CCMR1_IC1PSC 0x000CU
7510 #define TIM_CCMR1_IC1PSC_0 0x0004U
7511 #define TIM_CCMR1_IC1PSC_1 0x0008U
7513 #define TIM_CCMR1_IC1F 0x00F0U
7514 #define TIM_CCMR1_IC1F_0 0x0010U
7515 #define TIM_CCMR1_IC1F_1 0x0020U
7516 #define TIM_CCMR1_IC1F_2 0x0040U
7517 #define TIM_CCMR1_IC1F_3 0x0080U
7519 #define TIM_CCMR1_IC2PSC 0x0C00U
7520 #define TIM_CCMR1_IC2PSC_0 0x0400U
7521 #define TIM_CCMR1_IC2PSC_1 0x0800U
7523 #define TIM_CCMR1_IC2F 0xF000U
7524 #define TIM_CCMR1_IC2F_0 0x1000U
7525 #define TIM_CCMR1_IC2F_1 0x2000U
7526 #define TIM_CCMR1_IC2F_2 0x4000U
7527 #define TIM_CCMR1_IC2F_3 0x8000U
7529 /****************** Bit definition for TIM_CCMR2 register *******************/
7530 #define TIM_CCMR2_CC3S 0x00000003U
7531 #define TIM_CCMR2_CC3S_0 0x00000001U
7532 #define TIM_CCMR2_CC3S_1 0x00000002U
7534 #define TIM_CCMR2_OC3FE 0x00000004U
7535 #define TIM_CCMR2_OC3PE 0x00000008U
7537 #define TIM_CCMR2_OC3M 0x00010070U
7538 #define TIM_CCMR2_OC3M_0 0x00000010U
7539 #define TIM_CCMR2_OC3M_1 0x00000020U
7540 #define TIM_CCMR2_OC3M_2 0x00000040U
7541 #define TIM_CCMR2_OC3M_3 0x00010000U
7545 #define TIM_CCMR2_OC3CE 0x00000080U
7547 #define TIM_CCMR2_CC4S 0x00000300U
7548 #define TIM_CCMR2_CC4S_0 0x00000100U
7549 #define TIM_CCMR2_CC4S_1 0x00000200U
7551 #define TIM_CCMR2_OC4FE 0x00000400U
7552 #define TIM_CCMR2_OC4PE 0x00000800U
7554 #define TIM_CCMR2_OC4M 0x01007000U
7555 #define TIM_CCMR2_OC4M_0 0x00001000U
7556 #define TIM_CCMR2_OC4M_1 0x00002000U
7557 #define TIM_CCMR2_OC4M_2 0x00004000U
7558 #define TIM_CCMR2_OC4M_3 0x01000000U
7560 #define TIM_CCMR2_OC4CE 0x8000U
7562 /*----------------------------------------------------------------------------*/
7563 
7564 #define TIM_CCMR2_IC3PSC 0x000CU
7565 #define TIM_CCMR2_IC3PSC_0 0x0004U
7566 #define TIM_CCMR2_IC3PSC_1 0x0008U
7568 #define TIM_CCMR2_IC3F 0x00F0U
7569 #define TIM_CCMR2_IC3F_0 0x0010U
7570 #define TIM_CCMR2_IC3F_1 0x0020U
7571 #define TIM_CCMR2_IC3F_2 0x0040U
7572 #define TIM_CCMR2_IC3F_3 0x0080U
7574 #define TIM_CCMR2_IC4PSC 0x0C00U
7575 #define TIM_CCMR2_IC4PSC_0 0x0400U
7576 #define TIM_CCMR2_IC4PSC_1 0x0800U
7578 #define TIM_CCMR2_IC4F 0xF000U
7579 #define TIM_CCMR2_IC4F_0 0x1000U
7580 #define TIM_CCMR2_IC4F_1 0x2000U
7581 #define TIM_CCMR2_IC4F_2 0x4000U
7582 #define TIM_CCMR2_IC4F_3 0x8000U
7584 /******************* Bit definition for TIM_CCER register *******************/
7585 #define TIM_CCER_CC1E 0x00000001U
7586 #define TIM_CCER_CC1P 0x00000002U
7587 #define TIM_CCER_CC1NE 0x00000004U
7588 #define TIM_CCER_CC1NP 0x00000008U
7589 #define TIM_CCER_CC2E 0x00000010U
7590 #define TIM_CCER_CC2P 0x00000020U
7591 #define TIM_CCER_CC2NE 0x00000040U
7592 #define TIM_CCER_CC2NP 0x00000080U
7593 #define TIM_CCER_CC3E 0x00000100U
7594 #define TIM_CCER_CC3P 0x00000200U
7595 #define TIM_CCER_CC3NE 0x00000400U
7596 #define TIM_CCER_CC3NP 0x00000800U
7597 #define TIM_CCER_CC4E 0x00001000U
7598 #define TIM_CCER_CC4P 0x00002000U
7599 #define TIM_CCER_CC4NP 0x00008000U
7600 #define TIM_CCER_CC5E 0x00010000U
7601 #define TIM_CCER_CC5P 0x00020000U
7602 #define TIM_CCER_CC6E 0x00100000U
7603 #define TIM_CCER_CC6P 0x00200000U
7606 /******************* Bit definition for TIM_CNT register ********************/
7607 #define TIM_CNT_CNT 0xFFFFU
7609 /******************* Bit definition for TIM_PSC register ********************/
7610 #define TIM_PSC_PSC 0xFFFFU
7612 /******************* Bit definition for TIM_ARR register ********************/
7613 #define TIM_ARR_ARR 0xFFFFU
7615 /******************* Bit definition for TIM_RCR register ********************/
7616 #define TIM_RCR_REP ((uint8_t)0xFFU)
7618 /******************* Bit definition for TIM_CCR1 register *******************/
7619 #define TIM_CCR1_CCR1 0xFFFFU
7621 /******************* Bit definition for TIM_CCR2 register *******************/
7622 #define TIM_CCR2_CCR2 0xFFFFU
7624 /******************* Bit definition for TIM_CCR3 register *******************/
7625 #define TIM_CCR3_CCR3 0xFFFFU
7627 /******************* Bit definition for TIM_CCR4 register *******************/
7628 #define TIM_CCR4_CCR4 0xFFFFU
7630 /******************* Bit definition for TIM_BDTR register *******************/
7631 #define TIM_BDTR_DTG 0x000000FFU
7632 #define TIM_BDTR_DTG_0 0x00000001U
7633 #define TIM_BDTR_DTG_1 0x00000002U
7634 #define TIM_BDTR_DTG_2 0x00000004U
7635 #define TIM_BDTR_DTG_3 0x00000008U
7636 #define TIM_BDTR_DTG_4 0x00000010U
7637 #define TIM_BDTR_DTG_5 0x00000020U
7638 #define TIM_BDTR_DTG_6 0x00000040U
7639 #define TIM_BDTR_DTG_7 0x00000080U
7641 #define TIM_BDTR_LOCK 0x00000300U
7642 #define TIM_BDTR_LOCK_0 0x00000100U
7643 #define TIM_BDTR_LOCK_1 0x00000200U
7645 #define TIM_BDTR_OSSI 0x00000400U
7646 #define TIM_BDTR_OSSR 0x00000800U
7647 #define TIM_BDTR_BKE 0x00001000U
7648 #define TIM_BDTR_BKP 0x00002000U
7649 #define TIM_BDTR_AOE 0x00004000U
7650 #define TIM_BDTR_MOE 0x00008000U
7651 #define TIM_BDTR_BKF 0x000F0000U
7652 #define TIM_BDTR_BK2F 0x00F00000U
7653 #define TIM_BDTR_BK2E 0x01000000U
7654 #define TIM_BDTR_BK2P 0x02000000U
7656 /******************* Bit definition for TIM_DCR register ********************/
7657 #define TIM_DCR_DBA 0x001FU
7658 #define TIM_DCR_DBA_0 0x0001U
7659 #define TIM_DCR_DBA_1 0x0002U
7660 #define TIM_DCR_DBA_2 0x0004U
7661 #define TIM_DCR_DBA_3 0x0008U
7662 #define TIM_DCR_DBA_4 0x0010U
7664 #define TIM_DCR_DBL 0x1F00U
7665 #define TIM_DCR_DBL_0 0x0100U
7666 #define TIM_DCR_DBL_1 0x0200U
7667 #define TIM_DCR_DBL_2 0x0400U
7668 #define TIM_DCR_DBL_3 0x0800U
7669 #define TIM_DCR_DBL_4 0x1000U
7671 /******************* Bit definition for TIM_DMAR register *******************/
7672 #define TIM_DMAR_DMAB 0xFFFFU
7674 /******************* Bit definition for TIM_OR regiter *********************/
7675 #define TIM_OR_TI4_RMP 0x00C0U
7676 #define TIM_OR_TI4_RMP_0 0x0040U
7677 #define TIM_OR_TI4_RMP_1 0x0080U
7678 #define TIM_OR_ITR1_RMP 0x0C00U
7679 #define TIM_OR_ITR1_RMP_0 0x0400U
7680 #define TIM_OR_ITR1_RMP_1 0x0800U
7682 /****************** Bit definition for TIM_CCMR3 register *******************/
7683 #define TIM_CCMR3_OC5FE 0x00000004U
7684 #define TIM_CCMR3_OC5PE 0x00000008U
7686 #define TIM_CCMR3_OC5M 0x00010070U
7687 #define TIM_CCMR3_OC5M_0 0x00000010U
7688 #define TIM_CCMR3_OC5M_1 0x00000020U
7689 #define TIM_CCMR3_OC5M_2 0x00000040U
7690 #define TIM_CCMR3_OC5M_3 0x00010000U
7692 #define TIM_CCMR3_OC5CE 0x00000080U
7694 #define TIM_CCMR3_OC6FE 0x00000400U
7695 #define TIM_CCMR3_OC6PE 0x00000800U
7697 #define TIM_CCMR3_OC6M 0x01007000U
7698 #define TIM_CCMR3_OC6M_0 0x00001000U
7699 #define TIM_CCMR3_OC6M_1 0x00002000U
7700 #define TIM_CCMR3_OC6M_2 0x00004000U
7701 #define TIM_CCMR3_OC6M_3 0x01000000U
7703 #define TIM_CCMR3_OC6CE 0x00008000U
7705 /******************* Bit definition for TIM_CCR5 register *******************/
7706 #define TIM_CCR5_CCR5 0xFFFFFFFFU
7707 #define TIM_CCR5_GC5C1 0x20000000U
7708 #define TIM_CCR5_GC5C2 0x40000000U
7709 #define TIM_CCR5_GC5C3 0x80000000U
7711 /******************* Bit definition for TIM_CCR6 register *******************/
7712 #define TIM_CCR6_CCR6 ((uint16_t)0xFFFFU)
7715 /******************************************************************************/
7716 /* */
7717 /* Low Power Timer (LPTIM) */
7718 /* */
7719 /******************************************************************************/
7720 /****************** Bit definition for LPTIM_ISR register *******************/
7721 #define LPTIM_ISR_CMPM 0x00000001U
7722 #define LPTIM_ISR_ARRM 0x00000002U
7723 #define LPTIM_ISR_EXTTRIG 0x00000004U
7724 #define LPTIM_ISR_CMPOK 0x00000008U
7725 #define LPTIM_ISR_ARROK 0x00000010U
7726 #define LPTIM_ISR_UP 0x00000020U
7727 #define LPTIM_ISR_DOWN 0x00000040U
7729 /****************** Bit definition for LPTIM_ICR register *******************/
7730 #define LPTIM_ICR_CMPMCF 0x00000001U
7731 #define LPTIM_ICR_ARRMCF 0x00000002U
7732 #define LPTIM_ICR_EXTTRIGCF 0x00000004U
7733 #define LPTIM_ICR_CMPOKCF 0x00000008U
7734 #define LPTIM_ICR_ARROKCF 0x00000010U
7735 #define LPTIM_ICR_UPCF 0x00000020U
7736 #define LPTIM_ICR_DOWNCF 0x00000040U
7738 /****************** Bit definition for LPTIM_IER register *******************/
7739 #define LPTIM_IER_CMPMIE 0x00000001U
7740 #define LPTIM_IER_ARRMIE 0x00000002U
7741 #define LPTIM_IER_EXTTRIGIE 0x00000004U
7742 #define LPTIM_IER_CMPOKIE 0x00000008U
7743 #define LPTIM_IER_ARROKIE 0x00000010U
7744 #define LPTIM_IER_UPIE 0x00000020U
7745 #define LPTIM_IER_DOWNIE 0x00000040U
7747 /****************** Bit definition for LPTIM_CFGR register*******************/
7748 #define LPTIM_CFGR_CKSEL 0x00000001U
7750 #define LPTIM_CFGR_CKPOL 0x00000006U
7751 #define LPTIM_CFGR_CKPOL_0 0x00000002U
7752 #define LPTIM_CFGR_CKPOL_1 0x00000004U
7754 #define LPTIM_CFGR_CKFLT 0x00000018U
7755 #define LPTIM_CFGR_CKFLT_0 0x00000008U
7756 #define LPTIM_CFGR_CKFLT_1 0x00000010U
7758 #define LPTIM_CFGR_TRGFLT 0x000000C0U
7759 #define LPTIM_CFGR_TRGFLT_0 0x00000040U
7760 #define LPTIM_CFGR_TRGFLT_1 0x00000080U
7762 #define LPTIM_CFGR_PRESC 0x00000E00U
7763 #define LPTIM_CFGR_PRESC_0 0x00000200U
7764 #define LPTIM_CFGR_PRESC_1 0x00000400U
7765 #define LPTIM_CFGR_PRESC_2 0x00000800U
7767 #define LPTIM_CFGR_TRIGSEL 0x0000E000U
7768 #define LPTIM_CFGR_TRIGSEL_0 0x00002000U
7769 #define LPTIM_CFGR_TRIGSEL_1 0x00004000U
7770 #define LPTIM_CFGR_TRIGSEL_2 0x00008000U
7772 #define LPTIM_CFGR_TRIGEN 0x00060000U
7773 #define LPTIM_CFGR_TRIGEN_0 0x00020000U
7774 #define LPTIM_CFGR_TRIGEN_1 0x00040000U
7776 #define LPTIM_CFGR_TIMOUT 0x00080000U
7777 #define LPTIM_CFGR_WAVE 0x00100000U
7778 #define LPTIM_CFGR_WAVPOL 0x00200000U
7779 #define LPTIM_CFGR_PRELOAD 0x00400000U
7780 #define LPTIM_CFGR_COUNTMODE 0x00800000U
7781 #define LPTIM_CFGR_ENC 0x01000000U
7783 /****************** Bit definition for LPTIM_CR register ********************/
7784 #define LPTIM_CR_ENABLE 0x00000001U
7785 #define LPTIM_CR_SNGSTRT 0x00000002U
7786 #define LPTIM_CR_CNTSTRT 0x00000004U
7788 /****************** Bit definition for LPTIM_CMP register *******************/
7789 #define LPTIM_CMP_CMP 0x0000FFFFU
7791 /****************** Bit definition for LPTIM_ARR register *******************/
7792 #define LPTIM_ARR_ARR 0x0000FFFFU
7794 /****************** Bit definition for LPTIM_CNT register *******************/
7795 #define LPTIM_CNT_CNT 0x0000FFFFU
7796 /******************************************************************************/
7797 /* */
7798 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
7799 /* */
7800 /******************************************************************************/
7801 /****************** Bit definition for USART_CR1 register *******************/
7802 #define USART_CR1_UE 0x00000001U
7803 #define USART_CR1_RE 0x00000004U
7804 #define USART_CR1_TE 0x00000008U
7805 #define USART_CR1_IDLEIE 0x00000010U
7806 #define USART_CR1_RXNEIE 0x00000020U
7807 #define USART_CR1_TCIE 0x00000040U
7808 #define USART_CR1_TXEIE 0x00000080U
7809 #define USART_CR1_PEIE 0x00000100U
7810 #define USART_CR1_PS 0x00000200U
7811 #define USART_CR1_PCE 0x00000400U
7812 #define USART_CR1_WAKE 0x00000800U
7813 #define USART_CR1_M 0x10001000U
7814 #define USART_CR1_M_0 0x00001000U
7815 #define USART_CR1_MME 0x00002000U
7816 #define USART_CR1_CMIE 0x00004000U
7817 #define USART_CR1_OVER8 0x00008000U
7818 #define USART_CR1_DEDT 0x001F0000U
7819 #define USART_CR1_DEDT_0 0x00010000U
7820 #define USART_CR1_DEDT_1 0x00020000U
7821 #define USART_CR1_DEDT_2 0x00040000U
7822 #define USART_CR1_DEDT_3 0x00080000U
7823 #define USART_CR1_DEDT_4 0x00100000U
7824 #define USART_CR1_DEAT 0x03E00000U
7825 #define USART_CR1_DEAT_0 0x00200000U
7826 #define USART_CR1_DEAT_1 0x00400000U
7827 #define USART_CR1_DEAT_2 0x00800000U
7828 #define USART_CR1_DEAT_3 0x01000000U
7829 #define USART_CR1_DEAT_4 0x02000000U
7830 #define USART_CR1_RTOIE 0x04000000U
7831 #define USART_CR1_EOBIE 0x08000000U
7832 #define USART_CR1_M_1 0x10000000U
7834 /****************** Bit definition for USART_CR2 register *******************/
7835 #define USART_CR2_ADDM7 0x00000010U
7836 #define USART_CR2_LBDL 0x00000020U
7837 #define USART_CR2_LBDIE 0x00000040U
7838 #define USART_CR2_LBCL 0x00000100U
7839 #define USART_CR2_CPHA 0x00000200U
7840 #define USART_CR2_CPOL 0x00000400U
7841 #define USART_CR2_CLKEN 0x00000800U
7842 #define USART_CR2_STOP 0x00003000U
7843 #define USART_CR2_STOP_0 0x00001000U
7844 #define USART_CR2_STOP_1 0x00002000U
7845 #define USART_CR2_LINEN 0x00004000U
7846 #define USART_CR2_SWAP 0x00008000U
7847 #define USART_CR2_RXINV 0x00010000U
7848 #define USART_CR2_TXINV 0x00020000U
7849 #define USART_CR2_DATAINV 0x00040000U
7850 #define USART_CR2_MSBFIRST 0x00080000U
7851 #define USART_CR2_ABREN 0x00100000U
7852 #define USART_CR2_ABRMODE 0x00600000U
7853 #define USART_CR2_ABRMODE_0 0x00200000U
7854 #define USART_CR2_ABRMODE_1 0x00400000U
7855 #define USART_CR2_RTOEN 0x00800000U
7856 #define USART_CR2_ADD 0xFF000000U
7858 /****************** Bit definition for USART_CR3 register *******************/
7859 #define USART_CR3_EIE 0x00000001U
7860 #define USART_CR3_IREN 0x00000002U
7861 #define USART_CR3_IRLP 0x00000004U
7862 #define USART_CR3_HDSEL 0x00000008U
7863 #define USART_CR3_NACK 0x00000010U
7864 #define USART_CR3_SCEN 0x00000020U
7865 #define USART_CR3_DMAR 0x00000040U
7866 #define USART_CR3_DMAT 0x00000080U
7867 #define USART_CR3_RTSE 0x00000100U
7868 #define USART_CR3_CTSE 0x00000200U
7869 #define USART_CR3_CTSIE 0x00000400U
7870 #define USART_CR3_ONEBIT 0x00000800U
7871 #define USART_CR3_OVRDIS 0x00001000U
7872 #define USART_CR3_DDRE 0x00002000U
7873 #define USART_CR3_DEM 0x00004000U
7874 #define USART_CR3_DEP 0x00008000U
7875 #define USART_CR3_SCARCNT 0x000E0000U
7876 #define USART_CR3_SCARCNT_0 0x00020000U
7877 #define USART_CR3_SCARCNT_1 0x00040000U
7878 #define USART_CR3_SCARCNT_2 0x00080000U
7881 /****************** Bit definition for USART_BRR register *******************/
7882 #define USART_BRR_DIV_FRACTION 0x000FU
7883 #define USART_BRR_DIV_MANTISSA 0xFFF0U
7885 /****************** Bit definition for USART_GTPR register ******************/
7886 #define USART_GTPR_PSC 0x00FFU
7887 #define USART_GTPR_GT 0xFF00U
7890 /******************* Bit definition for USART_RTOR register *****************/
7891 #define USART_RTOR_RTO 0x00FFFFFFU
7892 #define USART_RTOR_BLEN 0xFF000000U
7894 /******************* Bit definition for USART_RQR register ******************/
7895 #define USART_RQR_ABRRQ 0x0001U
7896 #define USART_RQR_SBKRQ 0x0002U
7897 #define USART_RQR_MMRQ 0x0004U
7898 #define USART_RQR_RXFRQ 0x0008U
7899 #define USART_RQR_TXFRQ 0x0010U
7901 /******************* Bit definition for USART_ISR register ******************/
7902 #define USART_ISR_PE 0x00000001U
7903 #define USART_ISR_FE 0x00000002U
7904 #define USART_ISR_NE 0x00000004U
7905 #define USART_ISR_ORE 0x00000008U
7906 #define USART_ISR_IDLE 0x00000010U
7907 #define USART_ISR_RXNE 0x00000020U
7908 #define USART_ISR_TC 0x00000040U
7909 #define USART_ISR_TXE 0x00000080U
7910 #define USART_ISR_LBDF 0x00000100U
7911 #define USART_ISR_CTSIF 0x00000200U
7912 #define USART_ISR_CTS 0x00000400U
7913 #define USART_ISR_RTOF 0x00000800U
7914 #define USART_ISR_EOBF 0x00001000U
7915 #define USART_ISR_ABRE 0x00004000U
7916 #define USART_ISR_ABRF 0x00008000U
7917 #define USART_ISR_BUSY 0x00010000U
7918 #define USART_ISR_CMF 0x00020000U
7919 #define USART_ISR_SBKF 0x00040000U
7920 #define USART_ISR_RWU 0x00080000U
7921 #define USART_ISR_WUF 0x00100000U
7922 #define USART_ISR_TEACK 0x00200000U
7923 #define USART_ISR_REACK 0x00400000U
7925 /* Legacy define */
7926 #define USART_ISR_LBD USART_ISR_LBDF
7927 
7928 /******************* Bit definition for USART_ICR register ******************/
7929 #define USART_ICR_PECF 0x00000001U
7930 #define USART_ICR_FECF 0x00000002U
7931 #define USART_ICR_NCF 0x00000004U
7932 #define USART_ICR_ORECF 0x00000008U
7933 #define USART_ICR_IDLECF 0x00000010U
7934 #define USART_ICR_TCCF 0x00000040U
7935 #define USART_ICR_LBDCF 0x00000100U
7936 #define USART_ICR_CTSCF 0x00000200U
7937 #define USART_ICR_RTOCF 0x00000800U
7938 #define USART_ICR_EOBCF 0x00001000U
7939 #define USART_ICR_CMCF 0x00020000U
7940 #define USART_ICR_WUCF 0x00100000U
7942 /******************* Bit definition for USART_RDR register ******************/
7943 #define USART_RDR_RDR 0x01FFU
7945 /******************* Bit definition for USART_TDR register ******************/
7946 #define USART_TDR_TDR 0x01FFU
7948 /******************************************************************************/
7949 /* */
7950 /* Window WATCHDOG */
7951 /* */
7952 /******************************************************************************/
7953 /******************* Bit definition for WWDG_CR register ********************/
7954 #define WWDG_CR_T 0x7FU
7955 #define WWDG_CR_T_0 0x01U
7956 #define WWDG_CR_T_1 0x02U
7957 #define WWDG_CR_T_2 0x04U
7958 #define WWDG_CR_T_3 0x08U
7959 #define WWDG_CR_T_4 0x10U
7960 #define WWDG_CR_T_5 0x20U
7961 #define WWDG_CR_T_6 0x40U
7963 /* Legacy defines */
7964 #define WWDG_CR_T0 WWDG_CR_T_0
7965 #define WWDG_CR_T1 WWDG_CR_T_1
7966 #define WWDG_CR_T2 WWDG_CR_T_2
7967 #define WWDG_CR_T3 WWDG_CR_T_3
7968 #define WWDG_CR_T4 WWDG_CR_T_4
7969 #define WWDG_CR_T5 WWDG_CR_T_5
7970 #define WWDG_CR_T6 WWDG_CR_T_6
7972 #define WWDG_CR_WDGA 0x80U
7974 /******************* Bit definition for WWDG_CFR register *******************/
7975 #define WWDG_CFR_W 0x007FU
7976 #define WWDG_CFR_W_0 0x0001U
7977 #define WWDG_CFR_W_1 0x0002U
7978 #define WWDG_CFR_W_2 0x0004U
7979 #define WWDG_CFR_W_3 0x0008U
7980 #define WWDG_CFR_W_4 0x0010U
7981 #define WWDG_CFR_W_5 0x0020U
7982 #define WWDG_CFR_W_6 0x0040U
7984 /* Legacy defines */
7985 #define WWDG_CFR_W0 WWDG_CFR_W_0
7986 #define WWDG_CFR_W1 WWDG_CFR_W_1
7987 #define WWDG_CFR_W2 WWDG_CFR_W_2
7988 #define WWDG_CFR_W3 WWDG_CFR_W_3
7989 #define WWDG_CFR_W4 WWDG_CFR_W_4
7990 #define WWDG_CFR_W5 WWDG_CFR_W_5
7991 #define WWDG_CFR_W6 WWDG_CFR_W_6
7993 #define WWDG_CFR_WDGTB 0x0180U
7994 #define WWDG_CFR_WDGTB_0 0x0080U
7995 #define WWDG_CFR_WDGTB_1 0x0100U
7997 /* Legacy defines */
7998 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
7999 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
8001 #define WWDG_CFR_EWI 0x0200U
8003 /******************* Bit definition for WWDG_SR register ********************/
8004 #define WWDG_SR_EWIF 0x01U
8006 /******************************************************************************/
8007 /* */
8008 /* DBG */
8009 /* */
8010 /******************************************************************************/
8011 /******************** Bit definition for DBGMCU_IDCODE register *************/
8012 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
8013 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
8014 
8015 /******************** Bit definition for DBGMCU_CR register *****************/
8016 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
8017 #define DBGMCU_CR_DBG_STOP 0x00000002U
8018 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
8019 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
8020 
8021 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
8022 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U
8023 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U
8025 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
8026 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
8027 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
8028 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
8029 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
8030 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
8031 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
8032 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
8033 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
8034 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
8035 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
8036 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
8037 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
8038 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
8039 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
8040 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
8041 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
8042 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
8043 
8044 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
8045 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
8046 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
8047 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
8048 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
8049 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
8050 
8051 /******************************************************************************/
8052 /* */
8053 /* Ethernet MAC Registers bits definitions */
8054 /* */
8055 /******************************************************************************/
8056 /* Bit definition for Ethernet MAC Control Register register */
8057 #define ETH_MACCR_WD 0x00800000U /* Watchdog disable */
8058 #define ETH_MACCR_JD 0x00400000U /* Jabber disable */
8059 #define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */
8060 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
8061 #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
8062 #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
8063 #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
8064 #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
8065 #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
8066 #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
8067 #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
8068 #define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */
8069 #define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */
8070 #define ETH_MACCR_ROD 0x00002000U /* Receive own disable */
8071 #define ETH_MACCR_LM 0x00001000U /* loopback mode */
8072 #define ETH_MACCR_DM 0x00000800U /* Duplex mode */
8073 #define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */
8074 #define ETH_MACCR_RD 0x00000200U /* Retry disable */
8075 #define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */
8076 #define ETH_MACCR_BL 0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling
8077  a transmission attempt during retries after a collision: 0 =< r <2^k */
8078 #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
8079 #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
8080 #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
8081 #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
8082 #define ETH_MACCR_DC 0x00000010U /* Defferal check */
8083 #define ETH_MACCR_TE 0x00000008U /* Transmitter enable */
8084 #define ETH_MACCR_RE 0x00000004U /* Receiver enable */
8085 
8086 /* Bit definition for Ethernet MAC Frame Filter Register */
8087 #define ETH_MACFFR_RA 0x80000000U /* Receive all */
8088 #define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */
8089 #define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */
8090 #define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */
8091 #define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */
8092 #define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */
8093 #define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
8094 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
8095 #define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */
8096 #define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */
8097 #define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */
8098 #define ETH_MACFFR_HM 0x00000004U /* Hash multicast */
8099 #define ETH_MACFFR_HU 0x00000002U /* Hash unicast */
8100 #define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */
8101 
8102 /* Bit definition for Ethernet MAC Hash Table High Register */
8103 #define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */
8104 
8105 /* Bit definition for Ethernet MAC Hash Table Low Register */
8106 #define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */
8107 
8108 /* Bit definition for Ethernet MAC MII Address Register */
8109 #define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */
8110 #define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */
8111 #define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */
8112 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
8113 #define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
8114 #define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
8115 #define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
8116 #define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
8117 #define ETH_MACMIIAR_MW 0x00000002U /* MII write */
8118 #define ETH_MACMIIAR_MB 0x00000001U /* MII busy */
8119 
8120 /* Bit definition for Ethernet MAC MII Data Register */
8121 #define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */
8122 
8123 /* Bit definition for Ethernet MAC Flow Control Register */
8124 #define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */
8125 #define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */
8126 #define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */
8127 #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
8128 #define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */
8129 #define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */
8130 #define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */
8131 #define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */
8132 #define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */
8133 #define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */
8134 #define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */
8135 
8136 /* Bit definition for Ethernet MAC VLAN Tag Register */
8137 #define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */
8138 #define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */
8139 
8140 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
8141 #define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */
8142 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
8143  Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
8144 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
8145  Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
8146  Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
8147  Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
8148  Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
8149  RSVD - Filter1 Command - RSVD - Filter0 Command
8150  Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
8151  Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
8152  Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
8153 
8154 /* Bit definition for Ethernet MAC PMT Control and Status Register */
8155 #define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
8156 #define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */
8157 #define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */
8158 #define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */
8159 #define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */
8160 #define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */
8161 #define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */
8162 
8163 /* Bit definition for Ethernet MAC Status Register */
8164 #define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */
8165 #define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */
8166 #define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */
8167 #define ETH_MACSR_MMCS 0x00000010U /* MMC status */
8168 #define ETH_MACSR_PMTS 0x00000008U /* PMT status */
8169 
8170 /* Bit definition for Ethernet MAC Interrupt Mask Register */
8171 #define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */
8172 #define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */
8173 
8174 /* Bit definition for Ethernet MAC Address0 High Register */
8175 #define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */
8176 
8177 /* Bit definition for Ethernet MAC Address0 Low Register */
8178 #define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */
8179 
8180 /* Bit definition for Ethernet MAC Address1 High Register */
8181 #define ETH_MACA1HR_AE 0x80000000U /* Address enable */
8182 #define ETH_MACA1HR_SA 0x40000000U /* Source address */
8183 #define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
8184  #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
8185  #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
8186  #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
8187  #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
8188  #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
8189  #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
8190 #define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */
8191 
8192 /* Bit definition for Ethernet MAC Address1 Low Register */
8193 #define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */
8194 
8195 /* Bit definition for Ethernet MAC Address2 High Register */
8196 #define ETH_MACA2HR_AE 0x80000000U /* Address enable */
8197 #define ETH_MACA2HR_SA 0x40000000U /* Source address */
8198 #define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */
8199  #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
8200  #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
8201  #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
8202  #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
8203  #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
8204  #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
8205 #define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */
8206 
8207 /* Bit definition for Ethernet MAC Address2 Low Register */
8208 #define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */
8209 
8210 /* Bit definition for Ethernet MAC Address3 High Register */
8211 #define ETH_MACA3HR_AE 0x80000000U /* Address enable */
8212 #define ETH_MACA3HR_SA 0x40000000U /* Source address */
8213 #define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */
8214  #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
8215  #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
8216  #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
8217  #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
8218  #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
8219  #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
8220 #define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */
8221 
8222 /* Bit definition for Ethernet MAC Address3 Low Register */
8223 #define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */
8224 
8225 /******************************************************************************/
8226 /* Ethernet MMC Registers bits definition */
8227 /******************************************************************************/
8228 
8229 /* Bit definition for Ethernet MMC Contol Register */
8230 #define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */
8231 #define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */
8232 #define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */
8233 #define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */
8234 #define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */
8235 #define ETH_MMCCR_CR 0x00000001U /* Counters Reset */
8236 
8237 /* Bit definition for Ethernet MMC Receive Interrupt Register */
8238 #define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
8239 #define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
8240 #define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
8241 
8242 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
8243 #define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
8244 #define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
8245 #define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
8246 
8247 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
8248 #define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
8249 #define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
8250 #define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
8251 
8252 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
8253 #define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
8254 #define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
8255 #define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
8256 
8257 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
8258 #define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
8259 
8260 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
8261 #define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
8262 
8263 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
8264 #define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */
8265 
8266 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
8267 #define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */
8268 
8269 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
8270 #define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
8271 
8272 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
8273 #define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */
8274 
8275 /******************************************************************************/
8276 /* Ethernet PTP Registers bits definition */
8277 /******************************************************************************/
8278 
8279 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
8280 #define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */
8281 #define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */
8282 #define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */
8283 #define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */
8284 #define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */
8285 #define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
8286 #define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
8287 #define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */
8288 #define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */
8289 
8290 #define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */
8291 #define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */
8292 #define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */
8293 #define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */
8294 #define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */
8295 #define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */
8296 
8297 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
8298 #define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */
8299 
8300 /* Bit definition for Ethernet PTP Time Stamp High Register */
8301 #define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */
8302 
8303 /* Bit definition for Ethernet PTP Time Stamp Low Register */
8304 #define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */
8305 #define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */
8306 
8307 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
8308 #define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */
8309 
8310 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
8311 #define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */
8312 #define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */
8313 
8314 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
8315 #define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */
8316 
8317 /* Bit definition for Ethernet PTP Target Time High Register */
8318 #define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */
8319 
8320 /* Bit definition for Ethernet PTP Target Time Low Register */
8321 #define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */
8322 
8323 /* Bit definition for Ethernet PTP Time Stamp Status Register */
8324 #define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */
8325 #define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */
8326 
8327 /******************************************************************************/
8328 /* Ethernet DMA Registers bits definition */
8329 /******************************************************************************/
8330 
8331 /* Bit definition for Ethernet DMA Bus Mode Register */
8332 #define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */
8333 #define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */
8334 #define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */
8335 #define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */
8336  #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
8337  #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
8338  #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
8339  #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
8340  #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
8341  #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
8342  #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
8343  #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
8344  #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
8345  #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
8346  #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
8347  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
8348 #define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */
8349 #define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */
8350  #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
8351  #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
8352  #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
8353  #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
8354 #define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */
8355  #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
8356  #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
8357  #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
8358  #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
8359  #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
8360  #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
8361  #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
8362  #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
8363  #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
8364  #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
8365  #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
8366  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
8367 #define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */
8368 #define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */
8369 #define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */
8370 #define ETH_DMABMR_SR 0x00000001U /* Software reset */
8371 
8372 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
8373 #define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */
8374 
8375 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
8376 #define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */
8377 
8378 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
8379 #define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */
8380 
8381 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
8382 #define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */
8383 
8384 /* Bit definition for Ethernet DMA Status Register */
8385 #define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */
8386 #define ETH_DMASR_PMTS 0x10000000U /* PMT status */
8387 #define ETH_DMASR_MMCS 0x08000000U /* MMC status */
8388 #define ETH_DMASR_EBS 0x03800000U /* Error bits status */
8389  /* combination with EBS[2:0] for GetFlagStatus function */
8390  #define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */
8391  #define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
8392  #define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
8393 #define ETH_DMASR_TPS 0x00700000U /* Transmit process state */
8394  #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
8395  #define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */
8396  #define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */
8397  #define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */
8398  #define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */
8399  #define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */
8400 #define ETH_DMASR_RPS 0x000E0000U /* Receive process state */
8401  #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
8402  #define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */
8403  #define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */
8404  #define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */
8405  #define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */
8406  #define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */
8407 #define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */
8408 #define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */
8409 #define ETH_DMASR_ERS 0x00004000U /* Early receive status */
8410 #define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */
8411 #define ETH_DMASR_ETS 0x00000400U /* Early transmit status */
8412 #define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */
8413 #define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */
8414 #define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */
8415 #define ETH_DMASR_RS 0x00000040U /* Receive status */
8416 #define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */
8417 #define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */
8418 #define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */
8419 #define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */
8420 #define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */
8421 #define ETH_DMASR_TS 0x00000001U /* Transmit status */
8422 
8423 /* Bit definition for Ethernet DMA Operation Mode Register */
8424 #define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
8425 #define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */
8426 #define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */
8427 #define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */
8428 #define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */
8429 #define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */
8430  #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
8431  #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
8432  #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
8433  #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
8434  #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
8435  #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
8436  #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
8437  #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
8438 #define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */
8439 #define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */
8440 #define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */
8441 #define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */
8442  #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
8443  #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
8444  #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
8445  #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
8446 #define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */
8447 #define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */
8448 
8449 /* Bit definition for Ethernet DMA Interrupt Enable Register */
8450 #define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */
8451 #define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */
8452 #define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */
8453 #define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */
8454 #define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */
8455 #define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */
8456 #define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */
8457 #define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */
8458 #define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */
8459 #define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */
8460 #define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */
8461 #define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */
8462 #define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */
8463 #define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */
8464 #define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */
8465 
8466 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
8467 #define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */
8468 #define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */
8469 #define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */
8470 #define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */
8471 
8472 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
8473 #define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */
8474 
8475 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
8476 #define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */
8477 
8478 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
8479 #define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */
8480 
8481 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
8482 #define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */
8483 
8484 /******************************************************************************/
8485 /* */
8486 /* USB_OTG */
8487 /* */
8488 /******************************************************************************/
8489 /******************** Bit definition for USB_OTG_GOTGCTL register ********************/
8490 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U
8491 #define USB_OTG_GOTGCTL_SRQ 0x00000002U
8492 #define USB_OTG_GOTGCTL_VBVALOEN 0x00000004U
8493 #define USB_OTG_GOTGCTL_VBVALOVAL 0x00000008U
8494 #define USB_OTG_GOTGCTL_AVALOEN 0x00000010U
8495 #define USB_OTG_GOTGCTL_AVALOVAL 0x00000020U
8496 #define USB_OTG_GOTGCTL_BVALOEN 0x00000040U
8497 #define USB_OTG_GOTGCTL_BVALOVAL 0x00000080U
8498 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U
8499 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U
8500 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U
8501 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U
8502 #define USB_OTG_GOTGCTL_EHEN 0x00001000U
8503 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U
8504 #define USB_OTG_GOTGCTL_DBCT 0x00020000U
8505 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U
8506 #define USB_OTG_GOTGCTL_BSESVLD 0x00080000U
8507 #define USB_OTG_GOTGCTL_OTGVER 0x00100000U
8509 /******************** Bit definition for USB_OTG_HCFG register ********************/
8510 #define USB_OTG_HCFG_FSLSPCS 0x00000003U
8511 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U
8512 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U
8513 #define USB_OTG_HCFG_FSLSS 0x00000004U
8515 /******************** Bit definition for USB_OTG_DCFG register ********************/
8516 #define USB_OTG_DCFG_DSPD 0x00000003U
8517 #define USB_OTG_DCFG_DSPD_0 0x00000001U
8518 #define USB_OTG_DCFG_DSPD_1 0x00000002U
8519 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U
8521 #define USB_OTG_DCFG_DAD 0x000007F0U
8522 #define USB_OTG_DCFG_DAD_0 0x00000010U
8523 #define USB_OTG_DCFG_DAD_1 0x00000020U
8524 #define USB_OTG_DCFG_DAD_2 0x00000040U
8525 #define USB_OTG_DCFG_DAD_3 0x00000080U
8526 #define USB_OTG_DCFG_DAD_4 0x00000100U
8527 #define USB_OTG_DCFG_DAD_5 0x00000200U
8528 #define USB_OTG_DCFG_DAD_6 0x00000400U
8530 #define USB_OTG_DCFG_PFIVL 0x00001800U
8531 #define USB_OTG_DCFG_PFIVL_0 0x00000800U
8532 #define USB_OTG_DCFG_PFIVL_1 0x00001000U
8534 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U
8535 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U
8536 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U
8538 /******************** Bit definition for USB_OTG_PCGCR register ********************/
8539 #define USB_OTG_PCGCR_STPPCLK 0x00000001U
8540 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U
8541 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U
8543 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
8544 #define USB_OTG_GOTGINT_SEDET 0x00000004U
8545 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U
8546 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U
8547 #define USB_OTG_GOTGINT_HNGDET 0x00020000U
8548 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U
8549 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U
8550 #define USB_OTG_GOTGINT_IDCHNG 0x00100000U
8552 /******************** Bit definition for USB_OTG_DCTL register ********************/
8553 #define USB_OTG_DCTL_RWUSIG 0x00000001U
8554 #define USB_OTG_DCTL_SDIS 0x00000002U
8555 #define USB_OTG_DCTL_GINSTS 0x00000004U
8556 #define USB_OTG_DCTL_GONSTS 0x00000008U
8558 #define USB_OTG_DCTL_TCTL 0x00000070U
8559 #define USB_OTG_DCTL_TCTL_0 0x00000010U
8560 #define USB_OTG_DCTL_TCTL_1 0x00000020U
8561 #define USB_OTG_DCTL_TCTL_2 0x00000040U
8562 #define USB_OTG_DCTL_SGINAK 0x00000080U
8563 #define USB_OTG_DCTL_CGINAK 0x00000100U
8564 #define USB_OTG_DCTL_SGONAK 0x00000200U
8565 #define USB_OTG_DCTL_CGONAK 0x00000400U
8566 #define USB_OTG_DCTL_POPRGDNE 0x00000800U
8568 /******************** Bit definition for USB_OTG_HFIR register ********************/
8569 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU
8571 /******************** Bit definition for USB_OTG_HFNUM register ********************/
8572 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU
8573 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U
8575 /******************** Bit definition for USB_OTG_DSTS register ********************/
8576 #define USB_OTG_DSTS_SUSPSTS 0x00000001U
8578 #define USB_OTG_DSTS_ENUMSPD 0x00000006U
8579 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U
8580 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U
8581 #define USB_OTG_DSTS_EERR 0x00000008U
8582 #define USB_OTG_DSTS_FNSOF 0x003FFF00U
8584 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
8585 #define USB_OTG_GAHBCFG_GINT 0x00000001U
8586 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU
8587 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U
8588 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U
8589 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U
8590 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U
8591 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U
8592 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U
8593 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U
8595 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
8596 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U
8597 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U
8598 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U
8599 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U
8600 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U
8601 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U
8602 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U
8603 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U
8604 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U
8605 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U
8606 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U
8607 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U
8608 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U
8609 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U
8610 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U
8611 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U
8612 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U
8613 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U
8614 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U
8615 #define USB_OTG_GUSBCFG_PCCI 0x00800000U
8616 #define USB_OTG_GUSBCFG_PTCI 0x01000000U
8617 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U
8618 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U
8619 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U
8620 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U
8622 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
8623 #define USB_OTG_GRSTCTL_CSRST 0x00000001U
8624 #define USB_OTG_GRSTCTL_HSRST 0x00000002U
8625 #define USB_OTG_GRSTCTL_FCRST 0x00000004U
8626 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U
8627 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U
8628 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U
8629 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U
8630 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U
8631 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U
8632 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U
8633 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U
8634 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U
8635 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U
8637 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
8638 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U
8639 #define USB_OTG_DIEPMSK_EPDM 0x00000002U
8640 #define USB_OTG_DIEPMSK_TOM 0x00000008U
8641 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U
8642 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U
8643 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U
8644 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U
8645 #define USB_OTG_DIEPMSK_BIM 0x00000200U
8647 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
8648 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU
8649 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U
8650 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U
8651 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U
8652 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U
8653 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U
8654 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U
8655 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U
8656 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U
8657 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U
8659 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U
8660 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U
8661 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U
8662 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U
8663 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U
8664 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U
8665 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U
8666 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U
8667 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U
8669 /******************** Bit definition for USB_OTG_HAINT register ********************/
8670 #define USB_OTG_HAINT_HAINT 0x0000FFFFU
8672 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
8673 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U
8674 #define USB_OTG_DOEPMSK_EPDM 0x00000002U
8675 #define USB_OTG_DOEPMSK_STUPM 0x00000008U
8676 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U
8677 #define USB_OTG_DOEPMSK_OTEPSPRM 0x00000020U
8678 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U
8679 #define USB_OTG_DOEPMSK_OPEM 0x00000100U
8680 #define USB_OTG_DOEPMSK_BOIM 0x00000200U
8682 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
8683 #define USB_OTG_GINTSTS_CMOD 0x00000001U
8684 #define USB_OTG_GINTSTS_MMIS 0x00000002U
8685 #define USB_OTG_GINTSTS_OTGINT 0x00000004U
8686 #define USB_OTG_GINTSTS_SOF 0x00000008U
8687 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U
8688 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U
8689 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U
8690 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U
8691 #define USB_OTG_GINTSTS_ESUSP 0x00000400U
8692 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U
8693 #define USB_OTG_GINTSTS_USBRST 0x00001000U
8694 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U
8695 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U
8696 #define USB_OTG_GINTSTS_EOPF 0x00008000U
8697 #define USB_OTG_GINTSTS_IEPINT 0x00040000U
8698 #define USB_OTG_GINTSTS_OEPINT 0x00080000U
8699 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U
8700 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U
8701 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U
8702 #define USB_OTG_GINTSTS_RSTDET 0x00800000U
8703 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U
8704 #define USB_OTG_GINTSTS_HCINT 0x02000000U
8705 #define USB_OTG_GINTSTS_PTXFE 0x04000000U
8706 #define USB_OTG_GINTSTS_LPMINT 0x08000000U
8707 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U
8708 #define USB_OTG_GINTSTS_DISCINT 0x20000000U
8709 #define USB_OTG_GINTSTS_SRQINT 0x40000000U
8710 #define USB_OTG_GINTSTS_WKUINT 0x80000000U
8712 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
8713 #define USB_OTG_GINTMSK_MMISM 0x00000002U
8714 #define USB_OTG_GINTMSK_OTGINT 0x00000004U
8715 #define USB_OTG_GINTMSK_SOFM 0x00000008U
8716 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U
8717 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U
8718 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U
8719 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U
8720 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U
8721 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U
8722 #define USB_OTG_GINTMSK_USBRST 0x00001000U
8723 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U
8724 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U
8725 #define USB_OTG_GINTMSK_EOPFM 0x00008000U
8726 #define USB_OTG_GINTMSK_EPMISM 0x00020000U
8727 #define USB_OTG_GINTMSK_IEPINT 0x00040000U
8728 #define USB_OTG_GINTMSK_OEPINT 0x00080000U
8729 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U
8730 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U
8731 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U
8732 #define USB_OTG_GINTMSK_RSTDEM 0x00800000U
8733 #define USB_OTG_GINTMSK_PRTIM 0x01000000U
8734 #define USB_OTG_GINTMSK_HCIM 0x02000000U
8735 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U
8736 #define USB_OTG_GINTMSK_LPMINTM 0x08000000U
8737 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U
8738 #define USB_OTG_GINTMSK_DISCINT 0x20000000U
8739 #define USB_OTG_GINTMSK_SRQIM 0x40000000U
8740 #define USB_OTG_GINTMSK_WUIM 0x80000000U
8742 /******************** Bit definition for USB_OTG_DAINT register ********************/
8743 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU
8744 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U
8746 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
8747 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU
8749 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
8750 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU
8751 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U
8752 #define USB_OTG_GRXSTSP_DPID 0x00018000U
8753 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U
8755 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
8756 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU
8757 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U
8759 /******************** Bit definition for OTG register ********************/
8760 
8761 #define USB_OTG_CHNUM 0x0000000FU
8762 #define USB_OTG_CHNUM_0 0x00000001U
8763 #define USB_OTG_CHNUM_1 0x00000002U
8764 #define USB_OTG_CHNUM_2 0x00000004U
8765 #define USB_OTG_CHNUM_3 0x00000008U
8766 #define USB_OTG_BCNT 0x00007FF0U
8768 #define USB_OTG_DPID 0x00018000U
8769 #define USB_OTG_DPID_0 0x00008000U
8770 #define USB_OTG_DPID_1 0x00010000U
8772 #define USB_OTG_PKTSTS 0x001E0000U
8773 #define USB_OTG_PKTSTS_0 0x00020000U
8774 #define USB_OTG_PKTSTS_1 0x00040000U
8775 #define USB_OTG_PKTSTS_2 0x00080000U
8776 #define USB_OTG_PKTSTS_3 0x00100000U
8778 #define USB_OTG_EPNUM 0x0000000FU
8779 #define USB_OTG_EPNUM_0 0x00000001U
8780 #define USB_OTG_EPNUM_1 0x00000002U
8781 #define USB_OTG_EPNUM_2 0x00000004U
8782 #define USB_OTG_EPNUM_3 0x00000008U
8784 #define USB_OTG_FRMNUM 0x01E00000U
8785 #define USB_OTG_FRMNUM_0 0x00200000U
8786 #define USB_OTG_FRMNUM_1 0x00400000U
8787 #define USB_OTG_FRMNUM_2 0x00800000U
8788 #define USB_OTG_FRMNUM_3 0x01000000U
8790 /******************** Bit definition for OTG register ********************/
8791 
8792 #define USB_OTG_CHNUM 0x0000000FU
8793 #define USB_OTG_CHNUM_0 0x00000001U
8794 #define USB_OTG_CHNUM_1 0x00000002U
8795 #define USB_OTG_CHNUM_2 0x00000004U
8796 #define USB_OTG_CHNUM_3 0x00000008U
8797 #define USB_OTG_BCNT 0x00007FF0U
8799 #define USB_OTG_DPID 0x00018000U
8800 #define USB_OTG_DPID_0 0x00008000U
8801 #define USB_OTG_DPID_1 0x00010000U
8803 #define USB_OTG_PKTSTS 0x001E0000U
8804 #define USB_OTG_PKTSTS_0 0x00020000U
8805 #define USB_OTG_PKTSTS_1 0x00040000U
8806 #define USB_OTG_PKTSTS_2 0x00080000U
8807 #define USB_OTG_PKTSTS_3 0x00100000U
8809 #define USB_OTG_EPNUM 0x0000000FU
8810 #define USB_OTG_EPNUM_0 0x00000001U
8811 #define USB_OTG_EPNUM_1 0x00000002U
8812 #define USB_OTG_EPNUM_2 0x00000004U
8813 #define USB_OTG_EPNUM_3 0x00000008U
8815 #define USB_OTG_FRMNUM 0x01E00000U
8816 #define USB_OTG_FRMNUM_0 0x00200000U
8817 #define USB_OTG_FRMNUM_1 0x00400000U
8818 #define USB_OTG_FRMNUM_2 0x00800000U
8819 #define USB_OTG_FRMNUM_3 0x01000000U
8821 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
8822 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU
8824 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
8825 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU
8827 /******************** Bit definition for OTG register ********************/
8828 #define USB_OTG_NPTXFSA 0x0000FFFFU
8829 #define USB_OTG_NPTXFD 0xFFFF0000U
8830 #define USB_OTG_TX0FSA 0x0000FFFFU
8831 #define USB_OTG_TX0FD 0xFFFF0000U
8833 /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
8834 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU
8836 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
8837 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU
8839 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U
8840 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U
8841 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U
8842 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U
8843 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U
8844 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U
8845 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U
8846 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U
8847 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U
8849 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U
8850 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U
8851 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U
8852 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U
8853 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U
8854 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U
8855 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U
8856 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U
8858 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
8859 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U
8860 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U
8862 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU
8863 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U
8864 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U
8865 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U
8866 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U
8867 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U
8868 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U
8869 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U
8870 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U
8871 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U
8872 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U
8874 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U
8875 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U
8876 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U
8877 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U
8878 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U
8879 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U
8880 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U
8881 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U
8882 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U
8883 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U
8884 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U
8886 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
8887 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU
8889 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
8890 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U
8891 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U
8893 /******************** Bit definition for USB_OTG_GCCFG register ********************/
8894 #define USB_OTG_GCCFG_PWRDWN 0x00010000U
8895 #define USB_OTG_GCCFG_VBDEN 0x00200000U
8897 /******************** Bit definition for USB_OTG_GPWRDN) register ********************/
8898 #define USB_OTG_GPWRDN_ADPMEN 0x00000001U
8899 #define USB_OTG_GPWRDN_ADPIF 0x00800000U
8901 /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
8902 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U
8903 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U
8905 /******************** Bit definition for USB_OTG_CID register ********************/
8906 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU
8908 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
8909 #define USB_OTG_GLPMCFG_LPMEN 0x00000001U
8910 #define USB_OTG_GLPMCFG_LPMACK 0x00000002U
8911 #define USB_OTG_GLPMCFG_BESL 0x0000003CU
8912 #define USB_OTG_GLPMCFG_REMWAKE 0x00000040U
8913 #define USB_OTG_GLPMCFG_L1SSEN 0x00000080U
8914 #define USB_OTG_GLPMCFG_BESLTHRS 0x00000F00U
8915 #define USB_OTG_GLPMCFG_L1DSEN 0x00001000U
8916 #define USB_OTG_GLPMCFG_LPMRSP 0x00006000U
8917 #define USB_OTG_GLPMCFG_SLPSTS 0x00008000U
8918 #define USB_OTG_GLPMCFG_L1RSMOK 0x00010000U
8919 #define USB_OTG_GLPMCFG_LPMCHIDX 0x001E0000U
8920 #define USB_OTG_GLPMCFG_LPMRCNT 0x00E00000U
8921 #define USB_OTG_GLPMCFG_SNDLPM 0x01000000U
8922 #define USB_OTG_GLPMCFG_LPMRCNTSTS 0x0E000000U
8923 #define USB_OTG_GLPMCFG_ENBESL 0x10000000U
8925 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
8926 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U
8927 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U
8928 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U
8929 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U
8930 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U
8931 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U
8932 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U
8933 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U
8934 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U
8936 /******************** Bit definition for USB_OTG_HPRT register ********************/
8937 #define USB_OTG_HPRT_PCSTS 0x00000001U
8938 #define USB_OTG_HPRT_PCDET 0x00000002U
8939 #define USB_OTG_HPRT_PENA 0x00000004U
8940 #define USB_OTG_HPRT_PENCHNG 0x00000008U
8941 #define USB_OTG_HPRT_POCA 0x00000010U
8942 #define USB_OTG_HPRT_POCCHNG 0x00000020U
8943 #define USB_OTG_HPRT_PRES 0x00000040U
8944 #define USB_OTG_HPRT_PSUSP 0x00000080U
8945 #define USB_OTG_HPRT_PRST 0x00000100U
8947 #define USB_OTG_HPRT_PLSTS 0x00000C00U
8948 #define USB_OTG_HPRT_PLSTS_0 0x00000400U
8949 #define USB_OTG_HPRT_PLSTS_1 0x00000800U
8950 #define USB_OTG_HPRT_PPWR 0x00001000U
8952 #define USB_OTG_HPRT_PTCTL 0x0001E000U
8953 #define USB_OTG_HPRT_PTCTL_0 0x00002000U
8954 #define USB_OTG_HPRT_PTCTL_1 0x00004000U
8955 #define USB_OTG_HPRT_PTCTL_2 0x00008000U
8956 #define USB_OTG_HPRT_PTCTL_3 0x00010000U
8958 #define USB_OTG_HPRT_PSPD 0x00060000U
8959 #define USB_OTG_HPRT_PSPD_0 0x00020000U
8960 #define USB_OTG_HPRT_PSPD_1 0x00040000U
8962 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
8963 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U
8964 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U
8965 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U
8966 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U
8967 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U
8968 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U
8969 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U
8970 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U
8971 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U
8972 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U
8973 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U
8975 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
8976 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU
8977 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U
8979 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
8980 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU
8981 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U
8982 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U
8983 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U
8985 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U
8986 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U
8987 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U
8988 #define USB_OTG_DIEPCTL_STALL 0x00200000U
8990 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U
8991 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U
8992 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U
8993 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U
8994 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U
8995 #define USB_OTG_DIEPCTL_CNAK 0x04000000U
8996 #define USB_OTG_DIEPCTL_SNAK 0x08000000U
8997 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U
8998 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U
8999 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U
9000 #define USB_OTG_DIEPCTL_EPENA 0x80000000U
9002 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
9003 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU
9005 #define USB_OTG_HCCHAR_EPNUM 0x00007800U
9006 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U
9007 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U
9008 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U
9009 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U
9010 #define USB_OTG_HCCHAR_EPDIR 0x00008000U
9011 #define USB_OTG_HCCHAR_LSDEV 0x00020000U
9013 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U
9014 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U
9015 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U
9017 #define USB_OTG_HCCHAR_MC 0x00300000U
9018 #define USB_OTG_HCCHAR_MC_0 0x00100000U
9019 #define USB_OTG_HCCHAR_MC_1 0x00200000U
9021 #define USB_OTG_HCCHAR_DAD 0x1FC00000U
9022 #define USB_OTG_HCCHAR_DAD_0 0x00400000U
9023 #define USB_OTG_HCCHAR_DAD_1 0x00800000U
9024 #define USB_OTG_HCCHAR_DAD_2 0x01000000U
9025 #define USB_OTG_HCCHAR_DAD_3 0x02000000U
9026 #define USB_OTG_HCCHAR_DAD_4 0x04000000U
9027 #define USB_OTG_HCCHAR_DAD_5 0x08000000U
9028 #define USB_OTG_HCCHAR_DAD_6 0x10000000U
9029 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U
9030 #define USB_OTG_HCCHAR_CHDIS 0x40000000U
9031 #define USB_OTG_HCCHAR_CHENA 0x80000000U
9033 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
9034 
9035 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU
9036 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U
9037 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U
9038 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U
9039 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U
9040 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U
9041 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U
9042 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U
9044 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U
9045 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U
9046 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U
9047 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U
9048 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U
9049 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U
9050 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U
9051 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U
9053 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U
9054 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U
9055 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U
9056 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U
9057 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U
9059 /******************** Bit definition for USB_OTG_HCINT register ********************/
9060 #define USB_OTG_HCINT_XFRC 0x00000001U
9061 #define USB_OTG_HCINT_CHH 0x00000002U
9062 #define USB_OTG_HCINT_AHBERR 0x00000004U
9063 #define USB_OTG_HCINT_STALL 0x00000008U
9064 #define USB_OTG_HCINT_NAK 0x00000010U
9065 #define USB_OTG_HCINT_ACK 0x00000020U
9066 #define USB_OTG_HCINT_NYET 0x00000040U
9067 #define USB_OTG_HCINT_TXERR 0x00000080U
9068 #define USB_OTG_HCINT_BBERR 0x00000100U
9069 #define USB_OTG_HCINT_FRMOR 0x00000200U
9070 #define USB_OTG_HCINT_DTERR 0x00000400U
9072 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
9073 #define USB_OTG_DIEPINT_XFRC 0x00000001U
9074 #define USB_OTG_DIEPINT_EPDISD 0x00000002U
9075 #define USB_OTG_DIEPINT_TOC 0x00000008U
9076 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U
9077 #define USB_OTG_DIEPINT_INEPNE 0x00000040U
9078 #define USB_OTG_DIEPINT_TXFE 0x00000080U
9079 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U
9080 #define USB_OTG_DIEPINT_BNA 0x00000200U
9081 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U
9082 #define USB_OTG_DIEPINT_BERR 0x00001000U
9083 #define USB_OTG_DIEPINT_NAK 0x00002000U
9085 /******************** Bit definition for USB_OTG_HCINTMSK register ********************/
9086 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U
9087 #define USB_OTG_HCINTMSK_CHHM 0x00000002U
9088 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U
9089 #define USB_OTG_HCINTMSK_STALLM 0x00000008U
9090 #define USB_OTG_HCINTMSK_NAKM 0x00000010U
9091 #define USB_OTG_HCINTMSK_ACKM 0x00000020U
9092 #define USB_OTG_HCINTMSK_NYET 0x00000040U
9093 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U
9094 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U
9095 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U
9096 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U
9098 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
9099 
9100 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU
9101 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U
9102 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U
9103 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
9104 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU
9105 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U
9106 #define USB_OTG_HCTSIZ_DOPING 0x80000000U
9107 #define USB_OTG_HCTSIZ_DPID 0x60000000U
9108 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U
9109 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U
9111 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
9112 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU
9114 /******************** Bit definition for USB_OTG_HCDMA register ********************/
9115 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU
9117 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
9118 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU
9120 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
9121 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU
9122 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U
9124 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
9125 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU
9126 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U
9127 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U
9128 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U
9129 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U
9130 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U
9131 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U
9132 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U
9133 #define USB_OTG_DOEPCTL_SNPM 0x00100000U
9134 #define USB_OTG_DOEPCTL_STALL 0x00200000U
9135 #define USB_OTG_DOEPCTL_CNAK 0x04000000U
9136 #define USB_OTG_DOEPCTL_SNAK 0x08000000U
9137 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U
9138 #define USB_OTG_DOEPCTL_EPENA 0x80000000U
9140 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
9141 #define USB_OTG_DOEPINT_XFRC 0x00000001U
9142 #define USB_OTG_DOEPINT_EPDISD 0x00000002U
9143 #define USB_OTG_DOEPINT_STUP 0x00000008U
9144 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U
9145 #define USB_OTG_DOEPINT_OTEPSPR 0x00000020U
9146 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U
9147 #define USB_OTG_DOEPINT_NYET 0x00004000U
9149 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
9150 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU
9151 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U
9153 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U
9154 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U
9155 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U
9157 /******************** Bit definition for PCGCCTL register ********************/
9158 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U
9159 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U
9160 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U
9176 /******************************* ADC Instances ********************************/
9177 #define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
9178  ((__INSTANCE__) == ADC2) || \
9179  ((__INSTANCE__) == ADC3))
9180 
9181 /******************************* CAN Instances ********************************/
9182 #define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
9183  ((__INSTANCE__) == CAN2))
9184 /******************************* CRC Instances ********************************/
9185 #define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
9186 
9187 /******************************* DAC Instances ********************************/
9188 #define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)
9189 
9190 /******************************* DCMI Instances *******************************/
9191 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
9192 
9193 
9194 /******************************* DMA2D Instances *******************************/
9195 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
9196 
9197 /******************************** DMA Instances *******************************/
9198 #define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
9199  ((__INSTANCE__) == DMA1_Stream1) || \
9200  ((__INSTANCE__) == DMA1_Stream2) || \
9201  ((__INSTANCE__) == DMA1_Stream3) || \
9202  ((__INSTANCE__) == DMA1_Stream4) || \
9203  ((__INSTANCE__) == DMA1_Stream5) || \
9204  ((__INSTANCE__) == DMA1_Stream6) || \
9205  ((__INSTANCE__) == DMA1_Stream7) || \
9206  ((__INSTANCE__) == DMA2_Stream0) || \
9207  ((__INSTANCE__) == DMA2_Stream1) || \
9208  ((__INSTANCE__) == DMA2_Stream2) || \
9209  ((__INSTANCE__) == DMA2_Stream3) || \
9210  ((__INSTANCE__) == DMA2_Stream4) || \
9211  ((__INSTANCE__) == DMA2_Stream5) || \
9212  ((__INSTANCE__) == DMA2_Stream6) || \
9213  ((__INSTANCE__) == DMA2_Stream7))
9214 
9215 /******************************* GPIO Instances *******************************/
9216 #define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
9217  ((__INSTANCE__) == GPIOB) || \
9218  ((__INSTANCE__) == GPIOC) || \
9219  ((__INSTANCE__) == GPIOD) || \
9220  ((__INSTANCE__) == GPIOE) || \
9221  ((__INSTANCE__) == GPIOF) || \
9222  ((__INSTANCE__) == GPIOG) || \
9223  ((__INSTANCE__) == GPIOH) || \
9224  ((__INSTANCE__) == GPIOI) || \
9225  ((__INSTANCE__) == GPIOJ) || \
9226  ((__INSTANCE__) == GPIOK))
9227 
9228 #define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
9229  ((__INSTANCE__) == GPIOB) || \
9230  ((__INSTANCE__) == GPIOC) || \
9231  ((__INSTANCE__) == GPIOD) || \
9232  ((__INSTANCE__) == GPIOE) || \
9233  ((__INSTANCE__) == GPIOF) || \
9234  ((__INSTANCE__) == GPIOG) || \
9235  ((__INSTANCE__) == GPIOH) || \
9236  ((__INSTANCE__) == GPIOI) || \
9237  ((__INSTANCE__) == GPIOJ) || \
9238  ((__INSTANCE__) == GPIOK))
9239 
9240 /****************************** CEC Instances *********************************/
9241 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
9242 
9243 /****************************** QSPI Instances *********************************/
9244 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
9245 
9246 
9247 /******************************** I2C Instances *******************************/
9248 #define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
9249  ((__INSTANCE__) == I2C2) || \
9250  ((__INSTANCE__) == I2C3) || \
9251  ((__INSTANCE__) == I2C4))
9252 
9253 /******************************** I2S Instances *******************************/
9254 #define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
9255  ((__INSTANCE__) == SPI2) || \
9256  ((__INSTANCE__) == SPI3))
9257 
9258 /******************************* LPTIM Instances ********************************/
9259 #define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
9260 
9261 /****************************** LTDC Instances ********************************/
9262 #define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)
9263 
9264 
9265 
9266 /******************************* RNG Instances ********************************/
9267 #define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
9268 
9269 /****************************** RTC Instances *********************************/
9270 #define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)
9271 
9272 /******************************* SAI Instances ********************************/
9273 #define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
9274  ((__PERIPH__) == SAI1_Block_B) || \
9275  ((__PERIPH__) == SAI2_Block_A) || \
9276  ((__PERIPH__) == SAI2_Block_B))
9277 /* Legacy define */
9278 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
9279 
9280 /******************************** SDMMC Instances *******************************/
9281 #define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SDMMC1)
9282 
9283 /****************************** SPDIFRX Instances *********************************/
9284 #define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
9285 
9286 /******************************** SPI Instances *******************************/
9287 #define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
9288  ((__INSTANCE__) == SPI2) || \
9289  ((__INSTANCE__) == SPI3) || \
9290  ((__INSTANCE__) == SPI4) || \
9291  ((__INSTANCE__) == SPI5) || \
9292  ((__INSTANCE__) == SPI6))
9293 
9294 /****************** TIM Instances : All supported instances *******************/
9295 #define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9296  ((__INSTANCE__) == TIM2) || \
9297  ((__INSTANCE__) == TIM3) || \
9298  ((__INSTANCE__) == TIM4) || \
9299  ((__INSTANCE__) == TIM5) || \
9300  ((__INSTANCE__) == TIM6) || \
9301  ((__INSTANCE__) == TIM7) || \
9302  ((__INSTANCE__) == TIM8) || \
9303  ((__INSTANCE__) == TIM9) || \
9304  ((__INSTANCE__) == TIM10) || \
9305  ((__INSTANCE__) == TIM11) || \
9306  ((__INSTANCE__) == TIM12) || \
9307  ((__INSTANCE__) == TIM13) || \
9308  ((__INSTANCE__) == TIM14))
9309 
9310 /************* TIM Instances : at least 1 capture/compare channel *************/
9311 #define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9312  ((__INSTANCE__) == TIM2) || \
9313  ((__INSTANCE__) == TIM3) || \
9314  ((__INSTANCE__) == TIM4) || \
9315  ((__INSTANCE__) == TIM5) || \
9316  ((__INSTANCE__) == TIM8) || \
9317  ((__INSTANCE__) == TIM9) || \
9318  ((__INSTANCE__) == TIM10) || \
9319  ((__INSTANCE__) == TIM11) || \
9320  ((__INSTANCE__) == TIM12) || \
9321  ((__INSTANCE__) == TIM13) || \
9322  ((__INSTANCE__) == TIM14))
9323 
9324 /************ TIM Instances : at least 2 capture/compare channels *************/
9325 #define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9326  ((__INSTANCE__) == TIM2) || \
9327  ((__INSTANCE__) == TIM3) || \
9328  ((__INSTANCE__) == TIM4) || \
9329  ((__INSTANCE__) == TIM5) || \
9330  ((__INSTANCE__) == TIM8) || \
9331  ((__INSTANCE__) == TIM9) || \
9332  ((__INSTANCE__) == TIM12))
9333 
9334 /************ TIM Instances : at least 3 capture/compare channels *************/
9335 #define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9336  ((__INSTANCE__) == TIM2) || \
9337  ((__INSTANCE__) == TIM3) || \
9338  ((__INSTANCE__) == TIM4) || \
9339  ((__INSTANCE__) == TIM5) || \
9340  ((__INSTANCE__) == TIM8))
9341 
9342 /************ TIM Instances : at least 4 capture/compare channels *************/
9343 #define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9344  ((__INSTANCE__) == TIM2) || \
9345  ((__INSTANCE__) == TIM3) || \
9346  ((__INSTANCE__) == TIM4) || \
9347  ((__INSTANCE__) == TIM5) || \
9348  ((__INSTANCE__) == TIM8))
9349 
9350 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
9351 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
9352  (((__INSTANCE__) == TIM1) || \
9353  ((__INSTANCE__) == TIM8))
9354 
9355 /****************** TIM Instances : supporting OCxREF clear *******************/
9356 #define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
9357  (((__INSTANCE__) == TIM1) || \
9358  ((__INSTANCE__) == TIM2) || \
9359  ((__INSTANCE__) == TIM3) || \
9360  ((__INSTANCE__) == TIM4) || \
9361  ((__INSTANCE__) == TIM8))
9362 
9363 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
9364 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
9365  (((__INSTANCE__) == TIM1) || \
9366  ((__INSTANCE__) == TIM2) || \
9367  ((__INSTANCE__) == TIM3) || \
9368  ((__INSTANCE__) == TIM4) || \
9369  ((__INSTANCE__) == TIM5) || \
9370  ((__INSTANCE__) == TIM8))
9371 
9372 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
9373 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
9374  (((__INSTANCE__) == TIM1) || \
9375  ((__INSTANCE__) == TIM2) || \
9376  ((__INSTANCE__) == TIM3) || \
9377  ((__INSTANCE__) == TIM4) || \
9378  ((__INSTANCE__) == TIM5) || \
9379  ((__INSTANCE__) == TIM8))
9380 /****************** TIM Instances : at least 5 capture/compare channels *******/
9381 #define IS_TIM_CC5_INSTANCE(__INSTANCE__)\
9382  (((__INSTANCE__) == TIM1) || \
9383  ((__INSTANCE__) == TIM8) )
9384 
9385 /****************** TIM Instances : at least 6 capture/compare channels *******/
9386 #define IS_TIM_CC6_INSTANCE(__INSTANCE__)\
9387  (((__INSTANCE__) == TIM1) || \
9388  ((__INSTANCE__) == TIM8))
9389 
9390 
9391 /******************** TIM Instances : Advanced-control timers *****************/
9392 #define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9393  ((__INSTANCE__) == TIM8))
9394 
9395 /****************** TIM Instances : supporting 2 break inputs *****************/
9396 #define IS_TIM_BREAK_INSTANCE(__INSTANCE__)\
9397  (((__INSTANCE__) == TIM1) || \
9398  ((__INSTANCE__) == TIM8))
9399 
9400 /******************* TIM Instances : Timer input XOR function *****************/
9401 #define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9402  ((__INSTANCE__) == TIM2) || \
9403  ((__INSTANCE__) == TIM3) || \
9404  ((__INSTANCE__) == TIM4) || \
9405  ((__INSTANCE__) == TIM5) || \
9406  ((__INSTANCE__) == TIM8))
9407 
9408 /****************** TIM Instances : DMA requests generation (UDE) *************/
9409 #define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9410  ((__INSTANCE__) == TIM2) || \
9411  ((__INSTANCE__) == TIM3) || \
9412  ((__INSTANCE__) == TIM4) || \
9413  ((__INSTANCE__) == TIM5) || \
9414  ((__INSTANCE__) == TIM6) || \
9415  ((__INSTANCE__) == TIM7) || \
9416  ((__INSTANCE__) == TIM8))
9417 
9418 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
9419 #define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9420  ((__INSTANCE__) == TIM2) || \
9421  ((__INSTANCE__) == TIM3) || \
9422  ((__INSTANCE__) == TIM4) || \
9423  ((__INSTANCE__) == TIM5) || \
9424  ((__INSTANCE__) == TIM8))
9425 
9426 /************ TIM Instances : DMA requests generation (COMDE) *****************/
9427 #define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9428  ((__INSTANCE__) == TIM2) || \
9429  ((__INSTANCE__) == TIM3) || \
9430  ((__INSTANCE__) == TIM4) || \
9431  ((__INSTANCE__) == TIM5) || \
9432  ((__INSTANCE__) == TIM8))
9433 
9434 /******************** TIM Instances : DMA burst feature ***********************/
9435 #define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9436  ((__INSTANCE__) == TIM2) || \
9437  ((__INSTANCE__) == TIM3) || \
9438  ((__INSTANCE__) == TIM4) || \
9439  ((__INSTANCE__) == TIM5) || \
9440  ((__INSTANCE__) == TIM8))
9441 
9442 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
9443 #define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9444  ((__INSTANCE__) == TIM2) || \
9445  ((__INSTANCE__) == TIM3) || \
9446  ((__INSTANCE__) == TIM4) || \
9447  ((__INSTANCE__) == TIM5) || \
9448  ((__INSTANCE__) == TIM6) || \
9449  ((__INSTANCE__) == TIM7) || \
9450  ((__INSTANCE__) == TIM8) || \
9451  ((__INSTANCE__) == TIM13) || \
9452  ((__INSTANCE__) == TIM14))
9453 
9454 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
9455 #define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9456  ((__INSTANCE__) == TIM2) || \
9457  ((__INSTANCE__) == TIM3) || \
9458  ((__INSTANCE__) == TIM4) || \
9459  ((__INSTANCE__) == TIM5) || \
9460  ((__INSTANCE__) == TIM8) || \
9461  ((__INSTANCE__) == TIM9) || \
9462  ((__INSTANCE__) == TIM12))
9463 
9464 /********************** TIM Instances : 32 bit Counter ************************/
9465 #define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)(((__INSTANCE__) == TIM2) || \
9466  ((__INSTANCE__) == TIM5))
9467 
9468 /***************** TIM Instances : external trigger input available ************/
9469 #define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9470  ((__INSTANCE__) == TIM2) || \
9471  ((__INSTANCE__) == TIM3) || \
9472  ((__INSTANCE__) == TIM4) || \
9473  ((__INSTANCE__) == TIM5) || \
9474  ((__INSTANCE__) == TIM8))
9475 
9476 /****************** TIM Instances : remapping capability **********************/
9477 #define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
9478  ((__INSTANCE__) == TIM5) || \
9479  ((__INSTANCE__) == TIM11))
9480 
9481 /******************* TIM Instances : output(s) available **********************/
9482 #define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
9483  ((((__INSTANCE__) == TIM1) && \
9484  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9485  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9486  ((__CHANNEL__) == TIM_CHANNEL_3) || \
9487  ((__CHANNEL__) == TIM_CHANNEL_4))) \
9488  || \
9489  (((__INSTANCE__) == TIM2) && \
9490  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9491  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9492  ((__CHANNEL__) == TIM_CHANNEL_3) || \
9493  ((__CHANNEL__) == TIM_CHANNEL_4))) \
9494  || \
9495  (((__INSTANCE__) == TIM3) && \
9496  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9497  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9498  ((__CHANNEL__) == TIM_CHANNEL_3) || \
9499  ((__CHANNEL__) == TIM_CHANNEL_4))) \
9500  || \
9501  (((__INSTANCE__) == TIM4) && \
9502  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9503  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9504  ((__CHANNEL__) == TIM_CHANNEL_3) || \
9505  ((__CHANNEL__) == TIM_CHANNEL_4))) \
9506  || \
9507  (((__INSTANCE__) == TIM5) && \
9508  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9509  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9510  ((__CHANNEL__) == TIM_CHANNEL_3) || \
9511  ((__CHANNEL__) == TIM_CHANNEL_4))) \
9512  || \
9513  (((__INSTANCE__) == TIM8) && \
9514  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9515  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9516  ((__CHANNEL__) == TIM_CHANNEL_3) || \
9517  ((__CHANNEL__) == TIM_CHANNEL_4))) \
9518  || \
9519  (((__INSTANCE__) == TIM9) && \
9520  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9521  ((__CHANNEL__) == TIM_CHANNEL_2))) \
9522  || \
9523  (((__INSTANCE__) == TIM10) && \
9524  (((__CHANNEL__) == TIM_CHANNEL_1))) \
9525  || \
9526  (((__INSTANCE__) == TIM11) && \
9527  (((__CHANNEL__) == TIM_CHANNEL_1))) \
9528  || \
9529  (((__INSTANCE__) == TIM12) && \
9530  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9531  ((__CHANNEL__) == TIM_CHANNEL_2))) \
9532  || \
9533  (((__INSTANCE__) == TIM13) && \
9534  (((__CHANNEL__) == TIM_CHANNEL_1))) \
9535  || \
9536  (((__INSTANCE__) == TIM14) && \
9537  (((__CHANNEL__) == TIM_CHANNEL_1))))
9538 
9539 /************ TIM Instances : complementary output(s) available ***************/
9540 #define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
9541  ((((__INSTANCE__) == TIM1) && \
9542  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9543  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9544  ((__CHANNEL__) == TIM_CHANNEL_3))) \
9545  || \
9546  (((__INSTANCE__) == TIM8) && \
9547  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9548  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9549  ((__CHANNEL__) == TIM_CHANNEL_3))))
9550 
9551 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
9552 #define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
9553  (((__INSTANCE__) == TIM1) || \
9554  ((__INSTANCE__) == TIM8) )
9555 
9556 /****************** TIM Instances : supporting synchronization ****************/
9557 #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
9558  (((__INSTANCE__) == TIM1) || \
9559  ((__INSTANCE__) == TIM2) || \
9560  ((__INSTANCE__) == TIM3) || \
9561  ((__INSTANCE__) == TIM4) || \
9562  ((__INSTANCE__) == TIM5) || \
9563  ((__INSTANCE__) == TIM6) || \
9564  ((__INSTANCE__) == TIM7) || \
9565  ((__INSTANCE__) == TIM8))
9566 
9567 /******************** USART Instances : Synchronous mode **********************/
9568 #define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9569  ((__INSTANCE__) == USART2) || \
9570  ((__INSTANCE__) == USART3) || \
9571  ((__INSTANCE__) == USART6))
9572 
9573 /******************** UART Instances : Asynchronous mode **********************/
9574 #define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9575  ((__INSTANCE__) == USART2) || \
9576  ((__INSTANCE__) == USART3) || \
9577  ((__INSTANCE__) == UART4) || \
9578  ((__INSTANCE__) == UART5) || \
9579  ((__INSTANCE__) == USART6) || \
9580  ((__INSTANCE__) == UART7) || \
9581  ((__INSTANCE__) == UART8))
9582 
9583 /****************** UART Instances : Driver Enable *****************/
9584 #define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9585  ((__INSTANCE__) == USART2) || \
9586  ((__INSTANCE__) == USART3) || \
9587  ((__INSTANCE__) == UART4) || \
9588  ((__INSTANCE__) == UART5) || \
9589  ((__INSTANCE__) == USART6) || \
9590  ((__INSTANCE__) == UART7) || \
9591  ((__INSTANCE__) == UART8))
9592 
9593 /****************** UART Instances : Hardware Flow control ********************/
9594 #define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9595  ((__INSTANCE__) == USART2) || \
9596  ((__INSTANCE__) == USART3) || \
9597  ((__INSTANCE__) == UART4) || \
9598  ((__INSTANCE__) == UART5) || \
9599  ((__INSTANCE__) == USART6) || \
9600  ((__INSTANCE__) == UART7) || \
9601  ((__INSTANCE__) == UART8))
9602 
9603 /********************* UART Instances : Smart card mode ***********************/
9604 #define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9605  ((__INSTANCE__) == USART2) || \
9606  ((__INSTANCE__) == USART3) || \
9607  ((__INSTANCE__) == USART6))
9608 
9609 /*********************** UART Instances : IRDA mode ***************************/
9610 #define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9611  ((__INSTANCE__) == USART2) || \
9612  ((__INSTANCE__) == USART3) || \
9613  ((__INSTANCE__) == UART4) || \
9614  ((__INSTANCE__) == UART5) || \
9615  ((__INSTANCE__) == USART6) || \
9616  ((__INSTANCE__) == UART7) || \
9617  ((__INSTANCE__) == UART8))
9618 
9619 /****************************** IWDG Instances ********************************/
9620 #define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)
9621 
9622 /****************************** WWDG Instances ********************************/
9623 #define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)
9624 
9625 
9626 /******************************************************************************/
9627 /* For a painless codes migration between the STM32F7xx device product */
9628 /* lines, the aliases defined below are put in place to overcome the */
9629 /* differences in the interrupt handlers and IRQn definitions. */
9630 /* No need to update developed interrupt code when moving across */
9631 /* product lines within the same STM32F7 Family */
9632 /******************************************************************************/
9633 
9634 /* Aliases for __IRQn */
9635 #define RNG_IRQn HASH_RNG_IRQn
9636 
9637 /* Aliases for __IRQHandler */
9638 #define RNG_IRQHandler HASH_RNG_IRQHandler
9639 
9652 #ifdef __cplusplus
9653 }
9654 #endif /* __cplusplus */
9655 
9656 #endif /* __STM32F756xx_H */
9657 
9658 
9659 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
CRYP_TypeDef::CSGCMCCM3R
__IO uint32_t CSGCMCCM3R
Definition: stm32f756xx.h:1034
RESERVED
#define RESERVED
Definition: usbh_cdc.h:68
HASH_TypeDef::SR
__IO uint32_t SR
Definition: stm32f756xx.h:1060
LTDC_TypeDef
LCD-TFT Display Controller.
Definition: stm32f746xx.h:661
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition: stm32f745xx.h:253
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f745xx.h:613
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f745xx.h:841
SPI5_IRQn
Definition: stm32f756xx.h:164
DMA1_Stream2_IRQn
Definition: stm32f756xx.h:92
HASH_TypeDef::CR
__IO uint32_t CR
Definition: stm32f756xx.h:1055
CAN2_SCE_IRQn
Definition: stm32f756xx.h:145
OTG_FS_WKUP_IRQn
Definition: stm32f756xx.h:121
CRYP_TypeDef::K1RR
__IO uint32_t K1RR
Definition: stm32f756xx.h:1022
CRYP_TypeDef::CR
__IO uint32_t CR
Definition: stm32f756xx.h:1011
SVCall_IRQn
Definition: stm32f756xx.h:74
DMA2_Stream6_IRQn
Definition: stm32f756xx.h:148
OTG_HS_EP1_IN_IRQn
Definition: stm32f756xx.h:154
DMA2_Stream7_IRQn
Definition: stm32f756xx.h:149
EXTI4_IRQn
Definition: stm32f756xx.h:89
CRYP_TypeDef::CSGCMCCM2R
__IO uint32_t CSGCMCCM2R
Definition: stm32f756xx.h:1033
TIM4_IRQn
Definition: stm32f756xx.h:109
LPTIM1_IRQn
Definition: stm32f756xx.h:172
SAI2_IRQn
Definition: stm32f756xx.h:170
ADC_IRQn
Definition: stm32f756xx.h:97
CAN1_SCE_IRQn
Definition: stm32f756xx.h:101
EXTI1_IRQn
Definition: stm32f756xx.h:86
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f745xx.h:519
CRYP_TypeDef::IV1LR
__IO uint32_t IV1LR
Definition: stm32f756xx.h:1029
DMA2_Stream1_IRQn
Definition: stm32f756xx.h:136
I2C4_EV_IRQn
Definition: stm32f756xx.h:174
EXTI15_10_IRQn
Definition: stm32f756xx.h:119
CRYP_TypeDef::CSGCMCCM4R
__IO uint32_t CSGCMCCM4R
Definition: stm32f756xx.h:1035
CRYP_TypeDef::DMACR
__IO uint32_t DMACR
Definition: stm32f756xx.h:1015
SPDIFRX_TypeDef
SPDIF-RX Interface.
Definition: stm32f745xx.h:797
CRYP_TypeDef::CSGCM1R
__IO uint32_t CSGCM1R
Definition: stm32f756xx.h:1040
CEC_TypeDef
HDMI-CEC.
Definition: stm32f745xx.h:305
SPI4_IRQn
Definition: stm32f756xx.h:163
UART5_IRQn
Definition: stm32f756xx.h:132
SAI1_IRQn
Definition: stm32f756xx.h:166
TIM1_TRG_COM_TIM11_IRQn
Definition: stm32f756xx.h:105
FMC_Bank3_TypeDef
Flexible Memory Controller Bank3.
Definition: stm32f745xx.h:568
CRC_TypeDef
CRC calculation unit.
Definition: stm32f745xx.h:320
CRYP_TypeDef::CSGCMCCM7R
__IO uint32_t CSGCMCCM7R
Definition: stm32f756xx.h:1038
CRYP_TypeDef::K2RR
__IO uint32_t K2RR
Definition: stm32f756xx.h:1024
EXTI9_5_IRQn
Definition: stm32f756xx.h:102
CRYP_TypeDef::IMSCR
__IO uint32_t IMSCR
Definition: stm32f756xx.h:1016
DIR
Definition: ff.h:151
CAN1_RX1_IRQn
Definition: stm32f756xx.h:100
DMA2_Stream0_IRQn
Definition: stm32f756xx.h:135
CEC_IRQn
Definition: stm32f756xx.h:173
USB_OTG_INEndpointTypeDef
USB_OTG_IN_Endpoint-Specific_Register.
Definition: stm32f745xx.h:1035
SDMMC1_IRQn
Definition: stm32f756xx.h:128
I2C2_ER_IRQn
Definition: stm32f756xx.h:113
DMA2_Stream4_IRQn
Definition: stm32f756xx.h:139
EXTI3_IRQn
Definition: stm32f756xx.h:88
CAN2_RX1_IRQn
Definition: stm32f756xx.h:144
FMC_Bank1E_TypeDef
Flexible Memory Controller Bank1E.
Definition: stm32f745xx.h:559
DMA_TypeDef
Definition: stm32f745xx.h:400
TAMP_STAMP_IRQn
Definition: stm32f756xx.h:81
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f745xx.h:948
UART4_IRQn
Definition: stm32f756xx.h:131
DMA1_Stream6_IRQn
Definition: stm32f756xx.h:96
RTC_Alarm_IRQn
Definition: stm32f756xx.h:120
CRYP_TypeDef::CSGCM2R
__IO uint32_t CSGCM2R
Definition: stm32f756xx.h:1041
__I
#define __I
Definition: core_cm0.h:210
DMA1_Stream5_IRQn
Definition: stm32f756xx.h:95
CRYP_TypeDef::CSGCM7R
__IO uint32_t CSGCM7R
Definition: stm32f756xx.h:1046
SPI2_IRQn
Definition: stm32f756xx.h:115
LTDC_Layer_TypeDef
LCD-TFT Display layer x Controller.
Definition: stm32f746xx.h:686
HASH_DIGEST_TypeDef
HASH_DIGEST.
Definition: stm32f756xx.h:1069
USB_OTG_GlobalTypeDef
USB_OTG_Core_Registers.
Definition: stm32f745xx.h:974
CRYP_TypeDef::K2LR
__IO uint32_t K2LR
Definition: stm32f756xx.h:1023
DMA1_Stream1_IRQn
Definition: stm32f756xx.h:91
CRYP_TypeDef::IV0RR
__IO uint32_t IV0RR
Definition: stm32f756xx.h:1028
PendSV_IRQn
Definition: stm32f756xx.h:76
UART7_IRQn
Definition: stm32f756xx.h:161
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f745xx.h:596
BusFault_IRQn
Definition: stm32f756xx.h:72
I2C2_EV_IRQn
Definition: stm32f756xx.h:112
TIM8_TRG_COM_TIM14_IRQn
Definition: stm32f756xx.h:124
QUADSPI_TypeDef
QUAD Serial Peripheral Interface.
Definition: stm32f745xx.h:858
CRYP_TypeDef::IV0LR
__IO uint32_t IV0LR
Definition: stm32f756xx.h:1027
CAN2_TX_IRQn
Definition: stm32f756xx.h:142
CRYP_TypeDef::CSGCM5R
__IO uint32_t CSGCM5R
Definition: stm32f756xx.h:1044
I2C1_EV_IRQn
Definition: stm32f756xx.h:110
CAN_TypeDef
Controller Area Network.
Definition: stm32f745xx.h:275
LPTIM_TypeDef
LPTIMIMER.
Definition: stm32f745xx.h:911
FMC_IRQn
Definition: stm32f756xx.h:127
CRYP_TypeDef::K1LR
__IO uint32_t K1LR
Definition: stm32f756xx.h:1021
DCMI_IRQn
Definition: stm32f756xx.h:157
TIM7_IRQn
Definition: stm32f756xx.h:134
CRYP_TypeDef::CSGCM3R
__IO uint32_t CSGCM3R
Definition: stm32f756xx.h:1042
DMA2D_TypeDef
DMA2D Controller.
Definition: stm32f745xx.h:413
RCC_IRQn
Definition: stm32f756xx.h:84
I2C3_EV_IRQn
Definition: stm32f756xx.h:151
__IO
#define __IO
Definition: core_cm0.h:213
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32f745xx.h:204
CRYP_TypeDef::CSGCM4R
__IO uint32_t CSGCM4R
Definition: stm32f756xx.h:1043
SysTick_IRQn
Definition: stm32f756xx.h:77
CRYP_TypeDef::DR
__IO uint32_t DR
Definition: stm32f756xx.h:1013
SAI_TypeDef
Serial Audio Interface.
Definition: stm32f745xx.h:776
CRYP_TypeDef::MISR
__IO uint32_t MISR
Definition: stm32f756xx.h:1018
DMA1_Stream0_IRQn
Definition: stm32f756xx.h:90
CRYP_TypeDef::IV1RR
__IO uint32_t IV1RR
Definition: stm32f756xx.h:1030
USB_OTG_HostTypeDef
USB_OTG_Host_Mode_Register_Structures.
Definition: stm32f745xx.h:1066
IRQn_Type
IRQn_Type
STM32F7xx Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f756xx.h:67
CRYP_TypeDef::K3RR
__IO uint32_t K3RR
Definition: stm32f756xx.h:1026
CRYP_TypeDef::DOUT
__IO uint32_t DOUT
Definition: stm32f756xx.h:1014
QUADSPI_IRQn
Definition: stm32f756xx.h:171
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition: stm32f745xx.h:241
ETH_TypeDef
Ethernet MAC.
Definition: stm32f745xx.h:445
TIM2_IRQn
Definition: stm32f756xx.h:107
SPI3_IRQn
Definition: stm32f756xx.h:130
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f745xx.h:928
TIM_TypeDef
TIM.
Definition: stm32f745xx.h:879
DMA1_Stream7_IRQn
Definition: stm32f756xx.h:126
DMA2_Stream5_IRQn
Definition: stm32f756xx.h:147
USART1_IRQn
Definition: stm32f756xx.h:116
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f745xx.h:390
CRYP_TypeDef::K0LR
__IO uint32_t K0LR
Definition: stm32f756xx.h:1019
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32f745xx.h:336
CRYP_TypeDef::RISR
__IO uint32_t RISR
Definition: stm32f756xx.h:1017
USB_OTG_HostChannelTypeDef
USB_OTG_Host_Channel_Specific_Registers.
Definition: stm32f745xx.h:1080
OTG_HS_WKUP_IRQn
Definition: stm32f756xx.h:155
I2C4_ER_IRQn
Definition: stm32f756xx.h:175
FLASH_TypeDef
FLASH Registers.
Definition: stm32f745xx.h:533
DMA2_Stream2_IRQn
Definition: stm32f756xx.h:137
PWR_TypeDef
Power Control.
Definition: stm32f745xx.h:660
PVD_IRQn
Definition: stm32f756xx.h:80
CRYP_IRQn
Definition: stm32f756xx.h:158
ETH_IRQn
Definition: stm32f756xx.h:140
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f745xx.h:645
HASH_TypeDef::DIN
__IO uint32_t DIN
Definition: stm32f756xx.h:1056
FPU_IRQn
Definition: stm32f756xx.h:160
OTG_HS_EP1_OUT_IRQn
Definition: stm32f756xx.h:153
ADC_Common_TypeDef
Definition: stm32f745xx.h:228
DMA1_Stream3_IRQn
Definition: stm32f756xx.h:93
CRYP_TypeDef::CSGCMCCM1R
__IO uint32_t CSGCMCCM1R
Definition: stm32f756xx.h:1032
RTC_WKUP_IRQn
Definition: stm32f756xx.h:82
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f745xx.h:673
WWDG_IRQn
Definition: stm32f756xx.h:79
CAN2_RX0_IRQn
Definition: stm32f756xx.h:143
TIM8_BRK_TIM12_IRQn
Definition: stm32f756xx.h:122
DMA2D_IRQn
Definition: stm32f756xx.h:169
I2C3_ER_IRQn
Definition: stm32f756xx.h:152
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition: stm32f745xx.h:265
CAN1_TX_IRQn
Definition: stm32f756xx.h:98
DebugMonitor_IRQn
Definition: stm32f756xx.h:75
FMC_Bank1_TypeDef
Flexible Memory Controller.
Definition: stm32f745xx.h:550
HASH_RNG_IRQn
Definition: stm32f756xx.h:159
DMA1_Stream4_IRQn
Definition: stm32f756xx.h:94
TIM6_DAC_IRQn
Definition: stm32f756xx.h:133
SPDIF_RX_IRQn
Definition: stm32f756xx.h:176
RTC_TypeDef
Real-Time Clock.
Definition: stm32f745xx.h:715
ETH_WKUP_IRQn
Definition: stm32f756xx.h:141
DCMI_TypeDef
DCMI.
Definition: stm32f745xx.h:371
I2C1_ER_IRQn
Definition: stm32f756xx.h:111
FMC_Bank5_6_TypeDef
Flexible Memory Controller Bank5_6.
Definition: stm32f745xx.h:582
OTG_HS_IRQn
Definition: stm32f756xx.h:156
TIM1_CC_IRQn
Definition: stm32f756xx.h:106
CRYP_TypeDef::CSGCMCCM6R
__IO uint32_t CSGCMCCM6R
Definition: stm32f756xx.h:1037
FLASH_IRQn
Definition: stm32f756xx.h:83
DMA2_Stream3_IRQn
Definition: stm32f756xx.h:138
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f745xx.h:626
TIM8_UP_TIM13_IRQn
Definition: stm32f756xx.h:123
CRYP_TypeDef::SR
__IO uint32_t SR
Definition: stm32f756xx.h:1012
HASH_TypeDef::STR
__IO uint32_t STR
Definition: stm32f756xx.h:1057
RNG_TypeDef
RNG.
Definition: stm32f745xx.h:960
HASH_TypeDef
HASH.
Definition: stm32f756xx.h:1053
SPI6_IRQn
Definition: stm32f756xx.h:165
TIM1_BRK_TIM9_IRQn
Definition: stm32f756xx.h:103
TIM1_UP_TIM10_IRQn
Definition: stm32f756xx.h:104
CRYP_TypeDef::CSGCM0R
__IO uint32_t CSGCM0R
Definition: stm32f756xx.h:1039
CRYP_TypeDef::CSGCMCCM0R
__IO uint32_t CSGCMCCM0R
Definition: stm32f756xx.h:1031
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f745xx.h:359
SPI1_IRQn
Definition: stm32f756xx.h:114
TIM3_IRQn
Definition: stm32f756xx.h:108
NonMaskableInt_IRQn
Definition: stm32f756xx.h:70
SDMMC_TypeDef
SD host Interface.
Definition: stm32f745xx.h:813
CRYP_TypeDef::CSGCM6R
__IO uint32_t CSGCM6R
Definition: stm32f756xx.h:1045
TIM8_CC_IRQn
Definition: stm32f756xx.h:125
SAI_Block_TypeDef
Definition: stm32f745xx.h:781
EXTI0_IRQn
Definition: stm32f756xx.h:85
LTDC_IRQn
Definition: stm32f756xx.h:167
CRYP_TypeDef
Crypto Processor.
Definition: stm32f756xx.h:1009
CRYP_TypeDef::K0RR
__IO uint32_t K0RR
Definition: stm32f756xx.h:1020
CRYP_TypeDef::CSGCMCCM5R
__IO uint32_t CSGCMCCM5R
Definition: stm32f756xx.h:1036
EXTI2_IRQn
Definition: stm32f756xx.h:87
USB_OTG_OUTEndpointTypeDef
USB_OTG_OUT_Endpoint-Specific_Registers.
Definition: stm32f745xx.h:1051
LTDC_ER_IRQn
Definition: stm32f756xx.h:168
CRYP_TypeDef::K3LR
__IO uint32_t K3LR
Definition: stm32f756xx.h:1025
USART3_IRQn
Definition: stm32f756xx.h:118
USART2_IRQn
Definition: stm32f756xx.h:117
UART8_IRQn
Definition: stm32f756xx.h:162
OTG_FS_IRQn
Definition: stm32f756xx.h:146
UsageFault_IRQn
Definition: stm32f756xx.h:73
MemoryManagement_IRQn
Definition: stm32f756xx.h:71
USB_OTG_DeviceTypeDef
USB_OTG_device_Registers.
Definition: stm32f745xx.h:1007
TIM5_IRQn
Definition: stm32f756xx.h:129
USART6_IRQn
Definition: stm32f756xx.h:150
CAN1_RX0_IRQn
Definition: stm32f756xx.h:99
HASH_TypeDef::IMR
__IO uint32_t IMR
Definition: stm32f756xx.h:1059
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