CMSIS Cortex-M7 Device Peripheral Access Layer Header File. More...

#include "core_cm7.h"
#include "system_stm32f7xx.h"
#include <stdint.h>

Data Structures
struct	ADC_TypeDef
	Analog to Digital Converter. More...

struct	ADC_Common_TypeDef

struct	CAN_TxMailBox_TypeDef
	Controller Area Network TxMailBox. More...

struct	CAN_FIFOMailBox_TypeDef
	Controller Area Network FIFOMailBox. More...

struct	CAN_FilterRegister_TypeDef
	Controller Area Network FilterRegister. More...

struct	CAN_TypeDef
	Controller Area Network. More...

struct	CEC_TypeDef
	HDMI-CEC. More...

struct	CRC_TypeDef
	CRC calculation unit. More...

struct	DAC_TypeDef
	Digital to Analog Converter. More...

struct	DBGMCU_TypeDef
	Debug MCU. More...

struct	DCMI_TypeDef
	DCMI. More...

struct	DMA_Stream_TypeDef
	DMA Controller. More...

struct	DMA_TypeDef

struct	DMA2D_TypeDef
	DMA2D Controller. More...

struct	ETH_TypeDef
	Ethernet MAC. More...

struct	EXTI_TypeDef
	External Interrupt/Event Controller. More...

struct	FLASH_TypeDef
	FLASH Registers. More...

struct	FMC_Bank1_TypeDef
	Flexible Memory Controller. More...

struct	FMC_Bank1E_TypeDef
	Flexible Memory Controller Bank1E. More...

struct	FMC_Bank3_TypeDef
	Flexible Memory Controller Bank3. More...

struct	FMC_Bank5_6_TypeDef
	Flexible Memory Controller Bank5_6. More...

struct	GPIO_TypeDef
	General Purpose I/O. More...

struct	SYSCFG_TypeDef
	System configuration controller. More...

struct	I2C_TypeDef
	Inter-integrated Circuit Interface. More...

struct	IWDG_TypeDef
	Independent WATCHDOG. More...

struct	LTDC_TypeDef
	LCD-TFT Display Controller. More...

struct	LTDC_Layer_TypeDef
	LCD-TFT Display layer x Controller. More...

struct	PWR_TypeDef
	Power Control. More...

struct	RCC_TypeDef
	Reset and Clock Control. More...

struct	RTC_TypeDef
	Real-Time Clock. More...

struct	SAI_TypeDef
	Serial Audio Interface. More...

struct	SAI_Block_TypeDef

struct	SPDIFRX_TypeDef
	SPDIF-RX Interface. More...

struct	SDMMC_TypeDef
	SD host Interface. More...

struct	SPI_TypeDef
	Serial Peripheral Interface. More...

struct	QUADSPI_TypeDef
	QUAD Serial Peripheral Interface. More...

struct	TIM_TypeDef
	TIM. More...

struct	LPTIM_TypeDef
	LPTIMIMER. More...

struct	USART_TypeDef
	Universal Synchronous Asynchronous Receiver Transmitter. More...

struct	WWDG_TypeDef
	Window WATCHDOG. More...

struct	CRYP_TypeDef
	Crypto Processor. More...

struct	HASH_TypeDef
	HASH. More...

struct	HASH_DIGEST_TypeDef
	HASH_DIGEST. More...

struct	RNG_TypeDef
	RNG. More...

struct	USB_OTG_GlobalTypeDef
	USB_OTG_Core_Registers. More...

struct	USB_OTG_DeviceTypeDef
	USB_OTG_device_Registers. More...

struct	USB_OTG_INEndpointTypeDef
	USB_OTG_IN_Endpoint-Specific_Register. More...

struct	USB_OTG_OUTEndpointTypeDef
	USB_OTG_OUT_Endpoint-Specific_Registers. More...

struct	USB_OTG_HostTypeDef
	USB_OTG_Host_Mode_Register_Structures. More...

struct	USB_OTG_HostChannelTypeDef
	USB_OTG_Host_Channel_Specific_Registers. More...

Macros
#define	__CM7_REV 0x0001U
	Configuration of the Cortex-M7 Processor and Core Peripherals. More...

#define	__MPU_PRESENT 1

#define	__NVIC_PRIO_BITS 4

#define	__Vendor_SysTickConfig 0

#define	__FPU_PRESENT 1

#define	__ICACHE_PRESENT 1

#define	__DCACHE_PRESENT 1

#define	RAMITCM_BASE 0x00000000U

#define	FLASHITCM_BASE 0x00200000U

#define	FLASHAXI_BASE 0x08000000U

#define	RAMDTCM_BASE 0x20000000U

#define	PERIPH_BASE 0x40000000U

#define	BKPSRAM_BASE 0x40024000U

#define	QSPI_BASE 0x90000000U

#define	FMC_R_BASE 0xA0000000U

#define	QSPI_R_BASE 0xA0001000U

#define	SRAM1_BASE 0x20010000U

#define	SRAM2_BASE 0x2004C000U

#define	FLASH_END 0x080FFFFFU

#define	FLASH_BASE FLASHAXI_BASE

#define	APB1PERIPH_BASE PERIPH_BASE

#define	APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)

#define	AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)

#define	AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)

#define	TIM2_BASE (APB1PERIPH_BASE + 0x0000U)

#define	TIM3_BASE (APB1PERIPH_BASE + 0x0400U)

#define	TIM4_BASE (APB1PERIPH_BASE + 0x0800U)

#define	TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)

#define	TIM6_BASE (APB1PERIPH_BASE + 0x1000U)

#define	TIM7_BASE (APB1PERIPH_BASE + 0x1400U)

#define	TIM12_BASE (APB1PERIPH_BASE + 0x1800U)

#define	TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)

#define	TIM14_BASE (APB1PERIPH_BASE + 0x2000U)

#define	LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)

#define	RTC_BASE (APB1PERIPH_BASE + 0x2800U)

#define	WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)

#define	IWDG_BASE (APB1PERIPH_BASE + 0x3000U)

#define	SPI2_BASE (APB1PERIPH_BASE + 0x3800U)

#define	SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)

#define	SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U)

#define	USART2_BASE (APB1PERIPH_BASE + 0x4400U)

#define	USART3_BASE (APB1PERIPH_BASE + 0x4800U)

#define	UART4_BASE (APB1PERIPH_BASE + 0x4C00U)

#define	UART5_BASE (APB1PERIPH_BASE + 0x5000U)

#define	I2C1_BASE (APB1PERIPH_BASE + 0x5400U)

#define	I2C2_BASE (APB1PERIPH_BASE + 0x5800U)

#define	I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)

#define	I2C4_BASE (APB1PERIPH_BASE + 0x6000U)

#define	CAN1_BASE (APB1PERIPH_BASE + 0x6400U)

#define	CAN2_BASE (APB1PERIPH_BASE + 0x6800U)

#define	CEC_BASE (APB1PERIPH_BASE + 0x6C00U)

#define	PWR_BASE (APB1PERIPH_BASE + 0x7000U)

#define	DAC_BASE (APB1PERIPH_BASE + 0x7400U)

#define	UART7_BASE (APB1PERIPH_BASE + 0x7800U)

#define	UART8_BASE (APB1PERIPH_BASE + 0x7C00U)

#define	TIM1_BASE (APB2PERIPH_BASE + 0x0000U)

#define	TIM8_BASE (APB2PERIPH_BASE + 0x0400U)

#define	USART1_BASE (APB2PERIPH_BASE + 0x1000U)

#define	USART6_BASE (APB2PERIPH_BASE + 0x1400U)

#define	ADC1_BASE (APB2PERIPH_BASE + 0x2000U)

#define	ADC2_BASE (APB2PERIPH_BASE + 0x2100U)

#define	ADC3_BASE (APB2PERIPH_BASE + 0x2200U)

#define	ADC_BASE (APB2PERIPH_BASE + 0x2300U)

#define	SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U)

#define	SPI1_BASE (APB2PERIPH_BASE + 0x3000U)

#define	SPI4_BASE (APB2PERIPH_BASE + 0x3400U)

#define	SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)

#define	EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)

#define	TIM9_BASE (APB2PERIPH_BASE + 0x4000U)

#define	TIM10_BASE (APB2PERIPH_BASE + 0x4400U)

#define	TIM11_BASE (APB2PERIPH_BASE + 0x4800U)

#define	SPI5_BASE (APB2PERIPH_BASE + 0x5000U)

#define	SPI6_BASE (APB2PERIPH_BASE + 0x5400U)

#define	SAI1_BASE (APB2PERIPH_BASE + 0x5800U)

#define	SAI2_BASE (APB2PERIPH_BASE + 0x5C00U)

#define	SAI1_Block_A_BASE (SAI1_BASE + 0x004U)

#define	SAI1_Block_B_BASE (SAI1_BASE + 0x024U)

#define	SAI2_Block_A_BASE (SAI2_BASE + 0x004U)

#define	SAI2_Block_B_BASE (SAI2_BASE + 0x024U)

#define	LTDC_BASE (APB2PERIPH_BASE + 0x6800U)

#define	LTDC_Layer1_BASE (LTDC_BASE + 0x84U)

#define	LTDC_Layer2_BASE (LTDC_BASE + 0x104U)

#define	GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)

#define	GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)

#define	GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)

#define	GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)

#define	GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)

#define	GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)

#define	GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)

#define	GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)

#define	GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)

#define	GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)

#define	GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)

#define	CRC_BASE (AHB1PERIPH_BASE + 0x3000U)

#define	RCC_BASE (AHB1PERIPH_BASE + 0x3800U)

#define	FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)

#define	UID_BASE 0x1FF0F420U

#define	FLASHSIZE_BASE 0x1FF0F442U

#define	PACKAGESIZE_BASE 0x1FFF7BF0U

#define	DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)

#define	DMA1_Stream0_BASE (DMA1_BASE + 0x010U)

#define	DMA1_Stream1_BASE (DMA1_BASE + 0x028U)

#define	DMA1_Stream2_BASE (DMA1_BASE + 0x040U)

#define	DMA1_Stream3_BASE (DMA1_BASE + 0x058U)

#define	DMA1_Stream4_BASE (DMA1_BASE + 0x070U)

#define	DMA1_Stream5_BASE (DMA1_BASE + 0x088U)

#define	DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)

#define	DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)

#define	DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)

#define	DMA2_Stream0_BASE (DMA2_BASE + 0x010U)

#define	DMA2_Stream1_BASE (DMA2_BASE + 0x028U)

#define	DMA2_Stream2_BASE (DMA2_BASE + 0x040U)

#define	DMA2_Stream3_BASE (DMA2_BASE + 0x058U)

#define	DMA2_Stream4_BASE (DMA2_BASE + 0x070U)

#define	DMA2_Stream5_BASE (DMA2_BASE + 0x088U)

#define	DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)

#define	DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)

#define	ETH_BASE (AHB1PERIPH_BASE + 0x8000U)

#define	ETH_MAC_BASE (ETH_BASE)

#define	ETH_MMC_BASE (ETH_BASE + 0x0100U)

#define	ETH_PTP_BASE (ETH_BASE + 0x0700U)

#define	ETH_DMA_BASE (ETH_BASE + 0x1000U)

#define	DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)

#define	DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)

#define	CRYP_BASE (AHB2PERIPH_BASE + 0x60000U)

#define	HASH_BASE (AHB2PERIPH_BASE + 0x60400U)

#define	HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710U)

#define	RNG_BASE (AHB2PERIPH_BASE + 0x60800U)

#define	FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)

#define	FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)

#define	FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)

#define	FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)

#define	DBGMCU_BASE 0xE0042000U

#define	USB_OTG_HS_PERIPH_BASE 0x40040000U

#define	USB_OTG_FS_PERIPH_BASE 0x50000000U

#define	USB_OTG_GLOBAL_BASE 0x000U

#define	USB_OTG_DEVICE_BASE 0x800U

#define	USB_OTG_IN_ENDPOINT_BASE 0x900U

#define	USB_OTG_OUT_ENDPOINT_BASE 0xB00U

#define	USB_OTG_EP_REG_SIZE 0x20U

#define	USB_OTG_HOST_BASE 0x400U

#define	USB_OTG_HOST_PORT_BASE 0x440U

#define	USB_OTG_HOST_CHANNEL_BASE 0x500U

#define	USB_OTG_HOST_CHANNEL_SIZE 0x20U

#define	USB_OTG_PCGCCTL_BASE 0xE00U

#define	USB_OTG_FIFO_BASE 0x1000U

#define	USB_OTG_FIFO_SIZE 0x1000U

#define	TIM2 ((TIM_TypeDef *) TIM2_BASE)

#define	TIM3 ((TIM_TypeDef *) TIM3_BASE)

#define	TIM4 ((TIM_TypeDef *) TIM4_BASE)

#define	TIM5 ((TIM_TypeDef *) TIM5_BASE)

#define	TIM6 ((TIM_TypeDef *) TIM6_BASE)

#define	TIM7 ((TIM_TypeDef *) TIM7_BASE)

#define	TIM12 ((TIM_TypeDef *) TIM12_BASE)

#define	TIM13 ((TIM_TypeDef *) TIM13_BASE)

#define	TIM14 ((TIM_TypeDef *) TIM14_BASE)

#define	LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)

#define	RTC ((RTC_TypeDef *) RTC_BASE)

#define	WWDG ((WWDG_TypeDef *) WWDG_BASE)

#define	IWDG ((IWDG_TypeDef *) IWDG_BASE)

#define	SPI2 ((SPI_TypeDef *) SPI2_BASE)

#define	SPI3 ((SPI_TypeDef *) SPI3_BASE)

#define	SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

#define	USART2 ((USART_TypeDef *) USART2_BASE)

#define	USART3 ((USART_TypeDef *) USART3_BASE)

#define	UART4 ((USART_TypeDef *) UART4_BASE)

#define	UART5 ((USART_TypeDef *) UART5_BASE)

#define	I2C1 ((I2C_TypeDef *) I2C1_BASE)

#define	I2C2 ((I2C_TypeDef *) I2C2_BASE)

#define	I2C3 ((I2C_TypeDef *) I2C3_BASE)

#define	I2C4 ((I2C_TypeDef *) I2C4_BASE)

#define	CAN1 ((CAN_TypeDef *) CAN1_BASE)

#define	CAN2 ((CAN_TypeDef *) CAN2_BASE)

#define	CEC ((CEC_TypeDef *) CEC_BASE)

#define	PWR ((PWR_TypeDef *) PWR_BASE)

#define	DAC ((DAC_TypeDef *) DAC_BASE)

#define	UART7 ((USART_TypeDef *) UART7_BASE)

#define	UART8 ((USART_TypeDef *) UART8_BASE)

#define	TIM1 ((TIM_TypeDef *) TIM1_BASE)

#define	TIM8 ((TIM_TypeDef *) TIM8_BASE)

#define	USART1 ((USART_TypeDef *) USART1_BASE)

#define	USART6 ((USART_TypeDef *) USART6_BASE)

#define	ADC ((ADC_Common_TypeDef *) ADC_BASE)

#define	ADC1 ((ADC_TypeDef *) ADC1_BASE)

#define	ADC2 ((ADC_TypeDef *) ADC2_BASE)

#define	ADC3 ((ADC_TypeDef *) ADC3_BASE)

#define	SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)

#define	SPI1 ((SPI_TypeDef *) SPI1_BASE)

#define	SPI4 ((SPI_TypeDef *) SPI4_BASE)

#define	SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)

#define	EXTI ((EXTI_TypeDef *) EXTI_BASE)

#define	TIM9 ((TIM_TypeDef *) TIM9_BASE)

#define	TIM10 ((TIM_TypeDef *) TIM10_BASE)

#define	TIM11 ((TIM_TypeDef *) TIM11_BASE)

#define	SPI5 ((SPI_TypeDef *) SPI5_BASE)

#define	SPI6 ((SPI_TypeDef *) SPI6_BASE)

#define	SAI1 ((SAI_TypeDef *) SAI1_BASE)

#define	SAI2 ((SAI_TypeDef *) SAI2_BASE)

#define	SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

#define	SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

#define	SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

#define	SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

#define	LTDC ((LTDC_TypeDef *)LTDC_BASE)

#define	LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

#define	LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

#define	GPIOA ((GPIO_TypeDef *) GPIOA_BASE)

#define	GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

#define	GPIOC ((GPIO_TypeDef *) GPIOC_BASE)

#define	GPIOD ((GPIO_TypeDef *) GPIOD_BASE)

#define	GPIOE ((GPIO_TypeDef *) GPIOE_BASE)

#define	GPIOF ((GPIO_TypeDef *) GPIOF_BASE)

#define	GPIOG ((GPIO_TypeDef *) GPIOG_BASE)

#define	GPIOH ((GPIO_TypeDef *) GPIOH_BASE)

#define	GPIOI ((GPIO_TypeDef *) GPIOI_BASE)

#define	GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)

#define	GPIOK ((GPIO_TypeDef *) GPIOK_BASE)

#define	CRC ((CRC_TypeDef *) CRC_BASE)

#define	RCC ((RCC_TypeDef *) RCC_BASE)

#define	FLASH ((FLASH_TypeDef *) FLASH_R_BASE)

#define	DMA1 ((DMA_TypeDef *) DMA1_BASE)

#define	DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

#define	DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

#define	DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

#define	DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

#define	DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

#define	DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

#define	DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

#define	DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

#define	DMA2 ((DMA_TypeDef *) DMA2_BASE)

#define	DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

#define	DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

#define	DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

#define	DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

#define	DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

#define	DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

#define	DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

#define	DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

#define	ETH ((ETH_TypeDef *) ETH_BASE)

#define	DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)

#define	DCMI ((DCMI_TypeDef *) DCMI_BASE)

#define	CRYP ((CRYP_TypeDef *) CRYP_BASE)

#define	HASH ((HASH_TypeDef *) HASH_BASE)

#define	HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)

#define	RNG ((RNG_TypeDef *) RNG_BASE)

#define	FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

#define	FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

#define	FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

#define	FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

#define	QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)

#define	DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

#define	USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)

#define	USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)

#define	ADC_SR_AWD 0x00000001U

#define	ADC_SR_EOC 0x00000002U

#define	ADC_SR_JEOC 0x00000004U

#define	ADC_SR_JSTRT 0x00000008U

#define	ADC_SR_STRT 0x00000010U

#define	ADC_SR_OVR 0x00000020U

#define	ADC_CR1_AWDCH 0x0000001FU

#define	ADC_CR1_AWDCH_0 0x00000001U

#define	ADC_CR1_AWDCH_1 0x00000002U

#define	ADC_CR1_AWDCH_2 0x00000004U

#define	ADC_CR1_AWDCH_3 0x00000008U

#define	ADC_CR1_AWDCH_4 0x00000010U

#define	ADC_CR1_EOCIE 0x00000020U

#define	ADC_CR1_AWDIE 0x00000040U

#define	ADC_CR1_JEOCIE 0x00000080U

#define	ADC_CR1_SCAN 0x00000100U

#define	ADC_CR1_AWDSGL 0x00000200U

#define	ADC_CR1_JAUTO 0x00000400U

#define	ADC_CR1_DISCEN 0x00000800U

#define	ADC_CR1_JDISCEN 0x00001000U

#define	ADC_CR1_DISCNUM 0x0000E000U

#define	ADC_CR1_DISCNUM_0 0x00002000U

#define	ADC_CR1_DISCNUM_1 0x00004000U

#define	ADC_CR1_DISCNUM_2 0x00008000U

#define	ADC_CR1_JAWDEN 0x00400000U

#define	ADC_CR1_AWDEN 0x00800000U

#define	ADC_CR1_RES 0x03000000U

#define	ADC_CR1_RES_0 0x01000000U

#define	ADC_CR1_RES_1 0x02000000U

#define	ADC_CR1_OVRIE 0x04000000U

#define	ADC_CR2_ADON 0x00000001U

#define	ADC_CR2_CONT 0x00000002U

#define	ADC_CR2_DMA 0x00000100U

#define	ADC_CR2_DDS 0x00000200U

#define	ADC_CR2_EOCS 0x00000400U

#define	ADC_CR2_ALIGN 0x00000800U

#define	ADC_CR2_JEXTSEL 0x000F0000U

#define	ADC_CR2_JEXTSEL_0 0x00010000U

#define	ADC_CR2_JEXTSEL_1 0x00020000U

#define	ADC_CR2_JEXTSEL_2 0x00040000U

#define	ADC_CR2_JEXTSEL_3 0x00080000U

#define	ADC_CR2_JEXTEN 0x00300000U

#define	ADC_CR2_JEXTEN_0 0x00100000U

#define	ADC_CR2_JEXTEN_1 0x00200000U

#define	ADC_CR2_JSWSTART 0x00400000U

#define	ADC_CR2_EXTSEL 0x0F000000U

#define	ADC_CR2_EXTSEL_0 0x01000000U

#define	ADC_CR2_EXTSEL_1 0x02000000U

#define	ADC_CR2_EXTSEL_2 0x04000000U

#define	ADC_CR2_EXTSEL_3 0x08000000U

#define	ADC_CR2_EXTEN 0x30000000U

#define	ADC_CR2_EXTEN_0 0x10000000U

#define	ADC_CR2_EXTEN_1 0x20000000U

#define	ADC_CR2_SWSTART 0x40000000U

#define	ADC_SMPR1_SMP10 0x00000007U

#define	ADC_SMPR1_SMP10_0 0x00000001U

#define	ADC_SMPR1_SMP10_1 0x00000002U

#define	ADC_SMPR1_SMP10_2 0x00000004U

#define	ADC_SMPR1_SMP11 0x00000038U

#define	ADC_SMPR1_SMP11_0 0x00000008U

#define	ADC_SMPR1_SMP11_1 0x00000010U

#define	ADC_SMPR1_SMP11_2 0x00000020U

#define	ADC_SMPR1_SMP12 0x000001C0U

#define	ADC_SMPR1_SMP12_0 0x00000040U

#define	ADC_SMPR1_SMP12_1 0x00000080U

#define	ADC_SMPR1_SMP12_2 0x00000100U

#define	ADC_SMPR1_SMP13 0x00000E00U

#define	ADC_SMPR1_SMP13_0 0x00000200U

#define	ADC_SMPR1_SMP13_1 0x00000400U

#define	ADC_SMPR1_SMP13_2 0x00000800U

#define	ADC_SMPR1_SMP14 0x00007000U

#define	ADC_SMPR1_SMP14_0 0x00001000U

#define	ADC_SMPR1_SMP14_1 0x00002000U

#define	ADC_SMPR1_SMP14_2 0x00004000U

#define	ADC_SMPR1_SMP15 0x00038000U

#define	ADC_SMPR1_SMP15_0 0x00008000U

#define	ADC_SMPR1_SMP15_1 0x00010000U

#define	ADC_SMPR1_SMP15_2 0x00020000U

#define	ADC_SMPR1_SMP16 0x001C0000U

#define	ADC_SMPR1_SMP16_0 0x00040000U

#define	ADC_SMPR1_SMP16_1 0x00080000U

#define	ADC_SMPR1_SMP16_2 0x00100000U

#define	ADC_SMPR1_SMP17 0x00E00000U

#define	ADC_SMPR1_SMP17_0 0x00200000U

#define	ADC_SMPR1_SMP17_1 0x00400000U

#define	ADC_SMPR1_SMP17_2 0x00800000U

#define	ADC_SMPR1_SMP18 0x07000000U

#define	ADC_SMPR1_SMP18_0 0x01000000U

#define	ADC_SMPR1_SMP18_1 0x02000000U

#define	ADC_SMPR1_SMP18_2 0x04000000U

#define	ADC_SMPR2_SMP0 0x00000007U

#define	ADC_SMPR2_SMP0_0 0x00000001U

#define	ADC_SMPR2_SMP0_1 0x00000002U

#define	ADC_SMPR2_SMP0_2 0x00000004U

#define	ADC_SMPR2_SMP1 0x00000038U

#define	ADC_SMPR2_SMP1_0 0x00000008U

#define	ADC_SMPR2_SMP1_1 0x00000010U

#define	ADC_SMPR2_SMP1_2 0x00000020U

#define	ADC_SMPR2_SMP2 0x000001C0U

#define	ADC_SMPR2_SMP2_0 0x00000040U

#define	ADC_SMPR2_SMP2_1 0x00000080U

#define	ADC_SMPR2_SMP2_2 0x00000100U

#define	ADC_SMPR2_SMP3 0x00000E00U

#define	ADC_SMPR2_SMP3_0 0x00000200U

#define	ADC_SMPR2_SMP3_1 0x00000400U

#define	ADC_SMPR2_SMP3_2 0x00000800U

#define	ADC_SMPR2_SMP4 0x00007000U

#define	ADC_SMPR2_SMP4_0 0x00001000U

#define	ADC_SMPR2_SMP4_1 0x00002000U

#define	ADC_SMPR2_SMP4_2 0x00004000U

#define	ADC_SMPR2_SMP5 0x00038000U

#define	ADC_SMPR2_SMP5_0 0x00008000U

#define	ADC_SMPR2_SMP5_1 0x00010000U

#define	ADC_SMPR2_SMP5_2 0x00020000U

#define	ADC_SMPR2_SMP6 0x001C0000U

#define	ADC_SMPR2_SMP6_0 0x00040000U

#define	ADC_SMPR2_SMP6_1 0x00080000U

#define	ADC_SMPR2_SMP6_2 0x00100000U

#define	ADC_SMPR2_SMP7 0x00E00000U

#define	ADC_SMPR2_SMP7_0 0x00200000U

#define	ADC_SMPR2_SMP7_1 0x00400000U

#define	ADC_SMPR2_SMP7_2 0x00800000U

#define	ADC_SMPR2_SMP8 0x07000000U

#define	ADC_SMPR2_SMP8_0 0x01000000U

#define	ADC_SMPR2_SMP8_1 0x02000000U

#define	ADC_SMPR2_SMP8_2 0x04000000U

#define	ADC_SMPR2_SMP9 0x38000000U

#define	ADC_SMPR2_SMP9_0 0x08000000U

#define	ADC_SMPR2_SMP9_1 0x10000000U

#define	ADC_SMPR2_SMP9_2 0x20000000U

#define	ADC_JOFR1_JOFFSET1 0x0FFFU

#define	ADC_JOFR2_JOFFSET2 0x0FFFU

#define	ADC_JOFR3_JOFFSET3 0x0FFFU

#define	ADC_JOFR4_JOFFSET4 0x0FFFU

#define	ADC_HTR_HT 0x0FFFU

#define	ADC_LTR_LT 0x0FFFU

#define	ADC_SQR1_SQ13 0x0000001FU

#define	ADC_SQR1_SQ13_0 0x00000001U

#define	ADC_SQR1_SQ13_1 0x00000002U

#define	ADC_SQR1_SQ13_2 0x00000004U

#define	ADC_SQR1_SQ13_3 0x00000008U

#define	ADC_SQR1_SQ13_4 0x00000010U

#define	ADC_SQR1_SQ14 0x000003E0U

#define	ADC_SQR1_SQ14_0 0x00000020U

#define	ADC_SQR1_SQ14_1 0x00000040U

#define	ADC_SQR1_SQ14_2 0x00000080U

#define	ADC_SQR1_SQ14_3 0x00000100U

#define	ADC_SQR1_SQ14_4 0x00000200U

#define	ADC_SQR1_SQ15 0x00007C00U

#define	ADC_SQR1_SQ15_0 0x00000400U

#define	ADC_SQR1_SQ15_1 0x00000800U

#define	ADC_SQR1_SQ15_2 0x00001000U

#define	ADC_SQR1_SQ15_3 0x00002000U

#define	ADC_SQR1_SQ15_4 0x00004000U

#define	ADC_SQR1_SQ16 0x000F8000U

#define	ADC_SQR1_SQ16_0 0x00008000U

#define	ADC_SQR1_SQ16_1 0x00010000U

#define	ADC_SQR1_SQ16_2 0x00020000U

#define	ADC_SQR1_SQ16_3 0x00040000U

#define	ADC_SQR1_SQ16_4 0x00080000U

#define	ADC_SQR1_L 0x00F00000U

#define	ADC_SQR1_L_0 0x00100000U

#define	ADC_SQR1_L_1 0x00200000U

#define	ADC_SQR1_L_2 0x00400000U

#define	ADC_SQR1_L_3 0x00800000U

#define	ADC_SQR2_SQ7 0x0000001FU

#define	ADC_SQR2_SQ7_0 0x00000001U

#define	ADC_SQR2_SQ7_1 0x00000002U

#define	ADC_SQR2_SQ7_2 0x00000004U

#define	ADC_SQR2_SQ7_3 0x00000008U

#define	ADC_SQR2_SQ7_4 0x00000010U

#define	ADC_SQR2_SQ8 0x000003E0U

#define	ADC_SQR2_SQ8_0 0x00000020U

#define	ADC_SQR2_SQ8_1 0x00000040U

#define	ADC_SQR2_SQ8_2 0x00000080U

#define	ADC_SQR2_SQ8_3 0x00000100U

#define	ADC_SQR2_SQ8_4 0x00000200U

#define	ADC_SQR2_SQ9 0x00007C00U

#define	ADC_SQR2_SQ9_0 0x00000400U

#define	ADC_SQR2_SQ9_1 0x00000800U

#define	ADC_SQR2_SQ9_2 0x00001000U

#define	ADC_SQR2_SQ9_3 0x00002000U

#define	ADC_SQR2_SQ9_4 0x00004000U

#define	ADC_SQR2_SQ10 0x000F8000U

#define	ADC_SQR2_SQ10_0 0x00008000U

#define	ADC_SQR2_SQ10_1 0x00010000U

#define	ADC_SQR2_SQ10_2 0x00020000U

#define	ADC_SQR2_SQ10_3 0x00040000U

#define	ADC_SQR2_SQ10_4 0x00080000U

#define	ADC_SQR2_SQ11 0x01F00000U

#define	ADC_SQR2_SQ11_0 0x00100000U

#define	ADC_SQR2_SQ11_1 0x00200000U

#define	ADC_SQR2_SQ11_2 0x00400000U

#define	ADC_SQR2_SQ11_3 0x00800000U

#define	ADC_SQR2_SQ11_4 0x01000000U

#define	ADC_SQR2_SQ12 0x3E000000U

#define	ADC_SQR2_SQ12_0 0x02000000U

#define	ADC_SQR2_SQ12_1 0x04000000U

#define	ADC_SQR2_SQ12_2 0x08000000U

#define	ADC_SQR2_SQ12_3 0x10000000U

#define	ADC_SQR2_SQ12_4 0x20000000U

#define	ADC_SQR3_SQ1 0x0000001FU

#define	ADC_SQR3_SQ1_0 0x00000001U

#define	ADC_SQR3_SQ1_1 0x00000002U

#define	ADC_SQR3_SQ1_2 0x00000004U

#define	ADC_SQR3_SQ1_3 0x00000008U

#define	ADC_SQR3_SQ1_4 0x00000010U

#define	ADC_SQR3_SQ2 0x000003E0U

#define	ADC_SQR3_SQ2_0 0x00000020U

#define	ADC_SQR3_SQ2_1 0x00000040U

#define	ADC_SQR3_SQ2_2 0x00000080U

#define	ADC_SQR3_SQ2_3 0x00000100U

#define	ADC_SQR3_SQ2_4 0x00000200U

#define	ADC_SQR3_SQ3 0x00007C00U

#define	ADC_SQR3_SQ3_0 0x00000400U

#define	ADC_SQR3_SQ3_1 0x00000800U

#define	ADC_SQR3_SQ3_2 0x00001000U

#define	ADC_SQR3_SQ3_3 0x00002000U

#define	ADC_SQR3_SQ3_4 0x00004000U

#define	ADC_SQR3_SQ4 0x000F8000U

#define	ADC_SQR3_SQ4_0 0x00008000U

#define	ADC_SQR3_SQ4_1 0x00010000U

#define	ADC_SQR3_SQ4_2 0x00020000U

#define	ADC_SQR3_SQ4_3 0x00040000U

#define	ADC_SQR3_SQ4_4 0x00080000U

#define	ADC_SQR3_SQ5 0x01F00000U

#define	ADC_SQR3_SQ5_0 0x00100000U

#define	ADC_SQR3_SQ5_1 0x00200000U

#define	ADC_SQR3_SQ5_2 0x00400000U

#define	ADC_SQR3_SQ5_3 0x00800000U

#define	ADC_SQR3_SQ5_4 0x01000000U

#define	ADC_SQR3_SQ6 0x3E000000U

#define	ADC_SQR3_SQ6_0 0x02000000U

#define	ADC_SQR3_SQ6_1 0x04000000U

#define	ADC_SQR3_SQ6_2 0x08000000U

#define	ADC_SQR3_SQ6_3 0x10000000U

#define	ADC_SQR3_SQ6_4 0x20000000U

#define	ADC_JSQR_JSQ1 0x0000001FU

#define	ADC_JSQR_JSQ1_0 0x00000001U

#define	ADC_JSQR_JSQ1_1 0x00000002U

#define	ADC_JSQR_JSQ1_2 0x00000004U

#define	ADC_JSQR_JSQ1_3 0x00000008U

#define	ADC_JSQR_JSQ1_4 0x00000010U

#define	ADC_JSQR_JSQ2 0x000003E0U

#define	ADC_JSQR_JSQ2_0 0x00000020U

#define	ADC_JSQR_JSQ2_1 0x00000040U

#define	ADC_JSQR_JSQ2_2 0x00000080U

#define	ADC_JSQR_JSQ2_3 0x00000100U

#define	ADC_JSQR_JSQ2_4 0x00000200U

#define	ADC_JSQR_JSQ3 0x00007C00U

#define	ADC_JSQR_JSQ3_0 0x00000400U

#define	ADC_JSQR_JSQ3_1 0x00000800U

#define	ADC_JSQR_JSQ3_2 0x00001000U

#define	ADC_JSQR_JSQ3_3 0x00002000U

#define	ADC_JSQR_JSQ3_4 0x00004000U

#define	ADC_JSQR_JSQ4 0x000F8000U

#define	ADC_JSQR_JSQ4_0 0x00008000U

#define	ADC_JSQR_JSQ4_1 0x00010000U

#define	ADC_JSQR_JSQ4_2 0x00020000U

#define	ADC_JSQR_JSQ4_3 0x00040000U

#define	ADC_JSQR_JSQ4_4 0x00080000U

#define	ADC_JSQR_JL 0x00300000U

#define	ADC_JSQR_JL_0 0x00100000U

#define	ADC_JSQR_JL_1 0x00200000U

#define	ADC_JDR1_JDATA ((uint16_t)0xFFFFU)

#define	ADC_JDR2_JDATA ((uint16_t)0xFFFFU)

#define	ADC_JDR3_JDATA ((uint16_t)0xFFFFU)

#define	ADC_JDR4_JDATA ((uint16_t)0xFFFFU)

#define	ADC_DR_DATA 0x0000FFFFU

#define	ADC_DR_ADC2DATA 0xFFFF0000U

#define	ADC_CSR_AWD1 0x00000001U

#define	ADC_CSR_EOC1 0x00000002U

#define	ADC_CSR_JEOC1 0x00000004U

#define	ADC_CSR_JSTRT1 0x00000008U

#define	ADC_CSR_STRT1 0x00000010U

#define	ADC_CSR_OVR1 0x00000020U

#define	ADC_CSR_AWD2 0x00000100U

#define	ADC_CSR_EOC2 0x00000200U

#define	ADC_CSR_JEOC2 0x00000400U

#define	ADC_CSR_JSTRT2 0x00000800U

#define	ADC_CSR_STRT2 0x00001000U

#define	ADC_CSR_OVR2 0x00002000U

#define	ADC_CSR_AWD3 0x00010000U

#define	ADC_CSR_EOC3 0x00020000U

#define	ADC_CSR_JEOC3 0x00040000U

#define	ADC_CSR_JSTRT3 0x00080000U

#define	ADC_CSR_STRT3 0x00100000U

#define	ADC_CSR_OVR3 0x00200000U

#define	ADC_CSR_DOVR1 ADC_CSR_OVR1

#define	ADC_CSR_DOVR2 ADC_CSR_OVR2

#define	ADC_CSR_DOVR3 ADC_CSR_OVR3

#define	ADC_CCR_MULTI 0x0000001FU

#define	ADC_CCR_MULTI_0 0x00000001U

#define	ADC_CCR_MULTI_1 0x00000002U

#define	ADC_CCR_MULTI_2 0x00000004U

#define	ADC_CCR_MULTI_3 0x00000008U

#define	ADC_CCR_MULTI_4 0x00000010U

#define	ADC_CCR_DELAY 0x00000F00U

#define	ADC_CCR_DELAY_0 0x00000100U

#define	ADC_CCR_DELAY_1 0x00000200U

#define	ADC_CCR_DELAY_2 0x00000400U

#define	ADC_CCR_DELAY_3 0x00000800U

#define	ADC_CCR_DDS 0x00002000U

#define	ADC_CCR_DMA 0x0000C000U

#define	ADC_CCR_DMA_0 0x00004000U

#define	ADC_CCR_DMA_1 0x00008000U

#define	ADC_CCR_ADCPRE 0x00030000U

#define	ADC_CCR_ADCPRE_0 0x00010000U

#define	ADC_CCR_ADCPRE_1 0x00020000U

#define	ADC_CCR_VBATE 0x00400000U

#define	ADC_CCR_TSVREFE 0x00800000U

#define	ADC_CDR_DATA1 0x0000FFFFU

#define	ADC_CDR_DATA2 0xFFFF0000U

#define	CAN_MCR_INRQ 0x00000001U

#define	CAN_MCR_SLEEP 0x00000002U

#define	CAN_MCR_TXFP 0x00000004U

#define	CAN_MCR_RFLM 0x00000008U

#define	CAN_MCR_NART 0x00000010U

#define	CAN_MCR_AWUM 0x00000020U

#define	CAN_MCR_ABOM 0x00000040U

#define	CAN_MCR_TTCM 0x00000080U

#define	CAN_MCR_RESET 0x00008000U

#define	CAN_MSR_INAK 0x00000001U

#define	CAN_MSR_SLAK 0x00000002U

#define	CAN_MSR_ERRI 0x00000004U

#define	CAN_MSR_WKUI 0x00000008U

#define	CAN_MSR_SLAKI 0x00000010U

#define	CAN_MSR_TXM 0x00000100U

#define	CAN_MSR_RXM 0x00000200U

#define	CAN_MSR_SAMP 0x00000400U

#define	CAN_MSR_RX 0x00000800U

#define	CAN_TSR_RQCP0 0x00000001U

#define	CAN_TSR_TXOK0 0x00000002U

#define	CAN_TSR_ALST0 0x00000004U

#define	CAN_TSR_TERR0 0x00000008U

#define	CAN_TSR_ABRQ0 0x00000080U

#define	CAN_TSR_RQCP1 0x00000100U

#define	CAN_TSR_TXOK1 0x00000200U

#define	CAN_TSR_ALST1 0x00000400U

#define	CAN_TSR_TERR1 0x00000800U

#define	CAN_TSR_ABRQ1 0x00008000U

#define	CAN_TSR_RQCP2 0x00010000U

#define	CAN_TSR_TXOK2 0x00020000U

#define	CAN_TSR_ALST2 0x00040000U

#define	CAN_TSR_TERR2 0x00080000U

#define	CAN_TSR_ABRQ2 0x00800000U

#define	CAN_TSR_CODE 0x03000000U

#define	CAN_TSR_TME 0x1C000000U

#define	CAN_TSR_TME0 0x04000000U

#define	CAN_TSR_TME1 0x08000000U

#define	CAN_TSR_TME2 0x10000000U

#define	CAN_TSR_LOW 0xE0000000U

#define	CAN_TSR_LOW0 0x20000000U

#define	CAN_TSR_LOW1 0x40000000U

#define	CAN_TSR_LOW2 0x80000000U

#define	CAN_RF0R_FMP0 0x00000003U

#define	CAN_RF0R_FULL0 0x00000008U

#define	CAN_RF0R_FOVR0 0x00000010U

#define	CAN_RF0R_RFOM0 0x00000020U

#define	CAN_RF1R_FMP1 0x00000003U

#define	CAN_RF1R_FULL1 0x00000008U

#define	CAN_RF1R_FOVR1 0x00000010U

#define	CAN_RF1R_RFOM1 0x00000020U

#define	CAN_IER_TMEIE 0x00000001U

#define	CAN_IER_FMPIE0 0x00000002U

#define	CAN_IER_FFIE0 0x00000004U

#define	CAN_IER_FOVIE0 0x00000008U

#define	CAN_IER_FMPIE1 0x00000010U

#define	CAN_IER_FFIE1 0x00000020U

#define	CAN_IER_FOVIE1 0x00000040U

#define	CAN_IER_EWGIE 0x00000100U

#define	CAN_IER_EPVIE 0x00000200U

#define	CAN_IER_BOFIE 0x00000400U

#define	CAN_IER_LECIE 0x00000800U

#define	CAN_IER_ERRIE 0x00008000U

#define	CAN_IER_WKUIE 0x00010000U

#define	CAN_IER_SLKIE 0x00020000U

#define	CAN_ESR_EWGF 0x00000001U

#define	CAN_ESR_EPVF 0x00000002U

#define	CAN_ESR_BOFF 0x00000004U

#define	CAN_ESR_LEC 0x00000070U

#define	CAN_ESR_LEC_0 0x00000010U

#define	CAN_ESR_LEC_1 0x00000020U

#define	CAN_ESR_LEC_2 0x00000040U

#define	CAN_ESR_TEC 0x00FF0000U

#define	CAN_ESR_REC 0xFF000000U

#define	CAN_BTR_BRP 0x000003FFU

#define	CAN_BTR_TS1 0x000F0000U

#define	CAN_BTR_TS1_0 0x00010000U

#define	CAN_BTR_TS1_1 0x00020000U

#define	CAN_BTR_TS1_2 0x00040000U

#define	CAN_BTR_TS1_3 0x00080000U

#define	CAN_BTR_TS2 0x00700000U

#define	CAN_BTR_TS2_0 0x00100000U

#define	CAN_BTR_TS2_1 0x00200000U

#define	CAN_BTR_TS2_2 0x00400000U

#define	CAN_BTR_SJW 0x03000000U

#define	CAN_BTR_SJW_0 0x01000000U

#define	CAN_BTR_SJW_1 0x02000000U

#define	CAN_BTR_LBKM 0x40000000U

#define	CAN_BTR_SILM 0x80000000U

#define	CAN_TI0R_TXRQ 0x00000001U

#define	CAN_TI0R_RTR 0x00000002U

#define	CAN_TI0R_IDE 0x00000004U

#define	CAN_TI0R_EXID 0x001FFFF8U

#define	CAN_TI0R_STID 0xFFE00000U

#define	CAN_TDT0R_DLC 0x0000000FU

#define	CAN_TDT0R_TGT 0x00000100U

#define	CAN_TDT0R_TIME 0xFFFF0000U

#define	CAN_TDL0R_DATA0 0x000000FFU

#define	CAN_TDL0R_DATA1 0x0000FF00U

#define	CAN_TDL0R_DATA2 0x00FF0000U

#define	CAN_TDL0R_DATA3 0xFF000000U

#define	CAN_TDH0R_DATA4 0x000000FFU

#define	CAN_TDH0R_DATA5 0x0000FF00U

#define	CAN_TDH0R_DATA6 0x00FF0000U

#define	CAN_TDH0R_DATA7 0xFF000000U

#define	CAN_TI1R_TXRQ 0x00000001U

#define	CAN_TI1R_RTR 0x00000002U

#define	CAN_TI1R_IDE 0x00000004U

#define	CAN_TI1R_EXID 0x001FFFF8U

#define	CAN_TI1R_STID 0xFFE00000U

#define	CAN_TDT1R_DLC 0x0000000FU

#define	CAN_TDT1R_TGT 0x00000100U

#define	CAN_TDT1R_TIME 0xFFFF0000U

#define	CAN_TDL1R_DATA0 0x000000FFU

#define	CAN_TDL1R_DATA1 0x0000FF00U

#define	CAN_TDL1R_DATA2 0x00FF0000U

#define	CAN_TDL1R_DATA3 0xFF000000U

#define	CAN_TDH1R_DATA4 0x000000FFU

#define	CAN_TDH1R_DATA5 0x0000FF00U

#define	CAN_TDH1R_DATA6 0x00FF0000U

#define	CAN_TDH1R_DATA7 0xFF000000U

#define	CAN_TI2R_TXRQ 0x00000001U

#define	CAN_TI2R_RTR 0x00000002U

#define	CAN_TI2R_IDE 0x00000004U

#define	CAN_TI2R_EXID 0x001FFFF8U

#define	CAN_TI2R_STID 0xFFE00000U

#define	CAN_TDT2R_DLC 0x0000000FU

#define	CAN_TDT2R_TGT 0x00000100U

#define	CAN_TDT2R_TIME 0xFFFF0000U

#define	CAN_TDL2R_DATA0 0x000000FFU

#define	CAN_TDL2R_DATA1 0x0000FF00U

#define	CAN_TDL2R_DATA2 0x00FF0000U

#define	CAN_TDL2R_DATA3 0xFF000000U

#define	CAN_TDH2R_DATA4 0x000000FFU

#define	CAN_TDH2R_DATA5 0x0000FF00U

#define	CAN_TDH2R_DATA6 0x00FF0000U

#define	CAN_TDH2R_DATA7 0xFF000000U

#define	CAN_RI0R_RTR 0x00000002U

#define	CAN_RI0R_IDE 0x00000004U

#define	CAN_RI0R_EXID 0x001FFFF8U

#define	CAN_RI0R_STID 0xFFE00000U

#define	CAN_RDT0R_DLC 0x0000000FU

#define	CAN_RDT0R_FMI 0x0000FF00U

#define	CAN_RDT0R_TIME 0xFFFF0000U

#define	CAN_RDL0R_DATA0 0x000000FFU

#define	CAN_RDL0R_DATA1 0x0000FF00U

#define	CAN_RDL0R_DATA2 0x00FF0000U

#define	CAN_RDL0R_DATA3 0xFF000000U

#define	CAN_RDH0R_DATA4 0x000000FFU

#define	CAN_RDH0R_DATA5 0x0000FF00U

#define	CAN_RDH0R_DATA6 0x00FF0000U

#define	CAN_RDH0R_DATA7 0xFF000000U

#define	CAN_RI1R_RTR 0x00000002U

#define	CAN_RI1R_IDE 0x00000004U

#define	CAN_RI1R_EXID 0x001FFFF8U

#define	CAN_RI1R_STID 0xFFE00000U

#define	CAN_RDT1R_DLC 0x0000000FU

#define	CAN_RDT1R_FMI 0x0000FF00U

#define	CAN_RDT1R_TIME 0xFFFF0000U

#define	CAN_RDL1R_DATA0 0x000000FFU

#define	CAN_RDL1R_DATA1 0x0000FF00U

#define	CAN_RDL1R_DATA2 0x00FF0000U

#define	CAN_RDL1R_DATA3 0xFF000000U

#define	CAN_RDH1R_DATA4 0x000000FFU

#define	CAN_RDH1R_DATA5 0x0000FF00U

#define	CAN_RDH1R_DATA6 0x00FF0000U

#define	CAN_RDH1R_DATA7 0xFF000000U

#define	CAN_FMR_FINIT ((uint8_t)0x01U)

#define	CAN_FMR_CAN2SB 0x00003F00U

#define	CAN_FM1R_FBM 0x3FFFU

#define	CAN_FM1R_FBM0 0x0001U

#define	CAN_FM1R_FBM1 0x0002U

#define	CAN_FM1R_FBM2 0x0004U

#define	CAN_FM1R_FBM3 0x0008U

#define	CAN_FM1R_FBM4 0x0010U

#define	CAN_FM1R_FBM5 0x0020U

#define	CAN_FM1R_FBM6 0x0040U

#define	CAN_FM1R_FBM7 0x0080U

#define	CAN_FM1R_FBM8 0x0100U

#define	CAN_FM1R_FBM9 0x0200U

#define	CAN_FM1R_FBM10 0x0400U

#define	CAN_FM1R_FBM11 0x0800U

#define	CAN_FM1R_FBM12 0x1000U

#define	CAN_FM1R_FBM13 0x2000U

#define	CAN_FS1R_FSC 0x00003FFFU

#define	CAN_FS1R_FSC0 0x00000001U

#define	CAN_FS1R_FSC1 0x00000002U

#define	CAN_FS1R_FSC2 0x00000004U

#define	CAN_FS1R_FSC3 0x00000008U

#define	CAN_FS1R_FSC4 0x00000010U

#define	CAN_FS1R_FSC5 0x00000020U

#define	CAN_FS1R_FSC6 0x00000040U

#define	CAN_FS1R_FSC7 0x00000080U

#define	CAN_FS1R_FSC8 0x00000100U

#define	CAN_FS1R_FSC9 0x00000200U

#define	CAN_FS1R_FSC10 0x00000400U

#define	CAN_FS1R_FSC11 0x00000800U

#define	CAN_FS1R_FSC12 0x00001000U

#define	CAN_FS1R_FSC13 0x00002000U

#define	CAN_FFA1R_FFA 0x00003FFFU

#define	CAN_FFA1R_FFA0 0x00000001U

#define	CAN_FFA1R_FFA1 0x00000002U

#define	CAN_FFA1R_FFA2 0x00000004U

#define	CAN_FFA1R_FFA3 0x00000008U

#define	CAN_FFA1R_FFA4 0x00000010U

#define	CAN_FFA1R_FFA5 0x00000020U

#define	CAN_FFA1R_FFA6 0x00000040U

#define	CAN_FFA1R_FFA7 0x00000080U

#define	CAN_FFA1R_FFA8 0x00000100U

#define	CAN_FFA1R_FFA9 0x00000200U

#define	CAN_FFA1R_FFA10 0x00000400U

#define	CAN_FFA1R_FFA11 0x00000800U

#define	CAN_FFA1R_FFA12 0x00001000U

#define	CAN_FFA1R_FFA13 0x00002000U

#define	CAN_FA1R_FACT 0x00003FFFU

#define	CAN_FA1R_FACT0 0x00000001U

#define	CAN_FA1R_FACT1 0x00000002U

#define	CAN_FA1R_FACT2 0x00000004U

#define	CAN_FA1R_FACT3 0x00000008U

#define	CAN_FA1R_FACT4 0x00000010U

#define	CAN_FA1R_FACT5 0x00000020U

#define	CAN_FA1R_FACT6 0x00000040U

#define	CAN_FA1R_FACT7 0x00000080U

#define	CAN_FA1R_FACT8 0x00000100U

#define	CAN_FA1R_FACT9 0x00000200U

#define	CAN_FA1R_FACT10 0x00000400U

#define	CAN_FA1R_FACT11 0x00000800U

#define	CAN_FA1R_FACT12 0x00001000U

#define	CAN_FA1R_FACT13 0x00002000U

#define	CAN_F0R1_FB0 0x00000001U

#define	CAN_F0R1_FB1 0x00000002U

#define	CAN_F0R1_FB2 0x00000004U

#define	CAN_F0R1_FB3 0x00000008U

#define	CAN_F0R1_FB4 0x00000010U

#define	CAN_F0R1_FB5 0x00000020U

#define	CAN_F0R1_FB6 0x00000040U

#define	CAN_F0R1_FB7 0x00000080U

#define	CAN_F0R1_FB8 0x00000100U

#define	CAN_F0R1_FB9 0x00000200U

#define	CAN_F0R1_FB10 0x00000400U

#define	CAN_F0R1_FB11 0x00000800U

#define	CAN_F0R1_FB12 0x00001000U

#define	CAN_F0R1_FB13 0x00002000U

#define	CAN_F0R1_FB14 0x00004000U

#define	CAN_F0R1_FB15 0x00008000U

#define	CAN_F0R1_FB16 0x00010000U

#define	CAN_F0R1_FB17 0x00020000U

#define	CAN_F0R1_FB18 0x00040000U

#define	CAN_F0R1_FB19 0x00080000U

#define	CAN_F0R1_FB20 0x00100000U

#define	CAN_F0R1_FB21 0x00200000U

#define	CAN_F0R1_FB22 0x00400000U

#define	CAN_F0R1_FB23 0x00800000U

#define	CAN_F0R1_FB24 0x01000000U

#define	CAN_F0R1_FB25 0x02000000U

#define	CAN_F0R1_FB26 0x04000000U

#define	CAN_F0R1_FB27 0x08000000U

#define	CAN_F0R1_FB28 0x10000000U

#define	CAN_F0R1_FB29 0x20000000U

#define	CAN_F0R1_FB30 0x40000000U

#define	CAN_F0R1_FB31 0x80000000U

#define	CAN_F1R1_FB0 0x00000001U

#define	CAN_F1R1_FB1 0x00000002U

#define	CAN_F1R1_FB2 0x00000004U

#define	CAN_F1R1_FB3 0x00000008U

#define	CAN_F1R1_FB4 0x00000010U

#define	CAN_F1R1_FB5 0x00000020U

#define	CAN_F1R1_FB6 0x00000040U

#define	CAN_F1R1_FB7 0x00000080U

#define	CAN_F1R1_FB8 0x00000100U

#define	CAN_F1R1_FB9 0x00000200U

#define	CAN_F1R1_FB10 0x00000400U

#define	CAN_F1R1_FB11 0x00000800U

#define	CAN_F1R1_FB12 0x00001000U

#define	CAN_F1R1_FB13 0x00002000U

#define	CAN_F1R1_FB14 0x00004000U

#define	CAN_F1R1_FB15 0x00008000U

#define	CAN_F1R1_FB16 0x00010000U

#define	CAN_F1R1_FB17 0x00020000U

#define	CAN_F1R1_FB18 0x00040000U

#define	CAN_F1R1_FB19 0x00080000U

#define	CAN_F1R1_FB20 0x00100000U

#define	CAN_F1R1_FB21 0x00200000U

#define	CAN_F1R1_FB22 0x00400000U

#define	CAN_F1R1_FB23 0x00800000U

#define	CAN_F1R1_FB24 0x01000000U

#define	CAN_F1R1_FB25 0x02000000U

#define	CAN_F1R1_FB26 0x04000000U

#define	CAN_F1R1_FB27 0x08000000U

#define	CAN_F1R1_FB28 0x10000000U

#define	CAN_F1R1_FB29 0x20000000U

#define	CAN_F1R1_FB30 0x40000000U

#define	CAN_F1R1_FB31 0x80000000U

#define	CAN_F2R1_FB0 0x00000001U

#define	CAN_F2R1_FB1 0x00000002U

#define	CAN_F2R1_FB2 0x00000004U

#define	CAN_F2R1_FB3 0x00000008U

#define	CAN_F2R1_FB4 0x00000010U

#define	CAN_F2R1_FB5 0x00000020U

#define	CAN_F2R1_FB6 0x00000040U

#define	CAN_F2R1_FB7 0x00000080U

#define	CAN_F2R1_FB8 0x00000100U

#define	CAN_F2R1_FB9 0x00000200U

#define	CAN_F2R1_FB10 0x00000400U

#define	CAN_F2R1_FB11 0x00000800U

#define	CAN_F2R1_FB12 0x00001000U

#define	CAN_F2R1_FB13 0x00002000U

#define	CAN_F2R1_FB14 0x00004000U

#define	CAN_F2R1_FB15 0x00008000U

#define	CAN_F2R1_FB16 0x00010000U

#define	CAN_F2R1_FB17 0x00020000U

#define	CAN_F2R1_FB18 0x00040000U

#define	CAN_F2R1_FB19 0x00080000U

#define	CAN_F2R1_FB20 0x00100000U

#define	CAN_F2R1_FB21 0x00200000U

#define	CAN_F2R1_FB22 0x00400000U

#define	CAN_F2R1_FB23 0x00800000U

#define	CAN_F2R1_FB24 0x01000000U

#define	CAN_F2R1_FB25 0x02000000U

#define	CAN_F2R1_FB26 0x04000000U

#define	CAN_F2R1_FB27 0x08000000U

#define	CAN_F2R1_FB28 0x10000000U

#define	CAN_F2R1_FB29 0x20000000U

#define	CAN_F2R1_FB30 0x40000000U

#define	CAN_F2R1_FB31 0x80000000U

#define	CAN_F3R1_FB0 0x00000001U

#define	CAN_F3R1_FB1 0x00000002U

#define	CAN_F3R1_FB2 0x00000004U

#define	CAN_F3R1_FB3 0x00000008U

#define	CAN_F3R1_FB4 0x00000010U

#define	CAN_F3R1_FB5 0x00000020U

#define	CAN_F3R1_FB6 0x00000040U

#define	CAN_F3R1_FB7 0x00000080U

#define	CAN_F3R1_FB8 0x00000100U

#define	CAN_F3R1_FB9 0x00000200U

#define	CAN_F3R1_FB10 0x00000400U

#define	CAN_F3R1_FB11 0x00000800U

#define	CAN_F3R1_FB12 0x00001000U

#define	CAN_F3R1_FB13 0x00002000U

#define	CAN_F3R1_FB14 0x00004000U

#define	CAN_F3R1_FB15 0x00008000U

#define	CAN_F3R1_FB16 0x00010000U

#define	CAN_F3R1_FB17 0x00020000U

#define	CAN_F3R1_FB18 0x00040000U

#define	CAN_F3R1_FB19 0x00080000U

#define	CAN_F3R1_FB20 0x00100000U

#define	CAN_F3R1_FB21 0x00200000U

#define	CAN_F3R1_FB22 0x00400000U

#define	CAN_F3R1_FB23 0x00800000U

#define	CAN_F3R1_FB24 0x01000000U

#define	CAN_F3R1_FB25 0x02000000U

#define	CAN_F3R1_FB26 0x04000000U

#define	CAN_F3R1_FB27 0x08000000U

#define	CAN_F3R1_FB28 0x10000000U

#define	CAN_F3R1_FB29 0x20000000U

#define	CAN_F3R1_FB30 0x40000000U

#define	CAN_F3R1_FB31 0x80000000U

#define	CAN_F4R1_FB0 0x00000001U

#define	CAN_F4R1_FB1 0x00000002U

#define	CAN_F4R1_FB2 0x00000004U

#define	CAN_F4R1_FB3 0x00000008U

#define	CAN_F4R1_FB4 0x00000010U

#define	CAN_F4R1_FB5 0x00000020U

#define	CAN_F4R1_FB6 0x00000040U

#define	CAN_F4R1_FB7 0x00000080U

#define	CAN_F4R1_FB8 0x00000100U

#define	CAN_F4R1_FB9 0x00000200U

#define	CAN_F4R1_FB10 0x00000400U

#define	CAN_F4R1_FB11 0x00000800U

#define	CAN_F4R1_FB12 0x00001000U

#define	CAN_F4R1_FB13 0x00002000U

#define	CAN_F4R1_FB14 0x00004000U

#define	CAN_F4R1_FB15 0x00008000U

#define	CAN_F4R1_FB16 0x00010000U

#define	CAN_F4R1_FB17 0x00020000U

#define	CAN_F4R1_FB18 0x00040000U

#define	CAN_F4R1_FB19 0x00080000U

#define	CAN_F4R1_FB20 0x00100000U

#define	CAN_F4R1_FB21 0x00200000U

#define	CAN_F4R1_FB22 0x00400000U

#define	CAN_F4R1_FB23 0x00800000U

#define	CAN_F4R1_FB24 0x01000000U

#define	CAN_F4R1_FB25 0x02000000U

#define	CAN_F4R1_FB26 0x04000000U

#define	CAN_F4R1_FB27 0x08000000U

#define	CAN_F4R1_FB28 0x10000000U

#define	CAN_F4R1_FB29 0x20000000U

#define	CAN_F4R1_FB30 0x40000000U

#define	CAN_F4R1_FB31 0x80000000U

#define	CAN_F5R1_FB0 0x00000001U

#define	CAN_F5R1_FB1 0x00000002U

#define	CAN_F5R1_FB2 0x00000004U

#define	CAN_F5R1_FB3 0x00000008U

#define	CAN_F5R1_FB4 0x00000010U

#define	CAN_F5R1_FB5 0x00000020U

#define	CAN_F5R1_FB6 0x00000040U

#define	CAN_F5R1_FB7 0x00000080U

#define	CAN_F5R1_FB8 0x00000100U

#define	CAN_F5R1_FB9 0x00000200U

#define	CAN_F5R1_FB10 0x00000400U

#define	CAN_F5R1_FB11 0x00000800U

#define	CAN_F5R1_FB12 0x00001000U

#define	CAN_F5R1_FB13 0x00002000U

#define	CAN_F5R1_FB14 0x00004000U

#define	CAN_F5R1_FB15 0x00008000U

#define	CAN_F5R1_FB16 0x00010000U

#define	CAN_F5R1_FB17 0x00020000U

#define	CAN_F5R1_FB18 0x00040000U

#define	CAN_F5R1_FB19 0x00080000U

#define	CAN_F5R1_FB20 0x00100000U

#define	CAN_F5R1_FB21 0x00200000U

#define	CAN_F5R1_FB22 0x00400000U

#define	CAN_F5R1_FB23 0x00800000U

#define	CAN_F5R1_FB24 0x01000000U

#define	CAN_F5R1_FB25 0x02000000U

#define	CAN_F5R1_FB26 0x04000000U

#define	CAN_F5R1_FB27 0x08000000U

#define	CAN_F5R1_FB28 0x10000000U

#define	CAN_F5R1_FB29 0x20000000U

#define	CAN_F5R1_FB30 0x40000000U

#define	CAN_F5R1_FB31 0x80000000U

#define	CAN_F6R1_FB0 0x00000001U

#define	CAN_F6R1_FB1 0x00000002U

#define	CAN_F6R1_FB2 0x00000004U

#define	CAN_F6R1_FB3 0x00000008U

#define	CAN_F6R1_FB4 0x00000010U

#define	CAN_F6R1_FB5 0x00000020U

#define	CAN_F6R1_FB6 0x00000040U

#define	CAN_F6R1_FB7 0x00000080U

#define	CAN_F6R1_FB8 0x00000100U

#define	CAN_F6R1_FB9 0x00000200U

#define	CAN_F6R1_FB10 0x00000400U

#define	CAN_F6R1_FB11 0x00000800U

#define	CAN_F6R1_FB12 0x00001000U

#define	CAN_F6R1_FB13 0x00002000U

#define	CAN_F6R1_FB14 0x00004000U

#define	CAN_F6R1_FB15 0x00008000U

#define	CAN_F6R1_FB16 0x00010000U

#define	CAN_F6R1_FB17 0x00020000U

#define	CAN_F6R1_FB18 0x00040000U

#define	CAN_F6R1_FB19 0x00080000U

#define	CAN_F6R1_FB20 0x00100000U

#define	CAN_F6R1_FB21 0x00200000U

#define	CAN_F6R1_FB22 0x00400000U

#define	CAN_F6R1_FB23 0x00800000U

#define	CAN_F6R1_FB24 0x01000000U

#define	CAN_F6R1_FB25 0x02000000U

#define	CAN_F6R1_FB26 0x04000000U

#define	CAN_F6R1_FB27 0x08000000U

#define	CAN_F6R1_FB28 0x10000000U

#define	CAN_F6R1_FB29 0x20000000U

#define	CAN_F6R1_FB30 0x40000000U

#define	CAN_F6R1_FB31 0x80000000U

#define	CAN_F7R1_FB0 0x00000001U

#define	CAN_F7R1_FB1 0x00000002U

#define	CAN_F7R1_FB2 0x00000004U

#define	CAN_F7R1_FB3 0x00000008U

#define	CAN_F7R1_FB4 0x00000010U

#define	CAN_F7R1_FB5 0x00000020U

#define	CAN_F7R1_FB6 0x00000040U

#define	CAN_F7R1_FB7 0x00000080U

#define	CAN_F7R1_FB8 0x00000100U

#define	CAN_F7R1_FB9 0x00000200U

#define	CAN_F7R1_FB10 0x00000400U

#define	CAN_F7R1_FB11 0x00000800U

#define	CAN_F7R1_FB12 0x00001000U

#define	CAN_F7R1_FB13 0x00002000U

#define	CAN_F7R1_FB14 0x00004000U

#define	CAN_F7R1_FB15 0x00008000U

#define	CAN_F7R1_FB16 0x00010000U

#define	CAN_F7R1_FB17 0x00020000U

#define	CAN_F7R1_FB18 0x00040000U

#define	CAN_F7R1_FB19 0x00080000U

#define	CAN_F7R1_FB20 0x00100000U

#define	CAN_F7R1_FB21 0x00200000U

#define	CAN_F7R1_FB22 0x00400000U

#define	CAN_F7R1_FB23 0x00800000U

#define	CAN_F7R1_FB24 0x01000000U

#define	CAN_F7R1_FB25 0x02000000U

#define	CAN_F7R1_FB26 0x04000000U

#define	CAN_F7R1_FB27 0x08000000U

#define	CAN_F7R1_FB28 0x10000000U

#define	CAN_F7R1_FB29 0x20000000U

#define	CAN_F7R1_FB30 0x40000000U

#define	CAN_F7R1_FB31 0x80000000U

#define	CAN_F8R1_FB0 0x00000001U

#define	CAN_F8R1_FB1 0x00000002U

#define	CAN_F8R1_FB2 0x00000004U

#define	CAN_F8R1_FB3 0x00000008U

#define	CAN_F8R1_FB4 0x00000010U

#define	CAN_F8R1_FB5 0x00000020U

#define	CAN_F8R1_FB6 0x00000040U

#define	CAN_F8R1_FB7 0x00000080U

#define	CAN_F8R1_FB8 0x00000100U

#define	CAN_F8R1_FB9 0x00000200U

#define	CAN_F8R1_FB10 0x00000400U

#define	CAN_F8R1_FB11 0x00000800U

#define	CAN_F8R1_FB12 0x00001000U

#define	CAN_F8R1_FB13 0x00002000U

#define	CAN_F8R1_FB14 0x00004000U

#define	CAN_F8R1_FB15 0x00008000U

#define	CAN_F8R1_FB16 0x00010000U

#define	CAN_F8R1_FB17 0x00020000U

#define	CAN_F8R1_FB18 0x00040000U

#define	CAN_F8R1_FB19 0x00080000U

#define	CAN_F8R1_FB20 0x00100000U

#define	CAN_F8R1_FB21 0x00200000U

#define	CAN_F8R1_FB22 0x00400000U

#define	CAN_F8R1_FB23 0x00800000U

#define	CAN_F8R1_FB24 0x01000000U

#define	CAN_F8R1_FB25 0x02000000U

#define	CAN_F8R1_FB26 0x04000000U

#define	CAN_F8R1_FB27 0x08000000U

#define	CAN_F8R1_FB28 0x10000000U

#define	CAN_F8R1_FB29 0x20000000U

#define	CAN_F8R1_FB30 0x40000000U

#define	CAN_F8R1_FB31 0x80000000U

#define	CAN_F9R1_FB0 0x00000001U

#define	CAN_F9R1_FB1 0x00000002U

#define	CAN_F9R1_FB2 0x00000004U

#define	CAN_F9R1_FB3 0x00000008U

#define	CAN_F9R1_FB4 0x00000010U

#define	CAN_F9R1_FB5 0x00000020U

#define	CAN_F9R1_FB6 0x00000040U

#define	CAN_F9R1_FB7 0x00000080U

#define	CAN_F9R1_FB8 0x00000100U

#define	CAN_F9R1_FB9 0x00000200U

#define	CAN_F9R1_FB10 0x00000400U

#define	CAN_F9R1_FB11 0x00000800U

#define	CAN_F9R1_FB12 0x00001000U

#define	CAN_F9R1_FB13 0x00002000U

#define	CAN_F9R1_FB14 0x00004000U

#define	CAN_F9R1_FB15 0x00008000U

#define	CAN_F9R1_FB16 0x00010000U

#define	CAN_F9R1_FB17 0x00020000U

#define	CAN_F9R1_FB18 0x00040000U

#define	CAN_F9R1_FB19 0x00080000U

#define	CAN_F9R1_FB20 0x00100000U

#define	CAN_F9R1_FB21 0x00200000U

#define	CAN_F9R1_FB22 0x00400000U

#define	CAN_F9R1_FB23 0x00800000U

#define	CAN_F9R1_FB24 0x01000000U

#define	CAN_F9R1_FB25 0x02000000U

#define	CAN_F9R1_FB26 0x04000000U

#define	CAN_F9R1_FB27 0x08000000U

#define	CAN_F9R1_FB28 0x10000000U

#define	CAN_F9R1_FB29 0x20000000U

#define	CAN_F9R1_FB30 0x40000000U

#define	CAN_F9R1_FB31 0x80000000U

#define	CAN_F10R1_FB0 0x00000001U

#define	CAN_F10R1_FB1 0x00000002U

#define	CAN_F10R1_FB2 0x00000004U

#define	CAN_F10R1_FB3 0x00000008U

#define	CAN_F10R1_FB4 0x00000010U

#define	CAN_F10R1_FB5 0x00000020U

#define	CAN_F10R1_FB6 0x00000040U

#define	CAN_F10R1_FB7 0x00000080U

#define	CAN_F10R1_FB8 0x00000100U

#define	CAN_F10R1_FB9 0x00000200U

#define	CAN_F10R1_FB10 0x00000400U

#define	CAN_F10R1_FB11 0x00000800U

#define	CAN_F10R1_FB12 0x00001000U

#define	CAN_F10R1_FB13 0x00002000U

#define	CAN_F10R1_FB14 0x00004000U

#define	CAN_F10R1_FB15 0x00008000U

#define	CAN_F10R1_FB16 0x00010000U

#define	CAN_F10R1_FB17 0x00020000U

#define	CAN_F10R1_FB18 0x00040000U

#define	CAN_F10R1_FB19 0x00080000U

#define	CAN_F10R1_FB20 0x00100000U

#define	CAN_F10R1_FB21 0x00200000U

#define	CAN_F10R1_FB22 0x00400000U

#define	CAN_F10R1_FB23 0x00800000U

#define	CAN_F10R1_FB24 0x01000000U

#define	CAN_F10R1_FB25 0x02000000U

#define	CAN_F10R1_FB26 0x04000000U

#define	CAN_F10R1_FB27 0x08000000U

#define	CAN_F10R1_FB28 0x10000000U

#define	CAN_F10R1_FB29 0x20000000U

#define	CAN_F10R1_FB30 0x40000000U

#define	CAN_F10R1_FB31 0x80000000U

#define	CAN_F11R1_FB0 0x00000001U

#define	CAN_F11R1_FB1 0x00000002U

#define	CAN_F11R1_FB2 0x00000004U

#define	CAN_F11R1_FB3 0x00000008U

#define	CAN_F11R1_FB4 0x00000010U

#define	CAN_F11R1_FB5 0x00000020U

#define	CAN_F11R1_FB6 0x00000040U

#define	CAN_F11R1_FB7 0x00000080U

#define	CAN_F11R1_FB8 0x00000100U

#define	CAN_F11R1_FB9 0x00000200U

#define	CAN_F11R1_FB10 0x00000400U

#define	CAN_F11R1_FB11 0x00000800U

#define	CAN_F11R1_FB12 0x00001000U

#define	CAN_F11R1_FB13 0x00002000U

#define	CAN_F11R1_FB14 0x00004000U

#define	CAN_F11R1_FB15 0x00008000U

#define	CAN_F11R1_FB16 0x00010000U

#define	CAN_F11R1_FB17 0x00020000U

#define	CAN_F11R1_FB18 0x00040000U

#define	CAN_F11R1_FB19 0x00080000U

#define	CAN_F11R1_FB20 0x00100000U

#define	CAN_F11R1_FB21 0x00200000U

#define	CAN_F11R1_FB22 0x00400000U

#define	CAN_F11R1_FB23 0x00800000U

#define	CAN_F11R1_FB24 0x01000000U

#define	CAN_F11R1_FB25 0x02000000U

#define	CAN_F11R1_FB26 0x04000000U

#define	CAN_F11R1_FB27 0x08000000U

#define	CAN_F11R1_FB28 0x10000000U

#define	CAN_F11R1_FB29 0x20000000U

#define	CAN_F11R1_FB30 0x40000000U

#define	CAN_F11R1_FB31 0x80000000U

#define	CAN_F12R1_FB0 0x00000001U

#define	CAN_F12R1_FB1 0x00000002U

#define	CAN_F12R1_FB2 0x00000004U

#define	CAN_F12R1_FB3 0x00000008U

#define	CAN_F12R1_FB4 0x00000010U

#define	CAN_F12R1_FB5 0x00000020U

#define	CAN_F12R1_FB6 0x00000040U

#define	CAN_F12R1_FB7 0x00000080U

#define	CAN_F12R1_FB8 0x00000100U

#define	CAN_F12R1_FB9 0x00000200U

#define	CAN_F12R1_FB10 0x00000400U

#define	CAN_F12R1_FB11 0x00000800U

#define	CAN_F12R1_FB12 0x00001000U

#define	CAN_F12R1_FB13 0x00002000U

#define	CAN_F12R1_FB14 0x00004000U

#define	CAN_F12R1_FB15 0x00008000U

#define	CAN_F12R1_FB16 0x00010000U

#define	CAN_F12R1_FB17 0x00020000U

#define	CAN_F12R1_FB18 0x00040000U

#define	CAN_F12R1_FB19 0x00080000U

#define	CAN_F12R1_FB20 0x00100000U

#define	CAN_F12R1_FB21 0x00200000U

#define	CAN_F12R1_FB22 0x00400000U

#define	CAN_F12R1_FB23 0x00800000U

#define	CAN_F12R1_FB24 0x01000000U

#define	CAN_F12R1_FB25 0x02000000U

#define	CAN_F12R1_FB26 0x04000000U

#define	CAN_F12R1_FB27 0x08000000U

#define	CAN_F12R1_FB28 0x10000000U

#define	CAN_F12R1_FB29 0x20000000U

#define	CAN_F12R1_FB30 0x40000000U

#define	CAN_F12R1_FB31 0x80000000U

#define	CAN_F13R1_FB0 0x00000001U

#define	CAN_F13R1_FB1 0x00000002U

#define	CAN_F13R1_FB2 0x00000004U

#define	CAN_F13R1_FB3 0x00000008U

#define	CAN_F13R1_FB4 0x00000010U

#define	CAN_F13R1_FB5 0x00000020U

#define	CAN_F13R1_FB6 0x00000040U

#define	CAN_F13R1_FB7 0x00000080U

#define	CAN_F13R1_FB8 0x00000100U

#define	CAN_F13R1_FB9 0x00000200U

#define	CAN_F13R1_FB10 0x00000400U

#define	CAN_F13R1_FB11 0x00000800U

#define	CAN_F13R1_FB12 0x00001000U

#define	CAN_F13R1_FB13 0x00002000U

#define	CAN_F13R1_FB14 0x00004000U

#define	CAN_F13R1_FB15 0x00008000U

#define	CAN_F13R1_FB16 0x00010000U

#define	CAN_F13R1_FB17 0x00020000U

#define	CAN_F13R1_FB18 0x00040000U

#define	CAN_F13R1_FB19 0x00080000U

#define	CAN_F13R1_FB20 0x00100000U

#define	CAN_F13R1_FB21 0x00200000U

#define	CAN_F13R1_FB22 0x00400000U

#define	CAN_F13R1_FB23 0x00800000U

#define	CAN_F13R1_FB24 0x01000000U

#define	CAN_F13R1_FB25 0x02000000U

#define	CAN_F13R1_FB26 0x04000000U

#define	CAN_F13R1_FB27 0x08000000U

#define	CAN_F13R1_FB28 0x10000000U

#define	CAN_F13R1_FB29 0x20000000U

#define	CAN_F13R1_FB30 0x40000000U

#define	CAN_F13R1_FB31 0x80000000U

#define	CAN_F0R2_FB0 0x00000001U

#define	CAN_F0R2_FB1 0x00000002U

#define	CAN_F0R2_FB2 0x00000004U

#define	CAN_F0R2_FB3 0x00000008U

#define	CAN_F0R2_FB4 0x00000010U

#define	CAN_F0R2_FB5 0x00000020U

#define	CAN_F0R2_FB6 0x00000040U

#define	CAN_F0R2_FB7 0x00000080U

#define	CAN_F0R2_FB8 0x00000100U

#define	CAN_F0R2_FB9 0x00000200U

#define	CAN_F0R2_FB10 0x00000400U

#define	CAN_F0R2_FB11 0x00000800U

#define	CAN_F0R2_FB12 0x00001000U

#define	CAN_F0R2_FB13 0x00002000U

#define	CAN_F0R2_FB14 0x00004000U

#define	CAN_F0R2_FB15 0x00008000U

#define	CAN_F0R2_FB16 0x00010000U

#define	CAN_F0R2_FB17 0x00020000U

#define	CAN_F0R2_FB18 0x00040000U

#define	CAN_F0R2_FB19 0x00080000U

#define	CAN_F0R2_FB20 0x00100000U

#define	CAN_F0R2_FB21 0x00200000U

#define	CAN_F0R2_FB22 0x00400000U

#define	CAN_F0R2_FB23 0x00800000U

#define	CAN_F0R2_FB24 0x01000000U

#define	CAN_F0R2_FB25 0x02000000U

#define	CAN_F0R2_FB26 0x04000000U

#define	CAN_F0R2_FB27 0x08000000U

#define	CAN_F0R2_FB28 0x10000000U

#define	CAN_F0R2_FB29 0x20000000U

#define	CAN_F0R2_FB30 0x40000000U

#define	CAN_F0R2_FB31 0x80000000U

#define	CAN_F1R2_FB0 0x00000001U

#define	CAN_F1R2_FB1 0x00000002U

#define	CAN_F1R2_FB2 0x00000004U

#define	CAN_F1R2_FB3 0x00000008U

#define	CAN_F1R2_FB4 0x00000010U

#define	CAN_F1R2_FB5 0x00000020U

#define	CAN_F1R2_FB6 0x00000040U

#define	CAN_F1R2_FB7 0x00000080U

#define	CAN_F1R2_FB8 0x00000100U

#define	CAN_F1R2_FB9 0x00000200U

#define	CAN_F1R2_FB10 0x00000400U

#define	CAN_F1R2_FB11 0x00000800U

#define	CAN_F1R2_FB12 0x00001000U

#define	CAN_F1R2_FB13 0x00002000U

#define	CAN_F1R2_FB14 0x00004000U

#define	CAN_F1R2_FB15 0x00008000U

#define	CAN_F1R2_FB16 0x00010000U

#define	CAN_F1R2_FB17 0x00020000U

#define	CAN_F1R2_FB18 0x00040000U

#define	CAN_F1R2_FB19 0x00080000U

#define	CAN_F1R2_FB20 0x00100000U

#define	CAN_F1R2_FB21 0x00200000U

#define	CAN_F1R2_FB22 0x00400000U

#define	CAN_F1R2_FB23 0x00800000U

#define	CAN_F1R2_FB24 0x01000000U

#define	CAN_F1R2_FB25 0x02000000U

#define	CAN_F1R2_FB26 0x04000000U

#define	CAN_F1R2_FB27 0x08000000U

#define	CAN_F1R2_FB28 0x10000000U

#define	CAN_F1R2_FB29 0x20000000U

#define	CAN_F1R2_FB30 0x40000000U

#define	CAN_F1R2_FB31 0x80000000U

#define	CAN_F2R2_FB0 0x00000001U

#define	CAN_F2R2_FB1 0x00000002U

#define	CAN_F2R2_FB2 0x00000004U

#define	CAN_F2R2_FB3 0x00000008U

#define	CAN_F2R2_FB4 0x00000010U

#define	CAN_F2R2_FB5 0x00000020U

#define	CAN_F2R2_FB6 0x00000040U

#define	CAN_F2R2_FB7 0x00000080U

#define	CAN_F2R2_FB8 0x00000100U

#define	CAN_F2R2_FB9 0x00000200U

#define	CAN_F2R2_FB10 0x00000400U

#define	CAN_F2R2_FB11 0x00000800U

#define	CAN_F2R2_FB12 0x00001000U

#define	CAN_F2R2_FB13 0x00002000U

#define	CAN_F2R2_FB14 0x00004000U

#define	CAN_F2R2_FB15 0x00008000U

#define	CAN_F2R2_FB16 0x00010000U

#define	CAN_F2R2_FB17 0x00020000U

#define	CAN_F2R2_FB18 0x00040000U

#define	CAN_F2R2_FB19 0x00080000U

#define	CAN_F2R2_FB20 0x00100000U

#define	CAN_F2R2_FB21 0x00200000U

#define	CAN_F2R2_FB22 0x00400000U

#define	CAN_F2R2_FB23 0x00800000U

#define	CAN_F2R2_FB24 0x01000000U

#define	CAN_F2R2_FB25 0x02000000U

#define	CAN_F2R2_FB26 0x04000000U

#define	CAN_F2R2_FB27 0x08000000U

#define	CAN_F2R2_FB28 0x10000000U

#define	CAN_F2R2_FB29 0x20000000U

#define	CAN_F2R2_FB30 0x40000000U

#define	CAN_F2R2_FB31 0x80000000U

#define	CAN_F3R2_FB0 0x00000001U

#define	CAN_F3R2_FB1 0x00000002U

#define	CAN_F3R2_FB2 0x00000004U

#define	CAN_F3R2_FB3 0x00000008U

#define	CAN_F3R2_FB4 0x00000010U

#define	CAN_F3R2_FB5 0x00000020U

#define	CAN_F3R2_FB6 0x00000040U

#define	CAN_F3R2_FB7 0x00000080U

#define	CAN_F3R2_FB8 0x00000100U

#define	CAN_F3R2_FB9 0x00000200U

#define	CAN_F3R2_FB10 0x00000400U

#define	CAN_F3R2_FB11 0x00000800U

#define	CAN_F3R2_FB12 0x00001000U

#define	CAN_F3R2_FB13 0x00002000U

#define	CAN_F3R2_FB14 0x00004000U

#define	CAN_F3R2_FB15 0x00008000U

#define	CAN_F3R2_FB16 0x00010000U

#define	CAN_F3R2_FB17 0x00020000U

#define	CAN_F3R2_FB18 0x00040000U

#define	CAN_F3R2_FB19 0x00080000U

#define	CAN_F3R2_FB20 0x00100000U

#define	CAN_F3R2_FB21 0x00200000U

#define	CAN_F3R2_FB22 0x00400000U

#define	CAN_F3R2_FB23 0x00800000U

#define	CAN_F3R2_FB24 0x01000000U

#define	CAN_F3R2_FB25 0x02000000U

#define	CAN_F3R2_FB26 0x04000000U

#define	CAN_F3R2_FB27 0x08000000U

#define	CAN_F3R2_FB28 0x10000000U

#define	CAN_F3R2_FB29 0x20000000U

#define	CAN_F3R2_FB30 0x40000000U

#define	CAN_F3R2_FB31 0x80000000U

#define	CAN_F4R2_FB0 0x00000001U

#define	CAN_F4R2_FB1 0x00000002U

#define	CAN_F4R2_FB2 0x00000004U

#define	CAN_F4R2_FB3 0x00000008U

#define	CAN_F4R2_FB4 0x00000010U

#define	CAN_F4R2_FB5 0x00000020U

#define	CAN_F4R2_FB6 0x00000040U

#define	CAN_F4R2_FB7 0x00000080U

#define	CAN_F4R2_FB8 0x00000100U

#define	CAN_F4R2_FB9 0x00000200U

#define	CAN_F4R2_FB10 0x00000400U

#define	CAN_F4R2_FB11 0x00000800U

#define	CAN_F4R2_FB12 0x00001000U

#define	CAN_F4R2_FB13 0x00002000U

#define	CAN_F4R2_FB14 0x00004000U

#define	CAN_F4R2_FB15 0x00008000U

#define	CAN_F4R2_FB16 0x00010000U

#define	CAN_F4R2_FB17 0x00020000U

#define	CAN_F4R2_FB18 0x00040000U

#define	CAN_F4R2_FB19 0x00080000U

#define	CAN_F4R2_FB20 0x00100000U

#define	CAN_F4R2_FB21 0x00200000U

#define	CAN_F4R2_FB22 0x00400000U

#define	CAN_F4R2_FB23 0x00800000U

#define	CAN_F4R2_FB24 0x01000000U

#define	CAN_F4R2_FB25 0x02000000U

#define	CAN_F4R2_FB26 0x04000000U

#define	CAN_F4R2_FB27 0x08000000U

#define	CAN_F4R2_FB28 0x10000000U

#define	CAN_F4R2_FB29 0x20000000U

#define	CAN_F4R2_FB30 0x40000000U

#define	CAN_F4R2_FB31 0x80000000U

#define	CAN_F5R2_FB0 0x00000001U

#define	CAN_F5R2_FB1 0x00000002U

#define	CAN_F5R2_FB2 0x00000004U

#define	CAN_F5R2_FB3 0x00000008U

#define	CAN_F5R2_FB4 0x00000010U

#define	CAN_F5R2_FB5 0x00000020U

#define	CAN_F5R2_FB6 0x00000040U

#define	CAN_F5R2_FB7 0x00000080U

#define	CAN_F5R2_FB8 0x00000100U

#define	CAN_F5R2_FB9 0x00000200U

#define	CAN_F5R2_FB10 0x00000400U

#define	CAN_F5R2_FB11 0x00000800U

#define	CAN_F5R2_FB12 0x00001000U

#define	CAN_F5R2_FB13 0x00002000U

#define	CAN_F5R2_FB14 0x00004000U

#define	CAN_F5R2_FB15 0x00008000U

#define	CAN_F5R2_FB16 0x00010000U

#define	CAN_F5R2_FB17 0x00020000U

#define	CAN_F5R2_FB18 0x00040000U

#define	CAN_F5R2_FB19 0x00080000U

#define	CAN_F5R2_FB20 0x00100000U

#define	CAN_F5R2_FB21 0x00200000U

#define	CAN_F5R2_FB22 0x00400000U

#define	CAN_F5R2_FB23 0x00800000U

#define	CAN_F5R2_FB24 0x01000000U

#define	CAN_F5R2_FB25 0x02000000U

#define	CAN_F5R2_FB26 0x04000000U

#define	CAN_F5R2_FB27 0x08000000U

#define	CAN_F5R2_FB28 0x10000000U

#define	CAN_F5R2_FB29 0x20000000U

#define	CAN_F5R2_FB30 0x40000000U

#define	CAN_F5R2_FB31 0x80000000U

#define	CAN_F6R2_FB0 0x00000001U

#define	CAN_F6R2_FB1 0x00000002U

#define	CAN_F6R2_FB2 0x00000004U

#define	CAN_F6R2_FB3 0x00000008U

#define	CAN_F6R2_FB4 0x00000010U

#define	CAN_F6R2_FB5 0x00000020U

#define	CAN_F6R2_FB6 0x00000040U

#define	CAN_F6R2_FB7 0x00000080U

#define	CAN_F6R2_FB8 0x00000100U

#define	CAN_F6R2_FB9 0x00000200U

#define	CAN_F6R2_FB10 0x00000400U

#define	CAN_F6R2_FB11 0x00000800U

#define	CAN_F6R2_FB12 0x00001000U

#define	CAN_F6R2_FB13 0x00002000U

#define	CAN_F6R2_FB14 0x00004000U

#define	CAN_F6R2_FB15 0x00008000U

#define	CAN_F6R2_FB16 0x00010000U

#define	CAN_F6R2_FB17 0x00020000U

#define	CAN_F6R2_FB18 0x00040000U

#define	CAN_F6R2_FB19 0x00080000U

#define	CAN_F6R2_FB20 0x00100000U

#define	CAN_F6R2_FB21 0x00200000U

#define	CAN_F6R2_FB22 0x00400000U

#define	CAN_F6R2_FB23 0x00800000U

#define	CAN_F6R2_FB24 0x01000000U

#define	CAN_F6R2_FB25 0x02000000U

#define	CAN_F6R2_FB26 0x04000000U

#define	CAN_F6R2_FB27 0x08000000U

#define	CAN_F6R2_FB28 0x10000000U

#define	CAN_F6R2_FB29 0x20000000U

#define	CAN_F6R2_FB30 0x40000000U

#define	CAN_F6R2_FB31 0x80000000U

#define	CAN_F7R2_FB0 0x00000001U

#define	CAN_F7R2_FB1 0x00000002U

#define	CAN_F7R2_FB2 0x00000004U

#define	CAN_F7R2_FB3 0x00000008U

#define	CAN_F7R2_FB4 0x00000010U

#define	CAN_F7R2_FB5 0x00000020U

#define	CAN_F7R2_FB6 0x00000040U

#define	CAN_F7R2_FB7 0x00000080U

#define	CAN_F7R2_FB8 0x00000100U

#define	CAN_F7R2_FB9 0x00000200U

#define	CAN_F7R2_FB10 0x00000400U

#define	CAN_F7R2_FB11 0x00000800U

#define	CAN_F7R2_FB12 0x00001000U

#define	CAN_F7R2_FB13 0x00002000U

#define	CAN_F7R2_FB14 0x00004000U

#define	CAN_F7R2_FB15 0x00008000U

#define	CAN_F7R2_FB16 0x00010000U

#define	CAN_F7R2_FB17 0x00020000U

#define	CAN_F7R2_FB18 0x00040000U

#define	CAN_F7R2_FB19 0x00080000U

#define	CAN_F7R2_FB20 0x00100000U

#define	CAN_F7R2_FB21 0x00200000U

#define	CAN_F7R2_FB22 0x00400000U

#define	CAN_F7R2_FB23 0x00800000U

#define	CAN_F7R2_FB24 0x01000000U

#define	CAN_F7R2_FB25 0x02000000U

#define	CAN_F7R2_FB26 0x04000000U

#define	CAN_F7R2_FB27 0x08000000U

#define	CAN_F7R2_FB28 0x10000000U

#define	CAN_F7R2_FB29 0x20000000U

#define	CAN_F7R2_FB30 0x40000000U

#define	CAN_F7R2_FB31 0x80000000U

#define	CAN_F8R2_FB0 0x00000001U

#define	CAN_F8R2_FB1 0x00000002U

#define	CAN_F8R2_FB2 0x00000004U

#define	CAN_F8R2_FB3 0x00000008U

#define	CAN_F8R2_FB4 0x00000010U

#define	CAN_F8R2_FB5 0x00000020U

#define	CAN_F8R2_FB6 0x00000040U

#define	CAN_F8R2_FB7 0x00000080U

#define	CAN_F8R2_FB8 0x00000100U

#define	CAN_F8R2_FB9 0x00000200U

#define	CAN_F8R2_FB10 0x00000400U

#define	CAN_F8R2_FB11 0x00000800U

#define	CAN_F8R2_FB12 0x00001000U

#define	CAN_F8R2_FB13 0x00002000U

#define	CAN_F8R2_FB14 0x00004000U

#define	CAN_F8R2_FB15 0x00008000U

#define	CAN_F8R2_FB16 0x00010000U

#define	CAN_F8R2_FB17 0x00020000U

#define	CAN_F8R2_FB18 0x00040000U

#define	CAN_F8R2_FB19 0x00080000U

#define	CAN_F8R2_FB20 0x00100000U

#define	CAN_F8R2_FB21 0x00200000U

#define	CAN_F8R2_FB22 0x00400000U

#define	CAN_F8R2_FB23 0x00800000U

#define	CAN_F8R2_FB24 0x01000000U

#define	CAN_F8R2_FB25 0x02000000U

#define	CAN_F8R2_FB26 0x04000000U

#define	CAN_F8R2_FB27 0x08000000U

#define	CAN_F8R2_FB28 0x10000000U

#define	CAN_F8R2_FB29 0x20000000U

#define	CAN_F8R2_FB30 0x40000000U

#define	CAN_F8R2_FB31 0x80000000U

#define	CAN_F9R2_FB0 0x00000001U

#define	CAN_F9R2_FB1 0x00000002U

#define	CAN_F9R2_FB2 0x00000004U

#define	CAN_F9R2_FB3 0x00000008U

#define	CAN_F9R2_FB4 0x00000010U

#define	CAN_F9R2_FB5 0x00000020U

#define	CAN_F9R2_FB6 0x00000040U

#define	CAN_F9R2_FB7 0x00000080U

#define	CAN_F9R2_FB8 0x00000100U

#define	CAN_F9R2_FB9 0x00000200U

#define	CAN_F9R2_FB10 0x00000400U

#define	CAN_F9R2_FB11 0x00000800U

#define	CAN_F9R2_FB12 0x00001000U

#define	CAN_F9R2_FB13 0x00002000U

#define	CAN_F9R2_FB14 0x00004000U

#define	CAN_F9R2_FB15 0x00008000U

#define	CAN_F9R2_FB16 0x00010000U

#define	CAN_F9R2_FB17 0x00020000U

#define	CAN_F9R2_FB18 0x00040000U

#define	CAN_F9R2_FB19 0x00080000U

#define	CAN_F9R2_FB20 0x00100000U

#define	CAN_F9R2_FB21 0x00200000U

#define	CAN_F9R2_FB22 0x00400000U

#define	CAN_F9R2_FB23 0x00800000U

#define	CAN_F9R2_FB24 0x01000000U

#define	CAN_F9R2_FB25 0x02000000U

#define	CAN_F9R2_FB26 0x04000000U

#define	CAN_F9R2_FB27 0x08000000U

#define	CAN_F9R2_FB28 0x10000000U

#define	CAN_F9R2_FB29 0x20000000U

#define	CAN_F9R2_FB30 0x40000000U

#define	CAN_F9R2_FB31 0x80000000U

#define	CAN_F10R2_FB0 0x00000001U

#define	CAN_F10R2_FB1 0x00000002U

#define	CAN_F10R2_FB2 0x00000004U

#define	CAN_F10R2_FB3 0x00000008U

#define	CAN_F10R2_FB4 0x00000010U

#define	CAN_F10R2_FB5 0x00000020U

#define	CAN_F10R2_FB6 0x00000040U

#define	CAN_F10R2_FB7 0x00000080U

#define	CAN_F10R2_FB8 0x00000100U

#define	CAN_F10R2_FB9 0x00000200U

#define	CAN_F10R2_FB10 0x00000400U

#define	CAN_F10R2_FB11 0x00000800U

#define	CAN_F10R2_FB12 0x00001000U

#define	CAN_F10R2_FB13 0x00002000U

#define	CAN_F10R2_FB14 0x00004000U

#define	CAN_F10R2_FB15 0x00008000U

#define	CAN_F10R2_FB16 0x00010000U

#define	CAN_F10R2_FB17 0x00020000U

#define	CAN_F10R2_FB18 0x00040000U

#define	CAN_F10R2_FB19 0x00080000U

#define	CAN_F10R2_FB20 0x00100000U

#define	CAN_F10R2_FB21 0x00200000U

#define	CAN_F10R2_FB22 0x00400000U

#define	CAN_F10R2_FB23 0x00800000U

#define	CAN_F10R2_FB24 0x01000000U

#define	CAN_F10R2_FB25 0x02000000U

#define	CAN_F10R2_FB26 0x04000000U

#define	CAN_F10R2_FB27 0x08000000U

#define	CAN_F10R2_FB28 0x10000000U

#define	CAN_F10R2_FB29 0x20000000U

#define	CAN_F10R2_FB30 0x40000000U

#define	CAN_F10R2_FB31 0x80000000U

#define	CAN_F11R2_FB0 0x00000001U

#define	CAN_F11R2_FB1 0x00000002U

#define	CAN_F11R2_FB2 0x00000004U

#define	CAN_F11R2_FB3 0x00000008U

#define	CAN_F11R2_FB4 0x00000010U

#define	CAN_F11R2_FB5 0x00000020U

#define	CAN_F11R2_FB6 0x00000040U

#define	CAN_F11R2_FB7 0x00000080U

#define	CAN_F11R2_FB8 0x00000100U

#define	CAN_F11R2_FB9 0x00000200U

#define	CAN_F11R2_FB10 0x00000400U

#define	CAN_F11R2_FB11 0x00000800U

#define	CAN_F11R2_FB12 0x00001000U

#define	CAN_F11R2_FB13 0x00002000U

#define	CAN_F11R2_FB14 0x00004000U

#define	CAN_F11R2_FB15 0x00008000U

#define	CAN_F11R2_FB16 0x00010000U

#define	CAN_F11R2_FB17 0x00020000U

#define	CAN_F11R2_FB18 0x00040000U

#define	CAN_F11R2_FB19 0x00080000U

#define	CAN_F11R2_FB20 0x00100000U

#define	CAN_F11R2_FB21 0x00200000U

#define	CAN_F11R2_FB22 0x00400000U

#define	CAN_F11R2_FB23 0x00800000U

#define	CAN_F11R2_FB24 0x01000000U

#define	CAN_F11R2_FB25 0x02000000U

#define	CAN_F11R2_FB26 0x04000000U

#define	CAN_F11R2_FB27 0x08000000U

#define	CAN_F11R2_FB28 0x10000000U

#define	CAN_F11R2_FB29 0x20000000U

#define	CAN_F11R2_FB30 0x40000000U

#define	CAN_F11R2_FB31 0x80000000U

#define	CAN_F12R2_FB0 0x00000001U

#define	CAN_F12R2_FB1 0x00000002U

#define	CAN_F12R2_FB2 0x00000004U

#define	CAN_F12R2_FB3 0x00000008U

#define	CAN_F12R2_FB4 0x00000010U

#define	CAN_F12R2_FB5 0x00000020U

#define	CAN_F12R2_FB6 0x00000040U

#define	CAN_F12R2_FB7 0x00000080U

#define	CAN_F12R2_FB8 0x00000100U

#define	CAN_F12R2_FB9 0x00000200U

#define	CAN_F12R2_FB10 0x00000400U

#define	CAN_F12R2_FB11 0x00000800U

#define	CAN_F12R2_FB12 0x00001000U

#define	CAN_F12R2_FB13 0x00002000U

#define	CAN_F12R2_FB14 0x00004000U

#define	CAN_F12R2_FB15 0x00008000U

#define	CAN_F12R2_FB16 0x00010000U

#define	CAN_F12R2_FB17 0x00020000U

#define	CAN_F12R2_FB18 0x00040000U

#define	CAN_F12R2_FB19 0x00080000U

#define	CAN_F12R2_FB20 0x00100000U

#define	CAN_F12R2_FB21 0x00200000U

#define	CAN_F12R2_FB22 0x00400000U

#define	CAN_F12R2_FB23 0x00800000U

#define	CAN_F12R2_FB24 0x01000000U

#define	CAN_F12R2_FB25 0x02000000U

#define	CAN_F12R2_FB26 0x04000000U

#define	CAN_F12R2_FB27 0x08000000U

#define	CAN_F12R2_FB28 0x10000000U

#define	CAN_F12R2_FB29 0x20000000U

#define	CAN_F12R2_FB30 0x40000000U

#define	CAN_F12R2_FB31 0x80000000U

#define	CAN_F13R2_FB0 0x00000001U

#define	CAN_F13R2_FB1 0x00000002U

#define	CAN_F13R2_FB2 0x00000004U

#define	CAN_F13R2_FB3 0x00000008U

#define	CAN_F13R2_FB4 0x00000010U

#define	CAN_F13R2_FB5 0x00000020U

#define	CAN_F13R2_FB6 0x00000040U

#define	CAN_F13R2_FB7 0x00000080U

#define	CAN_F13R2_FB8 0x00000100U

#define	CAN_F13R2_FB9 0x00000200U

#define	CAN_F13R2_FB10 0x00000400U

#define	CAN_F13R2_FB11 0x00000800U

#define	CAN_F13R2_FB12 0x00001000U

#define	CAN_F13R2_FB13 0x00002000U

#define	CAN_F13R2_FB14 0x00004000U

#define	CAN_F13R2_FB15 0x00008000U

#define	CAN_F13R2_FB16 0x00010000U

#define	CAN_F13R2_FB17 0x00020000U

#define	CAN_F13R2_FB18 0x00040000U

#define	CAN_F13R2_FB19 0x00080000U

#define	CAN_F13R2_FB20 0x00100000U

#define	CAN_F13R2_FB21 0x00200000U

#define	CAN_F13R2_FB22 0x00400000U

#define	CAN_F13R2_FB23 0x00800000U

#define	CAN_F13R2_FB24 0x01000000U

#define	CAN_F13R2_FB25 0x02000000U

#define	CAN_F13R2_FB26 0x04000000U

#define	CAN_F13R2_FB27 0x08000000U

#define	CAN_F13R2_FB28 0x10000000U

#define	CAN_F13R2_FB29 0x20000000U

#define	CAN_F13R2_FB30 0x40000000U

#define	CAN_F13R2_FB31 0x80000000U

#define	CEC_CR_CECEN 0x00000001U

#define	CEC_CR_TXSOM 0x00000002U

#define	CEC_CR_TXEOM 0x00000004U

#define	CEC_CFGR_SFT 0x00000007U

#define	CEC_CFGR_RXTOL 0x00000008U

#define	CEC_CFGR_BRESTP 0x00000010U

#define	CEC_CFGR_BREGEN 0x00000020U

#define	CEC_CFGR_LBPEGEN 0x00000040U

#define	CEC_CFGR_BRDNOGEN 0x00000080U

#define	CEC_CFGR_SFTOPT 0x00000100U

#define	CEC_CFGR_OAR 0x7FFF0000U

#define	CEC_CFGR_LSTN 0x80000000U

#define	CEC_TXDR_TXD 0x000000FFU

#define	CEC_TXDR_RXD 0x000000FFU

#define	CEC_ISR_RXBR 0x00000001U

#define	CEC_ISR_RXEND 0x00000002U

#define	CEC_ISR_RXOVR 0x00000004U

#define	CEC_ISR_BRE 0x00000008U

#define	CEC_ISR_SBPE 0x00000010U

#define	CEC_ISR_LBPE 0x00000020U

#define	CEC_ISR_RXACKE 0x00000040U

#define	CEC_ISR_ARBLST 0x00000080U

#define	CEC_ISR_TXBR 0x00000100U

#define	CEC_ISR_TXEND 0x00000200U

#define	CEC_ISR_TXUDR 0x00000400U

#define	CEC_ISR_TXERR 0x00000800U

#define	CEC_ISR_TXACKE 0x00001000U

#define	CEC_IER_RXBRIE 0x00000001U

#define	CEC_IER_RXENDIE 0x00000002U

#define	CEC_IER_RXOVRIE 0x00000004U

#define	CEC_IER_BREIE 0x00000008U

#define	CEC_IER_SBPEIE 0x00000010U

#define	CEC_IER_LBPEIE 0x00000020U

#define	CEC_IER_RXACKEIE 0x00000040U

#define	CEC_IER_ARBLSTIE 0x00000080U

#define	CEC_IER_TXBRIE 0x00000100U

#define	CEC_IER_TXENDIE 0x00000200U

#define	CEC_IER_TXUDRIE 0x00000400U

#define	CEC_IER_TXERRIE 0x00000800U

#define	CEC_IER_TXACKEIE 0x00001000U

#define	CRC_DR_DR 0xFFFFFFFFU

#define	CRC_IDR_IDR 0x000000FFU

#define	CRC_CR_RESET 0x00000001U

#define	CRC_CR_POLYSIZE 0x00000018U

#define	CRC_CR_POLYSIZE_0 0x00000008U

#define	CRC_CR_POLYSIZE_1 0x00000010U

#define	CRC_CR_REV_IN 0x00000060U

#define	CRC_CR_REV_IN_0 0x00000020U

#define	CRC_CR_REV_IN_1 0x00000040U

#define	CRC_CR_REV_OUT 0x00000080U

#define	CRC_INIT_INIT 0xFFFFFFFFU

#define	CRC_POL_POL 0xFFFFFFFFU

#define	CRYP_CR_ALGODIR 0x00000004U

#define	CRYP_CR_ALGOMODE 0x00080038U

#define	CRYP_CR_ALGOMODE_0 0x00000008U

#define	CRYP_CR_ALGOMODE_1 0x00000010U

#define	CRYP_CR_ALGOMODE_2 0x00000020U

#define	CRYP_CR_ALGOMODE_TDES_ECB 0x00000000U

#define	CRYP_CR_ALGOMODE_TDES_CBC 0x00000008U

#define	CRYP_CR_ALGOMODE_DES_ECB 0x00000010U

#define	CRYP_CR_ALGOMODE_DES_CBC 0x00000018U

#define	CRYP_CR_ALGOMODE_AES_ECB 0x00000020U

#define	CRYP_CR_ALGOMODE_AES_CBC 0x00000028U

#define	CRYP_CR_ALGOMODE_AES_CTR 0x00000030U

#define	CRYP_CR_ALGOMODE_AES_KEY 0x00000038U

#define	CRYP_CR_DATATYPE 0x000000C0U

#define	CRYP_CR_DATATYPE_0 0x00000040U

#define	CRYP_CR_DATATYPE_1 0x00000080U

#define	CRYP_CR_KEYSIZE 0x00000300U

#define	CRYP_CR_KEYSIZE_0 0x00000100U

#define	CRYP_CR_KEYSIZE_1 0x00000200U

#define	CRYP_CR_FFLUSH 0x00004000U

#define	CRYP_CR_CRYPEN 0x00008000U

#define	CRYP_CR_GCM_CCMPH 0x00030000U

#define	CRYP_CR_GCM_CCMPH_0 0x00010000U

#define	CRYP_CR_GCM_CCMPH_1 0x00020000U

#define	CRYP_CR_ALGOMODE_3 0x00080000U

#define	CRYP_SR_IFEM 0x00000001U

#define	CRYP_SR_IFNF 0x00000002U

#define	CRYP_SR_OFNE 0x00000004U

#define	CRYP_SR_OFFU 0x00000008U

#define	CRYP_SR_BUSY 0x00000010U

#define	CRYP_DMACR_DIEN 0x00000001U

#define	CRYP_DMACR_DOEN 0x00000002U

#define	CRYP_IMSCR_INIM 0x00000001U

#define	CRYP_IMSCR_OUTIM 0x00000002U

#define	CRYP_RISR_OUTRIS 0x00000001U

#define	CRYP_RISR_INRIS 0x00000002U

#define	CRYP_MISR_INMIS 0x00000001U

#define	CRYP_MISR_OUTMIS 0x00000002U

#define	DAC_CR_EN1 0x00000001U

#define	DAC_CR_BOFF1 0x00000002U

#define	DAC_CR_TEN1 0x00000004U

#define	DAC_CR_TSEL1 0x00000038U

#define	DAC_CR_TSEL1_0 0x00000008U

#define	DAC_CR_TSEL1_1 0x00000010U

#define	DAC_CR_TSEL1_2 0x00000020U

#define	DAC_CR_WAVE1 0x000000C0U

#define	DAC_CR_WAVE1_0 0x00000040U

#define	DAC_CR_WAVE1_1 0x00000080U

#define	DAC_CR_MAMP1 0x00000F00U

#define	DAC_CR_MAMP1_0 0x00000100U

#define	DAC_CR_MAMP1_1 0x00000200U

#define	DAC_CR_MAMP1_2 0x00000400U

#define	DAC_CR_MAMP1_3 0x00000800U

#define	DAC_CR_DMAEN1 0x00001000U

#define	DAC_CR_DMAUDRIE1 0x00002000U

#define	DAC_CR_EN2 0x00010000U

#define	DAC_CR_BOFF2 0x00020000U

#define	DAC_CR_TEN2 0x00040000U

#define	DAC_CR_TSEL2 0x00380000U

#define	DAC_CR_TSEL2_0 0x00080000U

#define	DAC_CR_TSEL2_1 0x00100000U

#define	DAC_CR_TSEL2_2 0x00200000U

#define	DAC_CR_WAVE2 0x00C00000U

#define	DAC_CR_WAVE2_0 0x00400000U

#define	DAC_CR_WAVE2_1 0x00800000U

#define	DAC_CR_MAMP2 0x0F000000U

#define	DAC_CR_MAMP2_0 0x01000000U

#define	DAC_CR_MAMP2_1 0x02000000U

#define	DAC_CR_MAMP2_2 0x04000000U

#define	DAC_CR_MAMP2_3 0x08000000U

#define	DAC_CR_DMAEN2 0x10000000U

#define	DAC_CR_DMAUDRIE2 0x20000000U

#define	DAC_SWTRIGR_SWTRIG1 0x01U

#define	DAC_SWTRIGR_SWTRIG2 0x02U

#define	DAC_DHR12R1_DACC1DHR 0x0FFFU

#define	DAC_DHR12L1_DACC1DHR 0xFFF0U

#define	DAC_DHR8R1_DACC1DHR 0xFFU

#define	DAC_DHR12R2_DACC2DHR 0x0FFFU

#define	DAC_DHR12L2_DACC2DHR 0xFFF0U

#define	DAC_DHR8R2_DACC2DHR 0xFFU

#define	DAC_DHR12RD_DACC1DHR 0x00000FFFU

#define	DAC_DHR12RD_DACC2DHR 0x0FFF0000U

#define	DAC_DHR12LD_DACC1DHR 0x0000FFF0U

#define	DAC_DHR12LD_DACC2DHR 0xFFF00000U

#define	DAC_DHR8RD_DACC1DHR 0x00FFU

#define	DAC_DHR8RD_DACC2DHR 0xFF00U

#define	DAC_DOR1_DACC1DOR 0x0FFFU

#define	DAC_DOR2_DACC2DOR 0x0FFFU

#define	DAC_SR_DMAUDR1 0x00002000U

#define	DAC_SR_DMAUDR2 0x20000000U

#define	DCMI_CR_CAPTURE 0x00000001U

#define	DCMI_CR_CM 0x00000002U

#define	DCMI_CR_CROP 0x00000004U

#define	DCMI_CR_JPEG 0x00000008U

#define	DCMI_CR_ESS 0x00000010U

#define	DCMI_CR_PCKPOL 0x00000020U

#define	DCMI_CR_HSPOL 0x00000040U

#define	DCMI_CR_VSPOL 0x00000080U

#define	DCMI_CR_FCRC_0 0x00000100U

#define	DCMI_CR_FCRC_1 0x00000200U

#define	DCMI_CR_EDM_0 0x00000400U

#define	DCMI_CR_EDM_1 0x00000800U

#define	DCMI_CR_CRE 0x00001000U

#define	DCMI_CR_ENABLE 0x00004000U

#define	DCMI_CR_BSM 0x00030000U

#define	DCMI_CR_BSM_0 0x00010000U

#define	DCMI_CR_BSM_1 0x00020000U

#define	DCMI_CR_OEBS 0x00040000U

#define	DCMI_CR_LSM 0x00080000U

#define	DCMI_CR_OELS 0x00100000U

#define	DCMI_SR_HSYNC 0x00000001U

#define	DCMI_SR_VSYNC 0x00000002U

#define	DCMI_SR_FNE 0x00000004U

#define	DCMI_RIS_FRAME_RIS 0x00000001U

#define	DCMI_RIS_OVR_RIS 0x00000002U

#define	DCMI_RIS_ERR_RIS 0x00000004U

#define	DCMI_RIS_VSYNC_RIS 0x00000008U

#define	DCMI_RIS_LINE_RIS 0x00000010U

#define	DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS

#define	DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS

#define	DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS

#define	DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS

#define	DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS

#define	DCMI_IER_FRAME_IE 0x00000001U

#define	DCMI_IER_OVR_IE 0x00000002U

#define	DCMI_IER_ERR_IE 0x00000004U

#define	DCMI_IER_VSYNC_IE 0x00000008U

#define	DCMI_IER_LINE_IE 0x00000010U

#define	DCMI_IER_OVF_IE DCMI_IER_OVR_IE

#define	DCMI_MIS_FRAME_MIS 0x00000001U

#define	DCMI_MIS_OVR_MIS 0x00000002U

#define	DCMI_MIS_ERR_MIS 0x00000004U

#define	DCMI_MIS_VSYNC_MIS 0x00000008U

#define	DCMI_MIS_LINE_MIS 0x00000010U

#define	DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS

#define	DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS

#define	DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS

#define	DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS

#define	DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS

#define	DCMI_ICR_FRAME_ISC 0x00000001U

#define	DCMI_ICR_OVR_ISC 0x00000002U

#define	DCMI_ICR_ERR_ISC 0x00000004U

#define	DCMI_ICR_VSYNC_ISC 0x00000008U

#define	DCMI_ICR_LINE_ISC 0x00000010U

#define	DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC

#define	DCMI_ESCR_FSC 0x000000FFU

#define	DCMI_ESCR_LSC 0x0000FF00U

#define	DCMI_ESCR_LEC 0x00FF0000U

#define	DCMI_ESCR_FEC 0xFF000000U

#define	DCMI_ESUR_FSU 0x000000FFU

#define	DCMI_ESUR_LSU 0x0000FF00U

#define	DCMI_ESUR_LEU 0x00FF0000U

#define	DCMI_ESUR_FEU 0xFF000000U

#define	DCMI_CWSTRT_HOFFCNT 0x00003FFFU

#define	DCMI_CWSTRT_VST 0x1FFF0000U

#define	DCMI_CWSIZE_CAPCNT 0x00003FFFU

#define	DCMI_CWSIZE_VLINE 0x3FFF0000U

#define	DCMI_DR_BYTE0 0x000000FFU

#define	DCMI_DR_BYTE1 0x0000FF00U

#define	DCMI_DR_BYTE2 0x00FF0000U

#define	DCMI_DR_BYTE3 0xFF000000U

#define	DMA_SxCR_CHSEL 0x0E000000U

#define	DMA_SxCR_CHSEL_0 0x02000000U

#define	DMA_SxCR_CHSEL_1 0x04000000U

#define	DMA_SxCR_CHSEL_2 0x08000000U

#define	DMA_SxCR_MBURST 0x01800000U

#define	DMA_SxCR_MBURST_0 0x00800000U

#define	DMA_SxCR_MBURST_1 0x01000000U

#define	DMA_SxCR_PBURST 0x00600000U

#define	DMA_SxCR_PBURST_0 0x00200000U

#define	DMA_SxCR_PBURST_1 0x00400000U

#define	DMA_SxCR_CT 0x00080000U

#define	DMA_SxCR_DBM 0x00040000U

#define	DMA_SxCR_PL 0x00030000U

#define	DMA_SxCR_PL_0 0x00010000U

#define	DMA_SxCR_PL_1 0x00020000U

#define	DMA_SxCR_PINCOS 0x00008000U

#define	DMA_SxCR_MSIZE 0x00006000U

#define	DMA_SxCR_MSIZE_0 0x00002000U

#define	DMA_SxCR_MSIZE_1 0x00004000U

#define	DMA_SxCR_PSIZE 0x00001800U

#define	DMA_SxCR_PSIZE_0 0x00000800U

#define	DMA_SxCR_PSIZE_1 0x00001000U

#define	DMA_SxCR_MINC 0x00000400U

#define	DMA_SxCR_PINC 0x00000200U

#define	DMA_SxCR_CIRC 0x00000100U

#define	DMA_SxCR_DIR 0x000000C0U

#define	DMA_SxCR_DIR_0 0x00000040U

#define	DMA_SxCR_DIR_1 0x00000080U

#define	DMA_SxCR_PFCTRL 0x00000020U

#define	DMA_SxCR_TCIE 0x00000010U

#define	DMA_SxCR_HTIE 0x00000008U

#define	DMA_SxCR_TEIE 0x00000004U

#define	DMA_SxCR_DMEIE 0x00000002U

#define	DMA_SxCR_EN 0x00000001U

#define	DMA_SxNDT 0x0000FFFFU

#define	DMA_SxNDT_0 0x00000001U

#define	DMA_SxNDT_1 0x00000002U

#define	DMA_SxNDT_2 0x00000004U

#define	DMA_SxNDT_3 0x00000008U

#define	DMA_SxNDT_4 0x00000010U

#define	DMA_SxNDT_5 0x00000020U

#define	DMA_SxNDT_6 0x00000040U

#define	DMA_SxNDT_7 0x00000080U

#define	DMA_SxNDT_8 0x00000100U

#define	DMA_SxNDT_9 0x00000200U

#define	DMA_SxNDT_10 0x00000400U

#define	DMA_SxNDT_11 0x00000800U

#define	DMA_SxNDT_12 0x00001000U

#define	DMA_SxNDT_13 0x00002000U

#define	DMA_SxNDT_14 0x00004000U

#define	DMA_SxNDT_15 0x00008000U

#define	DMA_SxFCR_FEIE 0x00000080U

#define	DMA_SxFCR_FS 0x00000038U

#define	DMA_SxFCR_FS_0 0x00000008U

#define	DMA_SxFCR_FS_1 0x00000010U

#define	DMA_SxFCR_FS_2 0x00000020U

#define	DMA_SxFCR_DMDIS 0x00000004U

#define	DMA_SxFCR_FTH 0x00000003U

#define	DMA_SxFCR_FTH_0 0x00000001U

#define	DMA_SxFCR_FTH_1 0x00000002U

#define	DMA_LISR_TCIF3 0x08000000U

#define	DMA_LISR_HTIF3 0x04000000U

#define	DMA_LISR_TEIF3 0x02000000U

#define	DMA_LISR_DMEIF3 0x01000000U

#define	DMA_LISR_FEIF3 0x00400000U

#define	DMA_LISR_TCIF2 0x00200000U

#define	DMA_LISR_HTIF2 0x00100000U

#define	DMA_LISR_TEIF2 0x00080000U

#define	DMA_LISR_DMEIF2 0x00040000U

#define	DMA_LISR_FEIF2 0x00010000U

#define	DMA_LISR_TCIF1 0x00000800U

#define	DMA_LISR_HTIF1 0x00000400U

#define	DMA_LISR_TEIF1 0x00000200U

#define	DMA_LISR_DMEIF1 0x00000100U

#define	DMA_LISR_FEIF1 0x00000040U

#define	DMA_LISR_TCIF0 0x00000020U

#define	DMA_LISR_HTIF0 0x00000010U

#define	DMA_LISR_TEIF0 0x00000008U

#define	DMA_LISR_DMEIF0 0x00000004U

#define	DMA_LISR_FEIF0 0x00000001U

#define	DMA_HISR_TCIF7 0x08000000U

#define	DMA_HISR_HTIF7 0x04000000U

#define	DMA_HISR_TEIF7 0x02000000U

#define	DMA_HISR_DMEIF7 0x01000000U

#define	DMA_HISR_FEIF7 0x00400000U

#define	DMA_HISR_TCIF6 0x00200000U

#define	DMA_HISR_HTIF6 0x00100000U

#define	DMA_HISR_TEIF6 0x00080000U

#define	DMA_HISR_DMEIF6 0x00040000U

#define	DMA_HISR_FEIF6 0x00010000U

#define	DMA_HISR_TCIF5 0x00000800U

#define	DMA_HISR_HTIF5 0x00000400U

#define	DMA_HISR_TEIF5 0x00000200U

#define	DMA_HISR_DMEIF5 0x00000100U

#define	DMA_HISR_FEIF5 0x00000040U

#define	DMA_HISR_TCIF4 0x00000020U

#define	DMA_HISR_HTIF4 0x00000010U

#define	DMA_HISR_TEIF4 0x00000008U

#define	DMA_HISR_DMEIF4 0x00000004U

#define	DMA_HISR_FEIF4 0x00000001U

#define	DMA_LIFCR_CTCIF3 0x08000000U

#define	DMA_LIFCR_CHTIF3 0x04000000U

#define	DMA_LIFCR_CTEIF3 0x02000000U

#define	DMA_LIFCR_CDMEIF3 0x01000000U

#define	DMA_LIFCR_CFEIF3 0x00400000U

#define	DMA_LIFCR_CTCIF2 0x00200000U

#define	DMA_LIFCR_CHTIF2 0x00100000U

#define	DMA_LIFCR_CTEIF2 0x00080000U

#define	DMA_LIFCR_CDMEIF2 0x00040000U

#define	DMA_LIFCR_CFEIF2 0x00010000U

#define	DMA_LIFCR_CTCIF1 0x00000800U

#define	DMA_LIFCR_CHTIF1 0x00000400U

#define	DMA_LIFCR_CTEIF1 0x00000200U

#define	DMA_LIFCR_CDMEIF1 0x00000100U

#define	DMA_LIFCR_CFEIF1 0x00000040U

#define	DMA_LIFCR_CTCIF0 0x00000020U

#define	DMA_LIFCR_CHTIF0 0x00000010U

#define	DMA_LIFCR_CTEIF0 0x00000008U

#define	DMA_LIFCR_CDMEIF0 0x00000004U

#define	DMA_LIFCR_CFEIF0 0x00000001U

#define	DMA_HIFCR_CTCIF7 0x08000000U

#define	DMA_HIFCR_CHTIF7 0x04000000U

#define	DMA_HIFCR_CTEIF7 0x02000000U

#define	DMA_HIFCR_CDMEIF7 0x01000000U

#define	DMA_HIFCR_CFEIF7 0x00400000U

#define	DMA_HIFCR_CTCIF6 0x00200000U

#define	DMA_HIFCR_CHTIF6 0x00100000U

#define	DMA_HIFCR_CTEIF6 0x00080000U

#define	DMA_HIFCR_CDMEIF6 0x00040000U

#define	DMA_HIFCR_CFEIF6 0x00010000U

#define	DMA_HIFCR_CTCIF5 0x00000800U

#define	DMA_HIFCR_CHTIF5 0x00000400U

#define	DMA_HIFCR_CTEIF5 0x00000200U

#define	DMA_HIFCR_CDMEIF5 0x00000100U

#define	DMA_HIFCR_CFEIF5 0x00000040U

#define	DMA_HIFCR_CTCIF4 0x00000020U

#define	DMA_HIFCR_CHTIF4 0x00000010U

#define	DMA_HIFCR_CTEIF4 0x00000008U

#define	DMA_HIFCR_CDMEIF4 0x00000004U

#define	DMA_HIFCR_CFEIF4 0x00000001U

#define	DMA2D_CR_START 0x00000001U

#define	DMA2D_CR_SUSP 0x00000002U

#define	DMA2D_CR_ABORT 0x00000004U

#define	DMA2D_CR_TEIE 0x00000100U

#define	DMA2D_CR_TCIE 0x00000200U

#define	DMA2D_CR_TWIE 0x00000400U

#define	DMA2D_CR_CAEIE 0x00000800U

#define	DMA2D_CR_CTCIE 0x00001000U

#define	DMA2D_CR_CEIE 0x00002000U

#define	DMA2D_CR_MODE 0x00030000U

#define	DMA2D_CR_MODE_0 0x00010000U

#define	DMA2D_CR_MODE_1 0x00020000U

#define	DMA2D_ISR_TEIF 0x00000001U

#define	DMA2D_ISR_TCIF 0x00000002U

#define	DMA2D_ISR_TWIF 0x00000004U

#define	DMA2D_ISR_CAEIF 0x00000008U

#define	DMA2D_ISR_CTCIF 0x00000010U

#define	DMA2D_ISR_CEIF 0x00000020U

#define	DMA2D_IFCR_CTEIF 0x00000001U

#define	DMA2D_IFCR_CTCIF 0x00000002U

#define	DMA2D_IFCR_CTWIF 0x00000004U

#define	DMA2D_IFCR_CAECIF 0x00000008U

#define	DMA2D_IFCR_CCTCIF 0x00000010U

#define	DMA2D_IFCR_CCEIF 0x00000020U

#define	DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF

#define	DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF

#define	DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF

#define	DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF

#define	DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF

#define	DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF

#define	DMA2D_FGMAR_MA 0xFFFFFFFFU

#define	DMA2D_FGOR_LO 0x00003FFFU

#define	DMA2D_BGMAR_MA 0xFFFFFFFFU

#define	DMA2D_BGOR_LO 0x00003FFFU

#define	DMA2D_FGPFCCR_CM 0x0000000FU

#define	DMA2D_FGPFCCR_CM_0 0x00000001U

#define	DMA2D_FGPFCCR_CM_1 0x00000002U

#define	DMA2D_FGPFCCR_CM_2 0x00000004U

#define	DMA2D_FGPFCCR_CM_3 0x00000008U

#define	DMA2D_FGPFCCR_CCM 0x00000010U

#define	DMA2D_FGPFCCR_START 0x00000020U

#define	DMA2D_FGPFCCR_CS 0x0000FF00U

#define	DMA2D_FGPFCCR_AM 0x00030000U

#define	DMA2D_FGPFCCR_AM_0 0x00010000U

#define	DMA2D_FGPFCCR_AM_1 0x00020000U

#define	DMA2D_FGPFCCR_ALPHA 0xFF000000U

#define	DMA2D_FGCOLR_BLUE 0x000000FFU

#define	DMA2D_FGCOLR_GREEN 0x0000FF00U

#define	DMA2D_FGCOLR_RED 0x00FF0000U

#define	DMA2D_BGPFCCR_CM 0x0000000FU

#define	DMA2D_BGPFCCR_CM_0 0x00000001U

#define	DMA2D_BGPFCCR_CM_1 0x00000002U

#define	DMA2D_BGPFCCR_CM_2 0x00000004U

#define	DMA2D_FGPFCCR_CM_3 0x00000008U

#define	DMA2D_BGPFCCR_CCM 0x00000010U

#define	DMA2D_BGPFCCR_START 0x00000020U

#define	DMA2D_BGPFCCR_CS 0x0000FF00U

#define	DMA2D_BGPFCCR_AM 0x00030000U

#define	DMA2D_BGPFCCR_AM_0 0x00010000U

#define	DMA2D_BGPFCCR_AM_1 0x00020000U

#define	DMA2D_BGPFCCR_ALPHA 0xFF000000U

#define	DMA2D_BGCOLR_BLUE 0x000000FFU

#define	DMA2D_BGCOLR_GREEN 0x0000FF00U

#define	DMA2D_BGCOLR_RED 0x00FF0000U

#define	DMA2D_FGCMAR_MA 0xFFFFFFFFU

#define	DMA2D_BGCMAR_MA 0xFFFFFFFFU

#define	DMA2D_OPFCCR_CM 0x00000007U

#define	DMA2D_OPFCCR_CM_0 0x00000001U

#define	DMA2D_OPFCCR_CM_1 0x00000002U

#define	DMA2D_OPFCCR_CM_2 0x00000004U

#define	DMA2D_OCOLR_BLUE_1 0x000000FFU

#define	DMA2D_OCOLR_GREEN_1 0x0000FF00U

#define	DMA2D_OCOLR_RED_1 0x00FF0000U

#define	DMA2D_OCOLR_ALPHA_1 0xFF000000U

#define	DMA2D_OCOLR_BLUE_2 0x0000001FU

#define	DMA2D_OCOLR_GREEN_2 0x000007E0U

#define	DMA2D_OCOLR_RED_2 0x0000F800U

#define	DMA2D_OCOLR_BLUE_3 0x0000001FU

#define	DMA2D_OCOLR_GREEN_3 0x000003E0U

#define	DMA2D_OCOLR_RED_3 0x00007C00U

#define	DMA2D_OCOLR_ALPHA_3 0x00008000U

#define	DMA2D_OCOLR_BLUE_4 0x0000000FU

#define	DMA2D_OCOLR_GREEN_4 0x000000F0U

#define	DMA2D_OCOLR_RED_4 0x00000F00U

#define	DMA2D_OCOLR_ALPHA_4 0x0000F000U

#define	DMA2D_OMAR_MA 0xFFFFFFFFU

#define	DMA2D_OOR_LO 0x00003FFFU

#define	DMA2D_NLR_NL 0x0000FFFFU

#define	DMA2D_NLR_PL 0x3FFF0000U

#define	DMA2D_LWR_LW 0x0000FFFFU

#define	DMA2D_AMTCR_EN 0x00000001U

#define	DMA2D_AMTCR_DT 0x0000FF00U

#define	EXTI_IMR_MR0 0x00000001U

#define	EXTI_IMR_MR1 0x00000002U

#define	EXTI_IMR_MR2 0x00000004U

#define	EXTI_IMR_MR3 0x00000008U

#define	EXTI_IMR_MR4 0x00000010U

#define	EXTI_IMR_MR5 0x00000020U

#define	EXTI_IMR_MR6 0x00000040U

#define	EXTI_IMR_MR7 0x00000080U

#define	EXTI_IMR_MR8 0x00000100U

#define	EXTI_IMR_MR9 0x00000200U

#define	EXTI_IMR_MR10 0x00000400U

#define	EXTI_IMR_MR11 0x00000800U

#define	EXTI_IMR_MR12 0x00001000U

#define	EXTI_IMR_MR13 0x00002000U

#define	EXTI_IMR_MR14 0x00004000U

#define	EXTI_IMR_MR15 0x00008000U

#define	EXTI_IMR_MR16 0x00010000U

#define	EXTI_IMR_MR17 0x00020000U

#define	EXTI_IMR_MR18 0x00040000U

#define	EXTI_IMR_MR19 0x00080000U

#define	EXTI_IMR_MR20 0x00100000U

#define	EXTI_IMR_MR21 0x00200000U

#define	EXTI_IMR_MR22 0x00400000U

#define	EXTI_IMR_MR23 0x00800000U

#define	EXTI_IMR_IM0 EXTI_IMR_MR0

#define	EXTI_IMR_IM1 EXTI_IMR_MR1

#define	EXTI_IMR_IM2 EXTI_IMR_MR2

#define	EXTI_IMR_IM3 EXTI_IMR_MR3

#define	EXTI_IMR_IM4 EXTI_IMR_MR4

#define	EXTI_IMR_IM5 EXTI_IMR_MR5

#define	EXTI_IMR_IM6 EXTI_IMR_MR6

#define	EXTI_IMR_IM7 EXTI_IMR_MR7

#define	EXTI_IMR_IM8 EXTI_IMR_MR8

#define	EXTI_IMR_IM9 EXTI_IMR_MR9

#define	EXTI_IMR_IM10 EXTI_IMR_MR10

#define	EXTI_IMR_IM11 EXTI_IMR_MR11

#define	EXTI_IMR_IM12 EXTI_IMR_MR12

#define	EXTI_IMR_IM13 EXTI_IMR_MR13

#define	EXTI_IMR_IM14 EXTI_IMR_MR14

#define	EXTI_IMR_IM15 EXTI_IMR_MR15

#define	EXTI_IMR_IM16 EXTI_IMR_MR16

#define	EXTI_IMR_IM17 EXTI_IMR_MR17

#define	EXTI_IMR_IM18 EXTI_IMR_MR18

#define	EXTI_IMR_IM19 EXTI_IMR_MR19

#define	EXTI_IMR_IM20 EXTI_IMR_MR20

#define	EXTI_IMR_IM21 EXTI_IMR_MR21

#define	EXTI_IMR_IM22 EXTI_IMR_MR22

#define	EXTI_IMR_IM23 EXTI_IMR_MR23

#define	EXTI_IMR_IM 0x00FFFFFFU

#define	EXTI_EMR_MR0 0x00000001U

#define	EXTI_EMR_MR1 0x00000002U

#define	EXTI_EMR_MR2 0x00000004U

#define	EXTI_EMR_MR3 0x00000008U

#define	EXTI_EMR_MR4 0x00000010U

#define	EXTI_EMR_MR5 0x00000020U

#define	EXTI_EMR_MR6 0x00000040U

#define	EXTI_EMR_MR7 0x00000080U

#define	EXTI_EMR_MR8 0x00000100U

#define	EXTI_EMR_MR9 0x00000200U

#define	EXTI_EMR_MR10 0x00000400U

#define	EXTI_EMR_MR11 0x00000800U

#define	EXTI_EMR_MR12 0x00001000U

#define	EXTI_EMR_MR13 0x00002000U

#define	EXTI_EMR_MR14 0x00004000U

#define	EXTI_EMR_MR15 0x00008000U

#define	EXTI_EMR_MR16 0x00010000U

#define	EXTI_EMR_MR17 0x00020000U

#define	EXTI_EMR_MR18 0x00040000U

#define	EXTI_EMR_MR19 0x00080000U

#define	EXTI_EMR_MR20 0x00100000U

#define	EXTI_EMR_MR21 0x00200000U

#define	EXTI_EMR_MR22 0x00400000U

#define	EXTI_EMR_MR23 0x00800000U

#define	EXTI_EMR_EM0 EXTI_EMR_MR0

#define	EXTI_EMR_EM1 EXTI_EMR_MR1

#define	EXTI_EMR_EM2 EXTI_EMR_MR2

#define	EXTI_EMR_EM3 EXTI_EMR_MR3

#define	EXTI_EMR_EM4 EXTI_EMR_MR4

#define	EXTI_EMR_EM5 EXTI_EMR_MR5

#define	EXTI_EMR_EM6 EXTI_EMR_MR6

#define	EXTI_EMR_EM7 EXTI_EMR_MR7

#define	EXTI_EMR_EM8 EXTI_EMR_MR8

#define	EXTI_EMR_EM9 EXTI_EMR_MR9

#define	EXTI_EMR_EM10 EXTI_EMR_MR10

#define	EXTI_EMR_EM11 EXTI_EMR_MR11

#define	EXTI_EMR_EM12 EXTI_EMR_MR12

#define	EXTI_EMR_EM13 EXTI_EMR_MR13

#define	EXTI_EMR_EM14 EXTI_EMR_MR14

#define	EXTI_EMR_EM15 EXTI_EMR_MR15

#define	EXTI_EMR_EM16 EXTI_EMR_MR16

#define	EXTI_EMR_EM17 EXTI_EMR_MR17

#define	EXTI_EMR_EM18 EXTI_EMR_MR18

#define	EXTI_EMR_EM19 EXTI_EMR_MR19

#define	EXTI_EMR_EM20 EXTI_EMR_MR20

#define	EXTI_EMR_EM21 EXTI_EMR_MR21

#define	EXTI_EMR_EM22 EXTI_EMR_MR22

#define	EXTI_EMR_EM23 EXTI_EMR_MR23

#define	EXTI_RTSR_TR0 0x00000001U

#define	EXTI_RTSR_TR1 0x00000002U

#define	EXTI_RTSR_TR2 0x00000004U

#define	EXTI_RTSR_TR3 0x00000008U

#define	EXTI_RTSR_TR4 0x00000010U

#define	EXTI_RTSR_TR5 0x00000020U

#define	EXTI_RTSR_TR6 0x00000040U

#define	EXTI_RTSR_TR7 0x00000080U

#define	EXTI_RTSR_TR8 0x00000100U

#define	EXTI_RTSR_TR9 0x00000200U

#define	EXTI_RTSR_TR10 0x00000400U

#define	EXTI_RTSR_TR11 0x00000800U

#define	EXTI_RTSR_TR12 0x00001000U

#define	EXTI_RTSR_TR13 0x00002000U

#define	EXTI_RTSR_TR14 0x00004000U

#define	EXTI_RTSR_TR15 0x00008000U

#define	EXTI_RTSR_TR16 0x00010000U

#define	EXTI_RTSR_TR17 0x00020000U

#define	EXTI_RTSR_TR18 0x00040000U

#define	EXTI_RTSR_TR19 0x00080000U

#define	EXTI_RTSR_TR20 0x00100000U

#define	EXTI_RTSR_TR21 0x00200000U

#define	EXTI_RTSR_TR22 0x00400000U

#define	EXTI_RTSR_TR23 0x00800000U

#define	EXTI_FTSR_TR0 0x00000001U

#define	EXTI_FTSR_TR1 0x00000002U

#define	EXTI_FTSR_TR2 0x00000004U

#define	EXTI_FTSR_TR3 0x00000008U

#define	EXTI_FTSR_TR4 0x00000010U

#define	EXTI_FTSR_TR5 0x00000020U

#define	EXTI_FTSR_TR6 0x00000040U

#define	EXTI_FTSR_TR7 0x00000080U

#define	EXTI_FTSR_TR8 0x00000100U

#define	EXTI_FTSR_TR9 0x00000200U

#define	EXTI_FTSR_TR10 0x00000400U

#define	EXTI_FTSR_TR11 0x00000800U

#define	EXTI_FTSR_TR12 0x00001000U

#define	EXTI_FTSR_TR13 0x00002000U

#define	EXTI_FTSR_TR14 0x00004000U

#define	EXTI_FTSR_TR15 0x00008000U

#define	EXTI_FTSR_TR16 0x00010000U

#define	EXTI_FTSR_TR17 0x00020000U

#define	EXTI_FTSR_TR18 0x00040000U

#define	EXTI_FTSR_TR19 0x00080000U

#define	EXTI_FTSR_TR20 0x00100000U

#define	EXTI_FTSR_TR21 0x00200000U

#define	EXTI_FTSR_TR22 0x00400000U

#define	EXTI_FTSR_TR23 0x00800000U

#define	EXTI_SWIER_SWIER0 0x00000001U

#define	EXTI_SWIER_SWIER1 0x00000002U

#define	EXTI_SWIER_SWIER2 0x00000004U

#define	EXTI_SWIER_SWIER3 0x00000008U

#define	EXTI_SWIER_SWIER4 0x00000010U

#define	EXTI_SWIER_SWIER5 0x00000020U

#define	EXTI_SWIER_SWIER6 0x00000040U

#define	EXTI_SWIER_SWIER7 0x00000080U

#define	EXTI_SWIER_SWIER8 0x00000100U

#define	EXTI_SWIER_SWIER9 0x00000200U

#define	EXTI_SWIER_SWIER10 0x00000400U

#define	EXTI_SWIER_SWIER11 0x00000800U

#define	EXTI_SWIER_SWIER12 0x00001000U

#define	EXTI_SWIER_SWIER13 0x00002000U

#define	EXTI_SWIER_SWIER14 0x00004000U

#define	EXTI_SWIER_SWIER15 0x00008000U

#define	EXTI_SWIER_SWIER16 0x00010000U

#define	EXTI_SWIER_SWIER17 0x00020000U

#define	EXTI_SWIER_SWIER18 0x00040000U

#define	EXTI_SWIER_SWIER19 0x00080000U

#define	EXTI_SWIER_SWIER20 0x00100000U

#define	EXTI_SWIER_SWIER21 0x00200000U

#define	EXTI_SWIER_SWIER22 0x00400000U

#define	EXTI_SWIER_SWIER23 0x00800000U

#define	EXTI_PR_PR0 0x00000001U

#define	EXTI_PR_PR1 0x00000002U

#define	EXTI_PR_PR2 0x00000004U

#define	EXTI_PR_PR3 0x00000008U

#define	EXTI_PR_PR4 0x00000010U

#define	EXTI_PR_PR5 0x00000020U

#define	EXTI_PR_PR6 0x00000040U

#define	EXTI_PR_PR7 0x00000080U

#define	EXTI_PR_PR8 0x00000100U

#define	EXTI_PR_PR9 0x00000200U

#define	EXTI_PR_PR10 0x00000400U

#define	EXTI_PR_PR11 0x00000800U

#define	EXTI_PR_PR12 0x00001000U

#define	EXTI_PR_PR13 0x00002000U

#define	EXTI_PR_PR14 0x00004000U

#define	EXTI_PR_PR15 0x00008000U

#define	EXTI_PR_PR16 0x00010000U

#define	EXTI_PR_PR17 0x00020000U

#define	EXTI_PR_PR18 0x00040000U

#define	EXTI_PR_PR19 0x00080000U

#define	EXTI_PR_PR20 0x00100000U

#define	EXTI_PR_PR21 0x00200000U

#define	EXTI_PR_PR22 0x00400000U

#define	EXTI_PR_PR23 0x00800000U

#define	FLASH_SECTOR_TOTAL 8

#define	FLASH_ACR_LATENCY 0x0000000FU

#define	FLASH_ACR_LATENCY_0WS 0x00000000U

#define	FLASH_ACR_LATENCY_1WS 0x00000001U

#define	FLASH_ACR_LATENCY_2WS 0x00000002U

#define	FLASH_ACR_LATENCY_3WS 0x00000003U

#define	FLASH_ACR_LATENCY_4WS 0x00000004U

#define	FLASH_ACR_LATENCY_5WS 0x00000005U

#define	FLASH_ACR_LATENCY_6WS 0x00000006U

#define	FLASH_ACR_LATENCY_7WS 0x00000007U

#define	FLASH_ACR_LATENCY_8WS 0x00000008U

#define	FLASH_ACR_LATENCY_9WS 0x00000009U

#define	FLASH_ACR_LATENCY_10WS 0x0000000AU

#define	FLASH_ACR_LATENCY_11WS 0x0000000BU

#define	FLASH_ACR_LATENCY_12WS 0x0000000CU

#define	FLASH_ACR_LATENCY_13WS 0x0000000DU

#define	FLASH_ACR_LATENCY_14WS 0x0000000EU

#define	FLASH_ACR_LATENCY_15WS 0x0000000FU

#define	FLASH_ACR_PRFTEN 0x00000100U

#define	FLASH_ACR_ARTEN 0x00000200U

#define	FLASH_ACR_ARTRST 0x00000800U

#define	FLASH_SR_EOP 0x00000001U

#define	FLASH_SR_OPERR 0x00000002U

#define	FLASH_SR_WRPERR 0x00000010U

#define	FLASH_SR_PGAERR 0x00000020U

#define	FLASH_SR_PGPERR 0x00000040U

#define	FLASH_SR_ERSERR 0x00000080U

#define	FLASH_SR_BSY 0x00010000U

#define	FLASH_CR_PG 0x00000001U

#define	FLASH_CR_SER 0x00000002U

#define	FLASH_CR_MER 0x00000004U

#define	FLASH_CR_SNB 0x00000078U

#define	FLASH_CR_SNB_0 0x00000008U

#define	FLASH_CR_SNB_1 0x00000010U

#define	FLASH_CR_SNB_2 0x00000020U

#define	FLASH_CR_SNB_3 0x00000040U

#define	FLASH_CR_PSIZE 0x00000300U

#define	FLASH_CR_PSIZE_0 0x00000100U

#define	FLASH_CR_PSIZE_1 0x00000200U

#define	FLASH_CR_STRT 0x00010000U

#define	FLASH_CR_EOPIE 0x01000000U

#define	FLASH_CR_ERRIE 0x02000000U

#define	FLASH_CR_LOCK 0x80000000U

#define	FLASH_OPTCR_OPTLOCK 0x00000001U

#define	FLASH_OPTCR_OPTSTRT 0x00000002U

#define	FLASH_OPTCR_BOR_LEV 0x0000000CU

#define	FLASH_OPTCR_BOR_LEV_0 0x00000004U

#define	FLASH_OPTCR_BOR_LEV_1 0x00000008U

#define	FLASH_OPTCR_WWDG_SW 0x00000010U

#define	FLASH_OPTCR_IWDG_SW 0x00000020U

#define	FLASH_OPTCR_nRST_STOP 0x00000040U

#define	FLASH_OPTCR_nRST_STDBY 0x00000080U

#define	FLASH_OPTCR_RDP 0x0000FF00U

#define	FLASH_OPTCR_RDP_0 0x00000100U

#define	FLASH_OPTCR_RDP_1 0x00000200U

#define	FLASH_OPTCR_RDP_2 0x00000400U

#define	FLASH_OPTCR_RDP_3 0x00000800U

#define	FLASH_OPTCR_RDP_4 0x00001000U

#define	FLASH_OPTCR_RDP_5 0x00002000U

#define	FLASH_OPTCR_RDP_6 0x00004000U

#define	FLASH_OPTCR_RDP_7 0x00008000U

#define	FLASH_OPTCR_nWRP 0x00FF0000U

#define	FLASH_OPTCR_nWRP_0 0x00010000U

#define	FLASH_OPTCR_nWRP_1 0x00020000U

#define	FLASH_OPTCR_nWRP_2 0x00040000U

#define	FLASH_OPTCR_nWRP_3 0x00080000U

#define	FLASH_OPTCR_nWRP_4 0x00100000U

#define	FLASH_OPTCR_nWRP_5 0x00200000U

#define	FLASH_OPTCR_nWRP_6 0x00400000U

#define	FLASH_OPTCR_nWRP_7 0x00800000U

#define	FLASH_OPTCR_IWDG_STDBY 0x40000000U

#define	FLASH_OPTCR_IWDG_STOP 0x80000000U

#define	FLASH_OPTCR1_BOOT_ADD0 0x0000FFFFU

#define	FLASH_OPTCR1_BOOT_ADD1 0xFFFF0000U

#define	FMC_BCR1_MBKEN 0x00000001U

#define	FMC_BCR1_MUXEN 0x00000002U

#define	FMC_BCR1_MTYP 0x0000000CU

#define	FMC_BCR1_MTYP_0 0x00000004U

#define	FMC_BCR1_MTYP_1 0x00000008U

#define	FMC_BCR1_MWID 0x00000030U

#define	FMC_BCR1_MWID_0 0x00000010U

#define	FMC_BCR1_MWID_1 0x00000020U

#define	FMC_BCR1_FACCEN 0x00000040U

#define	FMC_BCR1_BURSTEN 0x00000100U

#define	FMC_BCR1_WAITPOL 0x00000200U

#define	FMC_BCR1_WRAPMOD 0x00000400U

#define	FMC_BCR1_WAITCFG 0x00000800U

#define	FMC_BCR1_WREN 0x00001000U

#define	FMC_BCR1_WAITEN 0x00002000U

#define	FMC_BCR1_EXTMOD 0x00004000U

#define	FMC_BCR1_ASYNCWAIT 0x00008000U

#define	FMC_BCR1_CPSIZE 0x00070000U

#define	FMC_BCR1_CPSIZE_0 0x00010000U

#define	FMC_BCR1_CPSIZE_1 0x00020000U

#define	FMC_BCR1_CPSIZE_2 0x00040000U

#define	FMC_BCR1_CBURSTRW 0x00080000U

#define	FMC_BCR1_CCLKEN 0x00100000U

#define	FMC_BCR1_WFDIS 0x00200000U

#define	FMC_BCR2_MBKEN 0x00000001U

#define	FMC_BCR2_MUXEN 0x00000002U

#define	FMC_BCR2_MTYP 0x0000000CU

#define	FMC_BCR2_MTYP_0 0x00000004U

#define	FMC_BCR2_MTYP_1 0x00000008U

#define	FMC_BCR2_MWID 0x00000030U

#define	FMC_BCR2_MWID_0 0x00000010U

#define	FMC_BCR2_MWID_1 0x00000020U

#define	FMC_BCR2_FACCEN 0x00000040U

#define	FMC_BCR2_BURSTEN 0x00000100U

#define	FMC_BCR2_WAITPOL 0x00000200U

#define	FMC_BCR2_WRAPMOD 0x00000400U

#define	FMC_BCR2_WAITCFG 0x00000800U

#define	FMC_BCR2_WREN 0x00001000U

#define	FMC_BCR2_WAITEN 0x00002000U

#define	FMC_BCR2_EXTMOD 0x00004000U

#define	FMC_BCR2_ASYNCWAIT 0x00008000U

#define	FMC_BCR2_CPSIZE 0x00070000U

#define	FMC_BCR2_CPSIZE_0 0x00010000U

#define	FMC_BCR2_CPSIZE_1 0x00020000U

#define	FMC_BCR2_CPSIZE_2 0x00040000U

#define	FMC_BCR2_CBURSTRW 0x00080000U

#define	FMC_BCR3_MBKEN 0x00000001U

#define	FMC_BCR3_MUXEN 0x00000002U

#define	FMC_BCR3_MTYP 0x0000000CU

#define	FMC_BCR3_MTYP_0 0x00000004U

#define	FMC_BCR3_MTYP_1 0x00000008U

#define	FMC_BCR3_MWID 0x00000030U

#define	FMC_BCR3_MWID_0 0x00000010U

#define	FMC_BCR3_MWID_1 0x00000020U

#define	FMC_BCR3_FACCEN 0x00000040U

#define	FMC_BCR3_BURSTEN 0x00000100U

#define	FMC_BCR3_WAITPOL 0x00000200U

#define	FMC_BCR3_WRAPMOD 0x00000400U

#define	FMC_BCR3_WAITCFG 0x00000800U

#define	FMC_BCR3_WREN 0x00001000U

#define	FMC_BCR3_WAITEN 0x00002000U

#define	FMC_BCR3_EXTMOD 0x00004000U

#define	FMC_BCR3_ASYNCWAIT 0x00008000U

#define	FMC_BCR3_CPSIZE 0x00070000U

#define	FMC_BCR3_CPSIZE_0 0x00010000U

#define	FMC_BCR3_CPSIZE_1 0x00020000U

#define	FMC_BCR3_CPSIZE_2 0x00040000U

#define	FMC_BCR3_CBURSTRW 0x00080000U

#define	FMC_BCR4_MBKEN 0x00000001U

#define	FMC_BCR4_MUXEN 0x00000002U

#define	FMC_BCR4_MTYP 0x0000000CU

#define	FMC_BCR4_MTYP_0 0x00000004U

#define	FMC_BCR4_MTYP_1 0x00000008U

#define	FMC_BCR4_MWID 0x00000030U

#define	FMC_BCR4_MWID_0 0x00000010U

#define	FMC_BCR4_MWID_1 0x00000020U

#define	FMC_BCR4_FACCEN 0x00000040U

#define	FMC_BCR4_BURSTEN 0x00000100U

#define	FMC_BCR4_WAITPOL 0x00000200U

#define	FMC_BCR4_WRAPMOD 0x00000400U

#define	FMC_BCR4_WAITCFG 0x00000800U

#define	FMC_BCR4_WREN 0x00001000U

#define	FMC_BCR4_WAITEN 0x00002000U

#define	FMC_BCR4_EXTMOD 0x00004000U

#define	FMC_BCR4_ASYNCWAIT 0x00008000U

#define	FMC_BCR4_CPSIZE 0x00070000U

#define	FMC_BCR4_CPSIZE_0 0x00010000U

#define	FMC_BCR4_CPSIZE_1 0x00020000U

#define	FMC_BCR4_CPSIZE_2 0x00040000U

#define	FMC_BCR4_CBURSTRW 0x00080000U

#define	FMC_BTR1_ADDSET 0x0000000FU

#define	FMC_BTR1_ADDSET_0 0x00000001U

#define	FMC_BTR1_ADDSET_1 0x00000002U

#define	FMC_BTR1_ADDSET_2 0x00000004U

#define	FMC_BTR1_ADDSET_3 0x00000008U

#define	FMC_BTR1_ADDHLD 0x000000F0U

#define	FMC_BTR1_ADDHLD_0 0x00000010U

#define	FMC_BTR1_ADDHLD_1 0x00000020U

#define	FMC_BTR1_ADDHLD_2 0x00000040U

#define	FMC_BTR1_ADDHLD_3 0x00000080U

#define	FMC_BTR1_DATAST 0x0000FF00U

#define	FMC_BTR1_DATAST_0 0x00000100U

#define	FMC_BTR1_DATAST_1 0x00000200U

#define	FMC_BTR1_DATAST_2 0x00000400U

#define	FMC_BTR1_DATAST_3 0x00000800U

#define	FMC_BTR1_DATAST_4 0x00001000U

#define	FMC_BTR1_DATAST_5 0x00002000U

#define	FMC_BTR1_DATAST_6 0x00004000U

#define	FMC_BTR1_DATAST_7 0x00008000U

#define	FMC_BTR1_BUSTURN 0x000F0000U

#define	FMC_BTR1_BUSTURN_0 0x00010000U

#define	FMC_BTR1_BUSTURN_1 0x00020000U

#define	FMC_BTR1_BUSTURN_2 0x00040000U

#define	FMC_BTR1_BUSTURN_3 0x00080000U

#define	FMC_BTR1_CLKDIV 0x00F00000U

#define	FMC_BTR1_CLKDIV_0 0x00100000U

#define	FMC_BTR1_CLKDIV_1 0x00200000U

#define	FMC_BTR1_CLKDIV_2 0x00400000U

#define	FMC_BTR1_CLKDIV_3 0x00800000U

#define	FMC_BTR1_DATLAT 0x0F000000U

#define	FMC_BTR1_DATLAT_0 0x01000000U

#define	FMC_BTR1_DATLAT_1 0x02000000U

#define	FMC_BTR1_DATLAT_2 0x04000000U

#define	FMC_BTR1_DATLAT_3 0x08000000U

#define	FMC_BTR1_ACCMOD 0x30000000U

#define	FMC_BTR1_ACCMOD_0 0x10000000U

#define	FMC_BTR1_ACCMOD_1 0x20000000U

#define	FMC_BTR2_ADDSET 0x0000000FU

#define	FMC_BTR2_ADDSET_0 0x00000001U

#define	FMC_BTR2_ADDSET_1 0x00000002U

#define	FMC_BTR2_ADDSET_2 0x00000004U

#define	FMC_BTR2_ADDSET_3 0x00000008U

#define	FMC_BTR2_ADDHLD 0x000000F0U

#define	FMC_BTR2_ADDHLD_0 0x00000010U

#define	FMC_BTR2_ADDHLD_1 0x00000020U

#define	FMC_BTR2_ADDHLD_2 0x00000040U

#define	FMC_BTR2_ADDHLD_3 0x00000080U

#define	FMC_BTR2_DATAST 0x0000FF00U

#define	FMC_BTR2_DATAST_0 0x00000100U

#define	FMC_BTR2_DATAST_1 0x00000200U

#define	FMC_BTR2_DATAST_2 0x00000400U

#define	FMC_BTR2_DATAST_3 0x00000800U

#define	FMC_BTR2_DATAST_4 0x00001000U

#define	FMC_BTR2_DATAST_5 0x00002000U

#define	FMC_BTR2_DATAST_6 0x00004000U

#define	FMC_BTR2_DATAST_7 0x00008000U

#define	FMC_BTR2_BUSTURN 0x000F0000U

#define	FMC_BTR2_BUSTURN_0 0x00010000U

#define	FMC_BTR2_BUSTURN_1 0x00020000U

#define	FMC_BTR2_BUSTURN_2 0x00040000U

#define	FMC_BTR2_BUSTURN_3 0x00080000U

#define	FMC_BTR2_CLKDIV 0x00F00000U

#define	FMC_BTR2_CLKDIV_0 0x00100000U

#define	FMC_BTR2_CLKDIV_1 0x00200000U

#define	FMC_BTR2_CLKDIV_2 0x00400000U

#define	FMC_BTR2_CLKDIV_3 0x00800000U

#define	FMC_BTR2_DATLAT 0x0F000000U

#define	FMC_BTR2_DATLAT_0 0x01000000U

#define	FMC_BTR2_DATLAT_1 0x02000000U

#define	FMC_BTR2_DATLAT_2 0x04000000U

#define	FMC_BTR2_DATLAT_3 0x08000000U

#define	FMC_BTR2_ACCMOD 0x30000000U

#define	FMC_BTR2_ACCMOD_0 0x10000000U

#define	FMC_BTR2_ACCMOD_1 0x20000000U

#define	FMC_BTR3_ADDSET 0x0000000FU

#define	FMC_BTR3_ADDSET_0 0x00000001U

#define	FMC_BTR3_ADDSET_1 0x00000002U

#define	FMC_BTR3_ADDSET_2 0x00000004U

#define	FMC_BTR3_ADDSET_3 0x00000008U

#define	FMC_BTR3_ADDHLD 0x000000F0U

#define	FMC_BTR3_ADDHLD_0 0x00000010U

#define	FMC_BTR3_ADDHLD_1 0x00000020U

#define	FMC_BTR3_ADDHLD_2 0x00000040U

#define	FMC_BTR3_ADDHLD_3 0x00000080U

#define	FMC_BTR3_DATAST 0x0000FF00U

#define	FMC_BTR3_DATAST_0 0x00000100U

#define	FMC_BTR3_DATAST_1 0x00000200U

#define	FMC_BTR3_DATAST_2 0x00000400U

#define	FMC_BTR3_DATAST_3 0x00000800U

#define	FMC_BTR3_DATAST_4 0x00001000U

#define	FMC_BTR3_DATAST_5 0x00002000U

#define	FMC_BTR3_DATAST_6 0x00004000U

#define	FMC_BTR3_DATAST_7 0x00008000U

#define	FMC_BTR3_BUSTURN 0x000F0000U

#define	FMC_BTR3_BUSTURN_0 0x00010000U

#define	FMC_BTR3_BUSTURN_1 0x00020000U

#define	FMC_BTR3_BUSTURN_2 0x00040000U

#define	FMC_BTR3_BUSTURN_3 0x00080000U

#define	FMC_BTR3_CLKDIV 0x00F00000U

#define	FMC_BTR3_CLKDIV_0 0x00100000U

#define	FMC_BTR3_CLKDIV_1 0x00200000U

#define	FMC_BTR3_CLKDIV_2 0x00400000U

#define	FMC_BTR3_CLKDIV_3 0x00800000U

#define	FMC_BTR3_DATLAT 0x0F000000U

#define	FMC_BTR3_DATLAT_0 0x01000000U

#define	FMC_BTR3_DATLAT_1 0x02000000U

#define	FMC_BTR3_DATLAT_2 0x04000000U

#define	FMC_BTR3_DATLAT_3 0x08000000U

#define	FMC_BTR3_ACCMOD 0x30000000U

#define	FMC_BTR3_ACCMOD_0 0x10000000U

#define	FMC_BTR3_ACCMOD_1 0x20000000U

#define	FMC_BTR4_ADDSET 0x0000000FU

#define	FMC_BTR4_ADDSET_0 0x00000001U

#define	FMC_BTR4_ADDSET_1 0x00000002U

#define	FMC_BTR4_ADDSET_2 0x00000004U

#define	FMC_BTR4_ADDSET_3 0x00000008U

#define	FMC_BTR4_ADDHLD 0x000000F0U

#define	FMC_BTR4_ADDHLD_0 0x00000010U

#define	FMC_BTR4_ADDHLD_1 0x00000020U

#define	FMC_BTR4_ADDHLD_2 0x00000040U

#define	FMC_BTR4_ADDHLD_3 0x00000080U

#define	FMC_BTR4_DATAST 0x0000FF00U

#define	FMC_BTR4_DATAST_0 0x00000100U

#define	FMC_BTR4_DATAST_1 0x00000200U

#define	FMC_BTR4_DATAST_2 0x00000400U

#define	FMC_BTR4_DATAST_3 0x00000800U

#define	FMC_BTR4_DATAST_4 0x00001000U

#define	FMC_BTR4_DATAST_5 0x00002000U

#define	FMC_BTR4_DATAST_6 0x00004000U

#define	FMC_BTR4_DATAST_7 0x00008000U

#define	FMC_BTR4_BUSTURN 0x000F0000U

#define	FMC_BTR4_BUSTURN_0 0x00010000U

#define	FMC_BTR4_BUSTURN_1 0x00020000U

#define	FMC_BTR4_BUSTURN_2 0x00040000U

#define	FMC_BTR4_BUSTURN_3 0x00080000U

#define	FMC_BTR4_CLKDIV 0x00F00000U

#define	FMC_BTR4_CLKDIV_0 0x00100000U

#define	FMC_BTR4_CLKDIV_1 0x00200000U

#define	FMC_BTR4_CLKDIV_2 0x00400000U

#define	FMC_BTR4_CLKDIV_3 0x00800000U

#define	FMC_BTR4_DATLAT 0x0F000000U

#define	FMC_BTR4_DATLAT_0 0x01000000U

#define	FMC_BTR4_DATLAT_1 0x02000000U

#define	FMC_BTR4_DATLAT_2 0x04000000U

#define	FMC_BTR4_DATLAT_3 0x08000000U

#define	FMC_BTR4_ACCMOD 0x30000000U

#define	FMC_BTR4_ACCMOD_0 0x10000000U

#define	FMC_BTR4_ACCMOD_1 0x20000000U

#define	FMC_BWTR1_ADDSET 0x0000000FU

#define	FMC_BWTR1_ADDSET_0 0x00000001U

#define	FMC_BWTR1_ADDSET_1 0x00000002U

#define	FMC_BWTR1_ADDSET_2 0x00000004U

#define	FMC_BWTR1_ADDSET_3 0x00000008U

#define	FMC_BWTR1_ADDHLD 0x000000F0U

#define	FMC_BWTR1_ADDHLD_0 0x00000010U

#define	FMC_BWTR1_ADDHLD_1 0x00000020U

#define	FMC_BWTR1_ADDHLD_2 0x00000040U

#define	FMC_BWTR1_ADDHLD_3 0x00000080U

#define	FMC_BWTR1_DATAST 0x0000FF00U

#define	FMC_BWTR1_DATAST_0 0x00000100U

#define	FMC_BWTR1_DATAST_1 0x00000200U

#define	FMC_BWTR1_DATAST_2 0x00000400U

#define	FMC_BWTR1_DATAST_3 0x00000800U

#define	FMC_BWTR1_DATAST_4 0x00001000U

#define	FMC_BWTR1_DATAST_5 0x00002000U

#define	FMC_BWTR1_DATAST_6 0x00004000U

#define	FMC_BWTR1_DATAST_7 0x00008000U

#define	FMC_BWTR1_BUSTURN 0x000F0000U

#define	FMC_BWTR1_BUSTURN_0 0x00010000U

#define	FMC_BWTR1_BUSTURN_1 0x00020000U

#define	FMC_BWTR1_BUSTURN_2 0x00040000U

#define	FMC_BWTR1_BUSTURN_3 0x00080000U

#define	FMC_BWTR1_ACCMOD 0x30000000U

#define	FMC_BWTR1_ACCMOD_0 0x10000000U

#define	FMC_BWTR1_ACCMOD_1 0x20000000U

#define	FMC_BWTR2_ADDSET 0x0000000FU

#define	FMC_BWTR2_ADDSET_0 0x00000001U

#define	FMC_BWTR2_ADDSET_1 0x00000002U

#define	FMC_BWTR2_ADDSET_2 0x00000004U

#define	FMC_BWTR2_ADDSET_3 0x00000008U

#define	FMC_BWTR2_ADDHLD 0x000000F0U

#define	FMC_BWTR2_ADDHLD_0 0x00000010U

#define	FMC_BWTR2_ADDHLD_1 0x00000020U

#define	FMC_BWTR2_ADDHLD_2 0x00000040U

#define	FMC_BWTR2_ADDHLD_3 0x00000080U

#define	FMC_BWTR2_DATAST 0x0000FF00U

#define	FMC_BWTR2_DATAST_0 0x00000100U

#define	FMC_BWTR2_DATAST_1 0x00000200U

#define	FMC_BWTR2_DATAST_2 0x00000400U

#define	FMC_BWTR2_DATAST_3 0x00000800U

#define	FMC_BWTR2_DATAST_4 0x00001000U

#define	FMC_BWTR2_DATAST_5 0x00002000U

#define	FMC_BWTR2_DATAST_6 0x00004000U

#define	FMC_BWTR2_DATAST_7 0x00008000U

#define	FMC_BWTR2_BUSTURN 0x000F0000U

#define	FMC_BWTR2_BUSTURN_0 0x00010000U

#define	FMC_BWTR2_BUSTURN_1 0x00020000U

#define	FMC_BWTR2_BUSTURN_2 0x00040000U

#define	FMC_BWTR2_BUSTURN_3 0x00080000U

#define	FMC_BWTR2_ACCMOD 0x30000000U

#define	FMC_BWTR2_ACCMOD_0 0x10000000U

#define	FMC_BWTR2_ACCMOD_1 0x20000000U

#define	FMC_BWTR3_ADDSET 0x0000000FU

#define	FMC_BWTR3_ADDSET_0 0x00000001U

#define	FMC_BWTR3_ADDSET_1 0x00000002U

#define	FMC_BWTR3_ADDSET_2 0x00000004U

#define	FMC_BWTR3_ADDSET_3 0x00000008U

#define	FMC_BWTR3_ADDHLD 0x000000F0U

#define	FMC_BWTR3_ADDHLD_0 0x00000010U

#define	FMC_BWTR3_ADDHLD_1 0x00000020U

#define	FMC_BWTR3_ADDHLD_2 0x00000040U

#define	FMC_BWTR3_ADDHLD_3 0x00000080U

#define	FMC_BWTR3_DATAST 0x0000FF00U

#define	FMC_BWTR3_DATAST_0 0x00000100U

#define	FMC_BWTR3_DATAST_1 0x00000200U

#define	FMC_BWTR3_DATAST_2 0x00000400U

#define	FMC_BWTR3_DATAST_3 0x00000800U

#define	FMC_BWTR3_DATAST_4 0x00001000U

#define	FMC_BWTR3_DATAST_5 0x00002000U

#define	FMC_BWTR3_DATAST_6 0x00004000U

#define	FMC_BWTR3_DATAST_7 0x00008000U

#define	FMC_BWTR3_BUSTURN 0x000F0000U

#define	FMC_BWTR3_BUSTURN_0 0x00010000U

#define	FMC_BWTR3_BUSTURN_1 0x00020000U

#define	FMC_BWTR3_BUSTURN_2 0x00040000U

#define	FMC_BWTR3_BUSTURN_3 0x00080000U

#define	FMC_BWTR3_ACCMOD 0x30000000U

#define	FMC_BWTR3_ACCMOD_0 0x10000000U

#define	FMC_BWTR3_ACCMOD_1 0x20000000U

#define	FMC_BWTR4_ADDSET 0x0000000FU

#define	FMC_BWTR4_ADDSET_0 0x00000001U

#define	FMC_BWTR4_ADDSET_1 0x00000002U

#define	FMC_BWTR4_ADDSET_2 0x00000004U

#define	FMC_BWTR4_ADDSET_3 0x00000008U

#define	FMC_BWTR4_ADDHLD 0x000000F0U

#define	FMC_BWTR4_ADDHLD_0 0x00000010U

#define	FMC_BWTR4_ADDHLD_1 0x00000020U

#define	FMC_BWTR4_ADDHLD_2 0x00000040U

#define	FMC_BWTR4_ADDHLD_3 0x00000080U

#define	FMC_BWTR4_DATAST 0x0000FF00U

#define	FMC_BWTR4_DATAST_0 0x00000100U

#define	FMC_BWTR4_DATAST_1 0x00000200U

#define	FMC_BWTR4_DATAST_2 0x00000400U

#define	FMC_BWTR4_DATAST_3 0x00000800U

#define	FMC_BWTR4_DATAST_4 0x00001000U

#define	FMC_BWTR4_DATAST_5 0x00002000U

#define	FMC_BWTR4_DATAST_6 0x00004000U

#define	FMC_BWTR4_DATAST_7 0x00008000U

#define	FMC_BWTR4_BUSTURN 0x000F0000U

#define	FMC_BWTR4_BUSTURN_0 0x00010000U

#define	FMC_BWTR4_BUSTURN_1 0x00020000U

#define	FMC_BWTR4_BUSTURN_2 0x00040000U

#define	FMC_BWTR4_BUSTURN_3 0x00080000U

#define	FMC_BWTR4_ACCMOD 0x30000000U

#define	FMC_BWTR4_ACCMOD_0 0x10000000U

#define	FMC_BWTR4_ACCMOD_1 0x20000000U

#define	FMC_PCR_PWAITEN 0x00000002U

#define	FMC_PCR_PBKEN 0x00000004U

#define	FMC_PCR_PTYP 0x00000008U

#define	FMC_PCR_PWID 0x00000030U

#define	FMC_PCR_PWID_0 0x00000010U

#define	FMC_PCR_PWID_1 0x00000020U

#define	FMC_PCR_ECCEN 0x00000040U

#define	FMC_PCR_TCLR 0x00001E00U

#define	FMC_PCR_TCLR_0 0x00000200U

#define	FMC_PCR_TCLR_1 0x00000400U

#define	FMC_PCR_TCLR_2 0x00000800U

#define	FMC_PCR_TCLR_3 0x00001000U

#define	FMC_PCR_TAR 0x0001E000U

#define	FMC_PCR_TAR_0 0x00002000U

#define	FMC_PCR_TAR_1 0x00004000U

#define	FMC_PCR_TAR_2 0x00008000U

#define	FMC_PCR_TAR_3 0x00010000U

#define	FMC_PCR_ECCPS 0x000E0000U

#define	FMC_PCR_ECCPS_0 0x00020000U

#define	FMC_PCR_ECCPS_1 0x00040000U

#define	FMC_PCR_ECCPS_2 0x00080000U

#define	FMC_SR_IRS 0x01U

#define	FMC_SR_ILS 0x02U

#define	FMC_SR_IFS 0x04U

#define	FMC_SR_IREN 0x08U

#define	FMC_SR_ILEN 0x10U

#define	FMC_SR_IFEN 0x20U

#define	FMC_SR_FEMPT 0x40U

#define	FMC_PMEM_MEMSET3 0x000000FFU

#define	FMC_PMEM_MEMSET3_0 0x00000001U

#define	FMC_PMEM_MEMSET3_1 0x00000002U

#define	FMC_PMEM_MEMSET3_2 0x00000004U

#define	FMC_PMEM_MEMSET3_3 0x00000008U

#define	FMC_PMEM_MEMSET3_4 0x00000010U

#define	FMC_PMEM_MEMSET3_5 0x00000020U

#define	FMC_PMEM_MEMSET3_6 0x00000040U

#define	FMC_PMEM_MEMSET3_7 0x00000080U

#define	FMC_PMEM_MEMWAIT3 0x0000FF00U

#define	FMC_PMEM_MEMWAIT3_0 0x00000100U

#define	FMC_PMEM_MEMWAIT3_1 0x00000200U

#define	FMC_PMEM_MEMWAIT3_2 0x00000400U

#define	FMC_PMEM_MEMWAIT3_3 0x00000800U

#define	FMC_PMEM_MEMWAIT3_4 0x00001000U

#define	FMC_PMEM_MEMWAIT3_5 0x00002000U

#define	FMC_PMEM_MEMWAIT3_6 0x00004000U

#define	FMC_PMEM_MEMWAIT3_7 0x00008000U

#define	FMC_PMEM_MEMHOLD3 0x00FF0000U

#define	FMC_PMEM_MEMHOLD3_0 0x00010000U

#define	FMC_PMEM_MEMHOLD3_1 0x00020000U

#define	FMC_PMEM_MEMHOLD3_2 0x00040000U

#define	FMC_PMEM_MEMHOLD3_3 0x00080000U

#define	FMC_PMEM_MEMHOLD3_4 0x00100000U

#define	FMC_PMEM_MEMHOLD3_5 0x00200000U

#define	FMC_PMEM_MEMHOLD3_6 0x00400000U

#define	FMC_PMEM_MEMHOLD3_7 0x00800000U

#define	FMC_PMEM_MEMHIZ3 0xFF000000U

#define	FMC_PMEM_MEMHIZ3_0 0x01000000U

#define	FMC_PMEM_MEMHIZ3_1 0x02000000U

#define	FMC_PMEM_MEMHIZ3_2 0x04000000U

#define	FMC_PMEM_MEMHIZ3_3 0x08000000U

#define	FMC_PMEM_MEMHIZ3_4 0x10000000U

#define	FMC_PMEM_MEMHIZ3_5 0x20000000U

#define	FMC_PMEM_MEMHIZ3_6 0x40000000U

#define	FMC_PMEM_MEMHIZ3_7 0x80000000U

#define	FMC_PATT_ATTSET3 0x000000FFU

#define	FMC_PATT_ATTSET3_0 0x00000001U

#define	FMC_PATT_ATTSET3_1 0x00000002U

#define	FMC_PATT_ATTSET3_2 0x00000004U

#define	FMC_PATT_ATTSET3_3 0x00000008U

#define	FMC_PATT_ATTSET3_4 0x00000010U

#define	FMC_PATT_ATTSET3_5 0x00000020U

#define	FMC_PATT_ATTSET3_6 0x00000040U

#define	FMC_PATT_ATTSET3_7 0x00000080U

#define	FMC_PATT_ATTWAIT3 0x0000FF00U

#define	FMC_PATT_ATTWAIT3_0 0x00000100U

#define	FMC_PATT_ATTWAIT3_1 0x00000200U

#define	FMC_PATT_ATTWAIT3_2 0x00000400U

#define	FMC_PATT_ATTWAIT3_3 0x00000800U

#define	FMC_PATT_ATTWAIT3_4 0x00001000U

#define	FMC_PATT_ATTWAIT3_5 0x00002000U

#define	FMC_PATT_ATTWAIT3_6 0x00004000U

#define	FMC_PATT_ATTWAIT3_7 0x00008000U

#define	FMC_PATT_ATTHOLD3 0x00FF0000U

#define	FMC_PATT_ATTHOLD3_0 0x00010000U

#define	FMC_PATT_ATTHOLD3_1 0x00020000U

#define	FMC_PATT_ATTHOLD3_2 0x00040000U

#define	FMC_PATT_ATTHOLD3_3 0x00080000U

#define	FMC_PATT_ATTHOLD3_4 0x00100000U

#define	FMC_PATT_ATTHOLD3_5 0x00200000U

#define	FMC_PATT_ATTHOLD3_6 0x00400000U

#define	FMC_PATT_ATTHOLD3_7 0x00800000U

#define	FMC_PATT_ATTHIZ3 0xFF000000U

#define	FMC_PATT_ATTHIZ3_0 0x01000000U

#define	FMC_PATT_ATTHIZ3_1 0x02000000U

#define	FMC_PATT_ATTHIZ3_2 0x04000000U

#define	FMC_PATT_ATTHIZ3_3 0x08000000U

#define	FMC_PATT_ATTHIZ3_4 0x10000000U

#define	FMC_PATT_ATTHIZ3_5 0x20000000U

#define	FMC_PATT_ATTHIZ3_6 0x40000000U

#define	FMC_PATT_ATTHIZ3_7 0x80000000U

#define	FMC_ECCR_ECC3 0xFFFFFFFFU

#define	FMC_SDCR1_NC 0x00000003U

#define	FMC_SDCR1_NC_0 0x00000001U

#define	FMC_SDCR1_NC_1 0x00000002U

#define	FMC_SDCR1_NR 0x0000000CU

#define	FMC_SDCR1_NR_0 0x00000004U

#define	FMC_SDCR1_NR_1 0x00000008U

#define	FMC_SDCR1_MWID 0x00000030U

#define	FMC_SDCR1_MWID_0 0x00000010U

#define	FMC_SDCR1_MWID_1 0x00000020U

#define	FMC_SDCR1_NB 0x00000040U

#define	FMC_SDCR1_CAS 0x00000180U

#define	FMC_SDCR1_CAS_0 0x00000080U

#define	FMC_SDCR1_CAS_1 0x00000100U

#define	FMC_SDCR1_WP 0x00000200U

#define	FMC_SDCR1_SDCLK 0x00000C00U

#define	FMC_SDCR1_SDCLK_0 0x00000400U

#define	FMC_SDCR1_SDCLK_1 0x00000800U

#define	FMC_SDCR1_RBURST 0x00001000U

#define	FMC_SDCR1_RPIPE 0x00006000U

#define	FMC_SDCR1_RPIPE_0 0x00002000U

#define	FMC_SDCR1_RPIPE_1 0x00004000U

#define	FMC_SDCR2_NC 0x00000003U

#define	FMC_SDCR2_NC_0 0x00000001U

#define	FMC_SDCR2_NC_1 0x00000002U

#define	FMC_SDCR2_NR 0x0000000CU

#define	FMC_SDCR2_NR_0 0x00000004U

#define	FMC_SDCR2_NR_1 0x00000008U

#define	FMC_SDCR2_MWID 0x00000030U

#define	FMC_SDCR2_MWID_0 0x00000010U

#define	FMC_SDCR2_MWID_1 0x00000020U

#define	FMC_SDCR2_NB 0x00000040U

#define	FMC_SDCR2_CAS 0x00000180U

#define	FMC_SDCR2_CAS_0 0x00000080U

#define	FMC_SDCR2_CAS_1 0x00000100U

#define	FMC_SDCR2_WP 0x00000200U

#define	FMC_SDCR2_SDCLK 0x00000C00U

#define	FMC_SDCR2_SDCLK_0 0x00000400U

#define	FMC_SDCR2_SDCLK_1 0x00000800U

#define	FMC_SDCR2_RBURST 0x00001000U

#define	FMC_SDCR2_RPIPE 0x00006000U

#define	FMC_SDCR2_RPIPE_0 0x00002000U

#define	FMC_SDCR2_RPIPE_1 0x00004000U

#define	FMC_SDTR1_TMRD 0x0000000FU

#define	FMC_SDTR1_TMRD_0 0x00000001U

#define	FMC_SDTR1_TMRD_1 0x00000002U

#define	FMC_SDTR1_TMRD_2 0x00000004U

#define	FMC_SDTR1_TMRD_3 0x00000008U

#define	FMC_SDTR1_TXSR 0x000000F0U

#define	FMC_SDTR1_TXSR_0 0x00000010U

#define	FMC_SDTR1_TXSR_1 0x00000020U

#define	FMC_SDTR1_TXSR_2 0x00000040U

#define	FMC_SDTR1_TXSR_3 0x00000080U

#define	FMC_SDTR1_TRAS 0x00000F00U

#define	FMC_SDTR1_TRAS_0 0x00000100U

#define	FMC_SDTR1_TRAS_1 0x00000200U

#define	FMC_SDTR1_TRAS_2 0x00000400U

#define	FMC_SDTR1_TRAS_3 0x00000800U

#define	FMC_SDTR1_TRC 0x0000F000U

#define	FMC_SDTR1_TRC_0 0x00001000U

#define	FMC_SDTR1_TRC_1 0x00002000U

#define	FMC_SDTR1_TRC_2 0x00004000U

#define	FMC_SDTR1_TWR 0x000F0000U

#define	FMC_SDTR1_TWR_0 0x00010000U

#define	FMC_SDTR1_TWR_1 0x00020000U

#define	FMC_SDTR1_TWR_2 0x00040000U

#define	FMC_SDTR1_TRP 0x00F00000U

#define	FMC_SDTR1_TRP_0 0x00100000U

#define	FMC_SDTR1_TRP_1 0x00200000U

#define	FMC_SDTR1_TRP_2 0x00400000U

#define	FMC_SDTR1_TRCD 0x0F000000U

#define	FMC_SDTR1_TRCD_0 0x01000000U

#define	FMC_SDTR1_TRCD_1 0x02000000U

#define	FMC_SDTR1_TRCD_2 0x04000000U

#define	FMC_SDTR2_TMRD 0x0000000FU

#define	FMC_SDTR2_TMRD_0 0x00000001U

#define	FMC_SDTR2_TMRD_1 0x00000002U

#define	FMC_SDTR2_TMRD_2 0x00000004U

#define	FMC_SDTR2_TMRD_3 0x00000008U

#define	FMC_SDTR2_TXSR 0x000000F0U

#define	FMC_SDTR2_TXSR_0 0x00000010U

#define	FMC_SDTR2_TXSR_1 0x00000020U

#define	FMC_SDTR2_TXSR_2 0x00000040U

#define	FMC_SDTR2_TXSR_3 0x00000080U

#define	FMC_SDTR2_TRAS 0x00000F00U

#define	FMC_SDTR2_TRAS_0 0x00000100U

#define	FMC_SDTR2_TRAS_1 0x00000200U

#define	FMC_SDTR2_TRAS_2 0x00000400U

#define	FMC_SDTR2_TRAS_3 0x00000800U

#define	FMC_SDTR2_TRC 0x0000F000U

#define	FMC_SDTR2_TRC_0 0x00001000U

#define	FMC_SDTR2_TRC_1 0x00002000U

#define	FMC_SDTR2_TRC_2 0x00004000U

#define	FMC_SDTR2_TWR 0x000F0000U

#define	FMC_SDTR2_TWR_0 0x00010000U

#define	FMC_SDTR2_TWR_1 0x00020000U

#define	FMC_SDTR2_TWR_2 0x00040000U

#define	FMC_SDTR2_TRP 0x00F00000U

#define	FMC_SDTR2_TRP_0 0x00100000U

#define	FMC_SDTR2_TRP_1 0x00200000U

#define	FMC_SDTR2_TRP_2 0x00400000U

#define	FMC_SDTR2_TRCD 0x0F000000U

#define	FMC_SDTR2_TRCD_0 0x01000000U

#define	FMC_SDTR2_TRCD_1 0x02000000U

#define	FMC_SDTR2_TRCD_2 0x04000000U

#define	FMC_SDCMR_MODE 0x00000007U

#define	FMC_SDCMR_MODE_0 0x00000001U

#define	FMC_SDCMR_MODE_1 0x00000002U

#define	FMC_SDCMR_MODE_2 0x00000003U

#define	FMC_SDCMR_CTB2 0x00000008U

#define	FMC_SDCMR_CTB1 0x00000010U

#define	FMC_SDCMR_NRFS 0x000001E0U

#define	FMC_SDCMR_NRFS_0 0x00000020U

#define	FMC_SDCMR_NRFS_1 0x00000040U

#define	FMC_SDCMR_NRFS_2 0x00000080U

#define	FMC_SDCMR_NRFS_3 0x00000100U

#define	FMC_SDCMR_MRD 0x003FFE00U

#define	FMC_SDRTR_CRE 0x00000001U

#define	FMC_SDRTR_COUNT 0x00003FFEU

#define	FMC_SDRTR_REIE 0x00004000U

#define	FMC_SDSR_RE 0x00000001U

#define	FMC_SDSR_MODES1 0x00000006U

#define	FMC_SDSR_MODES1_0 0x00000002U

#define	FMC_SDSR_MODES1_1 0x00000004U

#define	FMC_SDSR_MODES2 0x00000018U

#define	FMC_SDSR_MODES2_0 0x00000008U

#define	FMC_SDSR_MODES2_1 0x00000010U

#define	FMC_SDSR_BUSY 0x00000020U

#define	GPIO_MODER_MODER0 0x00000003U

#define	GPIO_MODER_MODER0_0 0x00000001U

#define	GPIO_MODER_MODER0_1 0x00000002U

#define	GPIO_MODER_MODER1 0x0000000CU

#define	GPIO_MODER_MODER1_0 0x00000004U

#define	GPIO_MODER_MODER1_1 0x00000008U

#define	GPIO_MODER_MODER2 0x00000030U

#define	GPIO_MODER_MODER2_0 0x00000010U

#define	GPIO_MODER_MODER2_1 0x00000020U

#define	GPIO_MODER_MODER3 0x000000C0U

#define	GPIO_MODER_MODER3_0 0x00000040U

#define	GPIO_MODER_MODER3_1 0x00000080U

#define	GPIO_MODER_MODER4 0x00000300U

#define	GPIO_MODER_MODER4_0 0x00000100U

#define	GPIO_MODER_MODER4_1 0x00000200U

#define	GPIO_MODER_MODER5 0x00000C00U

#define	GPIO_MODER_MODER5_0 0x00000400U

#define	GPIO_MODER_MODER5_1 0x00000800U

#define	GPIO_MODER_MODER6 0x00003000U

#define	GPIO_MODER_MODER6_0 0x00001000U

#define	GPIO_MODER_MODER6_1 0x00002000U

#define	GPIO_MODER_MODER7 0x0000C000U

#define	GPIO_MODER_MODER7_0 0x00004000U

#define	GPIO_MODER_MODER7_1 0x00008000U

#define	GPIO_MODER_MODER8 0x00030000U

#define	GPIO_MODER_MODER8_0 0x00010000U

#define	GPIO_MODER_MODER8_1 0x00020000U

#define	GPIO_MODER_MODER9 0x000C0000U

#define	GPIO_MODER_MODER9_0 0x00040000U

#define	GPIO_MODER_MODER9_1 0x00080000U

#define	GPIO_MODER_MODER10 0x00300000U

#define	GPIO_MODER_MODER10_0 0x00100000U

#define	GPIO_MODER_MODER10_1 0x00200000U

#define	GPIO_MODER_MODER11 0x00C00000U

#define	GPIO_MODER_MODER11_0 0x00400000U

#define	GPIO_MODER_MODER11_1 0x00800000U

#define	GPIO_MODER_MODER12 0x03000000U

#define	GPIO_MODER_MODER12_0 0x01000000U

#define	GPIO_MODER_MODER12_1 0x02000000U

#define	GPIO_MODER_MODER13 0x0C000000U

#define	GPIO_MODER_MODER13_0 0x04000000U

#define	GPIO_MODER_MODER13_1 0x08000000U

#define	GPIO_MODER_MODER14 0x30000000U

#define	GPIO_MODER_MODER14_0 0x10000000U

#define	GPIO_MODER_MODER14_1 0x20000000U

#define	GPIO_MODER_MODER15 0xC0000000U

#define	GPIO_MODER_MODER15_0 0x40000000U

#define	GPIO_MODER_MODER15_1 0x80000000U

#define	GPIO_OTYPER_OT_0 0x00000001U

#define	GPIO_OTYPER_OT_1 0x00000002U

#define	GPIO_OTYPER_OT_2 0x00000004U

#define	GPIO_OTYPER_OT_3 0x00000008U

#define	GPIO_OTYPER_OT_4 0x00000010U

#define	GPIO_OTYPER_OT_5 0x00000020U

#define	GPIO_OTYPER_OT_6 0x00000040U

#define	GPIO_OTYPER_OT_7 0x00000080U

#define	GPIO_OTYPER_OT_8 0x00000100U

#define	GPIO_OTYPER_OT_9 0x00000200U

#define	GPIO_OTYPER_OT_10 0x00000400U

#define	GPIO_OTYPER_OT_11 0x00000800U

#define	GPIO_OTYPER_OT_12 0x00001000U

#define	GPIO_OTYPER_OT_13 0x00002000U

#define	GPIO_OTYPER_OT_14 0x00004000U

#define	GPIO_OTYPER_OT_15 0x00008000U

#define	GPIO_OSPEEDER_OSPEEDR0 0x00000003U

#define	GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U

#define	GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U

#define	GPIO_OSPEEDER_OSPEEDR1 0x0000000CU

#define	GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U

#define	GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U

#define	GPIO_OSPEEDER_OSPEEDR2 0x00000030U

#define	GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U

#define	GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U

#define	GPIO_OSPEEDER_OSPEEDR3 0x000000C0U

#define	GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U

#define	GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U

#define	GPIO_OSPEEDER_OSPEEDR4 0x00000300U

#define	GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U

#define	GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U

#define	GPIO_OSPEEDER_OSPEEDR5 0x00000C00U

#define	GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U

#define	GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U

#define	GPIO_OSPEEDER_OSPEEDR6 0x00003000U

#define	GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U

#define	GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U

#define	GPIO_OSPEEDER_OSPEEDR7 0x0000C000U

#define	GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U

#define	GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U

#define	GPIO_OSPEEDER_OSPEEDR8 0x00030000U

#define	GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U

#define	GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U

#define	GPIO_OSPEEDER_OSPEEDR9 0x000C0000U

#define	GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U

#define	GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U

#define	GPIO_OSPEEDER_OSPEEDR10 0x00300000U

#define	GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U

#define	GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U

#define	GPIO_OSPEEDER_OSPEEDR11 0x00C00000U

#define	GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U

#define	GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U

#define	GPIO_OSPEEDER_OSPEEDR12 0x03000000U

#define	GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U

#define	GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U

#define	GPIO_OSPEEDER_OSPEEDR13 0x0C000000U

#define	GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U

#define	GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U

#define	GPIO_OSPEEDER_OSPEEDR14 0x30000000U

#define	GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U

#define	GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U

#define	GPIO_OSPEEDER_OSPEEDR15 0xC0000000U

#define	GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U

#define	GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U

#define	GPIO_PUPDR_PUPDR0 0x00000003U

#define	GPIO_PUPDR_PUPDR0_0 0x00000001U

#define	GPIO_PUPDR_PUPDR0_1 0x00000002U

#define	GPIO_PUPDR_PUPDR1 0x0000000CU

#define	GPIO_PUPDR_PUPDR1_0 0x00000004U

#define	GPIO_PUPDR_PUPDR1_1 0x00000008U

#define	GPIO_PUPDR_PUPDR2 0x00000030U

#define	GPIO_PUPDR_PUPDR2_0 0x00000010U

#define	GPIO_PUPDR_PUPDR2_1 0x00000020U

#define	GPIO_PUPDR_PUPDR3 0x000000C0U

#define	GPIO_PUPDR_PUPDR3_0 0x00000040U

#define	GPIO_PUPDR_PUPDR3_1 0x00000080U

#define	GPIO_PUPDR_PUPDR4 0x00000300U

#define	GPIO_PUPDR_PUPDR4_0 0x00000100U

#define	GPIO_PUPDR_PUPDR4_1 0x00000200U

#define	GPIO_PUPDR_PUPDR5 0x00000C00U

#define	GPIO_PUPDR_PUPDR5_0 0x00000400U

#define	GPIO_PUPDR_PUPDR5_1 0x00000800U

#define	GPIO_PUPDR_PUPDR6 0x00003000U

#define	GPIO_PUPDR_PUPDR6_0 0x00001000U

#define	GPIO_PUPDR_PUPDR6_1 0x00002000U

#define	GPIO_PUPDR_PUPDR7 0x0000C000U

#define	GPIO_PUPDR_PUPDR7_0 0x00004000U

#define	GPIO_PUPDR_PUPDR7_1 0x00008000U

#define	GPIO_PUPDR_PUPDR8 0x00030000U

#define	GPIO_PUPDR_PUPDR8_0 0x00010000U

#define	GPIO_PUPDR_PUPDR8_1 0x00020000U

#define	GPIO_PUPDR_PUPDR9 0x000C0000U

#define	GPIO_PUPDR_PUPDR9_0 0x00040000U

#define	GPIO_PUPDR_PUPDR9_1 0x00080000U

#define	GPIO_PUPDR_PUPDR10 0x00300000U

#define	GPIO_PUPDR_PUPDR10_0 0x00100000U

#define	GPIO_PUPDR_PUPDR10_1 0x00200000U

#define	GPIO_PUPDR_PUPDR11 0x00C00000U

#define	GPIO_PUPDR_PUPDR11_0 0x00400000U

#define	GPIO_PUPDR_PUPDR11_1 0x00800000U

#define	GPIO_PUPDR_PUPDR12 0x03000000U

#define	GPIO_PUPDR_PUPDR12_0 0x01000000U

#define	GPIO_PUPDR_PUPDR12_1 0x02000000U

#define	GPIO_PUPDR_PUPDR13 0x0C000000U

#define	GPIO_PUPDR_PUPDR13_0 0x04000000U

#define	GPIO_PUPDR_PUPDR13_1 0x08000000U

#define	GPIO_PUPDR_PUPDR14 0x30000000U

#define	GPIO_PUPDR_PUPDR14_0 0x10000000U

#define	GPIO_PUPDR_PUPDR14_1 0x20000000U

#define	GPIO_PUPDR_PUPDR15 0xC0000000U

#define	GPIO_PUPDR_PUPDR15_0 0x40000000U

#define	GPIO_PUPDR_PUPDR15_1 0x80000000U

#define	GPIO_IDR_IDR_0 0x00000001U

#define	GPIO_IDR_IDR_1 0x00000002U

#define	GPIO_IDR_IDR_2 0x00000004U

#define	GPIO_IDR_IDR_3 0x00000008U

#define	GPIO_IDR_IDR_4 0x00000010U

#define	GPIO_IDR_IDR_5 0x00000020U

#define	GPIO_IDR_IDR_6 0x00000040U

#define	GPIO_IDR_IDR_7 0x00000080U

#define	GPIO_IDR_IDR_8 0x00000100U

#define	GPIO_IDR_IDR_9 0x00000200U

#define	GPIO_IDR_IDR_10 0x00000400U

#define	GPIO_IDR_IDR_11 0x00000800U

#define	GPIO_IDR_IDR_12 0x00001000U

#define	GPIO_IDR_IDR_13 0x00002000U

#define	GPIO_IDR_IDR_14 0x00004000U

#define	GPIO_IDR_IDR_15 0x00008000U

#define	GPIO_ODR_ODR_0 0x00000001U

#define	GPIO_ODR_ODR_1 0x00000002U

#define	GPIO_ODR_ODR_2 0x00000004U

#define	GPIO_ODR_ODR_3 0x00000008U

#define	GPIO_ODR_ODR_4 0x00000010U

#define	GPIO_ODR_ODR_5 0x00000020U

#define	GPIO_ODR_ODR_6 0x00000040U

#define	GPIO_ODR_ODR_7 0x00000080U

#define	GPIO_ODR_ODR_8 0x00000100U

#define	GPIO_ODR_ODR_9 0x00000200U

#define	GPIO_ODR_ODR_10 0x00000400U

#define	GPIO_ODR_ODR_11 0x00000800U

#define	GPIO_ODR_ODR_12 0x00001000U

#define	GPIO_ODR_ODR_13 0x00002000U

#define	GPIO_ODR_ODR_14 0x00004000U

#define	GPIO_ODR_ODR_15 0x00008000U

#define	GPIO_BSRR_BS_0 0x00000001U

#define	GPIO_BSRR_BS_1 0x00000002U

#define	GPIO_BSRR_BS_2 0x00000004U

#define	GPIO_BSRR_BS_3 0x00000008U

#define	GPIO_BSRR_BS_4 0x00000010U

#define	GPIO_BSRR_BS_5 0x00000020U

#define	GPIO_BSRR_BS_6 0x00000040U

#define	GPIO_BSRR_BS_7 0x00000080U

#define	GPIO_BSRR_BS_8 0x00000100U

#define	GPIO_BSRR_BS_9 0x00000200U

#define	GPIO_BSRR_BS_10 0x00000400U

#define	GPIO_BSRR_BS_11 0x00000800U

#define	GPIO_BSRR_BS_12 0x00001000U

#define	GPIO_BSRR_BS_13 0x00002000U

#define	GPIO_BSRR_BS_14 0x00004000U

#define	GPIO_BSRR_BS_15 0x00008000U

#define	GPIO_BSRR_BR_0 0x00010000U

#define	GPIO_BSRR_BR_1 0x00020000U

#define	GPIO_BSRR_BR_2 0x00040000U

#define	GPIO_BSRR_BR_3 0x00080000U

#define	GPIO_BSRR_BR_4 0x00100000U

#define	GPIO_BSRR_BR_5 0x00200000U

#define	GPIO_BSRR_BR_6 0x00400000U

#define	GPIO_BSRR_BR_7 0x00800000U

#define	GPIO_BSRR_BR_8 0x01000000U

#define	GPIO_BSRR_BR_9 0x02000000U

#define	GPIO_BSRR_BR_10 0x04000000U

#define	GPIO_BSRR_BR_11 0x08000000U

#define	GPIO_BSRR_BR_12 0x10000000U

#define	GPIO_BSRR_BR_13 0x20000000U

#define	GPIO_BSRR_BR_14 0x40000000U

#define	GPIO_BSRR_BR_15 0x80000000U

#define	GPIO_LCKR_LCK0 0x00000001U

#define	GPIO_LCKR_LCK1 0x00000002U

#define	GPIO_LCKR_LCK2 0x00000004U

#define	GPIO_LCKR_LCK3 0x00000008U

#define	GPIO_LCKR_LCK4 0x00000010U

#define	GPIO_LCKR_LCK5 0x00000020U

#define	GPIO_LCKR_LCK6 0x00000040U

#define	GPIO_LCKR_LCK7 0x00000080U

#define	GPIO_LCKR_LCK8 0x00000100U

#define	GPIO_LCKR_LCK9 0x00000200U

#define	GPIO_LCKR_LCK10 0x00000400U

#define	GPIO_LCKR_LCK11 0x00000800U

#define	GPIO_LCKR_LCK12 0x00001000U

#define	GPIO_LCKR_LCK13 0x00002000U

#define	GPIO_LCKR_LCK14 0x00004000U

#define	GPIO_LCKR_LCK15 0x00008000U

#define	GPIO_LCKR_LCKK 0x00010000U

#define	HASH_CR_INIT 0x00000004U

#define	HASH_CR_DMAE 0x00000008U

#define	HASH_CR_DATATYPE 0x00000030U

#define	HASH_CR_DATATYPE_0 0x00000010U

#define	HASH_CR_DATATYPE_1 0x00000020U

#define	HASH_CR_MODE 0x00000040U

#define	HASH_CR_ALGO 0x00040080U

#define	HASH_CR_ALGO_0 0x00000080U

#define	HASH_CR_ALGO_1 0x00040000U

#define	HASH_CR_NBW 0x00000F00U

#define	HASH_CR_NBW_0 0x00000100U

#define	HASH_CR_NBW_1 0x00000200U

#define	HASH_CR_NBW_2 0x00000400U

#define	HASH_CR_NBW_3 0x00000800U

#define	HASH_CR_DINNE 0x00001000U

#define	HASH_CR_MDMAT 0x00002000U

#define	HASH_CR_LKEY 0x00010000U

#define	HASH_STR_NBLW 0x0000001FU

#define	HASH_STR_NBLW_0 0x00000001U

#define	HASH_STR_NBLW_1 0x00000002U

#define	HASH_STR_NBLW_2 0x00000004U

#define	HASH_STR_NBLW_3 0x00000008U

#define	HASH_STR_NBLW_4 0x00000010U

#define	HASH_STR_DCAL 0x00000100U

#define	HASH_STR_NBW HASH_STR_NBLW

#define	HASH_STR_NBW_0 HASH_STR_NBLW_0

#define	HASH_STR_NBW_1 HASH_STR_NBLW_1

#define	HASH_STR_NBW_2 HASH_STR_NBLW_2

#define	HASH_STR_NBW_3 HASH_STR_NBLW_3

#define	HASH_STR_NBW_4 HASH_STR_NBLW_4

#define	HASH_IMR_DINIE 0x00000001U

#define	HASH_IMR_DCIE 0x00000002U

#define	HASH_IMR_DINIM HASH_IMR_DINIE

#define	HASH_IMR_DCIM HASH_IMR_DCIE

#define	HASH_SR_DINIS 0x00000001U

#define	HASH_SR_DCIS 0x00000002U

#define	HASH_SR_DMAS 0x00000004U

#define	HASH_SR_BUSY 0x00000008U

#define	I2C_CR1_PE 0x00000001U

#define	I2C_CR1_TXIE 0x00000002U

#define	I2C_CR1_RXIE 0x00000004U

#define	I2C_CR1_ADDRIE 0x00000008U

#define	I2C_CR1_NACKIE 0x00000010U

#define	I2C_CR1_STOPIE 0x00000020U

#define	I2C_CR1_TCIE 0x00000040U

#define	I2C_CR1_ERRIE 0x00000080U

#define	I2C_CR1_DNF 0x00000F00U

#define	I2C_CR1_ANFOFF 0x00001000U

#define	I2C_CR1_TXDMAEN 0x00004000U

#define	I2C_CR1_RXDMAEN 0x00008000U

#define	I2C_CR1_SBC 0x00010000U

#define	I2C_CR1_NOSTRETCH 0x00020000U

#define	I2C_CR1_GCEN 0x00080000U

#define	I2C_CR1_SMBHEN 0x00100000U

#define	I2C_CR1_SMBDEN 0x00200000U

#define	I2C_CR1_ALERTEN 0x00400000U

#define	I2C_CR1_PECEN 0x00800000U

#define	I2C_CR1_DFN I2C_CR1_DNF

#define	I2C_CR2_SADD 0x000003FFU

#define	I2C_CR2_RD_WRN 0x00000400U

#define	I2C_CR2_ADD10 0x00000800U

#define	I2C_CR2_HEAD10R 0x00001000U

#define	I2C_CR2_START 0x00002000U

#define	I2C_CR2_STOP 0x00004000U

#define	I2C_CR2_NACK 0x00008000U

#define	I2C_CR2_NBYTES 0x00FF0000U

#define	I2C_CR2_RELOAD 0x01000000U

#define	I2C_CR2_AUTOEND 0x02000000U

#define	I2C_CR2_PECBYTE 0x04000000U

#define	I2C_OAR1_OA1 0x000003FFU

#define	I2C_OAR1_OA1MODE 0x00000400U

#define	I2C_OAR1_OA1EN 0x00008000U

#define	I2C_OAR2_OA2 0x000000FEU

#define	I2C_OAR2_OA2MSK 0x00000700U

#define	I2C_OAR2_OA2NOMASK 0x00000000U

#define	I2C_OAR2_OA2MASK01 0x00000100U

#define	I2C_OAR2_OA2MASK02 0x00000200U

#define	I2C_OAR2_OA2MASK03 0x00000300U

#define	I2C_OAR2_OA2MASK04 0x00000400U

#define	I2C_OAR2_OA2MASK05 0x00000500U

#define	I2C_OAR2_OA2MASK06 0x00000600U

#define	I2C_OAR2_OA2MASK07 0x00000700U

#define	I2C_OAR2_OA2EN 0x00008000U

#define	I2C_TIMINGR_SCLL 0x000000FFU

#define	I2C_TIMINGR_SCLH 0x0000FF00U

#define	I2C_TIMINGR_SDADEL 0x000F0000U

#define	I2C_TIMINGR_SCLDEL 0x00F00000U

#define	I2C_TIMINGR_PRESC 0xF0000000U

#define	I2C_TIMEOUTR_TIMEOUTA 0x00000FFFU

#define	I2C_TIMEOUTR_TIDLE 0x00001000U

#define	I2C_TIMEOUTR_TIMOUTEN 0x00008000U

#define	I2C_TIMEOUTR_TIMEOUTB 0x0FFF0000U

#define	I2C_TIMEOUTR_TEXTEN 0x80000000U

#define	I2C_ISR_TXE 0x00000001U

#define	I2C_ISR_TXIS 0x00000002U

#define	I2C_ISR_RXNE 0x00000004U

#define	I2C_ISR_ADDR 0x00000008U

#define	I2C_ISR_NACKF 0x00000010U

#define	I2C_ISR_STOPF 0x00000020U

#define	I2C_ISR_TC 0x00000040U

#define	I2C_ISR_TCR 0x00000080U

#define	I2C_ISR_BERR 0x00000100U

#define	I2C_ISR_ARLO 0x00000200U

#define	I2C_ISR_OVR 0x00000400U

#define	I2C_ISR_PECERR 0x00000800U

#define	I2C_ISR_TIMEOUT 0x00001000U

#define	I2C_ISR_ALERT 0x00002000U

#define	I2C_ISR_BUSY 0x00008000U

#define	I2C_ISR_DIR 0x00010000U

#define	I2C_ISR_ADDCODE 0x00FE0000U

#define	I2C_ICR_ADDRCF 0x00000008U

#define	I2C_ICR_NACKCF 0x00000010U

#define	I2C_ICR_STOPCF 0x00000020U

#define	I2C_ICR_BERRCF 0x00000100U

#define	I2C_ICR_ARLOCF 0x00000200U

#define	I2C_ICR_OVRCF 0x00000400U

#define	I2C_ICR_PECCF 0x00000800U

#define	I2C_ICR_TIMOUTCF 0x00001000U

#define	I2C_ICR_ALERTCF 0x00002000U

#define	I2C_PECR_PEC 0x000000FFU

#define	I2C_RXDR_RXDATA 0x000000FFU

#define	I2C_TXDR_TXDATA 0x000000FFU

#define	IWDG_KR_KEY 0xFFFFU

#define	IWDG_PR_PR 0x07U

#define	IWDG_PR_PR_0 0x01U

#define	IWDG_PR_PR_1 0x02U

#define	IWDG_PR_PR_2 0x04U

#define	IWDG_RLR_RL 0x0FFFU

#define	IWDG_SR_PVU 0x01U

#define	IWDG_SR_RVU 0x02U

#define	IWDG_SR_WVU 0x04U

#define	IWDG_WINR_WIN 0x0FFFU

#define	LTDC_SSCR_VSH 0x000007FFU

#define	LTDC_SSCR_HSW 0x0FFF0000U

#define	LTDC_BPCR_AVBP 0x000007FFU

#define	LTDC_BPCR_AHBP 0x0FFF0000U

#define	LTDC_AWCR_AAH 0x000007FFU

#define	LTDC_AWCR_AAW 0x0FFF0000U

#define	LTDC_TWCR_TOTALH 0x000007FFU

#define	LTDC_TWCR_TOTALW 0x0FFF0000U

#define	LTDC_GCR_LTDCEN 0x00000001U

#define	LTDC_GCR_DBW 0x00000070U

#define	LTDC_GCR_DGW 0x00000700U

#define	LTDC_GCR_DRW 0x00007000U

#define	LTDC_GCR_DEN 0x00010000U

#define	LTDC_GCR_PCPOL 0x10000000U

#define	LTDC_GCR_DEPOL 0x20000000U

#define	LTDC_GCR_VSPOL 0x40000000U

#define	LTDC_GCR_HSPOL 0x80000000U

#define	LTDC_GCR_DTEN LTDC_GCR_DEN

#define	LTDC_SRCR_IMR 0x00000001U

#define	LTDC_SRCR_VBR 0x00000002U

#define	LTDC_BCCR_BCBLUE 0x000000FFU

#define	LTDC_BCCR_BCGREEN 0x0000FF00U

#define	LTDC_BCCR_BCRED 0x00FF0000U

#define	LTDC_IER_LIE 0x00000001U

#define	LTDC_IER_FUIE 0x00000002U

#define	LTDC_IER_TERRIE 0x00000004U

#define	LTDC_IER_RRIE 0x00000008U

#define	LTDC_ISR_LIF 0x00000001U

#define	LTDC_ISR_FUIF 0x00000002U

#define	LTDC_ISR_TERRIF 0x00000004U

#define	LTDC_ISR_RRIF 0x00000008U

#define	LTDC_ICR_CLIF 0x00000001U

#define	LTDC_ICR_CFUIF 0x00000002U

#define	LTDC_ICR_CTERRIF 0x00000004U

#define	LTDC_ICR_CRRIF 0x00000008U

#define	LTDC_LIPCR_LIPOS 0x000007FFU

#define	LTDC_CPSR_CYPOS 0x0000FFFFU

#define	LTDC_CPSR_CXPOS 0xFFFF0000U

#define	LTDC_CDSR_VDES 0x00000001U

#define	LTDC_CDSR_HDES 0x00000002U

#define	LTDC_CDSR_VSYNCS 0x00000004U

#define	LTDC_CDSR_HSYNCS 0x00000008U

#define	LTDC_LxCR_LEN 0x00000001U

#define	LTDC_LxCR_COLKEN 0x00000002U

#define	LTDC_LxCR_CLUTEN 0x00000010U

#define	LTDC_LxWHPCR_WHSTPOS 0x00000FFFU

#define	LTDC_LxWHPCR_WHSPPOS 0xFFFF0000U

#define	LTDC_LxWVPCR_WVSTPOS 0x00000FFFU

#define	LTDC_LxWVPCR_WVSPPOS 0xFFFF0000U

#define	LTDC_LxCKCR_CKBLUE 0x000000FFU

#define	LTDC_LxCKCR_CKGREEN 0x0000FF00U

#define	LTDC_LxCKCR_CKRED 0x00FF0000U

#define	LTDC_LxPFCR_PF 0x00000007U

#define	LTDC_LxCACR_CONSTA 0x000000FFU

#define	LTDC_LxDCCR_DCBLUE 0x000000FFU

#define	LTDC_LxDCCR_DCGREEN 0x0000FF00U

#define	LTDC_LxDCCR_DCRED 0x00FF0000U

#define	LTDC_LxDCCR_DCALPHA 0xFF000000U

#define	LTDC_LxBFCR_BF2 0x00000007U

#define	LTDC_LxBFCR_BF1 0x00000700U

#define	LTDC_LxCFBAR_CFBADD 0xFFFFFFFFU

#define	LTDC_LxCFBLR_CFBLL 0x00001FFFU

#define	LTDC_LxCFBLR_CFBP 0x1FFF0000U

#define	LTDC_LxCFBLNR_CFBLNBR 0x000007FFU

#define	LTDC_LxCLUTWR_BLUE 0x000000FFU

#define	LTDC_LxCLUTWR_GREEN 0x0000FF00U

#define	LTDC_LxCLUTWR_RED 0x00FF0000U

#define	LTDC_LxCLUTWR_CLUTADD 0xFF000000U

#define	PWR_CR1_LPDS 0x00000001U

#define	PWR_CR1_PDDS 0x00000002U

#define	PWR_CR1_CSBF 0x00000008U

#define	PWR_CR1_PVDE 0x00000010U

#define	PWR_CR1_PLS 0x000000E0U

#define	PWR_CR1_PLS_0 0x00000020U

#define	PWR_CR1_PLS_1 0x00000040U

#define	PWR_CR1_PLS_2 0x00000080U

#define	PWR_CR1_PLS_LEV0 0x00000000U

#define	PWR_CR1_PLS_LEV1 0x00000020U

#define	PWR_CR1_PLS_LEV2 0x00000040U

#define	PWR_CR1_PLS_LEV3 0x00000060U

#define	PWR_CR1_PLS_LEV4 0x00000080U

#define	PWR_CR1_PLS_LEV5 0x000000A0U

#define	PWR_CR1_PLS_LEV6 0x000000C0U

#define	PWR_CR1_PLS_LEV7 0x000000E0U

#define	PWR_CR1_DBP 0x00000100U

#define	PWR_CR1_FPDS 0x00000200U

#define	PWR_CR1_LPUDS 0x00000400U

#define	PWR_CR1_MRUDS 0x00000800U

#define	PWR_CR1_ADCDC1 0x00002000U

#define	PWR_CR1_VOS 0x0000C000U

#define	PWR_CR1_VOS_0 0x00004000U

#define	PWR_CR1_VOS_1 0x00008000U

#define	PWR_CR1_ODEN 0x00010000U

#define	PWR_CR1_ODSWEN 0x00020000U

#define	PWR_CR1_UDEN 0x000C0000U

#define	PWR_CR1_UDEN_0 0x00040000U

#define	PWR_CR1_UDEN_1 0x00080000U

#define	PWR_CSR1_WUIF 0x00000001U

#define	PWR_CSR1_SBF 0x00000002U

#define	PWR_CSR1_PVDO 0x00000004U

#define	PWR_CSR1_BRR 0x00000008U

#define	PWR_CSR1_EIWUP 0x00000100U

#define	PWR_CSR1_BRE 0x00000200U

#define	PWR_CSR1_VOSRDY 0x00004000U

#define	PWR_CSR1_ODRDY 0x00010000U

#define	PWR_CSR1_ODSWRDY 0x00020000U

#define	PWR_CSR1_UDRDY 0x000C0000U

#define	PWR_CSR1_UDSWRDY PWR_CSR1_UDRDY

#define	PWR_CR2_CWUPF1 0x00000001U

#define	PWR_CR2_CWUPF2 0x00000002U

#define	PWR_CR2_CWUPF3 0x00000004U

#define	PWR_CR2_CWUPF4 0x00000008U

#define	PWR_CR2_CWUPF5 0x00000010U

#define	PWR_CR2_CWUPF6 0x00000020U

#define	PWR_CR2_WUPP1 0x00000100U

#define	PWR_CR2_WUPP2 0x00000200U

#define	PWR_CR2_WUPP3 0x00000400U

#define	PWR_CR2_WUPP4 0x00000800U

#define	PWR_CR2_WUPP5 0x00001000U

#define	PWR_CR2_WUPP6 0x00002000U

#define	PWR_CSR2_WUPF1 0x00000001U

#define	PWR_CSR2_WUPF2 0x00000002U

#define	PWR_CSR2_WUPF3 0x00000004U

#define	PWR_CSR2_WUPF4 0x00000008U

#define	PWR_CSR2_WUPF5 0x00000010U

#define	PWR_CSR2_WUPF6 0x00000020U

#define	PWR_CSR2_EWUP1 0x00000100U

#define	PWR_CSR2_EWUP2 0x00000200U

#define	PWR_CSR2_EWUP3 0x00000400U

#define	PWR_CSR2_EWUP4 0x00000800U

#define	PWR_CSR2_EWUP5 0x00001000U

#define	PWR_CSR2_EWUP6 0x00002000U

#define	QSPI1_V1_0

#define	QUADSPI_CR_EN 0x00000001U

#define	QUADSPI_CR_ABORT 0x00000002U

#define	QUADSPI_CR_DMAEN 0x00000004U

#define	QUADSPI_CR_TCEN 0x00000008U

#define	QUADSPI_CR_SSHIFT 0x00000010U

#define	QUADSPI_CR_DFM 0x00000040U

#define	QUADSPI_CR_FSEL 0x00000080U

#define	QUADSPI_CR_FTHRES 0x00001F00U

#define	QUADSPI_CR_FTHRES_0 0x00000100U

#define	QUADSPI_CR_FTHRES_1 0x00000200U

#define	QUADSPI_CR_FTHRES_2 0x00000400U

#define	QUADSPI_CR_FTHRES_3 0x00000800U

#define	QUADSPI_CR_FTHRES_4 0x00001000U

#define	QUADSPI_CR_TEIE 0x00010000U

#define	QUADSPI_CR_TCIE 0x00020000U

#define	QUADSPI_CR_FTIE 0x00040000U

#define	QUADSPI_CR_SMIE 0x00080000U

#define	QUADSPI_CR_TOIE 0x00100000U

#define	QUADSPI_CR_APMS 0x00400000U

#define	QUADSPI_CR_PMM 0x00800000U

#define	QUADSPI_CR_PRESCALER 0xFF000000U

#define	QUADSPI_CR_PRESCALER_0 0x01000000U

#define	QUADSPI_CR_PRESCALER_1 0x02000000U

#define	QUADSPI_CR_PRESCALER_2 0x04000000U

#define	QUADSPI_CR_PRESCALER_3 0x08000000U

#define	QUADSPI_CR_PRESCALER_4 0x10000000U

#define	QUADSPI_CR_PRESCALER_5 0x20000000U

#define	QUADSPI_CR_PRESCALER_6 0x40000000U

#define	QUADSPI_CR_PRESCALER_7 0x80000000U

#define	QUADSPI_DCR_CKMODE 0x00000001U

#define	QUADSPI_DCR_CSHT 0x00000700U

#define	QUADSPI_DCR_CSHT_0 0x00000100U

#define	QUADSPI_DCR_CSHT_1 0x00000200U

#define	QUADSPI_DCR_CSHT_2 0x00000400U

#define	QUADSPI_DCR_FSIZE 0x001F0000U

#define	QUADSPI_DCR_FSIZE_0 0x00010000U

#define	QUADSPI_DCR_FSIZE_1 0x00020000U

#define	QUADSPI_DCR_FSIZE_2 0x00040000U

#define	QUADSPI_DCR_FSIZE_3 0x00080000U

#define	QUADSPI_DCR_FSIZE_4 0x00100000U

#define	QUADSPI_SR_TEF 0x00000001U

#define	QUADSPI_SR_TCF 0x00000002U

#define	QUADSPI_SR_FTF 0x00000004U

#define	QUADSPI_SR_SMF 0x00000008U

#define	QUADSPI_SR_TOF 0x00000010U

#define	QUADSPI_SR_BUSY 0x00000020U

#define	QUADSPI_SR_FLEVEL 0x00001F00U

#define	QUADSPI_SR_FLEVEL_0 0x00000100U

#define	QUADSPI_SR_FLEVEL_1 0x00000200U

#define	QUADSPI_SR_FLEVEL_2 0x00000400U

#define	QUADSPI_SR_FLEVEL_3 0x00000800U

#define	QUADSPI_SR_FLEVEL_4 0x00001000U

#define	QUADSPI_FCR_CTEF 0x00000001U

#define	QUADSPI_FCR_CTCF 0x00000002U

#define	QUADSPI_FCR_CSMF 0x00000008U

#define	QUADSPI_FCR_CTOF 0x00000010U

#define	QUADSPI_DLR_DL 0xFFFFFFFFU

#define	QUADSPI_CCR_INSTRUCTION 0x000000FFU

#define	QUADSPI_CCR_INSTRUCTION_0 0x00000001U

#define	QUADSPI_CCR_INSTRUCTION_1 0x00000002U

#define	QUADSPI_CCR_INSTRUCTION_2 0x00000004U

#define	QUADSPI_CCR_INSTRUCTION_3 0x00000008U

#define	QUADSPI_CCR_INSTRUCTION_4 0x00000010U

#define	QUADSPI_CCR_INSTRUCTION_5 0x00000020U

#define	QUADSPI_CCR_INSTRUCTION_6 0x00000040U

#define	QUADSPI_CCR_INSTRUCTION_7 0x00000080U

#define	QUADSPI_CCR_IMODE 0x00000300U

#define	QUADSPI_CCR_IMODE_0 0x00000100U

#define	QUADSPI_CCR_IMODE_1 0x00000200U

#define	QUADSPI_CCR_ADMODE 0x00000C00U

#define	QUADSPI_CCR_ADMODE_0 0x00000400U

#define	QUADSPI_CCR_ADMODE_1 0x00000800U

#define	QUADSPI_CCR_ADSIZE 0x00003000U

#define	QUADSPI_CCR_ADSIZE_0 0x00001000U

#define	QUADSPI_CCR_ADSIZE_1 0x00002000U

#define	QUADSPI_CCR_ABMODE 0x0000C000U

#define	QUADSPI_CCR_ABMODE_0 0x00004000U

#define	QUADSPI_CCR_ABMODE_1 0x00008000U

#define	QUADSPI_CCR_ABSIZE 0x00030000U

#define	QUADSPI_CCR_ABSIZE_0 0x00010000U

#define	QUADSPI_CCR_ABSIZE_1 0x00020000U

#define	QUADSPI_CCR_DCYC 0x007C0000U

#define	QUADSPI_CCR_DCYC_0 0x00040000U

#define	QUADSPI_CCR_DCYC_1 0x00080000U

#define	QUADSPI_CCR_DCYC_2 0x00100000U

#define	QUADSPI_CCR_DCYC_3 0x00200000U

#define	QUADSPI_CCR_DCYC_4 0x00400000U

#define	QUADSPI_CCR_DMODE 0x03000000U

#define	QUADSPI_CCR_DMODE_0 0x01000000U

#define	QUADSPI_CCR_DMODE_1 0x02000000U

#define	QUADSPI_CCR_FMODE 0x0C000000U

#define	QUADSPI_CCR_FMODE_0 0x04000000U

#define	QUADSPI_CCR_FMODE_1 0x08000000U

#define	QUADSPI_CCR_SIOO 0x10000000U

#define	QUADSPI_CCR_DHHC 0x40000000U

#define	QUADSPI_CCR_DDRM 0x80000000U

#define	QUADSPI_AR_ADDRESS 0xFFFFFFFFU

#define	QUADSPI_ABR_ALTERNATE 0xFFFFFFFFU

#define	QUADSPI_DR_DATA 0xFFFFFFFFU

#define	QUADSPI_PSMKR_MASK 0xFFFFFFFFU

#define	QUADSPI_PSMAR_MATCH 0xFFFFFFFFU

#define	QUADSPI_PIR_INTERVAL 0x0000FFFFU

#define	QUADSPI_LPTR_TIMEOUT 0x0000FFFFU

#define	RCC_CR_HSION 0x00000001U

#define	RCC_CR_HSIRDY 0x00000002U

#define	RCC_CR_HSITRIM 0x000000F8U

#define	RCC_CR_HSITRIM_0 0x00000008U

#define	RCC_CR_HSITRIM_1 0x00000010U

#define	RCC_CR_HSITRIM_2 0x00000020U

#define	RCC_CR_HSITRIM_3 0x00000040U

#define	RCC_CR_HSITRIM_4 0x00000080U

#define	RCC_CR_HSICAL 0x0000FF00U

#define	RCC_CR_HSICAL_0 0x00000100U

#define	RCC_CR_HSICAL_1 0x00000200U

#define	RCC_CR_HSICAL_2 0x00000400U

#define	RCC_CR_HSICAL_3 0x00000800U

#define	RCC_CR_HSICAL_4 0x00001000U

#define	RCC_CR_HSICAL_5 0x00002000U

#define	RCC_CR_HSICAL_6 0x00004000U

#define	RCC_CR_HSICAL_7 0x00008000U

#define	RCC_CR_HSEON 0x00010000U

#define	RCC_CR_HSERDY 0x00020000U

#define	RCC_CR_HSEBYP 0x00040000U

#define	RCC_CR_CSSON 0x00080000U

#define	RCC_CR_PLLON 0x01000000U

#define	RCC_CR_PLLRDY 0x02000000U

#define	RCC_CR_PLLI2SON 0x04000000U

#define	RCC_CR_PLLI2SRDY 0x08000000U

#define	RCC_CR_PLLSAION 0x10000000U

#define	RCC_CR_PLLSAIRDY 0x20000000U

#define	RCC_PLLCFGR_PLLM 0x0000003FU

#define	RCC_PLLCFGR_PLLM_0 0x00000001U

#define	RCC_PLLCFGR_PLLM_1 0x00000002U

#define	RCC_PLLCFGR_PLLM_2 0x00000004U

#define	RCC_PLLCFGR_PLLM_3 0x00000008U

#define	RCC_PLLCFGR_PLLM_4 0x00000010U

#define	RCC_PLLCFGR_PLLM_5 0x00000020U

#define	RCC_PLLCFGR_PLLN 0x00007FC0U

#define	RCC_PLLCFGR_PLLN_0 0x00000040U

#define	RCC_PLLCFGR_PLLN_1 0x00000080U

#define	RCC_PLLCFGR_PLLN_2 0x00000100U

#define	RCC_PLLCFGR_PLLN_3 0x00000200U

#define	RCC_PLLCFGR_PLLN_4 0x00000400U

#define	RCC_PLLCFGR_PLLN_5 0x00000800U

#define	RCC_PLLCFGR_PLLN_6 0x00001000U

#define	RCC_PLLCFGR_PLLN_7 0x00002000U

#define	RCC_PLLCFGR_PLLN_8 0x00004000U

#define	RCC_PLLCFGR_PLLP 0x00030000U

#define	RCC_PLLCFGR_PLLP_0 0x00010000U

#define	RCC_PLLCFGR_PLLP_1 0x00020000U

#define	RCC_PLLCFGR_PLLSRC 0x00400000U

#define	RCC_PLLCFGR_PLLSRC_HSE 0x00400000U

#define	RCC_PLLCFGR_PLLSRC_HSI 0x00000000U

#define	RCC_PLLCFGR_PLLQ 0x0F000000U

#define	RCC_PLLCFGR_PLLQ_0 0x01000000U

#define	RCC_PLLCFGR_PLLQ_1 0x02000000U

#define	RCC_PLLCFGR_PLLQ_2 0x04000000U

#define	RCC_PLLCFGR_PLLQ_3 0x08000000U

#define	RCC_CFGR_SW 0x00000003U

#define	RCC_CFGR_SW_0 0x00000001U

#define	RCC_CFGR_SW_1 0x00000002U

#define	RCC_CFGR_SW_HSI 0x00000000U

#define	RCC_CFGR_SW_HSE 0x00000001U

#define	RCC_CFGR_SW_PLL 0x00000002U

#define	RCC_CFGR_SWS 0x0000000CU

#define	RCC_CFGR_SWS_0 0x00000004U

#define	RCC_CFGR_SWS_1 0x00000008U

#define	RCC_CFGR_SWS_HSI 0x00000000U

#define	RCC_CFGR_SWS_HSE 0x00000004U

#define	RCC_CFGR_SWS_PLL 0x00000008U

#define	RCC_CFGR_HPRE 0x000000F0U

#define	RCC_CFGR_HPRE_0 0x00000010U

#define	RCC_CFGR_HPRE_1 0x00000020U

#define	RCC_CFGR_HPRE_2 0x00000040U

#define	RCC_CFGR_HPRE_3 0x00000080U

#define	RCC_CFGR_HPRE_DIV1 0x00000000U

#define	RCC_CFGR_HPRE_DIV2 0x00000080U

#define	RCC_CFGR_HPRE_DIV4 0x00000090U

#define	RCC_CFGR_HPRE_DIV8 0x000000A0U

#define	RCC_CFGR_HPRE_DIV16 0x000000B0U

#define	RCC_CFGR_HPRE_DIV64 0x000000C0U

#define	RCC_CFGR_HPRE_DIV128 0x000000D0U

#define	RCC_CFGR_HPRE_DIV256 0x000000E0U

#define	RCC_CFGR_HPRE_DIV512 0x000000F0U

#define	RCC_CFGR_PPRE1 0x00001C00U

#define	RCC_CFGR_PPRE1_0 0x00000400U

#define	RCC_CFGR_PPRE1_1 0x00000800U

#define	RCC_CFGR_PPRE1_2 0x00001000U

#define	RCC_CFGR_PPRE1_DIV1 0x00000000U

#define	RCC_CFGR_PPRE1_DIV2 0x00001000U

#define	RCC_CFGR_PPRE1_DIV4 0x00001400U

#define	RCC_CFGR_PPRE1_DIV8 0x00001800U

#define	RCC_CFGR_PPRE1_DIV16 0x00001C00U

#define	RCC_CFGR_PPRE2 0x0000E000U

#define	RCC_CFGR_PPRE2_0 0x00002000U

#define	RCC_CFGR_PPRE2_1 0x00004000U

#define	RCC_CFGR_PPRE2_2 0x00008000U

#define	RCC_CFGR_PPRE2_DIV1 0x00000000U

#define	RCC_CFGR_PPRE2_DIV2 0x00008000U

#define	RCC_CFGR_PPRE2_DIV4 0x0000A000U

#define	RCC_CFGR_PPRE2_DIV8 0x0000C000U

#define	RCC_CFGR_PPRE2_DIV16 0x0000E000U

#define	RCC_CFGR_RTCPRE 0x001F0000U

#define	RCC_CFGR_RTCPRE_0 0x00010000U

#define	RCC_CFGR_RTCPRE_1 0x00020000U

#define	RCC_CFGR_RTCPRE_2 0x00040000U

#define	RCC_CFGR_RTCPRE_3 0x00080000U

#define	RCC_CFGR_RTCPRE_4 0x00100000U

#define	RCC_CFGR_MCO1 0x00600000U

#define	RCC_CFGR_MCO1_0 0x00200000U

#define	RCC_CFGR_MCO1_1 0x00400000U

#define	RCC_CFGR_I2SSRC 0x00800000U

#define	RCC_CFGR_MCO1PRE 0x07000000U

#define	RCC_CFGR_MCO1PRE_0 0x01000000U

#define	RCC_CFGR_MCO1PRE_1 0x02000000U

#define	RCC_CFGR_MCO1PRE_2 0x04000000U

#define	RCC_CFGR_MCO2PRE 0x38000000U

#define	RCC_CFGR_MCO2PRE_0 0x08000000U

#define	RCC_CFGR_MCO2PRE_1 0x10000000U

#define	RCC_CFGR_MCO2PRE_2 0x20000000U

#define	RCC_CFGR_MCO2 0xC0000000U

#define	RCC_CFGR_MCO2_0 0x40000000U

#define	RCC_CFGR_MCO2_1 0x80000000U

#define	RCC_CIR_LSIRDYF 0x00000001U

#define	RCC_CIR_LSERDYF 0x00000002U

#define	RCC_CIR_HSIRDYF 0x00000004U

#define	RCC_CIR_HSERDYF 0x00000008U

#define	RCC_CIR_PLLRDYF 0x00000010U

#define	RCC_CIR_PLLI2SRDYF 0x00000020U

#define	RCC_CIR_PLLSAIRDYF 0x00000040U

#define	RCC_CIR_CSSF 0x00000080U

#define	RCC_CIR_LSIRDYIE 0x00000100U

#define	RCC_CIR_LSERDYIE 0x00000200U

#define	RCC_CIR_HSIRDYIE 0x00000400U

#define	RCC_CIR_HSERDYIE 0x00000800U

#define	RCC_CIR_PLLRDYIE 0x00001000U

#define	RCC_CIR_PLLI2SRDYIE 0x00002000U

#define	RCC_CIR_PLLSAIRDYIE 0x00004000U

#define	RCC_CIR_LSIRDYC 0x00010000U

#define	RCC_CIR_LSERDYC 0x00020000U

#define	RCC_CIR_HSIRDYC 0x00040000U

#define	RCC_CIR_HSERDYC 0x00080000U

#define	RCC_CIR_PLLRDYC 0x00100000U

#define	RCC_CIR_PLLI2SRDYC 0x00200000U

#define	RCC_CIR_PLLSAIRDYC 0x00400000U

#define	RCC_CIR_CSSC 0x00800000U

#define	RCC_AHB1RSTR_GPIOARST 0x00000001U

#define	RCC_AHB1RSTR_GPIOBRST 0x00000002U

#define	RCC_AHB1RSTR_GPIOCRST 0x00000004U

#define	RCC_AHB1RSTR_GPIODRST 0x00000008U

#define	RCC_AHB1RSTR_GPIOERST 0x00000010U

#define	RCC_AHB1RSTR_GPIOFRST 0x00000020U

#define	RCC_AHB1RSTR_GPIOGRST 0x00000040U

#define	RCC_AHB1RSTR_GPIOHRST 0x00000080U

#define	RCC_AHB1RSTR_GPIOIRST 0x00000100U

#define	RCC_AHB1RSTR_GPIOJRST 0x00000200U

#define	RCC_AHB1RSTR_GPIOKRST 0x00000400U

#define	RCC_AHB1RSTR_CRCRST 0x00001000U

#define	RCC_AHB1RSTR_DMA1RST 0x00200000U

#define	RCC_AHB1RSTR_DMA2RST 0x00400000U

#define	RCC_AHB1RSTR_DMA2DRST 0x00800000U

#define	RCC_AHB1RSTR_ETHMACRST 0x02000000U

#define	RCC_AHB1RSTR_OTGHRST 0x20000000U

#define	RCC_AHB2RSTR_DCMIRST 0x00000001U

#define	RCC_AHB2RSTR_CRYPRST 0x00000010U

#define	RCC_AHB2RSTR_HASHRST 0x00000020U

#define	RCC_AHB2RSTR_RNGRST 0x00000040U

#define	RCC_AHB2RSTR_OTGFSRST 0x00000080U

#define	RCC_AHB3RSTR_FMCRST 0x00000001U

#define	RCC_AHB3RSTR_QSPIRST 0x00000002U

#define	RCC_APB1RSTR_TIM2RST 0x00000001U

#define	RCC_APB1RSTR_TIM3RST 0x00000002U

#define	RCC_APB1RSTR_TIM4RST 0x00000004U

#define	RCC_APB1RSTR_TIM5RST 0x00000008U

#define	RCC_APB1RSTR_TIM6RST 0x00000010U

#define	RCC_APB1RSTR_TIM7RST 0x00000020U

#define	RCC_APB1RSTR_TIM12RST 0x00000040U

#define	RCC_APB1RSTR_TIM13RST 0x00000080U

#define	RCC_APB1RSTR_TIM14RST 0x00000100U

#define	RCC_APB1RSTR_LPTIM1RST 0x00000200U

#define	RCC_APB1RSTR_WWDGRST 0x00000800U

#define	RCC_APB1RSTR_SPI2RST 0x00004000U

#define	RCC_APB1RSTR_SPI3RST 0x00008000U

#define	RCC_APB1RSTR_SPDIFRXRST 0x00010000U

#define	RCC_APB1RSTR_USART2RST 0x00020000U

#define	RCC_APB1RSTR_USART3RST 0x00040000U

#define	RCC_APB1RSTR_UART4RST 0x00080000U

#define	RCC_APB1RSTR_UART5RST 0x00100000U

#define	RCC_APB1RSTR_I2C1RST 0x00200000U

#define	RCC_APB1RSTR_I2C2RST 0x00400000U

#define	RCC_APB1RSTR_I2C3RST 0x00800000U

#define	RCC_APB1RSTR_I2C4RST 0x01000000U

#define	RCC_APB1RSTR_CAN1RST 0x02000000U

#define	RCC_APB1RSTR_CAN2RST 0x04000000U

#define	RCC_APB1RSTR_CECRST 0x08000000U

#define	RCC_APB1RSTR_PWRRST 0x10000000U

#define	RCC_APB1RSTR_DACRST 0x20000000U

#define	RCC_APB1RSTR_UART7RST 0x40000000U

#define	RCC_APB1RSTR_UART8RST 0x80000000U

#define	RCC_APB2RSTR_TIM1RST 0x00000001U

#define	RCC_APB2RSTR_TIM8RST 0x00000002U

#define	RCC_APB2RSTR_USART1RST 0x00000010U

#define	RCC_APB2RSTR_USART6RST 0x00000020U

#define	RCC_APB2RSTR_ADCRST 0x00000100U

#define	RCC_APB2RSTR_SDMMC1RST 0x00000800U

#define	RCC_APB2RSTR_SPI1RST 0x00001000U

#define	RCC_APB2RSTR_SPI4RST 0x00002000U

#define	RCC_APB2RSTR_SYSCFGRST 0x00004000U

#define	RCC_APB2RSTR_TIM9RST 0x00010000U

#define	RCC_APB2RSTR_TIM10RST 0x00020000U

#define	RCC_APB2RSTR_TIM11RST 0x00040000U

#define	RCC_APB2RSTR_SPI5RST 0x00100000U

#define	RCC_APB2RSTR_SPI6RST 0x00200000U

#define	RCC_APB2RSTR_SAI1RST 0x00400000U

#define	RCC_APB2RSTR_SAI2RST 0x00800000U

#define	RCC_APB2RSTR_LTDCRST 0x04000000U

#define	RCC_AHB1ENR_GPIOAEN 0x00000001U

#define	RCC_AHB1ENR_GPIOBEN 0x00000002U

#define	RCC_AHB1ENR_GPIOCEN 0x00000004U

#define	RCC_AHB1ENR_GPIODEN 0x00000008U

#define	RCC_AHB1ENR_GPIOEEN 0x00000010U

#define	RCC_AHB1ENR_GPIOFEN 0x00000020U

#define	RCC_AHB1ENR_GPIOGEN 0x00000040U

#define	RCC_AHB1ENR_GPIOHEN 0x00000080U

#define	RCC_AHB1ENR_GPIOIEN 0x00000100U

#define	RCC_AHB1ENR_GPIOJEN 0x00000200U

#define	RCC_AHB1ENR_GPIOKEN 0x00000400U

#define	RCC_AHB1ENR_CRCEN 0x00001000U

#define	RCC_AHB1ENR_BKPSRAMEN 0x00040000U

#define	RCC_AHB1ENR_DTCMRAMEN 0x00100000U

#define	RCC_AHB1ENR_DMA1EN 0x00200000U

#define	RCC_AHB1ENR_DMA2EN 0x00400000U

#define	RCC_AHB1ENR_DMA2DEN 0x00800000U

#define	RCC_AHB1ENR_ETHMACEN 0x02000000U

#define	RCC_AHB1ENR_ETHMACTXEN 0x04000000U

#define	RCC_AHB1ENR_ETHMACRXEN 0x08000000U

#define	RCC_AHB1ENR_ETHMACPTPEN 0x10000000U

#define	RCC_AHB1ENR_OTGHSEN 0x20000000U

#define	RCC_AHB1ENR_OTGHSULPIEN 0x40000000U

#define	RCC_AHB2ENR_DCMIEN 0x00000001U

#define	RCC_AHB2ENR_CRYPEN 0x00000010U

#define	RCC_AHB2ENR_HASHEN 0x00000020U

#define	RCC_AHB2ENR_RNGEN 0x00000040U

#define	RCC_AHB2ENR_OTGFSEN 0x00000080U

#define	RCC_AHB3ENR_FMCEN 0x00000001U

#define	RCC_AHB3ENR_QSPIEN 0x00000002U

#define	RCC_APB1ENR_TIM2EN 0x00000001U

#define	RCC_APB1ENR_TIM3EN 0x00000002U

#define	RCC_APB1ENR_TIM4EN 0x00000004U

#define	RCC_APB1ENR_TIM5EN 0x00000008U

#define	RCC_APB1ENR_TIM6EN 0x00000010U

#define	RCC_APB1ENR_TIM7EN 0x00000020U

#define	RCC_APB1ENR_TIM12EN 0x00000040U

#define	RCC_APB1ENR_TIM13EN 0x00000080U

#define	RCC_APB1ENR_TIM14EN 0x00000100U

#define	RCC_APB1ENR_LPTIM1EN 0x00000200U

#define	RCC_APB1ENR_WWDGEN 0x00000800U

#define	RCC_APB1ENR_SPI2EN 0x00004000U

#define	RCC_APB1ENR_SPI3EN 0x00008000U

#define	RCC_APB1ENR_SPDIFRXEN 0x00010000U

#define	RCC_APB1ENR_USART2EN 0x00020000U

#define	RCC_APB1ENR_USART3EN 0x00040000U

#define	RCC_APB1ENR_UART4EN 0x00080000U

#define	RCC_APB1ENR_UART5EN 0x00100000U

#define	RCC_APB1ENR_I2C1EN 0x00200000U

#define	RCC_APB1ENR_I2C2EN 0x00400000U

#define	RCC_APB1ENR_I2C3EN 0x00800000U

#define	RCC_APB1ENR_I2C4EN 0x01000000U

#define	RCC_APB1ENR_CAN1EN 0x02000000U

#define	RCC_APB1ENR_CAN2EN 0x04000000U

#define	RCC_APB1ENR_CECEN 0x08000000U

#define	RCC_APB1ENR_PWREN 0x10000000U

#define	RCC_APB1ENR_DACEN 0x20000000U

#define	RCC_APB1ENR_UART7EN 0x40000000U

#define	RCC_APB1ENR_UART8EN 0x80000000U

#define	RCC_APB2ENR_TIM1EN 0x00000001U

#define	RCC_APB2ENR_TIM8EN 0x00000002U

#define	RCC_APB2ENR_USART1EN 0x00000010U

#define	RCC_APB2ENR_USART6EN 0x00000020U

#define	RCC_APB2ENR_ADC1EN 0x00000100U

#define	RCC_APB2ENR_ADC2EN 0x00000200U

#define	RCC_APB2ENR_ADC3EN 0x00000400U

#define	RCC_APB2ENR_SDMMC1EN 0x00000800U

#define	RCC_APB2ENR_SPI1EN 0x00001000U

#define	RCC_APB2ENR_SPI4EN 0x00002000U

#define	RCC_APB2ENR_SYSCFGEN 0x00004000U

#define	RCC_APB2ENR_TIM9EN 0x00010000U

#define	RCC_APB2ENR_TIM10EN 0x00020000U

#define	RCC_APB2ENR_TIM11EN 0x00040000U

#define	RCC_APB2ENR_SPI5EN 0x00100000U

#define	RCC_APB2ENR_SPI6EN 0x00200000U

#define	RCC_APB2ENR_SAI1EN 0x00400000U

#define	RCC_APB2ENR_SAI2EN 0x00800000U

#define	RCC_APB2ENR_LTDCEN 0x04000000U

#define	RCC_AHB1LPENR_GPIOALPEN 0x00000001U

#define	RCC_AHB1LPENR_GPIOBLPEN 0x00000002U

#define	RCC_AHB1LPENR_GPIOCLPEN 0x00000004U

#define	RCC_AHB1LPENR_GPIODLPEN 0x00000008U

#define	RCC_AHB1LPENR_GPIOELPEN 0x00000010U

#define	RCC_AHB1LPENR_GPIOFLPEN 0x00000020U

#define	RCC_AHB1LPENR_GPIOGLPEN 0x00000040U

#define	RCC_AHB1LPENR_GPIOHLPEN 0x00000080U

#define	RCC_AHB1LPENR_GPIOILPEN 0x00000100U

#define	RCC_AHB1LPENR_GPIOJLPEN 0x00000200U

#define	RCC_AHB1LPENR_GPIOKLPEN 0x00000400U

#define	RCC_AHB1LPENR_CRCLPEN 0x00001000U

#define	RCC_AHB1LPENR_AXILPEN 0x00002000U

#define	RCC_AHB1LPENR_FLITFLPEN 0x00008000U

#define	RCC_AHB1LPENR_SRAM1LPEN 0x00010000U

#define	RCC_AHB1LPENR_SRAM2LPEN 0x00020000U

#define	RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U

#define	RCC_AHB1LPENR_DTCMLPEN 0x00100000U

#define	RCC_AHB1LPENR_DMA1LPEN 0x00200000U

#define	RCC_AHB1LPENR_DMA2LPEN 0x00400000U

#define	RCC_AHB1LPENR_DMA2DLPEN 0x00800000U

#define	RCC_AHB1LPENR_ETHMACLPEN 0x02000000U

#define	RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U

#define	RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U

#define	RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U

#define	RCC_AHB1LPENR_OTGHSLPEN 0x20000000U

#define	RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U

#define	RCC_AHB2LPENR_DCMILPEN 0x00000001U

#define	RCC_AHB2LPENR_CRYPLPEN 0x00000010U

#define	RCC_AHB2LPENR_HASHLPEN 0x00000020U

#define	RCC_AHB2LPENR_RNGLPEN 0x00000040U

#define	RCC_AHB2LPENR_OTGFSLPEN 0x00000080U

#define	RCC_AHB3LPENR_FMCLPEN 0x00000001U

#define	RCC_AHB3LPENR_QSPILPEN 0x00000002U

#define	RCC_APB1LPENR_TIM2LPEN 0x00000001U

#define	RCC_APB1LPENR_TIM3LPEN 0x00000002U

#define	RCC_APB1LPENR_TIM4LPEN 0x00000004U

#define	RCC_APB1LPENR_TIM5LPEN 0x00000008U

#define	RCC_APB1LPENR_TIM6LPEN 0x00000010U

#define	RCC_APB1LPENR_TIM7LPEN 0x00000020U

#define	RCC_APB1LPENR_TIM12LPEN 0x00000040U

#define	RCC_APB1LPENR_TIM13LPEN 0x00000080U

#define	RCC_APB1LPENR_TIM14LPEN 0x00000100U

#define	RCC_APB1LPENR_LPTIM1LPEN 0x00000200U

#define	RCC_APB1LPENR_WWDGLPEN 0x00000800U

#define	RCC_APB1LPENR_SPI2LPEN 0x00004000U

#define	RCC_APB1LPENR_SPI3LPEN 0x00008000U

#define	RCC_APB1LPENR_SPDIFRXLPEN 0x00010000U

#define	RCC_APB1LPENR_USART2LPEN 0x00020000U

#define	RCC_APB1LPENR_USART3LPEN 0x00040000U

#define	RCC_APB1LPENR_UART4LPEN 0x00080000U

#define	RCC_APB1LPENR_UART5LPEN 0x00100000U

#define	RCC_APB1LPENR_I2C1LPEN 0x00200000U

#define	RCC_APB1LPENR_I2C2LPEN 0x00400000U

#define	RCC_APB1LPENR_I2C3LPEN 0x00800000U

#define	RCC_APB1LPENR_I2C4LPEN 0x01000000U

#define	RCC_APB1LPENR_CAN1LPEN 0x02000000U

#define	RCC_APB1LPENR_CAN2LPEN 0x04000000U

#define	RCC_APB1LPENR_CECLPEN 0x08000000U

#define	RCC_APB1LPENR_PWRLPEN 0x10000000U

#define	RCC_APB1LPENR_DACLPEN 0x20000000U

#define	RCC_APB1LPENR_UART7LPEN 0x40000000U

#define	RCC_APB1LPENR_UART8LPEN 0x80000000U

#define	RCC_APB2LPENR_TIM1LPEN 0x00000001U

#define	RCC_APB2LPENR_TIM8LPEN 0x00000002U

#define	RCC_APB2LPENR_USART1LPEN 0x00000010U

#define	RCC_APB2LPENR_USART6LPEN 0x00000020U

#define	RCC_APB2LPENR_ADC1LPEN 0x00000100U

#define	RCC_APB2LPENR_ADC2LPEN 0x00000200U

#define	RCC_APB2LPENR_ADC3LPEN 0x00000400U

#define	RCC_APB2LPENR_SDMMC1LPEN 0x00000800U

#define	RCC_APB2LPENR_SPI1LPEN 0x00001000U

#define	RCC_APB2LPENR_SPI4LPEN 0x00002000U

#define	RCC_APB2LPENR_SYSCFGLPEN 0x00004000U

#define	RCC_APB2LPENR_TIM9LPEN 0x00010000U

#define	RCC_APB2LPENR_TIM10LPEN 0x00020000U

#define	RCC_APB2LPENR_TIM11LPEN 0x00040000U

#define	RCC_APB2LPENR_SPI5LPEN 0x00100000U

#define	RCC_APB2LPENR_SPI6LPEN 0x00200000U

#define	RCC_APB2LPENR_SAI1LPEN 0x00400000U

#define	RCC_APB2LPENR_SAI2LPEN 0x00800000U

#define	RCC_APB2LPENR_LTDCLPEN 0x04000000U

#define	RCC_BDCR_LSEON 0x00000001U

#define	RCC_BDCR_LSERDY 0x00000002U

#define	RCC_BDCR_LSEBYP 0x00000004U

#define	RCC_BDCR_LSEDRV 0x00000018U

#define	RCC_BDCR_LSEDRV_0 0x00000008U

#define	RCC_BDCR_LSEDRV_1 0x00000010U

#define	RCC_BDCR_RTCSEL 0x00000300U

#define	RCC_BDCR_RTCSEL_0 0x00000100U

#define	RCC_BDCR_RTCSEL_1 0x00000200U

#define	RCC_BDCR_RTCEN 0x00008000U

#define	RCC_BDCR_BDRST 0x00010000U

#define	RCC_CSR_LSION 0x00000001U

#define	RCC_CSR_LSIRDY 0x00000002U

#define	RCC_CSR_RMVF 0x01000000U

#define	RCC_CSR_BORRSTF 0x02000000U

#define	RCC_CSR_PINRSTF 0x04000000U

#define	RCC_CSR_PORRSTF 0x08000000U

#define	RCC_CSR_SFTRSTF 0x10000000U

#define	RCC_CSR_IWDGRSTF 0x20000000U

#define	RCC_CSR_WWDGRSTF 0x40000000U

#define	RCC_CSR_LPWRRSTF 0x80000000U

#define	RCC_SSCGR_MODPER 0x00001FFFU

#define	RCC_SSCGR_INCSTEP 0x0FFFE000U

#define	RCC_SSCGR_SPREADSEL 0x40000000U

#define	RCC_SSCGR_SSCGEN 0x80000000U

#define	RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U

#define	RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U

#define	RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U

#define	RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U

#define	RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U

#define	RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U

#define	RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U

#define	RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U

#define	RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U

#define	RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U

#define	RCC_PLLI2SCFGR_PLLI2SP 0x00030000U

#define	RCC_PLLI2SCFGR_PLLI2SP_0 0x00010000U

#define	RCC_PLLI2SCFGR_PLLI2SP_1 0x00020000U

#define	RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U

#define	RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U

#define	RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U

#define	RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U

#define	RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U

#define	RCC_PLLI2SCFGR_PLLI2SR 0x70000000U

#define	RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U

#define	RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U

#define	RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U

#define	RCC_PLLSAICFGR_PLLSAIN 0x00007FC0U

#define	RCC_PLLSAICFGR_PLLSAIN_0 0x00000040U

#define	RCC_PLLSAICFGR_PLLSAIN_1 0x00000080U

#define	RCC_PLLSAICFGR_PLLSAIN_2 0x00000100U

#define	RCC_PLLSAICFGR_PLLSAIN_3 0x00000200U

#define	RCC_PLLSAICFGR_PLLSAIN_4 0x00000400U

#define	RCC_PLLSAICFGR_PLLSAIN_5 0x00000800U

#define	RCC_PLLSAICFGR_PLLSAIN_6 0x00001000U

#define	RCC_PLLSAICFGR_PLLSAIN_7 0x00002000U

#define	RCC_PLLSAICFGR_PLLSAIN_8 0x00004000U

#define	RCC_PLLSAICFGR_PLLSAIP 0x00030000U

#define	RCC_PLLSAICFGR_PLLSAIP_0 0x00010000U

#define	RCC_PLLSAICFGR_PLLSAIP_1 0x00020000U

#define	RCC_PLLSAICFGR_PLLSAIQ 0x0F000000U

#define	RCC_PLLSAICFGR_PLLSAIQ_0 0x01000000U

#define	RCC_PLLSAICFGR_PLLSAIQ_1 0x02000000U

#define	RCC_PLLSAICFGR_PLLSAIQ_2 0x04000000U

#define	RCC_PLLSAICFGR_PLLSAIQ_3 0x08000000U

#define	RCC_PLLSAICFGR_PLLSAIR 0x70000000U

#define	RCC_PLLSAICFGR_PLLSAIR_0 0x10000000U

#define	RCC_PLLSAICFGR_PLLSAIR_1 0x20000000U

#define	RCC_PLLSAICFGR_PLLSAIR_2 0x40000000U

#define	RCC_DCKCFGR1_PLLI2SDIVQ 0x0000001FU

#define	RCC_DCKCFGR1_PLLI2SDIVQ_0 0x00000001U

#define	RCC_DCKCFGR1_PLLI2SDIVQ_1 0x00000002U

#define	RCC_DCKCFGR1_PLLI2SDIVQ_2 0x00000004U

#define	RCC_DCKCFGR1_PLLI2SDIVQ_3 0x00000008U

#define	RCC_DCKCFGR1_PLLI2SDIVQ_4 0x00000010U

#define	RCC_DCKCFGR1_PLLSAIDIVQ 0x00001F00U

#define	RCC_DCKCFGR1_PLLSAIDIVQ_0 0x00000100U

#define	RCC_DCKCFGR1_PLLSAIDIVQ_1 0x00000200U

#define	RCC_DCKCFGR1_PLLSAIDIVQ_2 0x00000400U

#define	RCC_DCKCFGR1_PLLSAIDIVQ_3 0x00000800U

#define	RCC_DCKCFGR1_PLLSAIDIVQ_4 0x00001000U

#define	RCC_DCKCFGR1_PLLSAIDIVR 0x00030000U

#define	RCC_DCKCFGR1_PLLSAIDIVR_0 0x00010000U

#define	RCC_DCKCFGR1_PLLSAIDIVR_1 0x00020000U

#define	RCC_DCKCFGR1_SAI1SEL 0x00300000U

#define	RCC_DCKCFGR1_SAI1SEL_0 0x00100000U

#define	RCC_DCKCFGR1_SAI1SEL_1 0x00200000U

#define	RCC_DCKCFGR1_SAI2SEL 0x00C00000U

#define	RCC_DCKCFGR1_SAI2SEL_0 0x00400000U

#define	RCC_DCKCFGR1_SAI2SEL_1 0x00800000U

#define	RCC_DCKCFGR1_TIMPRE 0x01000000U

#define	RCC_DCKCFGR2_USART1SEL 0x00000003U

#define	RCC_DCKCFGR2_USART1SEL_0 0x00000001U

#define	RCC_DCKCFGR2_USART1SEL_1 0x00000002U

#define	RCC_DCKCFGR2_USART2SEL 0x0000000CU

#define	RCC_DCKCFGR2_USART2SEL_0 0x00000004U

#define	RCC_DCKCFGR2_USART2SEL_1 0x00000008U

#define	RCC_DCKCFGR2_USART3SEL 0x00000030U

#define	RCC_DCKCFGR2_USART3SEL_0 0x00000010U

#define	RCC_DCKCFGR2_USART3SEL_1 0x00000020U

#define	RCC_DCKCFGR2_UART4SEL 0x000000C0U

#define	RCC_DCKCFGR2_UART4SEL_0 0x00000040U

#define	RCC_DCKCFGR2_UART4SEL_1 0x00000080U

#define	RCC_DCKCFGR2_UART5SEL 0x00000300U

#define	RCC_DCKCFGR2_UART5SEL_0 0x00000100U

#define	RCC_DCKCFGR2_UART5SEL_1 0x00000200U

#define	RCC_DCKCFGR2_USART6SEL 0x00000C00U

#define	RCC_DCKCFGR2_USART6SEL_0 0x00000400U

#define	RCC_DCKCFGR2_USART6SEL_1 0x00000800U

#define	RCC_DCKCFGR2_UART7SEL 0x00003000U

#define	RCC_DCKCFGR2_UART7SEL_0 0x00001000U

#define	RCC_DCKCFGR2_UART7SEL_1 0x00002000U

#define	RCC_DCKCFGR2_UART8SEL 0x0000C000U

#define	RCC_DCKCFGR2_UART8SEL_0 0x00004000U

#define	RCC_DCKCFGR2_UART8SEL_1 0x00008000U

#define	RCC_DCKCFGR2_I2C1SEL 0x00030000U

#define	RCC_DCKCFGR2_I2C1SEL_0 0x00010000U

#define	RCC_DCKCFGR2_I2C1SEL_1 0x00020000U

#define	RCC_DCKCFGR2_I2C2SEL 0x000C0000U

#define	RCC_DCKCFGR2_I2C2SEL_0 0x00040000U

#define	RCC_DCKCFGR2_I2C2SEL_1 0x00080000U

#define	RCC_DCKCFGR2_I2C3SEL 0x00300000U

#define	RCC_DCKCFGR2_I2C3SEL_0 0x00100000U

#define	RCC_DCKCFGR2_I2C3SEL_1 0x00200000U

#define	RCC_DCKCFGR2_I2C4SEL 0x00C00000U

#define	RCC_DCKCFGR2_I2C4SEL_0 0x00400000U

#define	RCC_DCKCFGR2_I2C4SEL_1 0x00800000U

#define	RCC_DCKCFGR2_LPTIM1SEL 0x03000000U

#define	RCC_DCKCFGR2_LPTIM1SEL_0 0x01000000U

#define	RCC_DCKCFGR2_LPTIM1SEL_1 0x02000000U

#define	RCC_DCKCFGR2_CECSEL 0x04000000U

#define	RCC_DCKCFGR2_CK48MSEL 0x08000000U

#define	RCC_DCKCFGR2_SDMMC1SEL 0x10000000U

#define	RNG_CR_RNGEN 0x00000004U

#define	RNG_CR_IE 0x00000008U

#define	RNG_SR_DRDY 0x00000001U

#define	RNG_SR_CECS 0x00000002U

#define	RNG_SR_SECS 0x00000004U

#define	RNG_SR_CEIS 0x00000020U

#define	RNG_SR_SEIS 0x00000040U

#define	RTC_TR_PM 0x00400000U

#define	RTC_TR_HT 0x00300000U

#define	RTC_TR_HT_0 0x00100000U

#define	RTC_TR_HT_1 0x00200000U

#define	RTC_TR_HU 0x000F0000U

#define	RTC_TR_HU_0 0x00010000U

#define	RTC_TR_HU_1 0x00020000U

#define	RTC_TR_HU_2 0x00040000U

#define	RTC_TR_HU_3 0x00080000U

#define	RTC_TR_MNT 0x00007000U

#define	RTC_TR_MNT_0 0x00001000U

#define	RTC_TR_MNT_1 0x00002000U

#define	RTC_TR_MNT_2 0x00004000U

#define	RTC_TR_MNU 0x00000F00U

#define	RTC_TR_MNU_0 0x00000100U

#define	RTC_TR_MNU_1 0x00000200U

#define	RTC_TR_MNU_2 0x00000400U

#define	RTC_TR_MNU_3 0x00000800U

#define	RTC_TR_ST 0x00000070U

#define	RTC_TR_ST_0 0x00000010U

#define	RTC_TR_ST_1 0x00000020U

#define	RTC_TR_ST_2 0x00000040U

#define	RTC_TR_SU 0x0000000FU

#define	RTC_TR_SU_0 0x00000001U

#define	RTC_TR_SU_1 0x00000002U

#define	RTC_TR_SU_2 0x00000004U

#define	RTC_TR_SU_3 0x00000008U

#define	RTC_DR_YT 0x00F00000U

#define	RTC_DR_YT_0 0x00100000U

#define	RTC_DR_YT_1 0x00200000U

#define	RTC_DR_YT_2 0x00400000U

#define	RTC_DR_YT_3 0x00800000U

#define	RTC_DR_YU 0x000F0000U

#define	RTC_DR_YU_0 0x00010000U

#define	RTC_DR_YU_1 0x00020000U

#define	RTC_DR_YU_2 0x00040000U

#define	RTC_DR_YU_3 0x00080000U

#define	RTC_DR_WDU 0x0000E000U

#define	RTC_DR_WDU_0 0x00002000U

#define	RTC_DR_WDU_1 0x00004000U

#define	RTC_DR_WDU_2 0x00008000U

#define	RTC_DR_MT 0x00001000U

#define	RTC_DR_MU 0x00000F00U

#define	RTC_DR_MU_0 0x00000100U

#define	RTC_DR_MU_1 0x00000200U

#define	RTC_DR_MU_2 0x00000400U

#define	RTC_DR_MU_3 0x00000800U

#define	RTC_DR_DT 0x00000030U

#define	RTC_DR_DT_0 0x00000010U

#define	RTC_DR_DT_1 0x00000020U

#define	RTC_DR_DU 0x0000000FU

#define	RTC_DR_DU_0 0x00000001U

#define	RTC_DR_DU_1 0x00000002U

#define	RTC_DR_DU_2 0x00000004U

#define	RTC_DR_DU_3 0x00000008U

#define	RTC_CR_ITSE 0x01000000U

#define	RTC_CR_COE 0x00800000U

#define	RTC_CR_OSEL 0x00600000U

#define	RTC_CR_OSEL_0 0x00200000U

#define	RTC_CR_OSEL_1 0x00400000U

#define	RTC_CR_POL 0x00100000U

#define	RTC_CR_COSEL 0x00080000U

#define	RTC_CR_BCK 0x00040000U

#define	RTC_CR_SUB1H 0x00020000U

#define	RTC_CR_ADD1H 0x00010000U

#define	RTC_CR_TSIE 0x00008000U

#define	RTC_CR_WUTIE 0x00004000U

#define	RTC_CR_ALRBIE 0x00002000U

#define	RTC_CR_ALRAIE 0x00001000U

#define	RTC_CR_TSE 0x00000800U

#define	RTC_CR_WUTE 0x00000400U

#define	RTC_CR_ALRBE 0x00000200U

#define	RTC_CR_ALRAE 0x00000100U

#define	RTC_CR_FMT 0x00000040U

#define	RTC_CR_BYPSHAD 0x00000020U

#define	RTC_CR_REFCKON 0x00000010U

#define	RTC_CR_TSEDGE 0x00000008U

#define	RTC_CR_WUCKSEL 0x00000007U

#define	RTC_CR_WUCKSEL_0 0x00000001U

#define	RTC_CR_WUCKSEL_1 0x00000002U

#define	RTC_CR_WUCKSEL_2 0x00000004U

#define	RTC_ISR_ITSF 0x00020000U

#define	RTC_ISR_RECALPF 0x00010000U

#define	RTC_ISR_TAMP3F 0x00008000U

#define	RTC_ISR_TAMP2F 0x00004000U

#define	RTC_ISR_TAMP1F 0x00002000U

#define	RTC_ISR_TSOVF 0x00001000U

#define	RTC_ISR_TSF 0x00000800U

#define	RTC_ISR_WUTF 0x00000400U

#define	RTC_ISR_ALRBF 0x00000200U

#define	RTC_ISR_ALRAF 0x00000100U

#define	RTC_ISR_INIT 0x00000080U

#define	RTC_ISR_INITF 0x00000040U

#define	RTC_ISR_RSF 0x00000020U

#define	RTC_ISR_INITS 0x00000010U

#define	RTC_ISR_SHPF 0x00000008U

#define	RTC_ISR_WUTWF 0x00000004U

#define	RTC_ISR_ALRBWF 0x00000002U

#define	RTC_ISR_ALRAWF 0x00000001U

#define	RTC_PRER_PREDIV_A 0x007F0000U

#define	RTC_PRER_PREDIV_S 0x00007FFFU

#define	RTC_WUTR_WUT 0x0000FFFFU

#define	RTC_ALRMAR_MSK4 0x80000000U

#define	RTC_ALRMAR_WDSEL 0x40000000U

#define	RTC_ALRMAR_DT 0x30000000U

#define	RTC_ALRMAR_DT_0 0x10000000U

#define	RTC_ALRMAR_DT_1 0x20000000U

#define	RTC_ALRMAR_DU 0x0F000000U

#define	RTC_ALRMAR_DU_0 0x01000000U

#define	RTC_ALRMAR_DU_1 0x02000000U

#define	RTC_ALRMAR_DU_2 0x04000000U

#define	RTC_ALRMAR_DU_3 0x08000000U

#define	RTC_ALRMAR_MSK3 0x00800000U

#define	RTC_ALRMAR_PM 0x00400000U

#define	RTC_ALRMAR_HT 0x00300000U

#define	RTC_ALRMAR_HT_0 0x00100000U

#define	RTC_ALRMAR_HT_1 0x00200000U

#define	RTC_ALRMAR_HU 0x000F0000U

#define	RTC_ALRMAR_HU_0 0x00010000U

#define	RTC_ALRMAR_HU_1 0x00020000U

#define	RTC_ALRMAR_HU_2 0x00040000U

#define	RTC_ALRMAR_HU_3 0x00080000U

#define	RTC_ALRMAR_MSK2 0x00008000U

#define	RTC_ALRMAR_MNT 0x00007000U

#define	RTC_ALRMAR_MNT_0 0x00001000U

#define	RTC_ALRMAR_MNT_1 0x00002000U

#define	RTC_ALRMAR_MNT_2 0x00004000U

#define	RTC_ALRMAR_MNU 0x00000F00U

#define	RTC_ALRMAR_MNU_0 0x00000100U

#define	RTC_ALRMAR_MNU_1 0x00000200U

#define	RTC_ALRMAR_MNU_2 0x00000400U

#define	RTC_ALRMAR_MNU_3 0x00000800U

#define	RTC_ALRMAR_MSK1 0x00000080U

#define	RTC_ALRMAR_ST 0x00000070U

#define	RTC_ALRMAR_ST_0 0x00000010U

#define	RTC_ALRMAR_ST_1 0x00000020U

#define	RTC_ALRMAR_ST_2 0x00000040U

#define	RTC_ALRMAR_SU 0x0000000FU

#define	RTC_ALRMAR_SU_0 0x00000001U

#define	RTC_ALRMAR_SU_1 0x00000002U

#define	RTC_ALRMAR_SU_2 0x00000004U

#define	RTC_ALRMAR_SU_3 0x00000008U

#define	RTC_ALRMBR_MSK4 0x80000000U

#define	RTC_ALRMBR_WDSEL 0x40000000U

#define	RTC_ALRMBR_DT 0x30000000U

#define	RTC_ALRMBR_DT_0 0x10000000U

#define	RTC_ALRMBR_DT_1 0x20000000U

#define	RTC_ALRMBR_DU 0x0F000000U

#define	RTC_ALRMBR_DU_0 0x01000000U

#define	RTC_ALRMBR_DU_1 0x02000000U

#define	RTC_ALRMBR_DU_2 0x04000000U

#define	RTC_ALRMBR_DU_3 0x08000000U

#define	RTC_ALRMBR_MSK3 0x00800000U

#define	RTC_ALRMBR_PM 0x00400000U

#define	RTC_ALRMBR_HT 0x00300000U

#define	RTC_ALRMBR_HT_0 0x00100000U

#define	RTC_ALRMBR_HT_1 0x00200000U

#define	RTC_ALRMBR_HU 0x000F0000U

#define	RTC_ALRMBR_HU_0 0x00010000U

#define	RTC_ALRMBR_HU_1 0x00020000U

#define	RTC_ALRMBR_HU_2 0x00040000U

#define	RTC_ALRMBR_HU_3 0x00080000U

#define	RTC_ALRMBR_MSK2 0x00008000U

#define	RTC_ALRMBR_MNT 0x00007000U

#define	RTC_ALRMBR_MNT_0 0x00001000U

#define	RTC_ALRMBR_MNT_1 0x00002000U

#define	RTC_ALRMBR_MNT_2 0x00004000U

#define	RTC_ALRMBR_MNU 0x00000F00U

#define	RTC_ALRMBR_MNU_0 0x00000100U

#define	RTC_ALRMBR_MNU_1 0x00000200U

#define	RTC_ALRMBR_MNU_2 0x00000400U

#define	RTC_ALRMBR_MNU_3 0x00000800U

#define	RTC_ALRMBR_MSK1 0x00000080U

#define	RTC_ALRMBR_ST 0x00000070U

#define	RTC_ALRMBR_ST_0 0x00000010U

#define	RTC_ALRMBR_ST_1 0x00000020U

#define	RTC_ALRMBR_ST_2 0x00000040U

#define	RTC_ALRMBR_SU 0x0000000FU

#define	RTC_ALRMBR_SU_0 0x00000001U

#define	RTC_ALRMBR_SU_1 0x00000002U

#define	RTC_ALRMBR_SU_2 0x00000004U

#define	RTC_ALRMBR_SU_3 0x00000008U

#define	RTC_WPR_KEY 0x000000FFU

#define	RTC_SSR_SS 0x0000FFFFU

#define	RTC_SHIFTR_SUBFS 0x00007FFFU

#define	RTC_SHIFTR_ADD1S 0x80000000U

#define	RTC_TSTR_PM 0x00400000U

#define	RTC_TSTR_HT 0x00300000U

#define	RTC_TSTR_HT_0 0x00100000U

#define	RTC_TSTR_HT_1 0x00200000U

#define	RTC_TSTR_HU 0x000F0000U

#define	RTC_TSTR_HU_0 0x00010000U

#define	RTC_TSTR_HU_1 0x00020000U

#define	RTC_TSTR_HU_2 0x00040000U

#define	RTC_TSTR_HU_3 0x00080000U

#define	RTC_TSTR_MNT 0x00007000U

#define	RTC_TSTR_MNT_0 0x00001000U

#define	RTC_TSTR_MNT_1 0x00002000U

#define	RTC_TSTR_MNT_2 0x00004000U

#define	RTC_TSTR_MNU 0x00000F00U

#define	RTC_TSTR_MNU_0 0x00000100U

#define	RTC_TSTR_MNU_1 0x00000200U

#define	RTC_TSTR_MNU_2 0x00000400U

#define	RTC_TSTR_MNU_3 0x00000800U

#define	RTC_TSTR_ST 0x00000070U

#define	RTC_TSTR_ST_0 0x00000010U

#define	RTC_TSTR_ST_1 0x00000020U

#define	RTC_TSTR_ST_2 0x00000040U

#define	RTC_TSTR_SU 0x0000000FU

#define	RTC_TSTR_SU_0 0x00000001U

#define	RTC_TSTR_SU_1 0x00000002U

#define	RTC_TSTR_SU_2 0x00000004U

#define	RTC_TSTR_SU_3 0x00000008U

#define	RTC_TSDR_WDU 0x0000E000U

#define	RTC_TSDR_WDU_0 0x00002000U

#define	RTC_TSDR_WDU_1 0x00004000U

#define	RTC_TSDR_WDU_2 0x00008000U

#define	RTC_TSDR_MT 0x00001000U

#define	RTC_TSDR_MU 0x00000F00U

#define	RTC_TSDR_MU_0 0x00000100U

#define	RTC_TSDR_MU_1 0x00000200U

#define	RTC_TSDR_MU_2 0x00000400U

#define	RTC_TSDR_MU_3 0x00000800U

#define	RTC_TSDR_DT 0x00000030U

#define	RTC_TSDR_DT_0 0x00000010U

#define	RTC_TSDR_DT_1 0x00000020U

#define	RTC_TSDR_DU 0x0000000FU

#define	RTC_TSDR_DU_0 0x00000001U

#define	RTC_TSDR_DU_1 0x00000002U

#define	RTC_TSDR_DU_2 0x00000004U

#define	RTC_TSDR_DU_3 0x00000008U

#define	RTC_TSSSR_SS 0x0000FFFFU

#define	RTC_CALR_CALP 0x00008000U

#define	RTC_CALR_CALW8 0x00004000U

#define	RTC_CALR_CALW16 0x00002000U

#define	RTC_CALR_CALM 0x000001FFU

#define	RTC_CALR_CALM_0 0x00000001U

#define	RTC_CALR_CALM_1 0x00000002U

#define	RTC_CALR_CALM_2 0x00000004U

#define	RTC_CALR_CALM_3 0x00000008U

#define	RTC_CALR_CALM_4 0x00000010U

#define	RTC_CALR_CALM_5 0x00000020U

#define	RTC_CALR_CALM_6 0x00000040U

#define	RTC_CALR_CALM_7 0x00000080U

#define	RTC_CALR_CALM_8 0x00000100U

#define	RTC_TAMPCR_TAMP3MF 0x01000000U

#define	RTC_TAMPCR_TAMP3NOERASE 0x00800000U

#define	RTC_TAMPCR_TAMP3IE 0x00400000U

#define	RTC_TAMPCR_TAMP2MF 0x00200000U

#define	RTC_TAMPCR_TAMP2NOERASE 0x00100000U

#define	RTC_TAMPCR_TAMP2IE 0x00080000U

#define	RTC_TAMPCR_TAMP1MF 0x00040000U

#define	RTC_TAMPCR_TAMP1NOERASE 0x00020000U

#define	RTC_TAMPCR_TAMP1IE 0x00010000U

#define	RTC_TAMPCR_TAMPPUDIS 0x00008000U

#define	RTC_TAMPCR_TAMPPRCH 0x00006000U

#define	RTC_TAMPCR_TAMPPRCH_0 0x00002000U

#define	RTC_TAMPCR_TAMPPRCH_1 0x00004000U

#define	RTC_TAMPCR_TAMPFLT 0x00001800U

#define	RTC_TAMPCR_TAMPFLT_0 0x00000800U

#define	RTC_TAMPCR_TAMPFLT_1 0x00001000U

#define	RTC_TAMPCR_TAMPFREQ 0x00000700U

#define	RTC_TAMPCR_TAMPFREQ_0 0x00000100U

#define	RTC_TAMPCR_TAMPFREQ_1 0x00000200U

#define	RTC_TAMPCR_TAMPFREQ_2 0x00000400U

#define	RTC_TAMPCR_TAMPTS 0x00000080U

#define	RTC_TAMPCR_TAMP3TRG 0x00000040U

#define	RTC_TAMPCR_TAMP3E 0x00000020U

#define	RTC_TAMPCR_TAMP2TRG 0x00000010U

#define	RTC_TAMPCR_TAMP2E 0x00000008U

#define	RTC_TAMPCR_TAMPIE 0x00000004U

#define	RTC_TAMPCR_TAMP1TRG 0x00000002U

#define	RTC_TAMPCR_TAMP1E 0x00000001U

#define	RTC_TAMPCR_TAMP3_TRG RTC_TAMPCR_TAMP3TRG

#define	RTC_TAMPCR_TAMP2_TRG RTC_TAMPCR_TAMP2TRG

#define	RTC_TAMPCR_TAMP1_TRG RTC_TAMPCR_TAMP1TRG

#define	RTC_ALRMASSR_MASKSS 0x0F000000U

#define	RTC_ALRMASSR_MASKSS_0 0x01000000U

#define	RTC_ALRMASSR_MASKSS_1 0x02000000U

#define	RTC_ALRMASSR_MASKSS_2 0x04000000U

#define	RTC_ALRMASSR_MASKSS_3 0x08000000U

#define	RTC_ALRMASSR_SS 0x00007FFFU

#define	RTC_ALRMBSSR_MASKSS 0x0F000000U

#define	RTC_ALRMBSSR_MASKSS_0 0x01000000U

#define	RTC_ALRMBSSR_MASKSS_1 0x02000000U

#define	RTC_ALRMBSSR_MASKSS_2 0x04000000U

#define	RTC_ALRMBSSR_MASKSS_3 0x08000000U

#define	RTC_ALRMBSSR_SS 0x00007FFFU

#define	RTC_OR_TSINSEL 0x00000006U

#define	RTC_OR_TSINSEL_0 0x00000002U

#define	RTC_OR_TSINSEL_1 0x00000004U

#define	RTC_OR_ALARMTYPE 0x00000008U

#define	RTC_BKP0R 0xFFFFFFFFU

#define	RTC_BKP1R 0xFFFFFFFFU

#define	RTC_BKP2R 0xFFFFFFFFU

#define	RTC_BKP3R 0xFFFFFFFFU

#define	RTC_BKP4R 0xFFFFFFFFU

#define	RTC_BKP5R 0xFFFFFFFFU

#define	RTC_BKP6R 0xFFFFFFFFU

#define	RTC_BKP7R 0xFFFFFFFFU

#define	RTC_BKP8R 0xFFFFFFFFU

#define	RTC_BKP9R 0xFFFFFFFFU

#define	RTC_BKP10R 0xFFFFFFFFU

#define	RTC_BKP11R 0xFFFFFFFFU

#define	RTC_BKP12R 0xFFFFFFFFU

#define	RTC_BKP13R 0xFFFFFFFFU

#define	RTC_BKP14R 0xFFFFFFFFU

#define	RTC_BKP15R 0xFFFFFFFFU

#define	RTC_BKP16R 0xFFFFFFFFU

#define	RTC_BKP17R 0xFFFFFFFFU

#define	RTC_BKP18R 0xFFFFFFFFU

#define	RTC_BKP19R 0xFFFFFFFFU

#define	RTC_BKP20R 0xFFFFFFFFU

#define	RTC_BKP21R 0xFFFFFFFFU

#define	RTC_BKP22R 0xFFFFFFFFU

#define	RTC_BKP23R 0xFFFFFFFFU

#define	RTC_BKP24R 0xFFFFFFFFU

#define	RTC_BKP25R 0xFFFFFFFFU

#define	RTC_BKP26R 0xFFFFFFFFU

#define	RTC_BKP27R 0xFFFFFFFFU

#define	RTC_BKP28R 0xFFFFFFFFU

#define	RTC_BKP29R 0xFFFFFFFFU

#define	RTC_BKP30R 0xFFFFFFFFU

#define	RTC_BKP31R 0xFFFFFFFFU

#define	RTC_BKP_NUMBER 0x00000020U

#define	SAI_GCR_SYNCIN 0x00000003U

#define	SAI_GCR_SYNCIN_0 0x00000001U

#define	SAI_GCR_SYNCIN_1 0x00000002U

#define	SAI_GCR_SYNCOUT 0x00000030U

#define	SAI_GCR_SYNCOUT_0 0x00000010U

#define	SAI_GCR_SYNCOUT_1 0x00000020U

#define	SAI_xCR1_MODE 0x00000003U

#define	SAI_xCR1_MODE_0 0x00000001U

#define	SAI_xCR1_MODE_1 0x00000002U

#define	SAI_xCR1_PRTCFG 0x0000000CU

#define	SAI_xCR1_PRTCFG_0 0x00000004U

#define	SAI_xCR1_PRTCFG_1 0x00000008U

#define	SAI_xCR1_DS 0x000000E0U

#define	SAI_xCR1_DS_0 0x00000020U

#define	SAI_xCR1_DS_1 0x00000040U

#define	SAI_xCR1_DS_2 0x00000080U

#define	SAI_xCR1_LSBFIRST 0x00000100U

#define	SAI_xCR1_CKSTR 0x00000200U

#define	SAI_xCR1_SYNCEN 0x00000C00U

#define	SAI_xCR1_SYNCEN_0 0x00000400U

#define	SAI_xCR1_SYNCEN_1 0x00000800U

#define	SAI_xCR1_MONO 0x00001000U

#define	SAI_xCR1_OUTDRIV 0x00002000U

#define	SAI_xCR1_SAIEN 0x00010000U

#define	SAI_xCR1_DMAEN 0x00020000U

#define	SAI_xCR1_NODIV 0x00080000U

#define	SAI_xCR1_MCKDIV 0x00F00000U

#define	SAI_xCR1_MCKDIV_0 0x00100000U

#define	SAI_xCR1_MCKDIV_1 0x00200000U

#define	SAI_xCR1_MCKDIV_2 0x00400000U

#define	SAI_xCR1_MCKDIV_3 0x00800000U

#define	SAI_xCR2_FTH 0x00000007U

#define	SAI_xCR2_FTH_0 0x00000001U

#define	SAI_xCR2_FTH_1 0x00000002U

#define	SAI_xCR2_FTH_2 0x00000004U

#define	SAI_xCR2_FFLUSH 0x00000008U

#define	SAI_xCR2_TRIS 0x00000010U

#define	SAI_xCR2_MUTE 0x00000020U

#define	SAI_xCR2_MUTEVAL 0x00000040U

#define	SAI_xCR2_MUTECNT 0x00001F80U

#define	SAI_xCR2_MUTECNT_0 0x00000080U

#define	SAI_xCR2_MUTECNT_1 0x00000100U

#define	SAI_xCR2_MUTECNT_2 0x00000200U

#define	SAI_xCR2_MUTECNT_3 0x00000400U

#define	SAI_xCR2_MUTECNT_4 0x00000800U

#define	SAI_xCR2_MUTECNT_5 0x00001000U

#define	SAI_xCR2_CPL 0x00002000U

#define	SAI_xCR2_COMP 0x0000C000U

#define	SAI_xCR2_COMP_0 0x00004000U

#define	SAI_xCR2_COMP_1 0x00008000U

#define	SAI_xFRCR_FRL 0x000000FFU

#define	SAI_xFRCR_FRL_0 0x00000001U

#define	SAI_xFRCR_FRL_1 0x00000002U

#define	SAI_xFRCR_FRL_2 0x00000004U

#define	SAI_xFRCR_FRL_3 0x00000008U

#define	SAI_xFRCR_FRL_4 0x00000010U

#define	SAI_xFRCR_FRL_5 0x00000020U

#define	SAI_xFRCR_FRL_6 0x00000040U

#define	SAI_xFRCR_FRL_7 0x00000080U

#define	SAI_xFRCR_FSALL 0x00007F00U

#define	SAI_xFRCR_FSALL_0 0x00000100U

#define	SAI_xFRCR_FSALL_1 0x00000200U

#define	SAI_xFRCR_FSALL_2 0x00000400U

#define	SAI_xFRCR_FSALL_3 0x00000800U

#define	SAI_xFRCR_FSALL_4 0x00001000U

#define	SAI_xFRCR_FSALL_5 0x00002000U

#define	SAI_xFRCR_FSALL_6 0x00004000U

#define	SAI_xFRCR_FSDEF 0x00010000U

#define	SAI_xFRCR_FSPOL 0x00020000U

#define	SAI_xFRCR_FSOFF 0x00040000U

#define	SAI_xFRCR_FSPO SAI_xFRCR_FSPOL

#define	SAI_xSLOTR_FBOFF 0x0000001FU

#define	SAI_xSLOTR_FBOFF_0 0x00000001U

#define	SAI_xSLOTR_FBOFF_1 0x00000002U

#define	SAI_xSLOTR_FBOFF_2 0x00000004U

#define	SAI_xSLOTR_FBOFF_3 0x00000008U

#define	SAI_xSLOTR_FBOFF_4 0x00000010U

#define	SAI_xSLOTR_SLOTSZ 0x000000C0U

#define	SAI_xSLOTR_SLOTSZ_0 0x00000040U

#define	SAI_xSLOTR_SLOTSZ_1 0x00000080U

#define	SAI_xSLOTR_NBSLOT 0x00000F00U

#define	SAI_xSLOTR_NBSLOT_0 0x00000100U

#define	SAI_xSLOTR_NBSLOT_1 0x00000200U

#define	SAI_xSLOTR_NBSLOT_2 0x00000400U

#define	SAI_xSLOTR_NBSLOT_3 0x00000800U

#define	SAI_xSLOTR_SLOTEN 0xFFFF0000U

#define	SAI_xIMR_OVRUDRIE 0x00000001U

#define	SAI_xIMR_MUTEDETIE 0x00000002U

#define	SAI_xIMR_WCKCFGIE 0x00000004U

#define	SAI_xIMR_FREQIE 0x00000008U

#define	SAI_xIMR_CNRDYIE 0x00000010U

#define	SAI_xIMR_AFSDETIE 0x00000020U

#define	SAI_xIMR_LFSDETIE 0x00000040U

#define	SAI_xSR_OVRUDR 0x00000001U

#define	SAI_xSR_MUTEDET 0x00000002U

#define	SAI_xSR_WCKCFG 0x00000004U

#define	SAI_xSR_FREQ 0x00000008U

#define	SAI_xSR_CNRDY 0x00000010U

#define	SAI_xSR_AFSDET 0x00000020U

#define	SAI_xSR_LFSDET 0x00000040U

#define	SAI_xSR_FLVL 0x00070000U

#define	SAI_xSR_FLVL_0 0x00010000U

#define	SAI_xSR_FLVL_1 0x00020000U

#define	SAI_xSR_FLVL_2 0x00040000U

#define	SAI_xCLRFR_COVRUDR 0x00000001U

#define	SAI_xCLRFR_CMUTEDET 0x00000002U

#define	SAI_xCLRFR_CWCKCFG 0x00000004U

#define	SAI_xCLRFR_CFREQ 0x00000008U

#define	SAI_xCLRFR_CCNRDY 0x00000010U

#define	SAI_xCLRFR_CAFSDET 0x00000020U

#define	SAI_xCLRFR_CLFSDET 0x00000040U

#define	SAI_xDR_DATA 0xFFFFFFFFU

#define	SPDIFRX_CR_SPDIFEN 0x00000003U

#define	SPDIFRX_CR_RXDMAEN 0x00000004U

#define	SPDIFRX_CR_RXSTEO 0x00000008U

#define	SPDIFRX_CR_DRFMT 0x00000030U

#define	SPDIFRX_CR_PMSK 0x00000040U

#define	SPDIFRX_CR_VMSK 0x00000080U

#define	SPDIFRX_CR_CUMSK 0x00000100U

#define	SPDIFRX_CR_PTMSK 0x00000200U

#define	SPDIFRX_CR_CBDMAEN 0x00000400U

#define	SPDIFRX_CR_CHSEL 0x00000800U

#define	SPDIFRX_CR_NBTR 0x00003000U

#define	SPDIFRX_CR_WFA 0x00004000U

#define	SPDIFRX_CR_INSEL 0x00070000U

#define	SPDIFRX_IMR_RXNEIE 0x00000001U

#define	SPDIFRX_IMR_CSRNEIE 0x00000002U

#define	SPDIFRX_IMR_PERRIE 0x00000004U

#define	SPDIFRX_IMR_OVRIE 0x00000008U

#define	SPDIFRX_IMR_SBLKIE 0x00000010U

#define	SPDIFRX_IMR_SYNCDIE 0x00000020U

#define	SPDIFRX_IMR_IFEIE 0x00000040U

#define	SPDIFRX_SR_RXNE 0x00000001U

#define	SPDIFRX_SR_CSRNE 0x00000002U

#define	SPDIFRX_SR_PERR 0x00000004U

#define	SPDIFRX_SR_OVR 0x00000008U

#define	SPDIFRX_SR_SBD 0x00000010U

#define	SPDIFRX_SR_SYNCD 0x00000020U

#define	SPDIFRX_SR_FERR 0x00000040U

#define	SPDIFRX_SR_SERR 0x00000080U

#define	SPDIFRX_SR_TERR 0x00000100U

#define	SPDIFRX_SR_WIDTH5 0x7FFF0000U

#define	SPDIFRX_IFCR_PERRCF 0x00000004U

#define	SPDIFRX_IFCR_OVRCF 0x00000008U

#define	SPDIFRX_IFCR_SBDCF 0x00000010U

#define	SPDIFRX_IFCR_SYNCDCF 0x00000020U

#define	SPDIFRX_DR0_DR 0x00FFFFFFU

#define	SPDIFRX_DR0_PE 0x01000000U

#define	SPDIFRX_DR0_V 0x02000000U

#define	SPDIFRX_DR0_U 0x04000000U

#define	SPDIFRX_DR0_C 0x08000000U

#define	SPDIFRX_DR0_PT 0x30000000U

#define	SPDIFRX_DR1_DR 0xFFFFFF00U

#define	SPDIFRX_DR1_PT 0x00000030U

#define	SPDIFRX_DR1_C 0x00000008U

#define	SPDIFRX_DR1_U 0x00000004U

#define	SPDIFRX_DR1_V 0x00000002U

#define	SPDIFRX_DR1_PE 0x00000001U

#define	SPDIFRX_DR1_DRNL1 0xFFFF0000U

#define	SPDIFRX_DR1_DRNL2 0x0000FFFFU

#define	SPDIFRX_CSR_USR 0x0000FFFFU

#define	SPDIFRX_CSR_CS 0x00FF0000U

#define	SPDIFRX_CSR_SOB 0x01000000U

#define	SPDIFRX_DIR_THI 0x000013FFU

#define	SPDIFRX_DIR_TLO 0x1FFF0000U

#define	SDMMC_POWER_PWRCTRL 0x03U

#define	SDMMC_POWER_PWRCTRL_0 0x01U

#define	SDMMC_POWER_PWRCTRL_1 0x02U

#define	SDMMC_CLKCR_CLKDIV 0x00FFU

#define	SDMMC_CLKCR_CLKEN 0x0100U

#define	SDMMC_CLKCR_PWRSAV 0x0200U

#define	SDMMC_CLKCR_BYPASS 0x0400U

#define	SDMMC_CLKCR_WIDBUS 0x1800U

#define	SDMMC_CLKCR_WIDBUS_0 0x0800U

#define	SDMMC_CLKCR_WIDBUS_1 0x1000U

#define	SDMMC_CLKCR_NEGEDGE 0x2000U

#define	SDMMC_CLKCR_HWFC_EN 0x4000U

#define	SDMMC_ARG_CMDARG 0xFFFFFFFFU

#define	SDMMC_CMD_CMDINDEX 0x003FU

#define	SDMMC_CMD_WAITRESP 0x00C0U

#define	SDMMC_CMD_WAITRESP_0 0x0040U

#define	SDMMC_CMD_WAITRESP_1 0x0080U

#define	SDMMC_CMD_WAITINT 0x0100U

#define	SDMMC_CMD_WAITPEND 0x0200U

#define	SDMMC_CMD_CPSMEN 0x0400U

#define	SDMMC_CMD_SDIOSUSPEND 0x0800U

#define	SDMMC_RESPCMD_RESPCMD 0x3FU

#define	SDMMC_RESP0_CARDSTATUS0 0xFFFFFFFFU

#define	SDMMC_RESP1_CARDSTATUS1 0xFFFFFFFFU

#define	SDMMC_RESP2_CARDSTATUS2 0xFFFFFFFFU

#define	SDMMC_RESP3_CARDSTATUS3 0xFFFFFFFFU

#define	SDMMC_RESP4_CARDSTATUS4 0xFFFFFFFFU

#define	SDMMC_DTIMER_DATATIME 0xFFFFFFFFU

#define	SDMMC_DLEN_DATALENGTH 0x01FFFFFFU

#define	SDMMC_DCTRL_DTEN 0x0001U

#define	SDMMC_DCTRL_DTDIR 0x0002U

#define	SDMMC_DCTRL_DTMODE 0x0004U

#define	SDMMC_DCTRL_DMAEN 0x0008U

#define	SDMMC_DCTRL_DBLOCKSIZE 0x00F0U

#define	SDMMC_DCTRL_DBLOCKSIZE_0 0x0010U

#define	SDMMC_DCTRL_DBLOCKSIZE_1 0x0020U

#define	SDMMC_DCTRL_DBLOCKSIZE_2 0x0040U

#define	SDMMC_DCTRL_DBLOCKSIZE_3 0x0080U

#define	SDMMC_DCTRL_RWSTART 0x0100U

#define	SDMMC_DCTRL_RWSTOP 0x0200U

#define	SDMMC_DCTRL_RWMOD 0x0400U

#define	SDMMC_DCTRL_SDIOEN 0x0800U

#define	SDMMC_DCOUNT_DATACOUNT 0x01FFFFFFU

#define	SDMMC_STA_CCRCFAIL 0x00000001U

#define	SDMMC_STA_DCRCFAIL 0x00000002U

#define	SDMMC_STA_CTIMEOUT 0x00000004U

#define	SDMMC_STA_DTIMEOUT 0x00000008U

#define	SDMMC_STA_TXUNDERR 0x00000010U

#define	SDMMC_STA_RXOVERR 0x00000020U

#define	SDMMC_STA_CMDREND 0x00000040U

#define	SDMMC_STA_CMDSENT 0x00000080U

#define	SDMMC_STA_DATAEND 0x00000100U

#define	SDMMC_STA_DBCKEND 0x00000400U

#define	SDMMC_STA_CMDACT 0x00000800U

#define	SDMMC_STA_TXACT 0x00001000U

#define	SDMMC_STA_RXACT 0x00002000U

#define	SDMMC_STA_TXFIFOHE 0x00004000U

#define	SDMMC_STA_RXFIFOHF 0x00008000U

#define	SDMMC_STA_TXFIFOF 0x00010000U

#define	SDMMC_STA_RXFIFOF 0x00020000U

#define	SDMMC_STA_TXFIFOE 0x00040000U

#define	SDMMC_STA_RXFIFOE 0x00080000U

#define	SDMMC_STA_TXDAVL 0x00100000U

#define	SDMMC_STA_RXDAVL 0x00200000U

#define	SDMMC_STA_SDIOIT 0x00400000U

#define	SDMMC_ICR_CCRCFAILC 0x00000001U

#define	SDMMC_ICR_DCRCFAILC 0x00000002U

#define	SDMMC_ICR_CTIMEOUTC 0x00000004U

#define	SDMMC_ICR_DTIMEOUTC 0x00000008U

#define	SDMMC_ICR_TXUNDERRC 0x00000010U

#define	SDMMC_ICR_RXOVERRC 0x00000020U

#define	SDMMC_ICR_CMDRENDC 0x00000040U

#define	SDMMC_ICR_CMDSENTC 0x00000080U

#define	SDMMC_ICR_DATAENDC 0x00000100U

#define	SDMMC_ICR_DBCKENDC 0x00000400U

#define	SDMMC_ICR_SDIOITC 0x00400000U

#define	SDMMC_MASK_CCRCFAILIE 0x00000001U

#define	SDMMC_MASK_DCRCFAILIE 0x00000002U

#define	SDMMC_MASK_CTIMEOUTIE 0x00000004U

#define	SDMMC_MASK_DTIMEOUTIE 0x00000008U

#define	SDMMC_MASK_TXUNDERRIE 0x00000010U

#define	SDMMC_MASK_RXOVERRIE 0x00000020U

#define	SDMMC_MASK_CMDRENDIE 0x00000040U

#define	SDMMC_MASK_CMDSENTIE 0x00000080U

#define	SDMMC_MASK_DATAENDIE 0x00000100U

#define	SDMMC_MASK_DBCKENDIE 0x00000400U

#define	SDMMC_MASK_CMDACTIE 0x00000800U

#define	SDMMC_MASK_TXACTIE 0x00001000U

#define	SDMMC_MASK_RXACTIE 0x00002000U

#define	SDMMC_MASK_TXFIFOHEIE 0x00004000U

#define	SDMMC_MASK_RXFIFOHFIE 0x00008000U

#define	SDMMC_MASK_TXFIFOFIE 0x00010000U

#define	SDMMC_MASK_RXFIFOFIE 0x00020000U

#define	SDMMC_MASK_TXFIFOEIE 0x00040000U

#define	SDMMC_MASK_RXFIFOEIE 0x00080000U

#define	SDMMC_MASK_TXDAVLIE 0x00100000U

#define	SDMMC_MASK_RXDAVLIE 0x00200000U

#define	SDMMC_MASK_SDIOITIE 0x00400000U

#define	SDMMC_FIFOCNT_FIFOCOUNT 0x00FFFFFFU

#define	SDMMC_FIFO_FIFODATA 0xFFFFFFFFU

#define	SPI_CR1_CPHA 0x00000001U

#define	SPI_CR1_CPOL 0x00000002U

#define	SPI_CR1_MSTR 0x00000004U

#define	SPI_CR1_BR 0x00000038U

#define	SPI_CR1_BR_0 0x00000008U

#define	SPI_CR1_BR_1 0x00000010U

#define	SPI_CR1_BR_2 0x00000020U

#define	SPI_CR1_SPE 0x00000040U

#define	SPI_CR1_LSBFIRST 0x00000080U

#define	SPI_CR1_SSI 0x00000100U

#define	SPI_CR1_SSM 0x00000200U

#define	SPI_CR1_RXONLY 0x00000400U

#define	SPI_CR1_CRCL 0x00000800U

#define	SPI_CR1_CRCNEXT 0x00001000U

#define	SPI_CR1_CRCEN 0x00002000U

#define	SPI_CR1_BIDIOE 0x00004000U

#define	SPI_CR1_BIDIMODE 0x00008000U

#define	SPI_CR2_RXDMAEN 0x00000001U

#define	SPI_CR2_TXDMAEN 0x00000002U

#define	SPI_CR2_SSOE 0x00000004U

#define	SPI_CR2_NSSP 0x00000008U

#define	SPI_CR2_FRF 0x00000010U

#define	SPI_CR2_ERRIE 0x00000020U

#define	SPI_CR2_RXNEIE 0x00000040U

#define	SPI_CR2_TXEIE 0x00000080U

#define	SPI_CR2_DS 0x00000F00U

#define	SPI_CR2_DS_0 0x00000100U

#define	SPI_CR2_DS_1 0x00000200U

#define	SPI_CR2_DS_2 0x00000400U

#define	SPI_CR2_DS_3 0x00000800U

#define	SPI_CR2_FRXTH 0x00001000U

#define	SPI_CR2_LDMARX 0x00002000U

#define	SPI_CR2_LDMATX 0x00004000U

#define	SPI_SR_RXNE 0x00000001U

#define	SPI_SR_TXE 0x00000002U

#define	SPI_SR_CHSIDE 0x00000004U

#define	SPI_SR_UDR 0x00000008U

#define	SPI_SR_CRCERR 0x00000010U

#define	SPI_SR_MODF 0x00000020U

#define	SPI_SR_OVR 0x00000040U

#define	SPI_SR_BSY 0x00000080U

#define	SPI_SR_FRE 0x00000100U

#define	SPI_SR_FRLVL 0x00000600U

#define	SPI_SR_FRLVL_0 0x00000200U

#define	SPI_SR_FRLVL_1 0x00000400U

#define	SPI_SR_FTLVL 0x00001800U

#define	SPI_SR_FTLVL_0 0x00000800U

#define	SPI_SR_FTLVL_1 0x00001000U

#define	SPI_DR_DR 0xFFFFU

#define	SPI_CRCPR_CRCPOLY 0xFFFFU

#define	SPI_RXCRCR_RXCRC 0xFFFFU

#define	SPI_TXCRCR_TXCRC 0xFFFFU

#define	SPI_I2SCFGR_CHLEN 0x00000001U

#define	SPI_I2SCFGR_DATLEN 0x00000006U

#define	SPI_I2SCFGR_DATLEN_0 0x00000002U

#define	SPI_I2SCFGR_DATLEN_1 0x00000004U

#define	SPI_I2SCFGR_CKPOL 0x00000008U

#define	SPI_I2SCFGR_I2SSTD 0x00000030U

#define	SPI_I2SCFGR_I2SSTD_0 0x00000010U

#define	SPI_I2SCFGR_I2SSTD_1 0x00000020U

#define	SPI_I2SCFGR_PCMSYNC 0x00000080U

#define	SPI_I2SCFGR_I2SCFG 0x00000300U

#define	SPI_I2SCFGR_I2SCFG_0 0x00000100U

#define	SPI_I2SCFGR_I2SCFG_1 0x00000200U

#define	SPI_I2SCFGR_I2SE 0x00000400U

#define	SPI_I2SCFGR_I2SMOD 0x00000800U

#define	SPI_I2SCFGR_ASTRTEN 0x00001000U

#define	SPI_I2SPR_I2SDIV 0x00FFU

#define	SPI_I2SPR_ODD 0x0100U

#define	SPI_I2SPR_MCKOE 0x0200U

#define	SYSCFG_MEMRMP_MEM_BOOT 0x00000001U

#define	SYSCFG_MEMRMP_SWP_FMC 0x00000C00U

#define	SYSCFG_MEMRMP_SWP_FMC_0 0x00000400U

#define	SYSCFG_MEMRMP_SWP_FMC_1 0x00000800U

#define	SYSCFG_PMC_ADCxDC2 0x00070000U

#define	SYSCFG_PMC_ADC1DC2 0x00010000U

#define	SYSCFG_PMC_ADC2DC2 0x00020000U

#define	SYSCFG_PMC_ADC3DC2 0x00040000U

#define	SYSCFG_PMC_MII_RMII_SEL 0x00800000U

#define	SYSCFG_EXTICR1_EXTI0 0x000FU

#define	SYSCFG_EXTICR1_EXTI1 0x00F0U

#define	SYSCFG_EXTICR1_EXTI2 0x0F00U

#define	SYSCFG_EXTICR1_EXTI3 0xF000U

#define	SYSCFG_EXTICR1_EXTI0_PA 0x0000U
	EXTI0 configuration. More...

#define	SYSCFG_EXTICR1_EXTI0_PB 0x0001U

#define	SYSCFG_EXTICR1_EXTI0_PC 0x0002U

#define	SYSCFG_EXTICR1_EXTI0_PD 0x0003U

#define	SYSCFG_EXTICR1_EXTI0_PE 0x0004U

#define	SYSCFG_EXTICR1_EXTI0_PF 0x0005U

#define	SYSCFG_EXTICR1_EXTI0_PG 0x0006U

#define	SYSCFG_EXTICR1_EXTI0_PH 0x0007U

#define	SYSCFG_EXTICR1_EXTI0_PI 0x0008U

#define	SYSCFG_EXTICR1_EXTI0_PJ 0x0009U

#define	SYSCFG_EXTICR1_EXTI0_PK 0x000AU

#define	SYSCFG_EXTICR1_EXTI1_PA 0x0000U
	EXTI1 configuration. More...

#define	SYSCFG_EXTICR1_EXTI1_PB 0x0010U

#define	SYSCFG_EXTICR1_EXTI1_PC 0x0020U

#define	SYSCFG_EXTICR1_EXTI1_PD 0x0030U

#define	SYSCFG_EXTICR1_EXTI1_PE 0x0040U

#define	SYSCFG_EXTICR1_EXTI1_PF 0x0050U

#define	SYSCFG_EXTICR1_EXTI1_PG 0x0060U

#define	SYSCFG_EXTICR1_EXTI1_PH 0x0070U

#define	SYSCFG_EXTICR1_EXTI1_PI 0x0080U

#define	SYSCFG_EXTICR1_EXTI1_PJ 0x0090U

#define	SYSCFG_EXTICR1_EXTI1_PK 0x00A0U

#define	SYSCFG_EXTICR1_EXTI2_PA 0x0000U
	EXTI2 configuration. More...

#define	SYSCFG_EXTICR1_EXTI2_PB 0x0100U

#define	SYSCFG_EXTICR1_EXTI2_PC 0x0200U

#define	SYSCFG_EXTICR1_EXTI2_PD 0x0300U

#define	SYSCFG_EXTICR1_EXTI2_PE 0x0400U

#define	SYSCFG_EXTICR1_EXTI2_PF 0x0500U

#define	SYSCFG_EXTICR1_EXTI2_PG 0x0600U

#define	SYSCFG_EXTICR1_EXTI2_PH 0x0700U

#define	SYSCFG_EXTICR1_EXTI2_PI 0x0800U

#define	SYSCFG_EXTICR1_EXTI2_PJ 0x0900U

#define	SYSCFG_EXTICR1_EXTI2_PK 0x0A00U

#define	SYSCFG_EXTICR1_EXTI3_PA 0x0000U
	EXTI3 configuration. More...

#define	SYSCFG_EXTICR1_EXTI3_PB 0x1000U

#define	SYSCFG_EXTICR1_EXTI3_PC 0x2000U

#define	SYSCFG_EXTICR1_EXTI3_PD 0x3000U

#define	SYSCFG_EXTICR1_EXTI3_PE 0x4000U

#define	SYSCFG_EXTICR1_EXTI3_PF 0x5000U

#define	SYSCFG_EXTICR1_EXTI3_PG 0x6000U

#define	SYSCFG_EXTICR1_EXTI3_PH 0x7000U

#define	SYSCFG_EXTICR1_EXTI3_PI 0x8000U

#define	SYSCFG_EXTICR1_EXTI3_PJ 0x9000U

#define	SYSCFG_EXTICR1_EXTI3_PK 0xA000U

#define	SYSCFG_EXTICR2_EXTI4 0x000FU

#define	SYSCFG_EXTICR2_EXTI5 0x00F0U

#define	SYSCFG_EXTICR2_EXTI6 0x0F00U

#define	SYSCFG_EXTICR2_EXTI7 0xF000U

#define	SYSCFG_EXTICR2_EXTI4_PA 0x0000U
	EXTI4 configuration. More...

#define	SYSCFG_EXTICR2_EXTI4_PB 0x0001U

#define	SYSCFG_EXTICR2_EXTI4_PC 0x0002U

#define	SYSCFG_EXTICR2_EXTI4_PD 0x0003U

#define	SYSCFG_EXTICR2_EXTI4_PE 0x0004U

#define	SYSCFG_EXTICR2_EXTI4_PF 0x0005U

#define	SYSCFG_EXTICR2_EXTI4_PG 0x0006U

#define	SYSCFG_EXTICR2_EXTI4_PH 0x0007U

#define	SYSCFG_EXTICR2_EXTI4_PI 0x0008U

#define	SYSCFG_EXTICR2_EXTI4_PJ 0x0009U

#define	SYSCFG_EXTICR2_EXTI4_PK 0x000AU

#define	SYSCFG_EXTICR2_EXTI5_PA 0x0000U
	EXTI5 configuration. More...

#define	SYSCFG_EXTICR2_EXTI5_PB 0x0010U

#define	SYSCFG_EXTICR2_EXTI5_PC 0x0020U

#define	SYSCFG_EXTICR2_EXTI5_PD 0x0030U

#define	SYSCFG_EXTICR2_EXTI5_PE 0x0040U

#define	SYSCFG_EXTICR2_EXTI5_PF 0x0050U

#define	SYSCFG_EXTICR2_EXTI5_PG 0x0060U

#define	SYSCFG_EXTICR2_EXTI5_PH 0x0070U

#define	SYSCFG_EXTICR2_EXTI5_PI 0x0080U

#define	SYSCFG_EXTICR2_EXTI5_PJ 0x0090U

#define	SYSCFG_EXTICR2_EXTI5_PK 0x00A0U

#define	SYSCFG_EXTICR2_EXTI6_PA 0x0000U
	EXTI6 configuration. More...

#define	SYSCFG_EXTICR2_EXTI6_PB 0x0100U

#define	SYSCFG_EXTICR2_EXTI6_PC 0x0200U

#define	SYSCFG_EXTICR2_EXTI6_PD 0x0300U

#define	SYSCFG_EXTICR2_EXTI6_PE 0x0400U

#define	SYSCFG_EXTICR2_EXTI6_PF 0x0500U

#define	SYSCFG_EXTICR2_EXTI6_PG 0x0600U

#define	SYSCFG_EXTICR2_EXTI6_PH 0x0700U

#define	SYSCFG_EXTICR2_EXTI6_PI 0x0800U

#define	SYSCFG_EXTICR2_EXTI6_PJ 0x0900U

#define	SYSCFG_EXTICR2_EXTI6_PK 0x0A00U

#define	SYSCFG_EXTICR2_EXTI7_PA 0x0000U
	EXTI7 configuration. More...

#define	SYSCFG_EXTICR2_EXTI7_PB 0x1000U

#define	SYSCFG_EXTICR2_EXTI7_PC 0x2000U

#define	SYSCFG_EXTICR2_EXTI7_PD 0x3000U

#define	SYSCFG_EXTICR2_EXTI7_PE 0x4000U

#define	SYSCFG_EXTICR2_EXTI7_PF 0x5000U

#define	SYSCFG_EXTICR2_EXTI7_PG 0x6000U

#define	SYSCFG_EXTICR2_EXTI7_PH 0x7000U

#define	SYSCFG_EXTICR2_EXTI7_PI 0x8000U

#define	SYSCFG_EXTICR2_EXTI7_PJ 0x9000U

#define	SYSCFG_EXTICR2_EXTI7_PK 0xA000U

#define	SYSCFG_EXTICR3_EXTI8 0x000FU

#define	SYSCFG_EXTICR3_EXTI9 0x00F0U

#define	SYSCFG_EXTICR3_EXTI10 0x0F00U

#define	SYSCFG_EXTICR3_EXTI11 0xF000U

#define	SYSCFG_EXTICR3_EXTI8_PA 0x0000U
	EXTI8 configuration. More...

#define	SYSCFG_EXTICR3_EXTI8_PB 0x0001U

#define	SYSCFG_EXTICR3_EXTI8_PC 0x0002U

#define	SYSCFG_EXTICR3_EXTI8_PD 0x0003U

#define	SYSCFG_EXTICR3_EXTI8_PE 0x0004U

#define	SYSCFG_EXTICR3_EXTI8_PF 0x0005U

#define	SYSCFG_EXTICR3_EXTI8_PG 0x0006U

#define	SYSCFG_EXTICR3_EXTI8_PH 0x0007U

#define	SYSCFG_EXTICR3_EXTI8_PI 0x0008U

#define	SYSCFG_EXTICR3_EXTI8_PJ 0x0009U

#define	SYSCFG_EXTICR3_EXTI9_PA 0x0000U
	EXTI9 configuration. More...

#define	SYSCFG_EXTICR3_EXTI9_PB 0x0010U

#define	SYSCFG_EXTICR3_EXTI9_PC 0x0020U

#define	SYSCFG_EXTICR3_EXTI9_PD 0x0030U

#define	SYSCFG_EXTICR3_EXTI9_PE 0x0040U

#define	SYSCFG_EXTICR3_EXTI9_PF 0x0050U

#define	SYSCFG_EXTICR3_EXTI9_PG 0x0060U

#define	SYSCFG_EXTICR3_EXTI9_PH 0x0070U

#define	SYSCFG_EXTICR3_EXTI9_PI 0x0080U

#define	SYSCFG_EXTICR3_EXTI9_PJ 0x0090U

#define	SYSCFG_EXTICR3_EXTI10_PA 0x0000U
	EXTI10 configuration. More...

#define	SYSCFG_EXTICR3_EXTI10_PB 0x0100U

#define	SYSCFG_EXTICR3_EXTI10_PC 0x0200U

#define	SYSCFG_EXTICR3_EXTI10_PD 0x0300U

#define	SYSCFG_EXTICR3_EXTI10_PE 0x0400U

#define	SYSCFG_EXTICR3_EXTI10_PF 0x0500U

#define	SYSCFG_EXTICR3_EXTI10_PG 0x0600U

#define	SYSCFG_EXTICR3_EXTI10_PH 0x0700U

#define	SYSCFG_EXTICR3_EXTI10_PI 0x0800U

#define	SYSCFG_EXTICR3_EXTI10_PJ 0x0900U

#define	SYSCFG_EXTICR3_EXTI11_PA 0x0000U
	EXTI11 configuration. More...

#define	SYSCFG_EXTICR3_EXTI11_PB 0x1000U

#define	SYSCFG_EXTICR3_EXTI11_PC 0x2000U

#define	SYSCFG_EXTICR3_EXTI11_PD 0x3000U

#define	SYSCFG_EXTICR3_EXTI11_PE 0x4000U

#define	SYSCFG_EXTICR3_EXTI11_PF 0x5000U

#define	SYSCFG_EXTICR3_EXTI11_PG 0x6000U

#define	SYSCFG_EXTICR3_EXTI11_PH 0x7000U

#define	SYSCFG_EXTICR3_EXTI11_PI 0x8000U

#define	SYSCFG_EXTICR3_EXTI11_PJ 0x9000U

#define	SYSCFG_EXTICR4_EXTI12 0x000FU

#define	SYSCFG_EXTICR4_EXTI13 0x00F0U

#define	SYSCFG_EXTICR4_EXTI14 0x0F00U

#define	SYSCFG_EXTICR4_EXTI15 0xF000U

#define	SYSCFG_EXTICR4_EXTI12_PA 0x0000U
	EXTI12 configuration. More...

#define	SYSCFG_EXTICR4_EXTI12_PB 0x0001U

#define	SYSCFG_EXTICR4_EXTI12_PC 0x0002U

#define	SYSCFG_EXTICR4_EXTI12_PD 0x0003U

#define	SYSCFG_EXTICR4_EXTI12_PE 0x0004U

#define	SYSCFG_EXTICR4_EXTI12_PF 0x0005U

#define	SYSCFG_EXTICR4_EXTI12_PG 0x0006U

#define	SYSCFG_EXTICR4_EXTI12_PH 0x0007U

#define	SYSCFG_EXTICR4_EXTI12_PI 0x0008U

#define	SYSCFG_EXTICR4_EXTI12_PJ 0x0009U

#define	SYSCFG_EXTICR4_EXTI13_PA 0x0000U
	EXTI13 configuration. More...

#define	SYSCFG_EXTICR4_EXTI13_PB 0x0010U

#define	SYSCFG_EXTICR4_EXTI13_PC 0x0020U

#define	SYSCFG_EXTICR4_EXTI13_PD 0x0030U

#define	SYSCFG_EXTICR4_EXTI13_PE 0x0040U

#define	SYSCFG_EXTICR4_EXTI13_PF 0x0050U

#define	SYSCFG_EXTICR4_EXTI13_PG 0x0060U

#define	SYSCFG_EXTICR4_EXTI13_PH 0x0070U

#define	SYSCFG_EXTICR4_EXTI13_PI 0x0080U

#define	SYSCFG_EXTICR4_EXTI13_PJ 0x0090U

#define	SYSCFG_EXTICR4_EXTI14_PA 0x0000U
	EXTI14 configuration. More...

#define	SYSCFG_EXTICR4_EXTI14_PB 0x0100U

#define	SYSCFG_EXTICR4_EXTI14_PC 0x0200U

#define	SYSCFG_EXTICR4_EXTI14_PD 0x0300U

#define	SYSCFG_EXTICR4_EXTI14_PE 0x0400U

#define	SYSCFG_EXTICR4_EXTI14_PF 0x0500U

#define	SYSCFG_EXTICR4_EXTI14_PG 0x0600U

#define	SYSCFG_EXTICR4_EXTI14_PH 0x0700U

#define	SYSCFG_EXTICR4_EXTI14_PI 0x0800U

#define	SYSCFG_EXTICR4_EXTI14_PJ 0x0900U

#define	SYSCFG_EXTICR4_EXTI15_PA 0x0000U
	EXTI15 configuration. More...

#define	SYSCFG_EXTICR4_EXTI15_PB 0x1000U

#define	SYSCFG_EXTICR4_EXTI15_PC 0x2000U

#define	SYSCFG_EXTICR4_EXTI15_PD 0x3000U

#define	SYSCFG_EXTICR4_EXTI15_PE 0x4000U

#define	SYSCFG_EXTICR4_EXTI15_PF 0x5000U

#define	SYSCFG_EXTICR4_EXTI15_PG 0x6000U

#define	SYSCFG_EXTICR4_EXTI15_PH 0x7000U

#define	SYSCFG_EXTICR4_EXTI15_PI 0x8000U

#define	SYSCFG_EXTICR4_EXTI15_PJ 0x9000U

#define	SYSCFG_CMPCR_CMP_PD 0x00000001U

#define	SYSCFG_CMPCR_READY 0x00000100U

#define	TIM_CR1_CEN 0x0001U

#define	TIM_CR1_UDIS 0x0002U

#define	TIM_CR1_URS 0x0004U

#define	TIM_CR1_OPM 0x0008U

#define	TIM_CR1_DIR 0x0010U

#define	TIM_CR1_CMS 0x0060U

#define	TIM_CR1_CMS_0 0x0020U

#define	TIM_CR1_CMS_1 0x0040U

#define	TIM_CR1_ARPE 0x0080U

#define	TIM_CR1_CKD 0x0300U

#define	TIM_CR1_CKD_0 0x0100U

#define	TIM_CR1_CKD_1 0x0200U

#define	TIM_CR1_UIFREMAP 0x0800U

#define	TIM_CR2_CCPC 0x00000001U

#define	TIM_CR2_CCUS 0x00000004U

#define	TIM_CR2_CCDS 0x00000008U

#define	TIM_CR2_OIS5 0x00010000U

#define	TIM_CR2_OIS6 0x00040000U

#define	TIM_CR2_MMS 0x0070U

#define	TIM_CR2_MMS_0 0x0010U

#define	TIM_CR2_MMS_1 0x0020U

#define	TIM_CR2_MMS_2 0x0040U

#define	TIM_CR2_MMS2 0x00F00000U

#define	TIM_CR2_MMS2_0 0x00100000U

#define	TIM_CR2_MMS2_1 0x00200000U

#define	TIM_CR2_MMS2_2 0x00400000U

#define	TIM_CR2_MMS2_3 0x00800000U

#define	TIM_CR2_TI1S 0x0080U

#define	TIM_CR2_OIS1 0x0100U

#define	TIM_CR2_OIS1N 0x0200U

#define	TIM_CR2_OIS2 0x0400U

#define	TIM_CR2_OIS2N 0x0800U

#define	TIM_CR2_OIS3 0x1000U

#define	TIM_CR2_OIS3N 0x2000U

#define	TIM_CR2_OIS4 0x4000U

#define	TIM_SMCR_SMS 0x00010007U

#define	TIM_SMCR_SMS_0 0x00000001U

#define	TIM_SMCR_SMS_1 0x00000002U

#define	TIM_SMCR_SMS_2 0x00000004U

#define	TIM_SMCR_SMS_3 0x00010000U

#define	TIM_SMCR_OCCS 0x00000008U

#define	TIM_SMCR_TS 0x0070U

#define	TIM_SMCR_TS_0 0x0010U

#define	TIM_SMCR_TS_1 0x0020U

#define	TIM_SMCR_TS_2 0x0040U

#define	TIM_SMCR_MSM 0x0080U

#define	TIM_SMCR_ETF 0x0F00U

#define	TIM_SMCR_ETF_0 0x0100U

#define	TIM_SMCR_ETF_1 0x0200U

#define	TIM_SMCR_ETF_2 0x0400U

#define	TIM_SMCR_ETF_3 0x0800U

#define	TIM_SMCR_ETPS 0x3000U

#define	TIM_SMCR_ETPS_0 0x1000U

#define	TIM_SMCR_ETPS_1 0x2000U

#define	TIM_SMCR_ECE 0x4000U

#define	TIM_SMCR_ETP 0x8000U

#define	TIM_DIER_UIE 0x0001U

#define	TIM_DIER_CC1IE 0x0002U

#define	TIM_DIER_CC2IE 0x0004U

#define	TIM_DIER_CC3IE 0x0008U

#define	TIM_DIER_CC4IE 0x0010U

#define	TIM_DIER_COMIE 0x0020U

#define	TIM_DIER_TIE 0x0040U

#define	TIM_DIER_BIE 0x0080U

#define	TIM_DIER_UDE 0x0100U

#define	TIM_DIER_CC1DE 0x0200U

#define	TIM_DIER_CC2DE 0x0400U

#define	TIM_DIER_CC3DE 0x0800U

#define	TIM_DIER_CC4DE 0x1000U

#define	TIM_DIER_COMDE 0x2000U

#define	TIM_DIER_TDE 0x4000U

#define	TIM_SR_UIF 0x0001U

#define	TIM_SR_CC1IF 0x0002U

#define	TIM_SR_CC2IF 0x0004U

#define	TIM_SR_CC3IF 0x0008U

#define	TIM_SR_CC4IF 0x0010U

#define	TIM_SR_COMIF 0x0020U

#define	TIM_SR_TIF 0x0040U

#define	TIM_SR_BIF 0x0080U

#define	TIM_SR_B2IF 0x0100U

#define	TIM_SR_CC1OF 0x0200U

#define	TIM_SR_CC2OF 0x0400U

#define	TIM_SR_CC3OF 0x0800U

#define	TIM_SR_CC4OF 0x1000U

#define	TIM_EGR_UG 0x00000001U

#define	TIM_EGR_CC1G 0x00000002U

#define	TIM_EGR_CC2G 0x00000004U

#define	TIM_EGR_CC3G 0x00000008U

#define	TIM_EGR_CC4G 0x00000010U

#define	TIM_EGR_COMG 0x00000020U

#define	TIM_EGR_TG 0x00000040U

#define	TIM_EGR_BG 0x00000080U

#define	TIM_EGR_B2G 0x00000100U

#define	TIM_CCMR1_CC1S 0x00000003U

#define	TIM_CCMR1_CC1S_0 0x00000001U

#define	TIM_CCMR1_CC1S_1 0x00000002U

#define	TIM_CCMR1_OC1FE 0x00000004U

#define	TIM_CCMR1_OC1PE 0x00000008U

#define	TIM_CCMR1_OC1M 0x00010070U

#define	TIM_CCMR1_OC1M_0 0x00000010U

#define	TIM_CCMR1_OC1M_1 0x00000020U

#define	TIM_CCMR1_OC1M_2 0x00000040U

#define	TIM_CCMR1_OC1M_3 0x00010000U

#define	TIM_CCMR1_OC1CE 0x00000080U

#define	TIM_CCMR1_CC2S 0x00000300U

#define	TIM_CCMR1_CC2S_0 0x00000100U

#define	TIM_CCMR1_CC2S_1 0x00000200U

#define	TIM_CCMR1_OC2FE 0x00000400U

#define	TIM_CCMR1_OC2PE 0x00000800U

#define	TIM_CCMR1_OC2M 0x01007000U

#define	TIM_CCMR1_OC2M_0 0x00001000U

#define	TIM_CCMR1_OC2M_1 0x00002000U

#define	TIM_CCMR1_OC2M_2 0x00004000U

#define	TIM_CCMR1_OC2M_3 0x01000000U

#define	TIM_CCMR1_OC2CE 0x00008000U

#define	TIM_CCMR1_IC1PSC 0x000CU

#define	TIM_CCMR1_IC1PSC_0 0x0004U

#define	TIM_CCMR1_IC1PSC_1 0x0008U

#define	TIM_CCMR1_IC1F 0x00F0U

#define	TIM_CCMR1_IC1F_0 0x0010U

#define	TIM_CCMR1_IC1F_1 0x0020U

#define	TIM_CCMR1_IC1F_2 0x0040U

#define	TIM_CCMR1_IC1F_3 0x0080U

#define	TIM_CCMR1_IC2PSC 0x0C00U

#define	TIM_CCMR1_IC2PSC_0 0x0400U

#define	TIM_CCMR1_IC2PSC_1 0x0800U

#define	TIM_CCMR1_IC2F 0xF000U

#define	TIM_CCMR1_IC2F_0 0x1000U

#define	TIM_CCMR1_IC2F_1 0x2000U

#define	TIM_CCMR1_IC2F_2 0x4000U

#define	TIM_CCMR1_IC2F_3 0x8000U

#define	TIM_CCMR2_CC3S 0x00000003U

#define	TIM_CCMR2_CC3S_0 0x00000001U

#define	TIM_CCMR2_CC3S_1 0x00000002U

#define	TIM_CCMR2_OC3FE 0x00000004U

#define	TIM_CCMR2_OC3PE 0x00000008U

#define	TIM_CCMR2_OC3M 0x00010070U

#define	TIM_CCMR2_OC3M_0 0x00000010U

#define	TIM_CCMR2_OC3M_1 0x00000020U

#define	TIM_CCMR2_OC3M_2 0x00000040U

#define	TIM_CCMR2_OC3M_3 0x00010000U

#define	TIM_CCMR2_OC3CE 0x00000080U

#define	TIM_CCMR2_CC4S 0x00000300U

#define	TIM_CCMR2_CC4S_0 0x00000100U

#define	TIM_CCMR2_CC4S_1 0x00000200U

#define	TIM_CCMR2_OC4FE 0x00000400U

#define	TIM_CCMR2_OC4PE 0x00000800U

#define	TIM_CCMR2_OC4M 0x01007000U

#define	TIM_CCMR2_OC4M_0 0x00001000U

#define	TIM_CCMR2_OC4M_1 0x00002000U

#define	TIM_CCMR2_OC4M_2 0x00004000U

#define	TIM_CCMR2_OC4M_3 0x01000000U

#define	TIM_CCMR2_OC4CE 0x8000U

#define	TIM_CCMR2_IC3PSC 0x000CU

#define	TIM_CCMR2_IC3PSC_0 0x0004U

#define	TIM_CCMR2_IC3PSC_1 0x0008U

#define	TIM_CCMR2_IC3F 0x00F0U

#define	TIM_CCMR2_IC3F_0 0x0010U

#define	TIM_CCMR2_IC3F_1 0x0020U

#define	TIM_CCMR2_IC3F_2 0x0040U

#define	TIM_CCMR2_IC3F_3 0x0080U

#define	TIM_CCMR2_IC4PSC 0x0C00U

#define	TIM_CCMR2_IC4PSC_0 0x0400U

#define	TIM_CCMR2_IC4PSC_1 0x0800U

#define	TIM_CCMR2_IC4F 0xF000U

#define	TIM_CCMR2_IC4F_0 0x1000U

#define	TIM_CCMR2_IC4F_1 0x2000U

#define	TIM_CCMR2_IC4F_2 0x4000U

#define	TIM_CCMR2_IC4F_3 0x8000U

#define	TIM_CCER_CC1E 0x00000001U

#define	TIM_CCER_CC1P 0x00000002U

#define	TIM_CCER_CC1NE 0x00000004U

#define	TIM_CCER_CC1NP 0x00000008U

#define	TIM_CCER_CC2E 0x00000010U

#define	TIM_CCER_CC2P 0x00000020U

#define	TIM_CCER_CC2NE 0x00000040U

#define	TIM_CCER_CC2NP 0x00000080U

#define	TIM_CCER_CC3E 0x00000100U

#define	TIM_CCER_CC3P 0x00000200U

#define	TIM_CCER_CC3NE 0x00000400U

#define	TIM_CCER_CC3NP 0x00000800U

#define	TIM_CCER_CC4E 0x00001000U

#define	TIM_CCER_CC4P 0x00002000U

#define	TIM_CCER_CC4NP 0x00008000U

#define	TIM_CCER_CC5E 0x00010000U

#define	TIM_CCER_CC5P 0x00020000U

#define	TIM_CCER_CC6E 0x00100000U

#define	TIM_CCER_CC6P 0x00200000U

#define	TIM_CNT_CNT 0xFFFFU

#define	TIM_PSC_PSC 0xFFFFU

#define	TIM_ARR_ARR 0xFFFFU

#define	TIM_RCR_REP ((uint8_t)0xFFU)

#define	TIM_CCR1_CCR1 0xFFFFU

#define	TIM_CCR2_CCR2 0xFFFFU

#define	TIM_CCR3_CCR3 0xFFFFU

#define	TIM_CCR4_CCR4 0xFFFFU

#define	TIM_BDTR_DTG 0x000000FFU

#define	TIM_BDTR_DTG_0 0x00000001U

#define	TIM_BDTR_DTG_1 0x00000002U

#define	TIM_BDTR_DTG_2 0x00000004U

#define	TIM_BDTR_DTG_3 0x00000008U

#define	TIM_BDTR_DTG_4 0x00000010U

#define	TIM_BDTR_DTG_5 0x00000020U

#define	TIM_BDTR_DTG_6 0x00000040U

#define	TIM_BDTR_DTG_7 0x00000080U

#define	TIM_BDTR_LOCK 0x00000300U

#define	TIM_BDTR_LOCK_0 0x00000100U

#define	TIM_BDTR_LOCK_1 0x00000200U

#define	TIM_BDTR_OSSI 0x00000400U

#define	TIM_BDTR_OSSR 0x00000800U

#define	TIM_BDTR_BKE 0x00001000U

#define	TIM_BDTR_BKP 0x00002000U

#define	TIM_BDTR_AOE 0x00004000U

#define	TIM_BDTR_MOE 0x00008000U

#define	TIM_BDTR_BKF 0x000F0000U

#define	TIM_BDTR_BK2F 0x00F00000U

#define	TIM_BDTR_BK2E 0x01000000U

#define	TIM_BDTR_BK2P 0x02000000U

#define	TIM_DCR_DBA 0x001FU

#define	TIM_DCR_DBA_0 0x0001U

#define	TIM_DCR_DBA_1 0x0002U

#define	TIM_DCR_DBA_2 0x0004U

#define	TIM_DCR_DBA_3 0x0008U

#define	TIM_DCR_DBA_4 0x0010U

#define	TIM_DCR_DBL 0x1F00U

#define	TIM_DCR_DBL_0 0x0100U

#define	TIM_DCR_DBL_1 0x0200U

#define	TIM_DCR_DBL_2 0x0400U

#define	TIM_DCR_DBL_3 0x0800U

#define	TIM_DCR_DBL_4 0x1000U

#define	TIM_DMAR_DMAB 0xFFFFU

#define	TIM_OR_TI4_RMP 0x00C0U

#define	TIM_OR_TI4_RMP_0 0x0040U

#define	TIM_OR_TI4_RMP_1 0x0080U

#define	TIM_OR_ITR1_RMP 0x0C00U

#define	TIM_OR_ITR1_RMP_0 0x0400U

#define	TIM_OR_ITR1_RMP_1 0x0800U

#define	TIM_CCMR3_OC5FE 0x00000004U

#define	TIM_CCMR3_OC5PE 0x00000008U

#define	TIM_CCMR3_OC5M 0x00010070U

#define	TIM_CCMR3_OC5M_0 0x00000010U

#define	TIM_CCMR3_OC5M_1 0x00000020U

#define	TIM_CCMR3_OC5M_2 0x00000040U

#define	TIM_CCMR3_OC5M_3 0x00010000U

#define	TIM_CCMR3_OC5CE 0x00000080U

#define	TIM_CCMR3_OC6FE 0x00000400U

#define	TIM_CCMR3_OC6PE 0x00000800U

#define	TIM_CCMR3_OC6M 0x01007000U

#define	TIM_CCMR3_OC6M_0 0x00001000U

#define	TIM_CCMR3_OC6M_1 0x00002000U

#define	TIM_CCMR3_OC6M_2 0x00004000U

#define	TIM_CCMR3_OC6M_3 0x01000000U

#define	TIM_CCMR3_OC6CE 0x00008000U

#define	TIM_CCR5_CCR5 0xFFFFFFFFU

#define	TIM_CCR5_GC5C1 0x20000000U

#define	TIM_CCR5_GC5C2 0x40000000U

#define	TIM_CCR5_GC5C3 0x80000000U

#define	TIM_CCR6_CCR6 ((uint16_t)0xFFFFU)

#define	LPTIM_ISR_CMPM 0x00000001U

#define	LPTIM_ISR_ARRM 0x00000002U

#define	LPTIM_ISR_EXTTRIG 0x00000004U

#define	LPTIM_ISR_CMPOK 0x00000008U

#define	LPTIM_ISR_ARROK 0x00000010U

#define	LPTIM_ISR_UP 0x00000020U

#define	LPTIM_ISR_DOWN 0x00000040U

#define	LPTIM_ICR_CMPMCF 0x00000001U

#define	LPTIM_ICR_ARRMCF 0x00000002U

#define	LPTIM_ICR_EXTTRIGCF 0x00000004U

#define	LPTIM_ICR_CMPOKCF 0x00000008U

#define	LPTIM_ICR_ARROKCF 0x00000010U

#define	LPTIM_ICR_UPCF 0x00000020U

#define	LPTIM_ICR_DOWNCF 0x00000040U

#define	LPTIM_IER_CMPMIE 0x00000001U

#define	LPTIM_IER_ARRMIE 0x00000002U

#define	LPTIM_IER_EXTTRIGIE 0x00000004U

#define	LPTIM_IER_CMPOKIE 0x00000008U

#define	LPTIM_IER_ARROKIE 0x00000010U

#define	LPTIM_IER_UPIE 0x00000020U

#define	LPTIM_IER_DOWNIE 0x00000040U

#define	LPTIM_CFGR_CKSEL 0x00000001U

#define	LPTIM_CFGR_CKPOL 0x00000006U

#define	LPTIM_CFGR_CKPOL_0 0x00000002U

#define	LPTIM_CFGR_CKPOL_1 0x00000004U

#define	LPTIM_CFGR_CKFLT 0x00000018U

#define	LPTIM_CFGR_CKFLT_0 0x00000008U

#define	LPTIM_CFGR_CKFLT_1 0x00000010U

#define	LPTIM_CFGR_TRGFLT 0x000000C0U

#define	LPTIM_CFGR_TRGFLT_0 0x00000040U

#define	LPTIM_CFGR_TRGFLT_1 0x00000080U

#define	LPTIM_CFGR_PRESC 0x00000E00U

#define	LPTIM_CFGR_PRESC_0 0x00000200U

#define	LPTIM_CFGR_PRESC_1 0x00000400U

#define	LPTIM_CFGR_PRESC_2 0x00000800U

#define	LPTIM_CFGR_TRIGSEL 0x0000E000U

#define	LPTIM_CFGR_TRIGSEL_0 0x00002000U

#define	LPTIM_CFGR_TRIGSEL_1 0x00004000U

#define	LPTIM_CFGR_TRIGSEL_2 0x00008000U

#define	LPTIM_CFGR_TRIGEN 0x00060000U

#define	LPTIM_CFGR_TRIGEN_0 0x00020000U

#define	LPTIM_CFGR_TRIGEN_1 0x00040000U

#define	LPTIM_CFGR_TIMOUT 0x00080000U

#define	LPTIM_CFGR_WAVE 0x00100000U

#define	LPTIM_CFGR_WAVPOL 0x00200000U

#define	LPTIM_CFGR_PRELOAD 0x00400000U

#define	LPTIM_CFGR_COUNTMODE 0x00800000U

#define	LPTIM_CFGR_ENC 0x01000000U

#define	LPTIM_CR_ENABLE 0x00000001U

#define	LPTIM_CR_SNGSTRT 0x00000002U

#define	LPTIM_CR_CNTSTRT 0x00000004U

#define	LPTIM_CMP_CMP 0x0000FFFFU

#define	LPTIM_ARR_ARR 0x0000FFFFU

#define	LPTIM_CNT_CNT 0x0000FFFFU

#define	USART_CR1_UE 0x00000001U

#define	USART_CR1_RE 0x00000004U

#define	USART_CR1_TE 0x00000008U

#define	USART_CR1_IDLEIE 0x00000010U

#define	USART_CR1_RXNEIE 0x00000020U

#define	USART_CR1_TCIE 0x00000040U

#define	USART_CR1_TXEIE 0x00000080U

#define	USART_CR1_PEIE 0x00000100U

#define	USART_CR1_PS 0x00000200U

#define	USART_CR1_PCE 0x00000400U

#define	USART_CR1_WAKE 0x00000800U

#define	USART_CR1_M 0x10001000U

#define	USART_CR1_M_0 0x00001000U

#define	USART_CR1_MME 0x00002000U

#define	USART_CR1_CMIE 0x00004000U

#define	USART_CR1_OVER8 0x00008000U

#define	USART_CR1_DEDT 0x001F0000U

#define	USART_CR1_DEDT_0 0x00010000U

#define	USART_CR1_DEDT_1 0x00020000U

#define	USART_CR1_DEDT_2 0x00040000U

#define	USART_CR1_DEDT_3 0x00080000U

#define	USART_CR1_DEDT_4 0x00100000U

#define	USART_CR1_DEAT 0x03E00000U

#define	USART_CR1_DEAT_0 0x00200000U

#define	USART_CR1_DEAT_1 0x00400000U

#define	USART_CR1_DEAT_2 0x00800000U

#define	USART_CR1_DEAT_3 0x01000000U

#define	USART_CR1_DEAT_4 0x02000000U

#define	USART_CR1_RTOIE 0x04000000U

#define	USART_CR1_EOBIE 0x08000000U

#define	USART_CR1_M_1 0x10000000U

#define	USART_CR2_ADDM7 0x00000010U

#define	USART_CR2_LBDL 0x00000020U

#define	USART_CR2_LBDIE 0x00000040U

#define	USART_CR2_LBCL 0x00000100U

#define	USART_CR2_CPHA 0x00000200U

#define	USART_CR2_CPOL 0x00000400U

#define	USART_CR2_CLKEN 0x00000800U

#define	USART_CR2_STOP 0x00003000U

#define	USART_CR2_STOP_0 0x00001000U

#define	USART_CR2_STOP_1 0x00002000U

#define	USART_CR2_LINEN 0x00004000U

#define	USART_CR2_SWAP 0x00008000U

#define	USART_CR2_RXINV 0x00010000U

#define	USART_CR2_TXINV 0x00020000U

#define	USART_CR2_DATAINV 0x00040000U

#define	USART_CR2_MSBFIRST 0x00080000U

#define	USART_CR2_ABREN 0x00100000U

#define	USART_CR2_ABRMODE 0x00600000U

#define	USART_CR2_ABRMODE_0 0x00200000U

#define	USART_CR2_ABRMODE_1 0x00400000U

#define	USART_CR2_RTOEN 0x00800000U

#define	USART_CR2_ADD 0xFF000000U

#define	USART_CR3_EIE 0x00000001U

#define	USART_CR3_IREN 0x00000002U

#define	USART_CR3_IRLP 0x00000004U

#define	USART_CR3_HDSEL 0x00000008U

#define	USART_CR3_NACK 0x00000010U

#define	USART_CR3_SCEN 0x00000020U

#define	USART_CR3_DMAR 0x00000040U

#define	USART_CR3_DMAT 0x00000080U

#define	USART_CR3_RTSE 0x00000100U

#define	USART_CR3_CTSE 0x00000200U

#define	USART_CR3_CTSIE 0x00000400U

#define	USART_CR3_ONEBIT 0x00000800U

#define	USART_CR3_OVRDIS 0x00001000U

#define	USART_CR3_DDRE 0x00002000U

#define	USART_CR3_DEM 0x00004000U

#define	USART_CR3_DEP 0x00008000U

#define	USART_CR3_SCARCNT 0x000E0000U

#define	USART_CR3_SCARCNT_0 0x00020000U

#define	USART_CR3_SCARCNT_1 0x00040000U

#define	USART_CR3_SCARCNT_2 0x00080000U

#define	USART_BRR_DIV_FRACTION 0x000FU

#define	USART_BRR_DIV_MANTISSA 0xFFF0U

#define	USART_GTPR_PSC 0x00FFU

#define	USART_GTPR_GT 0xFF00U

#define	USART_RTOR_RTO 0x00FFFFFFU

#define	USART_RTOR_BLEN 0xFF000000U

#define	USART_RQR_ABRRQ 0x0001U

#define	USART_RQR_SBKRQ 0x0002U

#define	USART_RQR_MMRQ 0x0004U

#define	USART_RQR_RXFRQ 0x0008U

#define	USART_RQR_TXFRQ 0x0010U

#define	USART_ISR_PE 0x00000001U

#define	USART_ISR_FE 0x00000002U

#define	USART_ISR_NE 0x00000004U

#define	USART_ISR_ORE 0x00000008U

#define	USART_ISR_IDLE 0x00000010U

#define	USART_ISR_RXNE 0x00000020U

#define	USART_ISR_TC 0x00000040U

#define	USART_ISR_TXE 0x00000080U

#define	USART_ISR_LBDF 0x00000100U

#define	USART_ISR_CTSIF 0x00000200U

#define	USART_ISR_CTS 0x00000400U

#define	USART_ISR_RTOF 0x00000800U

#define	USART_ISR_EOBF 0x00001000U

#define	USART_ISR_ABRE 0x00004000U

#define	USART_ISR_ABRF 0x00008000U

#define	USART_ISR_BUSY 0x00010000U

#define	USART_ISR_CMF 0x00020000U

#define	USART_ISR_SBKF 0x00040000U

#define	USART_ISR_RWU 0x00080000U

#define	USART_ISR_WUF 0x00100000U

#define	USART_ISR_TEACK 0x00200000U

#define	USART_ISR_REACK 0x00400000U

#define	USART_ISR_LBD USART_ISR_LBDF

#define	USART_ICR_PECF 0x00000001U

#define	USART_ICR_FECF 0x00000002U

#define	USART_ICR_NCF 0x00000004U

#define	USART_ICR_ORECF 0x00000008U

#define	USART_ICR_IDLECF 0x00000010U

#define	USART_ICR_TCCF 0x00000040U

#define	USART_ICR_LBDCF 0x00000100U

#define	USART_ICR_CTSCF 0x00000200U

#define	USART_ICR_RTOCF 0x00000800U

#define	USART_ICR_EOBCF 0x00001000U

#define	USART_ICR_CMCF 0x00020000U

#define	USART_ICR_WUCF 0x00100000U

#define	USART_RDR_RDR 0x01FFU

#define	USART_TDR_TDR 0x01FFU

#define	WWDG_CR_T 0x7FU

#define	WWDG_CR_T_0 0x01U

#define	WWDG_CR_T_1 0x02U

#define	WWDG_CR_T_2 0x04U

#define	WWDG_CR_T_3 0x08U

#define	WWDG_CR_T_4 0x10U

#define	WWDG_CR_T_5 0x20U

#define	WWDG_CR_T_6 0x40U

#define	WWDG_CR_T0 WWDG_CR_T_0

#define	WWDG_CR_T1 WWDG_CR_T_1

#define	WWDG_CR_T2 WWDG_CR_T_2

#define	WWDG_CR_T3 WWDG_CR_T_3

#define	WWDG_CR_T4 WWDG_CR_T_4

#define	WWDG_CR_T5 WWDG_CR_T_5

#define	WWDG_CR_T6 WWDG_CR_T_6

#define	WWDG_CR_WDGA 0x80U

#define	WWDG_CFR_W 0x007FU

#define	WWDG_CFR_W_0 0x0001U

#define	WWDG_CFR_W_1 0x0002U

#define	WWDG_CFR_W_2 0x0004U

#define	WWDG_CFR_W_3 0x0008U

#define	WWDG_CFR_W_4 0x0010U

#define	WWDG_CFR_W_5 0x0020U

#define	WWDG_CFR_W_6 0x0040U

#define	WWDG_CFR_W0 WWDG_CFR_W_0

#define	WWDG_CFR_W1 WWDG_CFR_W_1

#define	WWDG_CFR_W2 WWDG_CFR_W_2

#define	WWDG_CFR_W3 WWDG_CFR_W_3

#define	WWDG_CFR_W4 WWDG_CFR_W_4

#define	WWDG_CFR_W5 WWDG_CFR_W_5

#define	WWDG_CFR_W6 WWDG_CFR_W_6

#define	WWDG_CFR_WDGTB 0x0180U

#define	WWDG_CFR_WDGTB_0 0x0080U

#define	WWDG_CFR_WDGTB_1 0x0100U

#define	WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0

#define	WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1

#define	WWDG_CFR_EWI 0x0200U

#define	WWDG_SR_EWIF 0x01U

#define	DBGMCU_IDCODE_DEV_ID 0x00000FFFU

#define	DBGMCU_IDCODE_REV_ID 0xFFFF0000U

#define	DBGMCU_CR_DBG_SLEEP 0x00000001U

#define	DBGMCU_CR_DBG_STOP 0x00000002U

#define	DBGMCU_CR_DBG_STANDBY 0x00000004U

#define	DBGMCU_CR_TRACE_IOEN 0x00000020U

#define	DBGMCU_CR_TRACE_MODE 0x000000C0U

#define	DBGMCU_CR_TRACE_MODE_0 0x00000040U

#define	DBGMCU_CR_TRACE_MODE_1 0x00000080U

#define	DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U

#define	DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U

#define	DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U

#define	DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U

#define	DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U

#define	DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U

#define	DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U

#define	DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U

#define	DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U

#define	DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U

#define	DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U

#define	DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U

#define	DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U

#define	DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U

#define	DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U

#define	DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U

#define	DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U

#define	DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U

#define	DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U

#define	DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U

#define	DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U

#define	DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U

#define	ETH_MACCR_WD 0x00800000U /* Watchdog disable */

#define	ETH_MACCR_JD 0x00400000U /* Jabber disable */

#define	ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */

#define	ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */

#define	ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */

#define	ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */

#define	ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */

#define	ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */

#define	ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */

#define	ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */

#define	ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */

#define	ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */

#define	ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */

#define	ETH_MACCR_ROD 0x00002000U /* Receive own disable */

#define	ETH_MACCR_LM 0x00001000U /* loopback mode */

#define	ETH_MACCR_DM 0x00000800U /* Duplex mode */

#define	ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */

#define	ETH_MACCR_RD 0x00000200U /* Retry disable */

#define	ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */

#define	ETH_MACCR_BL

#define	ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */

#define	ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */

#define	ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */

#define	ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */

#define	ETH_MACCR_DC 0x00000010U /* Defferal check */

#define	ETH_MACCR_TE 0x00000008U /* Transmitter enable */

#define	ETH_MACCR_RE 0x00000004U /* Receiver enable */

#define	ETH_MACFFR_RA 0x80000000U /* Receive all */

#define	ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */

#define	ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */

#define	ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */

#define	ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */

#define	ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */

#define	ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */

#define	ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */

#define	ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */

#define	ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */

#define	ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */

#define	ETH_MACFFR_HM 0x00000004U /* Hash multicast */

#define	ETH_MACFFR_HU 0x00000002U /* Hash unicast */

#define	ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */

#define	ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */

#define	ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */

#define	ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */

#define	ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */

#define	ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */

#define	ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */

#define	ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */

#define	ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */

#define	ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */

#define	ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */

#define	ETH_MACMIIAR_MW 0x00000002U /* MII write */

#define	ETH_MACMIIAR_MB 0x00000001U /* MII busy */

#define	ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */

#define	ETH_MACFCR_PT 0xFFFF0000U /* Pause time */

#define	ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */

#define	ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */

#define	ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */

#define	ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */

#define	ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */

#define	ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */

#define	ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */

#define	ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */

#define	ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */

#define	ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */

#define	ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */

#define	ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */

#define	ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */

#define	ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */

#define	ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */

#define	ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */

#define	ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */

#define	ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */

#define	ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */

#define	ETH_MACPMTCSR_PD 0x00000001U /* Power Down */

#define	ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */

#define	ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */

#define	ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */

#define	ETH_MACSR_MMCS 0x00000010U /* MMC status */

#define	ETH_MACSR_PMTS 0x00000008U /* PMT status */

#define	ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */

#define	ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */

#define	ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */

#define	ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */

#define	ETH_MACA1HR_AE 0x80000000U /* Address enable */

#define	ETH_MACA1HR_SA 0x40000000U /* Source address */

#define	ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */

#define	ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */

#define	ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */

#define	ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */

#define	ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */

#define	ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */

#define	ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */

#define	ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */

#define	ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */

#define	ETH_MACA2HR_AE 0x80000000U /* Address enable */

#define	ETH_MACA2HR_SA 0x40000000U /* Source address */

#define	ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */

#define	ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */

#define	ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */

#define	ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */

#define	ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */

#define	ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */

#define	ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */

#define	ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */

#define	ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */

#define	ETH_MACA3HR_AE 0x80000000U /* Address enable */

#define	ETH_MACA3HR_SA 0x40000000U /* Source address */

#define	ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */

#define	ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */

#define	ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */

#define	ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */

#define	ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */

#define	ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */

#define	ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */

#define	ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */

#define	ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */

#define	ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */

#define	ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */

#define	ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */

#define	ETH_MMCCR_ROR 0x00000004U /* Reset on Read */

#define	ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */

#define	ETH_MMCCR_CR 0x00000001U /* Counters Reset */

#define	ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */

#define	ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */

#define	ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */

#define	ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */

#define	ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */

#define	ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */

#define	ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */

#define	ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */

#define	ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */

#define	ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */

#define	ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */

#define	ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */

#define	ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */

#define	ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */

#define	ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */

#define	ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */

#define	ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */

#define	ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */

#define	ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */

#define	ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */

#define	ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */

#define	ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */

#define	ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */

#define	ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */

#define	ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */

#define	ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */

#define	ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */

#define	ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */

#define	ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */

#define	ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */

#define	ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */

#define	ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */

#define	ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */

#define	ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */

#define	ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */

#define	ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */

#define	ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */

#define	ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */

#define	ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */

#define	ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */

#define	ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */

#define	ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */

#define	ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */

#define	ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */

#define	ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */

#define	ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */

#define	ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */

#define	ETH_DMABMR_USP 0x00800000U /* Use separate PBL */

#define	ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */

#define	ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */

#define	ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */

#define	ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */

#define	ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */

#define	ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */

#define	ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */

#define	ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */

#define	ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */

#define	ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */

#define	ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */

#define	ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */

#define	ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */

#define	ETH_DMABMR_FB 0x00010000U /* Fixed Burst */

#define	ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */

#define	ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */

#define	ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */

#define	ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */

#define	ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */

#define	ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */

#define	ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */

#define	ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */

#define	ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */

#define	ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */

#define	ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */

#define	ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */

#define	ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */

#define	ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */

#define	ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */

#define	ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */

#define	ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */

#define	ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */

#define	ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */

#define	ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */

#define	ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */

#define	ETH_DMABMR_SR 0x00000001U /* Software reset */

#define	ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */

#define	ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */

#define	ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */

#define	ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */

#define	ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */

#define	ETH_DMASR_PMTS 0x10000000U /* PMT status */

#define	ETH_DMASR_MMCS 0x08000000U /* MMC status */

#define	ETH_DMASR_EBS 0x03800000U /* Error bits status */

#define	ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */

#define	ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */

#define	ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */

#define	ETH_DMASR_TPS 0x00700000U /* Transmit process state */

#define	ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */

#define	ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */

#define	ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */

#define	ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */

#define	ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */

#define	ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */

#define	ETH_DMASR_RPS 0x000E0000U /* Receive process state */

#define	ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */

#define	ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */

#define	ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */

#define	ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */

#define	ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */

#define	ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */

#define	ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */

#define	ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */

#define	ETH_DMASR_ERS 0x00004000U /* Early receive status */

#define	ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */

#define	ETH_DMASR_ETS 0x00000400U /* Early transmit status */

#define	ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */

#define	ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */

#define	ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */

#define	ETH_DMASR_RS 0x00000040U /* Receive status */

#define	ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */

#define	ETH_DMASR_ROS 0x00000010U /* Receive overflow status */

#define	ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */

#define	ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */

#define	ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */

#define	ETH_DMASR_TS 0x00000001U /* Transmit status */

#define	ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */

#define	ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */

#define	ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */

#define	ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */

#define	ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */

#define	ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */

#define	ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */

#define	ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */

#define	ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */

#define	ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */

#define	ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */

#define	ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */

#define	ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */

#define	ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */

#define	ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */

#define	ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */

#define	ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */

#define	ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */

#define	ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */

#define	ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */

#define	ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */

#define	ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */

#define	ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */

#define	ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */

#define	ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */

#define	ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */

#define	ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */

#define	ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */

#define	ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */

#define	ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */

#define	ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */

#define	ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */

#define	ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */

#define	ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */

#define	ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */

#define	ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */

#define	ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */

#define	ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */

#define	ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */

#define	ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */

#define	ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */

#define	ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */

#define	ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */

#define	ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */

#define	ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */

#define	ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */

#define	ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */

#define	USB_OTG_GOTGCTL_SRQSCS 0x00000001U

#define	USB_OTG_GOTGCTL_SRQ 0x00000002U

#define	USB_OTG_GOTGCTL_VBVALOEN 0x00000004U

#define	USB_OTG_GOTGCTL_VBVALOVAL 0x00000008U

#define	USB_OTG_GOTGCTL_AVALOEN 0x00000010U

#define	USB_OTG_GOTGCTL_AVALOVAL 0x00000020U

#define	USB_OTG_GOTGCTL_BVALOEN 0x00000040U

#define	USB_OTG_GOTGCTL_BVALOVAL 0x00000080U

#define	USB_OTG_GOTGCTL_HNGSCS 0x00000100U

#define	USB_OTG_GOTGCTL_HNPRQ 0x00000200U

#define	USB_OTG_GOTGCTL_HSHNPEN 0x00000400U

#define	USB_OTG_GOTGCTL_DHNPEN 0x00000800U

#define	USB_OTG_GOTGCTL_EHEN 0x00001000U

#define	USB_OTG_GOTGCTL_CIDSTS 0x00010000U

#define	USB_OTG_GOTGCTL_DBCT 0x00020000U

#define	USB_OTG_GOTGCTL_ASVLD 0x00040000U

#define	USB_OTG_GOTGCTL_BSESVLD 0x00080000U

#define	USB_OTG_GOTGCTL_OTGVER 0x00100000U

#define	USB_OTG_HCFG_FSLSPCS 0x00000003U

#define	USB_OTG_HCFG_FSLSPCS_0 0x00000001U

#define	USB_OTG_HCFG_FSLSPCS_1 0x00000002U

#define	USB_OTG_HCFG_FSLSS 0x00000004U

#define	USB_OTG_DCFG_DSPD 0x00000003U

#define	USB_OTG_DCFG_DSPD_0 0x00000001U

#define	USB_OTG_DCFG_DSPD_1 0x00000002U

#define	USB_OTG_DCFG_NZLSOHSK 0x00000004U

#define	USB_OTG_DCFG_DAD 0x000007F0U

#define	USB_OTG_DCFG_DAD_0 0x00000010U

#define	USB_OTG_DCFG_DAD_1 0x00000020U

#define	USB_OTG_DCFG_DAD_2 0x00000040U

#define	USB_OTG_DCFG_DAD_3 0x00000080U

#define	USB_OTG_DCFG_DAD_4 0x00000100U

#define	USB_OTG_DCFG_DAD_5 0x00000200U

#define	USB_OTG_DCFG_DAD_6 0x00000400U

#define	USB_OTG_DCFG_PFIVL 0x00001800U

#define	USB_OTG_DCFG_PFIVL_0 0x00000800U

#define	USB_OTG_DCFG_PFIVL_1 0x00001000U

#define	USB_OTG_DCFG_PERSCHIVL 0x03000000U

#define	USB_OTG_DCFG_PERSCHIVL_0 0x01000000U

#define	USB_OTG_DCFG_PERSCHIVL_1 0x02000000U

#define	USB_OTG_PCGCR_STPPCLK 0x00000001U

#define	USB_OTG_PCGCR_GATEHCLK 0x00000002U

#define	USB_OTG_PCGCR_PHYSUSP 0x00000010U

#define	USB_OTG_GOTGINT_SEDET 0x00000004U

#define	USB_OTG_GOTGINT_SRSSCHG 0x00000100U

#define	USB_OTG_GOTGINT_HNSSCHG 0x00000200U

#define	USB_OTG_GOTGINT_HNGDET 0x00020000U

#define	USB_OTG_GOTGINT_ADTOCHG 0x00040000U

#define	USB_OTG_GOTGINT_DBCDNE 0x00080000U

#define	USB_OTG_GOTGINT_IDCHNG 0x00100000U

#define	USB_OTG_DCTL_RWUSIG 0x00000001U

#define	USB_OTG_DCTL_SDIS 0x00000002U

#define	USB_OTG_DCTL_GINSTS 0x00000004U

#define	USB_OTG_DCTL_GONSTS 0x00000008U

#define	USB_OTG_DCTL_TCTL 0x00000070U

#define	USB_OTG_DCTL_TCTL_0 0x00000010U

#define	USB_OTG_DCTL_TCTL_1 0x00000020U

#define	USB_OTG_DCTL_TCTL_2 0x00000040U

#define	USB_OTG_DCTL_SGINAK 0x00000080U

#define	USB_OTG_DCTL_CGINAK 0x00000100U

#define	USB_OTG_DCTL_SGONAK 0x00000200U

#define	USB_OTG_DCTL_CGONAK 0x00000400U

#define	USB_OTG_DCTL_POPRGDNE 0x00000800U

#define	USB_OTG_HFIR_FRIVL 0x0000FFFFU

#define	USB_OTG_HFNUM_FRNUM 0x0000FFFFU

#define	USB_OTG_HFNUM_FTREM 0xFFFF0000U

#define	USB_OTG_DSTS_SUSPSTS 0x00000001U

#define	USB_OTG_DSTS_ENUMSPD 0x00000006U

#define	USB_OTG_DSTS_ENUMSPD_0 0x00000002U

#define	USB_OTG_DSTS_ENUMSPD_1 0x00000004U

#define	USB_OTG_DSTS_EERR 0x00000008U

#define	USB_OTG_DSTS_FNSOF 0x003FFF00U

#define	USB_OTG_GAHBCFG_GINT 0x00000001U

#define	USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU

#define	USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U

#define	USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U

#define	USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U

#define	USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U

#define	USB_OTG_GAHBCFG_DMAEN 0x00000020U

#define	USB_OTG_GAHBCFG_TXFELVL 0x00000080U

#define	USB_OTG_GAHBCFG_PTXFELVL 0x00000100U

#define	USB_OTG_GUSBCFG_TOCAL 0x00000007U

#define	USB_OTG_GUSBCFG_TOCAL_0 0x00000001U

#define	USB_OTG_GUSBCFG_TOCAL_1 0x00000002U

#define	USB_OTG_GUSBCFG_TOCAL_2 0x00000004U

#define	USB_OTG_GUSBCFG_PHYSEL 0x00000040U

#define	USB_OTG_GUSBCFG_SRPCAP 0x00000100U

#define	USB_OTG_GUSBCFG_HNPCAP 0x00000200U

#define	USB_OTG_GUSBCFG_TRDT 0x00003C00U

#define	USB_OTG_GUSBCFG_TRDT_0 0x00000400U

#define	USB_OTG_GUSBCFG_TRDT_1 0x00000800U

#define	USB_OTG_GUSBCFG_TRDT_2 0x00001000U

#define	USB_OTG_GUSBCFG_TRDT_3 0x00002000U

#define	USB_OTG_GUSBCFG_PHYLPCS 0x00008000U

#define	USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U

#define	USB_OTG_GUSBCFG_ULPIAR 0x00040000U

#define	USB_OTG_GUSBCFG_ULPICSM 0x00080000U

#define	USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U

#define	USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U

#define	USB_OTG_GUSBCFG_TSDPS 0x00400000U

#define	USB_OTG_GUSBCFG_PCCI 0x00800000U

#define	USB_OTG_GUSBCFG_PTCI 0x01000000U

#define	USB_OTG_GUSBCFG_ULPIIPD 0x02000000U

#define	USB_OTG_GUSBCFG_FHMOD 0x20000000U

#define	USB_OTG_GUSBCFG_FDMOD 0x40000000U

#define	USB_OTG_GUSBCFG_CTXPKT 0x80000000U

#define	USB_OTG_GRSTCTL_CSRST 0x00000001U

#define	USB_OTG_GRSTCTL_HSRST 0x00000002U

#define	USB_OTG_GRSTCTL_FCRST 0x00000004U

#define	USB_OTG_GRSTCTL_RXFFLSH 0x00000010U

#define	USB_OTG_GRSTCTL_TXFFLSH 0x00000020U

#define	USB_OTG_GRSTCTL_TXFNUM 0x000007C0U

#define	USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U

#define	USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U

#define	USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U

#define	USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U

#define	USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U

#define	USB_OTG_GRSTCTL_DMAREQ 0x40000000U

#define	USB_OTG_GRSTCTL_AHBIDL 0x80000000U

#define	USB_OTG_DIEPMSK_XFRCM 0x00000001U

#define	USB_OTG_DIEPMSK_EPDM 0x00000002U

#define	USB_OTG_DIEPMSK_TOM 0x00000008U

#define	USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U

#define	USB_OTG_DIEPMSK_INEPNMM 0x00000020U

#define	USB_OTG_DIEPMSK_INEPNEM 0x00000040U

#define	USB_OTG_DIEPMSK_TXFURM 0x00000100U

#define	USB_OTG_DIEPMSK_BIM 0x00000200U

#define	USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU

#define	USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U

#define	USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U

#define	USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U

#define	USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U

#define	USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U

#define	USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U

#define	USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U

#define	USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U

#define	USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U

#define	USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U

#define	USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U

#define	USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U

#define	USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U

#define	USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U

#define	USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U

#define	USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U

#define	USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U

#define	USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U

#define	USB_OTG_HAINT_HAINT 0x0000FFFFU

#define	USB_OTG_DOEPMSK_XFRCM 0x00000001U

#define	USB_OTG_DOEPMSK_EPDM 0x00000002U

#define	USB_OTG_DOEPMSK_STUPM 0x00000008U

#define	USB_OTG_DOEPMSK_OTEPDM 0x00000010U

#define	USB_OTG_DOEPMSK_OTEPSPRM 0x00000020U

#define	USB_OTG_DOEPMSK_B2BSTUP 0x00000040U

#define	USB_OTG_DOEPMSK_OPEM 0x00000100U

#define	USB_OTG_DOEPMSK_BOIM 0x00000200U

#define	USB_OTG_GINTSTS_CMOD 0x00000001U

#define	USB_OTG_GINTSTS_MMIS 0x00000002U

#define	USB_OTG_GINTSTS_OTGINT 0x00000004U

#define	USB_OTG_GINTSTS_SOF 0x00000008U

#define	USB_OTG_GINTSTS_RXFLVL 0x00000010U

#define	USB_OTG_GINTSTS_NPTXFE 0x00000020U

#define	USB_OTG_GINTSTS_GINAKEFF 0x00000040U

#define	USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U

#define	USB_OTG_GINTSTS_ESUSP 0x00000400U

#define	USB_OTG_GINTSTS_USBSUSP 0x00000800U

#define	USB_OTG_GINTSTS_USBRST 0x00001000U

#define	USB_OTG_GINTSTS_ENUMDNE 0x00002000U

#define	USB_OTG_GINTSTS_ISOODRP 0x00004000U

#define	USB_OTG_GINTSTS_EOPF 0x00008000U

#define	USB_OTG_GINTSTS_IEPINT 0x00040000U

#define	USB_OTG_GINTSTS_OEPINT 0x00080000U

#define	USB_OTG_GINTSTS_IISOIXFR 0x00100000U

#define	USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U

#define	USB_OTG_GINTSTS_DATAFSUSP 0x00400000U

#define	USB_OTG_GINTSTS_RSTDET 0x00800000U

#define	USB_OTG_GINTSTS_HPRTINT 0x01000000U

#define	USB_OTG_GINTSTS_HCINT 0x02000000U

#define	USB_OTG_GINTSTS_PTXFE 0x04000000U

#define	USB_OTG_GINTSTS_LPMINT 0x08000000U

#define	USB_OTG_GINTSTS_CIDSCHG 0x10000000U

#define	USB_OTG_GINTSTS_DISCINT 0x20000000U

#define	USB_OTG_GINTSTS_SRQINT 0x40000000U

#define	USB_OTG_GINTSTS_WKUINT 0x80000000U

#define	USB_OTG_GINTMSK_MMISM 0x00000002U

#define	USB_OTG_GINTMSK_OTGINT 0x00000004U

#define	USB_OTG_GINTMSK_SOFM 0x00000008U

#define	USB_OTG_GINTMSK_RXFLVLM 0x00000010U

#define	USB_OTG_GINTMSK_NPTXFEM 0x00000020U

#define	USB_OTG_GINTMSK_GINAKEFFM 0x00000040U

#define	USB_OTG_GINTMSK_GONAKEFFM 0x00000080U

#define	USB_OTG_GINTMSK_ESUSPM 0x00000400U

#define	USB_OTG_GINTMSK_USBSUSPM 0x00000800U

#define	USB_OTG_GINTMSK_USBRST 0x00001000U

#define	USB_OTG_GINTMSK_ENUMDNEM 0x00002000U

#define	USB_OTG_GINTMSK_ISOODRPM 0x00004000U

#define	USB_OTG_GINTMSK_EOPFM 0x00008000U

#define	USB_OTG_GINTMSK_EPMISM 0x00020000U

#define	USB_OTG_GINTMSK_IEPINT 0x00040000U

#define	USB_OTG_GINTMSK_OEPINT 0x00080000U

#define	USB_OTG_GINTMSK_IISOIXFRM 0x00100000U

#define	USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U

#define	USB_OTG_GINTMSK_FSUSPM 0x00400000U

#define	USB_OTG_GINTMSK_RSTDEM 0x00800000U

#define	USB_OTG_GINTMSK_PRTIM 0x01000000U

#define	USB_OTG_GINTMSK_HCIM 0x02000000U

#define	USB_OTG_GINTMSK_PTXFEM 0x04000000U

#define	USB_OTG_GINTMSK_LPMINTM 0x08000000U

#define	USB_OTG_GINTMSK_CIDSCHGM 0x10000000U

#define	USB_OTG_GINTMSK_DISCINT 0x20000000U

#define	USB_OTG_GINTMSK_SRQIM 0x40000000U

#define	USB_OTG_GINTMSK_WUIM 0x80000000U

#define	USB_OTG_DAINT_IEPINT 0x0000FFFFU

#define	USB_OTG_DAINT_OEPINT 0xFFFF0000U

#define	USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU

#define	USB_OTG_GRXSTSP_EPNUM 0x0000000FU

#define	USB_OTG_GRXSTSP_BCNT 0x00007FF0U

#define	USB_OTG_GRXSTSP_DPID 0x00018000U

#define	USB_OTG_GRXSTSP_PKTSTS 0x001E0000U

#define	USB_OTG_DAINTMSK_IEPM 0x0000FFFFU

#define	USB_OTG_DAINTMSK_OEPM 0xFFFF0000U

#define	USB_OTG_CHNUM 0x0000000FU

#define	USB_OTG_CHNUM_0 0x00000001U

#define	USB_OTG_CHNUM_1 0x00000002U

#define	USB_OTG_CHNUM_2 0x00000004U

#define	USB_OTG_CHNUM_3 0x00000008U

#define	USB_OTG_BCNT 0x00007FF0U

#define	USB_OTG_DPID 0x00018000U

#define	USB_OTG_DPID_0 0x00008000U

#define	USB_OTG_DPID_1 0x00010000U

#define	USB_OTG_PKTSTS 0x001E0000U

#define	USB_OTG_PKTSTS_0 0x00020000U

#define	USB_OTG_PKTSTS_1 0x00040000U

#define	USB_OTG_PKTSTS_2 0x00080000U

#define	USB_OTG_PKTSTS_3 0x00100000U

#define	USB_OTG_EPNUM 0x0000000FU

#define	USB_OTG_EPNUM_0 0x00000001U

#define	USB_OTG_EPNUM_1 0x00000002U

#define	USB_OTG_EPNUM_2 0x00000004U

#define	USB_OTG_EPNUM_3 0x00000008U

#define	USB_OTG_FRMNUM 0x01E00000U

#define	USB_OTG_FRMNUM_0 0x00200000U

#define	USB_OTG_FRMNUM_1 0x00400000U

#define	USB_OTG_FRMNUM_2 0x00800000U

#define	USB_OTG_FRMNUM_3 0x01000000U

#define	USB_OTG_CHNUM 0x0000000FU

#define	USB_OTG_CHNUM_0 0x00000001U

#define	USB_OTG_CHNUM_1 0x00000002U

#define	USB_OTG_CHNUM_2 0x00000004U

#define	USB_OTG_CHNUM_3 0x00000008U

#define	USB_OTG_BCNT 0x00007FF0U

#define	USB_OTG_DPID 0x00018000U

#define	USB_OTG_DPID_0 0x00008000U

#define	USB_OTG_DPID_1 0x00010000U

#define	USB_OTG_PKTSTS 0x001E0000U

#define	USB_OTG_PKTSTS_0 0x00020000U

#define	USB_OTG_PKTSTS_1 0x00040000U

#define	USB_OTG_PKTSTS_2 0x00080000U

#define	USB_OTG_PKTSTS_3 0x00100000U

#define	USB_OTG_EPNUM 0x0000000FU

#define	USB_OTG_EPNUM_0 0x00000001U

#define	USB_OTG_EPNUM_1 0x00000002U

#define	USB_OTG_EPNUM_2 0x00000004U

#define	USB_OTG_EPNUM_3 0x00000008U

#define	USB_OTG_FRMNUM 0x01E00000U

#define	USB_OTG_FRMNUM_0 0x00200000U

#define	USB_OTG_FRMNUM_1 0x00400000U

#define	USB_OTG_FRMNUM_2 0x00800000U

#define	USB_OTG_FRMNUM_3 0x01000000U

#define	USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU

#define	USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU

#define	USB_OTG_NPTXFSA 0x0000FFFFU

#define	USB_OTG_NPTXFD 0xFFFF0000U

#define	USB_OTG_TX0FSA 0x0000FFFFU

#define	USB_OTG_TX0FD 0xFFFF0000U

#define	USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU

#define	USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU

#define	USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U

#define	USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U

#define	USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U

#define	USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U

#define	USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U

#define	USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U

#define	USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U

#define	USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U

#define	USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U

#define	USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U

#define	USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U

#define	USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U

#define	USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U

#define	USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U

#define	USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U

#define	USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U

#define	USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U

#define	USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U

#define	USB_OTG_DTHRCTL_ISOTHREN 0x00000002U

#define	USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU

#define	USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U

#define	USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U

#define	USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U

#define	USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U

#define	USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U

#define	USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U

#define	USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U

#define	USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U

#define	USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U

#define	USB_OTG_DTHRCTL_RXTHREN 0x00010000U

#define	USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U

#define	USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U

#define	USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U

#define	USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U

#define	USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U

#define	USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U

#define	USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U

#define	USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U

#define	USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U

#define	USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U

#define	USB_OTG_DTHRCTL_ARPEN 0x08000000U

#define	USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU

#define	USB_OTG_DEACHINT_IEP1INT 0x00000002U

#define	USB_OTG_DEACHINT_OEP1INT 0x00020000U

#define	USB_OTG_GCCFG_PWRDWN 0x00010000U

#define	USB_OTG_GCCFG_VBDEN 0x00200000U

#define	USB_OTG_GPWRDN_ADPMEN 0x00000001U

#define	USB_OTG_GPWRDN_ADPIF 0x00800000U

#define	USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U

#define	USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U

#define	USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU

#define	USB_OTG_GLPMCFG_LPMEN 0x00000001U

#define	USB_OTG_GLPMCFG_LPMACK 0x00000002U

#define	USB_OTG_GLPMCFG_BESL 0x0000003CU

#define	USB_OTG_GLPMCFG_REMWAKE 0x00000040U

#define	USB_OTG_GLPMCFG_L1SSEN 0x00000080U

#define	USB_OTG_GLPMCFG_BESLTHRS 0x00000F00U

#define	USB_OTG_GLPMCFG_L1DSEN 0x00001000U

#define	USB_OTG_GLPMCFG_LPMRSP 0x00006000U

#define	USB_OTG_GLPMCFG_SLPSTS 0x00008000U

#define	USB_OTG_GLPMCFG_L1RSMOK 0x00010000U

#define	USB_OTG_GLPMCFG_LPMCHIDX 0x001E0000U

#define	USB_OTG_GLPMCFG_LPMRCNT 0x00E00000U

#define	USB_OTG_GLPMCFG_SNDLPM 0x01000000U

#define	USB_OTG_GLPMCFG_LPMRCNTSTS 0x0E000000U

#define	USB_OTG_GLPMCFG_ENBESL 0x10000000U

#define	USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U

#define	USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U

#define	USB_OTG_DIEPEACHMSK1_TOM 0x00000008U

#define	USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U

#define	USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U

#define	USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U

#define	USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U

#define	USB_OTG_DIEPEACHMSK1_BIM 0x00000200U

#define	USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U

#define	USB_OTG_HPRT_PCSTS 0x00000001U

#define	USB_OTG_HPRT_PCDET 0x00000002U

#define	USB_OTG_HPRT_PENA 0x00000004U

#define	USB_OTG_HPRT_PENCHNG 0x00000008U

#define	USB_OTG_HPRT_POCA 0x00000010U

#define	USB_OTG_HPRT_POCCHNG 0x00000020U

#define	USB_OTG_HPRT_PRES 0x00000040U

#define	USB_OTG_HPRT_PSUSP 0x00000080U

#define	USB_OTG_HPRT_PRST 0x00000100U

#define	USB_OTG_HPRT_PLSTS 0x00000C00U

#define	USB_OTG_HPRT_PLSTS_0 0x00000400U

#define	USB_OTG_HPRT_PLSTS_1 0x00000800U

#define	USB_OTG_HPRT_PPWR 0x00001000U

#define	USB_OTG_HPRT_PTCTL 0x0001E000U

#define	USB_OTG_HPRT_PTCTL_0 0x00002000U

#define	USB_OTG_HPRT_PTCTL_1 0x00004000U

#define	USB_OTG_HPRT_PTCTL_2 0x00008000U

#define	USB_OTG_HPRT_PTCTL_3 0x00010000U

#define	USB_OTG_HPRT_PSPD 0x00060000U

#define	USB_OTG_HPRT_PSPD_0 0x00020000U

#define	USB_OTG_HPRT_PSPD_1 0x00040000U

#define	USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U

#define	USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U

#define	USB_OTG_DOEPEACHMSK1_TOM 0x00000008U

#define	USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U

#define	USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U

#define	USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U

#define	USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U

#define	USB_OTG_DOEPEACHMSK1_BIM 0x00000200U

#define	USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U

#define	USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U

#define	USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U

#define	USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU

#define	USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U

#define	USB_OTG_DIEPCTL_MPSIZ 0x000007FFU

#define	USB_OTG_DIEPCTL_USBAEP 0x00008000U

#define	USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U

#define	USB_OTG_DIEPCTL_NAKSTS 0x00020000U

#define	USB_OTG_DIEPCTL_EPTYP 0x000C0000U

#define	USB_OTG_DIEPCTL_EPTYP_0 0x00040000U

#define	USB_OTG_DIEPCTL_EPTYP_1 0x00080000U

#define	USB_OTG_DIEPCTL_STALL 0x00200000U

#define	USB_OTG_DIEPCTL_TXFNUM 0x03C00000U

#define	USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U

#define	USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U

#define	USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U

#define	USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U

#define	USB_OTG_DIEPCTL_CNAK 0x04000000U

#define	USB_OTG_DIEPCTL_SNAK 0x08000000U

#define	USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U

#define	USB_OTG_DIEPCTL_SODDFRM 0x20000000U

#define	USB_OTG_DIEPCTL_EPDIS 0x40000000U

#define	USB_OTG_DIEPCTL_EPENA 0x80000000U

#define	USB_OTG_HCCHAR_MPSIZ 0x000007FFU

#define	USB_OTG_HCCHAR_EPNUM 0x00007800U

#define	USB_OTG_HCCHAR_EPNUM_0 0x00000800U

#define	USB_OTG_HCCHAR_EPNUM_1 0x00001000U

#define	USB_OTG_HCCHAR_EPNUM_2 0x00002000U

#define	USB_OTG_HCCHAR_EPNUM_3 0x00004000U

#define	USB_OTG_HCCHAR_EPDIR 0x00008000U

#define	USB_OTG_HCCHAR_LSDEV 0x00020000U

#define	USB_OTG_HCCHAR_EPTYP 0x000C0000U

#define	USB_OTG_HCCHAR_EPTYP_0 0x00040000U

#define	USB_OTG_HCCHAR_EPTYP_1 0x00080000U

#define	USB_OTG_HCCHAR_MC 0x00300000U

#define	USB_OTG_HCCHAR_MC_0 0x00100000U

#define	USB_OTG_HCCHAR_MC_1 0x00200000U

#define	USB_OTG_HCCHAR_DAD 0x1FC00000U

#define	USB_OTG_HCCHAR_DAD_0 0x00400000U

#define	USB_OTG_HCCHAR_DAD_1 0x00800000U

#define	USB_OTG_HCCHAR_DAD_2 0x01000000U

#define	USB_OTG_HCCHAR_DAD_3 0x02000000U

#define	USB_OTG_HCCHAR_DAD_4 0x04000000U

#define	USB_OTG_HCCHAR_DAD_5 0x08000000U

#define	USB_OTG_HCCHAR_DAD_6 0x10000000U

#define	USB_OTG_HCCHAR_ODDFRM 0x20000000U

#define	USB_OTG_HCCHAR_CHDIS 0x40000000U

#define	USB_OTG_HCCHAR_CHENA 0x80000000U

#define	USB_OTG_HCSPLT_PRTADDR 0x0000007FU

#define	USB_OTG_HCSPLT_PRTADDR_0 0x00000001U

#define	USB_OTG_HCSPLT_PRTADDR_1 0x00000002U

#define	USB_OTG_HCSPLT_PRTADDR_2 0x00000004U

#define	USB_OTG_HCSPLT_PRTADDR_3 0x00000008U

#define	USB_OTG_HCSPLT_PRTADDR_4 0x00000010U

#define	USB_OTG_HCSPLT_PRTADDR_5 0x00000020U

#define	USB_OTG_HCSPLT_PRTADDR_6 0x00000040U

#define	USB_OTG_HCSPLT_HUBADDR 0x00003F80U

#define	USB_OTG_HCSPLT_HUBADDR_0 0x00000080U

#define	USB_OTG_HCSPLT_HUBADDR_1 0x00000100U

#define	USB_OTG_HCSPLT_HUBADDR_2 0x00000200U

#define	USB_OTG_HCSPLT_HUBADDR_3 0x00000400U

#define	USB_OTG_HCSPLT_HUBADDR_4 0x00000800U

#define	USB_OTG_HCSPLT_HUBADDR_5 0x00001000U

#define	USB_OTG_HCSPLT_HUBADDR_6 0x00002000U

#define	USB_OTG_HCSPLT_XACTPOS 0x0000C000U

#define	USB_OTG_HCSPLT_XACTPOS_0 0x00004000U

#define	USB_OTG_HCSPLT_XACTPOS_1 0x00008000U

#define	USB_OTG_HCSPLT_COMPLSPLT 0x00010000U

#define	USB_OTG_HCSPLT_SPLITEN 0x80000000U

#define	USB_OTG_HCINT_XFRC 0x00000001U

#define	USB_OTG_HCINT_CHH 0x00000002U

#define	USB_OTG_HCINT_AHBERR 0x00000004U

#define	USB_OTG_HCINT_STALL 0x00000008U

#define	USB_OTG_HCINT_NAK 0x00000010U

#define	USB_OTG_HCINT_ACK 0x00000020U

#define	USB_OTG_HCINT_NYET 0x00000040U

#define	USB_OTG_HCINT_TXERR 0x00000080U

#define	USB_OTG_HCINT_BBERR 0x00000100U

#define	USB_OTG_HCINT_FRMOR 0x00000200U

#define	USB_OTG_HCINT_DTERR 0x00000400U

#define	USB_OTG_DIEPINT_XFRC 0x00000001U

#define	USB_OTG_DIEPINT_EPDISD 0x00000002U

#define	USB_OTG_DIEPINT_TOC 0x00000008U

#define	USB_OTG_DIEPINT_ITTXFE 0x00000010U

#define	USB_OTG_DIEPINT_INEPNE 0x00000040U

#define	USB_OTG_DIEPINT_TXFE 0x00000080U

#define	USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U

#define	USB_OTG_DIEPINT_BNA 0x00000200U

#define	USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U

#define	USB_OTG_DIEPINT_BERR 0x00001000U

#define	USB_OTG_DIEPINT_NAK 0x00002000U

#define	USB_OTG_HCINTMSK_XFRCM 0x00000001U

#define	USB_OTG_HCINTMSK_CHHM 0x00000002U

#define	USB_OTG_HCINTMSK_AHBERR 0x00000004U

#define	USB_OTG_HCINTMSK_STALLM 0x00000008U

#define	USB_OTG_HCINTMSK_NAKM 0x00000010U

#define	USB_OTG_HCINTMSK_ACKM 0x00000020U

#define	USB_OTG_HCINTMSK_NYET 0x00000040U

#define	USB_OTG_HCINTMSK_TXERRM 0x00000080U

#define	USB_OTG_HCINTMSK_BBERRM 0x00000100U

#define	USB_OTG_HCINTMSK_FRMORM 0x00000200U

#define	USB_OTG_HCINTMSK_DTERRM 0x00000400U

#define	USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU

#define	USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U

#define	USB_OTG_DIEPTSIZ_MULCNT 0x60000000U

#define	USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU

#define	USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U

#define	USB_OTG_HCTSIZ_DOPING 0x80000000U

#define	USB_OTG_HCTSIZ_DPID 0x60000000U

#define	USB_OTG_HCTSIZ_DPID_0 0x20000000U

#define	USB_OTG_HCTSIZ_DPID_1 0x40000000U

#define	USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU

#define	USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU

#define	USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU

#define	USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU

#define	USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U

#define	USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /!< Maximum packet size /

#define	USB_OTG_DOEPCTL_USBAEP 0x00008000U

#define	USB_OTG_DOEPCTL_NAKSTS 0x00020000U

#define	USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U

#define	USB_OTG_DOEPCTL_SODDFRM 0x20000000U

#define	USB_OTG_DOEPCTL_EPTYP 0x000C0000U

#define	USB_OTG_DOEPCTL_EPTYP_0 0x00040000U

#define	USB_OTG_DOEPCTL_EPTYP_1 0x00080000U

#define	USB_OTG_DOEPCTL_SNPM 0x00100000U

#define	USB_OTG_DOEPCTL_STALL 0x00200000U

#define	USB_OTG_DOEPCTL_CNAK 0x04000000U

#define	USB_OTG_DOEPCTL_SNAK 0x08000000U

#define	USB_OTG_DOEPCTL_EPDIS 0x40000000U

#define	USB_OTG_DOEPCTL_EPENA 0x80000000U

#define	USB_OTG_DOEPINT_XFRC 0x00000001U

#define	USB_OTG_DOEPINT_EPDISD 0x00000002U

#define	USB_OTG_DOEPINT_STUP 0x00000008U

#define	USB_OTG_DOEPINT_OTEPDIS 0x00000010U

#define	USB_OTG_DOEPINT_OTEPSPR 0x00000020U

#define	USB_OTG_DOEPINT_B2BSTUP 0x00000040U

#define	USB_OTG_DOEPINT_NYET 0x00004000U

#define	USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU

#define	USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U

#define	USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U

#define	USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U

#define	USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U

#define	USB_OTG_PCGCCTL_STOPCLK 0x00000001U

#define	USB_OTG_PCGCCTL_GATECLK 0x00000002U

#define	USB_OTG_PCGCCTL_PHYSUSP 0x00000010U

#define	IS_ADC_ALL_INSTANCE(__INSTANCE__)

#define	IS_CAN_ALL_INSTANCE(__INSTANCE__)

#define	IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)

#define	IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)

#define	IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)

#define	IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)

#define	IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__)

#define	IS_GPIO_ALL_INSTANCE(__INSTANCE__)

#define	IS_GPIO_AF_INSTANCE(__INSTANCE__)

#define	IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)

#define	IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)

#define	IS_I2C_ALL_INSTANCE(__INSTANCE__)

#define	IS_I2S_ALL_INSTANCE(__INSTANCE__)

#define	IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)

#define	IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)

#define	IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)

#define	IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)

#define	IS_SAI_ALL_INSTANCE(__PERIPH__)

#define	IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE

#define	IS_SDMMC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SDMMC1)

#define	IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)

#define	IS_SPI_ALL_INSTANCE(__INSTANCE__)

#define	IS_TIM_INSTANCE(__INSTANCE__)

#define	IS_TIM_CC1_INSTANCE(__INSTANCE__)

#define	IS_TIM_CC2_INSTANCE(__INSTANCE__)

#define	IS_TIM_CC3_INSTANCE(__INSTANCE__)

#define	IS_TIM_CC4_INSTANCE(__INSTANCE__)

#define	IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__)

#define	IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)

#define	IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)

#define	IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)

#define	IS_TIM_CC5_INSTANCE(__INSTANCE__)

#define	IS_TIM_CC6_INSTANCE(__INSTANCE__)

#define	IS_TIM_ADVANCED_INSTANCE(__INSTANCE__)

#define	IS_TIM_BREAK_INSTANCE(__INSTANCE__)

#define	IS_TIM_XOR_INSTANCE(__INSTANCE__)

#define	IS_TIM_DMA_INSTANCE(__INSTANCE__)

#define	IS_TIM_DMA_CC_INSTANCE(__INSTANCE__)

#define	IS_TIM_CCDMA_INSTANCE(__INSTANCE__)

#define	IS_TIM_DMABURST_INSTANCE(__INSTANCE__)

#define	IS_TIM_MASTER_INSTANCE(__INSTANCE__)

#define	IS_TIM_SLAVE_INSTANCE(__INSTANCE__)

#define	IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)

#define	IS_TIM_ETR_INSTANCE(__INSTANCE__)

#define	IS_TIM_REMAP_INSTANCE(__INSTANCE__)

#define	IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__)

#define	IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__)

#define	IS_TIM_TRGO2_INSTANCE(__INSTANCE__)

#define	IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)

#define	IS_USART_INSTANCE(__INSTANCE__)

#define	IS_UART_INSTANCE(__INSTANCE__)

#define	IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__)

#define	IS_UART_HWFLOW_INSTANCE(__INSTANCE__)

#define	IS_SMARTCARD_INSTANCE(__INSTANCE__)

#define	IS_IRDA_INSTANCE(__INSTANCE__)

#define	IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)

#define	IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)

#define	RNG_IRQn HASH_RNG_IRQn

#define	RNG_IRQHandler HASH_RNG_IRQHandler

Enumerations
enum	IRQn_Type { NonMaskableInt_IRQn = -14, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, WWDG_IRQn = 0, PVD_IRQn = 1, TAMP_STAMP_IRQn = 2, RTC_WKUP_IRQn = 3, FLASH_IRQn = 4, RCC_IRQn = 5, EXTI0_IRQn = 6, EXTI1_IRQn = 7, EXTI2_IRQn = 8, EXTI3_IRQn = 9, EXTI4_IRQn = 10, DMA1_Stream0_IRQn = 11, DMA1_Stream1_IRQn = 12, DMA1_Stream2_IRQn = 13, DMA1_Stream3_IRQn = 14, DMA1_Stream4_IRQn = 15, DMA1_Stream5_IRQn = 16, DMA1_Stream6_IRQn = 17, ADC_IRQn = 18, CAN1_TX_IRQn = 19, CAN1_RX0_IRQn = 20, CAN1_RX1_IRQn = 21, CAN1_SCE_IRQn = 22, EXTI9_5_IRQn = 23, TIM1_BRK_TIM9_IRQn = 24, TIM1_UP_TIM10_IRQn = 25, TIM1_TRG_COM_TIM11_IRQn = 26, TIM1_CC_IRQn = 27, TIM2_IRQn = 28, TIM3_IRQn = 29, TIM4_IRQn = 30, I2C1_EV_IRQn = 31, I2C1_ER_IRQn = 32, I2C2_EV_IRQn = 33, I2C2_ER_IRQn = 34, SPI1_IRQn = 35, SPI2_IRQn = 36, USART1_IRQn = 37, USART2_IRQn = 38, USART3_IRQn = 39, EXTI15_10_IRQn = 40, RTC_Alarm_IRQn = 41, OTG_FS_WKUP_IRQn = 42, TIM8_BRK_TIM12_IRQn = 43, TIM8_UP_TIM13_IRQn = 44, TIM8_TRG_COM_TIM14_IRQn = 45, TIM8_CC_IRQn = 46, DMA1_Stream7_IRQn = 47, FMC_IRQn = 48, SDMMC1_IRQn = 49, TIM5_IRQn = 50, SPI3_IRQn = 51, UART4_IRQn = 52, UART5_IRQn = 53, TIM6_DAC_IRQn = 54, TIM7_IRQn = 55, DMA2_Stream0_IRQn = 56, DMA2_Stream1_IRQn = 57, DMA2_Stream2_IRQn = 58, DMA2_Stream3_IRQn = 59, DMA2_Stream4_IRQn = 60, ETH_IRQn = 61, ETH_WKUP_IRQn = 62, CAN2_TX_IRQn = 63, CAN2_RX0_IRQn = 64, CAN2_RX1_IRQn = 65, CAN2_SCE_IRQn = 66, OTG_FS_IRQn = 67, DMA2_Stream5_IRQn = 68, DMA2_Stream6_IRQn = 69, DMA2_Stream7_IRQn = 70, USART6_IRQn = 71, I2C3_EV_IRQn = 72, I2C3_ER_IRQn = 73, OTG_HS_EP1_OUT_IRQn = 74, OTG_HS_EP1_IN_IRQn = 75, OTG_HS_WKUP_IRQn = 76, OTG_HS_IRQn = 77, DCMI_IRQn = 78, RNG_IRQn = 80, FPU_IRQn = 81, UART7_IRQn = 82, UART8_IRQn = 83, SPI4_IRQn = 84, SPI5_IRQn = 85, SPI6_IRQn = 86, SAI1_IRQn = 87, DMA2D_IRQn = 90, SAI2_IRQn = 91, QUADSPI_IRQn = 92, LPTIM1_IRQn = 93, CEC_IRQn = 94, I2C4_EV_IRQn = 95, I2C4_ER_IRQn = 96, SPDIF_RX_IRQn = 97, NonMaskableInt_IRQn = -14, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, WWDG_IRQn = 0, PVD_IRQn = 1, TAMP_STAMP_IRQn = 2, RTC_WKUP_IRQn = 3, FLASH_IRQn = 4, RCC_IRQn = 5, EXTI0_IRQn = 6, EXTI1_IRQn = 7, EXTI2_IRQn = 8, EXTI3_IRQn = 9, EXTI4_IRQn = 10, DMA1_Stream0_IRQn = 11, DMA1_Stream1_IRQn = 12, DMA1_Stream2_IRQn = 13, DMA1_Stream3_IRQn = 14, DMA1_Stream4_IRQn = 15, DMA1_Stream5_IRQn = 16, DMA1_Stream6_IRQn = 17, ADC_IRQn = 18, CAN1_TX_IRQn = 19, CAN1_RX0_IRQn = 20, CAN1_RX1_IRQn = 21, CAN1_SCE_IRQn = 22, EXTI9_5_IRQn = 23, TIM1_BRK_TIM9_IRQn = 24, TIM1_UP_TIM10_IRQn = 25, TIM1_TRG_COM_TIM11_IRQn = 26, TIM1_CC_IRQn = 27, TIM2_IRQn = 28, TIM3_IRQn = 29, TIM4_IRQn = 30, I2C1_EV_IRQn = 31, I2C1_ER_IRQn = 32, I2C2_EV_IRQn = 33, I2C2_ER_IRQn = 34, SPI1_IRQn = 35, SPI2_IRQn = 36, USART1_IRQn = 37, USART2_IRQn = 38, USART3_IRQn = 39, EXTI15_10_IRQn = 40, RTC_Alarm_IRQn = 41, OTG_FS_WKUP_IRQn = 42, TIM8_BRK_TIM12_IRQn = 43, TIM8_UP_TIM13_IRQn = 44, TIM8_TRG_COM_TIM14_IRQn = 45, TIM8_CC_IRQn = 46, DMA1_Stream7_IRQn = 47, FMC_IRQn = 48, SDMMC1_IRQn = 49, TIM5_IRQn = 50, SPI3_IRQn = 51, UART4_IRQn = 52, UART5_IRQn = 53, TIM6_DAC_IRQn = 54, TIM7_IRQn = 55, DMA2_Stream0_IRQn = 56, DMA2_Stream1_IRQn = 57, DMA2_Stream2_IRQn = 58, DMA2_Stream3_IRQn = 59, DMA2_Stream4_IRQn = 60, ETH_IRQn = 61, ETH_WKUP_IRQn = 62, CAN2_TX_IRQn = 63, CAN2_RX0_IRQn = 64, CAN2_RX1_IRQn = 65, CAN2_SCE_IRQn = 66, OTG_FS_IRQn = 67, DMA2_Stream5_IRQn = 68, DMA2_Stream6_IRQn = 69, DMA2_Stream7_IRQn = 70, USART6_IRQn = 71, I2C3_EV_IRQn = 72, I2C3_ER_IRQn = 73, OTG_HS_EP1_OUT_IRQn = 74, OTG_HS_EP1_IN_IRQn = 75, OTG_HS_WKUP_IRQn = 76, OTG_HS_IRQn = 77, DCMI_IRQn = 78, RNG_IRQn = 80, FPU_IRQn = 81, UART7_IRQn = 82, UART8_IRQn = 83, SPI4_IRQn = 84, SPI5_IRQn = 85, SPI6_IRQn = 86, SAI1_IRQn = 87, LTDC_IRQn = 88, LTDC_ER_IRQn = 89, DMA2D_IRQn = 90, SAI2_IRQn = 91, QUADSPI_IRQn = 92, LPTIM1_IRQn = 93, CEC_IRQn = 94, I2C4_EV_IRQn = 95, I2C4_ER_IRQn = 96, SPDIF_RX_IRQn = 97, NonMaskableInt_IRQn = -14, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, WWDG_IRQn = 0, PVD_IRQn = 1, TAMP_STAMP_IRQn = 2, RTC_WKUP_IRQn = 3, FLASH_IRQn = 4, RCC_IRQn = 5, EXTI0_IRQn = 6, EXTI1_IRQn = 7, EXTI2_IRQn = 8, EXTI3_IRQn = 9, EXTI4_IRQn = 10, DMA1_Stream0_IRQn = 11, DMA1_Stream1_IRQn = 12, DMA1_Stream2_IRQn = 13, DMA1_Stream3_IRQn = 14, DMA1_Stream4_IRQn = 15, DMA1_Stream5_IRQn = 16, DMA1_Stream6_IRQn = 17, ADC_IRQn = 18, CAN1_TX_IRQn = 19, CAN1_RX0_IRQn = 20, CAN1_RX1_IRQn = 21, CAN1_SCE_IRQn = 22, EXTI9_5_IRQn = 23, TIM1_BRK_TIM9_IRQn = 24, TIM1_UP_TIM10_IRQn = 25, TIM1_TRG_COM_TIM11_IRQn = 26, TIM1_CC_IRQn = 27, TIM2_IRQn = 28, TIM3_IRQn = 29, TIM4_IRQn = 30, I2C1_EV_IRQn = 31, I2C1_ER_IRQn = 32, I2C2_EV_IRQn = 33, I2C2_ER_IRQn = 34, SPI1_IRQn = 35, SPI2_IRQn = 36, USART1_IRQn = 37, USART2_IRQn = 38, USART3_IRQn = 39, EXTI15_10_IRQn = 40, RTC_Alarm_IRQn = 41, OTG_FS_WKUP_IRQn = 42, TIM8_BRK_TIM12_IRQn = 43, TIM8_UP_TIM13_IRQn = 44, TIM8_TRG_COM_TIM14_IRQn = 45, TIM8_CC_IRQn = 46, DMA1_Stream7_IRQn = 47, FMC_IRQn = 48, SDMMC1_IRQn = 49, TIM5_IRQn = 50, SPI3_IRQn = 51, UART4_IRQn = 52, UART5_IRQn = 53, TIM6_DAC_IRQn = 54, TIM7_IRQn = 55, DMA2_Stream0_IRQn = 56, DMA2_Stream1_IRQn = 57, DMA2_Stream2_IRQn = 58, DMA2_Stream3_IRQn = 59, DMA2_Stream4_IRQn = 60, ETH_IRQn = 61, ETH_WKUP_IRQn = 62, CAN2_TX_IRQn = 63, CAN2_RX0_IRQn = 64, CAN2_RX1_IRQn = 65, CAN2_SCE_IRQn = 66, OTG_FS_IRQn = 67, DMA2_Stream5_IRQn = 68, DMA2_Stream6_IRQn = 69, DMA2_Stream7_IRQn = 70, USART6_IRQn = 71, I2C3_EV_IRQn = 72, I2C3_ER_IRQn = 73, OTG_HS_EP1_OUT_IRQn = 74, OTG_HS_EP1_IN_IRQn = 75, OTG_HS_WKUP_IRQn = 76, OTG_HS_IRQn = 77, DCMI_IRQn = 78, CRYP_IRQn = 79, HASH_RNG_IRQn = 80, FPU_IRQn = 81, UART7_IRQn = 82, UART8_IRQn = 83, SPI4_IRQn = 84, SPI5_IRQn = 85, SPI6_IRQn = 86, SAI1_IRQn = 87, LTDC_IRQn = 88, LTDC_ER_IRQn = 89, DMA2D_IRQn = 90, SAI2_IRQn = 91, QUADSPI_IRQn = 92, LPTIM1_IRQn = 93, CEC_IRQn = 94, I2C4_EV_IRQn = 95, I2C4_ER_IRQn = 96, SPDIF_RX_IRQn = 97, NonMaskableInt_IRQn = -14, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, WWDG_IRQn = 0, PVD_IRQn = 1, TAMP_STAMP_IRQn = 2, RTC_WKUP_IRQn = 3, FLASH_IRQn = 4, RCC_IRQn = 5, EXTI0_IRQn = 6, EXTI1_IRQn = 7, EXTI2_IRQn = 8, EXTI3_IRQn = 9, EXTI4_IRQn = 10, DMA1_Stream0_IRQn = 11, DMA1_Stream1_IRQn = 12, DMA1_Stream2_IRQn = 13, DMA1_Stream3_IRQn = 14, DMA1_Stream4_IRQn = 15, DMA1_Stream5_IRQn = 16, DMA1_Stream6_IRQn = 17, ADC_IRQn = 18, CAN1_TX_IRQn = 19, CAN1_RX0_IRQn = 20, CAN1_RX1_IRQn = 21, CAN1_SCE_IRQn = 22, EXTI9_5_IRQn = 23, TIM1_BRK_TIM9_IRQn = 24, TIM1_UP_TIM10_IRQn = 25, TIM1_TRG_COM_TIM11_IRQn = 26, TIM1_CC_IRQn = 27, TIM2_IRQn = 28, TIM3_IRQn = 29, TIM4_IRQn = 30, I2C1_EV_IRQn = 31, I2C1_ER_IRQn = 32, I2C2_EV_IRQn = 33, I2C2_ER_IRQn = 34, SPI1_IRQn = 35, SPI2_IRQn = 36, USART1_IRQn = 37, USART2_IRQn = 38, USART3_IRQn = 39, EXTI15_10_IRQn = 40, RTC_Alarm_IRQn = 41, OTG_FS_WKUP_IRQn = 42, TIM8_BRK_TIM12_IRQn = 43, TIM8_UP_TIM13_IRQn = 44, TIM8_TRG_COM_TIM14_IRQn = 45, TIM8_CC_IRQn = 46, DMA1_Stream7_IRQn = 47, FMC_IRQn = 48, SDMMC1_IRQn = 49, TIM5_IRQn = 50, SPI3_IRQn = 51, UART4_IRQn = 52, UART5_IRQn = 53, TIM6_DAC_IRQn = 54, TIM7_IRQn = 55, DMA2_Stream0_IRQn = 56, DMA2_Stream1_IRQn = 57, DMA2_Stream2_IRQn = 58, DMA2_Stream3_IRQn = 59, DMA2_Stream4_IRQn = 60, ETH_IRQn = 61, ETH_WKUP_IRQn = 62, CAN2_TX_IRQn = 63, CAN2_RX0_IRQn = 64, CAN2_RX1_IRQn = 65, CAN2_SCE_IRQn = 66, OTG_FS_IRQn = 67, DMA2_Stream5_IRQn = 68, DMA2_Stream6_IRQn = 69, DMA2_Stream7_IRQn = 70, USART6_IRQn = 71, I2C3_EV_IRQn = 72, I2C3_ER_IRQn = 73, OTG_HS_EP1_OUT_IRQn = 74, OTG_HS_EP1_IN_IRQn = 75, OTG_HS_WKUP_IRQn = 76, OTG_HS_IRQn = 77, DCMI_IRQn = 78, RNG_IRQn = 80, FPU_IRQn = 81, UART7_IRQn = 82, UART8_IRQn = 83, SPI4_IRQn = 84, SPI5_IRQn = 85, SPI6_IRQn = 86, SAI1_IRQn = 87, DMA2D_IRQn = 90, SAI2_IRQn = 91, QUADSPI_IRQn = 92, LPTIM1_IRQn = 93, CEC_IRQn = 94, I2C4_EV_IRQn = 95, I2C4_ER_IRQn = 96, SPDIF_RX_IRQn = 97, DFSDM1_FLT0_IRQn = 99, DFSDM1_FLT1_IRQn = 100, DFSDM1_FLT2_IRQn = 101, DFSDM1_FLT3_IRQn = 102, SDMMC2_IRQn = 103, CAN3_TX_IRQn = 104, CAN3_RX0_IRQn = 105, CAN3_RX1_IRQn = 106, CAN3_SCE_IRQn = 107, MDIOS_IRQn = 109, NonMaskableInt_IRQn = -14, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, WWDG_IRQn = 0, PVD_IRQn = 1, TAMP_STAMP_IRQn = 2, RTC_WKUP_IRQn = 3, FLASH_IRQn = 4, RCC_IRQn = 5, EXTI0_IRQn = 6, EXTI1_IRQn = 7, EXTI2_IRQn = 8, EXTI3_IRQn = 9, EXTI4_IRQn = 10, DMA1_Stream0_IRQn = 11, DMA1_Stream1_IRQn = 12, DMA1_Stream2_IRQn = 13, DMA1_Stream3_IRQn = 14, DMA1_Stream4_IRQn = 15, DMA1_Stream5_IRQn = 16, DMA1_Stream6_IRQn = 17, ADC_IRQn = 18, CAN1_TX_IRQn = 19, CAN1_RX0_IRQn = 20, CAN1_RX1_IRQn = 21, CAN1_SCE_IRQn = 22, EXTI9_5_IRQn = 23, TIM1_BRK_TIM9_IRQn = 24, TIM1_UP_TIM10_IRQn = 25, TIM1_TRG_COM_TIM11_IRQn = 26, TIM1_CC_IRQn = 27, TIM2_IRQn = 28, TIM3_IRQn = 29, TIM4_IRQn = 30, I2C1_EV_IRQn = 31, I2C1_ER_IRQn = 32, I2C2_EV_IRQn = 33, I2C2_ER_IRQn = 34, SPI1_IRQn = 35, SPI2_IRQn = 36, USART1_IRQn = 37, USART2_IRQn = 38, USART3_IRQn = 39, EXTI15_10_IRQn = 40, RTC_Alarm_IRQn = 41, OTG_FS_WKUP_IRQn = 42, TIM8_BRK_TIM12_IRQn = 43, TIM8_UP_TIM13_IRQn = 44, TIM8_TRG_COM_TIM14_IRQn = 45, TIM8_CC_IRQn = 46, DMA1_Stream7_IRQn = 47, FMC_IRQn = 48, SDMMC1_IRQn = 49, TIM5_IRQn = 50, SPI3_IRQn = 51, UART4_IRQn = 52, UART5_IRQn = 53, TIM6_DAC_IRQn = 54, TIM7_IRQn = 55, DMA2_Stream0_IRQn = 56, DMA2_Stream1_IRQn = 57, DMA2_Stream2_IRQn = 58, DMA2_Stream3_IRQn = 59, DMA2_Stream4_IRQn = 60, ETH_IRQn = 61, ETH_WKUP_IRQn = 62, CAN2_TX_IRQn = 63, CAN2_RX0_IRQn = 64, CAN2_RX1_IRQn = 65, CAN2_SCE_IRQn = 66, OTG_FS_IRQn = 67, DMA2_Stream5_IRQn = 68, DMA2_Stream6_IRQn = 69, DMA2_Stream7_IRQn = 70, USART6_IRQn = 71, I2C3_EV_IRQn = 72, I2C3_ER_IRQn = 73, OTG_HS_EP1_OUT_IRQn = 74, OTG_HS_EP1_IN_IRQn = 75, OTG_HS_WKUP_IRQn = 76, OTG_HS_IRQn = 77, DCMI_IRQn = 78, RNG_IRQn = 80, FPU_IRQn = 81, UART7_IRQn = 82, UART8_IRQn = 83, SPI4_IRQn = 84, SPI5_IRQn = 85, SPI6_IRQn = 86, SAI1_IRQn = 87, LTDC_IRQn = 88, LTDC_ER_IRQn = 89, DMA2D_IRQn = 90, SAI2_IRQn = 91, QUADSPI_IRQn = 92, LPTIM1_IRQn = 93, CEC_IRQn = 94, I2C4_EV_IRQn = 95, I2C4_ER_IRQn = 96, SPDIF_RX_IRQn = 97, DFSDM1_FLT0_IRQn = 99, DFSDM1_FLT1_IRQn = 100, DFSDM1_FLT2_IRQn = 101, DFSDM1_FLT3_IRQn = 102, SDMMC2_IRQn = 103, CAN3_TX_IRQn = 104, CAN3_RX0_IRQn = 105, CAN3_RX1_IRQn = 106, CAN3_SCE_IRQn = 107, JPEG_IRQn = 108, MDIOS_IRQn = 109, NonMaskableInt_IRQn = -14, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, WWDG_IRQn = 0, PVD_IRQn = 1, TAMP_STAMP_IRQn = 2, RTC_WKUP_IRQn = 3, FLASH_IRQn = 4, RCC_IRQn = 5, EXTI0_IRQn = 6, EXTI1_IRQn = 7, EXTI2_IRQn = 8, EXTI3_IRQn = 9, EXTI4_IRQn = 10, DMA1_Stream0_IRQn = 11, DMA1_Stream1_IRQn = 12, DMA1_Stream2_IRQn = 13, DMA1_Stream3_IRQn = 14, DMA1_Stream4_IRQn = 15, DMA1_Stream5_IRQn = 16, DMA1_Stream6_IRQn = 17, ADC_IRQn = 18, CAN1_TX_IRQn = 19, CAN1_RX0_IRQn = 20, CAN1_RX1_IRQn = 21, CAN1_SCE_IRQn = 22, EXTI9_5_IRQn = 23, TIM1_BRK_TIM9_IRQn = 24, TIM1_UP_TIM10_IRQn = 25, TIM1_TRG_COM_TIM11_IRQn = 26, TIM1_CC_IRQn = 27, TIM2_IRQn = 28, TIM3_IRQn = 29, TIM4_IRQn = 30, I2C1_EV_IRQn = 31, I2C1_ER_IRQn = 32, I2C2_EV_IRQn = 33, I2C2_ER_IRQn = 34, SPI1_IRQn = 35, SPI2_IRQn = 36, USART1_IRQn = 37, USART2_IRQn = 38, USART3_IRQn = 39, EXTI15_10_IRQn = 40, RTC_Alarm_IRQn = 41, OTG_FS_WKUP_IRQn = 42, TIM8_BRK_TIM12_IRQn = 43, TIM8_UP_TIM13_IRQn = 44, TIM8_TRG_COM_TIM14_IRQn = 45, TIM8_CC_IRQn = 46, DMA1_Stream7_IRQn = 47, FMC_IRQn = 48, SDMMC1_IRQn = 49, TIM5_IRQn = 50, SPI3_IRQn = 51, UART4_IRQn = 52, UART5_IRQn = 53, TIM6_DAC_IRQn = 54, TIM7_IRQn = 55, DMA2_Stream0_IRQn = 56, DMA2_Stream1_IRQn = 57, DMA2_Stream2_IRQn = 58, DMA2_Stream3_IRQn = 59, DMA2_Stream4_IRQn = 60, ETH_IRQn = 61, ETH_WKUP_IRQn = 62, CAN2_TX_IRQn = 63, CAN2_RX0_IRQn = 64, CAN2_RX1_IRQn = 65, CAN2_SCE_IRQn = 66, OTG_FS_IRQn = 67, DMA2_Stream5_IRQn = 68, DMA2_Stream6_IRQn = 69, DMA2_Stream7_IRQn = 70, USART6_IRQn = 71, I2C3_EV_IRQn = 72, I2C3_ER_IRQn = 73, OTG_HS_EP1_OUT_IRQn = 74, OTG_HS_EP1_IN_IRQn = 75, OTG_HS_WKUP_IRQn = 76, OTG_HS_IRQn = 77, DCMI_IRQn = 78, RNG_IRQn = 80, FPU_IRQn = 81, UART7_IRQn = 82, UART8_IRQn = 83, SPI4_IRQn = 84, SPI5_IRQn = 85, SPI6_IRQn = 86, SAI1_IRQn = 87, LTDC_IRQn = 88, LTDC_ER_IRQn = 89, DMA2D_IRQn = 90, SAI2_IRQn = 91, QUADSPI_IRQn = 92, LPTIM1_IRQn = 93, CEC_IRQn = 94, I2C4_EV_IRQn = 95, I2C4_ER_IRQn = 96, SPDIF_RX_IRQn = 97, DSI_IRQn = 98, DFSDM1_FLT0_IRQn = 99, DFSDM1_FLT1_IRQn = 100, DFSDM1_FLT2_IRQn = 101, DFSDM1_FLT3_IRQn = 102, SDMMC2_IRQn = 103, CAN3_TX_IRQn = 104, CAN3_RX0_IRQn = 105, CAN3_RX1_IRQn = 106, CAN3_SCE_IRQn = 107, JPEG_IRQn = 108, MDIOS_IRQn = 109, NonMaskableInt_IRQn = -14, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, WWDG_IRQn = 0, PVD_IRQn = 1, TAMP_STAMP_IRQn = 2, RTC_WKUP_IRQn = 3, FLASH_IRQn = 4, RCC_IRQn = 5, EXTI0_IRQn = 6, EXTI1_IRQn = 7, EXTI2_IRQn = 8, EXTI3_IRQn = 9, EXTI4_IRQn = 10, DMA1_Stream0_IRQn = 11, DMA1_Stream1_IRQn = 12, DMA1_Stream2_IRQn = 13, DMA1_Stream3_IRQn = 14, DMA1_Stream4_IRQn = 15, DMA1_Stream5_IRQn = 16, DMA1_Stream6_IRQn = 17, ADC_IRQn = 18, CAN1_TX_IRQn = 19, CAN1_RX0_IRQn = 20, CAN1_RX1_IRQn = 21, CAN1_SCE_IRQn = 22, EXTI9_5_IRQn = 23, TIM1_BRK_TIM9_IRQn = 24, TIM1_UP_TIM10_IRQn = 25, TIM1_TRG_COM_TIM11_IRQn = 26, TIM1_CC_IRQn = 27, TIM2_IRQn = 28, TIM3_IRQn = 29, TIM4_IRQn = 30, I2C1_EV_IRQn = 31, I2C1_ER_IRQn = 32, I2C2_EV_IRQn = 33, I2C2_ER_IRQn = 34, SPI1_IRQn = 35, SPI2_IRQn = 36, USART1_IRQn = 37, USART2_IRQn = 38, USART3_IRQn = 39, EXTI15_10_IRQn = 40, RTC_Alarm_IRQn = 41, OTG_FS_WKUP_IRQn = 42, TIM8_BRK_TIM12_IRQn = 43, TIM8_UP_TIM13_IRQn = 44, TIM8_TRG_COM_TIM14_IRQn = 45, TIM8_CC_IRQn = 46, DMA1_Stream7_IRQn = 47, FMC_IRQn = 48, SDMMC1_IRQn = 49, TIM5_IRQn = 50, SPI3_IRQn = 51, UART4_IRQn = 52, UART5_IRQn = 53, TIM6_DAC_IRQn = 54, TIM7_IRQn = 55, DMA2_Stream0_IRQn = 56, DMA2_Stream1_IRQn = 57, DMA2_Stream2_IRQn = 58, DMA2_Stream3_IRQn = 59, DMA2_Stream4_IRQn = 60, ETH_IRQn = 61, ETH_WKUP_IRQn = 62, CAN2_TX_IRQn = 63, CAN2_RX0_IRQn = 64, CAN2_RX1_IRQn = 65, CAN2_SCE_IRQn = 66, OTG_FS_IRQn = 67, DMA2_Stream5_IRQn = 68, DMA2_Stream6_IRQn = 69, DMA2_Stream7_IRQn = 70, USART6_IRQn = 71, I2C3_EV_IRQn = 72, I2C3_ER_IRQn = 73, OTG_HS_EP1_OUT_IRQn = 74, OTG_HS_EP1_IN_IRQn = 75, OTG_HS_WKUP_IRQn = 76, OTG_HS_IRQn = 77, DCMI_IRQn = 78, CRYP_IRQn = 79, HASH_RNG_IRQn = 80, FPU_IRQn = 81, UART7_IRQn = 82, UART8_IRQn = 83, SPI4_IRQn = 84, SPI5_IRQn = 85, SPI6_IRQn = 86, SAI1_IRQn = 87, LTDC_IRQn = 88, LTDC_ER_IRQn = 89, DMA2D_IRQn = 90, SAI2_IRQn = 91, QUADSPI_IRQn = 92, LPTIM1_IRQn = 93, CEC_IRQn = 94, I2C4_EV_IRQn = 95, I2C4_ER_IRQn = 96, SPDIF_RX_IRQn = 97, DFSDM1_FLT0_IRQn = 99, DFSDM1_FLT1_IRQn = 100, DFSDM1_FLT2_IRQn = 101, DFSDM1_FLT3_IRQn = 102, SDMMC2_IRQn = 103, CAN3_TX_IRQn = 104, CAN3_RX0_IRQn = 105, CAN3_RX1_IRQn = 106, CAN3_SCE_IRQn = 107, JPEG_IRQn = 108, MDIOS_IRQn = 109, NonMaskableInt_IRQn = -14, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, WWDG_IRQn = 0, PVD_IRQn = 1, TAMP_STAMP_IRQn = 2, RTC_WKUP_IRQn = 3, FLASH_IRQn = 4, RCC_IRQn = 5, EXTI0_IRQn = 6, EXTI1_IRQn = 7, EXTI2_IRQn = 8, EXTI3_IRQn = 9, EXTI4_IRQn = 10, DMA1_Stream0_IRQn = 11, DMA1_Stream1_IRQn = 12, DMA1_Stream2_IRQn = 13, DMA1_Stream3_IRQn = 14, DMA1_Stream4_IRQn = 15, DMA1_Stream5_IRQn = 16, DMA1_Stream6_IRQn = 17, ADC_IRQn = 18, CAN1_TX_IRQn = 19, CAN1_RX0_IRQn = 20, CAN1_RX1_IRQn = 21, CAN1_SCE_IRQn = 22, EXTI9_5_IRQn = 23, TIM1_BRK_TIM9_IRQn = 24, TIM1_UP_TIM10_IRQn = 25, TIM1_TRG_COM_TIM11_IRQn = 26, TIM1_CC_IRQn = 27, TIM2_IRQn = 28, TIM3_IRQn = 29, TIM4_IRQn = 30, I2C1_EV_IRQn = 31, I2C1_ER_IRQn = 32, I2C2_EV_IRQn = 33, I2C2_ER_IRQn = 34, SPI1_IRQn = 35, SPI2_IRQn = 36, USART1_IRQn = 37, USART2_IRQn = 38, USART3_IRQn = 39, EXTI15_10_IRQn = 40, RTC_Alarm_IRQn = 41, OTG_FS_WKUP_IRQn = 42, TIM8_BRK_TIM12_IRQn = 43, TIM8_UP_TIM13_IRQn = 44, TIM8_TRG_COM_TIM14_IRQn = 45, TIM8_CC_IRQn = 46, DMA1_Stream7_IRQn = 47, FMC_IRQn = 48, SDMMC1_IRQn = 49, TIM5_IRQn = 50, SPI3_IRQn = 51, UART4_IRQn = 52, UART5_IRQn = 53, TIM6_DAC_IRQn = 54, TIM7_IRQn = 55, DMA2_Stream0_IRQn = 56, DMA2_Stream1_IRQn = 57, DMA2_Stream2_IRQn = 58, DMA2_Stream3_IRQn = 59, DMA2_Stream4_IRQn = 60, ETH_IRQn = 61, ETH_WKUP_IRQn = 62, CAN2_TX_IRQn = 63, CAN2_RX0_IRQn = 64, CAN2_RX1_IRQn = 65, CAN2_SCE_IRQn = 66, OTG_FS_IRQn = 67, DMA2_Stream5_IRQn = 68, DMA2_Stream6_IRQn = 69, DMA2_Stream7_IRQn = 70, USART6_IRQn = 71, I2C3_EV_IRQn = 72, I2C3_ER_IRQn = 73, OTG_HS_EP1_OUT_IRQn = 74, OTG_HS_EP1_IN_IRQn = 75, OTG_HS_WKUP_IRQn = 76, OTG_HS_IRQn = 77, DCMI_IRQn = 78, CRYP_IRQn = 79, HASH_RNG_IRQn = 80, FPU_IRQn = 81, UART7_IRQn = 82, UART8_IRQn = 83, SPI4_IRQn = 84, SPI5_IRQn = 85, SPI6_IRQn = 86, SAI1_IRQn = 87, LTDC_IRQn = 88, LTDC_ER_IRQn = 89, DMA2D_IRQn = 90, SAI2_IRQn = 91, QUADSPI_IRQn = 92, LPTIM1_IRQn = 93, CEC_IRQn = 94, I2C4_EV_IRQn = 95, I2C4_ER_IRQn = 96, SPDIF_RX_IRQn = 97, DSI_IRQn = 98, DFSDM1_FLT0_IRQn = 99, DFSDM1_FLT1_IRQn = 100, DFSDM1_FLT2_IRQn = 101, DFSDM1_FLT3_IRQn = 102, SDMMC2_IRQn = 103, CAN3_TX_IRQn = 104, CAN3_RX0_IRQn = 105, CAN3_RX1_IRQn = 106, CAN3_SCE_IRQn = 107, JPEG_IRQn = 108, MDIOS_IRQn = 109 }
	STM32F7xx Interrupt Number Definition, according to the selected device in Library_configuration_section. More...

Detailed Description

CMSIS Cortex-M7 Device Peripheral Access Layer Header File.

Author: MCD Application Team

Version: V1.1.0

Date

22-April-2016 This file contains:

Data structures and the address mapping for all peripherals
Peripheral's registers declarations and bits definition
Macros to access peripheral�s registers hardware

Attention

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Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f756xx.h.

Data Structures

Macros

Enumerations

Detailed Description

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