STM32F769IDiscovery  1.00
uDANTE Audio Networking with STM32F7 DISCO board
core_cm7.h
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1 /**************************************************************************/
7 /* Copyright (c) 2009 - 2015 ARM LIMITED
8 
9  All rights reserved.
10  Redistribution and use in source and binary forms, with or without
11  modification, are permitted provided that the following conditions are met:
12  - Redistributions of source code must retain the above copyright
13  notice, this list of conditions and the following disclaimer.
14  - Redistributions in binary form must reproduce the above copyright
15  notice, this list of conditions and the following disclaimer in the
16  documentation and/or other materials provided with the distribution.
17  - Neither the name of ARM nor the names of its contributors may be used
18  to endorse or promote products derived from this software without
19  specific prior written permission.
20  *
21  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
25  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  POSSIBILITY OF SUCH DAMAGE.
32  ---------------------------------------------------------------------------*/
33 
34 
35 #if defined ( __ICCARM__ )
36  #pragma system_include /* treat file as system include file for MISRA check */
37 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
38  #pragma clang system_header /* treat file as system include file */
39 #endif
40 
41 #ifndef __CORE_CM7_H_GENERIC
42 #define __CORE_CM7_H_GENERIC
43 
44 #include <stdint.h>
45 
46 #ifdef __cplusplus
47  extern "C" {
48 #endif
49 
65 /*******************************************************************************
66  * CMSIS definitions
67  ******************************************************************************/
73 /* CMSIS CM7 definitions */
74 #define __CM7_CMSIS_VERSION_MAIN (0x04U)
75 #define __CM7_CMSIS_VERSION_SUB (0x1EU)
76 #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
77  __CM7_CMSIS_VERSION_SUB )
79 #define __CORTEX_M (0x07U)
82 #if defined ( __CC_ARM )
83  #define __ASM __asm
84  #define __INLINE __inline
85  #define __STATIC_INLINE static __inline
86 
87 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
88  #define __ASM __asm
89  #define __INLINE __inline
90  #define __STATIC_INLINE static __inline
91 
92 #elif defined ( __GNUC__ )
93  #define __ASM __asm
94  #define __INLINE inline
95  #define __STATIC_INLINE static inline
96 
97 #elif defined ( __ICCARM__ )
98  #define __ASM __asm
99  #define __INLINE inline
100  #define __STATIC_INLINE static inline
101 
102 #elif defined ( __TMS470__ )
103  #define __ASM __asm
104  #define __STATIC_INLINE static inline
105 
106 #elif defined ( __TASKING__ )
107  #define __ASM __asm
108  #define __INLINE inline
109  #define __STATIC_INLINE static inline
110 
111 #elif defined ( __CSMC__ )
112  #define __packed
113  #define __ASM _asm
114  #define __INLINE inline
115  #define __STATIC_INLINE static inline
116 
117 #else
118  #error Unknown compiler
119 #endif
120 
124 #if defined ( __CC_ARM )
125  #if defined __TARGET_FPU_VFP
126  #if (__FPU_PRESENT == 1U)
127  #define __FPU_USED 1U
128  #else
129  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
130  #define __FPU_USED 0U
131  #endif
132  #else
133  #define __FPU_USED 0U
134  #endif
135 
136 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
137  #if defined __ARM_PCS_VFP
138  #if (__FPU_PRESENT == 1)
139  #define __FPU_USED 1U
140  #else
141  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
142  #define __FPU_USED 0U
143  #endif
144  #else
145  #define __FPU_USED 0U
146  #endif
147 
148 #elif defined ( __GNUC__ )
149  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
150  #if (__FPU_PRESENT == 1U)
151  #define __FPU_USED 1U
152  #else
153  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
154  #define __FPU_USED 0U
155  #endif
156  #else
157  #define __FPU_USED 0U
158  #endif
159 
160 #elif defined ( __ICCARM__ )
161  #if defined __ARMVFP__
162  #if (__FPU_PRESENT == 1U)
163  #define __FPU_USED 1U
164  #else
165  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
166  #define __FPU_USED 0U
167  #endif
168  #else
169  #define __FPU_USED 0U
170  #endif
171 
172 #elif defined ( __TMS470__ )
173  #if defined __TI_VFP_SUPPORT__
174  #if (__FPU_PRESENT == 1U)
175  #define __FPU_USED 1U
176  #else
177  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
178  #define __FPU_USED 0U
179  #endif
180  #else
181  #define __FPU_USED 0U
182  #endif
183 
184 #elif defined ( __TASKING__ )
185  #if defined __FPU_VFP__
186  #if (__FPU_PRESENT == 1U)
187  #define __FPU_USED 1U
188  #else
189  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
190  #define __FPU_USED 0U
191  #endif
192  #else
193  #define __FPU_USED 0U
194  #endif
195 
196 #elif defined ( __CSMC__ )
197  #if ( __CSMC__ & 0x400U)
198  #if (__FPU_PRESENT == 1U)
199  #define __FPU_USED 1U
200  #else
201  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
202  #define __FPU_USED 0U
203  #endif
204  #else
205  #define __FPU_USED 0U
206  #endif
207 
208 #endif
209 
210 #include "core_cmInstr.h" /* Core Instruction Access */
211 #include "core_cmFunc.h" /* Core Function Access */
212 #include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */
213 
214 #ifdef __cplusplus
215 }
216 #endif
217 
218 #endif /* __CORE_CM7_H_GENERIC */
219 
220 #ifndef __CMSIS_GENERIC
221 
222 #ifndef __CORE_CM7_H_DEPENDANT
223 #define __CORE_CM7_H_DEPENDANT
224 
225 #ifdef __cplusplus
226  extern "C" {
227 #endif
228 
229 /* check device defines and use defaults */
230 #if defined __CHECK_DEVICE_DEFINES
231  #ifndef __CM7_REV
232  #define __CM7_REV 0x0000U
233  #warning "__CM7_REV not defined in device header file; using default!"
234  #endif
235 
236  #ifndef __FPU_PRESENT
237  #define __FPU_PRESENT 0U
238  #warning "__FPU_PRESENT not defined in device header file; using default!"
239  #endif
240 
241  #ifndef __MPU_PRESENT
242  #define __MPU_PRESENT 0U
243  #warning "__MPU_PRESENT not defined in device header file; using default!"
244  #endif
245 
246  #ifndef __ICACHE_PRESENT
247  #define __ICACHE_PRESENT 0U
248  #warning "__ICACHE_PRESENT not defined in device header file; using default!"
249  #endif
250 
251  #ifndef __DCACHE_PRESENT
252  #define __DCACHE_PRESENT 0U
253  #warning "__DCACHE_PRESENT not defined in device header file; using default!"
254  #endif
255 
256  #ifndef __DTCM_PRESENT
257  #define __DTCM_PRESENT 0U
258  #warning "__DTCM_PRESENT not defined in device header file; using default!"
259  #endif
260 
261  #ifndef __NVIC_PRIO_BITS
262  #define __NVIC_PRIO_BITS 3U
263  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
264  #endif
265 
266  #ifndef __Vendor_SysTickConfig
267  #define __Vendor_SysTickConfig 0U
268  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
269  #endif
270 #endif
271 
272 /* IO definitions (access restrictions to peripheral registers) */
280 #ifdef __cplusplus
281  #define __I volatile
282 #else
283  #define __I volatile const
284 #endif
285 #define __O volatile
286 #define __IO volatile
288 /* following defines should be used for structure members */
289 #define __IM volatile const
290 #define __OM volatile
291 #define __IOM volatile
293 
297 /*******************************************************************************
298  * Register Abstraction
299  Core Register contain:
300  - Core Register
301  - Core NVIC Register
302  - Core SCB Register
303  - Core SysTick Register
304  - Core Debug Register
305  - Core MPU Register
306  - Core FPU Register
307  ******************************************************************************/
308 
323 typedef union
324 {
325  struct
326  {
327  uint32_t _reserved0:16;
328  uint32_t GE:4;
329  uint32_t _reserved1:7;
330  uint32_t Q:1;
331  uint32_t V:1;
332  uint32_t C:1;
333  uint32_t Z:1;
334  uint32_t N:1;
335  } b;
336  uint32_t w;
337 } APSR_Type;
338 
339 /* APSR Register Definitions */
340 #define APSR_N_Pos 31U
341 #define APSR_N_Msk (1UL << APSR_N_Pos)
343 #define APSR_Z_Pos 30U
344 #define APSR_Z_Msk (1UL << APSR_Z_Pos)
346 #define APSR_C_Pos 29U
347 #define APSR_C_Msk (1UL << APSR_C_Pos)
349 #define APSR_V_Pos 28U
350 #define APSR_V_Msk (1UL << APSR_V_Pos)
352 #define APSR_Q_Pos 27U
353 #define APSR_Q_Msk (1UL << APSR_Q_Pos)
355 #define APSR_GE_Pos 16U
356 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos)
362 typedef union
363 {
364  struct
365  {
366  uint32_t ISR:9;
367  uint32_t _reserved0:23;
368  } b;
369  uint32_t w;
370 } IPSR_Type;
371 
372 /* IPSR Register Definitions */
373 #define IPSR_ISR_Pos 0U
374 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
380 typedef union
381 {
382  struct
383  {
384  uint32_t ISR:9;
385  uint32_t _reserved0:7;
386  uint32_t GE:4;
387  uint32_t _reserved1:4;
388  uint32_t T:1;
389  uint32_t IT:2;
390  uint32_t Q:1;
391  uint32_t V:1;
392  uint32_t C:1;
393  uint32_t Z:1;
394  uint32_t N:1;
395  } b;
396  uint32_t w;
397 } xPSR_Type;
398 
399 /* xPSR Register Definitions */
400 #define xPSR_N_Pos 31U
401 #define xPSR_N_Msk (1UL << xPSR_N_Pos)
403 #define xPSR_Z_Pos 30U
404 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
406 #define xPSR_C_Pos 29U
407 #define xPSR_C_Msk (1UL << xPSR_C_Pos)
409 #define xPSR_V_Pos 28U
410 #define xPSR_V_Msk (1UL << xPSR_V_Pos)
412 #define xPSR_Q_Pos 27U
413 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos)
415 #define xPSR_IT_Pos 25U
416 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos)
418 #define xPSR_T_Pos 24U
419 #define xPSR_T_Msk (1UL << xPSR_T_Pos)
421 #define xPSR_GE_Pos 16U
422 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)
424 #define xPSR_ISR_Pos 0U
425 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
431 typedef union
432 {
433  struct
434  {
435  uint32_t nPRIV:1;
436  uint32_t SPSEL:1;
437  uint32_t FPCA:1;
438  uint32_t _reserved0:29;
439  } b;
440  uint32_t w;
441 } CONTROL_Type;
442 
443 /* CONTROL Register Definitions */
444 #define CONTROL_FPCA_Pos 2U
445 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)
447 #define CONTROL_SPSEL_Pos 1U
448 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
450 #define CONTROL_nPRIV_Pos 0U
451 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)
453 
466 typedef struct
467 {
468  __IOM uint32_t ISER[8U];
469  uint32_t RESERVED0[24U];
470  __IOM uint32_t ICER[8U];
471  uint32_t RSERVED1[24U];
472  __IOM uint32_t ISPR[8U];
473  uint32_t RESERVED2[24U];
474  __IOM uint32_t ICPR[8U];
475  uint32_t RESERVED3[24U];
476  __IOM uint32_t IABR[8U];
477  uint32_t RESERVED4[56U];
478  __IOM uint8_t IP[240U];
479  uint32_t RESERVED5[644U];
480  __OM uint32_t STIR;
481 } NVIC_Type;
482 
483 /* Software Triggered Interrupt Register Definitions */
484 #define NVIC_STIR_INTID_Pos 0U
485 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
487 
500 typedef struct
501 {
502  __IM uint32_t CPUID;
503  __IOM uint32_t ICSR;
504  __IOM uint32_t VTOR;
505  __IOM uint32_t AIRCR;
506  __IOM uint32_t SCR;
507  __IOM uint32_t CCR;
508  __IOM uint8_t SHPR[12U];
509  __IOM uint32_t SHCSR;
510  __IOM uint32_t CFSR;
511  __IOM uint32_t HFSR;
512  __IOM uint32_t DFSR;
513  __IOM uint32_t MMFAR;
514  __IOM uint32_t BFAR;
515  __IOM uint32_t AFSR;
516  __IM uint32_t ID_PFR[2U];
517  __IM uint32_t ID_DFR;
518  __IM uint32_t ID_AFR;
519  __IM uint32_t ID_MFR[4U];
520  __IM uint32_t ID_ISAR[5U];
521  uint32_t RESERVED0[1U];
522  __IM uint32_t CLIDR;
523  __IM uint32_t CTR;
524  __IM uint32_t CCSIDR;
525  __IOM uint32_t CSSELR;
526  __IOM uint32_t CPACR;
527  uint32_t RESERVED3[93U];
528  __OM uint32_t STIR;
529  uint32_t RESERVED4[15U];
530  __IM uint32_t MVFR0;
531  __IM uint32_t MVFR1;
532  __IM uint32_t MVFR2;
533  uint32_t RESERVED5[1U];
534  __OM uint32_t ICIALLU;
535  uint32_t RESERVED6[1U];
536  __OM uint32_t ICIMVAU;
537  __OM uint32_t DCIMVAC;
538  __OM uint32_t DCISW;
539  __OM uint32_t DCCMVAU;
540  __OM uint32_t DCCMVAC;
541  __OM uint32_t DCCSW;
542  __OM uint32_t DCCIMVAC;
543  __OM uint32_t DCCISW;
544  uint32_t RESERVED7[6U];
545  __IOM uint32_t ITCMCR;
546  __IOM uint32_t DTCMCR;
547  __IOM uint32_t AHBPCR;
548  __IOM uint32_t CACR;
549  __IOM uint32_t AHBSCR;
550  uint32_t RESERVED8[1U];
551  __IOM uint32_t ABFSR;
552 } SCB_Type;
553 
554 /* SCB CPUID Register Definitions */
555 #define SCB_CPUID_IMPLEMENTER_Pos 24U
556 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
558 #define SCB_CPUID_VARIANT_Pos 20U
559 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
561 #define SCB_CPUID_ARCHITECTURE_Pos 16U
562 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
564 #define SCB_CPUID_PARTNO_Pos 4U
565 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
567 #define SCB_CPUID_REVISION_Pos 0U
568 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
570 /* SCB Interrupt Control State Register Definitions */
571 #define SCB_ICSR_NMIPENDSET_Pos 31U
572 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
574 #define SCB_ICSR_PENDSVSET_Pos 28U
575 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
577 #define SCB_ICSR_PENDSVCLR_Pos 27U
578 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
580 #define SCB_ICSR_PENDSTSET_Pos 26U
581 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
583 #define SCB_ICSR_PENDSTCLR_Pos 25U
584 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
586 #define SCB_ICSR_ISRPREEMPT_Pos 23U
587 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
589 #define SCB_ICSR_ISRPENDING_Pos 22U
590 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
592 #define SCB_ICSR_VECTPENDING_Pos 12U
593 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
595 #define SCB_ICSR_RETTOBASE_Pos 11U
596 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
598 #define SCB_ICSR_VECTACTIVE_Pos 0U
599 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
601 /* SCB Vector Table Offset Register Definitions */
602 #define SCB_VTOR_TBLOFF_Pos 7U
603 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
605 /* SCB Application Interrupt and Reset Control Register Definitions */
606 #define SCB_AIRCR_VECTKEY_Pos 16U
607 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
609 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U
610 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
612 #define SCB_AIRCR_ENDIANESS_Pos 15U
613 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
615 #define SCB_AIRCR_PRIGROUP_Pos 8U
616 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
618 #define SCB_AIRCR_SYSRESETREQ_Pos 2U
619 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
621 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
622 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
624 #define SCB_AIRCR_VECTRESET_Pos 0U
625 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
627 /* SCB System Control Register Definitions */
628 #define SCB_SCR_SEVONPEND_Pos 4U
629 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
631 #define SCB_SCR_SLEEPDEEP_Pos 2U
632 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
634 #define SCB_SCR_SLEEPONEXIT_Pos 1U
635 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
637 /* SCB Configuration Control Register Definitions */
638 #define SCB_CCR_BP_Pos 18U
639 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)
641 #define SCB_CCR_IC_Pos 17U
642 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)
644 #define SCB_CCR_DC_Pos 16U
645 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)
647 #define SCB_CCR_STKALIGN_Pos 9U
648 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
650 #define SCB_CCR_BFHFNMIGN_Pos 8U
651 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
653 #define SCB_CCR_DIV_0_TRP_Pos 4U
654 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
656 #define SCB_CCR_UNALIGN_TRP_Pos 3U
657 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
659 #define SCB_CCR_USERSETMPEND_Pos 1U
660 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
662 #define SCB_CCR_NONBASETHRDENA_Pos 0U
663 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
665 /* SCB System Handler Control and State Register Definitions */
666 #define SCB_SHCSR_USGFAULTENA_Pos 18U
667 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
669 #define SCB_SHCSR_BUSFAULTENA_Pos 17U
670 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
672 #define SCB_SHCSR_MEMFAULTENA_Pos 16U
673 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
675 #define SCB_SHCSR_SVCALLPENDED_Pos 15U
676 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
678 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U
679 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
681 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U
682 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
684 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U
685 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
687 #define SCB_SHCSR_SYSTICKACT_Pos 11U
688 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
690 #define SCB_SHCSR_PENDSVACT_Pos 10U
691 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
693 #define SCB_SHCSR_MONITORACT_Pos 8U
694 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
696 #define SCB_SHCSR_SVCALLACT_Pos 7U
697 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
699 #define SCB_SHCSR_USGFAULTACT_Pos 3U
700 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
702 #define SCB_SHCSR_BUSFAULTACT_Pos 1U
703 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
705 #define SCB_SHCSR_MEMFAULTACT_Pos 0U
706 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
708 /* SCB Configurable Fault Status Register Definitions */
709 #define SCB_CFSR_USGFAULTSR_Pos 16U
710 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
712 #define SCB_CFSR_BUSFAULTSR_Pos 8U
713 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
715 #define SCB_CFSR_MEMFAULTSR_Pos 0U
716 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
718 /* SCB Hard Fault Status Register Definitions */
719 #define SCB_HFSR_DEBUGEVT_Pos 31U
720 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
722 #define SCB_HFSR_FORCED_Pos 30U
723 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
725 #define SCB_HFSR_VECTTBL_Pos 1U
726 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
728 /* SCB Debug Fault Status Register Definitions */
729 #define SCB_DFSR_EXTERNAL_Pos 4U
730 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
732 #define SCB_DFSR_VCATCH_Pos 3U
733 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
735 #define SCB_DFSR_DWTTRAP_Pos 2U
736 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
738 #define SCB_DFSR_BKPT_Pos 1U
739 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
741 #define SCB_DFSR_HALTED_Pos 0U
742 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)
744 /* SCB Cache Level ID Register Definitions */
745 #define SCB_CLIDR_LOUU_Pos 27U
746 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)
748 #define SCB_CLIDR_LOC_Pos 24U
749 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)
751 /* SCB Cache Type Register Definitions */
752 #define SCB_CTR_FORMAT_Pos 29U
753 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)
755 #define SCB_CTR_CWG_Pos 24U
756 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)
758 #define SCB_CTR_ERG_Pos 20U
759 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)
761 #define SCB_CTR_DMINLINE_Pos 16U
762 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)
764 #define SCB_CTR_IMINLINE_Pos 0U
765 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
767 /* SCB Cache Size ID Register Definitions */
768 #define SCB_CCSIDR_WT_Pos 31U
769 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)
771 #define SCB_CCSIDR_WB_Pos 30U
772 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)
774 #define SCB_CCSIDR_RA_Pos 29U
775 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)
777 #define SCB_CCSIDR_WA_Pos 28U
778 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)
780 #define SCB_CCSIDR_NUMSETS_Pos 13U
781 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
783 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U
784 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
786 #define SCB_CCSIDR_LINESIZE_Pos 0U
787 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
789 /* SCB Cache Size Selection Register Definitions */
790 #define SCB_CSSELR_LEVEL_Pos 1U
791 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)
793 #define SCB_CSSELR_IND_Pos 0U
794 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)
796 /* SCB Software Triggered Interrupt Register Definitions */
797 #define SCB_STIR_INTID_Pos 0U
798 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
800 /* SCB D-Cache Invalidate by Set-way Register Definitions */
801 #define SCB_DCISW_WAY_Pos 30U
802 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)
804 #define SCB_DCISW_SET_Pos 5U
805 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)
807 /* SCB D-Cache Clean by Set-way Register Definitions */
808 #define SCB_DCCSW_WAY_Pos 30U
809 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)
811 #define SCB_DCCSW_SET_Pos 5U
812 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)
814 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
815 #define SCB_DCCISW_WAY_Pos 30U
816 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)
818 #define SCB_DCCISW_SET_Pos 5U
819 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)
821 /* Instruction Tightly-Coupled Memory Control Register Definitions */
822 #define SCB_ITCMCR_SZ_Pos 3U
823 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos)
825 #define SCB_ITCMCR_RETEN_Pos 2U
826 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos)
828 #define SCB_ITCMCR_RMW_Pos 1U
829 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos)
831 #define SCB_ITCMCR_EN_Pos 0U
832 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/)
834 /* Data Tightly-Coupled Memory Control Register Definitions */
835 #define SCB_DTCMCR_SZ_Pos 3U
836 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos)
838 #define SCB_DTCMCR_RETEN_Pos 2U
839 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos)
841 #define SCB_DTCMCR_RMW_Pos 1U
842 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos)
844 #define SCB_DTCMCR_EN_Pos 0U
845 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/)
847 /* AHBP Control Register Definitions */
848 #define SCB_AHBPCR_SZ_Pos 1U
849 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos)
851 #define SCB_AHBPCR_EN_Pos 0U
852 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/)
854 /* L1 Cache Control Register Definitions */
855 #define SCB_CACR_FORCEWT_Pos 2U
856 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos)
858 #define SCB_CACR_ECCEN_Pos 1U
859 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos)
861 #define SCB_CACR_SIWT_Pos 0U
862 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/)
864 /* AHBS Control Register Definitions */
865 #define SCB_AHBSCR_INITCOUNT_Pos 11U
866 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)
868 #define SCB_AHBSCR_TPRI_Pos 2U
869 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos)
871 #define SCB_AHBSCR_CTL_Pos 0U
872 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/)
874 /* Auxiliary Bus Fault Status Register Definitions */
875 #define SCB_ABFSR_AXIMTYPE_Pos 8U
876 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos)
878 #define SCB_ABFSR_EPPB_Pos 4U
879 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos)
881 #define SCB_ABFSR_AXIM_Pos 3U
882 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos)
884 #define SCB_ABFSR_AHBP_Pos 2U
885 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos)
887 #define SCB_ABFSR_DTCM_Pos 1U
888 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos)
890 #define SCB_ABFSR_ITCM_Pos 0U
891 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/)
893 
906 typedef struct
907 {
908  uint32_t RESERVED0[1U];
909  __IM uint32_t ICTR;
910  __IOM uint32_t ACTLR;
911 } SCnSCB_Type;
912 
913 /* Interrupt Controller Type Register Definitions */
914 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U
915 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
917 /* Auxiliary Control Register Definitions */
918 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U
919 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)
921 #define SCnSCB_ACTLR_DISRAMODE_Pos 11U
922 #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)
924 #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U
925 #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)
927 #define SCnSCB_ACTLR_DISFOLD_Pos 2U
928 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)
930 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U
931 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)
933 
946 typedef struct
947 {
948  __IOM uint32_t CTRL;
949  __IOM uint32_t LOAD;
950  __IOM uint32_t VAL;
951  __IM uint32_t CALIB;
952 } SysTick_Type;
953 
954 /* SysTick Control / Status Register Definitions */
955 #define SysTick_CTRL_COUNTFLAG_Pos 16U
956 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
958 #define SysTick_CTRL_CLKSOURCE_Pos 2U
959 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
961 #define SysTick_CTRL_TICKINT_Pos 1U
962 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
964 #define SysTick_CTRL_ENABLE_Pos 0U
965 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
967 /* SysTick Reload Register Definitions */
968 #define SysTick_LOAD_RELOAD_Pos 0U
969 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
971 /* SysTick Current Register Definitions */
972 #define SysTick_VAL_CURRENT_Pos 0U
973 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
975 /* SysTick Calibration Register Definitions */
976 #define SysTick_CALIB_NOREF_Pos 31U
977 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
979 #define SysTick_CALIB_SKEW_Pos 30U
980 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
982 #define SysTick_CALIB_TENMS_Pos 0U
983 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
985 
998 typedef struct
999 {
1000  __OM union
1001  {
1002  __OM uint8_t u8;
1003  __OM uint16_t u16;
1004  __OM uint32_t u32;
1005  } PORT [32U];
1006  uint32_t RESERVED0[864U];
1007  __IOM uint32_t TER;
1008  uint32_t RESERVED1[15U];
1009  __IOM uint32_t TPR;
1010  uint32_t RESERVED2[15U];
1011  __IOM uint32_t TCR;
1012  uint32_t RESERVED3[29U];
1013  __OM uint32_t IWR;
1014  __IM uint32_t IRR;
1015  __IOM uint32_t IMCR;
1016  uint32_t RESERVED4[43U];
1017  __OM uint32_t LAR;
1018  __IM uint32_t LSR;
1019  uint32_t RESERVED5[6U];
1020  __IM uint32_t PID4;
1021  __IM uint32_t PID5;
1022  __IM uint32_t PID6;
1023  __IM uint32_t PID7;
1024  __IM uint32_t PID0;
1025  __IM uint32_t PID1;
1026  __IM uint32_t PID2;
1027  __IM uint32_t PID3;
1028  __IM uint32_t CID0;
1029  __IM uint32_t CID1;
1030  __IM uint32_t CID2;
1031  __IM uint32_t CID3;
1032 } ITM_Type;
1033 
1034 /* ITM Trace Privilege Register Definitions */
1035 #define ITM_TPR_PRIVMASK_Pos 0U
1036 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
1038 /* ITM Trace Control Register Definitions */
1039 #define ITM_TCR_BUSY_Pos 23U
1040 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
1042 #define ITM_TCR_TraceBusID_Pos 16U
1043 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)
1045 #define ITM_TCR_GTSFREQ_Pos 10U
1046 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
1048 #define ITM_TCR_TSPrescale_Pos 8U
1049 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)
1051 #define ITM_TCR_SWOENA_Pos 4U
1052 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
1054 #define ITM_TCR_DWTENA_Pos 3U
1055 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
1057 #define ITM_TCR_SYNCENA_Pos 2U
1058 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
1060 #define ITM_TCR_TSENA_Pos 1U
1061 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
1063 #define ITM_TCR_ITMENA_Pos 0U
1064 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)
1066 /* ITM Integration Write Register Definitions */
1067 #define ITM_IWR_ATVALIDM_Pos 0U
1068 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)
1070 /* ITM Integration Read Register Definitions */
1071 #define ITM_IRR_ATREADYM_Pos 0U
1072 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)
1074 /* ITM Integration Mode Control Register Definitions */
1075 #define ITM_IMCR_INTEGRATION_Pos 0U
1076 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)
1078 /* ITM Lock Status Register Definitions */
1079 #define ITM_LSR_ByteAcc_Pos 2U
1080 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
1082 #define ITM_LSR_Access_Pos 1U
1083 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
1085 #define ITM_LSR_Present_Pos 0U
1086 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)
1088  /* end of group CMSIS_ITM */
1089 
1090 
1101 typedef struct
1102 {
1103  __IOM uint32_t CTRL;
1104  __IOM uint32_t CYCCNT;
1105  __IOM uint32_t CPICNT;
1106  __IOM uint32_t EXCCNT;
1107  __IOM uint32_t SLEEPCNT;
1108  __IOM uint32_t LSUCNT;
1109  __IOM uint32_t FOLDCNT;
1110  __IM uint32_t PCSR;
1111  __IOM uint32_t COMP0;
1112  __IOM uint32_t MASK0;
1113  __IOM uint32_t FUNCTION0;
1114  uint32_t RESERVED0[1U];
1115  __IOM uint32_t COMP1;
1116  __IOM uint32_t MASK1;
1117  __IOM uint32_t FUNCTION1;
1118  uint32_t RESERVED1[1U];
1119  __IOM uint32_t COMP2;
1120  __IOM uint32_t MASK2;
1121  __IOM uint32_t FUNCTION2;
1122  uint32_t RESERVED2[1U];
1123  __IOM uint32_t COMP3;
1124  __IOM uint32_t MASK3;
1125  __IOM uint32_t FUNCTION3;
1126  uint32_t RESERVED3[981U];
1127  __OM uint32_t LAR;
1128  __IM uint32_t LSR;
1129 } DWT_Type;
1130 
1131 /* DWT Control Register Definitions */
1132 #define DWT_CTRL_NUMCOMP_Pos 28U
1133 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
1135 #define DWT_CTRL_NOTRCPKT_Pos 27U
1136 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
1138 #define DWT_CTRL_NOEXTTRIG_Pos 26U
1139 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
1141 #define DWT_CTRL_NOCYCCNT_Pos 25U
1142 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
1144 #define DWT_CTRL_NOPRFCNT_Pos 24U
1145 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
1147 #define DWT_CTRL_CYCEVTENA_Pos 22U
1148 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
1150 #define DWT_CTRL_FOLDEVTENA_Pos 21U
1151 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
1153 #define DWT_CTRL_LSUEVTENA_Pos 20U
1154 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
1156 #define DWT_CTRL_SLEEPEVTENA_Pos 19U
1157 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
1159 #define DWT_CTRL_EXCEVTENA_Pos 18U
1160 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
1162 #define DWT_CTRL_CPIEVTENA_Pos 17U
1163 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
1165 #define DWT_CTRL_EXCTRCENA_Pos 16U
1166 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
1168 #define DWT_CTRL_PCSAMPLENA_Pos 12U
1169 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
1171 #define DWT_CTRL_SYNCTAP_Pos 10U
1172 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
1174 #define DWT_CTRL_CYCTAP_Pos 9U
1175 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
1177 #define DWT_CTRL_POSTINIT_Pos 5U
1178 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
1180 #define DWT_CTRL_POSTPRESET_Pos 1U
1181 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
1183 #define DWT_CTRL_CYCCNTENA_Pos 0U
1184 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
1186 /* DWT CPI Count Register Definitions */
1187 #define DWT_CPICNT_CPICNT_Pos 0U
1188 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
1190 /* DWT Exception Overhead Count Register Definitions */
1191 #define DWT_EXCCNT_EXCCNT_Pos 0U
1192 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
1194 /* DWT Sleep Count Register Definitions */
1195 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U
1196 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
1198 /* DWT LSU Count Register Definitions */
1199 #define DWT_LSUCNT_LSUCNT_Pos 0U
1200 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
1202 /* DWT Folded-instruction Count Register Definitions */
1203 #define DWT_FOLDCNT_FOLDCNT_Pos 0U
1204 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
1206 /* DWT Comparator Mask Register Definitions */
1207 #define DWT_MASK_MASK_Pos 0U
1208 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/)
1210 /* DWT Comparator Function Register Definitions */
1211 #define DWT_FUNCTION_MATCHED_Pos 24U
1212 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
1214 #define DWT_FUNCTION_DATAVADDR1_Pos 16U
1215 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
1217 #define DWT_FUNCTION_DATAVADDR0_Pos 12U
1218 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
1220 #define DWT_FUNCTION_DATAVSIZE_Pos 10U
1221 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
1223 #define DWT_FUNCTION_LNK1ENA_Pos 9U
1224 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
1226 #define DWT_FUNCTION_DATAVMATCH_Pos 8U
1227 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
1229 #define DWT_FUNCTION_CYCMATCH_Pos 7U
1230 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
1232 #define DWT_FUNCTION_EMITRANGE_Pos 5U
1233 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
1235 #define DWT_FUNCTION_FUNCTION_Pos 0U
1236 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)
1238  /* end of group CMSIS_DWT */
1239 
1240 
1251 typedef struct
1252 {
1253  __IOM uint32_t SSPSR;
1254  __IOM uint32_t CSPSR;
1255  uint32_t RESERVED0[2U];
1256  __IOM uint32_t ACPR;
1257  uint32_t RESERVED1[55U];
1258  __IOM uint32_t SPPR;
1259  uint32_t RESERVED2[131U];
1260  __IM uint32_t FFSR;
1261  __IOM uint32_t FFCR;
1262  __IM uint32_t FSCR;
1263  uint32_t RESERVED3[759U];
1264  __IM uint32_t TRIGGER;
1265  __IM uint32_t FIFO0;
1266  __IM uint32_t ITATBCTR2;
1267  uint32_t RESERVED4[1U];
1268  __IM uint32_t ITATBCTR0;
1269  __IM uint32_t FIFO1;
1270  __IOM uint32_t ITCTRL;
1271  uint32_t RESERVED5[39U];
1272  __IOM uint32_t CLAIMSET;
1273  __IOM uint32_t CLAIMCLR;
1274  uint32_t RESERVED7[8U];
1275  __IM uint32_t DEVID;
1276  __IM uint32_t DEVTYPE;
1277 } TPI_Type;
1278 
1279 /* TPI Asynchronous Clock Prescaler Register Definitions */
1280 #define TPI_ACPR_PRESCALER_Pos 0U
1281 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
1283 /* TPI Selected Pin Protocol Register Definitions */
1284 #define TPI_SPPR_TXMODE_Pos 0U
1285 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
1287 /* TPI Formatter and Flush Status Register Definitions */
1288 #define TPI_FFSR_FtNonStop_Pos 3U
1289 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
1291 #define TPI_FFSR_TCPresent_Pos 2U
1292 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
1294 #define TPI_FFSR_FtStopped_Pos 1U
1295 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
1297 #define TPI_FFSR_FlInProg_Pos 0U
1298 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
1300 /* TPI Formatter and Flush Control Register Definitions */
1301 #define TPI_FFCR_TrigIn_Pos 8U
1302 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
1304 #define TPI_FFCR_EnFCont_Pos 1U
1305 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
1307 /* TPI TRIGGER Register Definitions */
1308 #define TPI_TRIGGER_TRIGGER_Pos 0U
1309 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
1311 /* TPI Integration ETM Data Register Definitions (FIFO0) */
1312 #define TPI_FIFO0_ITM_ATVALID_Pos 29U
1313 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
1315 #define TPI_FIFO0_ITM_bytecount_Pos 27U
1316 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
1318 #define TPI_FIFO0_ETM_ATVALID_Pos 26U
1319 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
1321 #define TPI_FIFO0_ETM_bytecount_Pos 24U
1322 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
1324 #define TPI_FIFO0_ETM2_Pos 16U
1325 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
1327 #define TPI_FIFO0_ETM1_Pos 8U
1328 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
1330 #define TPI_FIFO0_ETM0_Pos 0U
1331 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)
1333 /* TPI ITATBCTR2 Register Definitions */
1334 #define TPI_ITATBCTR2_ATREADY_Pos 0U
1335 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)
1337 /* TPI Integration ITM Data Register Definitions (FIFO1) */
1338 #define TPI_FIFO1_ITM_ATVALID_Pos 29U
1339 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
1341 #define TPI_FIFO1_ITM_bytecount_Pos 27U
1342 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
1344 #define TPI_FIFO1_ETM_ATVALID_Pos 26U
1345 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
1347 #define TPI_FIFO1_ETM_bytecount_Pos 24U
1348 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
1350 #define TPI_FIFO1_ITM2_Pos 16U
1351 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
1353 #define TPI_FIFO1_ITM1_Pos 8U
1354 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
1356 #define TPI_FIFO1_ITM0_Pos 0U
1357 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)
1359 /* TPI ITATBCTR0 Register Definitions */
1360 #define TPI_ITATBCTR0_ATREADY_Pos 0U
1361 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)
1363 /* TPI Integration Mode Control Register Definitions */
1364 #define TPI_ITCTRL_Mode_Pos 0U
1365 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)
1367 /* TPI DEVID Register Definitions */
1368 #define TPI_DEVID_NRZVALID_Pos 11U
1369 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
1371 #define TPI_DEVID_MANCVALID_Pos 10U
1372 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
1374 #define TPI_DEVID_PTINVALID_Pos 9U
1375 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
1377 #define TPI_DEVID_MinBufSz_Pos 6U
1378 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
1380 #define TPI_DEVID_AsynClkIn_Pos 5U
1381 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
1383 #define TPI_DEVID_NrTraceInput_Pos 0U
1384 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
1386 /* TPI DEVTYPE Register Definitions */
1387 #define TPI_DEVTYPE_MajorType_Pos 4U
1388 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
1390 #define TPI_DEVTYPE_SubType_Pos 0U
1391 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
1393  /* end of group CMSIS_TPI */
1394 
1395 
1396 #if (__MPU_PRESENT == 1U)
1397 
1407 typedef struct
1408 {
1409  __IM uint32_t TYPE;
1410  __IOM uint32_t CTRL;
1411  __IOM uint32_t RNR;
1412  __IOM uint32_t RBAR;
1413  __IOM uint32_t RASR;
1414  __IOM uint32_t RBAR_A1;
1415  __IOM uint32_t RASR_A1;
1416  __IOM uint32_t RBAR_A2;
1417  __IOM uint32_t RASR_A2;
1418  __IOM uint32_t RBAR_A3;
1419  __IOM uint32_t RASR_A3;
1420 } MPU_Type;
1421 
1422 /* MPU Type Register Definitions */
1423 #define MPU_TYPE_IREGION_Pos 16U
1424 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
1426 #define MPU_TYPE_DREGION_Pos 8U
1427 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
1429 #define MPU_TYPE_SEPARATE_Pos 0U
1430 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
1432 /* MPU Control Register Definitions */
1433 #define MPU_CTRL_PRIVDEFENA_Pos 2U
1434 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
1436 #define MPU_CTRL_HFNMIENA_Pos 1U
1437 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
1439 #define MPU_CTRL_ENABLE_Pos 0U
1440 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
1442 /* MPU Region Number Register Definitions */
1443 #define MPU_RNR_REGION_Pos 0U
1444 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
1446 /* MPU Region Base Address Register Definitions */
1447 #define MPU_RBAR_ADDR_Pos 5U
1448 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
1450 #define MPU_RBAR_VALID_Pos 4U
1451 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
1453 #define MPU_RBAR_REGION_Pos 0U
1454 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
1456 /* MPU Region Attribute and Size Register Definitions */
1457 #define MPU_RASR_ATTRS_Pos 16U
1458 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
1460 #define MPU_RASR_XN_Pos 28U
1461 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
1463 #define MPU_RASR_AP_Pos 24U
1464 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
1466 #define MPU_RASR_TEX_Pos 19U
1467 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
1469 #define MPU_RASR_S_Pos 18U
1470 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
1472 #define MPU_RASR_C_Pos 17U
1473 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
1475 #define MPU_RASR_B_Pos 16U
1476 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
1478 #define MPU_RASR_SRD_Pos 8U
1479 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
1481 #define MPU_RASR_SIZE_Pos 1U
1482 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
1484 #define MPU_RASR_ENABLE_Pos 0U
1485 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/)
1487 
1488 #endif
1489 
1490 
1491 #if (__FPU_PRESENT == 1U)
1492 
1502 typedef struct
1503 {
1504  uint32_t RESERVED0[1U];
1505  __IOM uint32_t FPCCR;
1506  __IOM uint32_t FPCAR;
1507  __IOM uint32_t FPDSCR;
1508  __IM uint32_t MVFR0;
1509  __IM uint32_t MVFR1;
1510  __IM uint32_t MVFR2;
1511 } FPU_Type;
1512 
1513 /* Floating-Point Context Control Register Definitions */
1514 #define FPU_FPCCR_ASPEN_Pos 31U
1515 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
1517 #define FPU_FPCCR_LSPEN_Pos 30U
1518 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
1520 #define FPU_FPCCR_MONRDY_Pos 8U
1521 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
1523 #define FPU_FPCCR_BFRDY_Pos 6U
1524 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
1526 #define FPU_FPCCR_MMRDY_Pos 5U
1527 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
1529 #define FPU_FPCCR_HFRDY_Pos 4U
1530 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
1532 #define FPU_FPCCR_THREAD_Pos 3U
1533 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
1535 #define FPU_FPCCR_USER_Pos 1U
1536 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
1538 #define FPU_FPCCR_LSPACT_Pos 0U
1539 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
1541 /* Floating-Point Context Address Register Definitions */
1542 #define FPU_FPCAR_ADDRESS_Pos 3U
1543 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
1545 /* Floating-Point Default Status Control Register Definitions */
1546 #define FPU_FPDSCR_AHP_Pos 26U
1547 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
1549 #define FPU_FPDSCR_DN_Pos 25U
1550 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
1552 #define FPU_FPDSCR_FZ_Pos 24U
1553 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
1555 #define FPU_FPDSCR_RMode_Pos 22U
1556 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
1558 /* Media and FP Feature Register 0 Definitions */
1559 #define FPU_MVFR0_FP_rounding_modes_Pos 28U
1560 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
1562 #define FPU_MVFR0_Short_vectors_Pos 24U
1563 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)
1565 #define FPU_MVFR0_Square_root_Pos 20U
1566 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)
1568 #define FPU_MVFR0_Divide_Pos 16U
1569 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)
1571 #define FPU_MVFR0_FP_excep_trapping_Pos 12U
1572 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
1574 #define FPU_MVFR0_Double_precision_Pos 8U
1575 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)
1577 #define FPU_MVFR0_Single_precision_Pos 4U
1578 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)
1580 #define FPU_MVFR0_A_SIMD_registers_Pos 0U
1581 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
1583 /* Media and FP Feature Register 1 Definitions */
1584 #define FPU_MVFR1_FP_fused_MAC_Pos 28U
1585 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
1587 #define FPU_MVFR1_FP_HPFP_Pos 24U
1588 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
1590 #define FPU_MVFR1_D_NaN_mode_Pos 4U
1591 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
1593 #define FPU_MVFR1_FtZ_mode_Pos 0U
1594 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
1596 /* Media and FP Feature Register 2 Definitions */
1597 
1599 #endif
1600 
1601 
1612 typedef struct
1613 {
1614  __IOM uint32_t DHCSR;
1615  __OM uint32_t DCRSR;
1616  __IOM uint32_t DCRDR;
1617  __IOM uint32_t DEMCR;
1618 } CoreDebug_Type;
1619 
1620 /* Debug Halting Control and Status Register Definitions */
1621 #define CoreDebug_DHCSR_DBGKEY_Pos 16U
1622 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1624 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U
1625 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1627 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
1628 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1630 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U
1631 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1633 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U
1634 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1636 #define CoreDebug_DHCSR_S_HALT_Pos 17U
1637 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1639 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U
1640 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1642 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
1643 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
1645 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U
1646 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1648 #define CoreDebug_DHCSR_C_STEP_Pos 2U
1649 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1651 #define CoreDebug_DHCSR_C_HALT_Pos 1U
1652 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1654 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
1655 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
1657 /* Debug Core Register Selector Register Definitions */
1658 #define CoreDebug_DCRSR_REGWnR_Pos 16U
1659 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1661 #define CoreDebug_DCRSR_REGSEL_Pos 0U
1662 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
1664 /* Debug Exception and Monitor Control Register Definitions */
1665 #define CoreDebug_DEMCR_TRCENA_Pos 24U
1666 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
1668 #define CoreDebug_DEMCR_MON_REQ_Pos 19U
1669 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
1671 #define CoreDebug_DEMCR_MON_STEP_Pos 18U
1672 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
1674 #define CoreDebug_DEMCR_MON_PEND_Pos 17U
1675 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
1677 #define CoreDebug_DEMCR_MON_EN_Pos 16U
1678 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
1680 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U
1681 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1683 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U
1684 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
1686 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U
1687 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
1689 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U
1690 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
1692 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U
1693 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
1695 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
1696 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
1698 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U
1699 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
1701 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U
1702 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
1704 
1720 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
1721 
1728 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
1729 
1740 /* Memory mapping of Cortex-M4 Hardware */
1741 #define SCS_BASE (0xE000E000UL)
1742 #define ITM_BASE (0xE0000000UL)
1743 #define DWT_BASE (0xE0001000UL)
1744 #define TPI_BASE (0xE0040000UL)
1745 #define CoreDebug_BASE (0xE000EDF0UL)
1746 #define SysTick_BASE (SCS_BASE + 0x0010UL)
1747 #define NVIC_BASE (SCS_BASE + 0x0100UL)
1748 #define SCB_BASE (SCS_BASE + 0x0D00UL)
1750 #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
1751 #define SCB ((SCB_Type *) SCB_BASE )
1752 #define SysTick ((SysTick_Type *) SysTick_BASE )
1753 #define NVIC ((NVIC_Type *) NVIC_BASE )
1754 #define ITM ((ITM_Type *) ITM_BASE )
1755 #define DWT ((DWT_Type *) DWT_BASE )
1756 #define TPI ((TPI_Type *) TPI_BASE )
1757 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)
1759 #if (__MPU_PRESENT == 1U)
1760  #define MPU_BASE (SCS_BASE + 0x0D90UL)
1761  #define MPU ((MPU_Type *) MPU_BASE )
1762 #endif
1763 
1764 #if (__FPU_PRESENT == 1U)
1765  #define FPU_BASE (SCS_BASE + 0x0F30UL)
1766  #define FPU ((FPU_Type *) FPU_BASE )
1767 #endif
1768 
1773 /*******************************************************************************
1774  * Hardware Abstraction Layer
1775  Core Function Interface contains:
1776  - Core NVIC Functions
1777  - Core SysTick Functions
1778  - Core Debug Functions
1779  - Core Register Access Functions
1780  ******************************************************************************/
1787 /* ########################## NVIC functions #################################### */
1804 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1805 {
1806  uint32_t reg_value;
1807  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1808 
1809  reg_value = SCB->AIRCR; /* read old register configuration */
1810  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
1811  reg_value = (reg_value |
1812  ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1813  (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
1814  SCB->AIRCR = reg_value;
1815 }
1816 
1817 
1823 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1824 {
1825  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1826 }
1827 
1828 
1834 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1835 {
1836  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1837 }
1838 
1839 
1845 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1846 {
1847  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1848 }
1849 
1850 
1858 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1859 {
1860  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1861 }
1862 
1863 
1869 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1870 {
1871  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1872 }
1873 
1874 
1880 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1881 {
1882  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1883 }
1884 
1885 
1893 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1894 {
1895  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1896 }
1897 
1898 
1906 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1907 {
1908  if ((int32_t)(IRQn) < 0)
1909  {
1910  SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1911  }
1912  else
1913  {
1914  NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1915  }
1916 }
1917 
1918 
1928 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1929 {
1930 
1931  if ((int32_t)(IRQn) < 0)
1932  {
1933  return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
1934  }
1935  else
1936  {
1937  return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
1938  }
1939 }
1940 
1941 
1953 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1954 {
1955  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1956  uint32_t PreemptPriorityBits;
1957  uint32_t SubPriorityBits;
1958 
1959  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1960  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1961 
1962  return (
1963  ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1964  ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1965  );
1966 }
1967 
1968 
1980 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
1981 {
1982  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1983  uint32_t PreemptPriorityBits;
1984  uint32_t SubPriorityBits;
1985 
1986  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1987  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1988 
1989  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1990  *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1991 }
1992 
1993 
1998 __STATIC_INLINE void NVIC_SystemReset(void)
1999 {
2000  __DSB(); /* Ensure all outstanding memory accesses included
2001  buffered write are completed before reset */
2002  SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2003  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
2004  SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
2005  __DSB(); /* Ensure completion of memory access */
2006 
2007  for(;;) /* wait until reset */
2008  {
2009  __NOP();
2010  }
2011 }
2012 
2016 /* ########################## FPU functions #################################### */
2032 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
2033 {
2034  uint32_t mvfr0;
2035 
2036  mvfr0 = SCB->MVFR0;
2037  if ((mvfr0 & 0x00000FF0UL) == 0x220UL)
2038  {
2039  return 2UL; /* Double + Single precision FPU */
2040  }
2041  else if ((mvfr0 & 0x00000FF0UL) == 0x020UL)
2042  {
2043  return 1UL; /* Single precision FPU */
2044  }
2045  else
2046  {
2047  return 0UL; /* No FPU */
2048  }
2049 }
2050 
2051 
2056 /* ########################## Cache functions #################################### */
2064 /* Cache Size ID Register Macros */
2065 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
2066 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
2067 
2068 
2073 __STATIC_INLINE void SCB_EnableICache (void)
2074 {
2075  #if (__ICACHE_PRESENT == 1U)
2076  __DSB();
2077  __ISB();
2078  SCB->ICIALLU = 0UL; /* invalidate I-Cache */
2079  SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
2080  __DSB();
2081  __ISB();
2082  #endif
2083 }
2084 
2085 
2090 __STATIC_INLINE void SCB_DisableICache (void)
2091 {
2092  #if (__ICACHE_PRESENT == 1U)
2093  __DSB();
2094  __ISB();
2095  SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
2096  SCB->ICIALLU = 0UL; /* invalidate I-Cache */
2097  __DSB();
2098  __ISB();
2099  #endif
2100 }
2101 
2102 
2107 __STATIC_INLINE void SCB_InvalidateICache (void)
2108 {
2109  #if (__ICACHE_PRESENT == 1U)
2110  __DSB();
2111  __ISB();
2112  SCB->ICIALLU = 0UL;
2113  __DSB();
2114  __ISB();
2115  #endif
2116 }
2117 
2118 
2123 __STATIC_INLINE void SCB_EnableDCache (void)
2124 {
2125  #if (__DCACHE_PRESENT == 1U)
2126  uint32_t ccsidr;
2127  uint32_t sets;
2128  uint32_t ways;
2129 
2130  SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
2131  __DSB();
2132 
2133  ccsidr = SCB->CCSIDR;
2134 
2135  /* invalidate D-Cache */
2136  sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2137  do {
2138  ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2139  do {
2140  SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
2141  ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
2142  #if defined ( __CC_ARM )
2143  __schedule_barrier();
2144  #endif
2145  } while (ways--);
2146  } while(sets--);
2147  __DSB();
2148 
2149  SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
2150 
2151  __DSB();
2152  __ISB();
2153  #endif
2154 }
2155 
2156 
2161 __STATIC_INLINE void SCB_DisableDCache (void)
2162 {
2163  #if (__DCACHE_PRESENT == 1U)
2164  uint32_t ccsidr;
2165  uint32_t sets;
2166  uint32_t ways;
2167 
2168  SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
2169  __DSB();
2170 
2171  ccsidr = SCB->CCSIDR;
2172 
2173  SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
2174 
2175  /* clean & invalidate D-Cache */
2176  sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2177  do {
2178  ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2179  do {
2180  SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
2181  ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
2182  #if defined ( __CC_ARM )
2183  __schedule_barrier();
2184  #endif
2185  } while (ways--);
2186  } while(sets--);
2187 
2188  __DSB();
2189  __ISB();
2190  #endif
2191 }
2192 
2193 
2198 __STATIC_INLINE void SCB_InvalidateDCache (void)
2199 {
2200  #if (__DCACHE_PRESENT == 1U)
2201  uint32_t ccsidr;
2202  uint32_t sets;
2203  uint32_t ways;
2204 
2205  SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
2206  __DSB();
2207 
2208  ccsidr = SCB->CCSIDR;
2209 
2210  /* invalidate D-Cache */
2211  sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2212  do {
2213  ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2214  do {
2215  SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
2216  ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
2217  #if defined ( __CC_ARM )
2218  __schedule_barrier();
2219  #endif
2220  } while (ways--);
2221  } while(sets--);
2222 
2223  __DSB();
2224  __ISB();
2225  #endif
2226 }
2227 
2228 
2233 __STATIC_INLINE void SCB_CleanDCache (void)
2234 {
2235  #if (__DCACHE_PRESENT == 1U)
2236  uint32_t ccsidr;
2237  uint32_t sets;
2238  uint32_t ways;
2239 
2240  SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
2241  __DSB();
2242 
2243  ccsidr = SCB->CCSIDR;
2244 
2245  /* clean D-Cache */
2246  sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2247  do {
2248  ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2249  do {
2250  SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
2251  ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
2252  #if defined ( __CC_ARM )
2253  __schedule_barrier();
2254  #endif
2255  } while (ways--);
2256  } while(sets--);
2257 
2258  __DSB();
2259  __ISB();
2260  #endif
2261 }
2262 
2263 
2268 __STATIC_INLINE void SCB_CleanInvalidateDCache (void)
2269 {
2270  #if (__DCACHE_PRESENT == 1U)
2271  uint32_t ccsidr;
2272  uint32_t sets;
2273  uint32_t ways;
2274 
2275  SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
2276  __DSB();
2277 
2278  ccsidr = SCB->CCSIDR;
2279 
2280  /* clean & invalidate D-Cache */
2281  sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2282  do {
2283  ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2284  do {
2285  SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
2286  ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
2287  #if defined ( __CC_ARM )
2288  __schedule_barrier();
2289  #endif
2290  } while (ways--);
2291  } while(sets--);
2292 
2293  __DSB();
2294  __ISB();
2295  #endif
2296 }
2297 
2298 
2305 __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
2306 {
2307  #if (__DCACHE_PRESENT == 1U)
2308  int32_t op_size = dsize;
2309  uint32_t op_addr = (uint32_t)addr;
2310  int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
2311 
2312  __DSB();
2313 
2314  while (op_size > 0) {
2315  SCB->DCIMVAC = op_addr;
2316  op_addr += linesize;
2317  op_size -= linesize;
2318  }
2319 
2320  __DSB();
2321  __ISB();
2322  #endif
2323 }
2324 
2325 
2332 __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
2333 {
2334  #if (__DCACHE_PRESENT == 1)
2335  int32_t op_size = dsize;
2336  uint32_t op_addr = (uint32_t) addr;
2337  int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
2338 
2339  __DSB();
2340 
2341  while (op_size > 0) {
2342  SCB->DCCMVAC = op_addr;
2343  op_addr += linesize;
2344  op_size -= linesize;
2345  }
2346 
2347  __DSB();
2348  __ISB();
2349  #endif
2350 }
2351 
2352 
2359 __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
2360 {
2361  #if (__DCACHE_PRESENT == 1U)
2362  int32_t op_size = dsize;
2363  uint32_t op_addr = (uint32_t) addr;
2364  int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
2365 
2366  __DSB();
2367 
2368  while (op_size > 0) {
2369  SCB->DCCIMVAC = op_addr;
2370  op_addr += linesize;
2371  op_size -= linesize;
2372  }
2373 
2374  __DSB();
2375  __ISB();
2376  #endif
2377 }
2378 
2379 
2384 /* ################################## SysTick function ############################################ */
2392 #if (__Vendor_SysTickConfig == 0U)
2393 
2405 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2406 {
2407  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2408  {
2409  return (1UL); /* Reload value impossible */
2410  }
2411 
2412  SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2413  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2414  SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2415  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2416  SysTick_CTRL_TICKINT_Msk |
2417  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2418  return (0UL); /* Function successful */
2419 }
2420 
2421 #endif
2422 
2427 /* ##################################### Debug In/Output function ########################################### */
2435 extern volatile int32_t ITM_RxBuffer;
2436 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5U
2447 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
2448 {
2449  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
2450  ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
2451  {
2452  while (ITM->PORT[0U].u32 == 0UL)
2453  {
2454  __NOP();
2455  }
2456  ITM->PORT[0U].u8 = (uint8_t)ch;
2457  }
2458  return (ch);
2459 }
2460 
2461 
2468 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
2469 {
2470  int32_t ch = -1; /* no character available */
2471 
2472  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
2473  {
2474  ch = ITM_RxBuffer;
2475  ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
2476  }
2477 
2478  return (ch);
2479 }
2480 
2481 
2488 __STATIC_INLINE int32_t ITM_CheckChar (void)
2489 {
2490 
2491  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
2492  {
2493  return (0); /* no character available */
2494  }
2495  else
2496  {
2497  return (1); /* character available */
2498  }
2499 }
2500 
2506 #ifdef __cplusplus
2507 }
2508 #endif
2509 
2510 #endif /* __CORE_CM7_H_DEPENDANT */
2511 
2512 #endif /* __CMSIS_GENERIC */
SCB_Type::CSSELR
__IOM uint32_t CSSELR
Definition: core_cm7.h:525
ITM
#define ITM
Definition: core_cm7.h:1754
core_cmFunc.h
CMSIS Cortex-M Core Function Access Header File.
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: core_cm3.h:838
__NOP
#define __NOP
No Operation.
Definition: cmsis_armcc.h:313
SCB_Type::CTR
__IM uint32_t CTR
Definition: core_cm7.h:523
SCB_CleanInvalidateDCache_by_Addr
__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr(uint32_t *addr, int32_t dsize)
D-Cache Clean and Invalidate by address.
Definition: core_cm7.h:2359
SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
Definition: core_cm7.h:616
SCB_Type::STIR
__OM uint32_t STIR
Definition: core_cm7.h:528
SCB_DCCISW_WAY_Msk
#define SCB_DCCISW_WAY_Msk
Definition: core_cm7.h:816
NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_cm0.h:653
NVIC_SetPendingIRQ
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_cm0.h:664
SCB_Type::ID_DFR
__IM uint32_t ID_DFR
Definition: core_cm7.h:517
SCB_Type::MVFR0
__IM uint32_t MVFR0
Definition: core_cm7.h:530
CCSIDR_SETS
#define CCSIDR_SETS(x)
Definition: core_cm7.h:2066
SCB_DCISW_WAY_Pos
#define SCB_DCISW_WAY_Pos
Definition: core_cm7.h:801
SCB_Type::DTCMCR
__IOM uint32_t DTCMCR
Definition: core_cm7.h:546
SCB_Type::DCCSW
__OM uint32_t DCCSW
Definition: core_cm7.h:541
NVIC_GetPriorityGrouping
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
Definition: core_cm3.h:1441
SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
Definition: core_cm7.h:607
SCB_InvalidateDCache_by_Addr
__STATIC_INLINE void SCB_InvalidateDCache_by_Addr(uint32_t *addr, int32_t dsize)
D-Cache Invalidate by address.
Definition: core_cm7.h:2305
ch
return ch
Definition: lcd_log.c:311
SCB_Type::DCCMVAU
__OM uint32_t DCCMVAU
Definition: core_cm7.h:539
SysTick
#define SysTick
Definition: core_cm7.h:1752
ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Definition: core_cm7.h:2436
DWT_Type::LAR
__OM uint32_t LAR
Definition: core_cm7.h:1127
SCB_Type::CACR
__IOM uint32_t CACR
Definition: core_cm7.h:548
ITM_RxBuffer
volatile int32_t ITM_RxBuffer
ITM_ReceiveChar
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition: core_cm3.h:1719
__OM
#define __OM
Definition: core_cm7.h:290
SCB_Type::AHBSCR
__IOM uint32_t AHBSCR
Definition: core_cm7.h:549
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_cm0.h:277
SCB_Type::ITCMCR
__IOM uint32_t ITCMCR
Definition: core_cm7.h:545
SCB_CleanDCache
__STATIC_INLINE void SCB_CleanDCache(void)
Clean D-Cache.
Definition: core_cm7.h:2233
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition: core_cm3.h:985
ITM_CheckChar
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition: core_cm3.h:1739
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: core_cm7.h:2032
SCB_Type::DCCIMVAC
__OM uint32_t DCCIMVAC
Definition: core_cm7.h:542
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: core_cm3.h:1598
SCB_DisableICache
__STATIC_INLINE void SCB_DisableICache(void)
Disable I-Cache.
Definition: core_cm7.h:2090
SCB_Type::AHBPCR
__IOM uint32_t AHBPCR
Definition: core_cm7.h:547
__DSB
#define __DSB()
Data Synchronization Barrier.
Definition: cmsis_armcc.h:355
NVIC
#define NVIC
Definition: core_cm7.h:1753
SCB_CCR_DC_Msk
#define SCB_CCR_DC_Msk
Definition: core_cm7.h:645
SCB_Type::DCIMVAC
__OM uint32_t DCIMVAC
Definition: core_cm7.h:537
NVIC_EnableIRQ
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable External Interrupt.
Definition: core_cm0.h:629
SysTick_IRQn
Definition: stm32f745xx.h:77
CoreDebug_Type
Structure type to access the Core Debug Register (CoreDebug).
Definition: core_cm3.h:1235
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: core_cm0.h:389
ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
Definition: core_cm7.h:1064
SCB
#define SCB
Definition: core_cm7.h:1751
ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition: core_cm3.h:735
SCB_DisableDCache
__STATIC_INLINE void SCB_DisableDCache(void)
Disable D-Cache.
Definition: core_cm7.h:2161
core_cmSimd.h
CMSIS Cortex-M SIMD Header File.
IRQn_Type
IRQn_Type
STM32F7xx Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f745xx.h:67
NVIC_SetPriorityGrouping
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
Definition: core_cm3.h:1422
SCB_DCCISW_SET_Pos
#define SCB_DCCISW_SET_Pos
Definition: core_cm7.h:818
SysTick_Config
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
System Tick Configuration.
Definition: core_cm0.h:769
SCB_Type::ICIALLU
__OM uint32_t ICIALLU
Definition: core_cm7.h:534
NVIC_GetPriority
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_cm0.h:712
SCB_EnableICache
__STATIC_INLINE void SCB_EnableICache(void)
Enable I-Cache.
Definition: core_cm7.h:2073
SCB_InvalidateICache
__STATIC_INLINE void SCB_InvalidateICache(void)
Invalidate I-Cache.
Definition: core_cm7.h:2107
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: stm32f745xx.h:185
SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
Definition: core_cm7.h:615
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition: core_cm3.h:644
__IOM
#define __IOM
Definition: core_cm7.h:291
NVIC_SetPriority
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_cm0.h:688
SCB_DCISW_SET_Pos
#define SCB_DCISW_SET_Pos
Definition: core_cm7.h:804
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_cm0.h:362
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: core_cm0.h:496
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_cm7.h:606
NVIC_SystemReset
__STATIC_INLINE void NVIC_SystemReset(void)
System Reset.
Definition: core_cm0.h:730
SCB_Type::ICIMVAU
__OM uint32_t ICIMVAU
Definition: core_cm7.h:536
__IM
#define __IM
Definition: core_cm7.h:289
CCSIDR_WAYS
#define CCSIDR_WAYS(x)
Definition: core_cm7.h:2065
SCB_Type::ABFSR
__IOM uint32_t ABFSR
Definition: core_cm7.h:551
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_cm7.h:619
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: core_cm0.h:247
SCB_Type::MVFR1
__IM uint32_t MVFR1
Definition: core_cm7.h:531
NVIC_DisableIRQ
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Disable External Interrupt.
Definition: core_cm0.h:640
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_cm7.h:969
SCB_CCR_IC_Msk
#define SCB_CCR_IC_Msk
Definition: core_cm7.h:642
__ISB
#define __ISB()
Instruction Synchronization Barrier.
Definition: cmsis_armcc.h:344
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: core_cm0.h:334
SCB_CleanInvalidateDCache
__STATIC_INLINE void SCB_CleanInvalidateDCache(void)
Clean & Invalidate D-Cache.
Definition: core_cm7.h:2268
DWT_Type::LSR
__IM uint32_t LSR
Definition: core_cm7.h:1128
SCB_Type::ID_AFR
__IM uint32_t ID_AFR
Definition: core_cm7.h:518
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_cm7.h:959
SCB_CleanDCache_by_Addr
__STATIC_INLINE void SCB_CleanDCache_by_Addr(uint32_t *addr, int32_t dsize)
D-Cache Clean by address.
Definition: core_cm7.h:2332
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_cm7.h:965
NVIC_ClearPendingIRQ
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_cm0.h:675
SCB_DCISW_WAY_Msk
#define SCB_DCISW_WAY_Msk
Definition: core_cm7.h:802
SCB_DCCSW_WAY_Pos
#define SCB_DCCSW_WAY_Pos
Definition: core_cm7.h:808
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: core_cm3.h:1571
core_cmInstr.h
CMSIS Cortex-M Core Instruction Access Header File.
SCB_DCISW_SET_Msk
#define SCB_DCISW_SET_Msk
Definition: core_cm7.h:805
SCB_DCCSW_SET_Msk
#define SCB_DCCSW_SET_Msk
Definition: core_cm7.h:812
SCB_InvalidateDCache
__STATIC_INLINE void SCB_InvalidateDCache(void)
Invalidate D-Cache.
Definition: core_cm7.h:2198
SCB_EnableDCache
__STATIC_INLINE void SCB_EnableDCache(void)
Enable D-Cache.
Definition: core_cm7.h:2123
SCB_Type::CLIDR
__IM uint32_t CLIDR
Definition: core_cm7.h:522
NVIC_GetActive
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: core_cm3.h:1511
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_cm0.h:295
SCB_DCCSW_WAY_Msk
#define SCB_DCCSW_WAY_Msk
Definition: core_cm7.h:809
SCB_Type::CCSIDR
__IM uint32_t CCSIDR
Definition: core_cm7.h:524
SCB_Type::MVFR2
__IM uint32_t MVFR2
Definition: core_cm7.h:532
SCB_DCCISW_SET_Msk
#define SCB_DCCISW_SET_Msk
Definition: core_cm7.h:819
SCB_Type::DCCISW
__OM uint32_t DCCISW
Definition: core_cm7.h:543
SCB_DCCISW_WAY_Pos
#define SCB_DCCISW_WAY_Pos
Definition: core_cm7.h:815
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_cm7.h:962
SCB_Type::DCISW
__OM uint32_t DCISW
Definition: core_cm7.h:538
SCB_Type::DCCMVAC
__OM uint32_t DCCMVAC
Definition: core_cm7.h:540
SCB_DCCSW_SET_Pos
#define SCB_DCCSW_SET_Pos
Definition: core_cm7.h:811
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