STM32F769IDiscovery  1.00
uDANTE Audio Networking with STM32F7 DISCO board
core_cm3.h
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1 /**************************************************************************/
7 /* Copyright (c) 2009 - 2015 ARM LIMITED
8 
9  All rights reserved.
10  Redistribution and use in source and binary forms, with or without
11  modification, are permitted provided that the following conditions are met:
12  - Redistributions of source code must retain the above copyright
13  notice, this list of conditions and the following disclaimer.
14  - Redistributions in binary form must reproduce the above copyright
15  notice, this list of conditions and the following disclaimer in the
16  documentation and/or other materials provided with the distribution.
17  - Neither the name of ARM nor the names of its contributors may be used
18  to endorse or promote products derived from this software without
19  specific prior written permission.
20  *
21  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
25  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  POSSIBILITY OF SUCH DAMAGE.
32  ---------------------------------------------------------------------------*/
33 
34 
35 #if defined ( __ICCARM__ )
36  #pragma system_include /* treat file as system include file for MISRA check */
37 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
38  #pragma clang system_header /* treat file as system include file */
39 #endif
40 
41 #ifndef __CORE_CM3_H_GENERIC
42 #define __CORE_CM3_H_GENERIC
43 
44 #include <stdint.h>
45 
46 #ifdef __cplusplus
47  extern "C" {
48 #endif
49 
65 /*******************************************************************************
66  * CMSIS definitions
67  ******************************************************************************/
73 /* CMSIS CM3 definitions */
74 #define __CM3_CMSIS_VERSION_MAIN (0x04U)
75 #define __CM3_CMSIS_VERSION_SUB (0x1EU)
76 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
77  __CM3_CMSIS_VERSION_SUB )
79 #define __CORTEX_M (0x03U)
82 #if defined ( __CC_ARM )
83  #define __ASM __asm
84  #define __INLINE __inline
85  #define __STATIC_INLINE static __inline
86 
87 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
88  #define __ASM __asm
89  #define __INLINE __inline
90  #define __STATIC_INLINE static __inline
91 
92 #elif defined ( __GNUC__ )
93  #define __ASM __asm
94  #define __INLINE inline
95  #define __STATIC_INLINE static inline
96 
97 #elif defined ( __ICCARM__ )
98  #define __ASM __asm
99  #define __INLINE inline
100  #define __STATIC_INLINE static inline
101 
102 #elif defined ( __TMS470__ )
103  #define __ASM __asm
104  #define __STATIC_INLINE static inline
105 
106 #elif defined ( __TASKING__ )
107  #define __ASM __asm
108  #define __INLINE inline
109  #define __STATIC_INLINE static inline
110 
111 #elif defined ( __CSMC__ )
112  #define __packed
113  #define __ASM _asm
114  #define __INLINE inline
115  #define __STATIC_INLINE static inline
116 
117 #else
118  #error Unknown compiler
119 #endif
120 
124 #define __FPU_USED 0U
125 
126 #if defined ( __CC_ARM )
127  #if defined __TARGET_FPU_VFP
128  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
129  #endif
130 
131 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
132  #if defined __ARM_PCS_VFP
133  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
134  #endif
135 
136 #elif defined ( __GNUC__ )
137  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
138  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
139  #endif
140 
141 #elif defined ( __ICCARM__ )
142  #if defined __ARMVFP__
143  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
144  #endif
145 
146 #elif defined ( __TMS470__ )
147  #if defined __TI_VFP_SUPPORT__
148  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
149  #endif
150 
151 #elif defined ( __TASKING__ )
152  #if defined __FPU_VFP__
153  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
154  #endif
155 
156 #elif defined ( __CSMC__ )
157  #if ( __CSMC__ & 0x400U)
158  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
159  #endif
160 
161 #endif
162 
163 #include "core_cmInstr.h" /* Core Instruction Access */
164 #include "core_cmFunc.h" /* Core Function Access */
165 
166 #ifdef __cplusplus
167 }
168 #endif
169 
170 #endif /* __CORE_CM3_H_GENERIC */
171 
172 #ifndef __CMSIS_GENERIC
173 
174 #ifndef __CORE_CM3_H_DEPENDANT
175 #define __CORE_CM3_H_DEPENDANT
176 
177 #ifdef __cplusplus
178  extern "C" {
179 #endif
180 
181 /* check device defines and use defaults */
182 #if defined __CHECK_DEVICE_DEFINES
183  #ifndef __CM3_REV
184  #define __CM3_REV 0x0200U
185  #warning "__CM3_REV not defined in device header file; using default!"
186  #endif
187 
188  #ifndef __MPU_PRESENT
189  #define __MPU_PRESENT 0U
190  #warning "__MPU_PRESENT not defined in device header file; using default!"
191  #endif
192 
193  #ifndef __NVIC_PRIO_BITS
194  #define __NVIC_PRIO_BITS 4U
195  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
196  #endif
197 
198  #ifndef __Vendor_SysTickConfig
199  #define __Vendor_SysTickConfig 0U
200  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
201  #endif
202 #endif
203 
204 /* IO definitions (access restrictions to peripheral registers) */
212 #ifdef __cplusplus
213  #define __I volatile
214 #else
215  #define __I volatile const
216 #endif
217 #define __O volatile
218 #define __IO volatile
220 /* following defines should be used for structure members */
221 #define __IM volatile const
222 #define __OM volatile
223 #define __IOM volatile
225 
229 /*******************************************************************************
230  * Register Abstraction
231  Core Register contain:
232  - Core Register
233  - Core NVIC Register
234  - Core SCB Register
235  - Core SysTick Register
236  - Core Debug Register
237  - Core MPU Register
238  ******************************************************************************/
239 
254 typedef union
255 {
256  struct
257  {
258  uint32_t _reserved0:27;
259  uint32_t Q:1;
260  uint32_t V:1;
261  uint32_t C:1;
262  uint32_t Z:1;
263  uint32_t N:1;
264  } b;
265  uint32_t w;
266 } APSR_Type;
267 
268 /* APSR Register Definitions */
269 #define APSR_N_Pos 31U
270 #define APSR_N_Msk (1UL << APSR_N_Pos)
272 #define APSR_Z_Pos 30U
273 #define APSR_Z_Msk (1UL << APSR_Z_Pos)
275 #define APSR_C_Pos 29U
276 #define APSR_C_Msk (1UL << APSR_C_Pos)
278 #define APSR_V_Pos 28U
279 #define APSR_V_Msk (1UL << APSR_V_Pos)
281 #define APSR_Q_Pos 27U
282 #define APSR_Q_Msk (1UL << APSR_Q_Pos)
288 typedef union
289 {
290  struct
291  {
292  uint32_t ISR:9;
293  uint32_t _reserved0:23;
294  } b;
295  uint32_t w;
296 } IPSR_Type;
297 
298 /* IPSR Register Definitions */
299 #define IPSR_ISR_Pos 0U
300 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
306 typedef union
307 {
308  struct
309  {
310  uint32_t ISR:9;
311  uint32_t _reserved0:15;
312  uint32_t T:1;
313  uint32_t IT:2;
314  uint32_t Q:1;
315  uint32_t V:1;
316  uint32_t C:1;
317  uint32_t Z:1;
318  uint32_t N:1;
319  } b;
320  uint32_t w;
321 } xPSR_Type;
322 
323 /* xPSR Register Definitions */
324 #define xPSR_N_Pos 31U
325 #define xPSR_N_Msk (1UL << xPSR_N_Pos)
327 #define xPSR_Z_Pos 30U
328 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
330 #define xPSR_C_Pos 29U
331 #define xPSR_C_Msk (1UL << xPSR_C_Pos)
333 #define xPSR_V_Pos 28U
334 #define xPSR_V_Msk (1UL << xPSR_V_Pos)
336 #define xPSR_Q_Pos 27U
337 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos)
339 #define xPSR_IT_Pos 25U
340 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos)
342 #define xPSR_T_Pos 24U
343 #define xPSR_T_Msk (1UL << xPSR_T_Pos)
345 #define xPSR_ISR_Pos 0U
346 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
352 typedef union
353 {
354  struct
355  {
356  uint32_t nPRIV:1;
357  uint32_t SPSEL:1;
358  uint32_t _reserved1:30;
359  } b;
360  uint32_t w;
361 } CONTROL_Type;
362 
363 /* CONTROL Register Definitions */
364 #define CONTROL_SPSEL_Pos 1U
365 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
367 #define CONTROL_nPRIV_Pos 0U
368 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)
370 
383 typedef struct
384 {
385  __IOM uint32_t ISER[8U];
386  uint32_t RESERVED0[24U];
387  __IOM uint32_t ICER[8U];
388  uint32_t RSERVED1[24U];
389  __IOM uint32_t ISPR[8U];
390  uint32_t RESERVED2[24U];
391  __IOM uint32_t ICPR[8U];
392  uint32_t RESERVED3[24U];
393  __IOM uint32_t IABR[8U];
394  uint32_t RESERVED4[56U];
395  __IOM uint8_t IP[240U];
396  uint32_t RESERVED5[644U];
397  __OM uint32_t STIR;
398 } NVIC_Type;
399 
400 /* Software Triggered Interrupt Register Definitions */
401 #define NVIC_STIR_INTID_Pos 0U
402 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
404 
417 typedef struct
418 {
419  __IM uint32_t CPUID;
420  __IOM uint32_t ICSR;
421  __IOM uint32_t VTOR;
422  __IOM uint32_t AIRCR;
423  __IOM uint32_t SCR;
424  __IOM uint32_t CCR;
425  __IOM uint8_t SHP[12U];
426  __IOM uint32_t SHCSR;
427  __IOM uint32_t CFSR;
428  __IOM uint32_t HFSR;
429  __IOM uint32_t DFSR;
430  __IOM uint32_t MMFAR;
431  __IOM uint32_t BFAR;
432  __IOM uint32_t AFSR;
433  __IM uint32_t PFR[2U];
434  __IM uint32_t DFR;
435  __IM uint32_t ADR;
436  __IM uint32_t MMFR[4U];
437  __IM uint32_t ISAR[5U];
438  uint32_t RESERVED0[5U];
439  __IOM uint32_t CPACR;
440 } SCB_Type;
441 
442 /* SCB CPUID Register Definitions */
443 #define SCB_CPUID_IMPLEMENTER_Pos 24U
444 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
446 #define SCB_CPUID_VARIANT_Pos 20U
447 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
449 #define SCB_CPUID_ARCHITECTURE_Pos 16U
450 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
452 #define SCB_CPUID_PARTNO_Pos 4U
453 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
455 #define SCB_CPUID_REVISION_Pos 0U
456 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
458 /* SCB Interrupt Control State Register Definitions */
459 #define SCB_ICSR_NMIPENDSET_Pos 31U
460 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
462 #define SCB_ICSR_PENDSVSET_Pos 28U
463 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
465 #define SCB_ICSR_PENDSVCLR_Pos 27U
466 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
468 #define SCB_ICSR_PENDSTSET_Pos 26U
469 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
471 #define SCB_ICSR_PENDSTCLR_Pos 25U
472 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
474 #define SCB_ICSR_ISRPREEMPT_Pos 23U
475 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
477 #define SCB_ICSR_ISRPENDING_Pos 22U
478 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
480 #define SCB_ICSR_VECTPENDING_Pos 12U
481 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
483 #define SCB_ICSR_RETTOBASE_Pos 11U
484 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
486 #define SCB_ICSR_VECTACTIVE_Pos 0U
487 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
489 /* SCB Vector Table Offset Register Definitions */
490 #if (__CM3_REV < 0x0201U) /* core r2p1 */
491 #define SCB_VTOR_TBLBASE_Pos 29U
492 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos)
494 #define SCB_VTOR_TBLOFF_Pos 7U
495 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)
496 #else
497 #define SCB_VTOR_TBLOFF_Pos 7U
498 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
499 #endif
500 
501 /* SCB Application Interrupt and Reset Control Register Definitions */
502 #define SCB_AIRCR_VECTKEY_Pos 16U
503 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
505 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U
506 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
508 #define SCB_AIRCR_ENDIANESS_Pos 15U
509 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
511 #define SCB_AIRCR_PRIGROUP_Pos 8U
512 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
514 #define SCB_AIRCR_SYSRESETREQ_Pos 2U
515 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
517 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
518 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
520 #define SCB_AIRCR_VECTRESET_Pos 0U
521 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
523 /* SCB System Control Register Definitions */
524 #define SCB_SCR_SEVONPEND_Pos 4U
525 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
527 #define SCB_SCR_SLEEPDEEP_Pos 2U
528 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
530 #define SCB_SCR_SLEEPONEXIT_Pos 1U
531 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
533 /* SCB Configuration Control Register Definitions */
534 #define SCB_CCR_STKALIGN_Pos 9U
535 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
537 #define SCB_CCR_BFHFNMIGN_Pos 8U
538 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
540 #define SCB_CCR_DIV_0_TRP_Pos 4U
541 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
543 #define SCB_CCR_UNALIGN_TRP_Pos 3U
544 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
546 #define SCB_CCR_USERSETMPEND_Pos 1U
547 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
549 #define SCB_CCR_NONBASETHRDENA_Pos 0U
550 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
552 /* SCB System Handler Control and State Register Definitions */
553 #define SCB_SHCSR_USGFAULTENA_Pos 18U
554 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
556 #define SCB_SHCSR_BUSFAULTENA_Pos 17U
557 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
559 #define SCB_SHCSR_MEMFAULTENA_Pos 16U
560 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
562 #define SCB_SHCSR_SVCALLPENDED_Pos 15U
563 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
565 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U
566 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
568 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U
569 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
571 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U
572 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
574 #define SCB_SHCSR_SYSTICKACT_Pos 11U
575 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
577 #define SCB_SHCSR_PENDSVACT_Pos 10U
578 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
580 #define SCB_SHCSR_MONITORACT_Pos 8U
581 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
583 #define SCB_SHCSR_SVCALLACT_Pos 7U
584 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
586 #define SCB_SHCSR_USGFAULTACT_Pos 3U
587 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
589 #define SCB_SHCSR_BUSFAULTACT_Pos 1U
590 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
592 #define SCB_SHCSR_MEMFAULTACT_Pos 0U
593 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
595 /* SCB Configurable Fault Status Register Definitions */
596 #define SCB_CFSR_USGFAULTSR_Pos 16U
597 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
599 #define SCB_CFSR_BUSFAULTSR_Pos 8U
600 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
602 #define SCB_CFSR_MEMFAULTSR_Pos 0U
603 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
605 /* SCB Hard Fault Status Register Definitions */
606 #define SCB_HFSR_DEBUGEVT_Pos 31U
607 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
609 #define SCB_HFSR_FORCED_Pos 30U
610 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
612 #define SCB_HFSR_VECTTBL_Pos 1U
613 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
615 /* SCB Debug Fault Status Register Definitions */
616 #define SCB_DFSR_EXTERNAL_Pos 4U
617 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
619 #define SCB_DFSR_VCATCH_Pos 3U
620 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
622 #define SCB_DFSR_DWTTRAP_Pos 2U
623 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
625 #define SCB_DFSR_BKPT_Pos 1U
626 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
628 #define SCB_DFSR_HALTED_Pos 0U
629 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)
631 
644 typedef struct
645 {
646  uint32_t RESERVED0[1U];
647  __IM uint32_t ICTR;
648 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200U))
649  __IOM uint32_t ACTLR;
650 #else
651  uint32_t RESERVED1[1U];
652 #endif
653 } SCnSCB_Type;
654 
655 /* Interrupt Controller Type Register Definitions */
656 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U
657 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
659 /* Auxiliary Control Register Definitions */
660 
661 #define SCnSCB_ACTLR_DISFOLD_Pos 2U
662 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)
664 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U
665 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)
667 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U
668 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)
670 
683 typedef struct
684 {
685  __IOM uint32_t CTRL;
686  __IOM uint32_t LOAD;
687  __IOM uint32_t VAL;
688  __IM uint32_t CALIB;
689 } SysTick_Type;
690 
691 /* SysTick Control / Status Register Definitions */
692 #define SysTick_CTRL_COUNTFLAG_Pos 16U
693 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
695 #define SysTick_CTRL_CLKSOURCE_Pos 2U
696 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
698 #define SysTick_CTRL_TICKINT_Pos 1U
699 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
701 #define SysTick_CTRL_ENABLE_Pos 0U
702 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
704 /* SysTick Reload Register Definitions */
705 #define SysTick_LOAD_RELOAD_Pos 0U
706 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
708 /* SysTick Current Register Definitions */
709 #define SysTick_VAL_CURRENT_Pos 0U
710 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
712 /* SysTick Calibration Register Definitions */
713 #define SysTick_CALIB_NOREF_Pos 31U
714 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
716 #define SysTick_CALIB_SKEW_Pos 30U
717 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
719 #define SysTick_CALIB_TENMS_Pos 0U
720 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
722 
735 typedef struct
736 {
737  __OM union
738  {
739  __OM uint8_t u8;
740  __OM uint16_t u16;
741  __OM uint32_t u32;
742  } PORT [32U];
743  uint32_t RESERVED0[864U];
744  __IOM uint32_t TER;
745  uint32_t RESERVED1[15U];
746  __IOM uint32_t TPR;
747  uint32_t RESERVED2[15U];
748  __IOM uint32_t TCR;
749  uint32_t RESERVED3[29U];
750  __OM uint32_t IWR;
751  __IM uint32_t IRR;
752  __IOM uint32_t IMCR;
753  uint32_t RESERVED4[43U];
754  __OM uint32_t LAR;
755  __IM uint32_t LSR;
756  uint32_t RESERVED5[6U];
757  __IM uint32_t PID4;
758  __IM uint32_t PID5;
759  __IM uint32_t PID6;
760  __IM uint32_t PID7;
761  __IM uint32_t PID0;
762  __IM uint32_t PID1;
763  __IM uint32_t PID2;
764  __IM uint32_t PID3;
765  __IM uint32_t CID0;
766  __IM uint32_t CID1;
767  __IM uint32_t CID2;
768  __IM uint32_t CID3;
769 } ITM_Type;
770 
771 /* ITM Trace Privilege Register Definitions */
772 #define ITM_TPR_PRIVMASK_Pos 0U
773 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
775 /* ITM Trace Control Register Definitions */
776 #define ITM_TCR_BUSY_Pos 23U
777 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
779 #define ITM_TCR_TraceBusID_Pos 16U
780 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)
782 #define ITM_TCR_GTSFREQ_Pos 10U
783 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
785 #define ITM_TCR_TSPrescale_Pos 8U
786 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)
788 #define ITM_TCR_SWOENA_Pos 4U
789 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
791 #define ITM_TCR_DWTENA_Pos 3U
792 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
794 #define ITM_TCR_SYNCENA_Pos 2U
795 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
797 #define ITM_TCR_TSENA_Pos 1U
798 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
800 #define ITM_TCR_ITMENA_Pos 0U
801 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)
803 /* ITM Integration Write Register Definitions */
804 #define ITM_IWR_ATVALIDM_Pos 0U
805 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)
807 /* ITM Integration Read Register Definitions */
808 #define ITM_IRR_ATREADYM_Pos 0U
809 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)
811 /* ITM Integration Mode Control Register Definitions */
812 #define ITM_IMCR_INTEGRATION_Pos 0U
813 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)
815 /* ITM Lock Status Register Definitions */
816 #define ITM_LSR_ByteAcc_Pos 2U
817 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
819 #define ITM_LSR_Access_Pos 1U
820 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
822 #define ITM_LSR_Present_Pos 0U
823 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)
825  /* end of group CMSIS_ITM */
826 
827 
838 typedef struct
839 {
840  __IOM uint32_t CTRL;
841  __IOM uint32_t CYCCNT;
842  __IOM uint32_t CPICNT;
843  __IOM uint32_t EXCCNT;
844  __IOM uint32_t SLEEPCNT;
845  __IOM uint32_t LSUCNT;
846  __IOM uint32_t FOLDCNT;
847  __IM uint32_t PCSR;
848  __IOM uint32_t COMP0;
849  __IOM uint32_t MASK0;
850  __IOM uint32_t FUNCTION0;
851  uint32_t RESERVED0[1U];
852  __IOM uint32_t COMP1;
853  __IOM uint32_t MASK1;
854  __IOM uint32_t FUNCTION1;
855  uint32_t RESERVED1[1U];
856  __IOM uint32_t COMP2;
857  __IOM uint32_t MASK2;
858  __IOM uint32_t FUNCTION2;
859  uint32_t RESERVED2[1U];
860  __IOM uint32_t COMP3;
861  __IOM uint32_t MASK3;
862  __IOM uint32_t FUNCTION3;
863 } DWT_Type;
864 
865 /* DWT Control Register Definitions */
866 #define DWT_CTRL_NUMCOMP_Pos 28U
867 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
869 #define DWT_CTRL_NOTRCPKT_Pos 27U
870 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
872 #define DWT_CTRL_NOEXTTRIG_Pos 26U
873 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
875 #define DWT_CTRL_NOCYCCNT_Pos 25U
876 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
878 #define DWT_CTRL_NOPRFCNT_Pos 24U
879 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
881 #define DWT_CTRL_CYCEVTENA_Pos 22U
882 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
884 #define DWT_CTRL_FOLDEVTENA_Pos 21U
885 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
887 #define DWT_CTRL_LSUEVTENA_Pos 20U
888 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
890 #define DWT_CTRL_SLEEPEVTENA_Pos 19U
891 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
893 #define DWT_CTRL_EXCEVTENA_Pos 18U
894 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
896 #define DWT_CTRL_CPIEVTENA_Pos 17U
897 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
899 #define DWT_CTRL_EXCTRCENA_Pos 16U
900 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
902 #define DWT_CTRL_PCSAMPLENA_Pos 12U
903 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
905 #define DWT_CTRL_SYNCTAP_Pos 10U
906 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
908 #define DWT_CTRL_CYCTAP_Pos 9U
909 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
911 #define DWT_CTRL_POSTINIT_Pos 5U
912 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
914 #define DWT_CTRL_POSTPRESET_Pos 1U
915 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
917 #define DWT_CTRL_CYCCNTENA_Pos 0U
918 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
920 /* DWT CPI Count Register Definitions */
921 #define DWT_CPICNT_CPICNT_Pos 0U
922 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
924 /* DWT Exception Overhead Count Register Definitions */
925 #define DWT_EXCCNT_EXCCNT_Pos 0U
926 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
928 /* DWT Sleep Count Register Definitions */
929 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U
930 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
932 /* DWT LSU Count Register Definitions */
933 #define DWT_LSUCNT_LSUCNT_Pos 0U
934 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
936 /* DWT Folded-instruction Count Register Definitions */
937 #define DWT_FOLDCNT_FOLDCNT_Pos 0U
938 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
940 /* DWT Comparator Mask Register Definitions */
941 #define DWT_MASK_MASK_Pos 0U
942 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/)
944 /* DWT Comparator Function Register Definitions */
945 #define DWT_FUNCTION_MATCHED_Pos 24U
946 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
948 #define DWT_FUNCTION_DATAVADDR1_Pos 16U
949 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
951 #define DWT_FUNCTION_DATAVADDR0_Pos 12U
952 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
954 #define DWT_FUNCTION_DATAVSIZE_Pos 10U
955 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
957 #define DWT_FUNCTION_LNK1ENA_Pos 9U
958 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
960 #define DWT_FUNCTION_DATAVMATCH_Pos 8U
961 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
963 #define DWT_FUNCTION_CYCMATCH_Pos 7U
964 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
966 #define DWT_FUNCTION_EMITRANGE_Pos 5U
967 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
969 #define DWT_FUNCTION_FUNCTION_Pos 0U
970 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)
972  /* end of group CMSIS_DWT */
973 
974 
985 typedef struct
986 {
987  __IOM uint32_t SSPSR;
988  __IOM uint32_t CSPSR;
989  uint32_t RESERVED0[2U];
990  __IOM uint32_t ACPR;
991  uint32_t RESERVED1[55U];
992  __IOM uint32_t SPPR;
993  uint32_t RESERVED2[131U];
994  __IM uint32_t FFSR;
995  __IOM uint32_t FFCR;
996  __IM uint32_t FSCR;
997  uint32_t RESERVED3[759U];
998  __IM uint32_t TRIGGER;
999  __IM uint32_t FIFO0;
1000  __IM uint32_t ITATBCTR2;
1001  uint32_t RESERVED4[1U];
1002  __IM uint32_t ITATBCTR0;
1003  __IM uint32_t FIFO1;
1004  __IOM uint32_t ITCTRL;
1005  uint32_t RESERVED5[39U];
1006  __IOM uint32_t CLAIMSET;
1007  __IOM uint32_t CLAIMCLR;
1008  uint32_t RESERVED7[8U];
1009  __IM uint32_t DEVID;
1010  __IM uint32_t DEVTYPE;
1011 } TPI_Type;
1012 
1013 /* TPI Asynchronous Clock Prescaler Register Definitions */
1014 #define TPI_ACPR_PRESCALER_Pos 0U
1015 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
1017 /* TPI Selected Pin Protocol Register Definitions */
1018 #define TPI_SPPR_TXMODE_Pos 0U
1019 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
1021 /* TPI Formatter and Flush Status Register Definitions */
1022 #define TPI_FFSR_FtNonStop_Pos 3U
1023 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
1025 #define TPI_FFSR_TCPresent_Pos 2U
1026 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
1028 #define TPI_FFSR_FtStopped_Pos 1U
1029 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
1031 #define TPI_FFSR_FlInProg_Pos 0U
1032 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
1034 /* TPI Formatter and Flush Control Register Definitions */
1035 #define TPI_FFCR_TrigIn_Pos 8U
1036 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
1038 #define TPI_FFCR_EnFCont_Pos 1U
1039 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
1041 /* TPI TRIGGER Register Definitions */
1042 #define TPI_TRIGGER_TRIGGER_Pos 0U
1043 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
1045 /* TPI Integration ETM Data Register Definitions (FIFO0) */
1046 #define TPI_FIFO0_ITM_ATVALID_Pos 29U
1047 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
1049 #define TPI_FIFO0_ITM_bytecount_Pos 27U
1050 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
1052 #define TPI_FIFO0_ETM_ATVALID_Pos 26U
1053 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
1055 #define TPI_FIFO0_ETM_bytecount_Pos 24U
1056 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
1058 #define TPI_FIFO0_ETM2_Pos 16U
1059 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
1061 #define TPI_FIFO0_ETM1_Pos 8U
1062 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
1064 #define TPI_FIFO0_ETM0_Pos 0U
1065 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)
1067 /* TPI ITATBCTR2 Register Definitions */
1068 #define TPI_ITATBCTR2_ATREADY_Pos 0U
1069 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)
1071 /* TPI Integration ITM Data Register Definitions (FIFO1) */
1072 #define TPI_FIFO1_ITM_ATVALID_Pos 29U
1073 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
1075 #define TPI_FIFO1_ITM_bytecount_Pos 27U
1076 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
1078 #define TPI_FIFO1_ETM_ATVALID_Pos 26U
1079 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
1081 #define TPI_FIFO1_ETM_bytecount_Pos 24U
1082 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
1084 #define TPI_FIFO1_ITM2_Pos 16U
1085 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
1087 #define TPI_FIFO1_ITM1_Pos 8U
1088 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
1090 #define TPI_FIFO1_ITM0_Pos 0U
1091 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)
1093 /* TPI ITATBCTR0 Register Definitions */
1094 #define TPI_ITATBCTR0_ATREADY_Pos 0U
1095 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)
1097 /* TPI Integration Mode Control Register Definitions */
1098 #define TPI_ITCTRL_Mode_Pos 0U
1099 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)
1101 /* TPI DEVID Register Definitions */
1102 #define TPI_DEVID_NRZVALID_Pos 11U
1103 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
1105 #define TPI_DEVID_MANCVALID_Pos 10U
1106 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
1108 #define TPI_DEVID_PTINVALID_Pos 9U
1109 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
1111 #define TPI_DEVID_MinBufSz_Pos 6U
1112 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
1114 #define TPI_DEVID_AsynClkIn_Pos 5U
1115 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
1117 #define TPI_DEVID_NrTraceInput_Pos 0U
1118 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
1120 /* TPI DEVTYPE Register Definitions */
1121 #define TPI_DEVTYPE_MajorType_Pos 4U
1122 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
1124 #define TPI_DEVTYPE_SubType_Pos 0U
1125 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
1127  /* end of group CMSIS_TPI */
1128 
1129 
1130 #if (__MPU_PRESENT == 1U)
1131 
1141 typedef struct
1142 {
1143  __IM uint32_t TYPE;
1144  __IOM uint32_t CTRL;
1145  __IOM uint32_t RNR;
1146  __IOM uint32_t RBAR;
1147  __IOM uint32_t RASR;
1148  __IOM uint32_t RBAR_A1;
1149  __IOM uint32_t RASR_A1;
1150  __IOM uint32_t RBAR_A2;
1151  __IOM uint32_t RASR_A2;
1152  __IOM uint32_t RBAR_A3;
1153  __IOM uint32_t RASR_A3;
1154 } MPU_Type;
1155 
1156 /* MPU Type Register Definitions */
1157 #define MPU_TYPE_IREGION_Pos 16U
1158 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
1160 #define MPU_TYPE_DREGION_Pos 8U
1161 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
1163 #define MPU_TYPE_SEPARATE_Pos 0U
1164 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
1166 /* MPU Control Register Definitions */
1167 #define MPU_CTRL_PRIVDEFENA_Pos 2U
1168 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
1170 #define MPU_CTRL_HFNMIENA_Pos 1U
1171 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
1173 #define MPU_CTRL_ENABLE_Pos 0U
1174 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
1176 /* MPU Region Number Register Definitions */
1177 #define MPU_RNR_REGION_Pos 0U
1178 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
1180 /* MPU Region Base Address Register Definitions */
1181 #define MPU_RBAR_ADDR_Pos 5U
1182 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
1184 #define MPU_RBAR_VALID_Pos 4U
1185 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
1187 #define MPU_RBAR_REGION_Pos 0U
1188 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
1190 /* MPU Region Attribute and Size Register Definitions */
1191 #define MPU_RASR_ATTRS_Pos 16U
1192 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
1194 #define MPU_RASR_XN_Pos 28U
1195 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
1197 #define MPU_RASR_AP_Pos 24U
1198 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
1200 #define MPU_RASR_TEX_Pos 19U
1201 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
1203 #define MPU_RASR_S_Pos 18U
1204 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
1206 #define MPU_RASR_C_Pos 17U
1207 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
1209 #define MPU_RASR_B_Pos 16U
1210 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
1212 #define MPU_RASR_SRD_Pos 8U
1213 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
1215 #define MPU_RASR_SIZE_Pos 1U
1216 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
1218 #define MPU_RASR_ENABLE_Pos 0U
1219 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/)
1221 
1222 #endif
1223 
1224 
1235 typedef struct
1236 {
1237  __IOM uint32_t DHCSR;
1238  __OM uint32_t DCRSR;
1239  __IOM uint32_t DCRDR;
1240  __IOM uint32_t DEMCR;
1241 } CoreDebug_Type;
1242 
1243 /* Debug Halting Control and Status Register Definitions */
1244 #define CoreDebug_DHCSR_DBGKEY_Pos 16U
1245 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1247 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U
1248 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1250 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
1251 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1253 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U
1254 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1256 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U
1257 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1259 #define CoreDebug_DHCSR_S_HALT_Pos 17U
1260 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1262 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U
1263 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1265 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
1266 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
1268 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U
1269 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1271 #define CoreDebug_DHCSR_C_STEP_Pos 2U
1272 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1274 #define CoreDebug_DHCSR_C_HALT_Pos 1U
1275 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1277 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
1278 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
1280 /* Debug Core Register Selector Register Definitions */
1281 #define CoreDebug_DCRSR_REGWnR_Pos 16U
1282 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1284 #define CoreDebug_DCRSR_REGSEL_Pos 0U
1285 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
1287 /* Debug Exception and Monitor Control Register Definitions */
1288 #define CoreDebug_DEMCR_TRCENA_Pos 24U
1289 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
1291 #define CoreDebug_DEMCR_MON_REQ_Pos 19U
1292 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
1294 #define CoreDebug_DEMCR_MON_STEP_Pos 18U
1295 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
1297 #define CoreDebug_DEMCR_MON_PEND_Pos 17U
1298 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
1300 #define CoreDebug_DEMCR_MON_EN_Pos 16U
1301 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
1303 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U
1304 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1306 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U
1307 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
1309 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U
1310 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
1312 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U
1313 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
1315 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U
1316 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
1318 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
1319 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
1321 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U
1322 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
1324 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U
1325 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
1327 
1343 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
1344 
1351 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
1352 
1363 /* Memory mapping of Cortex-M3 Hardware */
1364 #define SCS_BASE (0xE000E000UL)
1365 #define ITM_BASE (0xE0000000UL)
1366 #define DWT_BASE (0xE0001000UL)
1367 #define TPI_BASE (0xE0040000UL)
1368 #define CoreDebug_BASE (0xE000EDF0UL)
1369 #define SysTick_BASE (SCS_BASE + 0x0010UL)
1370 #define NVIC_BASE (SCS_BASE + 0x0100UL)
1371 #define SCB_BASE (SCS_BASE + 0x0D00UL)
1373 #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
1374 #define SCB ((SCB_Type *) SCB_BASE )
1375 #define SysTick ((SysTick_Type *) SysTick_BASE )
1376 #define NVIC ((NVIC_Type *) NVIC_BASE )
1377 #define ITM ((ITM_Type *) ITM_BASE )
1378 #define DWT ((DWT_Type *) DWT_BASE )
1379 #define TPI ((TPI_Type *) TPI_BASE )
1380 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)
1382 #if (__MPU_PRESENT == 1U)
1383  #define MPU_BASE (SCS_BASE + 0x0D90UL)
1384  #define MPU ((MPU_Type *) MPU_BASE )
1385 #endif
1386 
1391 /*******************************************************************************
1392  * Hardware Abstraction Layer
1393  Core Function Interface contains:
1394  - Core NVIC Functions
1395  - Core SysTick Functions
1396  - Core Debug Functions
1397  - Core Register Access Functions
1398  ******************************************************************************/
1405 /* ########################## NVIC functions #################################### */
1422 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1423 {
1424  uint32_t reg_value;
1425  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1426 
1427  reg_value = SCB->AIRCR; /* read old register configuration */
1428  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
1429  reg_value = (reg_value |
1430  ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1431  (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
1432  SCB->AIRCR = reg_value;
1433 }
1434 
1435 
1441 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1442 {
1443  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1444 }
1445 
1446 
1452 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1453 {
1454  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1455 }
1456 
1457 
1463 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1464 {
1465  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1466 }
1467 
1468 
1476 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1477 {
1478  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1479 }
1480 
1481 
1487 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1488 {
1489  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1490 }
1491 
1492 
1498 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1499 {
1500  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1501 }
1502 
1503 
1511 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1512 {
1513  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1514 }
1515 
1516 
1524 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1525 {
1526  if ((int32_t)(IRQn) < 0)
1527  {
1528  SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1529  }
1530  else
1531  {
1532  NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1533  }
1534 }
1535 
1536 
1546 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1547 {
1548 
1549  if ((int32_t)(IRQn) < 0)
1550  {
1551  return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
1552  }
1553  else
1554  {
1555  return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
1556  }
1557 }
1558 
1559 
1571 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1572 {
1573  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1574  uint32_t PreemptPriorityBits;
1575  uint32_t SubPriorityBits;
1576 
1577  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1578  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1579 
1580  return (
1581  ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1582  ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1583  );
1584 }
1585 
1586 
1598 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
1599 {
1600  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1601  uint32_t PreemptPriorityBits;
1602  uint32_t SubPriorityBits;
1603 
1604  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1605  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1606 
1607  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1608  *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1609 }
1610 
1611 
1616 __STATIC_INLINE void NVIC_SystemReset(void)
1617 {
1618  __DSB(); /* Ensure all outstanding memory accesses included
1619  buffered write are completed before reset */
1620  SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1621  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1622  SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
1623  __DSB(); /* Ensure completion of memory access */
1624 
1625  for(;;) /* wait until reset */
1626  {
1627  __NOP();
1628  }
1629 }
1630 
1635 /* ################################## SysTick function ############################################ */
1643 #if (__Vendor_SysTickConfig == 0U)
1644 
1656 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1657 {
1658  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
1659  {
1660  return (1UL); /* Reload value impossible */
1661  }
1662 
1663  SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1664  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1665  SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
1666  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1667  SysTick_CTRL_TICKINT_Msk |
1668  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1669  return (0UL); /* Function successful */
1670 }
1671 
1672 #endif
1673 
1678 /* ##################################### Debug In/Output function ########################################### */
1686 extern volatile int32_t ITM_RxBuffer;
1687 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5U
1698 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
1699 {
1700  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
1701  ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
1702  {
1703  while (ITM->PORT[0U].u32 == 0UL)
1704  {
1705  __NOP();
1706  }
1707  ITM->PORT[0U].u8 = (uint8_t)ch;
1708  }
1709  return (ch);
1710 }
1711 
1712 
1719 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
1720 {
1721  int32_t ch = -1; /* no character available */
1722 
1723  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
1724  {
1725  ch = ITM_RxBuffer;
1726  ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1727  }
1728 
1729  return (ch);
1730 }
1731 
1732 
1739 __STATIC_INLINE int32_t ITM_CheckChar (void)
1740 {
1741 
1742  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
1743  {
1744  return (0); /* no character available */
1745  }
1746  else
1747  {
1748  return (1); /* character available */
1749  }
1750 }
1751 
1757 #ifdef __cplusplus
1758 }
1759 #endif
1760 
1761 #endif /* __CORE_CM3_H_DEPENDANT */
1762 
1763 #endif /* __CMSIS_GENERIC */
CoreDebug_Type::DCRDR
__IOM uint32_t DCRDR
Definition: core_cm3.h:1239
CoreDebug_Type::DCRSR
__OM uint32_t DCRSR
Definition: core_cm3.h:1238
ITM_Type::PID4
__IM uint32_t PID4
Definition: core_cm3.h:757
ITM
#define ITM
Definition: core_cm3.h:1377
core_cmFunc.h
CMSIS Cortex-M Core Function Access Header File.
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: core_cm3.h:838
SCB_Type::ADR
__IM uint32_t ADR
Definition: core_cm3.h:435
__NOP
#define __NOP
No Operation.
Definition: cmsis_armcc.h:313
SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
Definition: core_cm3.h:512
DWT_Type::FUNCTION3
__IOM uint32_t FUNCTION3
Definition: core_cm3.h:862
ITM_Type::LAR
__OM uint32_t LAR
Definition: core_cm3.h:754
NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_cm0.h:653
NVIC_SetPendingIRQ
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_cm0.h:664
ITM_Type::TER
__IOM uint32_t TER
Definition: core_cm3.h:744
TPI_Type::ITCTRL
__IOM uint32_t ITCTRL
Definition: core_cm3.h:1004
ITM_Type::CID1
__IM uint32_t CID1
Definition: core_cm3.h:766
NVIC_Type::STIR
__OM uint32_t STIR
Definition: core_cm3.h:397
TPI_Type::FFSR
__IM uint32_t FFSR
Definition: core_cm3.h:994
ITM_Type::PID1
__IM uint32_t PID1
Definition: core_cm3.h:762
ITM_Type::PID7
__IM uint32_t PID7
Definition: core_cm3.h:760
TPI_Type::FIFO0
__IM uint32_t FIFO0
Definition: core_cm3.h:999
TPI_Type::ITATBCTR0
__IM uint32_t ITATBCTR0
Definition: core_cm3.h:1002
NVIC_GetPriorityGrouping
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
Definition: core_cm3.h:1441
SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
Definition: core_cm3.h:503
ch
return ch
Definition: lcd_log.c:311
SysTick
#define SysTick
Definition: core_cm3.h:1375
DWT_Type::CYCCNT
__IOM uint32_t CYCCNT
Definition: core_cm3.h:841
ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Definition: core_cm3.h:1687
DWT_Type::CTRL
__IOM uint32_t CTRL
Definition: core_cm3.h:840
TPI_Type::CSPSR
__IOM uint32_t CSPSR
Definition: core_cm3.h:988
DWT_Type::MASK3
__IOM uint32_t MASK3
Definition: core_cm3.h:861
SCnSCB_Type::ICTR
__IM uint32_t ICTR
Definition: core_cm3.h:647
ITM_Type::TPR
__IOM uint32_t TPR
Definition: core_cm3.h:746
ITM_Type::PID0
__IM uint32_t PID0
Definition: core_cm3.h:761
CoreDebug_Type::DEMCR
__IOM uint32_t DEMCR
Definition: core_cm3.h:1240
ITM_RxBuffer
volatile int32_t ITM_RxBuffer
ITM_ReceiveChar
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition: core_cm3.h:1719
TPI_Type::CLAIMSET
__IOM uint32_t CLAIMSET
Definition: core_cm3.h:1006
ITM_Type::IRR
__IM uint32_t IRR
Definition: core_cm3.h:751
TPI_Type::SSPSR
__IOM uint32_t SSPSR
Definition: core_cm3.h:987
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_cm0.h:277
ITM_Type::CID3
__IM uint32_t CID3
Definition: core_cm3.h:768
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition: core_cm3.h:985
ITM_Type::PID3
__IM uint32_t PID3
Definition: core_cm3.h:764
DWT_Type::SLEEPCNT
__IOM uint32_t SLEEPCNT
Definition: core_cm3.h:844
ITM_CheckChar
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition: core_cm3.h:1739
DWT_Type::MASK1
__IOM uint32_t MASK1
Definition: core_cm3.h:853
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: core_cm3.h:1598
__IOM
#define __IOM
Definition: core_cm3.h:223
ITM_Type::IWR
__OM uint32_t IWR
Definition: core_cm3.h:750
__DSB
#define __DSB()
Data Synchronization Barrier.
Definition: cmsis_armcc.h:355
NVIC
#define NVIC
Definition: core_cm3.h:1376
SCB_Type::CFSR
__IOM uint32_t CFSR
Definition: core_cm3.h:427
DWT_Type::COMP2
__IOM uint32_t COMP2
Definition: core_cm3.h:856
TPI_Type::TRIGGER
__IM uint32_t TRIGGER
Definition: core_cm3.h:998
SCB_Type::AFSR
__IOM uint32_t AFSR
Definition: core_cm3.h:432
NVIC_EnableIRQ
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable External Interrupt.
Definition: core_cm0.h:629
DWT_Type::LSUCNT
__IOM uint32_t LSUCNT
Definition: core_cm3.h:845
SysTick_IRQn
Definition: stm32f745xx.h:77
CoreDebug_Type
Structure type to access the Core Debug Register (CoreDebug).
Definition: core_cm3.h:1235
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: core_cm0.h:389
ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
Definition: core_cm3.h:801
__IM
#define __IM
Definition: core_cm3.h:221
SCB
#define SCB
Definition: core_cm3.h:1374
ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition: core_cm3.h:735
__OM
#define __OM
Definition: core_cm3.h:222
IRQn_Type
IRQn_Type
STM32F7xx Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f745xx.h:67
ITM_Type::u16
__OM uint16_t u16
Definition: core_cm3.h:740
NVIC_SetPriorityGrouping
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
Definition: core_cm3.h:1422
SysTick_Config
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
System Tick Configuration.
Definition: core_cm0.h:769
DWT_Type::MASK0
__IOM uint32_t MASK0
Definition: core_cm3.h:849
NVIC_GetPriority
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_cm0.h:712
TPI_Type::ITATBCTR2
__IM uint32_t ITATBCTR2
Definition: core_cm3.h:1000
SCB_Type::DFR
__IM uint32_t DFR
Definition: core_cm3.h:434
ITM_Type::LSR
__IM uint32_t LSR
Definition: core_cm3.h:755
DWT_Type::FOLDCNT
__IOM uint32_t FOLDCNT
Definition: core_cm3.h:846
DWT_Type::COMP0
__IOM uint32_t COMP0
Definition: core_cm3.h:848
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: stm32f745xx.h:185
SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
Definition: core_cm3.h:511
DWT_Type::FUNCTION0
__IOM uint32_t FUNCTION0
Definition: core_cm3.h:850
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition: core_cm3.h:644
NVIC_SetPriority
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_cm0.h:688
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_cm0.h:362
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: core_cm0.h:496
SCB_Type::VTOR
__IOM uint32_t VTOR
Definition: core_cm3.h:421
ITM_Type::IMCR
__IOM uint32_t IMCR
Definition: core_cm3.h:752
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_cm3.h:502
ITM_Type::CID2
__IM uint32_t CID2
Definition: core_cm3.h:767
TPI_Type::ACPR
__IOM uint32_t ACPR
Definition: core_cm3.h:990
ITM_Type::CID0
__IM uint32_t CID0
Definition: core_cm3.h:765
NVIC_SystemReset
__STATIC_INLINE void NVIC_SystemReset(void)
System Reset.
Definition: core_cm0.h:730
DWT_Type::FUNCTION2
__IOM uint32_t FUNCTION2
Definition: core_cm3.h:858
DWT_Type::PCSR
__IM uint32_t PCSR
Definition: core_cm3.h:847
SCB_Type::HFSR
__IOM uint32_t HFSR
Definition: core_cm3.h:428
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_cm3.h:515
ITM_Type::TCR
__IOM uint32_t TCR
Definition: core_cm3.h:748
ITM_Type::u32
__OM uint32_t u32
Definition: core_cm3.h:741
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: core_cm0.h:247
SCB_Type::DFSR
__IOM uint32_t DFSR
Definition: core_cm3.h:429
DWT_Type::MASK2
__IOM uint32_t MASK2
Definition: core_cm3.h:857
NVIC_DisableIRQ
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Disable External Interrupt.
Definition: core_cm0.h:640
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_cm3.h:706
DWT_Type::COMP1
__IOM uint32_t COMP1
Definition: core_cm3.h:852
SCB_Type::CPACR
__IOM uint32_t CPACR
Definition: core_cm3.h:439
SCB_Type::MMFAR
__IOM uint32_t MMFAR
Definition: core_cm3.h:430
TPI_Type::FSCR
__IM uint32_t FSCR
Definition: core_cm3.h:996
SCB_Type::BFAR
__IOM uint32_t BFAR
Definition: core_cm3.h:431
ITM_Type::PID6
__IM uint32_t PID6
Definition: core_cm3.h:759
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: core_cm0.h:334
ITM_Type::PID2
__IM uint32_t PID2
Definition: core_cm3.h:763
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_cm3.h:696
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_cm3.h:702
DWT_Type::FUNCTION1
__IOM uint32_t FUNCTION1
Definition: core_cm3.h:854
ITM_Type::PID5
__IM uint32_t PID5
Definition: core_cm3.h:758
NVIC_ClearPendingIRQ
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_cm0.h:675
ITM_Type::u8
__OM uint8_t u8
Definition: core_cm3.h:739
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: core_cm3.h:1571
TPI_Type::SPPR
__IOM uint32_t SPPR
Definition: core_cm3.h:992
core_cmInstr.h
CMSIS Cortex-M Core Instruction Access Header File.
DWT_Type::CPICNT
__IOM uint32_t CPICNT
Definition: core_cm3.h:842
TPI_Type::CLAIMCLR
__IOM uint32_t CLAIMCLR
Definition: core_cm3.h:1007
NVIC_GetActive
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: core_cm3.h:1511
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_cm0.h:295
TPI_Type::FIFO1
__IM uint32_t FIFO1
Definition: core_cm3.h:1003
TPI_Type::FFCR
__IOM uint32_t FFCR
Definition: core_cm3.h:995
DWT_Type::COMP3
__IOM uint32_t COMP3
Definition: core_cm3.h:860
DWT_Type::EXCCNT
__IOM uint32_t EXCCNT
Definition: core_cm3.h:843
TPI_Type::DEVTYPE
__IM uint32_t DEVTYPE
Definition: core_cm3.h:1010
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_cm3.h:699
TPI_Type::DEVID
__IM uint32_t DEVID
Definition: core_cm3.h:1009
CoreDebug_Type::DHCSR
__IOM uint32_t DHCSR
Definition: core_cm3.h:1237
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