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STM32F769IDiscovery
1.00
uDANTE Audio Networking with STM32F7 DISCO board
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STM32F769IDiscovery
1.00
uDANTE Audio Networking with STM32F7 DISCO board
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Structure type to access the Instrumentation Trace Macrocell Register (ITM). More...
#include <core_cm3.h>
Data Fields | |
| union { | |
| __OM uint8_t u8 | |
| __OM uint16_t u16 | |
| __OM uint32_t u32 | |
| } | PORT [32U] |
| uint32_t | RESERVED0 [864U] |
| __IOM uint32_t | TER |
| uint32_t | RESERVED1 [15U] |
| __IOM uint32_t | TPR |
| uint32_t | RESERVED2 [15U] |
| __IOM uint32_t | TCR |
| uint32_t | RESERVED3 [29U] |
| __OM uint32_t | IWR |
| __IM uint32_t | IRR |
| __IOM uint32_t | IMCR |
| uint32_t | RESERVED4 [43U] |
| __OM uint32_t | LAR |
| __IM uint32_t | LSR |
| uint32_t | RESERVED5 [6U] |
| __IM uint32_t | PID4 |
| __IM uint32_t | PID5 |
| __IM uint32_t | PID6 |
| __IM uint32_t | PID7 |
| __IM uint32_t | PID0 |
| __IM uint32_t | PID1 |
| __IM uint32_t | PID2 |
| __IM uint32_t | PID3 |
| __IM uint32_t | CID0 |
| __IM uint32_t | CID1 |
| __IM uint32_t | CID2 |
| __IM uint32_t | CID3 |
| union { | |
| __OM uint8_t u8 | |
| __OM uint16_t u16 | |
| __OM uint32_t u32 | |
| } | PORT [32U] |
| union { | |
| __OM uint8_t u8 | |
| __OM uint16_t u16 | |
| __OM uint32_t u32 | |
| } | PORT [32U] |
| union { | |
| __OM uint8_t u8 | |
| __OM uint16_t u16 | |
| __OM uint32_t u32 | |
| } | PORT [32U] |
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition at line 735 of file core_cm3.h.
| __IM uint32_t CID0 |
Offset: 0xFF0 (R/ ) ITM Component Identification Register #0
Definition at line 765 of file core_cm3.h.
| __IM uint32_t CID1 |
Offset: 0xFF4 (R/ ) ITM Component Identification Register #1
Definition at line 766 of file core_cm3.h.
| __IM uint32_t CID2 |
Offset: 0xFF8 (R/ ) ITM Component Identification Register #2
Definition at line 767 of file core_cm3.h.
| __IM uint32_t CID3 |
Offset: 0xFFC (R/ ) ITM Component Identification Register #3
Definition at line 768 of file core_cm3.h.
| __IOM uint32_t IMCR |
Offset: 0xF00 (R/W) ITM Integration Mode Control Register
Definition at line 752 of file core_cm3.h.
| __IM uint32_t IRR |
Offset: 0xEFC (R/ ) ITM Integration Read Register
Definition at line 751 of file core_cm3.h.
| __OM uint32_t IWR |
Offset: 0xEF8 ( /W) ITM Integration Write Register
Definition at line 750 of file core_cm3.h.
| __OM uint32_t LAR |
Offset: 0xFB0 ( /W) ITM Lock Access Register
Definition at line 754 of file core_cm3.h.
| __IM uint32_t LSR |
Offset: 0xFB4 (R/ ) ITM Lock Status Register
Definition at line 755 of file core_cm3.h.
| __IM uint32_t PID0 |
Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0
Definition at line 761 of file core_cm3.h.
| __IM uint32_t PID1 |
Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1
Definition at line 762 of file core_cm3.h.
| __IM uint32_t PID2 |
Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2
Definition at line 763 of file core_cm3.h.
| __IM uint32_t PID3 |
Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3
Definition at line 764 of file core_cm3.h.
| __IM uint32_t PID4 |
Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4
Definition at line 757 of file core_cm3.h.
| __IM uint32_t PID5 |
Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5
Definition at line 758 of file core_cm3.h.
| __IM uint32_t PID6 |
Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6
Definition at line 759 of file core_cm3.h.
| __IM uint32_t PID7 |
Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7
Definition at line 760 of file core_cm3.h.
| __OM { ... } PORT[32U] |
Offset: 0x000 ( /W) ITM Stimulus Port Registers
| __OM { ... } PORT[32U] |
Offset: 0x000 ( /W) ITM Stimulus Port Registers
| __OM { ... } PORT[32U] |
Offset: 0x000 ( /W) ITM Stimulus Port Registers
| __OM { ... } PORT[32U] |
Offset: 0x000 ( /W) ITM Stimulus Port Registers
| uint32_t RESERVED0 |
Definition at line 743 of file core_cm3.h.
| uint32_t RESERVED1 |
Definition at line 745 of file core_cm3.h.
| uint32_t RESERVED2 |
Definition at line 747 of file core_cm3.h.
| uint32_t RESERVED3 |
Definition at line 749 of file core_cm3.h.
| uint32_t RESERVED4 |
Definition at line 753 of file core_cm3.h.
| uint32_t RESERVED5 |
Definition at line 756 of file core_cm3.h.
| __IOM uint32_t TCR |
Offset: 0xE80 (R/W) ITM Trace Control Register
Definition at line 748 of file core_cm3.h.
| __IOM uint32_t TER |
Offset: 0xE00 (R/W) ITM Trace Enable Register
Definition at line 744 of file core_cm3.h.
| __IOM uint32_t TPR |
Offset: 0xE40 (R/W) ITM Trace Privilege Register
Definition at line 746 of file core_cm3.h.
| __OM uint16_t u16 |
Offset: 0x000 ( /W) ITM Stimulus Port 16-bit
Definition at line 740 of file core_cm3.h.
| __OM uint32_t u32 |
Offset: 0x000 ( /W) ITM Stimulus Port 32-bit
Definition at line 741 of file core_cm3.h.
| __OM uint8_t u8 |
Offset: 0x000 ( /W) ITM Stimulus Port 8-bit
Definition at line 739 of file core_cm3.h.
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