STM32F769IDiscovery  1.00
uDANTE Audio Networking with STM32F7 DISCO board
core_sc300.h
Go to the documentation of this file.
1 /**************************************************************************/
7 /* Copyright (c) 2009 - 2015 ARM LIMITED
8 
9  All rights reserved.
10  Redistribution and use in source and binary forms, with or without
11  modification, are permitted provided that the following conditions are met:
12  - Redistributions of source code must retain the above copyright
13  notice, this list of conditions and the following disclaimer.
14  - Redistributions in binary form must reproduce the above copyright
15  notice, this list of conditions and the following disclaimer in the
16  documentation and/or other materials provided with the distribution.
17  - Neither the name of ARM nor the names of its contributors may be used
18  to endorse or promote products derived from this software without
19  specific prior written permission.
20  *
21  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
25  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  POSSIBILITY OF SUCH DAMAGE.
32  ---------------------------------------------------------------------------*/
33 
34 
35 #if defined ( __ICCARM__ )
36  #pragma system_include /* treat file as system include file for MISRA check */
37 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
38  #pragma clang system_header /* treat file as system include file */
39 #endif
40 
41 #ifndef __CORE_SC300_H_GENERIC
42 #define __CORE_SC300_H_GENERIC
43 
44 #include <stdint.h>
45 
46 #ifdef __cplusplus
47  extern "C" {
48 #endif
49 
65 /*******************************************************************************
66  * CMSIS definitions
67  ******************************************************************************/
73 /* CMSIS SC300 definitions */
74 #define __SC300_CMSIS_VERSION_MAIN (0x04U)
75 #define __SC300_CMSIS_VERSION_SUB (0x1EU)
76 #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
77  __SC300_CMSIS_VERSION_SUB )
79 #define __CORTEX_SC (300U)
82 #if defined ( __CC_ARM )
83  #define __ASM __asm
84  #define __INLINE __inline
85  #define __STATIC_INLINE static __inline
86 
87 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
88  #define __ASM __asm
89  #define __INLINE __inline
90  #define __STATIC_INLINE static __inline
91 
92 #elif defined ( __GNUC__ )
93  #define __ASM __asm
94  #define __INLINE inline
95  #define __STATIC_INLINE static inline
96 
97 #elif defined ( __ICCARM__ )
98  #define __ASM __asm
99  #define __INLINE inline
100  #define __STATIC_INLINE static inline
101 
102 #elif defined ( __TMS470__ )
103  #define __ASM __asm
104  #define __STATIC_INLINE static inline
105 
106 #elif defined ( __TASKING__ )
107  #define __ASM __asm
108  #define __INLINE inline
109  #define __STATIC_INLINE static inline
110 
111 #elif defined ( __CSMC__ )
112  #define __packed
113  #define __ASM _asm
114  #define __INLINE inline
115  #define __STATIC_INLINE static inline
116 
117 #else
118  #error Unknown compiler
119 #endif
120 
124 #define __FPU_USED 0U
125 
126 #if defined ( __CC_ARM )
127  #if defined __TARGET_FPU_VFP
128  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
129  #endif
130 
131 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
132  #if defined __ARM_PCS_VFP
133  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
134  #endif
135 
136 #elif defined ( __GNUC__ )
137  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
138  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
139  #endif
140 
141 #elif defined ( __ICCARM__ )
142  #if defined __ARMVFP__
143  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
144  #endif
145 
146 #elif defined ( __TMS470__ )
147  #if defined __TI_VFP_SUPPORT__
148  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
149  #endif
150 
151 #elif defined ( __TASKING__ )
152  #if defined __FPU_VFP__
153  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
154  #endif
155 
156 #elif defined ( __CSMC__ )
157  #if ( __CSMC__ & 0x400U)
158  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
159  #endif
160 
161 #endif
162 
163 #include "core_cmInstr.h" /* Core Instruction Access */
164 #include "core_cmFunc.h" /* Core Function Access */
165 
166 #ifdef __cplusplus
167 }
168 #endif
169 
170 #endif /* __CORE_SC300_H_GENERIC */
171 
172 #ifndef __CMSIS_GENERIC
173 
174 #ifndef __CORE_SC300_H_DEPENDANT
175 #define __CORE_SC300_H_DEPENDANT
176 
177 #ifdef __cplusplus
178  extern "C" {
179 #endif
180 
181 /* check device defines and use defaults */
182 #if defined __CHECK_DEVICE_DEFINES
183  #ifndef __SC300_REV
184  #define __SC300_REV 0x0000U
185  #warning "__SC300_REV not defined in device header file; using default!"
186  #endif
187 
188  #ifndef __MPU_PRESENT
189  #define __MPU_PRESENT 0U
190  #warning "__MPU_PRESENT not defined in device header file; using default!"
191  #endif
192 
193  #ifndef __NVIC_PRIO_BITS
194  #define __NVIC_PRIO_BITS 4U
195  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
196  #endif
197 
198  #ifndef __Vendor_SysTickConfig
199  #define __Vendor_SysTickConfig 0U
200  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
201  #endif
202 #endif
203 
204 /* IO definitions (access restrictions to peripheral registers) */
212 #ifdef __cplusplus
213  #define __I volatile
214 #else
215  #define __I volatile const
216 #endif
217 #define __O volatile
218 #define __IO volatile
220 /* following defines should be used for structure members */
221 #define __IM volatile const
222 #define __OM volatile
223 #define __IOM volatile
225 
229 /*******************************************************************************
230  * Register Abstraction
231  Core Register contain:
232  - Core Register
233  - Core NVIC Register
234  - Core SCB Register
235  - Core SysTick Register
236  - Core Debug Register
237  - Core MPU Register
238  ******************************************************************************/
239 
254 typedef union
255 {
256  struct
257  {
258  uint32_t _reserved0:27;
259  uint32_t Q:1;
260  uint32_t V:1;
261  uint32_t C:1;
262  uint32_t Z:1;
263  uint32_t N:1;
264  } b;
265  uint32_t w;
266 } APSR_Type;
267 
268 /* APSR Register Definitions */
269 #define APSR_N_Pos 31U
270 #define APSR_N_Msk (1UL << APSR_N_Pos)
272 #define APSR_Z_Pos 30U
273 #define APSR_Z_Msk (1UL << APSR_Z_Pos)
275 #define APSR_C_Pos 29U
276 #define APSR_C_Msk (1UL << APSR_C_Pos)
278 #define APSR_V_Pos 28U
279 #define APSR_V_Msk (1UL << APSR_V_Pos)
281 #define APSR_Q_Pos 27U
282 #define APSR_Q_Msk (1UL << APSR_Q_Pos)
288 typedef union
289 {
290  struct
291  {
292  uint32_t ISR:9;
293  uint32_t _reserved0:23;
294  } b;
295  uint32_t w;
296 } IPSR_Type;
297 
298 /* IPSR Register Definitions */
299 #define IPSR_ISR_Pos 0U
300 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
306 typedef union
307 {
308  struct
309  {
310  uint32_t ISR:9;
311  uint32_t _reserved0:15;
312  uint32_t T:1;
313  uint32_t IT:2;
314  uint32_t Q:1;
315  uint32_t V:1;
316  uint32_t C:1;
317  uint32_t Z:1;
318  uint32_t N:1;
319  } b;
320  uint32_t w;
321 } xPSR_Type;
322 
323 /* xPSR Register Definitions */
324 #define xPSR_N_Pos 31U
325 #define xPSR_N_Msk (1UL << xPSR_N_Pos)
327 #define xPSR_Z_Pos 30U
328 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
330 #define xPSR_C_Pos 29U
331 #define xPSR_C_Msk (1UL << xPSR_C_Pos)
333 #define xPSR_V_Pos 28U
334 #define xPSR_V_Msk (1UL << xPSR_V_Pos)
336 #define xPSR_Q_Pos 27U
337 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos)
339 #define xPSR_IT_Pos 25U
340 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos)
342 #define xPSR_T_Pos 24U
343 #define xPSR_T_Msk (1UL << xPSR_T_Pos)
345 #define xPSR_ISR_Pos 0U
346 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
352 typedef union
353 {
354  struct
355  {
356  uint32_t nPRIV:1;
357  uint32_t SPSEL:1;
358  uint32_t _reserved1:30;
359  } b;
360  uint32_t w;
361 } CONTROL_Type;
362 
363 /* CONTROL Register Definitions */
364 #define CONTROL_SPSEL_Pos 1U
365 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
367 #define CONTROL_nPRIV_Pos 0U
368 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)
370 
383 typedef struct
384 {
385  __IOM uint32_t ISER[8U];
386  uint32_t RESERVED0[24U];
387  __IOM uint32_t ICER[8U];
388  uint32_t RSERVED1[24U];
389  __IOM uint32_t ISPR[8U];
390  uint32_t RESERVED2[24U];
391  __IOM uint32_t ICPR[8U];
392  uint32_t RESERVED3[24U];
393  __IOM uint32_t IABR[8U];
394  uint32_t RESERVED4[56U];
395  __IOM uint8_t IP[240U];
396  uint32_t RESERVED5[644U];
397  __OM uint32_t STIR;
398 } NVIC_Type;
399 
400 /* Software Triggered Interrupt Register Definitions */
401 #define NVIC_STIR_INTID_Pos 0U
402 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
404 
417 typedef struct
418 {
419  __IM uint32_t CPUID;
420  __IOM uint32_t ICSR;
421  __IOM uint32_t VTOR;
422  __IOM uint32_t AIRCR;
423  __IOM uint32_t SCR;
424  __IOM uint32_t CCR;
425  __IOM uint8_t SHP[12U];
426  __IOM uint32_t SHCSR;
427  __IOM uint32_t CFSR;
428  __IOM uint32_t HFSR;
429  __IOM uint32_t DFSR;
430  __IOM uint32_t MMFAR;
431  __IOM uint32_t BFAR;
432  __IOM uint32_t AFSR;
433  __IM uint32_t PFR[2U];
434  __IM uint32_t DFR;
435  __IM uint32_t ADR;
436  __IM uint32_t MMFR[4U];
437  __IM uint32_t ISAR[5U];
438  uint32_t RESERVED0[5U];
439  __IOM uint32_t CPACR;
440  uint32_t RESERVED1[129U];
441  __IOM uint32_t SFCR;
442 } SCB_Type;
443 
444 /* SCB CPUID Register Definitions */
445 #define SCB_CPUID_IMPLEMENTER_Pos 24U
446 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
448 #define SCB_CPUID_VARIANT_Pos 20U
449 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
451 #define SCB_CPUID_ARCHITECTURE_Pos 16U
452 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
454 #define SCB_CPUID_PARTNO_Pos 4U
455 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
457 #define SCB_CPUID_REVISION_Pos 0U
458 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
460 /* SCB Interrupt Control State Register Definitions */
461 #define SCB_ICSR_NMIPENDSET_Pos 31U
462 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
464 #define SCB_ICSR_PENDSVSET_Pos 28U
465 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
467 #define SCB_ICSR_PENDSVCLR_Pos 27U
468 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
470 #define SCB_ICSR_PENDSTSET_Pos 26U
471 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
473 #define SCB_ICSR_PENDSTCLR_Pos 25U
474 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
476 #define SCB_ICSR_ISRPREEMPT_Pos 23U
477 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
479 #define SCB_ICSR_ISRPENDING_Pos 22U
480 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
482 #define SCB_ICSR_VECTPENDING_Pos 12U
483 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
485 #define SCB_ICSR_RETTOBASE_Pos 11U
486 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
488 #define SCB_ICSR_VECTACTIVE_Pos 0U
489 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
491 /* SCB Vector Table Offset Register Definitions */
492 #define SCB_VTOR_TBLBASE_Pos 29U
493 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos)
495 #define SCB_VTOR_TBLOFF_Pos 7U
496 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)
498 /* SCB Application Interrupt and Reset Control Register Definitions */
499 #define SCB_AIRCR_VECTKEY_Pos 16U
500 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
502 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U
503 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
505 #define SCB_AIRCR_ENDIANESS_Pos 15U
506 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
508 #define SCB_AIRCR_PRIGROUP_Pos 8U
509 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
511 #define SCB_AIRCR_SYSRESETREQ_Pos 2U
512 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
514 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
515 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
517 #define SCB_AIRCR_VECTRESET_Pos 0U
518 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
520 /* SCB System Control Register Definitions */
521 #define SCB_SCR_SEVONPEND_Pos 4U
522 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
524 #define SCB_SCR_SLEEPDEEP_Pos 2U
525 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
527 #define SCB_SCR_SLEEPONEXIT_Pos 1U
528 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
530 /* SCB Configuration Control Register Definitions */
531 #define SCB_CCR_STKALIGN_Pos 9U
532 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
534 #define SCB_CCR_BFHFNMIGN_Pos 8U
535 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
537 #define SCB_CCR_DIV_0_TRP_Pos 4U
538 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
540 #define SCB_CCR_UNALIGN_TRP_Pos 3U
541 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
543 #define SCB_CCR_USERSETMPEND_Pos 1U
544 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
546 #define SCB_CCR_NONBASETHRDENA_Pos 0U
547 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
549 /* SCB System Handler Control and State Register Definitions */
550 #define SCB_SHCSR_USGFAULTENA_Pos 18U
551 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
553 #define SCB_SHCSR_BUSFAULTENA_Pos 17U
554 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
556 #define SCB_SHCSR_MEMFAULTENA_Pos 16U
557 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
559 #define SCB_SHCSR_SVCALLPENDED_Pos 15U
560 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
562 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U
563 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
565 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U
566 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
568 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U
569 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
571 #define SCB_SHCSR_SYSTICKACT_Pos 11U
572 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
574 #define SCB_SHCSR_PENDSVACT_Pos 10U
575 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
577 #define SCB_SHCSR_MONITORACT_Pos 8U
578 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
580 #define SCB_SHCSR_SVCALLACT_Pos 7U
581 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
583 #define SCB_SHCSR_USGFAULTACT_Pos 3U
584 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
586 #define SCB_SHCSR_BUSFAULTACT_Pos 1U
587 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
589 #define SCB_SHCSR_MEMFAULTACT_Pos 0U
590 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
592 /* SCB Configurable Fault Status Register Definitions */
593 #define SCB_CFSR_USGFAULTSR_Pos 16U
594 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
596 #define SCB_CFSR_BUSFAULTSR_Pos 8U
597 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
599 #define SCB_CFSR_MEMFAULTSR_Pos 0U
600 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
602 /* SCB Hard Fault Status Register Definitions */
603 #define SCB_HFSR_DEBUGEVT_Pos 31U
604 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
606 #define SCB_HFSR_FORCED_Pos 30U
607 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
609 #define SCB_HFSR_VECTTBL_Pos 1U
610 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
612 /* SCB Debug Fault Status Register Definitions */
613 #define SCB_DFSR_EXTERNAL_Pos 4U
614 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
616 #define SCB_DFSR_VCATCH_Pos 3U
617 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
619 #define SCB_DFSR_DWTTRAP_Pos 2U
620 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
622 #define SCB_DFSR_BKPT_Pos 1U
623 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
625 #define SCB_DFSR_HALTED_Pos 0U
626 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)
628 
641 typedef struct
642 {
643  uint32_t RESERVED0[1U];
644  __IM uint32_t ICTR;
645  uint32_t RESERVED1[1U];
646 } SCnSCB_Type;
647 
648 /* Interrupt Controller Type Register Definitions */
649 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U
650 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
652 
665 typedef struct
666 {
667  __IOM uint32_t CTRL;
668  __IOM uint32_t LOAD;
669  __IOM uint32_t VAL;
670  __IM uint32_t CALIB;
671 } SysTick_Type;
672 
673 /* SysTick Control / Status Register Definitions */
674 #define SysTick_CTRL_COUNTFLAG_Pos 16U
675 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
677 #define SysTick_CTRL_CLKSOURCE_Pos 2U
678 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
680 #define SysTick_CTRL_TICKINT_Pos 1U
681 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
683 #define SysTick_CTRL_ENABLE_Pos 0U
684 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
686 /* SysTick Reload Register Definitions */
687 #define SysTick_LOAD_RELOAD_Pos 0U
688 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
690 /* SysTick Current Register Definitions */
691 #define SysTick_VAL_CURRENT_Pos 0U
692 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
694 /* SysTick Calibration Register Definitions */
695 #define SysTick_CALIB_NOREF_Pos 31U
696 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
698 #define SysTick_CALIB_SKEW_Pos 30U
699 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
701 #define SysTick_CALIB_TENMS_Pos 0U
702 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
704 
717 typedef struct
718 {
719  __OM union
720  {
721  __OM uint8_t u8;
722  __OM uint16_t u16;
723  __OM uint32_t u32;
724  } PORT [32U];
725  uint32_t RESERVED0[864U];
726  __IOM uint32_t TER;
727  uint32_t RESERVED1[15U];
728  __IOM uint32_t TPR;
729  uint32_t RESERVED2[15U];
730  __IOM uint32_t TCR;
731  uint32_t RESERVED3[29U];
732  __OM uint32_t IWR;
733  __IM uint32_t IRR;
734  __IOM uint32_t IMCR;
735  uint32_t RESERVED4[43U];
736  __OM uint32_t LAR;
737  __IM uint32_t LSR;
738  uint32_t RESERVED5[6U];
739  __IM uint32_t PID4;
740  __IM uint32_t PID5;
741  __IM uint32_t PID6;
742  __IM uint32_t PID7;
743  __IM uint32_t PID0;
744  __IM uint32_t PID1;
745  __IM uint32_t PID2;
746  __IM uint32_t PID3;
747  __IM uint32_t CID0;
748  __IM uint32_t CID1;
749  __IM uint32_t CID2;
750  __IM uint32_t CID3;
751 } ITM_Type;
752 
753 /* ITM Trace Privilege Register Definitions */
754 #define ITM_TPR_PRIVMASK_Pos 0U
755 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
757 /* ITM Trace Control Register Definitions */
758 #define ITM_TCR_BUSY_Pos 23U
759 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
761 #define ITM_TCR_TraceBusID_Pos 16U
762 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)
764 #define ITM_TCR_GTSFREQ_Pos 10U
765 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
767 #define ITM_TCR_TSPrescale_Pos 8U
768 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)
770 #define ITM_TCR_SWOENA_Pos 4U
771 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
773 #define ITM_TCR_DWTENA_Pos 3U
774 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
776 #define ITM_TCR_SYNCENA_Pos 2U
777 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
779 #define ITM_TCR_TSENA_Pos 1U
780 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
782 #define ITM_TCR_ITMENA_Pos 0U
783 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)
785 /* ITM Integration Write Register Definitions */
786 #define ITM_IWR_ATVALIDM_Pos 0U
787 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)
789 /* ITM Integration Read Register Definitions */
790 #define ITM_IRR_ATREADYM_Pos 0U
791 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)
793 /* ITM Integration Mode Control Register Definitions */
794 #define ITM_IMCR_INTEGRATION_Pos 0U
795 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)
797 /* ITM Lock Status Register Definitions */
798 #define ITM_LSR_ByteAcc_Pos 2U
799 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
801 #define ITM_LSR_Access_Pos 1U
802 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
804 #define ITM_LSR_Present_Pos 0U
805 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)
807  /* end of group CMSIS_ITM */
808 
809 
820 typedef struct
821 {
822  __IOM uint32_t CTRL;
823  __IOM uint32_t CYCCNT;
824  __IOM uint32_t CPICNT;
825  __IOM uint32_t EXCCNT;
826  __IOM uint32_t SLEEPCNT;
827  __IOM uint32_t LSUCNT;
828  __IOM uint32_t FOLDCNT;
829  __IM uint32_t PCSR;
830  __IOM uint32_t COMP0;
831  __IOM uint32_t MASK0;
832  __IOM uint32_t FUNCTION0;
833  uint32_t RESERVED0[1U];
834  __IOM uint32_t COMP1;
835  __IOM uint32_t MASK1;
836  __IOM uint32_t FUNCTION1;
837  uint32_t RESERVED1[1U];
838  __IOM uint32_t COMP2;
839  __IOM uint32_t MASK2;
840  __IOM uint32_t FUNCTION2;
841  uint32_t RESERVED2[1U];
842  __IOM uint32_t COMP3;
843  __IOM uint32_t MASK3;
844  __IOM uint32_t FUNCTION3;
845 } DWT_Type;
846 
847 /* DWT Control Register Definitions */
848 #define DWT_CTRL_NUMCOMP_Pos 28U
849 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
851 #define DWT_CTRL_NOTRCPKT_Pos 27U
852 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
854 #define DWT_CTRL_NOEXTTRIG_Pos 26U
855 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
857 #define DWT_CTRL_NOCYCCNT_Pos 25U
858 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
860 #define DWT_CTRL_NOPRFCNT_Pos 24U
861 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
863 #define DWT_CTRL_CYCEVTENA_Pos 22U
864 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
866 #define DWT_CTRL_FOLDEVTENA_Pos 21U
867 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
869 #define DWT_CTRL_LSUEVTENA_Pos 20U
870 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
872 #define DWT_CTRL_SLEEPEVTENA_Pos 19U
873 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
875 #define DWT_CTRL_EXCEVTENA_Pos 18U
876 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
878 #define DWT_CTRL_CPIEVTENA_Pos 17U
879 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
881 #define DWT_CTRL_EXCTRCENA_Pos 16U
882 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
884 #define DWT_CTRL_PCSAMPLENA_Pos 12U
885 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
887 #define DWT_CTRL_SYNCTAP_Pos 10U
888 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
890 #define DWT_CTRL_CYCTAP_Pos 9U
891 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
893 #define DWT_CTRL_POSTINIT_Pos 5U
894 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
896 #define DWT_CTRL_POSTPRESET_Pos 1U
897 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
899 #define DWT_CTRL_CYCCNTENA_Pos 0U
900 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
902 /* DWT CPI Count Register Definitions */
903 #define DWT_CPICNT_CPICNT_Pos 0U
904 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
906 /* DWT Exception Overhead Count Register Definitions */
907 #define DWT_EXCCNT_EXCCNT_Pos 0U
908 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
910 /* DWT Sleep Count Register Definitions */
911 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U
912 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
914 /* DWT LSU Count Register Definitions */
915 #define DWT_LSUCNT_LSUCNT_Pos 0U
916 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
918 /* DWT Folded-instruction Count Register Definitions */
919 #define DWT_FOLDCNT_FOLDCNT_Pos 0U
920 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
922 /* DWT Comparator Mask Register Definitions */
923 #define DWT_MASK_MASK_Pos 0U
924 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/)
926 /* DWT Comparator Function Register Definitions */
927 #define DWT_FUNCTION_MATCHED_Pos 24U
928 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
930 #define DWT_FUNCTION_DATAVADDR1_Pos 16U
931 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
933 #define DWT_FUNCTION_DATAVADDR0_Pos 12U
934 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
936 #define DWT_FUNCTION_DATAVSIZE_Pos 10U
937 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
939 #define DWT_FUNCTION_LNK1ENA_Pos 9U
940 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
942 #define DWT_FUNCTION_DATAVMATCH_Pos 8U
943 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
945 #define DWT_FUNCTION_CYCMATCH_Pos 7U
946 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
948 #define DWT_FUNCTION_EMITRANGE_Pos 5U
949 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
951 #define DWT_FUNCTION_FUNCTION_Pos 0U
952 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)
954  /* end of group CMSIS_DWT */
955 
956 
967 typedef struct
968 {
969  __IOM uint32_t SSPSR;
970  __IOM uint32_t CSPSR;
971  uint32_t RESERVED0[2U];
972  __IOM uint32_t ACPR;
973  uint32_t RESERVED1[55U];
974  __IOM uint32_t SPPR;
975  uint32_t RESERVED2[131U];
976  __IM uint32_t FFSR;
977  __IOM uint32_t FFCR;
978  __IM uint32_t FSCR;
979  uint32_t RESERVED3[759U];
980  __IM uint32_t TRIGGER;
981  __IM uint32_t FIFO0;
982  __IM uint32_t ITATBCTR2;
983  uint32_t RESERVED4[1U];
984  __IM uint32_t ITATBCTR0;
985  __IM uint32_t FIFO1;
986  __IOM uint32_t ITCTRL;
987  uint32_t RESERVED5[39U];
988  __IOM uint32_t CLAIMSET;
989  __IOM uint32_t CLAIMCLR;
990  uint32_t RESERVED7[8U];
991  __IM uint32_t DEVID;
992  __IM uint32_t DEVTYPE;
993 } TPI_Type;
994 
995 /* TPI Asynchronous Clock Prescaler Register Definitions */
996 #define TPI_ACPR_PRESCALER_Pos 0U
997 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
999 /* TPI Selected Pin Protocol Register Definitions */
1000 #define TPI_SPPR_TXMODE_Pos 0U
1001 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
1003 /* TPI Formatter and Flush Status Register Definitions */
1004 #define TPI_FFSR_FtNonStop_Pos 3U
1005 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
1007 #define TPI_FFSR_TCPresent_Pos 2U
1008 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
1010 #define TPI_FFSR_FtStopped_Pos 1U
1011 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
1013 #define TPI_FFSR_FlInProg_Pos 0U
1014 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
1016 /* TPI Formatter and Flush Control Register Definitions */
1017 #define TPI_FFCR_TrigIn_Pos 8U
1018 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
1020 #define TPI_FFCR_EnFCont_Pos 1U
1021 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
1023 /* TPI TRIGGER Register Definitions */
1024 #define TPI_TRIGGER_TRIGGER_Pos 0U
1025 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
1027 /* TPI Integration ETM Data Register Definitions (FIFO0) */
1028 #define TPI_FIFO0_ITM_ATVALID_Pos 29U
1029 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
1031 #define TPI_FIFO0_ITM_bytecount_Pos 27U
1032 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
1034 #define TPI_FIFO0_ETM_ATVALID_Pos 26U
1035 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
1037 #define TPI_FIFO0_ETM_bytecount_Pos 24U
1038 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
1040 #define TPI_FIFO0_ETM2_Pos 16U
1041 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
1043 #define TPI_FIFO0_ETM1_Pos 8U
1044 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
1046 #define TPI_FIFO0_ETM0_Pos 0U
1047 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)
1049 /* TPI ITATBCTR2 Register Definitions */
1050 #define TPI_ITATBCTR2_ATREADY_Pos 0U
1051 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)
1053 /* TPI Integration ITM Data Register Definitions (FIFO1) */
1054 #define TPI_FIFO1_ITM_ATVALID_Pos 29U
1055 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
1057 #define TPI_FIFO1_ITM_bytecount_Pos 27U
1058 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
1060 #define TPI_FIFO1_ETM_ATVALID_Pos 26U
1061 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
1063 #define TPI_FIFO1_ETM_bytecount_Pos 24U
1064 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
1066 #define TPI_FIFO1_ITM2_Pos 16U
1067 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
1069 #define TPI_FIFO1_ITM1_Pos 8U
1070 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
1072 #define TPI_FIFO1_ITM0_Pos 0U
1073 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)
1075 /* TPI ITATBCTR0 Register Definitions */
1076 #define TPI_ITATBCTR0_ATREADY_Pos 0U
1077 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)
1079 /* TPI Integration Mode Control Register Definitions */
1080 #define TPI_ITCTRL_Mode_Pos 0U
1081 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)
1083 /* TPI DEVID Register Definitions */
1084 #define TPI_DEVID_NRZVALID_Pos 11U
1085 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
1087 #define TPI_DEVID_MANCVALID_Pos 10U
1088 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
1090 #define TPI_DEVID_PTINVALID_Pos 9U
1091 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
1093 #define TPI_DEVID_MinBufSz_Pos 6U
1094 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
1096 #define TPI_DEVID_AsynClkIn_Pos 5U
1097 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
1099 #define TPI_DEVID_NrTraceInput_Pos 0U
1100 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
1102 /* TPI DEVTYPE Register Definitions */
1103 #define TPI_DEVTYPE_MajorType_Pos 4U
1104 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
1106 #define TPI_DEVTYPE_SubType_Pos 0U
1107 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
1109  /* end of group CMSIS_TPI */
1110 
1111 
1112 #if (__MPU_PRESENT == 1U)
1113 
1123 typedef struct
1124 {
1125  __IM uint32_t TYPE;
1126  __IOM uint32_t CTRL;
1127  __IOM uint32_t RNR;
1128  __IOM uint32_t RBAR;
1129  __IOM uint32_t RASR;
1130  __IOM uint32_t RBAR_A1;
1131  __IOM uint32_t RASR_A1;
1132  __IOM uint32_t RBAR_A2;
1133  __IOM uint32_t RASR_A2;
1134  __IOM uint32_t RBAR_A3;
1135  __IOM uint32_t RASR_A3;
1136 } MPU_Type;
1137 
1138 /* MPU Type Register Definitions */
1139 #define MPU_TYPE_IREGION_Pos 16U
1140 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
1142 #define MPU_TYPE_DREGION_Pos 8U
1143 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
1145 #define MPU_TYPE_SEPARATE_Pos 0U
1146 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
1148 /* MPU Control Register Definitions */
1149 #define MPU_CTRL_PRIVDEFENA_Pos 2U
1150 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
1152 #define MPU_CTRL_HFNMIENA_Pos 1U
1153 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
1155 #define MPU_CTRL_ENABLE_Pos 0U
1156 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
1158 /* MPU Region Number Register Definitions */
1159 #define MPU_RNR_REGION_Pos 0U
1160 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
1162 /* MPU Region Base Address Register Definitions */
1163 #define MPU_RBAR_ADDR_Pos 5U
1164 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
1166 #define MPU_RBAR_VALID_Pos 4U
1167 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
1169 #define MPU_RBAR_REGION_Pos 0U
1170 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
1172 /* MPU Region Attribute and Size Register Definitions */
1173 #define MPU_RASR_ATTRS_Pos 16U
1174 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
1176 #define MPU_RASR_XN_Pos 28U
1177 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
1179 #define MPU_RASR_AP_Pos 24U
1180 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
1182 #define MPU_RASR_TEX_Pos 19U
1183 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
1185 #define MPU_RASR_S_Pos 18U
1186 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
1188 #define MPU_RASR_C_Pos 17U
1189 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
1191 #define MPU_RASR_B_Pos 16U
1192 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
1194 #define MPU_RASR_SRD_Pos 8U
1195 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
1197 #define MPU_RASR_SIZE_Pos 1U
1198 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
1200 #define MPU_RASR_ENABLE_Pos 0U
1201 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/)
1203 
1204 #endif
1205 
1206 
1217 typedef struct
1218 {
1219  __IOM uint32_t DHCSR;
1220  __OM uint32_t DCRSR;
1221  __IOM uint32_t DCRDR;
1222  __IOM uint32_t DEMCR;
1223 } CoreDebug_Type;
1224 
1225 /* Debug Halting Control and Status Register Definitions */
1226 #define CoreDebug_DHCSR_DBGKEY_Pos 16U
1227 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1229 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U
1230 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1232 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
1233 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1235 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U
1236 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1238 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U
1239 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1241 #define CoreDebug_DHCSR_S_HALT_Pos 17U
1242 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1244 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U
1245 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1247 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
1248 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
1250 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U
1251 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1253 #define CoreDebug_DHCSR_C_STEP_Pos 2U
1254 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1256 #define CoreDebug_DHCSR_C_HALT_Pos 1U
1257 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1259 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
1260 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
1262 /* Debug Core Register Selector Register Definitions */
1263 #define CoreDebug_DCRSR_REGWnR_Pos 16U
1264 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1266 #define CoreDebug_DCRSR_REGSEL_Pos 0U
1267 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
1269 /* Debug Exception and Monitor Control Register Definitions */
1270 #define CoreDebug_DEMCR_TRCENA_Pos 24U
1271 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
1273 #define CoreDebug_DEMCR_MON_REQ_Pos 19U
1274 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
1276 #define CoreDebug_DEMCR_MON_STEP_Pos 18U
1277 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
1279 #define CoreDebug_DEMCR_MON_PEND_Pos 17U
1280 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
1282 #define CoreDebug_DEMCR_MON_EN_Pos 16U
1283 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
1285 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U
1286 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1288 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U
1289 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
1291 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U
1292 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
1294 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U
1295 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
1297 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U
1298 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
1300 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
1301 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
1303 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U
1304 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
1306 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U
1307 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
1309 
1325 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
1326 
1333 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
1334 
1345 /* Memory mapping of Cortex-M3 Hardware */
1346 #define SCS_BASE (0xE000E000UL)
1347 #define ITM_BASE (0xE0000000UL)
1348 #define DWT_BASE (0xE0001000UL)
1349 #define TPI_BASE (0xE0040000UL)
1350 #define CoreDebug_BASE (0xE000EDF0UL)
1351 #define SysTick_BASE (SCS_BASE + 0x0010UL)
1352 #define NVIC_BASE (SCS_BASE + 0x0100UL)
1353 #define SCB_BASE (SCS_BASE + 0x0D00UL)
1355 #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
1356 #define SCB ((SCB_Type *) SCB_BASE )
1357 #define SysTick ((SysTick_Type *) SysTick_BASE )
1358 #define NVIC ((NVIC_Type *) NVIC_BASE )
1359 #define ITM ((ITM_Type *) ITM_BASE )
1360 #define DWT ((DWT_Type *) DWT_BASE )
1361 #define TPI ((TPI_Type *) TPI_BASE )
1362 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)
1364 #if (__MPU_PRESENT == 1U)
1365  #define MPU_BASE (SCS_BASE + 0x0D90UL)
1366  #define MPU ((MPU_Type *) MPU_BASE )
1367 #endif
1368 
1373 /*******************************************************************************
1374  * Hardware Abstraction Layer
1375  Core Function Interface contains:
1376  - Core NVIC Functions
1377  - Core SysTick Functions
1378  - Core Debug Functions
1379  - Core Register Access Functions
1380  ******************************************************************************/
1387 /* ########################## NVIC functions #################################### */
1404 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1405 {
1406  uint32_t reg_value;
1407  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1408 
1409  reg_value = SCB->AIRCR; /* read old register configuration */
1410  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
1411  reg_value = (reg_value |
1412  ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1413  (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
1414  SCB->AIRCR = reg_value;
1415 }
1416 
1417 
1423 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1424 {
1425  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1426 }
1427 
1428 
1434 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1435 {
1436  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1437 }
1438 
1439 
1445 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1446 {
1447  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1448 }
1449 
1450 
1458 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1459 {
1460  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1461 }
1462 
1463 
1469 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1470 {
1471  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1472 }
1473 
1474 
1480 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1481 {
1482  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1483 }
1484 
1485 
1493 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1494 {
1495  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1496 }
1497 
1498 
1506 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1507 {
1508  if ((int32_t)(IRQn) < 0)
1509  {
1510  SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1511  }
1512  else
1513  {
1514  NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1515  }
1516 }
1517 
1518 
1528 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1529 {
1530 
1531  if ((int32_t)(IRQn) < 0)
1532  {
1533  return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
1534  }
1535  else
1536  {
1537  return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
1538  }
1539 }
1540 
1541 
1553 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1554 {
1555  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1556  uint32_t PreemptPriorityBits;
1557  uint32_t SubPriorityBits;
1558 
1559  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1560  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1561 
1562  return (
1563  ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1564  ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1565  );
1566 }
1567 
1568 
1580 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
1581 {
1582  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1583  uint32_t PreemptPriorityBits;
1584  uint32_t SubPriorityBits;
1585 
1586  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1587  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1588 
1589  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1590  *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1591 }
1592 
1593 
1598 __STATIC_INLINE void NVIC_SystemReset(void)
1599 {
1600  __DSB(); /* Ensure all outstanding memory accesses included
1601  buffered write are completed before reset */
1602  SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1603  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1604  SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
1605  __DSB(); /* Ensure completion of memory access */
1606 
1607  for(;;) /* wait until reset */
1608  {
1609  __NOP();
1610  }
1611 }
1612 
1617 /* ################################## SysTick function ############################################ */
1625 #if (__Vendor_SysTickConfig == 0U)
1626 
1638 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1639 {
1640  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
1641  {
1642  return (1UL); /* Reload value impossible */
1643  }
1644 
1645  SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1646  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1647  SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
1648  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1649  SysTick_CTRL_TICKINT_Msk |
1650  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1651  return (0UL); /* Function successful */
1652 }
1653 
1654 #endif
1655 
1660 /* ##################################### Debug In/Output function ########################################### */
1668 extern volatile int32_t ITM_RxBuffer;
1669 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5U
1680 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
1681 {
1682  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
1683  ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
1684  {
1685  while (ITM->PORT[0U].u32 == 0UL)
1686  {
1687  __NOP();
1688  }
1689  ITM->PORT[0U].u8 = (uint8_t)ch;
1690  }
1691  return (ch);
1692 }
1693 
1694 
1701 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
1702 {
1703  int32_t ch = -1; /* no character available */
1704 
1705  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
1706  {
1707  ch = ITM_RxBuffer;
1708  ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1709  }
1710 
1711  return (ch);
1712 }
1713 
1714 
1721 __STATIC_INLINE int32_t ITM_CheckChar (void)
1722 {
1723 
1724  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
1725  {
1726  return (0); /* no character available */
1727  }
1728  else
1729  {
1730  return (1); /* character available */
1731  }
1732 }
1733 
1739 #ifdef __cplusplus
1740 }
1741 #endif
1742 
1743 #endif /* __CORE_SC300_H_DEPENDANT */
1744 
1745 #endif /* __CMSIS_GENERIC */
ITM
#define ITM
Definition: core_sc300.h:1359
core_cmFunc.h
CMSIS Cortex-M Core Function Access Header File.
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: core_cm3.h:838
__NOP
#define __NOP
No Operation.
Definition: cmsis_armcc.h:313
SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
Definition: core_sc300.h:509
NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_cm0.h:653
NVIC_SetPendingIRQ
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_cm0.h:664
NVIC_GetPriorityGrouping
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
Definition: core_cm3.h:1441
SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
Definition: core_sc300.h:500
ch
return ch
Definition: lcd_log.c:311
SysTick
#define SysTick
Definition: core_sc300.h:1357
ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Definition: core_sc300.h:1669
ITM_RxBuffer
volatile int32_t ITM_RxBuffer
ITM_ReceiveChar
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition: core_cm3.h:1719
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_cm0.h:277
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition: core_cm3.h:985
__IOM
#define __IOM
Definition: core_sc300.h:223
ITM_CheckChar
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition: core_cm3.h:1739
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: core_cm3.h:1598
__DSB
#define __DSB()
Data Synchronization Barrier.
Definition: cmsis_armcc.h:355
NVIC
#define NVIC
Definition: core_sc300.h:1358
NVIC_EnableIRQ
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable External Interrupt.
Definition: core_cm0.h:629
SysTick_IRQn
Definition: stm32f745xx.h:77
CoreDebug_Type
Structure type to access the Core Debug Register (CoreDebug).
Definition: core_cm3.h:1235
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: core_cm0.h:389
ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
Definition: core_sc300.h:783
SCB
#define SCB
Definition: core_sc300.h:1356
ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition: core_cm3.h:735
IRQn_Type
IRQn_Type
STM32F7xx Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f745xx.h:67
NVIC_SetPriorityGrouping
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
Definition: core_cm3.h:1422
SysTick_Config
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
System Tick Configuration.
Definition: core_cm0.h:769
NVIC_GetPriority
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_cm0.h:712
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: stm32f745xx.h:185
SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
Definition: core_sc300.h:508
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition: core_cm3.h:644
NVIC_SetPriority
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_cm0.h:688
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_cm0.h:362
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: core_cm0.h:496
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_sc300.h:499
NVIC_SystemReset
__STATIC_INLINE void NVIC_SystemReset(void)
System Reset.
Definition: core_cm0.h:730
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_sc300.h:512
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: core_cm0.h:247
NVIC_DisableIRQ
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Disable External Interrupt.
Definition: core_cm0.h:640
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_sc300.h:688
__IM
#define __IM
Definition: core_sc300.h:221
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: core_cm0.h:334
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_sc300.h:678
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_sc300.h:684
__OM
#define __OM
Definition: core_sc300.h:222
NVIC_ClearPendingIRQ
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_cm0.h:675
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: core_cm3.h:1571
core_cmInstr.h
CMSIS Cortex-M Core Instruction Access Header File.
NVIC_GetActive
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: core_cm3.h:1511
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_cm0.h:295
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_sc300.h:681
Generated by   doxygen 1.8.11