STM32F769IDiscovery  1.00
uDANTE Audio Networking with STM32F7 DISCO board
stm32f745xx.h
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1 
52 #ifndef __STM32F745xx_H
53 #define __STM32F745xx_H
54 
55 #ifdef __cplusplus
56  extern "C" {
57 #endif /* __cplusplus */
58 
67 typedef enum
68 {
69 /****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/
70  NonMaskableInt_IRQn = -14,
71  MemoryManagement_IRQn = -12,
72  BusFault_IRQn = -11,
73  UsageFault_IRQn = -10,
74  SVCall_IRQn = -5,
75  DebugMonitor_IRQn = -4,
76  PendSV_IRQn = -2,
77  SysTick_IRQn = -1,
78 /****** STM32 specific Interrupt Numbers **********************************************************************/
79  WWDG_IRQn = 0,
80  PVD_IRQn = 1,
81  TAMP_STAMP_IRQn = 2,
82  RTC_WKUP_IRQn = 3,
83  FLASH_IRQn = 4,
84  RCC_IRQn = 5,
85  EXTI0_IRQn = 6,
86  EXTI1_IRQn = 7,
87  EXTI2_IRQn = 8,
88  EXTI3_IRQn = 9,
89  EXTI4_IRQn = 10,
90  DMA1_Stream0_IRQn = 11,
91  DMA1_Stream1_IRQn = 12,
92  DMA1_Stream2_IRQn = 13,
93  DMA1_Stream3_IRQn = 14,
94  DMA1_Stream4_IRQn = 15,
95  DMA1_Stream5_IRQn = 16,
96  DMA1_Stream6_IRQn = 17,
97  ADC_IRQn = 18,
98  CAN1_TX_IRQn = 19,
99  CAN1_RX0_IRQn = 20,
100  CAN1_RX1_IRQn = 21,
101  CAN1_SCE_IRQn = 22,
102  EXTI9_5_IRQn = 23,
103  TIM1_BRK_TIM9_IRQn = 24,
104  TIM1_UP_TIM10_IRQn = 25,
105  TIM1_TRG_COM_TIM11_IRQn = 26,
106  TIM1_CC_IRQn = 27,
107  TIM2_IRQn = 28,
108  TIM3_IRQn = 29,
109  TIM4_IRQn = 30,
110  I2C1_EV_IRQn = 31,
111  I2C1_ER_IRQn = 32,
112  I2C2_EV_IRQn = 33,
113  I2C2_ER_IRQn = 34,
114  SPI1_IRQn = 35,
115  SPI2_IRQn = 36,
116  USART1_IRQn = 37,
117  USART2_IRQn = 38,
118  USART3_IRQn = 39,
119  EXTI15_10_IRQn = 40,
120  RTC_Alarm_IRQn = 41,
121  OTG_FS_WKUP_IRQn = 42,
122  TIM8_BRK_TIM12_IRQn = 43,
123  TIM8_UP_TIM13_IRQn = 44,
124  TIM8_TRG_COM_TIM14_IRQn = 45,
125  TIM8_CC_IRQn = 46,
126  DMA1_Stream7_IRQn = 47,
127  FMC_IRQn = 48,
128  SDMMC1_IRQn = 49,
129  TIM5_IRQn = 50,
130  SPI3_IRQn = 51,
131  UART4_IRQn = 52,
132  UART5_IRQn = 53,
133  TIM6_DAC_IRQn = 54,
134  TIM7_IRQn = 55,
135  DMA2_Stream0_IRQn = 56,
136  DMA2_Stream1_IRQn = 57,
137  DMA2_Stream2_IRQn = 58,
138  DMA2_Stream3_IRQn = 59,
139  DMA2_Stream4_IRQn = 60,
140  ETH_IRQn = 61,
141  ETH_WKUP_IRQn = 62,
142  CAN2_TX_IRQn = 63,
143  CAN2_RX0_IRQn = 64,
144  CAN2_RX1_IRQn = 65,
145  CAN2_SCE_IRQn = 66,
146  OTG_FS_IRQn = 67,
147  DMA2_Stream5_IRQn = 68,
148  DMA2_Stream6_IRQn = 69,
149  DMA2_Stream7_IRQn = 70,
150  USART6_IRQn = 71,
151  I2C3_EV_IRQn = 72,
152  I2C3_ER_IRQn = 73,
153  OTG_HS_EP1_OUT_IRQn = 74,
154  OTG_HS_EP1_IN_IRQn = 75,
155  OTG_HS_WKUP_IRQn = 76,
156  OTG_HS_IRQn = 77,
157  DCMI_IRQn = 78,
158  RNG_IRQn = 80,
159  FPU_IRQn = 81,
160  UART7_IRQn = 82,
161  UART8_IRQn = 83,
162  SPI4_IRQn = 84,
163  SPI5_IRQn = 85,
164  SPI6_IRQn = 86,
165  SAI1_IRQn = 87,
166  DMA2D_IRQn = 90,
167  SAI2_IRQn = 91,
168  QUADSPI_IRQn = 92,
169  LPTIM1_IRQn = 93,
170  CEC_IRQn = 94,
171  I2C4_EV_IRQn = 95,
172  I2C4_ER_IRQn = 96,
173  SPDIF_RX_IRQn = 97,
174 } IRQn_Type;
175 
183 #define __CM7_REV 0x0001U
184 #define __MPU_PRESENT 1
185 #define __NVIC_PRIO_BITS 4
186 #define __Vendor_SysTickConfig 0
187 #define __FPU_PRESENT 1
188 #define __ICACHE_PRESENT 1
189 #define __DCACHE_PRESENT 1
190 #include "core_cm7.h"
193 #include "system_stm32f7xx.h"
194 #include <stdint.h>
195 
204 typedef struct
205 {
206  __IO uint32_t SR;
207  __IO uint32_t CR1;
208  __IO uint32_t CR2;
209  __IO uint32_t SMPR1;
210  __IO uint32_t SMPR2;
211  __IO uint32_t JOFR1;
212  __IO uint32_t JOFR2;
213  __IO uint32_t JOFR3;
214  __IO uint32_t JOFR4;
215  __IO uint32_t HTR;
216  __IO uint32_t LTR;
217  __IO uint32_t SQR1;
218  __IO uint32_t SQR2;
219  __IO uint32_t SQR3;
220  __IO uint32_t JSQR;
221  __IO uint32_t JDR1;
222  __IO uint32_t JDR2;
223  __IO uint32_t JDR3;
224  __IO uint32_t JDR4;
225  __IO uint32_t DR;
226 } ADC_TypeDef;
227 
228 typedef struct
229 {
230  __IO uint32_t CSR;
231  __IO uint32_t CCR;
232  __IO uint32_t CDR;
234 } ADC_Common_TypeDef;
235 
236 
241 typedef struct
242 {
243  __IO uint32_t TIR;
244  __IO uint32_t TDTR;
245  __IO uint32_t TDLR;
246  __IO uint32_t TDHR;
247 } CAN_TxMailBox_TypeDef;
248 
253 typedef struct
254 {
255  __IO uint32_t RIR;
256  __IO uint32_t RDTR;
257  __IO uint32_t RDLR;
258  __IO uint32_t RDHR;
259 } CAN_FIFOMailBox_TypeDef;
260 
265 typedef struct
266 {
267  __IO uint32_t FR1;
268  __IO uint32_t FR2;
269 } CAN_FilterRegister_TypeDef;
270 
275 typedef struct
276 {
277  __IO uint32_t MCR;
278  __IO uint32_t MSR;
279  __IO uint32_t TSR;
280  __IO uint32_t RF0R;
281  __IO uint32_t RF1R;
282  __IO uint32_t IER;
283  __IO uint32_t ESR;
284  __IO uint32_t BTR;
285  uint32_t RESERVED0[88];
286  CAN_TxMailBox_TypeDef sTxMailBox[3];
287  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
288  uint32_t RESERVED1[12];
289  __IO uint32_t FMR;
290  __IO uint32_t FM1R;
291  uint32_t RESERVED2;
292  __IO uint32_t FS1R;
293  uint32_t RESERVED3;
294  __IO uint32_t FFA1R;
295  uint32_t RESERVED4;
296  __IO uint32_t FA1R;
297  uint32_t RESERVED5[8];
298  CAN_FilterRegister_TypeDef sFilterRegister[28];
299 } CAN_TypeDef;
300 
305 typedef struct
306 {
307  __IO uint32_t CR;
308  __IO uint32_t CFGR;
309  __IO uint32_t TXDR;
310  __IO uint32_t RXDR;
311  __IO uint32_t ISR;
312  __IO uint32_t IER;
313 }CEC_TypeDef;
314 
315 
320 typedef struct
321 {
322  __IO uint32_t DR;
323  __IO uint8_t IDR;
324  uint8_t RESERVED0;
325  uint16_t RESERVED1;
326  __IO uint32_t CR;
327  uint32_t RESERVED2;
328  __IO uint32_t INIT;
329  __IO uint32_t POL;
330 } CRC_TypeDef;
331 
336 typedef struct
337 {
338  __IO uint32_t CR;
339  __IO uint32_t SWTRIGR;
340  __IO uint32_t DHR12R1;
341  __IO uint32_t DHR12L1;
342  __IO uint32_t DHR8R1;
343  __IO uint32_t DHR12R2;
344  __IO uint32_t DHR12L2;
345  __IO uint32_t DHR8R2;
346  __IO uint32_t DHR12RD;
347  __IO uint32_t DHR12LD;
348  __IO uint32_t DHR8RD;
349  __IO uint32_t DOR1;
350  __IO uint32_t DOR2;
351  __IO uint32_t SR;
352 } DAC_TypeDef;
353 
354 
359 typedef struct
360 {
361  __IO uint32_t IDCODE;
362  __IO uint32_t CR;
363  __IO uint32_t APB1FZ;
364  __IO uint32_t APB2FZ;
365 }DBGMCU_TypeDef;
366 
371 typedef struct
372 {
373  __IO uint32_t CR;
374  __IO uint32_t SR;
375  __IO uint32_t RISR;
376  __IO uint32_t IER;
377  __IO uint32_t MISR;
378  __IO uint32_t ICR;
379  __IO uint32_t ESCR;
380  __IO uint32_t ESUR;
381  __IO uint32_t CWSTRTR;
382  __IO uint32_t CWSIZER;
383  __IO uint32_t DR;
384 } DCMI_TypeDef;
385 
390 typedef struct
391 {
392  __IO uint32_t CR;
393  __IO uint32_t NDTR;
394  __IO uint32_t PAR;
395  __IO uint32_t M0AR;
396  __IO uint32_t M1AR;
397  __IO uint32_t FCR;
398 } DMA_Stream_TypeDef;
399 
400 typedef struct
401 {
402  __IO uint32_t LISR;
403  __IO uint32_t HISR;
404  __IO uint32_t LIFCR;
405  __IO uint32_t HIFCR;
406 } DMA_TypeDef;
407 
408 
413 typedef struct
414 {
415  __IO uint32_t CR;
416  __IO uint32_t ISR;
417  __IO uint32_t IFCR;
418  __IO uint32_t FGMAR;
419  __IO uint32_t FGOR;
420  __IO uint32_t BGMAR;
421  __IO uint32_t BGOR;
422  __IO uint32_t FGPFCCR;
423  __IO uint32_t FGCOLR;
424  __IO uint32_t BGPFCCR;
425  __IO uint32_t BGCOLR;
426  __IO uint32_t FGCMAR;
427  __IO uint32_t BGCMAR;
428  __IO uint32_t OPFCCR;
429  __IO uint32_t OCOLR;
430  __IO uint32_t OMAR;
431  __IO uint32_t OOR;
432  __IO uint32_t NLR;
433  __IO uint32_t LWR;
434  __IO uint32_t AMTCR;
435  uint32_t RESERVED[236];
436  __IO uint32_t FGCLUT[256];
437  __IO uint32_t BGCLUT[256];
438 } DMA2D_TypeDef;
439 
440 
445 typedef struct
446 {
447  __IO uint32_t MACCR;
448  __IO uint32_t MACFFR;
449  __IO uint32_t MACHTHR;
450  __IO uint32_t MACHTLR;
451  __IO uint32_t MACMIIAR;
452  __IO uint32_t MACMIIDR;
453  __IO uint32_t MACFCR;
454  __IO uint32_t MACVLANTR; /* 8 */
455  uint32_t RESERVED0[2];
456  __IO uint32_t MACRWUFFR; /* 11 */
457  __IO uint32_t MACPMTCSR;
458  uint32_t RESERVED1[2];
459  __IO uint32_t MACSR; /* 15 */
460  __IO uint32_t MACIMR;
461  __IO uint32_t MACA0HR;
462  __IO uint32_t MACA0LR;
463  __IO uint32_t MACA1HR;
464  __IO uint32_t MACA1LR;
465  __IO uint32_t MACA2HR;
466  __IO uint32_t MACA2LR;
467  __IO uint32_t MACA3HR;
468  __IO uint32_t MACA3LR; /* 24 */
469  uint32_t RESERVED2[40];
470  __IO uint32_t MMCCR; /* 65 */
471  __IO uint32_t MMCRIR;
472  __IO uint32_t MMCTIR;
473  __IO uint32_t MMCRIMR;
474  __IO uint32_t MMCTIMR; /* 69 */
475  uint32_t RESERVED3[14];
476  __IO uint32_t MMCTGFSCCR; /* 84 */
477  __IO uint32_t MMCTGFMSCCR;
478  uint32_t RESERVED4[5];
479  __IO uint32_t MMCTGFCR;
480  uint32_t RESERVED5[10];
481  __IO uint32_t MMCRFCECR;
482  __IO uint32_t MMCRFAECR;
483  uint32_t RESERVED6[10];
484  __IO uint32_t MMCRGUFCR;
485  uint32_t RESERVED7[334];
486  __IO uint32_t PTPTSCR;
487  __IO uint32_t PTPSSIR;
488  __IO uint32_t PTPTSHR;
489  __IO uint32_t PTPTSLR;
490  __IO uint32_t PTPTSHUR;
491  __IO uint32_t PTPTSLUR;
492  __IO uint32_t PTPTSAR;
493  __IO uint32_t PTPTTHR;
494  __IO uint32_t PTPTTLR;
495  __IO uint32_t RESERVED8;
496  __IO uint32_t PTPTSSR;
497  uint32_t RESERVED9[565];
498  __IO uint32_t DMABMR;
499  __IO uint32_t DMATPDR;
500  __IO uint32_t DMARPDR;
501  __IO uint32_t DMARDLAR;
502  __IO uint32_t DMATDLAR;
503  __IO uint32_t DMASR;
504  __IO uint32_t DMAOMR;
505  __IO uint32_t DMAIER;
506  __IO uint32_t DMAMFBOCR;
507  __IO uint32_t DMARSWTR;
508  uint32_t RESERVED10[8];
509  __IO uint32_t DMACHTDR;
510  __IO uint32_t DMACHRDR;
511  __IO uint32_t DMACHTBAR;
512  __IO uint32_t DMACHRBAR;
513 } ETH_TypeDef;
514 
519 typedef struct
520 {
521  __IO uint32_t IMR;
522  __IO uint32_t EMR;
523  __IO uint32_t RTSR;
524  __IO uint32_t FTSR;
525  __IO uint32_t SWIER;
526  __IO uint32_t PR;
527 } EXTI_TypeDef;
528 
533 typedef struct
534 {
535  __IO uint32_t ACR;
536  __IO uint32_t KEYR;
537  __IO uint32_t OPTKEYR;
538  __IO uint32_t SR;
539  __IO uint32_t CR;
540  __IO uint32_t OPTCR;
541  __IO uint32_t OPTCR1;
542 } FLASH_TypeDef;
543 
544 
545 
550 typedef struct
551 {
552  __IO uint32_t BTCR[8];
553 } FMC_Bank1_TypeDef;
554 
559 typedef struct
560 {
561  __IO uint32_t BWTR[7];
562 } FMC_Bank1E_TypeDef;
563 
568 typedef struct
569 {
570  __IO uint32_t PCR;
571  __IO uint32_t SR;
572  __IO uint32_t PMEM;
573  __IO uint32_t PATT;
574  uint32_t RESERVED0;
575  __IO uint32_t ECCR;
576 } FMC_Bank3_TypeDef;
577 
582 typedef struct
583 {
584  __IO uint32_t SDCR[2];
585  __IO uint32_t SDTR[2];
586  __IO uint32_t SDCMR;
587  __IO uint32_t SDRTR;
588  __IO uint32_t SDSR;
589 } FMC_Bank5_6_TypeDef;
590 
591 
596 typedef struct
597 {
598  __IO uint32_t MODER;
599  __IO uint32_t OTYPER;
600  __IO uint32_t OSPEEDR;
601  __IO uint32_t PUPDR;
602  __IO uint32_t IDR;
603  __IO uint32_t ODR;
604  __IO uint32_t BSRR;
605  __IO uint32_t LCKR;
606  __IO uint32_t AFR[2];
607 } GPIO_TypeDef;
608 
613 typedef struct
614 {
615  __IO uint32_t MEMRMP;
616  __IO uint32_t PMC;
617  __IO uint32_t EXTICR[4];
618  uint32_t RESERVED[2];
619  __IO uint32_t CMPCR;
620 } SYSCFG_TypeDef;
621 
626 typedef struct
627 {
628  __IO uint32_t CR1;
629  __IO uint32_t CR2;
630  __IO uint32_t OAR1;
631  __IO uint32_t OAR2;
632  __IO uint32_t TIMINGR;
633  __IO uint32_t TIMEOUTR;
634  __IO uint32_t ISR;
635  __IO uint32_t ICR;
636  __IO uint32_t PECR;
637  __IO uint32_t RXDR;
638  __IO uint32_t TXDR;
639 } I2C_TypeDef;
640 
645 typedef struct
646 {
647  __IO uint32_t KR;
648  __IO uint32_t PR;
649  __IO uint32_t RLR;
650  __IO uint32_t SR;
651  __IO uint32_t WINR;
652 } IWDG_TypeDef;
653 
654 
655 
660 typedef struct
661 {
662  __IO uint32_t CR1;
663  __IO uint32_t CSR1;
664  __IO uint32_t CR2;
665  __IO uint32_t CSR2;
666 } PWR_TypeDef;
667 
668 
673 typedef struct
674 {
675  __IO uint32_t CR;
676  __IO uint32_t PLLCFGR;
677  __IO uint32_t CFGR;
678  __IO uint32_t CIR;
679  __IO uint32_t AHB1RSTR;
680  __IO uint32_t AHB2RSTR;
681  __IO uint32_t AHB3RSTR;
682  uint32_t RESERVED0;
683  __IO uint32_t APB1RSTR;
684  __IO uint32_t APB2RSTR;
685  uint32_t RESERVED1[2];
686  __IO uint32_t AHB1ENR;
687  __IO uint32_t AHB2ENR;
688  __IO uint32_t AHB3ENR;
689  uint32_t RESERVED2;
690  __IO uint32_t APB1ENR;
691  __IO uint32_t APB2ENR;
692  uint32_t RESERVED3[2];
693  __IO uint32_t AHB1LPENR;
694  __IO uint32_t AHB2LPENR;
695  __IO uint32_t AHB3LPENR;
696  uint32_t RESERVED4;
697  __IO uint32_t APB1LPENR;
698  __IO uint32_t APB2LPENR;
699  uint32_t RESERVED5[2];
700  __IO uint32_t BDCR;
701  __IO uint32_t CSR;
702  uint32_t RESERVED6[2];
703  __IO uint32_t SSCGR;
704  __IO uint32_t PLLI2SCFGR;
705  __IO uint32_t PLLSAICFGR;
706  __IO uint32_t DCKCFGR1;
707  __IO uint32_t DCKCFGR2;
709 } RCC_TypeDef;
710 
715 typedef struct
716 {
717  __IO uint32_t TR;
718  __IO uint32_t DR;
719  __IO uint32_t CR;
720  __IO uint32_t ISR;
721  __IO uint32_t PRER;
722  __IO uint32_t WUTR;
723  uint32_t reserved;
724  __IO uint32_t ALRMAR;
725  __IO uint32_t ALRMBR;
726  __IO uint32_t WPR;
727  __IO uint32_t SSR;
728  __IO uint32_t SHIFTR;
729  __IO uint32_t TSTR;
730  __IO uint32_t TSDR;
731  __IO uint32_t TSSSR;
732  __IO uint32_t CALR;
733  __IO uint32_t TAMPCR;
734  __IO uint32_t ALRMASSR;
735  __IO uint32_t ALRMBSSR;
736  __IO uint32_t OR;
737  __IO uint32_t BKP0R;
738  __IO uint32_t BKP1R;
739  __IO uint32_t BKP2R;
740  __IO uint32_t BKP3R;
741  __IO uint32_t BKP4R;
742  __IO uint32_t BKP5R;
743  __IO uint32_t BKP6R;
744  __IO uint32_t BKP7R;
745  __IO uint32_t BKP8R;
746  __IO uint32_t BKP9R;
747  __IO uint32_t BKP10R;
748  __IO uint32_t BKP11R;
749  __IO uint32_t BKP12R;
750  __IO uint32_t BKP13R;
751  __IO uint32_t BKP14R;
752  __IO uint32_t BKP15R;
753  __IO uint32_t BKP16R;
754  __IO uint32_t BKP17R;
755  __IO uint32_t BKP18R;
756  __IO uint32_t BKP19R;
757  __IO uint32_t BKP20R;
758  __IO uint32_t BKP21R;
759  __IO uint32_t BKP22R;
760  __IO uint32_t BKP23R;
761  __IO uint32_t BKP24R;
762  __IO uint32_t BKP25R;
763  __IO uint32_t BKP26R;
764  __IO uint32_t BKP27R;
765  __IO uint32_t BKP28R;
766  __IO uint32_t BKP29R;
767  __IO uint32_t BKP30R;
768  __IO uint32_t BKP31R;
769 } RTC_TypeDef;
770 
771 
776 typedef struct
777 {
778  __IO uint32_t GCR;
779 } SAI_TypeDef;
780 
781 typedef struct
782 {
783  __IO uint32_t CR1;
784  __IO uint32_t CR2;
785  __IO uint32_t FRCR;
786  __IO uint32_t SLOTR;
787  __IO uint32_t IMR;
788  __IO uint32_t SR;
789  __IO uint32_t CLRFR;
790  __IO uint32_t DR;
791 } SAI_Block_TypeDef;
792 
797 typedef struct
798 {
799  __IO uint32_t CR;
800  __IO uint32_t IMR;
801  __IO uint32_t SR;
802  __IO uint32_t IFCR;
803  __IO uint32_t DR;
804  __IO uint32_t CSR;
805  __IO uint32_t DIR;
806 } SPDIFRX_TypeDef;
807 
808 
813 typedef struct
814 {
815  __IO uint32_t POWER;
816  __IO uint32_t CLKCR;
817  __IO uint32_t ARG;
818  __IO uint32_t CMD;
819  __I uint32_t RESPCMD;
820  __I uint32_t RESP1;
821  __I uint32_t RESP2;
822  __I uint32_t RESP3;
823  __I uint32_t RESP4;
824  __IO uint32_t DTIMER;
825  __IO uint32_t DLEN;
826  __IO uint32_t DCTRL;
827  __I uint32_t DCOUNT;
828  __I uint32_t STA;
829  __IO uint32_t ICR;
830  __IO uint32_t MASK;
831  uint32_t RESERVED0[2];
832  __I uint32_t FIFOCNT;
833  uint32_t RESERVED1[13];
834  __IO uint32_t FIFO;
835 } SDMMC_TypeDef;
836 
841 typedef struct
842 {
843  __IO uint32_t CR1;
844  __IO uint32_t CR2;
845  __IO uint32_t SR;
846  __IO uint32_t DR;
847  __IO uint32_t CRCPR;
848  __IO uint32_t RXCRCR;
849  __IO uint32_t TXCRCR;
850  __IO uint32_t I2SCFGR;
851  __IO uint32_t I2SPR;
852 } SPI_TypeDef;
853 
858 typedef struct
859 {
860  __IO uint32_t CR;
861  __IO uint32_t DCR;
862  __IO uint32_t SR;
863  __IO uint32_t FCR;
864  __IO uint32_t DLR;
865  __IO uint32_t CCR;
866  __IO uint32_t AR;
867  __IO uint32_t ABR;
868  __IO uint32_t DR;
869  __IO uint32_t PSMKR;
870  __IO uint32_t PSMAR;
871  __IO uint32_t PIR;
872  __IO uint32_t LPTR;
873 } QUADSPI_TypeDef;
874 
879 typedef struct
880 {
881  __IO uint32_t CR1;
882  __IO uint32_t CR2;
883  __IO uint32_t SMCR;
884  __IO uint32_t DIER;
885  __IO uint32_t SR;
886  __IO uint32_t EGR;
887  __IO uint32_t CCMR1;
888  __IO uint32_t CCMR2;
889  __IO uint32_t CCER;
890  __IO uint32_t CNT;
891  __IO uint32_t PSC;
892  __IO uint32_t ARR;
893  __IO uint32_t RCR;
894  __IO uint32_t CCR1;
895  __IO uint32_t CCR2;
896  __IO uint32_t CCR3;
897  __IO uint32_t CCR4;
898  __IO uint32_t BDTR;
899  __IO uint32_t DCR;
900  __IO uint32_t DMAR;
901  __IO uint32_t OR;
902  __IO uint32_t CCMR3;
903  __IO uint32_t CCR5;
904  __IO uint32_t CCR6;
906 } TIM_TypeDef;
907 
911 typedef struct
912 {
913  __IO uint32_t ISR;
914  __IO uint32_t ICR;
915  __IO uint32_t IER;
916  __IO uint32_t CFGR;
917  __IO uint32_t CR;
918  __IO uint32_t CMP;
919  __IO uint32_t ARR;
920  __IO uint32_t CNT;
921 } LPTIM_TypeDef;
922 
923 
928 typedef struct
929 {
930  __IO uint32_t CR1;
931  __IO uint32_t CR2;
932  __IO uint32_t CR3;
933  __IO uint32_t BRR;
934  __IO uint32_t GTPR;
935  __IO uint32_t RTOR;
936  __IO uint32_t RQR;
937  __IO uint32_t ISR;
938  __IO uint32_t ICR;
939  __IO uint32_t RDR;
940  __IO uint32_t TDR;
941 } USART_TypeDef;
942 
943 
948 typedef struct
949 {
950  __IO uint32_t CR;
951  __IO uint32_t CFR;
952  __IO uint32_t SR;
953 } WWDG_TypeDef;
954 
955 
960 typedef struct
961 {
962  __IO uint32_t CR;
963  __IO uint32_t SR;
964  __IO uint32_t DR;
965 } RNG_TypeDef;
966 
974 typedef struct
975 {
976  __IO uint32_t GOTGCTL;
977  __IO uint32_t GOTGINT;
978  __IO uint32_t GAHBCFG;
979  __IO uint32_t GUSBCFG;
980  __IO uint32_t GRSTCTL;
981  __IO uint32_t GINTSTS;
982  __IO uint32_t GINTMSK;
983  __IO uint32_t GRXSTSR;
984  __IO uint32_t GRXSTSP;
985  __IO uint32_t GRXFSIZ;
986  __IO uint32_t DIEPTXF0_HNPTXFSIZ;
987  __IO uint32_t HNPTXSTS;
988  uint32_t Reserved30[2];
989  __IO uint32_t GCCFG;
990  __IO uint32_t CID;
991  uint32_t Reserved5[3];
992  __IO uint32_t GHWCFG3;
993  uint32_t Reserved6;
994  __IO uint32_t GLPMCFG;
995  __IO uint32_t GPWRDN;
996  __IO uint32_t GDFIFOCFG;
997  __IO uint32_t GADPCTL;
998  uint32_t Reserved43[39];
999  __IO uint32_t HPTXFSIZ;
1000  __IO uint32_t DIEPTXF[0x0F];
1001 } USB_OTG_GlobalTypeDef;
1002 
1003 
1007 typedef struct
1008 {
1009  __IO uint32_t DCFG;
1010  __IO uint32_t DCTL;
1011  __IO uint32_t DSTS;
1012  uint32_t Reserved0C;
1013  __IO uint32_t DIEPMSK;
1014  __IO uint32_t DOEPMSK;
1015  __IO uint32_t DAINT;
1016  __IO uint32_t DAINTMSK;
1017  uint32_t Reserved20;
1018  uint32_t Reserved9;
1019  __IO uint32_t DVBUSDIS;
1020  __IO uint32_t DVBUSPULSE;
1021  __IO uint32_t DTHRCTL;
1022  __IO uint32_t DIEPEMPMSK;
1023  __IO uint32_t DEACHINT;
1024  __IO uint32_t DEACHMSK;
1025  uint32_t Reserved40;
1026  __IO uint32_t DINEP1MSK;
1027  uint32_t Reserved44[15];
1028  __IO uint32_t DOUTEP1MSK;
1029 } USB_OTG_DeviceTypeDef;
1030 
1031 
1035 typedef struct
1036 {
1037  __IO uint32_t DIEPCTL;
1038  uint32_t Reserved04;
1039  __IO uint32_t DIEPINT;
1040  uint32_t Reserved0C;
1041  __IO uint32_t DIEPTSIZ;
1042  __IO uint32_t DIEPDMA;
1043  __IO uint32_t DTXFSTS;
1044  uint32_t Reserved18;
1045 } USB_OTG_INEndpointTypeDef;
1046 
1047 
1051 typedef struct
1052 {
1053  __IO uint32_t DOEPCTL;
1054  uint32_t Reserved04;
1055  __IO uint32_t DOEPINT;
1056  uint32_t Reserved0C;
1057  __IO uint32_t DOEPTSIZ;
1058  __IO uint32_t DOEPDMA;
1059  uint32_t Reserved18[2];
1060 } USB_OTG_OUTEndpointTypeDef;
1061 
1062 
1066 typedef struct
1067 {
1068  __IO uint32_t HCFG;
1069  __IO uint32_t HFIR;
1070  __IO uint32_t HFNUM;
1071  uint32_t Reserved40C;
1072  __IO uint32_t HPTXSTS;
1073  __IO uint32_t HAINT;
1074  __IO uint32_t HAINTMSK;
1075 } USB_OTG_HostTypeDef;
1076 
1080 typedef struct
1081 {
1082  __IO uint32_t HCCHAR;
1083  __IO uint32_t HCSPLT;
1084  __IO uint32_t HCINT;
1085  __IO uint32_t HCINTMSK;
1086  __IO uint32_t HCTSIZ;
1087  __IO uint32_t HCDMA;
1088  uint32_t Reserved[2];
1089 } USB_OTG_HostChannelTypeDef;
1100 #define RAMITCM_BASE 0x00000000U
1101 #define FLASHITCM_BASE 0x00200000U
1102 #define FLASHAXI_BASE 0x08000000U
1103 #define RAMDTCM_BASE 0x20000000U
1104 #define PERIPH_BASE 0x40000000U
1105 #define BKPSRAM_BASE 0x40024000U
1106 #define QSPI_BASE 0x90000000U
1107 #define FMC_R_BASE 0xA0000000U
1108 #define QSPI_R_BASE 0xA0001000U
1109 #define SRAM1_BASE 0x20010000U
1110 #define SRAM2_BASE 0x2004C000U
1111 #define FLASH_END 0x080FFFFFU
1113 /* Legacy define */
1114 #define FLASH_BASE FLASHAXI_BASE
1115 
1117 #define APB1PERIPH_BASE PERIPH_BASE
1118 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
1119 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
1120 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
1121 
1123 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
1124 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
1125 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
1126 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
1127 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
1128 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
1129 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
1130 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
1131 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
1132 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
1133 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
1134 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
1135 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
1136 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
1137 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
1138 #define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U)
1139 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
1140 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
1141 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
1142 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
1143 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
1144 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
1145 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
1146 #define I2C4_BASE (APB1PERIPH_BASE + 0x6000U)
1147 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
1148 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
1149 #define CEC_BASE (APB1PERIPH_BASE + 0x6C00U)
1150 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
1151 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
1152 #define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
1153 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
1154 
1156 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
1157 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
1158 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
1159 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
1160 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
1161 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
1162 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
1163 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
1164 #define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U)
1165 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1166 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
1167 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
1168 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
1169 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
1170 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
1171 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
1172 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
1173 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
1174 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
1175 #define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U)
1176 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
1177 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
1178 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004U)
1179 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024U)
1180 
1181 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
1182 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
1183 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
1184 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
1185 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
1186 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
1187 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
1188 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
1189 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
1190 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
1191 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
1192 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1193 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
1194 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
1195 #define UID_BASE 0x1FF0F420U
1196 #define FLASHSIZE_BASE 0x1FF0F442U
1197 #define PACKAGESIZE_BASE 0x1FFF7BF0U
1198 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
1199 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
1200 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
1201 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
1202 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
1203 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
1204 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
1205 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
1206 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
1207 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
1208 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
1209 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
1210 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
1211 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
1212 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
1213 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
1214 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
1215 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
1216 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
1217 #define ETH_MAC_BASE (ETH_BASE)
1218 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
1219 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
1220 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
1221 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
1222 
1223 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
1224 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
1225 
1226 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
1227 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
1228 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
1229 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
1230 
1231 /* Debug MCU registers base address */
1232 #define DBGMCU_BASE 0xE0042000U
1233 
1235 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
1236 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
1237 
1238 #define USB_OTG_GLOBAL_BASE 0x000U
1239 #define USB_OTG_DEVICE_BASE 0x800U
1240 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
1241 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
1242 #define USB_OTG_EP_REG_SIZE 0x20U
1243 #define USB_OTG_HOST_BASE 0x400U
1244 #define USB_OTG_HOST_PORT_BASE 0x440U
1245 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
1246 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
1247 #define USB_OTG_PCGCCTL_BASE 0xE00U
1248 #define USB_OTG_FIFO_BASE 0x1000U
1249 #define USB_OTG_FIFO_SIZE 0x1000U
1250 
1258 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1259 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1260 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1261 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1262 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1263 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1264 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1265 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1266 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1267 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1268 #define RTC ((RTC_TypeDef *) RTC_BASE)
1269 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1270 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1271 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1272 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1273 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
1274 #define USART2 ((USART_TypeDef *) USART2_BASE)
1275 #define USART3 ((USART_TypeDef *) USART3_BASE)
1276 #define UART4 ((USART_TypeDef *) UART4_BASE)
1277 #define UART5 ((USART_TypeDef *) UART5_BASE)
1278 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1279 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1280 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1281 #define I2C4 ((I2C_TypeDef *) I2C4_BASE)
1282 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1283 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1284 #define CEC ((CEC_TypeDef *) CEC_BASE)
1285 #define PWR ((PWR_TypeDef *) PWR_BASE)
1286 #define DAC ((DAC_TypeDef *) DAC_BASE)
1287 #define UART7 ((USART_TypeDef *) UART7_BASE)
1288 #define UART8 ((USART_TypeDef *) UART8_BASE)
1289 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1290 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1291 #define USART1 ((USART_TypeDef *) USART1_BASE)
1292 #define USART6 ((USART_TypeDef *) USART6_BASE)
1293 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1294 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1295 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1296 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1297 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
1298 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1299 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1300 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1301 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1302 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1303 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1304 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1305 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1306 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
1307 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1308 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
1309 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1310 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1311 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
1312 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
1313 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1314 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1315 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1316 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1317 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1318 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1319 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1320 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1321 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1322 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
1323 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
1324 #define CRC ((CRC_TypeDef *) CRC_BASE)
1325 #define RCC ((RCC_TypeDef *) RCC_BASE)
1326 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1327 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1328 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1329 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1330 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1331 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1332 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1333 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1334 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1335 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1336 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1337 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1338 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1339 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1340 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1341 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1342 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1343 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1344 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1345 #define ETH ((ETH_TypeDef *) ETH_BASE)
1346 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1347 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1348 #define RNG ((RNG_TypeDef *) RNG_BASE)
1349 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1350 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1351 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1352 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1353 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1354 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1355 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1356 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1357 
1370 /******************************************************************************/
1371 /* Peripheral Registers_Bits_Definition */
1372 /******************************************************************************/
1373 
1374 /******************************************************************************/
1375 /* */
1376 /* Analog to Digital Converter */
1377 /* */
1378 /******************************************************************************/
1379 /******************** Bit definition for ADC_SR register ********************/
1380 #define ADC_SR_AWD 0x00000001U
1381 #define ADC_SR_EOC 0x00000002U
1382 #define ADC_SR_JEOC 0x00000004U
1383 #define ADC_SR_JSTRT 0x00000008U
1384 #define ADC_SR_STRT 0x00000010U
1385 #define ADC_SR_OVR 0x00000020U
1387 /******************* Bit definition for ADC_CR1 register ********************/
1388 #define ADC_CR1_AWDCH 0x0000001FU
1389 #define ADC_CR1_AWDCH_0 0x00000001U
1390 #define ADC_CR1_AWDCH_1 0x00000002U
1391 #define ADC_CR1_AWDCH_2 0x00000004U
1392 #define ADC_CR1_AWDCH_3 0x00000008U
1393 #define ADC_CR1_AWDCH_4 0x00000010U
1394 #define ADC_CR1_EOCIE 0x00000020U
1395 #define ADC_CR1_AWDIE 0x00000040U
1396 #define ADC_CR1_JEOCIE 0x00000080U
1397 #define ADC_CR1_SCAN 0x00000100U
1398 #define ADC_CR1_AWDSGL 0x00000200U
1399 #define ADC_CR1_JAUTO 0x00000400U
1400 #define ADC_CR1_DISCEN 0x00000800U
1401 #define ADC_CR1_JDISCEN 0x00001000U
1402 #define ADC_CR1_DISCNUM 0x0000E000U
1403 #define ADC_CR1_DISCNUM_0 0x00002000U
1404 #define ADC_CR1_DISCNUM_1 0x00004000U
1405 #define ADC_CR1_DISCNUM_2 0x00008000U
1406 #define ADC_CR1_JAWDEN 0x00400000U
1407 #define ADC_CR1_AWDEN 0x00800000U
1408 #define ADC_CR1_RES 0x03000000U
1409 #define ADC_CR1_RES_0 0x01000000U
1410 #define ADC_CR1_RES_1 0x02000000U
1411 #define ADC_CR1_OVRIE 0x04000000U
1413 /******************* Bit definition for ADC_CR2 register ********************/
1414 #define ADC_CR2_ADON 0x00000001U
1415 #define ADC_CR2_CONT 0x00000002U
1416 #define ADC_CR2_DMA 0x00000100U
1417 #define ADC_CR2_DDS 0x00000200U
1418 #define ADC_CR2_EOCS 0x00000400U
1419 #define ADC_CR2_ALIGN 0x00000800U
1420 #define ADC_CR2_JEXTSEL 0x000F0000U
1421 #define ADC_CR2_JEXTSEL_0 0x00010000U
1422 #define ADC_CR2_JEXTSEL_1 0x00020000U
1423 #define ADC_CR2_JEXTSEL_2 0x00040000U
1424 #define ADC_CR2_JEXTSEL_3 0x00080000U
1425 #define ADC_CR2_JEXTEN 0x00300000U
1426 #define ADC_CR2_JEXTEN_0 0x00100000U
1427 #define ADC_CR2_JEXTEN_1 0x00200000U
1428 #define ADC_CR2_JSWSTART 0x00400000U
1429 #define ADC_CR2_EXTSEL 0x0F000000U
1430 #define ADC_CR2_EXTSEL_0 0x01000000U
1431 #define ADC_CR2_EXTSEL_1 0x02000000U
1432 #define ADC_CR2_EXTSEL_2 0x04000000U
1433 #define ADC_CR2_EXTSEL_3 0x08000000U
1434 #define ADC_CR2_EXTEN 0x30000000U
1435 #define ADC_CR2_EXTEN_0 0x10000000U
1436 #define ADC_CR2_EXTEN_1 0x20000000U
1437 #define ADC_CR2_SWSTART 0x40000000U
1439 /****************** Bit definition for ADC_SMPR1 register *******************/
1440 #define ADC_SMPR1_SMP10 0x00000007U
1441 #define ADC_SMPR1_SMP10_0 0x00000001U
1442 #define ADC_SMPR1_SMP10_1 0x00000002U
1443 #define ADC_SMPR1_SMP10_2 0x00000004U
1444 #define ADC_SMPR1_SMP11 0x00000038U
1445 #define ADC_SMPR1_SMP11_0 0x00000008U
1446 #define ADC_SMPR1_SMP11_1 0x00000010U
1447 #define ADC_SMPR1_SMP11_2 0x00000020U
1448 #define ADC_SMPR1_SMP12 0x000001C0U
1449 #define ADC_SMPR1_SMP12_0 0x00000040U
1450 #define ADC_SMPR1_SMP12_1 0x00000080U
1451 #define ADC_SMPR1_SMP12_2 0x00000100U
1452 #define ADC_SMPR1_SMP13 0x00000E00U
1453 #define ADC_SMPR1_SMP13_0 0x00000200U
1454 #define ADC_SMPR1_SMP13_1 0x00000400U
1455 #define ADC_SMPR1_SMP13_2 0x00000800U
1456 #define ADC_SMPR1_SMP14 0x00007000U
1457 #define ADC_SMPR1_SMP14_0 0x00001000U
1458 #define ADC_SMPR1_SMP14_1 0x00002000U
1459 #define ADC_SMPR1_SMP14_2 0x00004000U
1460 #define ADC_SMPR1_SMP15 0x00038000U
1461 #define ADC_SMPR1_SMP15_0 0x00008000U
1462 #define ADC_SMPR1_SMP15_1 0x00010000U
1463 #define ADC_SMPR1_SMP15_2 0x00020000U
1464 #define ADC_SMPR1_SMP16 0x001C0000U
1465 #define ADC_SMPR1_SMP16_0 0x00040000U
1466 #define ADC_SMPR1_SMP16_1 0x00080000U
1467 #define ADC_SMPR1_SMP16_2 0x00100000U
1468 #define ADC_SMPR1_SMP17 0x00E00000U
1469 #define ADC_SMPR1_SMP17_0 0x00200000U
1470 #define ADC_SMPR1_SMP17_1 0x00400000U
1471 #define ADC_SMPR1_SMP17_2 0x00800000U
1472 #define ADC_SMPR1_SMP18 0x07000000U
1473 #define ADC_SMPR1_SMP18_0 0x01000000U
1474 #define ADC_SMPR1_SMP18_1 0x02000000U
1475 #define ADC_SMPR1_SMP18_2 0x04000000U
1477 /****************** Bit definition for ADC_SMPR2 register *******************/
1478 #define ADC_SMPR2_SMP0 0x00000007U
1479 #define ADC_SMPR2_SMP0_0 0x00000001U
1480 #define ADC_SMPR2_SMP0_1 0x00000002U
1481 #define ADC_SMPR2_SMP0_2 0x00000004U
1482 #define ADC_SMPR2_SMP1 0x00000038U
1483 #define ADC_SMPR2_SMP1_0 0x00000008U
1484 #define ADC_SMPR2_SMP1_1 0x00000010U
1485 #define ADC_SMPR2_SMP1_2 0x00000020U
1486 #define ADC_SMPR2_SMP2 0x000001C0U
1487 #define ADC_SMPR2_SMP2_0 0x00000040U
1488 #define ADC_SMPR2_SMP2_1 0x00000080U
1489 #define ADC_SMPR2_SMP2_2 0x00000100U
1490 #define ADC_SMPR2_SMP3 0x00000E00U
1491 #define ADC_SMPR2_SMP3_0 0x00000200U
1492 #define ADC_SMPR2_SMP3_1 0x00000400U
1493 #define ADC_SMPR2_SMP3_2 0x00000800U
1494 #define ADC_SMPR2_SMP4 0x00007000U
1495 #define ADC_SMPR2_SMP4_0 0x00001000U
1496 #define ADC_SMPR2_SMP4_1 0x00002000U
1497 #define ADC_SMPR2_SMP4_2 0x00004000U
1498 #define ADC_SMPR2_SMP5 0x00038000U
1499 #define ADC_SMPR2_SMP5_0 0x00008000U
1500 #define ADC_SMPR2_SMP5_1 0x00010000U
1501 #define ADC_SMPR2_SMP5_2 0x00020000U
1502 #define ADC_SMPR2_SMP6 0x001C0000U
1503 #define ADC_SMPR2_SMP6_0 0x00040000U
1504 #define ADC_SMPR2_SMP6_1 0x00080000U
1505 #define ADC_SMPR2_SMP6_2 0x00100000U
1506 #define ADC_SMPR2_SMP7 0x00E00000U
1507 #define ADC_SMPR2_SMP7_0 0x00200000U
1508 #define ADC_SMPR2_SMP7_1 0x00400000U
1509 #define ADC_SMPR2_SMP7_2 0x00800000U
1510 #define ADC_SMPR2_SMP8 0x07000000U
1511 #define ADC_SMPR2_SMP8_0 0x01000000U
1512 #define ADC_SMPR2_SMP8_1 0x02000000U
1513 #define ADC_SMPR2_SMP8_2 0x04000000U
1514 #define ADC_SMPR2_SMP9 0x38000000U
1515 #define ADC_SMPR2_SMP9_0 0x08000000U
1516 #define ADC_SMPR2_SMP9_1 0x10000000U
1517 #define ADC_SMPR2_SMP9_2 0x20000000U
1519 /****************** Bit definition for ADC_JOFR1 register *******************/
1520 #define ADC_JOFR1_JOFFSET1 0x0FFFU
1522 /****************** Bit definition for ADC_JOFR2 register *******************/
1523 #define ADC_JOFR2_JOFFSET2 0x0FFFU
1525 /****************** Bit definition for ADC_JOFR3 register *******************/
1526 #define ADC_JOFR3_JOFFSET3 0x0FFFU
1528 /****************** Bit definition for ADC_JOFR4 register *******************/
1529 #define ADC_JOFR4_JOFFSET4 0x0FFFU
1531 /******************* Bit definition for ADC_HTR register ********************/
1532 #define ADC_HTR_HT 0x0FFFU
1534 /******************* Bit definition for ADC_LTR register ********************/
1535 #define ADC_LTR_LT 0x0FFFU
1537 /******************* Bit definition for ADC_SQR1 register *******************/
1538 #define ADC_SQR1_SQ13 0x0000001FU
1539 #define ADC_SQR1_SQ13_0 0x00000001U
1540 #define ADC_SQR1_SQ13_1 0x00000002U
1541 #define ADC_SQR1_SQ13_2 0x00000004U
1542 #define ADC_SQR1_SQ13_3 0x00000008U
1543 #define ADC_SQR1_SQ13_4 0x00000010U
1544 #define ADC_SQR1_SQ14 0x000003E0U
1545 #define ADC_SQR1_SQ14_0 0x00000020U
1546 #define ADC_SQR1_SQ14_1 0x00000040U
1547 #define ADC_SQR1_SQ14_2 0x00000080U
1548 #define ADC_SQR1_SQ14_3 0x00000100U
1549 #define ADC_SQR1_SQ14_4 0x00000200U
1550 #define ADC_SQR1_SQ15 0x00007C00U
1551 #define ADC_SQR1_SQ15_0 0x00000400U
1552 #define ADC_SQR1_SQ15_1 0x00000800U
1553 #define ADC_SQR1_SQ15_2 0x00001000U
1554 #define ADC_SQR1_SQ15_3 0x00002000U
1555 #define ADC_SQR1_SQ15_4 0x00004000U
1556 #define ADC_SQR1_SQ16 0x000F8000U
1557 #define ADC_SQR1_SQ16_0 0x00008000U
1558 #define ADC_SQR1_SQ16_1 0x00010000U
1559 #define ADC_SQR1_SQ16_2 0x00020000U
1560 #define ADC_SQR1_SQ16_3 0x00040000U
1561 #define ADC_SQR1_SQ16_4 0x00080000U
1562 #define ADC_SQR1_L 0x00F00000U
1563 #define ADC_SQR1_L_0 0x00100000U
1564 #define ADC_SQR1_L_1 0x00200000U
1565 #define ADC_SQR1_L_2 0x00400000U
1566 #define ADC_SQR1_L_3 0x00800000U
1568 /******************* Bit definition for ADC_SQR2 register *******************/
1569 #define ADC_SQR2_SQ7 0x0000001FU
1570 #define ADC_SQR2_SQ7_0 0x00000001U
1571 #define ADC_SQR2_SQ7_1 0x00000002U
1572 #define ADC_SQR2_SQ7_2 0x00000004U
1573 #define ADC_SQR2_SQ7_3 0x00000008U
1574 #define ADC_SQR2_SQ7_4 0x00000010U
1575 #define ADC_SQR2_SQ8 0x000003E0U
1576 #define ADC_SQR2_SQ8_0 0x00000020U
1577 #define ADC_SQR2_SQ8_1 0x00000040U
1578 #define ADC_SQR2_SQ8_2 0x00000080U
1579 #define ADC_SQR2_SQ8_3 0x00000100U
1580 #define ADC_SQR2_SQ8_4 0x00000200U
1581 #define ADC_SQR2_SQ9 0x00007C00U
1582 #define ADC_SQR2_SQ9_0 0x00000400U
1583 #define ADC_SQR2_SQ9_1 0x00000800U
1584 #define ADC_SQR2_SQ9_2 0x00001000U
1585 #define ADC_SQR2_SQ9_3 0x00002000U
1586 #define ADC_SQR2_SQ9_4 0x00004000U
1587 #define ADC_SQR2_SQ10 0x000F8000U
1588 #define ADC_SQR2_SQ10_0 0x00008000U
1589 #define ADC_SQR2_SQ10_1 0x00010000U
1590 #define ADC_SQR2_SQ10_2 0x00020000U
1591 #define ADC_SQR2_SQ10_3 0x00040000U
1592 #define ADC_SQR2_SQ10_4 0x00080000U
1593 #define ADC_SQR2_SQ11 0x01F00000U
1594 #define ADC_SQR2_SQ11_0 0x00100000U
1595 #define ADC_SQR2_SQ11_1 0x00200000U
1596 #define ADC_SQR2_SQ11_2 0x00400000U
1597 #define ADC_SQR2_SQ11_3 0x00800000U
1598 #define ADC_SQR2_SQ11_4 0x01000000U
1599 #define ADC_SQR2_SQ12 0x3E000000U
1600 #define ADC_SQR2_SQ12_0 0x02000000U
1601 #define ADC_SQR2_SQ12_1 0x04000000U
1602 #define ADC_SQR2_SQ12_2 0x08000000U
1603 #define ADC_SQR2_SQ12_3 0x10000000U
1604 #define ADC_SQR2_SQ12_4 0x20000000U
1606 /******************* Bit definition for ADC_SQR3 register *******************/
1607 #define ADC_SQR3_SQ1 0x0000001FU
1608 #define ADC_SQR3_SQ1_0 0x00000001U
1609 #define ADC_SQR3_SQ1_1 0x00000002U
1610 #define ADC_SQR3_SQ1_2 0x00000004U
1611 #define ADC_SQR3_SQ1_3 0x00000008U
1612 #define ADC_SQR3_SQ1_4 0x00000010U
1613 #define ADC_SQR3_SQ2 0x000003E0U
1614 #define ADC_SQR3_SQ2_0 0x00000020U
1615 #define ADC_SQR3_SQ2_1 0x00000040U
1616 #define ADC_SQR3_SQ2_2 0x00000080U
1617 #define ADC_SQR3_SQ2_3 0x00000100U
1618 #define ADC_SQR3_SQ2_4 0x00000200U
1619 #define ADC_SQR3_SQ3 0x00007C00U
1620 #define ADC_SQR3_SQ3_0 0x00000400U
1621 #define ADC_SQR3_SQ3_1 0x00000800U
1622 #define ADC_SQR3_SQ3_2 0x00001000U
1623 #define ADC_SQR3_SQ3_3 0x00002000U
1624 #define ADC_SQR3_SQ3_4 0x00004000U
1625 #define ADC_SQR3_SQ4 0x000F8000U
1626 #define ADC_SQR3_SQ4_0 0x00008000U
1627 #define ADC_SQR3_SQ4_1 0x00010000U
1628 #define ADC_SQR3_SQ4_2 0x00020000U
1629 #define ADC_SQR3_SQ4_3 0x00040000U
1630 #define ADC_SQR3_SQ4_4 0x00080000U
1631 #define ADC_SQR3_SQ5 0x01F00000U
1632 #define ADC_SQR3_SQ5_0 0x00100000U
1633 #define ADC_SQR3_SQ5_1 0x00200000U
1634 #define ADC_SQR3_SQ5_2 0x00400000U
1635 #define ADC_SQR3_SQ5_3 0x00800000U
1636 #define ADC_SQR3_SQ5_4 0x01000000U
1637 #define ADC_SQR3_SQ6 0x3E000000U
1638 #define ADC_SQR3_SQ6_0 0x02000000U
1639 #define ADC_SQR3_SQ6_1 0x04000000U
1640 #define ADC_SQR3_SQ6_2 0x08000000U
1641 #define ADC_SQR3_SQ6_3 0x10000000U
1642 #define ADC_SQR3_SQ6_4 0x20000000U
1644 /******************* Bit definition for ADC_JSQR register *******************/
1645 #define ADC_JSQR_JSQ1 0x0000001FU
1646 #define ADC_JSQR_JSQ1_0 0x00000001U
1647 #define ADC_JSQR_JSQ1_1 0x00000002U
1648 #define ADC_JSQR_JSQ1_2 0x00000004U
1649 #define ADC_JSQR_JSQ1_3 0x00000008U
1650 #define ADC_JSQR_JSQ1_4 0x00000010U
1651 #define ADC_JSQR_JSQ2 0x000003E0U
1652 #define ADC_JSQR_JSQ2_0 0x00000020U
1653 #define ADC_JSQR_JSQ2_1 0x00000040U
1654 #define ADC_JSQR_JSQ2_2 0x00000080U
1655 #define ADC_JSQR_JSQ2_3 0x00000100U
1656 #define ADC_JSQR_JSQ2_4 0x00000200U
1657 #define ADC_JSQR_JSQ3 0x00007C00U
1658 #define ADC_JSQR_JSQ3_0 0x00000400U
1659 #define ADC_JSQR_JSQ3_1 0x00000800U
1660 #define ADC_JSQR_JSQ3_2 0x00001000U
1661 #define ADC_JSQR_JSQ3_3 0x00002000U
1662 #define ADC_JSQR_JSQ3_4 0x00004000U
1663 #define ADC_JSQR_JSQ4 0x000F8000U
1664 #define ADC_JSQR_JSQ4_0 0x00008000U
1665 #define ADC_JSQR_JSQ4_1 0x00010000U
1666 #define ADC_JSQR_JSQ4_2 0x00020000U
1667 #define ADC_JSQR_JSQ4_3 0x00040000U
1668 #define ADC_JSQR_JSQ4_4 0x00080000U
1669 #define ADC_JSQR_JL 0x00300000U
1670 #define ADC_JSQR_JL_0 0x00100000U
1671 #define ADC_JSQR_JL_1 0x00200000U
1673 /******************* Bit definition for ADC_JDR1 register *******************/
1674 #define ADC_JDR1_JDATA ((uint16_t)0xFFFFU)
1676 /******************* Bit definition for ADC_JDR2 register *******************/
1677 #define ADC_JDR2_JDATA ((uint16_t)0xFFFFU)
1679 /******************* Bit definition for ADC_JDR3 register *******************/
1680 #define ADC_JDR3_JDATA ((uint16_t)0xFFFFU)
1682 /******************* Bit definition for ADC_JDR4 register *******************/
1683 #define ADC_JDR4_JDATA ((uint16_t)0xFFFFU)
1685 /******************** Bit definition for ADC_DR register ********************/
1686 #define ADC_DR_DATA 0x0000FFFFU
1687 #define ADC_DR_ADC2DATA 0xFFFF0000U
1689 /******************* Bit definition for ADC_CSR register ********************/
1690 #define ADC_CSR_AWD1 0x00000001U
1691 #define ADC_CSR_EOC1 0x00000002U
1692 #define ADC_CSR_JEOC1 0x00000004U
1693 #define ADC_CSR_JSTRT1 0x00000008U
1694 #define ADC_CSR_STRT1 0x00000010U
1695 #define ADC_CSR_OVR1 0x00000020U
1696 #define ADC_CSR_AWD2 0x00000100U
1697 #define ADC_CSR_EOC2 0x00000200U
1698 #define ADC_CSR_JEOC2 0x00000400U
1699 #define ADC_CSR_JSTRT2 0x00000800U
1700 #define ADC_CSR_STRT2 0x00001000U
1701 #define ADC_CSR_OVR2 0x00002000U
1702 #define ADC_CSR_AWD3 0x00010000U
1703 #define ADC_CSR_EOC3 0x00020000U
1704 #define ADC_CSR_JEOC3 0x00040000U
1705 #define ADC_CSR_JSTRT3 0x00080000U
1706 #define ADC_CSR_STRT3 0x00100000U
1707 #define ADC_CSR_OVR3 0x00200000U
1709 /* Legacy defines */
1710 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1711 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
1712 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
1713 
1714 
1715 /******************* Bit definition for ADC_CCR register ********************/
1716 #define ADC_CCR_MULTI 0x0000001FU
1717 #define ADC_CCR_MULTI_0 0x00000001U
1718 #define ADC_CCR_MULTI_1 0x00000002U
1719 #define ADC_CCR_MULTI_2 0x00000004U
1720 #define ADC_CCR_MULTI_3 0x00000008U
1721 #define ADC_CCR_MULTI_4 0x00000010U
1722 #define ADC_CCR_DELAY 0x00000F00U
1723 #define ADC_CCR_DELAY_0 0x00000100U
1724 #define ADC_CCR_DELAY_1 0x00000200U
1725 #define ADC_CCR_DELAY_2 0x00000400U
1726 #define ADC_CCR_DELAY_3 0x00000800U
1727 #define ADC_CCR_DDS 0x00002000U
1728 #define ADC_CCR_DMA 0x0000C000U
1729 #define ADC_CCR_DMA_0 0x00004000U
1730 #define ADC_CCR_DMA_1 0x00008000U
1731 #define ADC_CCR_ADCPRE 0x00030000U
1732 #define ADC_CCR_ADCPRE_0 0x00010000U
1733 #define ADC_CCR_ADCPRE_1 0x00020000U
1734 #define ADC_CCR_VBATE 0x00400000U
1735 #define ADC_CCR_TSVREFE 0x00800000U
1737 /******************* Bit definition for ADC_CDR register ********************/
1738 #define ADC_CDR_DATA1 0x0000FFFFU
1739 #define ADC_CDR_DATA2 0xFFFF0000U
1741 /******************************************************************************/
1742 /* */
1743 /* Controller Area Network */
1744 /* */
1745 /******************************************************************************/
1747 /******************* Bit definition for CAN_MCR register ********************/
1748 #define CAN_MCR_INRQ 0x00000001U
1749 #define CAN_MCR_SLEEP 0x00000002U
1750 #define CAN_MCR_TXFP 0x00000004U
1751 #define CAN_MCR_RFLM 0x00000008U
1752 #define CAN_MCR_NART 0x00000010U
1753 #define CAN_MCR_AWUM 0x00000020U
1754 #define CAN_MCR_ABOM 0x00000040U
1755 #define CAN_MCR_TTCM 0x00000080U
1756 #define CAN_MCR_RESET 0x00008000U
1758 /******************* Bit definition for CAN_MSR register ********************/
1759 #define CAN_MSR_INAK 0x00000001U
1760 #define CAN_MSR_SLAK 0x00000002U
1761 #define CAN_MSR_ERRI 0x00000004U
1762 #define CAN_MSR_WKUI 0x00000008U
1763 #define CAN_MSR_SLAKI 0x00000010U
1764 #define CAN_MSR_TXM 0x00000100U
1765 #define CAN_MSR_RXM 0x00000200U
1766 #define CAN_MSR_SAMP 0x00000400U
1767 #define CAN_MSR_RX 0x00000800U
1769 /******************* Bit definition for CAN_TSR register ********************/
1770 #define CAN_TSR_RQCP0 0x00000001U
1771 #define CAN_TSR_TXOK0 0x00000002U
1772 #define CAN_TSR_ALST0 0x00000004U
1773 #define CAN_TSR_TERR0 0x00000008U
1774 #define CAN_TSR_ABRQ0 0x00000080U
1775 #define CAN_TSR_RQCP1 0x00000100U
1776 #define CAN_TSR_TXOK1 0x00000200U
1777 #define CAN_TSR_ALST1 0x00000400U
1778 #define CAN_TSR_TERR1 0x00000800U
1779 #define CAN_TSR_ABRQ1 0x00008000U
1780 #define CAN_TSR_RQCP2 0x00010000U
1781 #define CAN_TSR_TXOK2 0x00020000U
1782 #define CAN_TSR_ALST2 0x00040000U
1783 #define CAN_TSR_TERR2 0x00080000U
1784 #define CAN_TSR_ABRQ2 0x00800000U
1785 #define CAN_TSR_CODE 0x03000000U
1787 #define CAN_TSR_TME 0x1C000000U
1788 #define CAN_TSR_TME0 0x04000000U
1789 #define CAN_TSR_TME1 0x08000000U
1790 #define CAN_TSR_TME2 0x10000000U
1792 #define CAN_TSR_LOW 0xE0000000U
1793 #define CAN_TSR_LOW0 0x20000000U
1794 #define CAN_TSR_LOW1 0x40000000U
1795 #define CAN_TSR_LOW2 0x80000000U
1797 /******************* Bit definition for CAN_RF0R register *******************/
1798 #define CAN_RF0R_FMP0 0x00000003U
1799 #define CAN_RF0R_FULL0 0x00000008U
1800 #define CAN_RF0R_FOVR0 0x00000010U
1801 #define CAN_RF0R_RFOM0 0x00000020U
1803 /******************* Bit definition for CAN_RF1R register *******************/
1804 #define CAN_RF1R_FMP1 0x00000003U
1805 #define CAN_RF1R_FULL1 0x00000008U
1806 #define CAN_RF1R_FOVR1 0x00000010U
1807 #define CAN_RF1R_RFOM1 0x00000020U
1809 /******************** Bit definition for CAN_IER register *******************/
1810 #define CAN_IER_TMEIE 0x00000001U
1811 #define CAN_IER_FMPIE0 0x00000002U
1812 #define CAN_IER_FFIE0 0x00000004U
1813 #define CAN_IER_FOVIE0 0x00000008U
1814 #define CAN_IER_FMPIE1 0x00000010U
1815 #define CAN_IER_FFIE1 0x00000020U
1816 #define CAN_IER_FOVIE1 0x00000040U
1817 #define CAN_IER_EWGIE 0x00000100U
1818 #define CAN_IER_EPVIE 0x00000200U
1819 #define CAN_IER_BOFIE 0x00000400U
1820 #define CAN_IER_LECIE 0x00000800U
1821 #define CAN_IER_ERRIE 0x00008000U
1822 #define CAN_IER_WKUIE 0x00010000U
1823 #define CAN_IER_SLKIE 0x00020000U
1825 /******************** Bit definition for CAN_ESR register *******************/
1826 #define CAN_ESR_EWGF 0x00000001U
1827 #define CAN_ESR_EPVF 0x00000002U
1828 #define CAN_ESR_BOFF 0x00000004U
1830 #define CAN_ESR_LEC 0x00000070U
1831 #define CAN_ESR_LEC_0 0x00000010U
1832 #define CAN_ESR_LEC_1 0x00000020U
1833 #define CAN_ESR_LEC_2 0x00000040U
1835 #define CAN_ESR_TEC 0x00FF0000U
1836 #define CAN_ESR_REC 0xFF000000U
1838 /******************* Bit definition for CAN_BTR register ********************/
1839 #define CAN_BTR_BRP 0x000003FFU
1840 #define CAN_BTR_TS1 0x000F0000U
1841 #define CAN_BTR_TS1_0 0x00010000U
1842 #define CAN_BTR_TS1_1 0x00020000U
1843 #define CAN_BTR_TS1_2 0x00040000U
1844 #define CAN_BTR_TS1_3 0x00080000U
1845 #define CAN_BTR_TS2 0x00700000U
1846 #define CAN_BTR_TS2_0 0x00100000U
1847 #define CAN_BTR_TS2_1 0x00200000U
1848 #define CAN_BTR_TS2_2 0x00400000U
1849 #define CAN_BTR_SJW 0x03000000U
1850 #define CAN_BTR_SJW_0 0x01000000U
1851 #define CAN_BTR_SJW_1 0x02000000U
1852 #define CAN_BTR_LBKM 0x40000000U
1853 #define CAN_BTR_SILM 0x80000000U
1856 /****************** Bit definition for CAN_TI0R register ********************/
1857 #define CAN_TI0R_TXRQ 0x00000001U
1858 #define CAN_TI0R_RTR 0x00000002U
1859 #define CAN_TI0R_IDE 0x00000004U
1860 #define CAN_TI0R_EXID 0x001FFFF8U
1861 #define CAN_TI0R_STID 0xFFE00000U
1863 /****************** Bit definition for CAN_TDT0R register *******************/
1864 #define CAN_TDT0R_DLC 0x0000000FU
1865 #define CAN_TDT0R_TGT 0x00000100U
1866 #define CAN_TDT0R_TIME 0xFFFF0000U
1868 /****************** Bit definition for CAN_TDL0R register *******************/
1869 #define CAN_TDL0R_DATA0 0x000000FFU
1870 #define CAN_TDL0R_DATA1 0x0000FF00U
1871 #define CAN_TDL0R_DATA2 0x00FF0000U
1872 #define CAN_TDL0R_DATA3 0xFF000000U
1874 /****************** Bit definition for CAN_TDH0R register *******************/
1875 #define CAN_TDH0R_DATA4 0x000000FFU
1876 #define CAN_TDH0R_DATA5 0x0000FF00U
1877 #define CAN_TDH0R_DATA6 0x00FF0000U
1878 #define CAN_TDH0R_DATA7 0xFF000000U
1880 /******************* Bit definition for CAN_TI1R register *******************/
1881 #define CAN_TI1R_TXRQ 0x00000001U
1882 #define CAN_TI1R_RTR 0x00000002U
1883 #define CAN_TI1R_IDE 0x00000004U
1884 #define CAN_TI1R_EXID 0x001FFFF8U
1885 #define CAN_TI1R_STID 0xFFE00000U
1887 /******************* Bit definition for CAN_TDT1R register ******************/
1888 #define CAN_TDT1R_DLC 0x0000000FU
1889 #define CAN_TDT1R_TGT 0x00000100U
1890 #define CAN_TDT1R_TIME 0xFFFF0000U
1892 /******************* Bit definition for CAN_TDL1R register ******************/
1893 #define CAN_TDL1R_DATA0 0x000000FFU
1894 #define CAN_TDL1R_DATA1 0x0000FF00U
1895 #define CAN_TDL1R_DATA2 0x00FF0000U
1896 #define CAN_TDL1R_DATA3 0xFF000000U
1898 /******************* Bit definition for CAN_TDH1R register ******************/
1899 #define CAN_TDH1R_DATA4 0x000000FFU
1900 #define CAN_TDH1R_DATA5 0x0000FF00U
1901 #define CAN_TDH1R_DATA6 0x00FF0000U
1902 #define CAN_TDH1R_DATA7 0xFF000000U
1904 /******************* Bit definition for CAN_TI2R register *******************/
1905 #define CAN_TI2R_TXRQ 0x00000001U
1906 #define CAN_TI2R_RTR 0x00000002U
1907 #define CAN_TI2R_IDE 0x00000004U
1908 #define CAN_TI2R_EXID 0x001FFFF8U
1909 #define CAN_TI2R_STID 0xFFE00000U
1911 /******************* Bit definition for CAN_TDT2R register ******************/
1912 #define CAN_TDT2R_DLC 0x0000000FU
1913 #define CAN_TDT2R_TGT 0x00000100U
1914 #define CAN_TDT2R_TIME 0xFFFF0000U
1916 /******************* Bit definition for CAN_TDL2R register ******************/
1917 #define CAN_TDL2R_DATA0 0x000000FFU
1918 #define CAN_TDL2R_DATA1 0x0000FF00U
1919 #define CAN_TDL2R_DATA2 0x00FF0000U
1920 #define CAN_TDL2R_DATA3 0xFF000000U
1922 /******************* Bit definition for CAN_TDH2R register ******************/
1923 #define CAN_TDH2R_DATA4 0x000000FFU
1924 #define CAN_TDH2R_DATA5 0x0000FF00U
1925 #define CAN_TDH2R_DATA6 0x00FF0000U
1926 #define CAN_TDH2R_DATA7 0xFF000000U
1928 /******************* Bit definition for CAN_RI0R register *******************/
1929 #define CAN_RI0R_RTR 0x00000002U
1930 #define CAN_RI0R_IDE 0x00000004U
1931 #define CAN_RI0R_EXID 0x001FFFF8U
1932 #define CAN_RI0R_STID 0xFFE00000U
1934 /******************* Bit definition for CAN_RDT0R register ******************/
1935 #define CAN_RDT0R_DLC 0x0000000FU
1936 #define CAN_RDT0R_FMI 0x0000FF00U
1937 #define CAN_RDT0R_TIME 0xFFFF0000U
1939 /******************* Bit definition for CAN_RDL0R register ******************/
1940 #define CAN_RDL0R_DATA0 0x000000FFU
1941 #define CAN_RDL0R_DATA1 0x0000FF00U
1942 #define CAN_RDL0R_DATA2 0x00FF0000U
1943 #define CAN_RDL0R_DATA3 0xFF000000U
1945 /******************* Bit definition for CAN_RDH0R register ******************/
1946 #define CAN_RDH0R_DATA4 0x000000FFU
1947 #define CAN_RDH0R_DATA5 0x0000FF00U
1948 #define CAN_RDH0R_DATA6 0x00FF0000U
1949 #define CAN_RDH0R_DATA7 0xFF000000U
1951 /******************* Bit definition for CAN_RI1R register *******************/
1952 #define CAN_RI1R_RTR 0x00000002U
1953 #define CAN_RI1R_IDE 0x00000004U
1954 #define CAN_RI1R_EXID 0x001FFFF8U
1955 #define CAN_RI1R_STID 0xFFE00000U
1957 /******************* Bit definition for CAN_RDT1R register ******************/
1958 #define CAN_RDT1R_DLC 0x0000000FU
1959 #define CAN_RDT1R_FMI 0x0000FF00U
1960 #define CAN_RDT1R_TIME 0xFFFF0000U
1962 /******************* Bit definition for CAN_RDL1R register ******************/
1963 #define CAN_RDL1R_DATA0 0x000000FFU
1964 #define CAN_RDL1R_DATA1 0x0000FF00U
1965 #define CAN_RDL1R_DATA2 0x00FF0000U
1966 #define CAN_RDL1R_DATA3 0xFF000000U
1968 /******************* Bit definition for CAN_RDH1R register ******************/
1969 #define CAN_RDH1R_DATA4 0x000000FFU
1970 #define CAN_RDH1R_DATA5 0x0000FF00U
1971 #define CAN_RDH1R_DATA6 0x00FF0000U
1972 #define CAN_RDH1R_DATA7 0xFF000000U
1975 /******************* Bit definition for CAN_FMR register ********************/
1976 #define CAN_FMR_FINIT ((uint8_t)0x01U)
1977 #define CAN_FMR_CAN2SB 0x00003F00U
1979 /******************* Bit definition for CAN_FM1R register *******************/
1980 #define CAN_FM1R_FBM 0x3FFFU
1981 #define CAN_FM1R_FBM0 0x0001U
1982 #define CAN_FM1R_FBM1 0x0002U
1983 #define CAN_FM1R_FBM2 0x0004U
1984 #define CAN_FM1R_FBM3 0x0008U
1985 #define CAN_FM1R_FBM4 0x0010U
1986 #define CAN_FM1R_FBM5 0x0020U
1987 #define CAN_FM1R_FBM6 0x0040U
1988 #define CAN_FM1R_FBM7 0x0080U
1989 #define CAN_FM1R_FBM8 0x0100U
1990 #define CAN_FM1R_FBM9 0x0200U
1991 #define CAN_FM1R_FBM10 0x0400U
1992 #define CAN_FM1R_FBM11 0x0800U
1993 #define CAN_FM1R_FBM12 0x1000U
1994 #define CAN_FM1R_FBM13 0x2000U
1996 /******************* Bit definition for CAN_FS1R register *******************/
1997 #define CAN_FS1R_FSC 0x00003FFFU
1998 #define CAN_FS1R_FSC0 0x00000001U
1999 #define CAN_FS1R_FSC1 0x00000002U
2000 #define CAN_FS1R_FSC2 0x00000004U
2001 #define CAN_FS1R_FSC3 0x00000008U
2002 #define CAN_FS1R_FSC4 0x00000010U
2003 #define CAN_FS1R_FSC5 0x00000020U
2004 #define CAN_FS1R_FSC6 0x00000040U
2005 #define CAN_FS1R_FSC7 0x00000080U
2006 #define CAN_FS1R_FSC8 0x00000100U
2007 #define CAN_FS1R_FSC9 0x00000200U
2008 #define CAN_FS1R_FSC10 0x00000400U
2009 #define CAN_FS1R_FSC11 0x00000800U
2010 #define CAN_FS1R_FSC12 0x00001000U
2011 #define CAN_FS1R_FSC13 0x00002000U
2013 /****************** Bit definition for CAN_FFA1R register *******************/
2014 #define CAN_FFA1R_FFA 0x00003FFFU
2015 #define CAN_FFA1R_FFA0 0x00000001U
2016 #define CAN_FFA1R_FFA1 0x00000002U
2017 #define CAN_FFA1R_FFA2 0x00000004U
2018 #define CAN_FFA1R_FFA3 0x00000008U
2019 #define CAN_FFA1R_FFA4 0x00000010U
2020 #define CAN_FFA1R_FFA5 0x00000020U
2021 #define CAN_FFA1R_FFA6 0x00000040U
2022 #define CAN_FFA1R_FFA7 0x00000080U
2023 #define CAN_FFA1R_FFA8 0x00000100U
2024 #define CAN_FFA1R_FFA9 0x00000200U
2025 #define CAN_FFA1R_FFA10 0x00000400U
2026 #define CAN_FFA1R_FFA11 0x00000800U
2027 #define CAN_FFA1R_FFA12 0x00001000U
2028 #define CAN_FFA1R_FFA13 0x00002000U
2030 /******************* Bit definition for CAN_FA1R register *******************/
2031 #define CAN_FA1R_FACT 0x00003FFFU
2032 #define CAN_FA1R_FACT0 0x00000001U
2033 #define CAN_FA1R_FACT1 0x00000002U
2034 #define CAN_FA1R_FACT2 0x00000004U
2035 #define CAN_FA1R_FACT3 0x00000008U
2036 #define CAN_FA1R_FACT4 0x00000010U
2037 #define CAN_FA1R_FACT5 0x00000020U
2038 #define CAN_FA1R_FACT6 0x00000040U
2039 #define CAN_FA1R_FACT7 0x00000080U
2040 #define CAN_FA1R_FACT8 0x00000100U
2041 #define CAN_FA1R_FACT9 0x00000200U
2042 #define CAN_FA1R_FACT10 0x00000400U
2043 #define CAN_FA1R_FACT11 0x00000800U
2044 #define CAN_FA1R_FACT12 0x00001000U
2045 #define CAN_FA1R_FACT13 0x00002000U
2047 /******************* Bit definition for CAN_F0R1 register *******************/
2048 #define CAN_F0R1_FB0 0x00000001U
2049 #define CAN_F0R1_FB1 0x00000002U
2050 #define CAN_F0R1_FB2 0x00000004U
2051 #define CAN_F0R1_FB3 0x00000008U
2052 #define CAN_F0R1_FB4 0x00000010U
2053 #define CAN_F0R1_FB5 0x00000020U
2054 #define CAN_F0R1_FB6 0x00000040U
2055 #define CAN_F0R1_FB7 0x00000080U
2056 #define CAN_F0R1_FB8 0x00000100U
2057 #define CAN_F0R1_FB9 0x00000200U
2058 #define CAN_F0R1_FB10 0x00000400U
2059 #define CAN_F0R1_FB11 0x00000800U
2060 #define CAN_F0R1_FB12 0x00001000U
2061 #define CAN_F0R1_FB13 0x00002000U
2062 #define CAN_F0R1_FB14 0x00004000U
2063 #define CAN_F0R1_FB15 0x00008000U
2064 #define CAN_F0R1_FB16 0x00010000U
2065 #define CAN_F0R1_FB17 0x00020000U
2066 #define CAN_F0R1_FB18 0x00040000U
2067 #define CAN_F0R1_FB19 0x00080000U
2068 #define CAN_F0R1_FB20 0x00100000U
2069 #define CAN_F0R1_FB21 0x00200000U
2070 #define CAN_F0R1_FB22 0x00400000U
2071 #define CAN_F0R1_FB23 0x00800000U
2072 #define CAN_F0R1_FB24 0x01000000U
2073 #define CAN_F0R1_FB25 0x02000000U
2074 #define CAN_F0R1_FB26 0x04000000U
2075 #define CAN_F0R1_FB27 0x08000000U
2076 #define CAN_F0R1_FB28 0x10000000U
2077 #define CAN_F0R1_FB29 0x20000000U
2078 #define CAN_F0R1_FB30 0x40000000U
2079 #define CAN_F0R1_FB31 0x80000000U
2081 /******************* Bit definition for CAN_F1R1 register *******************/
2082 #define CAN_F1R1_FB0 0x00000001U
2083 #define CAN_F1R1_FB1 0x00000002U
2084 #define CAN_F1R1_FB2 0x00000004U
2085 #define CAN_F1R1_FB3 0x00000008U
2086 #define CAN_F1R1_FB4 0x00000010U
2087 #define CAN_F1R1_FB5 0x00000020U
2088 #define CAN_F1R1_FB6 0x00000040U
2089 #define CAN_F1R1_FB7 0x00000080U
2090 #define CAN_F1R1_FB8 0x00000100U
2091 #define CAN_F1R1_FB9 0x00000200U
2092 #define CAN_F1R1_FB10 0x00000400U
2093 #define CAN_F1R1_FB11 0x00000800U
2094 #define CAN_F1R1_FB12 0x00001000U
2095 #define CAN_F1R1_FB13 0x00002000U
2096 #define CAN_F1R1_FB14 0x00004000U
2097 #define CAN_F1R1_FB15 0x00008000U
2098 #define CAN_F1R1_FB16 0x00010000U
2099 #define CAN_F1R1_FB17 0x00020000U
2100 #define CAN_F1R1_FB18 0x00040000U
2101 #define CAN_F1R1_FB19 0x00080000U
2102 #define CAN_F1R1_FB20 0x00100000U
2103 #define CAN_F1R1_FB21 0x00200000U
2104 #define CAN_F1R1_FB22 0x00400000U
2105 #define CAN_F1R1_FB23 0x00800000U
2106 #define CAN_F1R1_FB24 0x01000000U
2107 #define CAN_F1R1_FB25 0x02000000U
2108 #define CAN_F1R1_FB26 0x04000000U
2109 #define CAN_F1R1_FB27 0x08000000U
2110 #define CAN_F1R1_FB28 0x10000000U
2111 #define CAN_F1R1_FB29 0x20000000U
2112 #define CAN_F1R1_FB30 0x40000000U
2113 #define CAN_F1R1_FB31 0x80000000U
2115 /******************* Bit definition for CAN_F2R1 register *******************/
2116 #define CAN_F2R1_FB0 0x00000001U
2117 #define CAN_F2R1_FB1 0x00000002U
2118 #define CAN_F2R1_FB2 0x00000004U
2119 #define CAN_F2R1_FB3 0x00000008U
2120 #define CAN_F2R1_FB4 0x00000010U
2121 #define CAN_F2R1_FB5 0x00000020U
2122 #define CAN_F2R1_FB6 0x00000040U
2123 #define CAN_F2R1_FB7 0x00000080U
2124 #define CAN_F2R1_FB8 0x00000100U
2125 #define CAN_F2R1_FB9 0x00000200U
2126 #define CAN_F2R1_FB10 0x00000400U
2127 #define CAN_F2R1_FB11 0x00000800U
2128 #define CAN_F2R1_FB12 0x00001000U
2129 #define CAN_F2R1_FB13 0x00002000U
2130 #define CAN_F2R1_FB14 0x00004000U
2131 #define CAN_F2R1_FB15 0x00008000U
2132 #define CAN_F2R1_FB16 0x00010000U
2133 #define CAN_F2R1_FB17 0x00020000U
2134 #define CAN_F2R1_FB18 0x00040000U
2135 #define CAN_F2R1_FB19 0x00080000U
2136 #define CAN_F2R1_FB20 0x00100000U
2137 #define CAN_F2R1_FB21 0x00200000U
2138 #define CAN_F2R1_FB22 0x00400000U
2139 #define CAN_F2R1_FB23 0x00800000U
2140 #define CAN_F2R1_FB24 0x01000000U
2141 #define CAN_F2R1_FB25 0x02000000U
2142 #define CAN_F2R1_FB26 0x04000000U
2143 #define CAN_F2R1_FB27 0x08000000U
2144 #define CAN_F2R1_FB28 0x10000000U
2145 #define CAN_F2R1_FB29 0x20000000U
2146 #define CAN_F2R1_FB30 0x40000000U
2147 #define CAN_F2R1_FB31 0x80000000U
2149 /******************* Bit definition for CAN_F3R1 register *******************/
2150 #define CAN_F3R1_FB0 0x00000001U
2151 #define CAN_F3R1_FB1 0x00000002U
2152 #define CAN_F3R1_FB2 0x00000004U
2153 #define CAN_F3R1_FB3 0x00000008U
2154 #define CAN_F3R1_FB4 0x00000010U
2155 #define CAN_F3R1_FB5 0x00000020U
2156 #define CAN_F3R1_FB6 0x00000040U
2157 #define CAN_F3R1_FB7 0x00000080U
2158 #define CAN_F3R1_FB8 0x00000100U
2159 #define CAN_F3R1_FB9 0x00000200U
2160 #define CAN_F3R1_FB10 0x00000400U
2161 #define CAN_F3R1_FB11 0x00000800U
2162 #define CAN_F3R1_FB12 0x00001000U
2163 #define CAN_F3R1_FB13 0x00002000U
2164 #define CAN_F3R1_FB14 0x00004000U
2165 #define CAN_F3R1_FB15 0x00008000U
2166 #define CAN_F3R1_FB16 0x00010000U
2167 #define CAN_F3R1_FB17 0x00020000U
2168 #define CAN_F3R1_FB18 0x00040000U
2169 #define CAN_F3R1_FB19 0x00080000U
2170 #define CAN_F3R1_FB20 0x00100000U
2171 #define CAN_F3R1_FB21 0x00200000U
2172 #define CAN_F3R1_FB22 0x00400000U
2173 #define CAN_F3R1_FB23 0x00800000U
2174 #define CAN_F3R1_FB24 0x01000000U
2175 #define CAN_F3R1_FB25 0x02000000U
2176 #define CAN_F3R1_FB26 0x04000000U
2177 #define CAN_F3R1_FB27 0x08000000U
2178 #define CAN_F3R1_FB28 0x10000000U
2179 #define CAN_F3R1_FB29 0x20000000U
2180 #define CAN_F3R1_FB30 0x40000000U
2181 #define CAN_F3R1_FB31 0x80000000U
2183 /******************* Bit definition for CAN_F4R1 register *******************/
2184 #define CAN_F4R1_FB0 0x00000001U
2185 #define CAN_F4R1_FB1 0x00000002U
2186 #define CAN_F4R1_FB2 0x00000004U
2187 #define CAN_F4R1_FB3 0x00000008U
2188 #define CAN_F4R1_FB4 0x00000010U
2189 #define CAN_F4R1_FB5 0x00000020U
2190 #define CAN_F4R1_FB6 0x00000040U
2191 #define CAN_F4R1_FB7 0x00000080U
2192 #define CAN_F4R1_FB8 0x00000100U
2193 #define CAN_F4R1_FB9 0x00000200U
2194 #define CAN_F4R1_FB10 0x00000400U
2195 #define CAN_F4R1_FB11 0x00000800U
2196 #define CAN_F4R1_FB12 0x00001000U
2197 #define CAN_F4R1_FB13 0x00002000U
2198 #define CAN_F4R1_FB14 0x00004000U
2199 #define CAN_F4R1_FB15 0x00008000U
2200 #define CAN_F4R1_FB16 0x00010000U
2201 #define CAN_F4R1_FB17 0x00020000U
2202 #define CAN_F4R1_FB18 0x00040000U
2203 #define CAN_F4R1_FB19 0x00080000U
2204 #define CAN_F4R1_FB20 0x00100000U
2205 #define CAN_F4R1_FB21 0x00200000U
2206 #define CAN_F4R1_FB22 0x00400000U
2207 #define CAN_F4R1_FB23 0x00800000U
2208 #define CAN_F4R1_FB24 0x01000000U
2209 #define CAN_F4R1_FB25 0x02000000U
2210 #define CAN_F4R1_FB26 0x04000000U
2211 #define CAN_F4R1_FB27 0x08000000U
2212 #define CAN_F4R1_FB28 0x10000000U
2213 #define CAN_F4R1_FB29 0x20000000U
2214 #define CAN_F4R1_FB30 0x40000000U
2215 #define CAN_F4R1_FB31 0x80000000U
2217 /******************* Bit definition for CAN_F5R1 register *******************/
2218 #define CAN_F5R1_FB0 0x00000001U
2219 #define CAN_F5R1_FB1 0x00000002U
2220 #define CAN_F5R1_FB2 0x00000004U
2221 #define CAN_F5R1_FB3 0x00000008U
2222 #define CAN_F5R1_FB4 0x00000010U
2223 #define CAN_F5R1_FB5 0x00000020U
2224 #define CAN_F5R1_FB6 0x00000040U
2225 #define CAN_F5R1_FB7 0x00000080U
2226 #define CAN_F5R1_FB8 0x00000100U
2227 #define CAN_F5R1_FB9 0x00000200U
2228 #define CAN_F5R1_FB10 0x00000400U
2229 #define CAN_F5R1_FB11 0x00000800U
2230 #define CAN_F5R1_FB12 0x00001000U
2231 #define CAN_F5R1_FB13 0x00002000U
2232 #define CAN_F5R1_FB14 0x00004000U
2233 #define CAN_F5R1_FB15 0x00008000U
2234 #define CAN_F5R1_FB16 0x00010000U
2235 #define CAN_F5R1_FB17 0x00020000U
2236 #define CAN_F5R1_FB18 0x00040000U
2237 #define CAN_F5R1_FB19 0x00080000U
2238 #define CAN_F5R1_FB20 0x00100000U
2239 #define CAN_F5R1_FB21 0x00200000U
2240 #define CAN_F5R1_FB22 0x00400000U
2241 #define CAN_F5R1_FB23 0x00800000U
2242 #define CAN_F5R1_FB24 0x01000000U
2243 #define CAN_F5R1_FB25 0x02000000U
2244 #define CAN_F5R1_FB26 0x04000000U
2245 #define CAN_F5R1_FB27 0x08000000U
2246 #define CAN_F5R1_FB28 0x10000000U
2247 #define CAN_F5R1_FB29 0x20000000U
2248 #define CAN_F5R1_FB30 0x40000000U
2249 #define CAN_F5R1_FB31 0x80000000U
2251 /******************* Bit definition for CAN_F6R1 register *******************/
2252 #define CAN_F6R1_FB0 0x00000001U
2253 #define CAN_F6R1_FB1 0x00000002U
2254 #define CAN_F6R1_FB2 0x00000004U
2255 #define CAN_F6R1_FB3 0x00000008U
2256 #define CAN_F6R1_FB4 0x00000010U
2257 #define CAN_F6R1_FB5 0x00000020U
2258 #define CAN_F6R1_FB6 0x00000040U
2259 #define CAN_F6R1_FB7 0x00000080U
2260 #define CAN_F6R1_FB8 0x00000100U
2261 #define CAN_F6R1_FB9 0x00000200U
2262 #define CAN_F6R1_FB10 0x00000400U
2263 #define CAN_F6R1_FB11 0x00000800U
2264 #define CAN_F6R1_FB12 0x00001000U
2265 #define CAN_F6R1_FB13 0x00002000U
2266 #define CAN_F6R1_FB14 0x00004000U
2267 #define CAN_F6R1_FB15 0x00008000U
2268 #define CAN_F6R1_FB16 0x00010000U
2269 #define CAN_F6R1_FB17 0x00020000U
2270 #define CAN_F6R1_FB18 0x00040000U
2271 #define CAN_F6R1_FB19 0x00080000U
2272 #define CAN_F6R1_FB20 0x00100000U
2273 #define CAN_F6R1_FB21 0x00200000U
2274 #define CAN_F6R1_FB22 0x00400000U
2275 #define CAN_F6R1_FB23 0x00800000U
2276 #define CAN_F6R1_FB24 0x01000000U
2277 #define CAN_F6R1_FB25 0x02000000U
2278 #define CAN_F6R1_FB26 0x04000000U
2279 #define CAN_F6R1_FB27 0x08000000U
2280 #define CAN_F6R1_FB28 0x10000000U
2281 #define CAN_F6R1_FB29 0x20000000U
2282 #define CAN_F6R1_FB30 0x40000000U
2283 #define CAN_F6R1_FB31 0x80000000U
2285 /******************* Bit definition for CAN_F7R1 register *******************/
2286 #define CAN_F7R1_FB0 0x00000001U
2287 #define CAN_F7R1_FB1 0x00000002U
2288 #define CAN_F7R1_FB2 0x00000004U
2289 #define CAN_F7R1_FB3 0x00000008U
2290 #define CAN_F7R1_FB4 0x00000010U
2291 #define CAN_F7R1_FB5 0x00000020U
2292 #define CAN_F7R1_FB6 0x00000040U
2293 #define CAN_F7R1_FB7 0x00000080U
2294 #define CAN_F7R1_FB8 0x00000100U
2295 #define CAN_F7R1_FB9 0x00000200U
2296 #define CAN_F7R1_FB10 0x00000400U
2297 #define CAN_F7R1_FB11 0x00000800U
2298 #define CAN_F7R1_FB12 0x00001000U
2299 #define CAN_F7R1_FB13 0x00002000U
2300 #define CAN_F7R1_FB14 0x00004000U
2301 #define CAN_F7R1_FB15 0x00008000U
2302 #define CAN_F7R1_FB16 0x00010000U
2303 #define CAN_F7R1_FB17 0x00020000U
2304 #define CAN_F7R1_FB18 0x00040000U
2305 #define CAN_F7R1_FB19 0x00080000U
2306 #define CAN_F7R1_FB20 0x00100000U
2307 #define CAN_F7R1_FB21 0x00200000U
2308 #define CAN_F7R1_FB22 0x00400000U
2309 #define CAN_F7R1_FB23 0x00800000U
2310 #define CAN_F7R1_FB24 0x01000000U
2311 #define CAN_F7R1_FB25 0x02000000U
2312 #define CAN_F7R1_FB26 0x04000000U
2313 #define CAN_F7R1_FB27 0x08000000U
2314 #define CAN_F7R1_FB28 0x10000000U
2315 #define CAN_F7R1_FB29 0x20000000U
2316 #define CAN_F7R1_FB30 0x40000000U
2317 #define CAN_F7R1_FB31 0x80000000U
2319 /******************* Bit definition for CAN_F8R1 register *******************/
2320 #define CAN_F8R1_FB0 0x00000001U
2321 #define CAN_F8R1_FB1 0x00000002U
2322 #define CAN_F8R1_FB2 0x00000004U
2323 #define CAN_F8R1_FB3 0x00000008U
2324 #define CAN_F8R1_FB4 0x00000010U
2325 #define CAN_F8R1_FB5 0x00000020U
2326 #define CAN_F8R1_FB6 0x00000040U
2327 #define CAN_F8R1_FB7 0x00000080U
2328 #define CAN_F8R1_FB8 0x00000100U
2329 #define CAN_F8R1_FB9 0x00000200U
2330 #define CAN_F8R1_FB10 0x00000400U
2331 #define CAN_F8R1_FB11 0x00000800U
2332 #define CAN_F8R1_FB12 0x00001000U
2333 #define CAN_F8R1_FB13 0x00002000U
2334 #define CAN_F8R1_FB14 0x00004000U
2335 #define CAN_F8R1_FB15 0x00008000U
2336 #define CAN_F8R1_FB16 0x00010000U
2337 #define CAN_F8R1_FB17 0x00020000U
2338 #define CAN_F8R1_FB18 0x00040000U
2339 #define CAN_F8R1_FB19 0x00080000U
2340 #define CAN_F8R1_FB20 0x00100000U
2341 #define CAN_F8R1_FB21 0x00200000U
2342 #define CAN_F8R1_FB22 0x00400000U
2343 #define CAN_F8R1_FB23 0x00800000U
2344 #define CAN_F8R1_FB24 0x01000000U
2345 #define CAN_F8R1_FB25 0x02000000U
2346 #define CAN_F8R1_FB26 0x04000000U
2347 #define CAN_F8R1_FB27 0x08000000U
2348 #define CAN_F8R1_FB28 0x10000000U
2349 #define CAN_F8R1_FB29 0x20000000U
2350 #define CAN_F8R1_FB30 0x40000000U
2351 #define CAN_F8R1_FB31 0x80000000U
2353 /******************* Bit definition for CAN_F9R1 register *******************/
2354 #define CAN_F9R1_FB0 0x00000001U
2355 #define CAN_F9R1_FB1 0x00000002U
2356 #define CAN_F9R1_FB2 0x00000004U
2357 #define CAN_F9R1_FB3 0x00000008U
2358 #define CAN_F9R1_FB4 0x00000010U
2359 #define CAN_F9R1_FB5 0x00000020U
2360 #define CAN_F9R1_FB6 0x00000040U
2361 #define CAN_F9R1_FB7 0x00000080U
2362 #define CAN_F9R1_FB8 0x00000100U
2363 #define CAN_F9R1_FB9 0x00000200U
2364 #define CAN_F9R1_FB10 0x00000400U
2365 #define CAN_F9R1_FB11 0x00000800U
2366 #define CAN_F9R1_FB12 0x00001000U
2367 #define CAN_F9R1_FB13 0x00002000U
2368 #define CAN_F9R1_FB14 0x00004000U
2369 #define CAN_F9R1_FB15 0x00008000U
2370 #define CAN_F9R1_FB16 0x00010000U
2371 #define CAN_F9R1_FB17 0x00020000U
2372 #define CAN_F9R1_FB18 0x00040000U
2373 #define CAN_F9R1_FB19 0x00080000U
2374 #define CAN_F9R1_FB20 0x00100000U
2375 #define CAN_F9R1_FB21 0x00200000U
2376 #define CAN_F9R1_FB22 0x00400000U
2377 #define CAN_F9R1_FB23 0x00800000U
2378 #define CAN_F9R1_FB24 0x01000000U
2379 #define CAN_F9R1_FB25 0x02000000U
2380 #define CAN_F9R1_FB26 0x04000000U
2381 #define CAN_F9R1_FB27 0x08000000U
2382 #define CAN_F9R1_FB28 0x10000000U
2383 #define CAN_F9R1_FB29 0x20000000U
2384 #define CAN_F9R1_FB30 0x40000000U
2385 #define CAN_F9R1_FB31 0x80000000U
2387 /******************* Bit definition for CAN_F10R1 register ******************/
2388 #define CAN_F10R1_FB0 0x00000001U
2389 #define CAN_F10R1_FB1 0x00000002U
2390 #define CAN_F10R1_FB2 0x00000004U
2391 #define CAN_F10R1_FB3 0x00000008U
2392 #define CAN_F10R1_FB4 0x00000010U
2393 #define CAN_F10R1_FB5 0x00000020U
2394 #define CAN_F10R1_FB6 0x00000040U
2395 #define CAN_F10R1_FB7 0x00000080U
2396 #define CAN_F10R1_FB8 0x00000100U
2397 #define CAN_F10R1_FB9 0x00000200U
2398 #define CAN_F10R1_FB10 0x00000400U
2399 #define CAN_F10R1_FB11 0x00000800U
2400 #define CAN_F10R1_FB12 0x00001000U
2401 #define CAN_F10R1_FB13 0x00002000U
2402 #define CAN_F10R1_FB14 0x00004000U
2403 #define CAN_F10R1_FB15 0x00008000U
2404 #define CAN_F10R1_FB16 0x00010000U
2405 #define CAN_F10R1_FB17 0x00020000U
2406 #define CAN_F10R1_FB18 0x00040000U
2407 #define CAN_F10R1_FB19 0x00080000U
2408 #define CAN_F10R1_FB20 0x00100000U
2409 #define CAN_F10R1_FB21 0x00200000U
2410 #define CAN_F10R1_FB22 0x00400000U
2411 #define CAN_F10R1_FB23 0x00800000U
2412 #define CAN_F10R1_FB24 0x01000000U
2413 #define CAN_F10R1_FB25 0x02000000U
2414 #define CAN_F10R1_FB26 0x04000000U
2415 #define CAN_F10R1_FB27 0x08000000U
2416 #define CAN_F10R1_FB28 0x10000000U
2417 #define CAN_F10R1_FB29 0x20000000U
2418 #define CAN_F10R1_FB30 0x40000000U
2419 #define CAN_F10R1_FB31 0x80000000U
2421 /******************* Bit definition for CAN_F11R1 register ******************/
2422 #define CAN_F11R1_FB0 0x00000001U
2423 #define CAN_F11R1_FB1 0x00000002U
2424 #define CAN_F11R1_FB2 0x00000004U
2425 #define CAN_F11R1_FB3 0x00000008U
2426 #define CAN_F11R1_FB4 0x00000010U
2427 #define CAN_F11R1_FB5 0x00000020U
2428 #define CAN_F11R1_FB6 0x00000040U
2429 #define CAN_F11R1_FB7 0x00000080U
2430 #define CAN_F11R1_FB8 0x00000100U
2431 #define CAN_F11R1_FB9 0x00000200U
2432 #define CAN_F11R1_FB10 0x00000400U
2433 #define CAN_F11R1_FB11 0x00000800U
2434 #define CAN_F11R1_FB12 0x00001000U
2435 #define CAN_F11R1_FB13 0x00002000U
2436 #define CAN_F11R1_FB14 0x00004000U
2437 #define CAN_F11R1_FB15 0x00008000U
2438 #define CAN_F11R1_FB16 0x00010000U
2439 #define CAN_F11R1_FB17 0x00020000U
2440 #define CAN_F11R1_FB18 0x00040000U
2441 #define CAN_F11R1_FB19 0x00080000U
2442 #define CAN_F11R1_FB20 0x00100000U
2443 #define CAN_F11R1_FB21 0x00200000U
2444 #define CAN_F11R1_FB22 0x00400000U
2445 #define CAN_F11R1_FB23 0x00800000U
2446 #define CAN_F11R1_FB24 0x01000000U
2447 #define CAN_F11R1_FB25 0x02000000U
2448 #define CAN_F11R1_FB26 0x04000000U
2449 #define CAN_F11R1_FB27 0x08000000U
2450 #define CAN_F11R1_FB28 0x10000000U
2451 #define CAN_F11R1_FB29 0x20000000U
2452 #define CAN_F11R1_FB30 0x40000000U
2453 #define CAN_F11R1_FB31 0x80000000U
2455 /******************* Bit definition for CAN_F12R1 register ******************/
2456 #define CAN_F12R1_FB0 0x00000001U
2457 #define CAN_F12R1_FB1 0x00000002U
2458 #define CAN_F12R1_FB2 0x00000004U
2459 #define CAN_F12R1_FB3 0x00000008U
2460 #define CAN_F12R1_FB4 0x00000010U
2461 #define CAN_F12R1_FB5 0x00000020U
2462 #define CAN_F12R1_FB6 0x00000040U
2463 #define CAN_F12R1_FB7 0x00000080U
2464 #define CAN_F12R1_FB8 0x00000100U
2465 #define CAN_F12R1_FB9 0x00000200U
2466 #define CAN_F12R1_FB10 0x00000400U
2467 #define CAN_F12R1_FB11 0x00000800U
2468 #define CAN_F12R1_FB12 0x00001000U
2469 #define CAN_F12R1_FB13 0x00002000U
2470 #define CAN_F12R1_FB14 0x00004000U
2471 #define CAN_F12R1_FB15 0x00008000U
2472 #define CAN_F12R1_FB16 0x00010000U
2473 #define CAN_F12R1_FB17 0x00020000U
2474 #define CAN_F12R1_FB18 0x00040000U
2475 #define CAN_F12R1_FB19 0x00080000U
2476 #define CAN_F12R1_FB20 0x00100000U
2477 #define CAN_F12R1_FB21 0x00200000U
2478 #define CAN_F12R1_FB22 0x00400000U
2479 #define CAN_F12R1_FB23 0x00800000U
2480 #define CAN_F12R1_FB24 0x01000000U
2481 #define CAN_F12R1_FB25 0x02000000U
2482 #define CAN_F12R1_FB26 0x04000000U
2483 #define CAN_F12R1_FB27 0x08000000U
2484 #define CAN_F12R1_FB28 0x10000000U
2485 #define CAN_F12R1_FB29 0x20000000U
2486 #define CAN_F12R1_FB30 0x40000000U
2487 #define CAN_F12R1_FB31 0x80000000U
2489 /******************* Bit definition for CAN_F13R1 register ******************/
2490 #define CAN_F13R1_FB0 0x00000001U
2491 #define CAN_F13R1_FB1 0x00000002U
2492 #define CAN_F13R1_FB2 0x00000004U
2493 #define CAN_F13R1_FB3 0x00000008U
2494 #define CAN_F13R1_FB4 0x00000010U
2495 #define CAN_F13R1_FB5 0x00000020U
2496 #define CAN_F13R1_FB6 0x00000040U
2497 #define CAN_F13R1_FB7 0x00000080U
2498 #define CAN_F13R1_FB8 0x00000100U
2499 #define CAN_F13R1_FB9 0x00000200U
2500 #define CAN_F13R1_FB10 0x00000400U
2501 #define CAN_F13R1_FB11 0x00000800U
2502 #define CAN_F13R1_FB12 0x00001000U
2503 #define CAN_F13R1_FB13 0x00002000U
2504 #define CAN_F13R1_FB14 0x00004000U
2505 #define CAN_F13R1_FB15 0x00008000U
2506 #define CAN_F13R1_FB16 0x00010000U
2507 #define CAN_F13R1_FB17 0x00020000U
2508 #define CAN_F13R1_FB18 0x00040000U
2509 #define CAN_F13R1_FB19 0x00080000U
2510 #define CAN_F13R1_FB20 0x00100000U
2511 #define CAN_F13R1_FB21 0x00200000U
2512 #define CAN_F13R1_FB22 0x00400000U
2513 #define CAN_F13R1_FB23 0x00800000U
2514 #define CAN_F13R1_FB24 0x01000000U
2515 #define CAN_F13R1_FB25 0x02000000U
2516 #define CAN_F13R1_FB26 0x04000000U
2517 #define CAN_F13R1_FB27 0x08000000U
2518 #define CAN_F13R1_FB28 0x10000000U
2519 #define CAN_F13R1_FB29 0x20000000U
2520 #define CAN_F13R1_FB30 0x40000000U
2521 #define CAN_F13R1_FB31 0x80000000U
2523 /******************* Bit definition for CAN_F0R2 register *******************/
2524 #define CAN_F0R2_FB0 0x00000001U
2525 #define CAN_F0R2_FB1 0x00000002U
2526 #define CAN_F0R2_FB2 0x00000004U
2527 #define CAN_F0R2_FB3 0x00000008U
2528 #define CAN_F0R2_FB4 0x00000010U
2529 #define CAN_F0R2_FB5 0x00000020U
2530 #define CAN_F0R2_FB6 0x00000040U
2531 #define CAN_F0R2_FB7 0x00000080U
2532 #define CAN_F0R2_FB8 0x00000100U
2533 #define CAN_F0R2_FB9 0x00000200U
2534 #define CAN_F0R2_FB10 0x00000400U
2535 #define CAN_F0R2_FB11 0x00000800U
2536 #define CAN_F0R2_FB12 0x00001000U
2537 #define CAN_F0R2_FB13 0x00002000U
2538 #define CAN_F0R2_FB14 0x00004000U
2539 #define CAN_F0R2_FB15 0x00008000U
2540 #define CAN_F0R2_FB16 0x00010000U
2541 #define CAN_F0R2_FB17 0x00020000U
2542 #define CAN_F0R2_FB18 0x00040000U
2543 #define CAN_F0R2_FB19 0x00080000U
2544 #define CAN_F0R2_FB20 0x00100000U
2545 #define CAN_F0R2_FB21 0x00200000U
2546 #define CAN_F0R2_FB22 0x00400000U
2547 #define CAN_F0R2_FB23 0x00800000U
2548 #define CAN_F0R2_FB24 0x01000000U
2549 #define CAN_F0R2_FB25 0x02000000U
2550 #define CAN_F0R2_FB26 0x04000000U
2551 #define CAN_F0R2_FB27 0x08000000U
2552 #define CAN_F0R2_FB28 0x10000000U
2553 #define CAN_F0R2_FB29 0x20000000U
2554 #define CAN_F0R2_FB30 0x40000000U
2555 #define CAN_F0R2_FB31 0x80000000U
2557 /******************* Bit definition for CAN_F1R2 register *******************/
2558 #define CAN_F1R2_FB0 0x00000001U
2559 #define CAN_F1R2_FB1 0x00000002U
2560 #define CAN_F1R2_FB2 0x00000004U
2561 #define CAN_F1R2_FB3 0x00000008U
2562 #define CAN_F1R2_FB4 0x00000010U
2563 #define CAN_F1R2_FB5 0x00000020U
2564 #define CAN_F1R2_FB6 0x00000040U
2565 #define CAN_F1R2_FB7 0x00000080U
2566 #define CAN_F1R2_FB8 0x00000100U
2567 #define CAN_F1R2_FB9 0x00000200U
2568 #define CAN_F1R2_FB10 0x00000400U
2569 #define CAN_F1R2_FB11 0x00000800U
2570 #define CAN_F1R2_FB12 0x00001000U
2571 #define CAN_F1R2_FB13 0x00002000U
2572 #define CAN_F1R2_FB14 0x00004000U
2573 #define CAN_F1R2_FB15 0x00008000U
2574 #define CAN_F1R2_FB16 0x00010000U
2575 #define CAN_F1R2_FB17 0x00020000U
2576 #define CAN_F1R2_FB18 0x00040000U
2577 #define CAN_F1R2_FB19 0x00080000U
2578 #define CAN_F1R2_FB20 0x00100000U
2579 #define CAN_F1R2_FB21 0x00200000U
2580 #define CAN_F1R2_FB22 0x00400000U
2581 #define CAN_F1R2_FB23 0x00800000U
2582 #define CAN_F1R2_FB24 0x01000000U
2583 #define CAN_F1R2_FB25 0x02000000U
2584 #define CAN_F1R2_FB26 0x04000000U
2585 #define CAN_F1R2_FB27 0x08000000U
2586 #define CAN_F1R2_FB28 0x10000000U
2587 #define CAN_F1R2_FB29 0x20000000U
2588 #define CAN_F1R2_FB30 0x40000000U
2589 #define CAN_F1R2_FB31 0x80000000U
2591 /******************* Bit definition for CAN_F2R2 register *******************/
2592 #define CAN_F2R2_FB0 0x00000001U
2593 #define CAN_F2R2_FB1 0x00000002U
2594 #define CAN_F2R2_FB2 0x00000004U
2595 #define CAN_F2R2_FB3 0x00000008U
2596 #define CAN_F2R2_FB4 0x00000010U
2597 #define CAN_F2R2_FB5 0x00000020U
2598 #define CAN_F2R2_FB6 0x00000040U
2599 #define CAN_F2R2_FB7 0x00000080U
2600 #define CAN_F2R2_FB8 0x00000100U
2601 #define CAN_F2R2_FB9 0x00000200U
2602 #define CAN_F2R2_FB10 0x00000400U
2603 #define CAN_F2R2_FB11 0x00000800U
2604 #define CAN_F2R2_FB12 0x00001000U
2605 #define CAN_F2R2_FB13 0x00002000U
2606 #define CAN_F2R2_FB14 0x00004000U
2607 #define CAN_F2R2_FB15 0x00008000U
2608 #define CAN_F2R2_FB16 0x00010000U
2609 #define CAN_F2R2_FB17 0x00020000U
2610 #define CAN_F2R2_FB18 0x00040000U
2611 #define CAN_F2R2_FB19 0x00080000U
2612 #define CAN_F2R2_FB20 0x00100000U
2613 #define CAN_F2R2_FB21 0x00200000U
2614 #define CAN_F2R2_FB22 0x00400000U
2615 #define CAN_F2R2_FB23 0x00800000U
2616 #define CAN_F2R2_FB24 0x01000000U
2617 #define CAN_F2R2_FB25 0x02000000U
2618 #define CAN_F2R2_FB26 0x04000000U
2619 #define CAN_F2R2_FB27 0x08000000U
2620 #define CAN_F2R2_FB28 0x10000000U
2621 #define CAN_F2R2_FB29 0x20000000U
2622 #define CAN_F2R2_FB30 0x40000000U
2623 #define CAN_F2R2_FB31 0x80000000U
2625 /******************* Bit definition for CAN_F3R2 register *******************/
2626 #define CAN_F3R2_FB0 0x00000001U
2627 #define CAN_F3R2_FB1 0x00000002U
2628 #define CAN_F3R2_FB2 0x00000004U
2629 #define CAN_F3R2_FB3 0x00000008U
2630 #define CAN_F3R2_FB4 0x00000010U
2631 #define CAN_F3R2_FB5 0x00000020U
2632 #define CAN_F3R2_FB6 0x00000040U
2633 #define CAN_F3R2_FB7 0x00000080U
2634 #define CAN_F3R2_FB8 0x00000100U
2635 #define CAN_F3R2_FB9 0x00000200U
2636 #define CAN_F3R2_FB10 0x00000400U
2637 #define CAN_F3R2_FB11 0x00000800U
2638 #define CAN_F3R2_FB12 0x00001000U
2639 #define CAN_F3R2_FB13 0x00002000U
2640 #define CAN_F3R2_FB14 0x00004000U
2641 #define CAN_F3R2_FB15 0x00008000U
2642 #define CAN_F3R2_FB16 0x00010000U
2643 #define CAN_F3R2_FB17 0x00020000U
2644 #define CAN_F3R2_FB18 0x00040000U
2645 #define CAN_F3R2_FB19 0x00080000U
2646 #define CAN_F3R2_FB20 0x00100000U
2647 #define CAN_F3R2_FB21 0x00200000U
2648 #define CAN_F3R2_FB22 0x00400000U
2649 #define CAN_F3R2_FB23 0x00800000U
2650 #define CAN_F3R2_FB24 0x01000000U
2651 #define CAN_F3R2_FB25 0x02000000U
2652 #define CAN_F3R2_FB26 0x04000000U
2653 #define CAN_F3R2_FB27 0x08000000U
2654 #define CAN_F3R2_FB28 0x10000000U
2655 #define CAN_F3R2_FB29 0x20000000U
2656 #define CAN_F3R2_FB30 0x40000000U
2657 #define CAN_F3R2_FB31 0x80000000U
2659 /******************* Bit definition for CAN_F4R2 register *******************/
2660 #define CAN_F4R2_FB0 0x00000001U
2661 #define CAN_F4R2_FB1 0x00000002U
2662 #define CAN_F4R2_FB2 0x00000004U
2663 #define CAN_F4R2_FB3 0x00000008U
2664 #define CAN_F4R2_FB4 0x00000010U
2665 #define CAN_F4R2_FB5 0x00000020U
2666 #define CAN_F4R2_FB6 0x00000040U
2667 #define CAN_F4R2_FB7 0x00000080U
2668 #define CAN_F4R2_FB8 0x00000100U
2669 #define CAN_F4R2_FB9 0x00000200U
2670 #define CAN_F4R2_FB10 0x00000400U
2671 #define CAN_F4R2_FB11 0x00000800U
2672 #define CAN_F4R2_FB12 0x00001000U
2673 #define CAN_F4R2_FB13 0x00002000U
2674 #define CAN_F4R2_FB14 0x00004000U
2675 #define CAN_F4R2_FB15 0x00008000U
2676 #define CAN_F4R2_FB16 0x00010000U
2677 #define CAN_F4R2_FB17 0x00020000U
2678 #define CAN_F4R2_FB18 0x00040000U
2679 #define CAN_F4R2_FB19 0x00080000U
2680 #define CAN_F4R2_FB20 0x00100000U
2681 #define CAN_F4R2_FB21 0x00200000U
2682 #define CAN_F4R2_FB22 0x00400000U
2683 #define CAN_F4R2_FB23 0x00800000U
2684 #define CAN_F4R2_FB24 0x01000000U
2685 #define CAN_F4R2_FB25 0x02000000U
2686 #define CAN_F4R2_FB26 0x04000000U
2687 #define CAN_F4R2_FB27 0x08000000U
2688 #define CAN_F4R2_FB28 0x10000000U
2689 #define CAN_F4R2_FB29 0x20000000U
2690 #define CAN_F4R2_FB30 0x40000000U
2691 #define CAN_F4R2_FB31 0x80000000U
2693 /******************* Bit definition for CAN_F5R2 register *******************/
2694 #define CAN_F5R2_FB0 0x00000001U
2695 #define CAN_F5R2_FB1 0x00000002U
2696 #define CAN_F5R2_FB2 0x00000004U
2697 #define CAN_F5R2_FB3 0x00000008U
2698 #define CAN_F5R2_FB4 0x00000010U
2699 #define CAN_F5R2_FB5 0x00000020U
2700 #define CAN_F5R2_FB6 0x00000040U
2701 #define CAN_F5R2_FB7 0x00000080U
2702 #define CAN_F5R2_FB8 0x00000100U
2703 #define CAN_F5R2_FB9 0x00000200U
2704 #define CAN_F5R2_FB10 0x00000400U
2705 #define CAN_F5R2_FB11 0x00000800U
2706 #define CAN_F5R2_FB12 0x00001000U
2707 #define CAN_F5R2_FB13 0x00002000U
2708 #define CAN_F5R2_FB14 0x00004000U
2709 #define CAN_F5R2_FB15 0x00008000U
2710 #define CAN_F5R2_FB16 0x00010000U
2711 #define CAN_F5R2_FB17 0x00020000U
2712 #define CAN_F5R2_FB18 0x00040000U
2713 #define CAN_F5R2_FB19 0x00080000U
2714 #define CAN_F5R2_FB20 0x00100000U
2715 #define CAN_F5R2_FB21 0x00200000U
2716 #define CAN_F5R2_FB22 0x00400000U
2717 #define CAN_F5R2_FB23 0x00800000U
2718 #define CAN_F5R2_FB24 0x01000000U
2719 #define CAN_F5R2_FB25 0x02000000U
2720 #define CAN_F5R2_FB26 0x04000000U
2721 #define CAN_F5R2_FB27 0x08000000U
2722 #define CAN_F5R2_FB28 0x10000000U
2723 #define CAN_F5R2_FB29 0x20000000U
2724 #define CAN_F5R2_FB30 0x40000000U
2725 #define CAN_F5R2_FB31 0x80000000U
2727 /******************* Bit definition for CAN_F6R2 register *******************/
2728 #define CAN_F6R2_FB0 0x00000001U
2729 #define CAN_F6R2_FB1 0x00000002U
2730 #define CAN_F6R2_FB2 0x00000004U
2731 #define CAN_F6R2_FB3 0x00000008U
2732 #define CAN_F6R2_FB4 0x00000010U
2733 #define CAN_F6R2_FB5 0x00000020U
2734 #define CAN_F6R2_FB6 0x00000040U
2735 #define CAN_F6R2_FB7 0x00000080U
2736 #define CAN_F6R2_FB8 0x00000100U
2737 #define CAN_F6R2_FB9 0x00000200U
2738 #define CAN_F6R2_FB10 0x00000400U
2739 #define CAN_F6R2_FB11 0x00000800U
2740 #define CAN_F6R2_FB12 0x00001000U
2741 #define CAN_F6R2_FB13 0x00002000U
2742 #define CAN_F6R2_FB14 0x00004000U
2743 #define CAN_F6R2_FB15 0x00008000U
2744 #define CAN_F6R2_FB16 0x00010000U
2745 #define CAN_F6R2_FB17 0x00020000U
2746 #define CAN_F6R2_FB18 0x00040000U
2747 #define CAN_F6R2_FB19 0x00080000U
2748 #define CAN_F6R2_FB20 0x00100000U
2749 #define CAN_F6R2_FB21 0x00200000U
2750 #define CAN_F6R2_FB22 0x00400000U
2751 #define CAN_F6R2_FB23 0x00800000U
2752 #define CAN_F6R2_FB24 0x01000000U
2753 #define CAN_F6R2_FB25 0x02000000U
2754 #define CAN_F6R2_FB26 0x04000000U
2755 #define CAN_F6R2_FB27 0x08000000U
2756 #define CAN_F6R2_FB28 0x10000000U
2757 #define CAN_F6R2_FB29 0x20000000U
2758 #define CAN_F6R2_FB30 0x40000000U
2759 #define CAN_F6R2_FB31 0x80000000U
2761 /******************* Bit definition for CAN_F7R2 register *******************/
2762 #define CAN_F7R2_FB0 0x00000001U
2763 #define CAN_F7R2_FB1 0x00000002U
2764 #define CAN_F7R2_FB2 0x00000004U
2765 #define CAN_F7R2_FB3 0x00000008U
2766 #define CAN_F7R2_FB4 0x00000010U
2767 #define CAN_F7R2_FB5 0x00000020U
2768 #define CAN_F7R2_FB6 0x00000040U
2769 #define CAN_F7R2_FB7 0x00000080U
2770 #define CAN_F7R2_FB8 0x00000100U
2771 #define CAN_F7R2_FB9 0x00000200U
2772 #define CAN_F7R2_FB10 0x00000400U
2773 #define CAN_F7R2_FB11 0x00000800U
2774 #define CAN_F7R2_FB12 0x00001000U
2775 #define CAN_F7R2_FB13 0x00002000U
2776 #define CAN_F7R2_FB14 0x00004000U
2777 #define CAN_F7R2_FB15 0x00008000U
2778 #define CAN_F7R2_FB16 0x00010000U
2779 #define CAN_F7R2_FB17 0x00020000U
2780 #define CAN_F7R2_FB18 0x00040000U
2781 #define CAN_F7R2_FB19 0x00080000U
2782 #define CAN_F7R2_FB20 0x00100000U
2783 #define CAN_F7R2_FB21 0x00200000U
2784 #define CAN_F7R2_FB22 0x00400000U
2785 #define CAN_F7R2_FB23 0x00800000U
2786 #define CAN_F7R2_FB24 0x01000000U
2787 #define CAN_F7R2_FB25 0x02000000U
2788 #define CAN_F7R2_FB26 0x04000000U
2789 #define CAN_F7R2_FB27 0x08000000U
2790 #define CAN_F7R2_FB28 0x10000000U
2791 #define CAN_F7R2_FB29 0x20000000U
2792 #define CAN_F7R2_FB30 0x40000000U
2793 #define CAN_F7R2_FB31 0x80000000U
2795 /******************* Bit definition for CAN_F8R2 register *******************/
2796 #define CAN_F8R2_FB0 0x00000001U
2797 #define CAN_F8R2_FB1 0x00000002U
2798 #define CAN_F8R2_FB2 0x00000004U
2799 #define CAN_F8R2_FB3 0x00000008U
2800 #define CAN_F8R2_FB4 0x00000010U
2801 #define CAN_F8R2_FB5 0x00000020U
2802 #define CAN_F8R2_FB6 0x00000040U
2803 #define CAN_F8R2_FB7 0x00000080U
2804 #define CAN_F8R2_FB8 0x00000100U
2805 #define CAN_F8R2_FB9 0x00000200U
2806 #define CAN_F8R2_FB10 0x00000400U
2807 #define CAN_F8R2_FB11 0x00000800U
2808 #define CAN_F8R2_FB12 0x00001000U
2809 #define CAN_F8R2_FB13 0x00002000U
2810 #define CAN_F8R2_FB14 0x00004000U
2811 #define CAN_F8R2_FB15 0x00008000U
2812 #define CAN_F8R2_FB16 0x00010000U
2813 #define CAN_F8R2_FB17 0x00020000U
2814 #define CAN_F8R2_FB18 0x00040000U
2815 #define CAN_F8R2_FB19 0x00080000U
2816 #define CAN_F8R2_FB20 0x00100000U
2817 #define CAN_F8R2_FB21 0x00200000U
2818 #define CAN_F8R2_FB22 0x00400000U
2819 #define CAN_F8R2_FB23 0x00800000U
2820 #define CAN_F8R2_FB24 0x01000000U
2821 #define CAN_F8R2_FB25 0x02000000U
2822 #define CAN_F8R2_FB26 0x04000000U
2823 #define CAN_F8R2_FB27 0x08000000U
2824 #define CAN_F8R2_FB28 0x10000000U
2825 #define CAN_F8R2_FB29 0x20000000U
2826 #define CAN_F8R2_FB30 0x40000000U
2827 #define CAN_F8R2_FB31 0x80000000U
2829 /******************* Bit definition for CAN_F9R2 register *******************/
2830 #define CAN_F9R2_FB0 0x00000001U
2831 #define CAN_F9R2_FB1 0x00000002U
2832 #define CAN_F9R2_FB2 0x00000004U
2833 #define CAN_F9R2_FB3 0x00000008U
2834 #define CAN_F9R2_FB4 0x00000010U
2835 #define CAN_F9R2_FB5 0x00000020U
2836 #define CAN_F9R2_FB6 0x00000040U
2837 #define CAN_F9R2_FB7 0x00000080U
2838 #define CAN_F9R2_FB8 0x00000100U
2839 #define CAN_F9R2_FB9 0x00000200U
2840 #define CAN_F9R2_FB10 0x00000400U
2841 #define CAN_F9R2_FB11 0x00000800U
2842 #define CAN_F9R2_FB12 0x00001000U
2843 #define CAN_F9R2_FB13 0x00002000U
2844 #define CAN_F9R2_FB14 0x00004000U
2845 #define CAN_F9R2_FB15 0x00008000U
2846 #define CAN_F9R2_FB16 0x00010000U
2847 #define CAN_F9R2_FB17 0x00020000U
2848 #define CAN_F9R2_FB18 0x00040000U
2849 #define CAN_F9R2_FB19 0x00080000U
2850 #define CAN_F9R2_FB20 0x00100000U
2851 #define CAN_F9R2_FB21 0x00200000U
2852 #define CAN_F9R2_FB22 0x00400000U
2853 #define CAN_F9R2_FB23 0x00800000U
2854 #define CAN_F9R2_FB24 0x01000000U
2855 #define CAN_F9R2_FB25 0x02000000U
2856 #define CAN_F9R2_FB26 0x04000000U
2857 #define CAN_F9R2_FB27 0x08000000U
2858 #define CAN_F9R2_FB28 0x10000000U
2859 #define CAN_F9R2_FB29 0x20000000U
2860 #define CAN_F9R2_FB30 0x40000000U
2861 #define CAN_F9R2_FB31 0x80000000U
2863 /******************* Bit definition for CAN_F10R2 register ******************/
2864 #define CAN_F10R2_FB0 0x00000001U
2865 #define CAN_F10R2_FB1 0x00000002U
2866 #define CAN_F10R2_FB2 0x00000004U
2867 #define CAN_F10R2_FB3 0x00000008U
2868 #define CAN_F10R2_FB4 0x00000010U
2869 #define CAN_F10R2_FB5 0x00000020U
2870 #define CAN_F10R2_FB6 0x00000040U
2871 #define CAN_F10R2_FB7 0x00000080U
2872 #define CAN_F10R2_FB8 0x00000100U
2873 #define CAN_F10R2_FB9 0x00000200U
2874 #define CAN_F10R2_FB10 0x00000400U
2875 #define CAN_F10R2_FB11 0x00000800U
2876 #define CAN_F10R2_FB12 0x00001000U
2877 #define CAN_F10R2_FB13 0x00002000U
2878 #define CAN_F10R2_FB14 0x00004000U
2879 #define CAN_F10R2_FB15 0x00008000U
2880 #define CAN_F10R2_FB16 0x00010000U
2881 #define CAN_F10R2_FB17 0x00020000U
2882 #define CAN_F10R2_FB18 0x00040000U
2883 #define CAN_F10R2_FB19 0x00080000U
2884 #define CAN_F10R2_FB20 0x00100000U
2885 #define CAN_F10R2_FB21 0x00200000U
2886 #define CAN_F10R2_FB22 0x00400000U
2887 #define CAN_F10R2_FB23 0x00800000U
2888 #define CAN_F10R2_FB24 0x01000000U
2889 #define CAN_F10R2_FB25 0x02000000U
2890 #define CAN_F10R2_FB26 0x04000000U
2891 #define CAN_F10R2_FB27 0x08000000U
2892 #define CAN_F10R2_FB28 0x10000000U
2893 #define CAN_F10R2_FB29 0x20000000U
2894 #define CAN_F10R2_FB30 0x40000000U
2895 #define CAN_F10R2_FB31 0x80000000U
2897 /******************* Bit definition for CAN_F11R2 register ******************/
2898 #define CAN_F11R2_FB0 0x00000001U
2899 #define CAN_F11R2_FB1 0x00000002U
2900 #define CAN_F11R2_FB2 0x00000004U
2901 #define CAN_F11R2_FB3 0x00000008U
2902 #define CAN_F11R2_FB4 0x00000010U
2903 #define CAN_F11R2_FB5 0x00000020U
2904 #define CAN_F11R2_FB6 0x00000040U
2905 #define CAN_F11R2_FB7 0x00000080U
2906 #define CAN_F11R2_FB8 0x00000100U
2907 #define CAN_F11R2_FB9 0x00000200U
2908 #define CAN_F11R2_FB10 0x00000400U
2909 #define CAN_F11R2_FB11 0x00000800U
2910 #define CAN_F11R2_FB12 0x00001000U
2911 #define CAN_F11R2_FB13 0x00002000U
2912 #define CAN_F11R2_FB14 0x00004000U
2913 #define CAN_F11R2_FB15 0x00008000U
2914 #define CAN_F11R2_FB16 0x00010000U
2915 #define CAN_F11R2_FB17 0x00020000U
2916 #define CAN_F11R2_FB18 0x00040000U
2917 #define CAN_F11R2_FB19 0x00080000U
2918 #define CAN_F11R2_FB20 0x00100000U
2919 #define CAN_F11R2_FB21 0x00200000U
2920 #define CAN_F11R2_FB22 0x00400000U
2921 #define CAN_F11R2_FB23 0x00800000U
2922 #define CAN_F11R2_FB24 0x01000000U
2923 #define CAN_F11R2_FB25 0x02000000U
2924 #define CAN_F11R2_FB26 0x04000000U
2925 #define CAN_F11R2_FB27 0x08000000U
2926 #define CAN_F11R2_FB28 0x10000000U
2927 #define CAN_F11R2_FB29 0x20000000U
2928 #define CAN_F11R2_FB30 0x40000000U
2929 #define CAN_F11R2_FB31 0x80000000U
2931 /******************* Bit definition for CAN_F12R2 register ******************/
2932 #define CAN_F12R2_FB0 0x00000001U
2933 #define CAN_F12R2_FB1 0x00000002U
2934 #define CAN_F12R2_FB2 0x00000004U
2935 #define CAN_F12R2_FB3 0x00000008U
2936 #define CAN_F12R2_FB4 0x00000010U
2937 #define CAN_F12R2_FB5 0x00000020U
2938 #define CAN_F12R2_FB6 0x00000040U
2939 #define CAN_F12R2_FB7 0x00000080U
2940 #define CAN_F12R2_FB8 0x00000100U
2941 #define CAN_F12R2_FB9 0x00000200U
2942 #define CAN_F12R2_FB10 0x00000400U
2943 #define CAN_F12R2_FB11 0x00000800U
2944 #define CAN_F12R2_FB12 0x00001000U
2945 #define CAN_F12R2_FB13 0x00002000U
2946 #define CAN_F12R2_FB14 0x00004000U
2947 #define CAN_F12R2_FB15 0x00008000U
2948 #define CAN_F12R2_FB16 0x00010000U
2949 #define CAN_F12R2_FB17 0x00020000U
2950 #define CAN_F12R2_FB18 0x00040000U
2951 #define CAN_F12R2_FB19 0x00080000U
2952 #define CAN_F12R2_FB20 0x00100000U
2953 #define CAN_F12R2_FB21 0x00200000U
2954 #define CAN_F12R2_FB22 0x00400000U
2955 #define CAN_F12R2_FB23 0x00800000U
2956 #define CAN_F12R2_FB24 0x01000000U
2957 #define CAN_F12R2_FB25 0x02000000U
2958 #define CAN_F12R2_FB26 0x04000000U
2959 #define CAN_F12R2_FB27 0x08000000U
2960 #define CAN_F12R2_FB28 0x10000000U
2961 #define CAN_F12R2_FB29 0x20000000U
2962 #define CAN_F12R2_FB30 0x40000000U
2963 #define CAN_F12R2_FB31 0x80000000U
2965 /******************* Bit definition for CAN_F13R2 register ******************/
2966 #define CAN_F13R2_FB0 0x00000001U
2967 #define CAN_F13R2_FB1 0x00000002U
2968 #define CAN_F13R2_FB2 0x00000004U
2969 #define CAN_F13R2_FB3 0x00000008U
2970 #define CAN_F13R2_FB4 0x00000010U
2971 #define CAN_F13R2_FB5 0x00000020U
2972 #define CAN_F13R2_FB6 0x00000040U
2973 #define CAN_F13R2_FB7 0x00000080U
2974 #define CAN_F13R2_FB8 0x00000100U
2975 #define CAN_F13R2_FB9 0x00000200U
2976 #define CAN_F13R2_FB10 0x00000400U
2977 #define CAN_F13R2_FB11 0x00000800U
2978 #define CAN_F13R2_FB12 0x00001000U
2979 #define CAN_F13R2_FB13 0x00002000U
2980 #define CAN_F13R2_FB14 0x00004000U
2981 #define CAN_F13R2_FB15 0x00008000U
2982 #define CAN_F13R2_FB16 0x00010000U
2983 #define CAN_F13R2_FB17 0x00020000U
2984 #define CAN_F13R2_FB18 0x00040000U
2985 #define CAN_F13R2_FB19 0x00080000U
2986 #define CAN_F13R2_FB20 0x00100000U
2987 #define CAN_F13R2_FB21 0x00200000U
2988 #define CAN_F13R2_FB22 0x00400000U
2989 #define CAN_F13R2_FB23 0x00800000U
2990 #define CAN_F13R2_FB24 0x01000000U
2991 #define CAN_F13R2_FB25 0x02000000U
2992 #define CAN_F13R2_FB26 0x04000000U
2993 #define CAN_F13R2_FB27 0x08000000U
2994 #define CAN_F13R2_FB28 0x10000000U
2995 #define CAN_F13R2_FB29 0x20000000U
2996 #define CAN_F13R2_FB30 0x40000000U
2997 #define CAN_F13R2_FB31 0x80000000U
2999 /******************************************************************************/
3000 /* */
3001 /* HDMI-CEC (CEC) */
3002 /* */
3003 /******************************************************************************/
3004 
3005 /******************* Bit definition for CEC_CR register *********************/
3006 #define CEC_CR_CECEN 0x00000001U
3007 #define CEC_CR_TXSOM 0x00000002U
3008 #define CEC_CR_TXEOM 0x00000004U
3010 /******************* Bit definition for CEC_CFGR register *******************/
3011 #define CEC_CFGR_SFT 0x00000007U
3012 #define CEC_CFGR_RXTOL 0x00000008U
3013 #define CEC_CFGR_BRESTP 0x00000010U
3014 #define CEC_CFGR_BREGEN 0x00000020U
3015 #define CEC_CFGR_LBPEGEN 0x00000040U
3016 #define CEC_CFGR_BRDNOGEN 0x00000080U
3017 #define CEC_CFGR_SFTOPT 0x00000100U
3018 #define CEC_CFGR_OAR 0x7FFF0000U
3019 #define CEC_CFGR_LSTN 0x80000000U
3021 /******************* Bit definition for CEC_TXDR register *******************/
3022 #define CEC_TXDR_TXD 0x000000FFU
3024 /******************* Bit definition for CEC_RXDR register *******************/
3025 #define CEC_TXDR_RXD 0x000000FFU
3027 /******************* Bit definition for CEC_ISR register ********************/
3028 #define CEC_ISR_RXBR 0x00000001U
3029 #define CEC_ISR_RXEND 0x00000002U
3030 #define CEC_ISR_RXOVR 0x00000004U
3031 #define CEC_ISR_BRE 0x00000008U
3032 #define CEC_ISR_SBPE 0x00000010U
3033 #define CEC_ISR_LBPE 0x00000020U
3034 #define CEC_ISR_RXACKE 0x00000040U
3035 #define CEC_ISR_ARBLST 0x00000080U
3036 #define CEC_ISR_TXBR 0x00000100U
3037 #define CEC_ISR_TXEND 0x00000200U
3038 #define CEC_ISR_TXUDR 0x00000400U
3039 #define CEC_ISR_TXERR 0x00000800U
3040 #define CEC_ISR_TXACKE 0x00001000U
3042 /******************* Bit definition for CEC_IER register ********************/
3043 #define CEC_IER_RXBRIE 0x00000001U
3044 #define CEC_IER_RXENDIE 0x00000002U
3045 #define CEC_IER_RXOVRIE 0x00000004U
3046 #define CEC_IER_BREIE 0x00000008U
3047 #define CEC_IER_SBPEIE 0x00000010U
3048 #define CEC_IER_LBPEIE 0x00000020U
3049 #define CEC_IER_RXACKEIE 0x00000040U
3050 #define CEC_IER_ARBLSTIE 0x00000080U
3051 #define CEC_IER_TXBRIE 0x00000100U
3052 #define CEC_IER_TXENDIE 0x00000200U
3053 #define CEC_IER_TXUDRIE 0x00000400U
3054 #define CEC_IER_TXERRIE 0x00000800U
3055 #define CEC_IER_TXACKEIE 0x00001000U
3057 /******************************************************************************/
3058 /* */
3059 /* CRC calculation unit */
3060 /* */
3061 /******************************************************************************/
3062 /******************* Bit definition for CRC_DR register *********************/
3063 #define CRC_DR_DR 0xFFFFFFFFU
3065 /******************* Bit definition for CRC_IDR register ********************/
3066 #define CRC_IDR_IDR 0x000000FFU
3068 /******************** Bit definition for CRC_CR register ********************/
3069 #define CRC_CR_RESET 0x00000001U
3070 #define CRC_CR_POLYSIZE 0x00000018U
3071 #define CRC_CR_POLYSIZE_0 0x00000008U
3072 #define CRC_CR_POLYSIZE_1 0x00000010U
3073 #define CRC_CR_REV_IN 0x00000060U
3074 #define CRC_CR_REV_IN_0 0x00000020U
3075 #define CRC_CR_REV_IN_1 0x00000040U
3076 #define CRC_CR_REV_OUT 0x00000080U
3078 /******************* Bit definition for CRC_INIT register *******************/
3079 #define CRC_INIT_INIT 0xFFFFFFFFU
3081 /******************* Bit definition for CRC_POL register ********************/
3082 #define CRC_POL_POL 0xFFFFFFFFU
3085 /******************************************************************************/
3086 /* */
3087 /* Digital to Analog Converter */
3088 /* */
3089 /******************************************************************************/
3090 /******************** Bit definition for DAC_CR register ********************/
3091 #define DAC_CR_EN1 0x00000001U
3092 #define DAC_CR_BOFF1 0x00000002U
3093 #define DAC_CR_TEN1 0x00000004U
3094 #define DAC_CR_TSEL1 0x00000038U
3095 #define DAC_CR_TSEL1_0 0x00000008U
3096 #define DAC_CR_TSEL1_1 0x00000010U
3097 #define DAC_CR_TSEL1_2 0x00000020U
3098 #define DAC_CR_WAVE1 0x000000C0U
3099 #define DAC_CR_WAVE1_0 0x00000040U
3100 #define DAC_CR_WAVE1_1 0x00000080U
3101 #define DAC_CR_MAMP1 0x00000F00U
3102 #define DAC_CR_MAMP1_0 0x00000100U
3103 #define DAC_CR_MAMP1_1 0x00000200U
3104 #define DAC_CR_MAMP1_2 0x00000400U
3105 #define DAC_CR_MAMP1_3 0x00000800U
3106 #define DAC_CR_DMAEN1 0x00001000U
3107 #define DAC_CR_DMAUDRIE1 0x00002000U
3108 #define DAC_CR_EN2 0x00010000U
3109 #define DAC_CR_BOFF2 0x00020000U
3110 #define DAC_CR_TEN2 0x00040000U
3111 #define DAC_CR_TSEL2 0x00380000U
3112 #define DAC_CR_TSEL2_0 0x00080000U
3113 #define DAC_CR_TSEL2_1 0x00100000U
3114 #define DAC_CR_TSEL2_2 0x00200000U
3115 #define DAC_CR_WAVE2 0x00C00000U
3116 #define DAC_CR_WAVE2_0 0x00400000U
3117 #define DAC_CR_WAVE2_1 0x00800000U
3118 #define DAC_CR_MAMP2 0x0F000000U
3119 #define DAC_CR_MAMP2_0 0x01000000U
3120 #define DAC_CR_MAMP2_1 0x02000000U
3121 #define DAC_CR_MAMP2_2 0x04000000U
3122 #define DAC_CR_MAMP2_3 0x08000000U
3123 #define DAC_CR_DMAEN2 0x10000000U
3124 #define DAC_CR_DMAUDRIE2 0x20000000U
3126 /***************** Bit definition for DAC_SWTRIGR register ******************/
3127 #define DAC_SWTRIGR_SWTRIG1 0x01U
3128 #define DAC_SWTRIGR_SWTRIG2 0x02U
3130 /***************** Bit definition for DAC_DHR12R1 register ******************/
3131 #define DAC_DHR12R1_DACC1DHR 0x0FFFU
3133 /***************** Bit definition for DAC_DHR12L1 register ******************/
3134 #define DAC_DHR12L1_DACC1DHR 0xFFF0U
3136 /****************** Bit definition for DAC_DHR8R1 register ******************/
3137 #define DAC_DHR8R1_DACC1DHR 0xFFU
3139 /***************** Bit definition for DAC_DHR12R2 register ******************/
3140 #define DAC_DHR12R2_DACC2DHR 0x0FFFU
3142 /***************** Bit definition for DAC_DHR12L2 register ******************/
3143 #define DAC_DHR12L2_DACC2DHR 0xFFF0U
3145 /****************** Bit definition for DAC_DHR8R2 register ******************/
3146 #define DAC_DHR8R2_DACC2DHR 0xFFU
3148 /***************** Bit definition for DAC_DHR12RD register ******************/
3149 #define DAC_DHR12RD_DACC1DHR 0x00000FFFU
3150 #define DAC_DHR12RD_DACC2DHR 0x0FFF0000U
3152 /***************** Bit definition for DAC_DHR12LD register ******************/
3153 #define DAC_DHR12LD_DACC1DHR 0x0000FFF0U
3154 #define DAC_DHR12LD_DACC2DHR 0xFFF00000U
3156 /****************** Bit definition for DAC_DHR8RD register ******************/
3157 #define DAC_DHR8RD_DACC1DHR 0x00FFU
3158 #define DAC_DHR8RD_DACC2DHR 0xFF00U
3160 /******************* Bit definition for DAC_DOR1 register *******************/
3161 #define DAC_DOR1_DACC1DOR 0x0FFFU
3163 /******************* Bit definition for DAC_DOR2 register *******************/
3164 #define DAC_DOR2_DACC2DOR 0x0FFFU
3166 /******************** Bit definition for DAC_SR register ********************/
3167 #define DAC_SR_DMAUDR1 0x00002000U
3168 #define DAC_SR_DMAUDR2 0x20000000U
3171 /******************************************************************************/
3172 /* */
3173 /* Debug MCU */
3174 /* */
3175 /******************************************************************************/
3176 
3177 /******************************************************************************/
3178 /* */
3179 /* DCMI */
3180 /* */
3181 /******************************************************************************/
3182 /******************** Bits definition for DCMI_CR register ******************/
3183 #define DCMI_CR_CAPTURE 0x00000001U
3184 #define DCMI_CR_CM 0x00000002U
3185 #define DCMI_CR_CROP 0x00000004U
3186 #define DCMI_CR_JPEG 0x00000008U
3187 #define DCMI_CR_ESS 0x00000010U
3188 #define DCMI_CR_PCKPOL 0x00000020U
3189 #define DCMI_CR_HSPOL 0x00000040U
3190 #define DCMI_CR_VSPOL 0x00000080U
3191 #define DCMI_CR_FCRC_0 0x00000100U
3192 #define DCMI_CR_FCRC_1 0x00000200U
3193 #define DCMI_CR_EDM_0 0x00000400U
3194 #define DCMI_CR_EDM_1 0x00000800U
3195 #define DCMI_CR_CRE 0x00001000U
3196 #define DCMI_CR_ENABLE 0x00004000U
3197 #define DCMI_CR_BSM 0x00030000U
3198 #define DCMI_CR_BSM_0 0x00010000U
3199 #define DCMI_CR_BSM_1 0x00020000U
3200 #define DCMI_CR_OEBS 0x00040000U
3201 #define DCMI_CR_LSM 0x00080000U
3202 #define DCMI_CR_OELS 0x00100000U
3203 
3204 /******************** Bits definition for DCMI_SR register ******************/
3205 #define DCMI_SR_HSYNC 0x00000001U
3206 #define DCMI_SR_VSYNC 0x00000002U
3207 #define DCMI_SR_FNE 0x00000004U
3208 
3209 /******************** Bits definition for DCMI_RIS register ****************/
3210 #define DCMI_RIS_FRAME_RIS 0x00000001U
3211 #define DCMI_RIS_OVR_RIS 0x00000002U
3212 #define DCMI_RIS_ERR_RIS 0x00000004U
3213 #define DCMI_RIS_VSYNC_RIS 0x00000008U
3214 #define DCMI_RIS_LINE_RIS 0x00000010U
3215 
3216 /* Legacy defines */
3217 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
3218 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
3219 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
3220 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
3221 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
3222 
3223 /******************** Bits definition for DCMI_IER register *****************/
3224 #define DCMI_IER_FRAME_IE 0x00000001U
3225 #define DCMI_IER_OVR_IE 0x00000002U
3226 #define DCMI_IER_ERR_IE 0x00000004U
3227 #define DCMI_IER_VSYNC_IE 0x00000008U
3228 #define DCMI_IER_LINE_IE 0x00000010U
3229 
3230 /* Legacy define */
3231 #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
3232 
3233 /******************** Bits definition for DCMI_MIS register *****************/
3234 #define DCMI_MIS_FRAME_MIS 0x00000001U
3235 #define DCMI_MIS_OVR_MIS 0x00000002U
3236 #define DCMI_MIS_ERR_MIS 0x00000004U
3237 #define DCMI_MIS_VSYNC_MIS 0x00000008U
3238 #define DCMI_MIS_LINE_MIS 0x00000010U
3239 
3240 /* Legacy defines */
3241 #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
3242 #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
3243 #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
3244 #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
3245 #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
3246 
3247 /******************** Bits definition for DCMI_ICR register *****************/
3248 #define DCMI_ICR_FRAME_ISC 0x00000001U
3249 #define DCMI_ICR_OVR_ISC 0x00000002U
3250 #define DCMI_ICR_ERR_ISC 0x00000004U
3251 #define DCMI_ICR_VSYNC_ISC 0x00000008U
3252 #define DCMI_ICR_LINE_ISC 0x00000010U
3253 
3254 /* Legacy defines */
3255 #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
3256 
3257 /******************** Bits definition for DCMI_ESCR register ******************/
3258 #define DCMI_ESCR_FSC 0x000000FFU
3259 #define DCMI_ESCR_LSC 0x0000FF00U
3260 #define DCMI_ESCR_LEC 0x00FF0000U
3261 #define DCMI_ESCR_FEC 0xFF000000U
3262 
3263 /******************** Bits definition for DCMI_ESUR register ******************/
3264 #define DCMI_ESUR_FSU 0x000000FFU
3265 #define DCMI_ESUR_LSU 0x0000FF00U
3266 #define DCMI_ESUR_LEU 0x00FF0000U
3267 #define DCMI_ESUR_FEU 0xFF000000U
3268 
3269 /******************** Bits definition for DCMI_CWSTRT register ******************/
3270 #define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
3271 #define DCMI_CWSTRT_VST 0x1FFF0000U
3272 
3273 /******************** Bits definition for DCMI_CWSIZE register ******************/
3274 #define DCMI_CWSIZE_CAPCNT 0x00003FFFU
3275 #define DCMI_CWSIZE_VLINE 0x3FFF0000U
3276 
3277 /******************** Bits definition for DCMI_DR register ******************/
3278 #define DCMI_DR_BYTE0 0x000000FFU
3279 #define DCMI_DR_BYTE1 0x0000FF00U
3280 #define DCMI_DR_BYTE2 0x00FF0000U
3281 #define DCMI_DR_BYTE3 0xFF000000U
3282 
3283 /******************************************************************************/
3284 /* */
3285 /* DMA Controller */
3286 /* */
3287 /******************************************************************************/
3288 /******************** Bits definition for DMA_SxCR register *****************/
3289 #define DMA_SxCR_CHSEL 0x0E000000U
3290 #define DMA_SxCR_CHSEL_0 0x02000000U
3291 #define DMA_SxCR_CHSEL_1 0x04000000U
3292 #define DMA_SxCR_CHSEL_2 0x08000000U
3293 #define DMA_SxCR_MBURST 0x01800000U
3294 #define DMA_SxCR_MBURST_0 0x00800000U
3295 #define DMA_SxCR_MBURST_1 0x01000000U
3296 #define DMA_SxCR_PBURST 0x00600000U
3297 #define DMA_SxCR_PBURST_0 0x00200000U
3298 #define DMA_SxCR_PBURST_1 0x00400000U
3299 #define DMA_SxCR_CT 0x00080000U
3300 #define DMA_SxCR_DBM 0x00040000U
3301 #define DMA_SxCR_PL 0x00030000U
3302 #define DMA_SxCR_PL_0 0x00010000U
3303 #define DMA_SxCR_PL_1 0x00020000U
3304 #define DMA_SxCR_PINCOS 0x00008000U
3305 #define DMA_SxCR_MSIZE 0x00006000U
3306 #define DMA_SxCR_MSIZE_0 0x00002000U
3307 #define DMA_SxCR_MSIZE_1 0x00004000U
3308 #define DMA_SxCR_PSIZE 0x00001800U
3309 #define DMA_SxCR_PSIZE_0 0x00000800U
3310 #define DMA_SxCR_PSIZE_1 0x00001000U
3311 #define DMA_SxCR_MINC 0x00000400U
3312 #define DMA_SxCR_PINC 0x00000200U
3313 #define DMA_SxCR_CIRC 0x00000100U
3314 #define DMA_SxCR_DIR 0x000000C0U
3315 #define DMA_SxCR_DIR_0 0x00000040U
3316 #define DMA_SxCR_DIR_1 0x00000080U
3317 #define DMA_SxCR_PFCTRL 0x00000020U
3318 #define DMA_SxCR_TCIE 0x00000010U
3319 #define DMA_SxCR_HTIE 0x00000008U
3320 #define DMA_SxCR_TEIE 0x00000004U
3321 #define DMA_SxCR_DMEIE 0x00000002U
3322 #define DMA_SxCR_EN 0x00000001U
3323 
3324 /******************** Bits definition for DMA_SxCNDTR register **************/
3325 #define DMA_SxNDT 0x0000FFFFU
3326 #define DMA_SxNDT_0 0x00000001U
3327 #define DMA_SxNDT_1 0x00000002U
3328 #define DMA_SxNDT_2 0x00000004U
3329 #define DMA_SxNDT_3 0x00000008U
3330 #define DMA_SxNDT_4 0x00000010U
3331 #define DMA_SxNDT_5 0x00000020U
3332 #define DMA_SxNDT_6 0x00000040U
3333 #define DMA_SxNDT_7 0x00000080U
3334 #define DMA_SxNDT_8 0x00000100U
3335 #define DMA_SxNDT_9 0x00000200U
3336 #define DMA_SxNDT_10 0x00000400U
3337 #define DMA_SxNDT_11 0x00000800U
3338 #define DMA_SxNDT_12 0x00001000U
3339 #define DMA_SxNDT_13 0x00002000U
3340 #define DMA_SxNDT_14 0x00004000U
3341 #define DMA_SxNDT_15 0x00008000U
3342 
3343 /******************** Bits definition for DMA_SxFCR register ****************/
3344 #define DMA_SxFCR_FEIE 0x00000080U
3345 #define DMA_SxFCR_FS 0x00000038U
3346 #define DMA_SxFCR_FS_0 0x00000008U
3347 #define DMA_SxFCR_FS_1 0x00000010U
3348 #define DMA_SxFCR_FS_2 0x00000020U
3349 #define DMA_SxFCR_DMDIS 0x00000004U
3350 #define DMA_SxFCR_FTH 0x00000003U
3351 #define DMA_SxFCR_FTH_0 0x00000001U
3352 #define DMA_SxFCR_FTH_1 0x00000002U
3353 
3354 /******************** Bits definition for DMA_LISR register *****************/
3355 #define DMA_LISR_TCIF3 0x08000000U
3356 #define DMA_LISR_HTIF3 0x04000000U
3357 #define DMA_LISR_TEIF3 0x02000000U
3358 #define DMA_LISR_DMEIF3 0x01000000U
3359 #define DMA_LISR_FEIF3 0x00400000U
3360 #define DMA_LISR_TCIF2 0x00200000U
3361 #define DMA_LISR_HTIF2 0x00100000U
3362 #define DMA_LISR_TEIF2 0x00080000U
3363 #define DMA_LISR_DMEIF2 0x00040000U
3364 #define DMA_LISR_FEIF2 0x00010000U
3365 #define DMA_LISR_TCIF1 0x00000800U
3366 #define DMA_LISR_HTIF1 0x00000400U
3367 #define DMA_LISR_TEIF1 0x00000200U
3368 #define DMA_LISR_DMEIF1 0x00000100U
3369 #define DMA_LISR_FEIF1 0x00000040U
3370 #define DMA_LISR_TCIF0 0x00000020U
3371 #define DMA_LISR_HTIF0 0x00000010U
3372 #define DMA_LISR_TEIF0 0x00000008U
3373 #define DMA_LISR_DMEIF0 0x00000004U
3374 #define DMA_LISR_FEIF0 0x00000001U
3375 
3376 /******************** Bits definition for DMA_HISR register *****************/
3377 #define DMA_HISR_TCIF7 0x08000000U
3378 #define DMA_HISR_HTIF7 0x04000000U
3379 #define DMA_HISR_TEIF7 0x02000000U
3380 #define DMA_HISR_DMEIF7 0x01000000U
3381 #define DMA_HISR_FEIF7 0x00400000U
3382 #define DMA_HISR_TCIF6 0x00200000U
3383 #define DMA_HISR_HTIF6 0x00100000U
3384 #define DMA_HISR_TEIF6 0x00080000U
3385 #define DMA_HISR_DMEIF6 0x00040000U
3386 #define DMA_HISR_FEIF6 0x00010000U
3387 #define DMA_HISR_TCIF5 0x00000800U
3388 #define DMA_HISR_HTIF5 0x00000400U
3389 #define DMA_HISR_TEIF5 0x00000200U
3390 #define DMA_HISR_DMEIF5 0x00000100U
3391 #define DMA_HISR_FEIF5 0x00000040U
3392 #define DMA_HISR_TCIF4 0x00000020U
3393 #define DMA_HISR_HTIF4 0x00000010U
3394 #define DMA_HISR_TEIF4 0x00000008U
3395 #define DMA_HISR_DMEIF4 0x00000004U
3396 #define DMA_HISR_FEIF4 0x00000001U
3397 
3398 /******************** Bits definition for DMA_LIFCR register ****************/
3399 #define DMA_LIFCR_CTCIF3 0x08000000U
3400 #define DMA_LIFCR_CHTIF3 0x04000000U
3401 #define DMA_LIFCR_CTEIF3 0x02000000U
3402 #define DMA_LIFCR_CDMEIF3 0x01000000U
3403 #define DMA_LIFCR_CFEIF3 0x00400000U
3404 #define DMA_LIFCR_CTCIF2 0x00200000U
3405 #define DMA_LIFCR_CHTIF2 0x00100000U
3406 #define DMA_LIFCR_CTEIF2 0x00080000U
3407 #define DMA_LIFCR_CDMEIF2 0x00040000U
3408 #define DMA_LIFCR_CFEIF2 0x00010000U
3409 #define DMA_LIFCR_CTCIF1 0x00000800U
3410 #define DMA_LIFCR_CHTIF1 0x00000400U
3411 #define DMA_LIFCR_CTEIF1 0x00000200U
3412 #define DMA_LIFCR_CDMEIF1 0x00000100U
3413 #define DMA_LIFCR_CFEIF1 0x00000040U
3414 #define DMA_LIFCR_CTCIF0 0x00000020U
3415 #define DMA_LIFCR_CHTIF0 0x00000010U
3416 #define DMA_LIFCR_CTEIF0 0x00000008U
3417 #define DMA_LIFCR_CDMEIF0 0x00000004U
3418 #define DMA_LIFCR_CFEIF0 0x00000001U
3419 
3420 /******************** Bits definition for DMA_HIFCR register ****************/
3421 #define DMA_HIFCR_CTCIF7 0x08000000U
3422 #define DMA_HIFCR_CHTIF7 0x04000000U
3423 #define DMA_HIFCR_CTEIF7 0x02000000U
3424 #define DMA_HIFCR_CDMEIF7 0x01000000U
3425 #define DMA_HIFCR_CFEIF7 0x00400000U
3426 #define DMA_HIFCR_CTCIF6 0x00200000U
3427 #define DMA_HIFCR_CHTIF6 0x00100000U
3428 #define DMA_HIFCR_CTEIF6 0x00080000U
3429 #define DMA_HIFCR_CDMEIF6 0x00040000U
3430 #define DMA_HIFCR_CFEIF6 0x00010000U
3431 #define DMA_HIFCR_CTCIF5 0x00000800U
3432 #define DMA_HIFCR_CHTIF5 0x00000400U
3433 #define DMA_HIFCR_CTEIF5 0x00000200U
3434 #define DMA_HIFCR_CDMEIF5 0x00000100U
3435 #define DMA_HIFCR_CFEIF5 0x00000040U
3436 #define DMA_HIFCR_CTCIF4 0x00000020U
3437 #define DMA_HIFCR_CHTIF4 0x00000010U
3438 #define DMA_HIFCR_CTEIF4 0x00000008U
3439 #define DMA_HIFCR_CDMEIF4 0x00000004U
3440 #define DMA_HIFCR_CFEIF4 0x00000001U
3441 
3442 /******************************************************************************/
3443 /* */
3444 /* AHB Master DMA2D Controller (DMA2D) */
3445 /* */
3446 /******************************************************************************/
3447 
3448 /******************** Bit definition for DMA2D_CR register ******************/
3449 
3450 #define DMA2D_CR_START 0x00000001U
3451 #define DMA2D_CR_SUSP 0x00000002U
3452 #define DMA2D_CR_ABORT 0x00000004U
3453 #define DMA2D_CR_TEIE 0x00000100U
3454 #define DMA2D_CR_TCIE 0x00000200U
3455 #define DMA2D_CR_TWIE 0x00000400U
3456 #define DMA2D_CR_CAEIE 0x00000800U
3457 #define DMA2D_CR_CTCIE 0x00001000U
3458 #define DMA2D_CR_CEIE 0x00002000U
3459 #define DMA2D_CR_MODE 0x00030000U
3460 #define DMA2D_CR_MODE_0 0x00010000U
3461 #define DMA2D_CR_MODE_1 0x00020000U
3463 /******************** Bit definition for DMA2D_ISR register *****************/
3464 
3465 #define DMA2D_ISR_TEIF 0x00000001U
3466 #define DMA2D_ISR_TCIF 0x00000002U
3467 #define DMA2D_ISR_TWIF 0x00000004U
3468 #define DMA2D_ISR_CAEIF 0x00000008U
3469 #define DMA2D_ISR_CTCIF 0x00000010U
3470 #define DMA2D_ISR_CEIF 0x00000020U
3472 /******************** Bit definition for DMA2D_IFCR register ****************/
3473 
3474 #define DMA2D_IFCR_CTEIF 0x00000001U
3475 #define DMA2D_IFCR_CTCIF 0x00000002U
3476 #define DMA2D_IFCR_CTWIF 0x00000004U
3477 #define DMA2D_IFCR_CAECIF 0x00000008U
3478 #define DMA2D_IFCR_CCTCIF 0x00000010U
3479 #define DMA2D_IFCR_CCEIF 0x00000020U
3481 /* Legacy defines */
3482 #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF
3483 #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF
3484 #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF
3485 #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF
3486 #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF
3487 #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF
3489 /******************** Bit definition for DMA2D_FGMAR register ***************/
3490 
3491 #define DMA2D_FGMAR_MA 0xFFFFFFFFU
3493 /******************** Bit definition for DMA2D_FGOR register ****************/
3494 
3495 #define DMA2D_FGOR_LO 0x00003FFFU
3497 /******************** Bit definition for DMA2D_BGMAR register ***************/
3498 
3499 #define DMA2D_BGMAR_MA 0xFFFFFFFFU
3501 /******************** Bit definition for DMA2D_BGOR register ****************/
3502 
3503 #define DMA2D_BGOR_LO 0x00003FFFU
3505 /******************** Bit definition for DMA2D_FGPFCCR register *************/
3506 
3507 #define DMA2D_FGPFCCR_CM 0x0000000FU
3508 #define DMA2D_FGPFCCR_CM_0 0x00000001U
3509 #define DMA2D_FGPFCCR_CM_1 0x00000002U
3510 #define DMA2D_FGPFCCR_CM_2 0x00000004U
3511 #define DMA2D_FGPFCCR_CM_3 0x00000008U
3512 #define DMA2D_FGPFCCR_CCM 0x00000010U
3513 #define DMA2D_FGPFCCR_START 0x00000020U
3514 #define DMA2D_FGPFCCR_CS 0x0000FF00U
3515 #define DMA2D_FGPFCCR_AM 0x00030000U
3516 #define DMA2D_FGPFCCR_AM_0 0x00010000U
3517 #define DMA2D_FGPFCCR_AM_1 0x00020000U
3518 #define DMA2D_FGPFCCR_ALPHA 0xFF000000U
3520 /******************** Bit definition for DMA2D_FGCOLR register **************/
3521 
3522 #define DMA2D_FGCOLR_BLUE 0x000000FFU
3523 #define DMA2D_FGCOLR_GREEN 0x0000FF00U
3524 #define DMA2D_FGCOLR_RED 0x00FF0000U
3526 /******************** Bit definition for DMA2D_BGPFCCR register *************/
3527 
3528 #define DMA2D_BGPFCCR_CM 0x0000000FU
3529 #define DMA2D_BGPFCCR_CM_0 0x00000001U
3530 #define DMA2D_BGPFCCR_CM_1 0x00000002U
3531 #define DMA2D_BGPFCCR_CM_2 0x00000004U
3532 #define DMA2D_FGPFCCR_CM_3 0x00000008U
3533 #define DMA2D_BGPFCCR_CCM 0x00000010U
3534 #define DMA2D_BGPFCCR_START 0x00000020U
3535 #define DMA2D_BGPFCCR_CS 0x0000FF00U
3536 #define DMA2D_BGPFCCR_AM 0x00030000U
3537 #define DMA2D_BGPFCCR_AM_0 0x00010000U
3538 #define DMA2D_BGPFCCR_AM_1 0x00020000U
3539 #define DMA2D_BGPFCCR_ALPHA 0xFF000000U
3541 /******************** Bit definition for DMA2D_BGCOLR register **************/
3542 
3543 #define DMA2D_BGCOLR_BLUE 0x000000FFU
3544 #define DMA2D_BGCOLR_GREEN 0x0000FF00U
3545 #define DMA2D_BGCOLR_RED 0x00FF0000U
3547 /******************** Bit definition for DMA2D_FGCMAR register **************/
3548 
3549 #define DMA2D_FGCMAR_MA 0xFFFFFFFFU
3551 /******************** Bit definition for DMA2D_BGCMAR register **************/
3552 
3553 #define DMA2D_BGCMAR_MA 0xFFFFFFFFU
3555 /******************** Bit definition for DMA2D_OPFCCR register **************/
3556 
3557 #define DMA2D_OPFCCR_CM 0x00000007U
3558 #define DMA2D_OPFCCR_CM_0 0x00000001U
3559 #define DMA2D_OPFCCR_CM_1 0x00000002U
3560 #define DMA2D_OPFCCR_CM_2 0x00000004U
3562 /******************** Bit definition for DMA2D_OCOLR register ***************/
3563 
3566 #define DMA2D_OCOLR_BLUE_1 0x000000FFU
3567 #define DMA2D_OCOLR_GREEN_1 0x0000FF00U
3568 #define DMA2D_OCOLR_RED_1 0x00FF0000U
3569 #define DMA2D_OCOLR_ALPHA_1 0xFF000000U
3572 #define DMA2D_OCOLR_BLUE_2 0x0000001FU
3573 #define DMA2D_OCOLR_GREEN_2 0x000007E0U
3574 #define DMA2D_OCOLR_RED_2 0x0000F800U
3577 #define DMA2D_OCOLR_BLUE_3 0x0000001FU
3578 #define DMA2D_OCOLR_GREEN_3 0x000003E0U
3579 #define DMA2D_OCOLR_RED_3 0x00007C00U
3580 #define DMA2D_OCOLR_ALPHA_3 0x00008000U
3583 #define DMA2D_OCOLR_BLUE_4 0x0000000FU
3584 #define DMA2D_OCOLR_GREEN_4 0x000000F0U
3585 #define DMA2D_OCOLR_RED_4 0x00000F00U
3586 #define DMA2D_OCOLR_ALPHA_4 0x0000F000U
3588 /******************** Bit definition for DMA2D_OMAR register ****************/
3589 
3590 #define DMA2D_OMAR_MA 0xFFFFFFFFU
3592 /******************** Bit definition for DMA2D_OOR register *****************/
3593 
3594 #define DMA2D_OOR_LO 0x00003FFFU
3596 /******************** Bit definition for DMA2D_NLR register *****************/
3597 
3598 #define DMA2D_NLR_NL 0x0000FFFFU
3599 #define DMA2D_NLR_PL 0x3FFF0000U
3601 /******************** Bit definition for DMA2D_LWR register *****************/
3602 
3603 #define DMA2D_LWR_LW 0x0000FFFFU
3605 /******************** Bit definition for DMA2D_AMTCR register ***************/
3606 
3607 #define DMA2D_AMTCR_EN 0x00000001U
3608 #define DMA2D_AMTCR_DT 0x0000FF00U
3611 /******************** Bit definition for DMA2D_FGCLUT register **************/
3612 
3613 /******************** Bit definition for DMA2D_BGCLUT register **************/
3614 
3615 
3616 /******************************************************************************/
3617 /* */
3618 /* External Interrupt/Event Controller */
3619 /* */
3620 /******************************************************************************/
3621 /******************* Bit definition for EXTI_IMR register *******************/
3622 #define EXTI_IMR_MR0 0x00000001U
3623 #define EXTI_IMR_MR1 0x00000002U
3624 #define EXTI_IMR_MR2 0x00000004U
3625 #define EXTI_IMR_MR3 0x00000008U
3626 #define EXTI_IMR_MR4 0x00000010U
3627 #define EXTI_IMR_MR5 0x00000020U
3628 #define EXTI_IMR_MR6 0x00000040U
3629 #define EXTI_IMR_MR7 0x00000080U
3630 #define EXTI_IMR_MR8 0x00000100U
3631 #define EXTI_IMR_MR9 0x00000200U
3632 #define EXTI_IMR_MR10 0x00000400U
3633 #define EXTI_IMR_MR11 0x00000800U
3634 #define EXTI_IMR_MR12 0x00001000U
3635 #define EXTI_IMR_MR13 0x00002000U
3636 #define EXTI_IMR_MR14 0x00004000U
3637 #define EXTI_IMR_MR15 0x00008000U
3638 #define EXTI_IMR_MR16 0x00010000U
3639 #define EXTI_IMR_MR17 0x00020000U
3640 #define EXTI_IMR_MR18 0x00040000U
3641 #define EXTI_IMR_MR19 0x00080000U
3642 #define EXTI_IMR_MR20 0x00100000U
3643 #define EXTI_IMR_MR21 0x00200000U
3644 #define EXTI_IMR_MR22 0x00400000U
3645 #define EXTI_IMR_MR23 0x00800000U
3647 /* Reference Defines */
3648 #define EXTI_IMR_IM0 EXTI_IMR_MR0
3649 #define EXTI_IMR_IM1 EXTI_IMR_MR1
3650 #define EXTI_IMR_IM2 EXTI_IMR_MR2
3651 #define EXTI_IMR_IM3 EXTI_IMR_MR3
3652 #define EXTI_IMR_IM4 EXTI_IMR_MR4
3653 #define EXTI_IMR_IM5 EXTI_IMR_MR5
3654 #define EXTI_IMR_IM6 EXTI_IMR_MR6
3655 #define EXTI_IMR_IM7 EXTI_IMR_MR7
3656 #define EXTI_IMR_IM8 EXTI_IMR_MR8
3657 #define EXTI_IMR_IM9 EXTI_IMR_MR9
3658 #define EXTI_IMR_IM10 EXTI_IMR_MR10
3659 #define EXTI_IMR_IM11 EXTI_IMR_MR11
3660 #define EXTI_IMR_IM12 EXTI_IMR_MR12
3661 #define EXTI_IMR_IM13 EXTI_IMR_MR13
3662 #define EXTI_IMR_IM14 EXTI_IMR_MR14
3663 #define EXTI_IMR_IM15 EXTI_IMR_MR15
3664 #define EXTI_IMR_IM16 EXTI_IMR_MR16
3665 #define EXTI_IMR_IM17 EXTI_IMR_MR17
3666 #define EXTI_IMR_IM18 EXTI_IMR_MR18
3667 #define EXTI_IMR_IM19 EXTI_IMR_MR19
3668 #define EXTI_IMR_IM20 EXTI_IMR_MR20
3669 #define EXTI_IMR_IM21 EXTI_IMR_MR21
3670 #define EXTI_IMR_IM22 EXTI_IMR_MR22
3671 #define EXTI_IMR_IM23 EXTI_IMR_MR23
3672 
3673 #define EXTI_IMR_IM 0x00FFFFFFU
3675 /******************* Bit definition for EXTI_EMR register *******************/
3676 #define EXTI_EMR_MR0 0x00000001U
3677 #define EXTI_EMR_MR1 0x00000002U
3678 #define EXTI_EMR_MR2 0x00000004U
3679 #define EXTI_EMR_MR3 0x00000008U
3680 #define EXTI_EMR_MR4 0x00000010U
3681 #define EXTI_EMR_MR5 0x00000020U
3682 #define EXTI_EMR_MR6 0x00000040U
3683 #define EXTI_EMR_MR7 0x00000080U
3684 #define EXTI_EMR_MR8 0x00000100U
3685 #define EXTI_EMR_MR9 0x00000200U
3686 #define EXTI_EMR_MR10 0x00000400U
3687 #define EXTI_EMR_MR11 0x00000800U
3688 #define EXTI_EMR_MR12 0x00001000U
3689 #define EXTI_EMR_MR13 0x00002000U
3690 #define EXTI_EMR_MR14 0x00004000U
3691 #define EXTI_EMR_MR15 0x00008000U
3692 #define EXTI_EMR_MR16 0x00010000U
3693 #define EXTI_EMR_MR17 0x00020000U
3694 #define EXTI_EMR_MR18 0x00040000U
3695 #define EXTI_EMR_MR19 0x00080000U
3696 #define EXTI_EMR_MR20 0x00100000U
3697 #define EXTI_EMR_MR21 0x00200000U
3698 #define EXTI_EMR_MR22 0x00400000U
3699 #define EXTI_EMR_MR23 0x00800000U
3701 /* Reference Defines */
3702 #define EXTI_EMR_EM0 EXTI_EMR_MR0
3703 #define EXTI_EMR_EM1 EXTI_EMR_MR1
3704 #define EXTI_EMR_EM2 EXTI_EMR_MR2
3705 #define EXTI_EMR_EM3 EXTI_EMR_MR3
3706 #define EXTI_EMR_EM4 EXTI_EMR_MR4
3707 #define EXTI_EMR_EM5 EXTI_EMR_MR5
3708 #define EXTI_EMR_EM6 EXTI_EMR_MR6
3709 #define EXTI_EMR_EM7 EXTI_EMR_MR7
3710 #define EXTI_EMR_EM8 EXTI_EMR_MR8
3711 #define EXTI_EMR_EM9 EXTI_EMR_MR9
3712 #define EXTI_EMR_EM10 EXTI_EMR_MR10
3713 #define EXTI_EMR_EM11 EXTI_EMR_MR11
3714 #define EXTI_EMR_EM12 EXTI_EMR_MR12
3715 #define EXTI_EMR_EM13 EXTI_EMR_MR13
3716 #define EXTI_EMR_EM14 EXTI_EMR_MR14
3717 #define EXTI_EMR_EM15 EXTI_EMR_MR15
3718 #define EXTI_EMR_EM16 EXTI_EMR_MR16
3719 #define EXTI_EMR_EM17 EXTI_EMR_MR17
3720 #define EXTI_EMR_EM18 EXTI_EMR_MR18
3721 #define EXTI_EMR_EM19 EXTI_EMR_MR19
3722 #define EXTI_EMR_EM20 EXTI_EMR_MR20
3723 #define EXTI_EMR_EM21 EXTI_EMR_MR21
3724 #define EXTI_EMR_EM22 EXTI_EMR_MR22
3725 #define EXTI_EMR_EM23 EXTI_EMR_MR23
3726 
3727 
3728 /****************** Bit definition for EXTI_RTSR register *******************/
3729 #define EXTI_RTSR_TR0 0x00000001U
3730 #define EXTI_RTSR_TR1 0x00000002U
3731 #define EXTI_RTSR_TR2 0x00000004U
3732 #define EXTI_RTSR_TR3 0x00000008U
3733 #define EXTI_RTSR_TR4 0x00000010U
3734 #define EXTI_RTSR_TR5 0x00000020U
3735 #define EXTI_RTSR_TR6 0x00000040U
3736 #define EXTI_RTSR_TR7 0x00000080U
3737 #define EXTI_RTSR_TR8 0x00000100U
3738 #define EXTI_RTSR_TR9 0x00000200U
3739 #define EXTI_RTSR_TR10 0x00000400U
3740 #define EXTI_RTSR_TR11 0x00000800U
3741 #define EXTI_RTSR_TR12 0x00001000U
3742 #define EXTI_RTSR_TR13 0x00002000U
3743 #define EXTI_RTSR_TR14 0x00004000U
3744 #define EXTI_RTSR_TR15 0x00008000U
3745 #define EXTI_RTSR_TR16 0x00010000U
3746 #define EXTI_RTSR_TR17 0x00020000U
3747 #define EXTI_RTSR_TR18 0x00040000U
3748 #define EXTI_RTSR_TR19 0x00080000U
3749 #define EXTI_RTSR_TR20 0x00100000U
3750 #define EXTI_RTSR_TR21 0x00200000U
3751 #define EXTI_RTSR_TR22 0x00400000U
3752 #define EXTI_RTSR_TR23 0x00800000U
3754 /****************** Bit definition for EXTI_FTSR register *******************/
3755 #define EXTI_FTSR_TR0 0x00000001U
3756 #define EXTI_FTSR_TR1 0x00000002U
3757 #define EXTI_FTSR_TR2 0x00000004U
3758 #define EXTI_FTSR_TR3 0x00000008U
3759 #define EXTI_FTSR_TR4 0x00000010U
3760 #define EXTI_FTSR_TR5 0x00000020U
3761 #define EXTI_FTSR_TR6 0x00000040U
3762 #define EXTI_FTSR_TR7 0x00000080U
3763 #define EXTI_FTSR_TR8 0x00000100U
3764 #define EXTI_FTSR_TR9 0x00000200U
3765 #define EXTI_FTSR_TR10 0x00000400U
3766 #define EXTI_FTSR_TR11 0x00000800U
3767 #define EXTI_FTSR_TR12 0x00001000U
3768 #define EXTI_FTSR_TR13 0x00002000U
3769 #define EXTI_FTSR_TR14 0x00004000U
3770 #define EXTI_FTSR_TR15 0x00008000U
3771 #define EXTI_FTSR_TR16 0x00010000U
3772 #define EXTI_FTSR_TR17 0x00020000U
3773 #define EXTI_FTSR_TR18 0x00040000U
3774 #define EXTI_FTSR_TR19 0x00080000U
3775 #define EXTI_FTSR_TR20 0x00100000U
3776 #define EXTI_FTSR_TR21 0x00200000U
3777 #define EXTI_FTSR_TR22 0x00400000U
3778 #define EXTI_FTSR_TR23 0x00800000U
3780 /****************** Bit definition for EXTI_SWIER register ******************/
3781 #define EXTI_SWIER_SWIER0 0x00000001U
3782 #define EXTI_SWIER_SWIER1 0x00000002U
3783 #define EXTI_SWIER_SWIER2 0x00000004U
3784 #define EXTI_SWIER_SWIER3 0x00000008U
3785 #define EXTI_SWIER_SWIER4 0x00000010U
3786 #define EXTI_SWIER_SWIER5 0x00000020U
3787 #define EXTI_SWIER_SWIER6 0x00000040U
3788 #define EXTI_SWIER_SWIER7 0x00000080U
3789 #define EXTI_SWIER_SWIER8 0x00000100U
3790 #define EXTI_SWIER_SWIER9 0x00000200U
3791 #define EXTI_SWIER_SWIER10 0x00000400U
3792 #define EXTI_SWIER_SWIER11 0x00000800U
3793 #define EXTI_SWIER_SWIER12 0x00001000U
3794 #define EXTI_SWIER_SWIER13 0x00002000U
3795 #define EXTI_SWIER_SWIER14 0x00004000U
3796 #define EXTI_SWIER_SWIER15 0x00008000U
3797 #define EXTI_SWIER_SWIER16 0x00010000U
3798 #define EXTI_SWIER_SWIER17 0x00020000U
3799 #define EXTI_SWIER_SWIER18 0x00040000U
3800 #define EXTI_SWIER_SWIER19 0x00080000U
3801 #define EXTI_SWIER_SWIER20 0x00100000U
3802 #define EXTI_SWIER_SWIER21 0x00200000U
3803 #define EXTI_SWIER_SWIER22 0x00400000U
3804 #define EXTI_SWIER_SWIER23 0x00800000U
3806 /******************* Bit definition for EXTI_PR register ********************/
3807 #define EXTI_PR_PR0 0x00000001U
3808 #define EXTI_PR_PR1 0x00000002U
3809 #define EXTI_PR_PR2 0x00000004U
3810 #define EXTI_PR_PR3 0x00000008U
3811 #define EXTI_PR_PR4 0x00000010U
3812 #define EXTI_PR_PR5 0x00000020U
3813 #define EXTI_PR_PR6 0x00000040U
3814 #define EXTI_PR_PR7 0x00000080U
3815 #define EXTI_PR_PR8 0x00000100U
3816 #define EXTI_PR_PR9 0x00000200U
3817 #define EXTI_PR_PR10 0x00000400U
3818 #define EXTI_PR_PR11 0x00000800U
3819 #define EXTI_PR_PR12 0x00001000U
3820 #define EXTI_PR_PR13 0x00002000U
3821 #define EXTI_PR_PR14 0x00004000U
3822 #define EXTI_PR_PR15 0x00008000U
3823 #define EXTI_PR_PR16 0x00010000U
3824 #define EXTI_PR_PR17 0x00020000U
3825 #define EXTI_PR_PR18 0x00040000U
3826 #define EXTI_PR_PR19 0x00080000U
3827 #define EXTI_PR_PR20 0x00100000U
3828 #define EXTI_PR_PR21 0x00200000U
3829 #define EXTI_PR_PR22 0x00400000U
3830 #define EXTI_PR_PR23 0x00800000U
3832 /******************************************************************************/
3833 /* */
3834 /* FLASH */
3835 /* */
3836 /******************************************************************************/
3837 /*
3838 * @brief FLASH Total Sectors Number
3839 */
3840 #define FLASH_SECTOR_TOTAL 8
3841 
3842 /******************* Bits definition for FLASH_ACR register *****************/
3843 #define FLASH_ACR_LATENCY 0x0000000FU
3844 #define FLASH_ACR_LATENCY_0WS 0x00000000U
3845 #define FLASH_ACR_LATENCY_1WS 0x00000001U
3846 #define FLASH_ACR_LATENCY_2WS 0x00000002U
3847 #define FLASH_ACR_LATENCY_3WS 0x00000003U
3848 #define FLASH_ACR_LATENCY_4WS 0x00000004U
3849 #define FLASH_ACR_LATENCY_5WS 0x00000005U
3850 #define FLASH_ACR_LATENCY_6WS 0x00000006U
3851 #define FLASH_ACR_LATENCY_7WS 0x00000007U
3852 #define FLASH_ACR_LATENCY_8WS 0x00000008U
3853 #define FLASH_ACR_LATENCY_9WS 0x00000009U
3854 #define FLASH_ACR_LATENCY_10WS 0x0000000AU
3855 #define FLASH_ACR_LATENCY_11WS 0x0000000BU
3856 #define FLASH_ACR_LATENCY_12WS 0x0000000CU
3857 #define FLASH_ACR_LATENCY_13WS 0x0000000DU
3858 #define FLASH_ACR_LATENCY_14WS 0x0000000EU
3859 #define FLASH_ACR_LATENCY_15WS 0x0000000FU
3860 #define FLASH_ACR_PRFTEN 0x00000100U
3861 #define FLASH_ACR_ARTEN 0x00000200U
3862 #define FLASH_ACR_ARTRST 0x00000800U
3863 
3864 /******************* Bits definition for FLASH_SR register ******************/
3865 #define FLASH_SR_EOP 0x00000001U
3866 #define FLASH_SR_OPERR 0x00000002U
3867 #define FLASH_SR_WRPERR 0x00000010U
3868 #define FLASH_SR_PGAERR 0x00000020U
3869 #define FLASH_SR_PGPERR 0x00000040U
3870 #define FLASH_SR_ERSERR 0x00000080U
3871 #define FLASH_SR_BSY 0x00010000U
3872 
3873 /******************* Bits definition for FLASH_CR register ******************/
3874 #define FLASH_CR_PG 0x00000001U
3875 #define FLASH_CR_SER 0x00000002U
3876 #define FLASH_CR_MER 0x00000004U
3877 #define FLASH_CR_SNB 0x00000078U
3878 #define FLASH_CR_SNB_0 0x00000008U
3879 #define FLASH_CR_SNB_1 0x00000010U
3880 #define FLASH_CR_SNB_2 0x00000020U
3881 #define FLASH_CR_SNB_3 0x00000040U
3882 #define FLASH_CR_PSIZE 0x00000300U
3883 #define FLASH_CR_PSIZE_0 0x00000100U
3884 #define FLASH_CR_PSIZE_1 0x00000200U
3885 #define FLASH_CR_STRT 0x00010000U
3886 #define FLASH_CR_EOPIE 0x01000000U
3887 #define FLASH_CR_ERRIE 0x02000000U
3888 #define FLASH_CR_LOCK 0x80000000U
3889 
3890 /******************* Bits definition for FLASH_OPTCR register ***************/
3891 #define FLASH_OPTCR_OPTLOCK 0x00000001U
3892 #define FLASH_OPTCR_OPTSTRT 0x00000002U
3893 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
3894 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
3895 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
3896 #define FLASH_OPTCR_WWDG_SW 0x00000010U
3897 #define FLASH_OPTCR_IWDG_SW 0x00000020U
3898 #define FLASH_OPTCR_nRST_STOP 0x00000040U
3899 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
3900 #define FLASH_OPTCR_RDP 0x0000FF00U
3901 #define FLASH_OPTCR_RDP_0 0x00000100U
3902 #define FLASH_OPTCR_RDP_1 0x00000200U
3903 #define FLASH_OPTCR_RDP_2 0x00000400U
3904 #define FLASH_OPTCR_RDP_3 0x00000800U
3905 #define FLASH_OPTCR_RDP_4 0x00001000U
3906 #define FLASH_OPTCR_RDP_5 0x00002000U
3907 #define FLASH_OPTCR_RDP_6 0x00004000U
3908 #define FLASH_OPTCR_RDP_7 0x00008000U
3909 #define FLASH_OPTCR_nWRP 0x00FF0000U
3910 #define FLASH_OPTCR_nWRP_0 0x00010000U
3911 #define FLASH_OPTCR_nWRP_1 0x00020000U
3912 #define FLASH_OPTCR_nWRP_2 0x00040000U
3913 #define FLASH_OPTCR_nWRP_3 0x00080000U
3914 #define FLASH_OPTCR_nWRP_4 0x00100000U
3915 #define FLASH_OPTCR_nWRP_5 0x00200000U
3916 #define FLASH_OPTCR_nWRP_6 0x00400000U
3917 #define FLASH_OPTCR_nWRP_7 0x00800000U
3918 #define FLASH_OPTCR_IWDG_STDBY 0x40000000U
3919 #define FLASH_OPTCR_IWDG_STOP 0x80000000U
3920 
3921 /******************* Bits definition for FLASH_OPTCR1 register ***************/
3922 #define FLASH_OPTCR1_BOOT_ADD0 0x0000FFFFU
3923 #define FLASH_OPTCR1_BOOT_ADD1 0xFFFF0000U
3924 
3925 /******************************************************************************/
3926 /* */
3927 /* Flexible Memory Controller */
3928 /* */
3929 /******************************************************************************/
3930 /****************** Bit definition for FMC_BCR1 register *******************/
3931 #define FMC_BCR1_MBKEN 0x00000001U
3932 #define FMC_BCR1_MUXEN 0x00000002U
3933 #define FMC_BCR1_MTYP 0x0000000CU
3934 #define FMC_BCR1_MTYP_0 0x00000004U
3935 #define FMC_BCR1_MTYP_1 0x00000008U
3936 #define FMC_BCR1_MWID 0x00000030U
3937 #define FMC_BCR1_MWID_0 0x00000010U
3938 #define FMC_BCR1_MWID_1 0x00000020U
3939 #define FMC_BCR1_FACCEN 0x00000040U
3940 #define FMC_BCR1_BURSTEN 0x00000100U
3941 #define FMC_BCR1_WAITPOL 0x00000200U
3942 #define FMC_BCR1_WRAPMOD 0x00000400U
3943 #define FMC_BCR1_WAITCFG 0x00000800U
3944 #define FMC_BCR1_WREN 0x00001000U
3945 #define FMC_BCR1_WAITEN 0x00002000U
3946 #define FMC_BCR1_EXTMOD 0x00004000U
3947 #define FMC_BCR1_ASYNCWAIT 0x00008000U
3948 #define FMC_BCR1_CPSIZE 0x00070000U
3949 #define FMC_BCR1_CPSIZE_0 0x00010000U
3950 #define FMC_BCR1_CPSIZE_1 0x00020000U
3951 #define FMC_BCR1_CPSIZE_2 0x00040000U
3952 #define FMC_BCR1_CBURSTRW 0x00080000U
3953 #define FMC_BCR1_CCLKEN 0x00100000U
3954 #define FMC_BCR1_WFDIS 0x00200000U
3956 /****************** Bit definition for FMC_BCR2 register *******************/
3957 #define FMC_BCR2_MBKEN 0x00000001U
3958 #define FMC_BCR2_MUXEN 0x00000002U
3959 #define FMC_BCR2_MTYP 0x0000000CU
3960 #define FMC_BCR2_MTYP_0 0x00000004U
3961 #define FMC_BCR2_MTYP_1 0x00000008U
3962 #define FMC_BCR2_MWID 0x00000030U
3963 #define FMC_BCR2_MWID_0 0x00000010U
3964 #define FMC_BCR2_MWID_1 0x00000020U
3965 #define FMC_BCR2_FACCEN 0x00000040U
3966 #define FMC_BCR2_BURSTEN 0x00000100U
3967 #define FMC_BCR2_WAITPOL 0x00000200U
3968 #define FMC_BCR2_WRAPMOD 0x00000400U
3969 #define FMC_BCR2_WAITCFG 0x00000800U
3970 #define FMC_BCR2_WREN 0x00001000U
3971 #define FMC_BCR2_WAITEN 0x00002000U
3972 #define FMC_BCR2_EXTMOD 0x00004000U
3973 #define FMC_BCR2_ASYNCWAIT 0x00008000U
3974 #define FMC_BCR2_CPSIZE 0x00070000U
3975 #define FMC_BCR2_CPSIZE_0 0x00010000U
3976 #define FMC_BCR2_CPSIZE_1 0x00020000U
3977 #define FMC_BCR2_CPSIZE_2 0x00040000U
3978 #define FMC_BCR2_CBURSTRW 0x00080000U
3980 /****************** Bit definition for FMC_BCR3 register *******************/
3981 #define FMC_BCR3_MBKEN 0x00000001U
3982 #define FMC_BCR3_MUXEN 0x00000002U
3983 #define FMC_BCR3_MTYP 0x0000000CU
3984 #define FMC_BCR3_MTYP_0 0x00000004U
3985 #define FMC_BCR3_MTYP_1 0x00000008U
3986 #define FMC_BCR3_MWID 0x00000030U
3987 #define FMC_BCR3_MWID_0 0x00000010U
3988 #define FMC_BCR3_MWID_1 0x00000020U
3989 #define FMC_BCR3_FACCEN 0x00000040U
3990 #define FMC_BCR3_BURSTEN 0x00000100U
3991 #define FMC_BCR3_WAITPOL 0x00000200U
3992 #define FMC_BCR3_WRAPMOD 0x00000400U
3993 #define FMC_BCR3_WAITCFG 0x00000800U
3994 #define FMC_BCR3_WREN 0x00001000U
3995 #define FMC_BCR3_WAITEN 0x00002000U
3996 #define FMC_BCR3_EXTMOD 0x00004000U
3997 #define FMC_BCR3_ASYNCWAIT 0x00008000U
3998 #define FMC_BCR3_CPSIZE 0x00070000U
3999 #define FMC_BCR3_CPSIZE_0 0x00010000U
4000 #define FMC_BCR3_CPSIZE_1 0x00020000U
4001 #define FMC_BCR3_CPSIZE_2 0x00040000U
4002 #define FMC_BCR3_CBURSTRW 0x00080000U
4004 /****************** Bit definition for FMC_BCR4 register *******************/
4005 #define FMC_BCR4_MBKEN 0x00000001U
4006 #define FMC_BCR4_MUXEN 0x00000002U
4007 #define FMC_BCR4_MTYP 0x0000000CU
4008 #define FMC_BCR4_MTYP_0 0x00000004U
4009 #define FMC_BCR4_MTYP_1 0x00000008U
4010 #define FMC_BCR4_MWID 0x00000030U
4011 #define FMC_BCR4_MWID_0 0x00000010U
4012 #define FMC_BCR4_MWID_1 0x00000020U
4013 #define FMC_BCR4_FACCEN 0x00000040U
4014 #define FMC_BCR4_BURSTEN 0x00000100U
4015 #define FMC_BCR4_WAITPOL 0x00000200U
4016 #define FMC_BCR4_WRAPMOD 0x00000400U
4017 #define FMC_BCR4_WAITCFG 0x00000800U
4018 #define FMC_BCR4_WREN 0x00001000U
4019 #define FMC_BCR4_WAITEN 0x00002000U
4020 #define FMC_BCR4_EXTMOD 0x00004000U
4021 #define FMC_BCR4_ASYNCWAIT 0x00008000U
4022 #define FMC_BCR4_CPSIZE 0x00070000U
4023 #define FMC_BCR4_CPSIZE_0 0x00010000U
4024 #define FMC_BCR4_CPSIZE_1 0x00020000U
4025 #define FMC_BCR4_CPSIZE_2 0x00040000U
4026 #define FMC_BCR4_CBURSTRW 0x00080000U
4028 /****************** Bit definition for FMC_BTR1 register ******************/
4029 #define FMC_BTR1_ADDSET 0x0000000FU
4030 #define FMC_BTR1_ADDSET_0 0x00000001U
4031 #define FMC_BTR1_ADDSET_1 0x00000002U
4032 #define FMC_BTR1_ADDSET_2 0x00000004U
4033 #define FMC_BTR1_ADDSET_3 0x00000008U
4034 #define FMC_BTR1_ADDHLD 0x000000F0U
4035 #define FMC_BTR1_ADDHLD_0 0x00000010U
4036 #define FMC_BTR1_ADDHLD_1 0x00000020U
4037 #define FMC_BTR1_ADDHLD_2 0x00000040U
4038 #define FMC_BTR1_ADDHLD_3 0x00000080U
4039 #define FMC_BTR1_DATAST 0x0000FF00U
4040 #define FMC_BTR1_DATAST_0 0x00000100U
4041 #define FMC_BTR1_DATAST_1 0x00000200U
4042 #define FMC_BTR1_DATAST_2 0x00000400U
4043 #define FMC_BTR1_DATAST_3 0x00000800U
4044 #define FMC_BTR1_DATAST_4 0x00001000U
4045 #define FMC_BTR1_DATAST_5 0x00002000U
4046 #define FMC_BTR1_DATAST_6 0x00004000U
4047 #define FMC_BTR1_DATAST_7 0x00008000U
4048 #define FMC_BTR1_BUSTURN 0x000F0000U
4049 #define FMC_BTR1_BUSTURN_0 0x00010000U
4050 #define FMC_BTR1_BUSTURN_1 0x00020000U
4051 #define FMC_BTR1_BUSTURN_2 0x00040000U
4052 #define FMC_BTR1_BUSTURN_3 0x00080000U
4053 #define FMC_BTR1_CLKDIV 0x00F00000U
4054 #define FMC_BTR1_CLKDIV_0 0x00100000U
4055 #define FMC_BTR1_CLKDIV_1 0x00200000U
4056 #define FMC_BTR1_CLKDIV_2 0x00400000U
4057 #define FMC_BTR1_CLKDIV_3 0x00800000U
4058 #define FMC_BTR1_DATLAT 0x0F000000U
4059 #define FMC_BTR1_DATLAT_0 0x01000000U
4060 #define FMC_BTR1_DATLAT_1 0x02000000U
4061 #define FMC_BTR1_DATLAT_2 0x04000000U
4062 #define FMC_BTR1_DATLAT_3 0x08000000U
4063 #define FMC_BTR1_ACCMOD 0x30000000U
4064 #define FMC_BTR1_ACCMOD_0 0x10000000U
4065 #define FMC_BTR1_ACCMOD_1 0x20000000U
4067 /****************** Bit definition for FMC_BTR2 register *******************/
4068 #define FMC_BTR2_ADDSET 0x0000000FU
4069 #define FMC_BTR2_ADDSET_0 0x00000001U
4070 #define FMC_BTR2_ADDSET_1 0x00000002U
4071 #define FMC_BTR2_ADDSET_2 0x00000004U
4072 #define FMC_BTR2_ADDSET_3 0x00000008U
4073 #define FMC_BTR2_ADDHLD 0x000000F0U
4074 #define FMC_BTR2_ADDHLD_0 0x00000010U
4075 #define FMC_BTR2_ADDHLD_1 0x00000020U
4076 #define FMC_BTR2_ADDHLD_2 0x00000040U
4077 #define FMC_BTR2_ADDHLD_3 0x00000080U
4078 #define FMC_BTR2_DATAST 0x0000FF00U
4079 #define FMC_BTR2_DATAST_0 0x00000100U
4080 #define FMC_BTR2_DATAST_1 0x00000200U
4081 #define FMC_BTR2_DATAST_2 0x00000400U
4082 #define FMC_BTR2_DATAST_3 0x00000800U
4083 #define FMC_BTR2_DATAST_4 0x00001000U
4084 #define FMC_BTR2_DATAST_5 0x00002000U
4085 #define FMC_BTR2_DATAST_6 0x00004000U
4086 #define FMC_BTR2_DATAST_7 0x00008000U
4087 #define FMC_BTR2_BUSTURN 0x000F0000U
4088 #define FMC_BTR2_BUSTURN_0 0x00010000U
4089 #define FMC_BTR2_BUSTURN_1 0x00020000U
4090 #define FMC_BTR2_BUSTURN_2 0x00040000U
4091 #define FMC_BTR2_BUSTURN_3 0x00080000U
4092 #define FMC_BTR2_CLKDIV 0x00F00000U
4093 #define FMC_BTR2_CLKDIV_0 0x00100000U
4094 #define FMC_BTR2_CLKDIV_1 0x00200000U
4095 #define FMC_BTR2_CLKDIV_2 0x00400000U
4096 #define FMC_BTR2_CLKDIV_3 0x00800000U
4097 #define FMC_BTR2_DATLAT 0x0F000000U
4098 #define FMC_BTR2_DATLAT_0 0x01000000U
4099 #define FMC_BTR2_DATLAT_1 0x02000000U
4100 #define FMC_BTR2_DATLAT_2 0x04000000U
4101 #define FMC_BTR2_DATLAT_3 0x08000000U
4102 #define FMC_BTR2_ACCMOD 0x30000000U
4103 #define FMC_BTR2_ACCMOD_0 0x10000000U
4104 #define FMC_BTR2_ACCMOD_1 0x20000000U
4106 /******************* Bit definition for FMC_BTR3 register *******************/
4107 #define FMC_BTR3_ADDSET 0x0000000FU
4108 #define FMC_BTR3_ADDSET_0 0x00000001U
4109 #define FMC_BTR3_ADDSET_1 0x00000002U
4110 #define FMC_BTR3_ADDSET_2 0x00000004U
4111 #define FMC_BTR3_ADDSET_3 0x00000008U
4112 #define FMC_BTR3_ADDHLD 0x000000F0U
4113 #define FMC_BTR3_ADDHLD_0 0x00000010U
4114 #define FMC_BTR3_ADDHLD_1 0x00000020U
4115 #define FMC_BTR3_ADDHLD_2 0x00000040U
4116 #define FMC_BTR3_ADDHLD_3 0x00000080U
4117 #define FMC_BTR3_DATAST 0x0000FF00U
4118 #define FMC_BTR3_DATAST_0 0x00000100U
4119 #define FMC_BTR3_DATAST_1 0x00000200U
4120 #define FMC_BTR3_DATAST_2 0x00000400U
4121 #define FMC_BTR3_DATAST_3 0x00000800U
4122 #define FMC_BTR3_DATAST_4 0x00001000U
4123 #define FMC_BTR3_DATAST_5 0x00002000U
4124 #define FMC_BTR3_DATAST_6 0x00004000U
4125 #define FMC_BTR3_DATAST_7 0x00008000U
4126 #define FMC_BTR3_BUSTURN 0x000F0000U
4127 #define FMC_BTR3_BUSTURN_0 0x00010000U
4128 #define FMC_BTR3_BUSTURN_1 0x00020000U
4129 #define FMC_BTR3_BUSTURN_2 0x00040000U
4130 #define FMC_BTR3_BUSTURN_3 0x00080000U
4131 #define FMC_BTR3_CLKDIV 0x00F00000U
4132 #define FMC_BTR3_CLKDIV_0 0x00100000U
4133 #define FMC_BTR3_CLKDIV_1 0x00200000U
4134 #define FMC_BTR3_CLKDIV_2 0x00400000U
4135 #define FMC_BTR3_CLKDIV_3 0x00800000U
4136 #define FMC_BTR3_DATLAT 0x0F000000U
4137 #define FMC_BTR3_DATLAT_0 0x01000000U
4138 #define FMC_BTR3_DATLAT_1 0x02000000U
4139 #define FMC_BTR3_DATLAT_2 0x04000000U
4140 #define FMC_BTR3_DATLAT_3 0x08000000U
4141 #define FMC_BTR3_ACCMOD 0x30000000U
4142 #define FMC_BTR3_ACCMOD_0 0x10000000U
4143 #define FMC_BTR3_ACCMOD_1 0x20000000U
4145 /****************** Bit definition for FMC_BTR4 register *******************/
4146 #define FMC_BTR4_ADDSET 0x0000000FU
4147 #define FMC_BTR4_ADDSET_0 0x00000001U
4148 #define FMC_BTR4_ADDSET_1 0x00000002U
4149 #define FMC_BTR4_ADDSET_2 0x00000004U
4150 #define FMC_BTR4_ADDSET_3 0x00000008U
4151 #define FMC_BTR4_ADDHLD 0x000000F0U
4152 #define FMC_BTR4_ADDHLD_0 0x00000010U
4153 #define FMC_BTR4_ADDHLD_1 0x00000020U
4154 #define FMC_BTR4_ADDHLD_2 0x00000040U
4155 #define FMC_BTR4_ADDHLD_3 0x00000080U
4156 #define FMC_BTR4_DATAST 0x0000FF00U
4157 #define FMC_BTR4_DATAST_0 0x00000100U
4158 #define FMC_BTR4_DATAST_1 0x00000200U
4159 #define FMC_BTR4_DATAST_2 0x00000400U
4160 #define FMC_BTR4_DATAST_3 0x00000800U
4161 #define FMC_BTR4_DATAST_4 0x00001000U
4162 #define FMC_BTR4_DATAST_5 0x00002000U
4163 #define FMC_BTR4_DATAST_6 0x00004000U
4164 #define FMC_BTR4_DATAST_7 0x00008000U
4165 #define FMC_BTR4_BUSTURN 0x000F0000U
4166 #define FMC_BTR4_BUSTURN_0 0x00010000U
4167 #define FMC_BTR4_BUSTURN_1 0x00020000U
4168 #define FMC_BTR4_BUSTURN_2 0x00040000U
4169 #define FMC_BTR4_BUSTURN_3 0x00080000U
4170 #define FMC_BTR4_CLKDIV 0x00F00000U
4171 #define FMC_BTR4_CLKDIV_0 0x00100000U
4172 #define FMC_BTR4_CLKDIV_1 0x00200000U
4173 #define FMC_BTR4_CLKDIV_2 0x00400000U
4174 #define FMC_BTR4_CLKDIV_3 0x00800000U
4175 #define FMC_BTR4_DATLAT 0x0F000000U
4176 #define FMC_BTR4_DATLAT_0 0x01000000U
4177 #define FMC_BTR4_DATLAT_1 0x02000000U
4178 #define FMC_BTR4_DATLAT_2 0x04000000U
4179 #define FMC_BTR4_DATLAT_3 0x08000000U
4180 #define FMC_BTR4_ACCMOD 0x30000000U
4181 #define FMC_BTR4_ACCMOD_0 0x10000000U
4182 #define FMC_BTR4_ACCMOD_1 0x20000000U
4184 /****************** Bit definition for FMC_BWTR1 register ******************/
4185 #define FMC_BWTR1_ADDSET 0x0000000FU
4186 #define FMC_BWTR1_ADDSET_0 0x00000001U
4187 #define FMC_BWTR1_ADDSET_1 0x00000002U
4188 #define FMC_BWTR1_ADDSET_2 0x00000004U
4189 #define FMC_BWTR1_ADDSET_3 0x00000008U
4190 #define FMC_BWTR1_ADDHLD 0x000000F0U
4191 #define FMC_BWTR1_ADDHLD_0 0x00000010U
4192 #define FMC_BWTR1_ADDHLD_1 0x00000020U
4193 #define FMC_BWTR1_ADDHLD_2 0x00000040U
4194 #define FMC_BWTR1_ADDHLD_3 0x00000080U
4195 #define FMC_BWTR1_DATAST 0x0000FF00U
4196 #define FMC_BWTR1_DATAST_0 0x00000100U
4197 #define FMC_BWTR1_DATAST_1 0x00000200U
4198 #define FMC_BWTR1_DATAST_2 0x00000400U
4199 #define FMC_BWTR1_DATAST_3 0x00000800U
4200 #define FMC_BWTR1_DATAST_4 0x00001000U
4201 #define FMC_BWTR1_DATAST_5 0x00002000U
4202 #define FMC_BWTR1_DATAST_6 0x00004000U
4203 #define FMC_BWTR1_DATAST_7 0x00008000U
4204 #define FMC_BWTR1_BUSTURN 0x000F0000U
4205 #define FMC_BWTR1_BUSTURN_0 0x00010000U
4206 #define FMC_BWTR1_BUSTURN_1 0x00020000U
4207 #define FMC_BWTR1_BUSTURN_2 0x00040000U
4208 #define FMC_BWTR1_BUSTURN_3 0x00080000U
4209 #define FMC_BWTR1_ACCMOD 0x30000000U
4210 #define FMC_BWTR1_ACCMOD_0 0x10000000U
4211 #define FMC_BWTR1_ACCMOD_1 0x20000000U
4213 /****************** Bit definition for FMC_BWTR2 register ******************/
4214 #define FMC_BWTR2_ADDSET 0x0000000FU
4215 #define FMC_BWTR2_ADDSET_0 0x00000001U
4216 #define FMC_BWTR2_ADDSET_1 0x00000002U
4217 #define FMC_BWTR2_ADDSET_2 0x00000004U
4218 #define FMC_BWTR2_ADDSET_3 0x00000008U
4219 #define FMC_BWTR2_ADDHLD 0x000000F0U
4220 #define FMC_BWTR2_ADDHLD_0 0x00000010U
4221 #define FMC_BWTR2_ADDHLD_1 0x00000020U
4222 #define FMC_BWTR2_ADDHLD_2 0x00000040U
4223 #define FMC_BWTR2_ADDHLD_3 0x00000080U
4224 #define FMC_BWTR2_DATAST 0x0000FF00U
4225 #define FMC_BWTR2_DATAST_0 0x00000100U
4226 #define FMC_BWTR2_DATAST_1 0x00000200U
4227 #define FMC_BWTR2_DATAST_2 0x00000400U
4228 #define FMC_BWTR2_DATAST_3 0x00000800U
4229 #define FMC_BWTR2_DATAST_4 0x00001000U
4230 #define FMC_BWTR2_DATAST_5 0x00002000U
4231 #define FMC_BWTR2_DATAST_6 0x00004000U
4232 #define FMC_BWTR2_DATAST_7 0x00008000U
4233 #define FMC_BWTR2_BUSTURN 0x000F0000U
4234 #define FMC_BWTR2_BUSTURN_0 0x00010000U
4235 #define FMC_BWTR2_BUSTURN_1 0x00020000U
4236 #define FMC_BWTR2_BUSTURN_2 0x00040000U
4237 #define FMC_BWTR2_BUSTURN_3 0x00080000U
4238 #define FMC_BWTR2_ACCMOD 0x30000000U
4239 #define FMC_BWTR2_ACCMOD_0 0x10000000U
4240 #define FMC_BWTR2_ACCMOD_1 0x20000000U
4242 /****************** Bit definition for FMC_BWTR3 register ******************/
4243 #define FMC_BWTR3_ADDSET 0x0000000FU
4244 #define FMC_BWTR3_ADDSET_0 0x00000001U
4245 #define FMC_BWTR3_ADDSET_1 0x00000002U
4246 #define FMC_BWTR3_ADDSET_2 0x00000004U
4247 #define FMC_BWTR3_ADDSET_3 0x00000008U
4248 #define FMC_BWTR3_ADDHLD 0x000000F0U
4249 #define FMC_BWTR3_ADDHLD_0 0x00000010U
4250 #define FMC_BWTR3_ADDHLD_1 0x00000020U
4251 #define FMC_BWTR3_ADDHLD_2 0x00000040U
4252 #define FMC_BWTR3_ADDHLD_3 0x00000080U
4253 #define FMC_BWTR3_DATAST 0x0000FF00U
4254 #define FMC_BWTR3_DATAST_0 0x00000100U
4255 #define FMC_BWTR3_DATAST_1 0x00000200U
4256 #define FMC_BWTR3_DATAST_2 0x00000400U
4257 #define FMC_BWTR3_DATAST_3 0x00000800U
4258 #define FMC_BWTR3_DATAST_4 0x00001000U
4259 #define FMC_BWTR3_DATAST_5 0x00002000U
4260 #define FMC_BWTR3_DATAST_6 0x00004000U
4261 #define FMC_BWTR3_DATAST_7 0x00008000U
4262 #define FMC_BWTR3_BUSTURN 0x000F0000U
4263 #define FMC_BWTR3_BUSTURN_0 0x00010000U
4264 #define FMC_BWTR3_BUSTURN_1 0x00020000U
4265 #define FMC_BWTR3_BUSTURN_2 0x00040000U
4266 #define FMC_BWTR3_BUSTURN_3 0x00080000U
4267 #define FMC_BWTR3_ACCMOD 0x30000000U
4268 #define FMC_BWTR3_ACCMOD_0 0x10000000U
4269 #define FMC_BWTR3_ACCMOD_1 0x20000000U
4271 /****************** Bit definition for FMC_BWTR4 register ******************/
4272 #define FMC_BWTR4_ADDSET 0x0000000FU
4273 #define FMC_BWTR4_ADDSET_0 0x00000001U
4274 #define FMC_BWTR4_ADDSET_1 0x00000002U
4275 #define FMC_BWTR4_ADDSET_2 0x00000004U
4276 #define FMC_BWTR4_ADDSET_3 0x00000008U
4277 #define FMC_BWTR4_ADDHLD 0x000000F0U
4278 #define FMC_BWTR4_ADDHLD_0 0x00000010U
4279 #define FMC_BWTR4_ADDHLD_1 0x00000020U
4280 #define FMC_BWTR4_ADDHLD_2 0x00000040U
4281 #define FMC_BWTR4_ADDHLD_3 0x00000080U
4282 #define FMC_BWTR4_DATAST 0x0000FF00U
4283 #define FMC_BWTR4_DATAST_0 0x00000100U
4284 #define FMC_BWTR4_DATAST_1 0x00000200U
4285 #define FMC_BWTR4_DATAST_2 0x00000400U
4286 #define FMC_BWTR4_DATAST_3 0x00000800U
4287 #define FMC_BWTR4_DATAST_4 0x00001000U
4288 #define FMC_BWTR4_DATAST_5 0x00002000U
4289 #define FMC_BWTR4_DATAST_6 0x00004000U
4290 #define FMC_BWTR4_DATAST_7 0x00008000U
4291 #define FMC_BWTR4_BUSTURN 0x000F0000U
4292 #define FMC_BWTR4_BUSTURN_0 0x00010000U
4293 #define FMC_BWTR4_BUSTURN_1 0x00020000U
4294 #define FMC_BWTR4_BUSTURN_2 0x00040000U
4295 #define FMC_BWTR4_BUSTURN_3 0x00080000U
4296 #define FMC_BWTR4_ACCMOD 0x30000000U
4297 #define FMC_BWTR4_ACCMOD_0 0x10000000U
4298 #define FMC_BWTR4_ACCMOD_1 0x20000000U
4300 /****************** Bit definition for FMC_PCR register *******************/
4301 #define FMC_PCR_PWAITEN 0x00000002U
4302 #define FMC_PCR_PBKEN 0x00000004U
4303 #define FMC_PCR_PTYP 0x00000008U
4304 #define FMC_PCR_PWID 0x00000030U
4305 #define FMC_PCR_PWID_0 0x00000010U
4306 #define FMC_PCR_PWID_1 0x00000020U
4307 #define FMC_PCR_ECCEN 0x00000040U
4308 #define FMC_PCR_TCLR 0x00001E00U
4309 #define FMC_PCR_TCLR_0 0x00000200U
4310 #define FMC_PCR_TCLR_1 0x00000400U
4311 #define FMC_PCR_TCLR_2 0x00000800U
4312 #define FMC_PCR_TCLR_3 0x00001000U
4313 #define FMC_PCR_TAR 0x0001E000U
4314 #define FMC_PCR_TAR_0 0x00002000U
4315 #define FMC_PCR_TAR_1 0x00004000U
4316 #define FMC_PCR_TAR_2 0x00008000U
4317 #define FMC_PCR_TAR_3 0x00010000U
4318 #define FMC_PCR_ECCPS 0x000E0000U
4319 #define FMC_PCR_ECCPS_0 0x00020000U
4320 #define FMC_PCR_ECCPS_1 0x00040000U
4321 #define FMC_PCR_ECCPS_2 0x00080000U
4323 /******************* Bit definition for FMC_SR register *******************/
4324 #define FMC_SR_IRS 0x01U
4325 #define FMC_SR_ILS 0x02U
4326 #define FMC_SR_IFS 0x04U
4327 #define FMC_SR_IREN 0x08U
4328 #define FMC_SR_ILEN 0x10U
4329 #define FMC_SR_IFEN 0x20U
4330 #define FMC_SR_FEMPT 0x40U
4332 /****************** Bit definition for FMC_PMEM register ******************/
4333 #define FMC_PMEM_MEMSET3 0x000000FFU
4334 #define FMC_PMEM_MEMSET3_0 0x00000001U
4335 #define FMC_PMEM_MEMSET3_1 0x00000002U
4336 #define FMC_PMEM_MEMSET3_2 0x00000004U
4337 #define FMC_PMEM_MEMSET3_3 0x00000008U
4338 #define FMC_PMEM_MEMSET3_4 0x00000010U
4339 #define FMC_PMEM_MEMSET3_5 0x00000020U
4340 #define FMC_PMEM_MEMSET3_6 0x00000040U
4341 #define FMC_PMEM_MEMSET3_7 0x00000080U
4342 #define FMC_PMEM_MEMWAIT3 0x0000FF00U
4343 #define FMC_PMEM_MEMWAIT3_0 0x00000100U
4344 #define FMC_PMEM_MEMWAIT3_1 0x00000200U
4345 #define FMC_PMEM_MEMWAIT3_2 0x00000400U
4346 #define FMC_PMEM_MEMWAIT3_3 0x00000800U
4347 #define FMC_PMEM_MEMWAIT3_4 0x00001000U
4348 #define FMC_PMEM_MEMWAIT3_5 0x00002000U
4349 #define FMC_PMEM_MEMWAIT3_6 0x00004000U
4350 #define FMC_PMEM_MEMWAIT3_7 0x00008000U
4351 #define FMC_PMEM_MEMHOLD3 0x00FF0000U
4352 #define FMC_PMEM_MEMHOLD3_0 0x00010000U
4353 #define FMC_PMEM_MEMHOLD3_1 0x00020000U
4354 #define FMC_PMEM_MEMHOLD3_2 0x00040000U
4355 #define FMC_PMEM_MEMHOLD3_3 0x00080000U
4356 #define FMC_PMEM_MEMHOLD3_4 0x00100000U
4357 #define FMC_PMEM_MEMHOLD3_5 0x00200000U
4358 #define FMC_PMEM_MEMHOLD3_6 0x00400000U
4359 #define FMC_PMEM_MEMHOLD3_7 0x00800000U
4360 #define FMC_PMEM_MEMHIZ3 0xFF000000U
4361 #define FMC_PMEM_MEMHIZ3_0 0x01000000U
4362 #define FMC_PMEM_MEMHIZ3_1 0x02000000U
4363 #define FMC_PMEM_MEMHIZ3_2 0x04000000U
4364 #define FMC_PMEM_MEMHIZ3_3 0x08000000U
4365 #define FMC_PMEM_MEMHIZ3_4 0x10000000U
4366 #define FMC_PMEM_MEMHIZ3_5 0x20000000U
4367 #define FMC_PMEM_MEMHIZ3_6 0x40000000U
4368 #define FMC_PMEM_MEMHIZ3_7 0x80000000U
4370 /****************** Bit definition for FMC_PATT register ******************/
4371 #define FMC_PATT_ATTSET3 0x000000FFU
4372 #define FMC_PATT_ATTSET3_0 0x00000001U
4373 #define FMC_PATT_ATTSET3_1 0x00000002U
4374 #define FMC_PATT_ATTSET3_2 0x00000004U
4375 #define FMC_PATT_ATTSET3_3 0x00000008U
4376 #define FMC_PATT_ATTSET3_4 0x00000010U
4377 #define FMC_PATT_ATTSET3_5 0x00000020U
4378 #define FMC_PATT_ATTSET3_6 0x00000040U
4379 #define FMC_PATT_ATTSET3_7 0x00000080U
4380 #define FMC_PATT_ATTWAIT3 0x0000FF00U
4381 #define FMC_PATT_ATTWAIT3_0 0x00000100U
4382 #define FMC_PATT_ATTWAIT3_1 0x00000200U
4383 #define FMC_PATT_ATTWAIT3_2 0x00000400U
4384 #define FMC_PATT_ATTWAIT3_3 0x00000800U
4385 #define FMC_PATT_ATTWAIT3_4 0x00001000U
4386 #define FMC_PATT_ATTWAIT3_5 0x00002000U
4387 #define FMC_PATT_ATTWAIT3_6 0x00004000U
4388 #define FMC_PATT_ATTWAIT3_7 0x00008000U
4389 #define FMC_PATT_ATTHOLD3 0x00FF0000U
4390 #define FMC_PATT_ATTHOLD3_0 0x00010000U
4391 #define FMC_PATT_ATTHOLD3_1 0x00020000U
4392 #define FMC_PATT_ATTHOLD3_2 0x00040000U
4393 #define FMC_PATT_ATTHOLD3_3 0x00080000U
4394 #define FMC_PATT_ATTHOLD3_4 0x00100000U
4395 #define FMC_PATT_ATTHOLD3_5 0x00200000U
4396 #define FMC_PATT_ATTHOLD3_6 0x00400000U
4397 #define FMC_PATT_ATTHOLD3_7 0x00800000U
4398 #define FMC_PATT_ATTHIZ3 0xFF000000U
4399 #define FMC_PATT_ATTHIZ3_0 0x01000000U
4400 #define FMC_PATT_ATTHIZ3_1 0x02000000U
4401 #define FMC_PATT_ATTHIZ3_2 0x04000000U
4402 #define FMC_PATT_ATTHIZ3_3 0x08000000U
4403 #define FMC_PATT_ATTHIZ3_4 0x10000000U
4404 #define FMC_PATT_ATTHIZ3_5 0x20000000U
4405 #define FMC_PATT_ATTHIZ3_6 0x40000000U
4406 #define FMC_PATT_ATTHIZ3_7 0x80000000U
4408 /****************** Bit definition for FMC_ECCR register ******************/
4409 #define FMC_ECCR_ECC3 0xFFFFFFFFU
4411 /****************** Bit definition for FMC_SDCR1 register ******************/
4412 #define FMC_SDCR1_NC 0x00000003U
4413 #define FMC_SDCR1_NC_0 0x00000001U
4414 #define FMC_SDCR1_NC_1 0x00000002U
4415 #define FMC_SDCR1_NR 0x0000000CU
4416 #define FMC_SDCR1_NR_0 0x00000004U
4417 #define FMC_SDCR1_NR_1 0x00000008U
4418 #define FMC_SDCR1_MWID 0x00000030U
4419 #define FMC_SDCR1_MWID_0 0x00000010U
4420 #define FMC_SDCR1_MWID_1 0x00000020U
4421 #define FMC_SDCR1_NB 0x00000040U
4422 #define FMC_SDCR1_CAS 0x00000180U
4423 #define FMC_SDCR1_CAS_0 0x00000080U
4424 #define FMC_SDCR1_CAS_1 0x00000100U
4425 #define FMC_SDCR1_WP 0x00000200U
4426 #define FMC_SDCR1_SDCLK 0x00000C00U
4427 #define FMC_SDCR1_SDCLK_0 0x00000400U
4428 #define FMC_SDCR1_SDCLK_1 0x00000800U
4429 #define FMC_SDCR1_RBURST 0x00001000U
4430 #define FMC_SDCR1_RPIPE 0x00006000U
4431 #define FMC_SDCR1_RPIPE_0 0x00002000U
4432 #define FMC_SDCR1_RPIPE_1 0x00004000U
4434 /****************** Bit definition for FMC_SDCR2 register ******************/
4435 #define FMC_SDCR2_NC 0x00000003U
4436 #define FMC_SDCR2_NC_0 0x00000001U
4437 #define FMC_SDCR2_NC_1 0x00000002U
4438 #define FMC_SDCR2_NR 0x0000000CU
4439 #define FMC_SDCR2_NR_0 0x00000004U
4440 #define FMC_SDCR2_NR_1 0x00000008U
4441 #define FMC_SDCR2_MWID 0x00000030U
4442 #define FMC_SDCR2_MWID_0 0x00000010U
4443 #define FMC_SDCR2_MWID_1 0x00000020U
4444 #define FMC_SDCR2_NB 0x00000040U
4445 #define FMC_SDCR2_CAS 0x00000180U
4446 #define FMC_SDCR2_CAS_0 0x00000080U
4447 #define FMC_SDCR2_CAS_1 0x00000100U
4448 #define FMC_SDCR2_WP 0x00000200U
4449 #define FMC_SDCR2_SDCLK 0x00000C00U
4450 #define FMC_SDCR2_SDCLK_0 0x00000400U
4451 #define FMC_SDCR2_SDCLK_1 0x00000800U
4452 #define FMC_SDCR2_RBURST 0x00001000U
4453 #define FMC_SDCR2_RPIPE 0x00006000U
4454 #define FMC_SDCR2_RPIPE_0 0x00002000U
4455 #define FMC_SDCR2_RPIPE_1 0x00004000U
4457 /****************** Bit definition for FMC_SDTR1 register ******************/
4458 #define FMC_SDTR1_TMRD 0x0000000FU
4459 #define FMC_SDTR1_TMRD_0 0x00000001U
4460 #define FMC_SDTR1_TMRD_1 0x00000002U
4461 #define FMC_SDTR1_TMRD_2 0x00000004U
4462 #define FMC_SDTR1_TMRD_3 0x00000008U
4463 #define FMC_SDTR1_TXSR 0x000000F0U
4464 #define FMC_SDTR1_TXSR_0 0x00000010U
4465 #define FMC_SDTR1_TXSR_1 0x00000020U
4466 #define FMC_SDTR1_TXSR_2 0x00000040U
4467 #define FMC_SDTR1_TXSR_3 0x00000080U
4468 #define FMC_SDTR1_TRAS 0x00000F00U
4469 #define FMC_SDTR1_TRAS_0 0x00000100U
4470 #define FMC_SDTR1_TRAS_1 0x00000200U
4471 #define FMC_SDTR1_TRAS_2 0x00000400U
4472 #define FMC_SDTR1_TRAS_3 0x00000800U
4473 #define FMC_SDTR1_TRC 0x0000F000U
4474 #define FMC_SDTR1_TRC_0 0x00001000U
4475 #define FMC_SDTR1_TRC_1 0x00002000U
4476 #define FMC_SDTR1_TRC_2 0x00004000U
4477 #define FMC_SDTR1_TWR 0x000F0000U
4478 #define FMC_SDTR1_TWR_0 0x00010000U
4479 #define FMC_SDTR1_TWR_1 0x00020000U
4480 #define FMC_SDTR1_TWR_2 0x00040000U
4481 #define FMC_SDTR1_TRP 0x00F00000U
4482 #define FMC_SDTR1_TRP_0 0x00100000U
4483 #define FMC_SDTR1_TRP_1 0x00200000U
4484 #define FMC_SDTR1_TRP_2 0x00400000U
4485 #define FMC_SDTR1_TRCD 0x0F000000U
4486 #define FMC_SDTR1_TRCD_0 0x01000000U
4487 #define FMC_SDTR1_TRCD_1 0x02000000U
4488 #define FMC_SDTR1_TRCD_2 0x04000000U
4490 /****************** Bit definition for FMC_SDTR2 register ******************/
4491 #define FMC_SDTR2_TMRD 0x0000000FU
4492 #define FMC_SDTR2_TMRD_0 0x00000001U
4493 #define FMC_SDTR2_TMRD_1 0x00000002U
4494 #define FMC_SDTR2_TMRD_2 0x00000004U
4495 #define FMC_SDTR2_TMRD_3 0x00000008U
4496 #define FMC_SDTR2_TXSR 0x000000F0U
4497 #define FMC_SDTR2_TXSR_0 0x00000010U
4498 #define FMC_SDTR2_TXSR_1 0x00000020U
4499 #define FMC_SDTR2_TXSR_2 0x00000040U
4500 #define FMC_SDTR2_TXSR_3 0x00000080U
4501 #define FMC_SDTR2_TRAS 0x00000F00U
4502 #define FMC_SDTR2_TRAS_0 0x00000100U
4503 #define FMC_SDTR2_TRAS_1 0x00000200U
4504 #define FMC_SDTR2_TRAS_2 0x00000400U
4505 #define FMC_SDTR2_TRAS_3 0x00000800U
4506 #define FMC_SDTR2_TRC 0x0000F000U
4507 #define FMC_SDTR2_TRC_0 0x00001000U
4508 #define FMC_SDTR2_TRC_1 0x00002000U
4509 #define FMC_SDTR2_TRC_2 0x00004000U
4510 #define FMC_SDTR2_TWR 0x000F0000U
4511 #define FMC_SDTR2_TWR_0 0x00010000U
4512 #define FMC_SDTR2_TWR_1 0x00020000U
4513 #define FMC_SDTR2_TWR_2 0x00040000U
4514 #define FMC_SDTR2_TRP 0x00F00000U
4515 #define FMC_SDTR2_TRP_0 0x00100000U
4516 #define FMC_SDTR2_TRP_1 0x00200000U
4517 #define FMC_SDTR2_TRP_2 0x00400000U
4518 #define FMC_SDTR2_TRCD 0x0F000000U
4519 #define FMC_SDTR2_TRCD_0 0x01000000U
4520 #define FMC_SDTR2_TRCD_1 0x02000000U
4521 #define FMC_SDTR2_TRCD_2 0x04000000U
4523 /****************** Bit definition for FMC_SDCMR register ******************/
4524 #define FMC_SDCMR_MODE 0x00000007U
4525 #define FMC_SDCMR_MODE_0 0x00000001U
4526 #define FMC_SDCMR_MODE_1 0x00000002U
4527 #define FMC_SDCMR_MODE_2 0x00000003U
4528 #define FMC_SDCMR_CTB2 0x00000008U
4529 #define FMC_SDCMR_CTB1 0x00000010U
4530 #define FMC_SDCMR_NRFS 0x000001E0U
4531 #define FMC_SDCMR_NRFS_0 0x00000020U
4532 #define FMC_SDCMR_NRFS_1 0x00000040U
4533 #define FMC_SDCMR_NRFS_2 0x00000080U
4534 #define FMC_SDCMR_NRFS_3 0x00000100U
4535 #define FMC_SDCMR_MRD 0x003FFE00U
4537 /****************** Bit definition for FMC_SDRTR register ******************/
4538 #define FMC_SDRTR_CRE 0x00000001U
4539 #define FMC_SDRTR_COUNT 0x00003FFEU
4540 #define FMC_SDRTR_REIE 0x00004000U
4542 /****************** Bit definition for FMC_SDSR register ******************/
4543 #define FMC_SDSR_RE 0x00000001U
4544 #define FMC_SDSR_MODES1 0x00000006U
4545 #define FMC_SDSR_MODES1_0 0x00000002U
4546 #define FMC_SDSR_MODES1_1 0x00000004U
4547 #define FMC_SDSR_MODES2 0x00000018U
4548 #define FMC_SDSR_MODES2_0 0x00000008U
4549 #define FMC_SDSR_MODES2_1 0x00000010U
4550 #define FMC_SDSR_BUSY 0x00000020U
4552 /******************************************************************************/
4553 /* */
4554 /* General Purpose I/O */
4555 /* */
4556 /******************************************************************************/
4557 /****************** Bits definition for GPIO_MODER register *****************/
4558 #define GPIO_MODER_MODER0 0x00000003U
4559 #define GPIO_MODER_MODER0_0 0x00000001U
4560 #define GPIO_MODER_MODER0_1 0x00000002U
4561 #define GPIO_MODER_MODER1 0x0000000CU
4562 #define GPIO_MODER_MODER1_0 0x00000004U
4563 #define GPIO_MODER_MODER1_1 0x00000008U
4564 #define GPIO_MODER_MODER2 0x00000030U
4565 #define GPIO_MODER_MODER2_0 0x00000010U
4566 #define GPIO_MODER_MODER2_1 0x00000020U
4567 #define GPIO_MODER_MODER3 0x000000C0U
4568 #define GPIO_MODER_MODER3_0 0x00000040U
4569 #define GPIO_MODER_MODER3_1 0x00000080U
4570 #define GPIO_MODER_MODER4 0x00000300U
4571 #define GPIO_MODER_MODER4_0 0x00000100U
4572 #define GPIO_MODER_MODER4_1 0x00000200U
4573 #define GPIO_MODER_MODER5 0x00000C00U
4574 #define GPIO_MODER_MODER5_0 0x00000400U
4575 #define GPIO_MODER_MODER5_1 0x00000800U
4576 #define GPIO_MODER_MODER6 0x00003000U
4577 #define GPIO_MODER_MODER6_0 0x00001000U
4578 #define GPIO_MODER_MODER6_1 0x00002000U
4579 #define GPIO_MODER_MODER7 0x0000C000U
4580 #define GPIO_MODER_MODER7_0 0x00004000U
4581 #define GPIO_MODER_MODER7_1 0x00008000U
4582 #define GPIO_MODER_MODER8 0x00030000U
4583 #define GPIO_MODER_MODER8_0 0x00010000U
4584 #define GPIO_MODER_MODER8_1 0x00020000U
4585 #define GPIO_MODER_MODER9 0x000C0000U
4586 #define GPIO_MODER_MODER9_0 0x00040000U
4587 #define GPIO_MODER_MODER9_1 0x00080000U
4588 #define GPIO_MODER_MODER10 0x00300000U
4589 #define GPIO_MODER_MODER10_0 0x00100000U
4590 #define GPIO_MODER_MODER10_1 0x00200000U
4591 #define GPIO_MODER_MODER11 0x00C00000U
4592 #define GPIO_MODER_MODER11_0 0x00400000U
4593 #define GPIO_MODER_MODER11_1 0x00800000U
4594 #define GPIO_MODER_MODER12 0x03000000U
4595 #define GPIO_MODER_MODER12_0 0x01000000U
4596 #define GPIO_MODER_MODER12_1 0x02000000U
4597 #define GPIO_MODER_MODER13 0x0C000000U
4598 #define GPIO_MODER_MODER13_0 0x04000000U
4599 #define GPIO_MODER_MODER13_1 0x08000000U
4600 #define GPIO_MODER_MODER14 0x30000000U
4601 #define GPIO_MODER_MODER14_0 0x10000000U
4602 #define GPIO_MODER_MODER14_1 0x20000000U
4603 #define GPIO_MODER_MODER15 0xC0000000U
4604 #define GPIO_MODER_MODER15_0 0x40000000U
4605 #define GPIO_MODER_MODER15_1 0x80000000U
4606 
4607 /****************** Bits definition for GPIO_OTYPER register ****************/
4608 #define GPIO_OTYPER_OT_0 0x00000001U
4609 #define GPIO_OTYPER_OT_1 0x00000002U
4610 #define GPIO_OTYPER_OT_2 0x00000004U
4611 #define GPIO_OTYPER_OT_3 0x00000008U
4612 #define GPIO_OTYPER_OT_4 0x00000010U
4613 #define GPIO_OTYPER_OT_5 0x00000020U
4614 #define GPIO_OTYPER_OT_6 0x00000040U
4615 #define GPIO_OTYPER_OT_7 0x00000080U
4616 #define GPIO_OTYPER_OT_8 0x00000100U
4617 #define GPIO_OTYPER_OT_9 0x00000200U
4618 #define GPIO_OTYPER_OT_10 0x00000400U
4619 #define GPIO_OTYPER_OT_11 0x00000800U
4620 #define GPIO_OTYPER_OT_12 0x00001000U
4621 #define GPIO_OTYPER_OT_13 0x00002000U
4622 #define GPIO_OTYPER_OT_14 0x00004000U
4623 #define GPIO_OTYPER_OT_15 0x00008000U
4624 
4625 /****************** Bits definition for GPIO_OSPEEDR register ***************/
4626 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
4627 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
4628 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
4629 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
4630 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
4631 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
4632 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
4633 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
4634 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
4635 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
4636 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
4637 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
4638 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
4639 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
4640 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
4641 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
4642 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
4643 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
4644 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
4645 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
4646 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
4647 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
4648 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
4649 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
4650 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
4651 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
4652 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
4653 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
4654 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
4655 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
4656 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
4657 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
4658 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
4659 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
4660 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
4661 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
4662 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
4663 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
4664 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
4665 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
4666 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
4667 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
4668 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
4669 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
4670 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
4671 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
4672 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
4673 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
4674 
4675 /****************** Bits definition for GPIO_PUPDR register *****************/
4676 #define GPIO_PUPDR_PUPDR0 0x00000003U
4677 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
4678 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
4679 #define GPIO_PUPDR_PUPDR1 0x0000000CU
4680 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
4681 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
4682 #define GPIO_PUPDR_PUPDR2 0x00000030U
4683 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
4684 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
4685 #define GPIO_PUPDR_PUPDR3 0x000000C0U
4686 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
4687 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
4688 #define GPIO_PUPDR_PUPDR4 0x00000300U
4689 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
4690 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
4691 #define GPIO_PUPDR_PUPDR5 0x00000C00U
4692 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
4693 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
4694 #define GPIO_PUPDR_PUPDR6 0x00003000U
4695 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
4696 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
4697 #define GPIO_PUPDR_PUPDR7 0x0000C000U
4698 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
4699 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
4700 #define GPIO_PUPDR_PUPDR8 0x00030000U
4701 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
4702 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
4703 #define GPIO_PUPDR_PUPDR9 0x000C0000U
4704 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
4705 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
4706 #define GPIO_PUPDR_PUPDR10 0x00300000U
4707 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
4708 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
4709 #define GPIO_PUPDR_PUPDR11 0x00C00000U
4710 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
4711 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
4712 #define GPIO_PUPDR_PUPDR12 0x03000000U
4713 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
4714 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
4715 #define GPIO_PUPDR_PUPDR13 0x0C000000U
4716 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
4717 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
4718 #define GPIO_PUPDR_PUPDR14 0x30000000U
4719 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
4720 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
4721 #define GPIO_PUPDR_PUPDR15 0xC0000000U
4722 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
4723 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
4724 
4725 /****************** Bits definition for GPIO_IDR register *******************/
4726 #define GPIO_IDR_IDR_0 0x00000001U
4727 #define GPIO_IDR_IDR_1 0x00000002U
4728 #define GPIO_IDR_IDR_2 0x00000004U
4729 #define GPIO_IDR_IDR_3 0x00000008U
4730 #define GPIO_IDR_IDR_4 0x00000010U
4731 #define GPIO_IDR_IDR_5 0x00000020U
4732 #define GPIO_IDR_IDR_6 0x00000040U
4733 #define GPIO_IDR_IDR_7 0x00000080U
4734 #define GPIO_IDR_IDR_8 0x00000100U
4735 #define GPIO_IDR_IDR_9 0x00000200U
4736 #define GPIO_IDR_IDR_10 0x00000400U
4737 #define GPIO_IDR_IDR_11 0x00000800U
4738 #define GPIO_IDR_IDR_12 0x00001000U
4739 #define GPIO_IDR_IDR_13 0x00002000U
4740 #define GPIO_IDR_IDR_14 0x00004000U
4741 #define GPIO_IDR_IDR_15 0x00008000U
4742 
4743 /****************** Bits definition for GPIO_ODR register *******************/
4744 #define GPIO_ODR_ODR_0 0x00000001U
4745 #define GPIO_ODR_ODR_1 0x00000002U
4746 #define GPIO_ODR_ODR_2 0x00000004U
4747 #define GPIO_ODR_ODR_3 0x00000008U
4748 #define GPIO_ODR_ODR_4 0x00000010U
4749 #define GPIO_ODR_ODR_5 0x00000020U
4750 #define GPIO_ODR_ODR_6 0x00000040U
4751 #define GPIO_ODR_ODR_7 0x00000080U
4752 #define GPIO_ODR_ODR_8 0x00000100U
4753 #define GPIO_ODR_ODR_9 0x00000200U
4754 #define GPIO_ODR_ODR_10 0x00000400U
4755 #define GPIO_ODR_ODR_11 0x00000800U
4756 #define GPIO_ODR_ODR_12 0x00001000U
4757 #define GPIO_ODR_ODR_13 0x00002000U
4758 #define GPIO_ODR_ODR_14 0x00004000U
4759 #define GPIO_ODR_ODR_15 0x00008000U
4760 
4761 /****************** Bits definition for GPIO_BSRR register ******************/
4762 #define GPIO_BSRR_BS_0 0x00000001U
4763 #define GPIO_BSRR_BS_1 0x00000002U
4764 #define GPIO_BSRR_BS_2 0x00000004U
4765 #define GPIO_BSRR_BS_3 0x00000008U
4766 #define GPIO_BSRR_BS_4 0x00000010U
4767 #define GPIO_BSRR_BS_5 0x00000020U
4768 #define GPIO_BSRR_BS_6 0x00000040U
4769 #define GPIO_BSRR_BS_7 0x00000080U
4770 #define GPIO_BSRR_BS_8 0x00000100U
4771 #define GPIO_BSRR_BS_9 0x00000200U
4772 #define GPIO_BSRR_BS_10 0x00000400U
4773 #define GPIO_BSRR_BS_11 0x00000800U
4774 #define GPIO_BSRR_BS_12 0x00001000U
4775 #define GPIO_BSRR_BS_13 0x00002000U
4776 #define GPIO_BSRR_BS_14 0x00004000U
4777 #define GPIO_BSRR_BS_15 0x00008000U
4778 #define GPIO_BSRR_BR_0 0x00010000U
4779 #define GPIO_BSRR_BR_1 0x00020000U
4780 #define GPIO_BSRR_BR_2 0x00040000U
4781 #define GPIO_BSRR_BR_3 0x00080000U
4782 #define GPIO_BSRR_BR_4 0x00100000U
4783 #define GPIO_BSRR_BR_5 0x00200000U
4784 #define GPIO_BSRR_BR_6 0x00400000U
4785 #define GPIO_BSRR_BR_7 0x00800000U
4786 #define GPIO_BSRR_BR_8 0x01000000U
4787 #define GPIO_BSRR_BR_9 0x02000000U
4788 #define GPIO_BSRR_BR_10 0x04000000U
4789 #define GPIO_BSRR_BR_11 0x08000000U
4790 #define GPIO_BSRR_BR_12 0x10000000U
4791 #define GPIO_BSRR_BR_13 0x20000000U
4792 #define GPIO_BSRR_BR_14 0x40000000U
4793 #define GPIO_BSRR_BR_15 0x80000000U
4794 
4795 /****************** Bit definition for GPIO_LCKR register *********************/
4796 #define GPIO_LCKR_LCK0 0x00000001U
4797 #define GPIO_LCKR_LCK1 0x00000002U
4798 #define GPIO_LCKR_LCK2 0x00000004U
4799 #define GPIO_LCKR_LCK3 0x00000008U
4800 #define GPIO_LCKR_LCK4 0x00000010U
4801 #define GPIO_LCKR_LCK5 0x00000020U
4802 #define GPIO_LCKR_LCK6 0x00000040U
4803 #define GPIO_LCKR_LCK7 0x00000080U
4804 #define GPIO_LCKR_LCK8 0x00000100U
4805 #define GPIO_LCKR_LCK9 0x00000200U
4806 #define GPIO_LCKR_LCK10 0x00000400U
4807 #define GPIO_LCKR_LCK11 0x00000800U
4808 #define GPIO_LCKR_LCK12 0x00001000U
4809 #define GPIO_LCKR_LCK13 0x00002000U
4810 #define GPIO_LCKR_LCK14 0x00004000U
4811 #define GPIO_LCKR_LCK15 0x00008000U
4812 #define GPIO_LCKR_LCKK 0x00010000U
4813 
4814 
4815 /******************************************************************************/
4816 /* */
4817 /* Inter-integrated Circuit Interface (I2C) */
4818 /* */
4819 /******************************************************************************/
4820 /******************* Bit definition for I2C_CR1 register *******************/
4821 #define I2C_CR1_PE 0x00000001U
4822 #define I2C_CR1_TXIE 0x00000002U
4823 #define I2C_CR1_RXIE 0x00000004U
4824 #define I2C_CR1_ADDRIE 0x00000008U
4825 #define I2C_CR1_NACKIE 0x00000010U
4826 #define I2C_CR1_STOPIE 0x00000020U
4827 #define I2C_CR1_TCIE 0x00000040U
4828 #define I2C_CR1_ERRIE 0x00000080U
4829 #define I2C_CR1_DNF 0x00000F00U
4830 #define I2C_CR1_ANFOFF 0x00001000U
4831 #define I2C_CR1_TXDMAEN 0x00004000U
4832 #define I2C_CR1_RXDMAEN 0x00008000U
4833 #define I2C_CR1_SBC 0x00010000U
4834 #define I2C_CR1_NOSTRETCH 0x00020000U
4835 #define I2C_CR1_GCEN 0x00080000U
4836 #define I2C_CR1_SMBHEN 0x00100000U
4837 #define I2C_CR1_SMBDEN 0x00200000U
4838 #define I2C_CR1_ALERTEN 0x00400000U
4839 #define I2C_CR1_PECEN 0x00800000U
4841 /* Legacy define */
4842 #define I2C_CR1_DFN I2C_CR1_DNF
4844 /****************** Bit definition for I2C_CR2 register ********************/
4845 #define I2C_CR2_SADD 0x000003FFU
4846 #define I2C_CR2_RD_WRN 0x00000400U
4847 #define I2C_CR2_ADD10 0x00000800U
4848 #define I2C_CR2_HEAD10R 0x00001000U
4849 #define I2C_CR2_START 0x00002000U
4850 #define I2C_CR2_STOP 0x00004000U
4851 #define I2C_CR2_NACK 0x00008000U
4852 #define I2C_CR2_NBYTES 0x00FF0000U
4853 #define I2C_CR2_RELOAD 0x01000000U
4854 #define I2C_CR2_AUTOEND 0x02000000U
4855 #define I2C_CR2_PECBYTE 0x04000000U
4857 /******************* Bit definition for I2C_OAR1 register ******************/
4858 #define I2C_OAR1_OA1 0x000003FFU
4859 #define I2C_OAR1_OA1MODE 0x00000400U
4860 #define I2C_OAR1_OA1EN 0x00008000U
4862 /******************* Bit definition for I2C_OAR2 register ******************/
4863 #define I2C_OAR2_OA2 0x000000FEU
4864 #define I2C_OAR2_OA2MSK 0x00000700U
4865 #define I2C_OAR2_OA2NOMASK 0x00000000U
4866 #define I2C_OAR2_OA2MASK01 0x00000100U
4867 #define I2C_OAR2_OA2MASK02 0x00000200U
4868 #define I2C_OAR2_OA2MASK03 0x00000300U
4869 #define I2C_OAR2_OA2MASK04 0x00000400U
4870 #define I2C_OAR2_OA2MASK05 0x00000500U
4871 #define I2C_OAR2_OA2MASK06 0x00000600U
4872 #define I2C_OAR2_OA2MASK07 0x00000700U
4873 #define I2C_OAR2_OA2EN 0x00008000U
4875 /******************* Bit definition for I2C_TIMINGR register *******************/
4876 #define I2C_TIMINGR_SCLL 0x000000FFU
4877 #define I2C_TIMINGR_SCLH 0x0000FF00U
4878 #define I2C_TIMINGR_SDADEL 0x000F0000U
4879 #define I2C_TIMINGR_SCLDEL 0x00F00000U
4880 #define I2C_TIMINGR_PRESC 0xF0000000U
4882 /******************* Bit definition for I2C_TIMEOUTR register *******************/
4883 #define I2C_TIMEOUTR_TIMEOUTA 0x00000FFFU
4884 #define I2C_TIMEOUTR_TIDLE 0x00001000U
4885 #define I2C_TIMEOUTR_TIMOUTEN 0x00008000U
4886 #define I2C_TIMEOUTR_TIMEOUTB 0x0FFF0000U
4887 #define I2C_TIMEOUTR_TEXTEN 0x80000000U
4889 /****************** Bit definition for I2C_ISR register *********************/
4890 #define I2C_ISR_TXE 0x00000001U
4891 #define I2C_ISR_TXIS 0x00000002U
4892 #define I2C_ISR_RXNE 0x00000004U
4893 #define I2C_ISR_ADDR 0x00000008U
4894 #define I2C_ISR_NACKF 0x00000010U
4895 #define I2C_ISR_STOPF 0x00000020U
4896 #define I2C_ISR_TC 0x00000040U
4897 #define I2C_ISR_TCR 0x00000080U
4898 #define I2C_ISR_BERR 0x00000100U
4899 #define I2C_ISR_ARLO 0x00000200U
4900 #define I2C_ISR_OVR 0x00000400U
4901 #define I2C_ISR_PECERR 0x00000800U
4902 #define I2C_ISR_TIMEOUT 0x00001000U
4903 #define I2C_ISR_ALERT 0x00002000U
4904 #define I2C_ISR_BUSY 0x00008000U
4905 #define I2C_ISR_DIR 0x00010000U
4906 #define I2C_ISR_ADDCODE 0x00FE0000U
4908 /****************** Bit definition for I2C_ICR register *********************/
4909 #define I2C_ICR_ADDRCF 0x00000008U
4910 #define I2C_ICR_NACKCF 0x00000010U
4911 #define I2C_ICR_STOPCF 0x00000020U
4912 #define I2C_ICR_BERRCF 0x00000100U
4913 #define I2C_ICR_ARLOCF 0x00000200U
4914 #define I2C_ICR_OVRCF 0x00000400U
4915 #define I2C_ICR_PECCF 0x00000800U
4916 #define I2C_ICR_TIMOUTCF 0x00001000U
4917 #define I2C_ICR_ALERTCF 0x00002000U
4919 /****************** Bit definition for I2C_PECR register *********************/
4920 #define I2C_PECR_PEC 0x000000FFU
4922 /****************** Bit definition for I2C_RXDR register *********************/
4923 #define I2C_RXDR_RXDATA 0x000000FFU
4925 /****************** Bit definition for I2C_TXDR register *********************/
4926 #define I2C_TXDR_TXDATA 0x000000FFU
4929 /******************************************************************************/
4930 /* */
4931 /* Independent WATCHDOG */
4932 /* */
4933 /******************************************************************************/
4934 /******************* Bit definition for IWDG_KR register ********************/
4935 #define IWDG_KR_KEY 0xFFFFU
4937 /******************* Bit definition for IWDG_PR register ********************/
4938 #define IWDG_PR_PR 0x07U
4939 #define IWDG_PR_PR_0 0x01U
4940 #define IWDG_PR_PR_1 0x02U
4941 #define IWDG_PR_PR_2 0x04U
4943 /******************* Bit definition for IWDG_RLR register *******************/
4944 #define IWDG_RLR_RL 0x0FFFU
4946 /******************* Bit definition for IWDG_SR register ********************/
4947 #define IWDG_SR_PVU 0x01U
4948 #define IWDG_SR_RVU 0x02U
4949 #define IWDG_SR_WVU 0x04U
4951 /******************* Bit definition for IWDG_KR register ********************/
4952 #define IWDG_WINR_WIN 0x0FFFU
4955 /******************************************************************************/
4956 /* */
4957 /* Power Control */
4958 /* */
4959 /******************************************************************************/
4960 /******************** Bit definition for PWR_CR1 register ********************/
4961 #define PWR_CR1_LPDS 0x00000001U
4962 #define PWR_CR1_PDDS 0x00000002U
4963 #define PWR_CR1_CSBF 0x00000008U
4964 #define PWR_CR1_PVDE 0x00000010U
4965 #define PWR_CR1_PLS 0x000000E0U
4966 #define PWR_CR1_PLS_0 0x00000020U
4967 #define PWR_CR1_PLS_1 0x00000040U
4968 #define PWR_CR1_PLS_2 0x00000080U
4971 #define PWR_CR1_PLS_LEV0 0x00000000U
4972 #define PWR_CR1_PLS_LEV1 0x00000020U
4973 #define PWR_CR1_PLS_LEV2 0x00000040U
4974 #define PWR_CR1_PLS_LEV3 0x00000060U
4975 #define PWR_CR1_PLS_LEV4 0x00000080U
4976 #define PWR_CR1_PLS_LEV5 0x000000A0U
4977 #define PWR_CR1_PLS_LEV6 0x000000C0U
4978 #define PWR_CR1_PLS_LEV7 0x000000E0U
4979 #define PWR_CR1_DBP 0x00000100U
4980 #define PWR_CR1_FPDS 0x00000200U
4981 #define PWR_CR1_LPUDS 0x00000400U
4982 #define PWR_CR1_MRUDS 0x00000800U
4983 #define PWR_CR1_ADCDC1 0x00002000U
4984 #define PWR_CR1_VOS 0x0000C000U
4985 #define PWR_CR1_VOS_0 0x00004000U
4986 #define PWR_CR1_VOS_1 0x00008000U
4987 #define PWR_CR1_ODEN 0x00010000U
4988 #define PWR_CR1_ODSWEN 0x00020000U
4989 #define PWR_CR1_UDEN 0x000C0000U
4990 #define PWR_CR1_UDEN_0 0x00040000U
4991 #define PWR_CR1_UDEN_1 0x00080000U
4993 /******************* Bit definition for PWR_CSR1 register ********************/
4994 #define PWR_CSR1_WUIF 0x00000001U
4995 #define PWR_CSR1_SBF 0x00000002U
4996 #define PWR_CSR1_PVDO 0x00000004U
4997 #define PWR_CSR1_BRR 0x00000008U
4998 #define PWR_CSR1_EIWUP 0x00000100U
4999 #define PWR_CSR1_BRE 0x00000200U
5000 #define PWR_CSR1_VOSRDY 0x00004000U
5001 #define PWR_CSR1_ODRDY 0x00010000U
5002 #define PWR_CSR1_ODSWRDY 0x00020000U
5003 #define PWR_CSR1_UDRDY 0x000C0000U
5005 /* Legacy define */
5006 #define PWR_CSR1_UDSWRDY PWR_CSR1_UDRDY
5007 
5008 /******************** Bit definition for PWR_CR2 register ********************/
5009 #define PWR_CR2_CWUPF1 0x00000001U
5010 #define PWR_CR2_CWUPF2 0x00000002U
5011 #define PWR_CR2_CWUPF3 0x00000004U
5012 #define PWR_CR2_CWUPF4 0x00000008U
5013 #define PWR_CR2_CWUPF5 0x00000010U
5014 #define PWR_CR2_CWUPF6 0x00000020U
5015 #define PWR_CR2_WUPP1 0x00000100U
5016 #define PWR_CR2_WUPP2 0x00000200U
5017 #define PWR_CR2_WUPP3 0x00000400U
5018 #define PWR_CR2_WUPP4 0x00000800U
5019 #define PWR_CR2_WUPP5 0x00001000U
5020 #define PWR_CR2_WUPP6 0x00002000U
5022 /******************* Bit definition for PWR_CSR2 register ********************/
5023 #define PWR_CSR2_WUPF1 0x00000001U
5024 #define PWR_CSR2_WUPF2 0x00000002U
5025 #define PWR_CSR2_WUPF3 0x00000004U
5026 #define PWR_CSR2_WUPF4 0x00000008U
5027 #define PWR_CSR2_WUPF5 0x00000010U
5028 #define PWR_CSR2_WUPF6 0x00000020U
5029 #define PWR_CSR2_EWUP1 0x00000100U
5030 #define PWR_CSR2_EWUP2 0x00000200U
5031 #define PWR_CSR2_EWUP3 0x00000400U
5032 #define PWR_CSR2_EWUP4 0x00000800U
5033 #define PWR_CSR2_EWUP5 0x00001000U
5034 #define PWR_CSR2_EWUP6 0x00002000U
5036 /******************************************************************************/
5037 /* */
5038 /* QUADSPI */
5039 /* */
5040 /******************************************************************************/
5041 /* QUADSPI IP version */
5042 #define QSPI1_V1_0
5043 /***************** Bit definition for QUADSPI_CR register *******************/
5044 #define QUADSPI_CR_EN 0x00000001U
5045 #define QUADSPI_CR_ABORT 0x00000002U
5046 #define QUADSPI_CR_DMAEN 0x00000004U
5047 #define QUADSPI_CR_TCEN 0x00000008U
5048 #define QUADSPI_CR_SSHIFT 0x00000010U
5049 #define QUADSPI_CR_DFM 0x00000040U
5050 #define QUADSPI_CR_FSEL 0x00000080U
5051 #define QUADSPI_CR_FTHRES 0x00001F00U
5052 #define QUADSPI_CR_FTHRES_0 0x00000100U
5053 #define QUADSPI_CR_FTHRES_1 0x00000200U
5054 #define QUADSPI_CR_FTHRES_2 0x00000400U
5055 #define QUADSPI_CR_FTHRES_3 0x00000800U
5056 #define QUADSPI_CR_FTHRES_4 0x00001000U
5057 #define QUADSPI_CR_TEIE 0x00010000U
5058 #define QUADSPI_CR_TCIE 0x00020000U
5059 #define QUADSPI_CR_FTIE 0x00040000U
5060 #define QUADSPI_CR_SMIE 0x00080000U
5061 #define QUADSPI_CR_TOIE 0x00100000U
5062 #define QUADSPI_CR_APMS 0x00400000U
5063 #define QUADSPI_CR_PMM 0x00800000U
5064 #define QUADSPI_CR_PRESCALER 0xFF000000U
5065 #define QUADSPI_CR_PRESCALER_0 0x01000000U
5066 #define QUADSPI_CR_PRESCALER_1 0x02000000U
5067 #define QUADSPI_CR_PRESCALER_2 0x04000000U
5068 #define QUADSPI_CR_PRESCALER_3 0x08000000U
5069 #define QUADSPI_CR_PRESCALER_4 0x10000000U
5070 #define QUADSPI_CR_PRESCALER_5 0x20000000U
5071 #define QUADSPI_CR_PRESCALER_6 0x40000000U
5072 #define QUADSPI_CR_PRESCALER_7 0x80000000U
5074 /***************** Bit definition for QUADSPI_DCR register ******************/
5075 #define QUADSPI_DCR_CKMODE 0x00000001U
5076 #define QUADSPI_DCR_CSHT 0x00000700U
5077 #define QUADSPI_DCR_CSHT_0 0x00000100U
5078 #define QUADSPI_DCR_CSHT_1 0x00000200U
5079 #define QUADSPI_DCR_CSHT_2 0x00000400U
5080 #define QUADSPI_DCR_FSIZE 0x001F0000U
5081 #define QUADSPI_DCR_FSIZE_0 0x00010000U
5082 #define QUADSPI_DCR_FSIZE_1 0x00020000U
5083 #define QUADSPI_DCR_FSIZE_2 0x00040000U
5084 #define QUADSPI_DCR_FSIZE_3 0x00080000U
5085 #define QUADSPI_DCR_FSIZE_4 0x00100000U
5087 /****************** Bit definition for QUADSPI_SR register *******************/
5088 #define QUADSPI_SR_TEF 0x00000001U
5089 #define QUADSPI_SR_TCF 0x00000002U
5090 #define QUADSPI_SR_FTF 0x00000004U
5091 #define QUADSPI_SR_SMF 0x00000008U
5092 #define QUADSPI_SR_TOF 0x00000010U
5093 #define QUADSPI_SR_BUSY 0x00000020U
5094 #define QUADSPI_SR_FLEVEL 0x00001F00U
5095 #define QUADSPI_SR_FLEVEL_0 0x00000100U
5096 #define QUADSPI_SR_FLEVEL_1 0x00000200U
5097 #define QUADSPI_SR_FLEVEL_2 0x00000400U
5098 #define QUADSPI_SR_FLEVEL_3 0x00000800U
5099 #define QUADSPI_SR_FLEVEL_4 0x00001000U
5101 /****************** Bit definition for QUADSPI_FCR register ******************/
5102 #define QUADSPI_FCR_CTEF 0x00000001U
5103 #define QUADSPI_FCR_CTCF 0x00000002U
5104 #define QUADSPI_FCR_CSMF 0x00000008U
5105 #define QUADSPI_FCR_CTOF 0x00000010U
5107 /****************** Bit definition for QUADSPI_DLR register ******************/
5108 #define QUADSPI_DLR_DL 0xFFFFFFFFU
5110 /****************** Bit definition for QUADSPI_CCR register ******************/
5111 #define QUADSPI_CCR_INSTRUCTION 0x000000FFU
5112 #define QUADSPI_CCR_INSTRUCTION_0 0x00000001U
5113 #define QUADSPI_CCR_INSTRUCTION_1 0x00000002U
5114 #define QUADSPI_CCR_INSTRUCTION_2 0x00000004U
5115 #define QUADSPI_CCR_INSTRUCTION_3 0x00000008U
5116 #define QUADSPI_CCR_INSTRUCTION_4 0x00000010U
5117 #define QUADSPI_CCR_INSTRUCTION_5 0x00000020U
5118 #define QUADSPI_CCR_INSTRUCTION_6 0x00000040U
5119 #define QUADSPI_CCR_INSTRUCTION_7 0x00000080U
5120 #define QUADSPI_CCR_IMODE 0x00000300U
5121 #define QUADSPI_CCR_IMODE_0 0x00000100U
5122 #define QUADSPI_CCR_IMODE_1 0x00000200U
5123 #define QUADSPI_CCR_ADMODE 0x00000C00U
5124 #define QUADSPI_CCR_ADMODE_0 0x00000400U
5125 #define QUADSPI_CCR_ADMODE_1 0x00000800U
5126 #define QUADSPI_CCR_ADSIZE 0x00003000U
5127 #define QUADSPI_CCR_ADSIZE_0 0x00001000U
5128 #define QUADSPI_CCR_ADSIZE_1 0x00002000U
5129 #define QUADSPI_CCR_ABMODE 0x0000C000U
5130 #define QUADSPI_CCR_ABMODE_0 0x00004000U
5131 #define QUADSPI_CCR_ABMODE_1 0x00008000U
5132 #define QUADSPI_CCR_ABSIZE 0x00030000U
5133 #define QUADSPI_CCR_ABSIZE_0 0x00010000U
5134 #define QUADSPI_CCR_ABSIZE_1 0x00020000U
5135 #define QUADSPI_CCR_DCYC 0x007C0000U
5136 #define QUADSPI_CCR_DCYC_0 0x00040000U
5137 #define QUADSPI_CCR_DCYC_1 0x00080000U
5138 #define QUADSPI_CCR_DCYC_2 0x00100000U
5139 #define QUADSPI_CCR_DCYC_3 0x00200000U
5140 #define QUADSPI_CCR_DCYC_4 0x00400000U
5141 #define QUADSPI_CCR_DMODE 0x03000000U
5142 #define QUADSPI_CCR_DMODE_0 0x01000000U
5143 #define QUADSPI_CCR_DMODE_1 0x02000000U
5144 #define QUADSPI_CCR_FMODE 0x0C000000U
5145 #define QUADSPI_CCR_FMODE_0 0x04000000U
5146 #define QUADSPI_CCR_FMODE_1 0x08000000U
5147 #define QUADSPI_CCR_SIOO 0x10000000U
5148 #define QUADSPI_CCR_DHHC 0x40000000U
5149 #define QUADSPI_CCR_DDRM 0x80000000U
5150 /****************** Bit definition for QUADSPI_AR register *******************/
5151 #define QUADSPI_AR_ADDRESS 0xFFFFFFFFU
5153 /****************** Bit definition for QUADSPI_ABR register ******************/
5154 #define QUADSPI_ABR_ALTERNATE 0xFFFFFFFFU
5156 /****************** Bit definition for QUADSPI_DR register *******************/
5157 #define QUADSPI_DR_DATA 0xFFFFFFFFU
5159 /****************** Bit definition for QUADSPI_PSMKR register ****************/
5160 #define QUADSPI_PSMKR_MASK 0xFFFFFFFFU
5162 /****************** Bit definition for QUADSPI_PSMAR register ****************/
5163 #define QUADSPI_PSMAR_MATCH 0xFFFFFFFFU
5165 /****************** Bit definition for QUADSPI_PIR register *****************/
5166 #define QUADSPI_PIR_INTERVAL 0x0000FFFFU
5168 /****************** Bit definition for QUADSPI_LPTR register *****************/
5169 #define QUADSPI_LPTR_TIMEOUT 0x0000FFFFU
5171 /******************************************************************************/
5172 /* */
5173 /* Reset and Clock Control */
5174 /* */
5175 /******************************************************************************/
5176 /******************** Bit definition for RCC_CR register ********************/
5177 #define RCC_CR_HSION 0x00000001U
5178 #define RCC_CR_HSIRDY 0x00000002U
5179 #define RCC_CR_HSITRIM 0x000000F8U
5180 #define RCC_CR_HSITRIM_0 0x00000008U
5181 #define RCC_CR_HSITRIM_1 0x00000010U
5182 #define RCC_CR_HSITRIM_2 0x00000020U
5183 #define RCC_CR_HSITRIM_3 0x00000040U
5184 #define RCC_CR_HSITRIM_4 0x00000080U
5185 #define RCC_CR_HSICAL 0x0000FF00U
5186 #define RCC_CR_HSICAL_0 0x00000100U
5187 #define RCC_CR_HSICAL_1 0x00000200U
5188 #define RCC_CR_HSICAL_2 0x00000400U
5189 #define RCC_CR_HSICAL_3 0x00000800U
5190 #define RCC_CR_HSICAL_4 0x00001000U
5191 #define RCC_CR_HSICAL_5 0x00002000U
5192 #define RCC_CR_HSICAL_6 0x00004000U
5193 #define RCC_CR_HSICAL_7 0x00008000U
5194 #define RCC_CR_HSEON 0x00010000U
5195 #define RCC_CR_HSERDY 0x00020000U
5196 #define RCC_CR_HSEBYP 0x00040000U
5197 #define RCC_CR_CSSON 0x00080000U
5198 #define RCC_CR_PLLON 0x01000000U
5199 #define RCC_CR_PLLRDY 0x02000000U
5200 #define RCC_CR_PLLI2SON 0x04000000U
5201 #define RCC_CR_PLLI2SRDY 0x08000000U
5202 #define RCC_CR_PLLSAION 0x10000000U
5203 #define RCC_CR_PLLSAIRDY 0x20000000U
5204 
5205 /******************** Bit definition for RCC_PLLCFGR register ***************/
5206 #define RCC_PLLCFGR_PLLM 0x0000003FU
5207 #define RCC_PLLCFGR_PLLM_0 0x00000001U
5208 #define RCC_PLLCFGR_PLLM_1 0x00000002U
5209 #define RCC_PLLCFGR_PLLM_2 0x00000004U
5210 #define RCC_PLLCFGR_PLLM_3 0x00000008U
5211 #define RCC_PLLCFGR_PLLM_4 0x00000010U
5212 #define RCC_PLLCFGR_PLLM_5 0x00000020U
5213 #define RCC_PLLCFGR_PLLN 0x00007FC0U
5214 #define RCC_PLLCFGR_PLLN_0 0x00000040U
5215 #define RCC_PLLCFGR_PLLN_1 0x00000080U
5216 #define RCC_PLLCFGR_PLLN_2 0x00000100U
5217 #define RCC_PLLCFGR_PLLN_3 0x00000200U
5218 #define RCC_PLLCFGR_PLLN_4 0x00000400U
5219 #define RCC_PLLCFGR_PLLN_5 0x00000800U
5220 #define RCC_PLLCFGR_PLLN_6 0x00001000U
5221 #define RCC_PLLCFGR_PLLN_7 0x00002000U
5222 #define RCC_PLLCFGR_PLLN_8 0x00004000U
5223 #define RCC_PLLCFGR_PLLP 0x00030000U
5224 #define RCC_PLLCFGR_PLLP_0 0x00010000U
5225 #define RCC_PLLCFGR_PLLP_1 0x00020000U
5226 #define RCC_PLLCFGR_PLLSRC 0x00400000U
5227 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
5228 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
5229 #define RCC_PLLCFGR_PLLQ 0x0F000000U
5230 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
5231 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
5232 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
5233 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
5234 
5235 
5236 /******************** Bit definition for RCC_CFGR register ******************/
5238 #define RCC_CFGR_SW 0x00000003U
5239 #define RCC_CFGR_SW_0 0x00000001U
5240 #define RCC_CFGR_SW_1 0x00000002U
5241 #define RCC_CFGR_SW_HSI 0x00000000U
5242 #define RCC_CFGR_SW_HSE 0x00000001U
5243 #define RCC_CFGR_SW_PLL 0x00000002U
5246 #define RCC_CFGR_SWS 0x0000000CU
5247 #define RCC_CFGR_SWS_0 0x00000004U
5248 #define RCC_CFGR_SWS_1 0x00000008U
5249 #define RCC_CFGR_SWS_HSI 0x00000000U
5250 #define RCC_CFGR_SWS_HSE 0x00000004U
5251 #define RCC_CFGR_SWS_PLL 0x00000008U
5254 #define RCC_CFGR_HPRE 0x000000F0U
5255 #define RCC_CFGR_HPRE_0 0x00000010U
5256 #define RCC_CFGR_HPRE_1 0x00000020U
5257 #define RCC_CFGR_HPRE_2 0x00000040U
5258 #define RCC_CFGR_HPRE_3 0x00000080U
5260 #define RCC_CFGR_HPRE_DIV1 0x00000000U
5261 #define RCC_CFGR_HPRE_DIV2 0x00000080U
5262 #define RCC_CFGR_HPRE_DIV4 0x00000090U
5263 #define RCC_CFGR_HPRE_DIV8 0x000000A0U
5264 #define RCC_CFGR_HPRE_DIV16 0x000000B0U
5265 #define RCC_CFGR_HPRE_DIV64 0x000000C0U
5266 #define RCC_CFGR_HPRE_DIV128 0x000000D0U
5267 #define RCC_CFGR_HPRE_DIV256 0x000000E0U
5268 #define RCC_CFGR_HPRE_DIV512 0x000000F0U
5271 #define RCC_CFGR_PPRE1 0x00001C00U
5272 #define RCC_CFGR_PPRE1_0 0x00000400U
5273 #define RCC_CFGR_PPRE1_1 0x00000800U
5274 #define RCC_CFGR_PPRE1_2 0x00001000U
5276 #define RCC_CFGR_PPRE1_DIV1 0x00000000U
5277 #define RCC_CFGR_PPRE1_DIV2 0x00001000U
5278 #define RCC_CFGR_PPRE1_DIV4 0x00001400U
5279 #define RCC_CFGR_PPRE1_DIV8 0x00001800U
5280 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U
5283 #define RCC_CFGR_PPRE2 0x0000E000U
5284 #define RCC_CFGR_PPRE2_0 0x00002000U
5285 #define RCC_CFGR_PPRE2_1 0x00004000U
5286 #define RCC_CFGR_PPRE2_2 0x00008000U
5288 #define RCC_CFGR_PPRE2_DIV1 0x00000000U
5289 #define RCC_CFGR_PPRE2_DIV2 0x00008000U
5290 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U
5291 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U
5292 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U
5295 #define RCC_CFGR_RTCPRE 0x001F0000U
5296 #define RCC_CFGR_RTCPRE_0 0x00010000U
5297 #define RCC_CFGR_RTCPRE_1 0x00020000U
5298 #define RCC_CFGR_RTCPRE_2 0x00040000U
5299 #define RCC_CFGR_RTCPRE_3 0x00080000U
5300 #define RCC_CFGR_RTCPRE_4 0x00100000U
5301 
5303 #define RCC_CFGR_MCO1 0x00600000U
5304 #define RCC_CFGR_MCO1_0 0x00200000U
5305 #define RCC_CFGR_MCO1_1 0x00400000U
5306 
5307 #define RCC_CFGR_I2SSRC 0x00800000U
5308 
5309 #define RCC_CFGR_MCO1PRE 0x07000000U
5310 #define RCC_CFGR_MCO1PRE_0 0x01000000U
5311 #define RCC_CFGR_MCO1PRE_1 0x02000000U
5312 #define RCC_CFGR_MCO1PRE_2 0x04000000U
5313 
5314 #define RCC_CFGR_MCO2PRE 0x38000000U
5315 #define RCC_CFGR_MCO2PRE_0 0x08000000U
5316 #define RCC_CFGR_MCO2PRE_1 0x10000000U
5317 #define RCC_CFGR_MCO2PRE_2 0x20000000U
5318 
5319 #define RCC_CFGR_MCO2 0xC0000000U
5320 #define RCC_CFGR_MCO2_0 0x40000000U
5321 #define RCC_CFGR_MCO2_1 0x80000000U
5322 
5323 /******************** Bit definition for RCC_CIR register *******************/
5324 #define RCC_CIR_LSIRDYF 0x00000001U
5325 #define RCC_CIR_LSERDYF 0x00000002U
5326 #define RCC_CIR_HSIRDYF 0x00000004U
5327 #define RCC_CIR_HSERDYF 0x00000008U
5328 #define RCC_CIR_PLLRDYF 0x00000010U
5329 #define RCC_CIR_PLLI2SRDYF 0x00000020U
5330 #define RCC_CIR_PLLSAIRDYF 0x00000040U
5331 #define RCC_CIR_CSSF 0x00000080U
5332 #define RCC_CIR_LSIRDYIE 0x00000100U
5333 #define RCC_CIR_LSERDYIE 0x00000200U
5334 #define RCC_CIR_HSIRDYIE 0x00000400U
5335 #define RCC_CIR_HSERDYIE 0x00000800U
5336 #define RCC_CIR_PLLRDYIE 0x00001000U
5337 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
5338 #define RCC_CIR_PLLSAIRDYIE 0x00004000U
5339 #define RCC_CIR_LSIRDYC 0x00010000U
5340 #define RCC_CIR_LSERDYC 0x00020000U
5341 #define RCC_CIR_HSIRDYC 0x00040000U
5342 #define RCC_CIR_HSERDYC 0x00080000U
5343 #define RCC_CIR_PLLRDYC 0x00100000U
5344 #define RCC_CIR_PLLI2SRDYC 0x00200000U
5345 #define RCC_CIR_PLLSAIRDYC 0x00400000U
5346 #define RCC_CIR_CSSC 0x00800000U
5347 
5348 /******************** Bit definition for RCC_AHB1RSTR register **************/
5349 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
5350 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
5351 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
5352 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
5353 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
5354 #define RCC_AHB1RSTR_GPIOFRST 0x00000020U
5355 #define RCC_AHB1RSTR_GPIOGRST 0x00000040U
5356 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
5357 #define RCC_AHB1RSTR_GPIOIRST 0x00000100U
5358 #define RCC_AHB1RSTR_GPIOJRST 0x00000200U
5359 #define RCC_AHB1RSTR_GPIOKRST 0x00000400U
5360 #define RCC_AHB1RSTR_CRCRST 0x00001000U
5361 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
5362 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
5363 #define RCC_AHB1RSTR_DMA2DRST 0x00800000U
5364 #define RCC_AHB1RSTR_ETHMACRST 0x02000000U
5365 #define RCC_AHB1RSTR_OTGHRST 0x20000000U
5366 
5367 /******************** Bit definition for RCC_AHB2RSTR register **************/
5368 #define RCC_AHB2RSTR_DCMIRST 0x00000001U
5369 #define RCC_AHB2RSTR_RNGRST 0x00000040U
5370 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
5371 
5372 /******************** Bit definition for RCC_AHB3RSTR register **************/
5373 
5374 #define RCC_AHB3RSTR_FMCRST 0x00000001U
5375 #define RCC_AHB3RSTR_QSPIRST 0x00000002U
5376 
5377 /******************** Bit definition for RCC_APB1RSTR register **************/
5378 #define RCC_APB1RSTR_TIM2RST 0x00000001U
5379 #define RCC_APB1RSTR_TIM3RST 0x00000002U
5380 #define RCC_APB1RSTR_TIM4RST 0x00000004U
5381 #define RCC_APB1RSTR_TIM5RST 0x00000008U
5382 #define RCC_APB1RSTR_TIM6RST 0x00000010U
5383 #define RCC_APB1RSTR_TIM7RST 0x00000020U
5384 #define RCC_APB1RSTR_TIM12RST 0x00000040U
5385 #define RCC_APB1RSTR_TIM13RST 0x00000080U
5386 #define RCC_APB1RSTR_TIM14RST 0x00000100U
5387 #define RCC_APB1RSTR_LPTIM1RST 0x00000200U
5388 #define RCC_APB1RSTR_WWDGRST 0x00000800U
5389 #define RCC_APB1RSTR_SPI2RST 0x00004000U
5390 #define RCC_APB1RSTR_SPI3RST 0x00008000U
5391 #define RCC_APB1RSTR_SPDIFRXRST 0x00010000U
5392 #define RCC_APB1RSTR_USART2RST 0x00020000U
5393 #define RCC_APB1RSTR_USART3RST 0x00040000U
5394 #define RCC_APB1RSTR_UART4RST 0x00080000U
5395 #define RCC_APB1RSTR_UART5RST 0x00100000U
5396 #define RCC_APB1RSTR_I2C1RST 0x00200000U
5397 #define RCC_APB1RSTR_I2C2RST 0x00400000U
5398 #define RCC_APB1RSTR_I2C3RST 0x00800000U
5399 #define RCC_APB1RSTR_I2C4RST 0x01000000U
5400 #define RCC_APB1RSTR_CAN1RST 0x02000000U
5401 #define RCC_APB1RSTR_CAN2RST 0x04000000U
5402 #define RCC_APB1RSTR_CECRST 0x08000000U
5403 #define RCC_APB1RSTR_PWRRST 0x10000000U
5404 #define RCC_APB1RSTR_DACRST 0x20000000U
5405 #define RCC_APB1RSTR_UART7RST 0x40000000U
5406 #define RCC_APB1RSTR_UART8RST 0x80000000U
5407 
5408 /******************** Bit definition for RCC_APB2RSTR register **************/
5409 #define RCC_APB2RSTR_TIM1RST 0x00000001U
5410 #define RCC_APB2RSTR_TIM8RST 0x00000002U
5411 #define RCC_APB2RSTR_USART1RST 0x00000010U
5412 #define RCC_APB2RSTR_USART6RST 0x00000020U
5413 #define RCC_APB2RSTR_ADCRST 0x00000100U
5414 #define RCC_APB2RSTR_SDMMC1RST 0x00000800U
5415 #define RCC_APB2RSTR_SPI1RST 0x00001000U
5416 #define RCC_APB2RSTR_SPI4RST 0x00002000U
5417 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
5418 #define RCC_APB2RSTR_TIM9RST 0x00010000U
5419 #define RCC_APB2RSTR_TIM10RST 0x00020000U
5420 #define RCC_APB2RSTR_TIM11RST 0x00040000U
5421 #define RCC_APB2RSTR_SPI5RST 0x00100000U
5422 #define RCC_APB2RSTR_SPI6RST 0x00200000U
5423 #define RCC_APB2RSTR_SAI1RST 0x00400000U
5424 #define RCC_APB2RSTR_SAI2RST 0x00800000U
5425 
5426 /******************** Bit definition for RCC_AHB1ENR register ***************/
5427 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
5428 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
5429 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
5430 #define RCC_AHB1ENR_GPIODEN 0x00000008U
5431 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
5432 #define RCC_AHB1ENR_GPIOFEN 0x00000020U
5433 #define RCC_AHB1ENR_GPIOGEN 0x00000040U
5434 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
5435 #define RCC_AHB1ENR_GPIOIEN 0x00000100U
5436 #define RCC_AHB1ENR_GPIOJEN 0x00000200U
5437 #define RCC_AHB1ENR_GPIOKEN 0x00000400U
5438 #define RCC_AHB1ENR_CRCEN 0x00001000U
5439 #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
5440 #define RCC_AHB1ENR_DTCMRAMEN 0x00100000U
5441 #define RCC_AHB1ENR_DMA1EN 0x00200000U
5442 #define RCC_AHB1ENR_DMA2EN 0x00400000U
5443 #define RCC_AHB1ENR_DMA2DEN 0x00800000U
5444 #define RCC_AHB1ENR_ETHMACEN 0x02000000U
5445 #define RCC_AHB1ENR_ETHMACTXEN 0x04000000U
5446 #define RCC_AHB1ENR_ETHMACRXEN 0x08000000U
5447 #define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U
5448 #define RCC_AHB1ENR_OTGHSEN 0x20000000U
5449 #define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
5450 
5451 /******************** Bit definition for RCC_AHB2ENR register ***************/
5452 #define RCC_AHB2ENR_DCMIEN 0x00000001U
5453 #define RCC_AHB2ENR_RNGEN 0x00000040U
5454 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
5455 
5456 /******************** Bit definition for RCC_AHB3ENR register ***************/
5457 #define RCC_AHB3ENR_FMCEN 0x00000001U
5458 #define RCC_AHB3ENR_QSPIEN 0x00000002U
5459 
5460 /******************** Bit definition for RCC_APB1ENR register ***************/
5461 #define RCC_APB1ENR_TIM2EN 0x00000001U
5462 #define RCC_APB1ENR_TIM3EN 0x00000002U
5463 #define RCC_APB1ENR_TIM4EN 0x00000004U
5464 #define RCC_APB1ENR_TIM5EN 0x00000008U
5465 #define RCC_APB1ENR_TIM6EN 0x00000010U
5466 #define RCC_APB1ENR_TIM7EN 0x00000020U
5467 #define RCC_APB1ENR_TIM12EN 0x00000040U
5468 #define RCC_APB1ENR_TIM13EN 0x00000080U
5469 #define RCC_APB1ENR_TIM14EN 0x00000100U
5470 #define RCC_APB1ENR_LPTIM1EN 0x00000200U
5471 #define RCC_APB1ENR_WWDGEN 0x00000800U
5472 #define RCC_APB1ENR_SPI2EN 0x00004000U
5473 #define RCC_APB1ENR_SPI3EN 0x00008000U
5474 #define RCC_APB1ENR_SPDIFRXEN 0x00010000U
5475 #define RCC_APB1ENR_USART2EN 0x00020000U
5476 #define RCC_APB1ENR_USART3EN 0x00040000U
5477 #define RCC_APB1ENR_UART4EN 0x00080000U
5478 #define RCC_APB1ENR_UART5EN 0x00100000U
5479 #define RCC_APB1ENR_I2C1EN 0x00200000U
5480 #define RCC_APB1ENR_I2C2EN 0x00400000U
5481 #define RCC_APB1ENR_I2C3EN 0x00800000U
5482 #define RCC_APB1ENR_I2C4EN 0x01000000U
5483 #define RCC_APB1ENR_CAN1EN 0x02000000U
5484 #define RCC_APB1ENR_CAN2EN 0x04000000U
5485 #define RCC_APB1ENR_CECEN 0x08000000U
5486 #define RCC_APB1ENR_PWREN 0x10000000U
5487 #define RCC_APB1ENR_DACEN 0x20000000U
5488 #define RCC_APB1ENR_UART7EN 0x40000000U
5489 #define RCC_APB1ENR_UART8EN 0x80000000U
5490 
5491 /******************** Bit definition for RCC_APB2ENR register ***************/
5492 #define RCC_APB2ENR_TIM1EN 0x00000001U
5493 #define RCC_APB2ENR_TIM8EN 0x00000002U
5494 #define RCC_APB2ENR_USART1EN 0x00000010U
5495 #define RCC_APB2ENR_USART6EN 0x00000020U
5496 #define RCC_APB2ENR_ADC1EN 0x00000100U
5497 #define RCC_APB2ENR_ADC2EN 0x00000200U
5498 #define RCC_APB2ENR_ADC3EN 0x00000400U
5499 #define RCC_APB2ENR_SDMMC1EN 0x00000800U
5500 #define RCC_APB2ENR_SPI1EN 0x00001000U
5501 #define RCC_APB2ENR_SPI4EN 0x00002000U
5502 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
5503 #define RCC_APB2ENR_TIM9EN 0x00010000U
5504 #define RCC_APB2ENR_TIM10EN 0x00020000U
5505 #define RCC_APB2ENR_TIM11EN 0x00040000U
5506 #define RCC_APB2ENR_SPI5EN 0x00100000U
5507 #define RCC_APB2ENR_SPI6EN 0x00200000U
5508 #define RCC_APB2ENR_SAI1EN 0x00400000U
5509 #define RCC_APB2ENR_SAI2EN 0x00800000U
5510 
5511 /******************** Bit definition for RCC_AHB1LPENR register *************/
5512 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
5513 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
5514 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
5515 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
5516 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
5517 #define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
5518 #define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
5519 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
5520 #define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
5521 #define RCC_AHB1LPENR_GPIOJLPEN 0x00000200U
5522 #define RCC_AHB1LPENR_GPIOKLPEN 0x00000400U
5523 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
5524 #define RCC_AHB1LPENR_AXILPEN 0x00002000U
5525 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
5526 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
5527 #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
5528 #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
5529 #define RCC_AHB1LPENR_DTCMLPEN 0x00100000U
5530 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
5531 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
5532 #define RCC_AHB1LPENR_DMA2DLPEN 0x00800000U
5533 #define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U
5534 #define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U
5535 #define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U
5536 #define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U
5537 #define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
5538 #define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
5539 
5540 /******************** Bit definition for RCC_AHB2LPENR register *************/
5541 #define RCC_AHB2LPENR_DCMILPEN 0x00000001U
5542 #define RCC_AHB2LPENR_RNGLPEN 0x00000040U
5543 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
5544 
5545 /******************** Bit definition for RCC_AHB3LPENR register *************/
5546 #define RCC_AHB3LPENR_FMCLPEN 0x00000001U
5547 #define RCC_AHB3LPENR_QSPILPEN 0x00000002U
5548 /******************** Bit definition for RCC_APB1LPENR register *************/
5549 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
5550 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
5551 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
5552 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
5553 #define RCC_APB1LPENR_TIM6LPEN 0x00000010U
5554 #define RCC_APB1LPENR_TIM7LPEN 0x00000020U
5555 #define RCC_APB1LPENR_TIM12LPEN 0x00000040U
5556 #define RCC_APB1LPENR_TIM13LPEN 0x00000080U
5557 #define RCC_APB1LPENR_TIM14LPEN 0x00000100U
5558 #define RCC_APB1LPENR_LPTIM1LPEN 0x00000200U
5559 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
5560 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
5561 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
5562 #define RCC_APB1LPENR_SPDIFRXLPEN 0x00010000U
5563 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
5564 #define RCC_APB1LPENR_USART3LPEN 0x00040000U
5565 #define RCC_APB1LPENR_UART4LPEN 0x00080000U
5566 #define RCC_APB1LPENR_UART5LPEN 0x00100000U
5567 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
5568 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
5569 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
5570 #define RCC_APB1LPENR_I2C4LPEN 0x01000000U
5571 #define RCC_APB1LPENR_CAN1LPEN 0x02000000U
5572 #define RCC_APB1LPENR_CAN2LPEN 0x04000000U
5573 #define RCC_APB1LPENR_CECLPEN 0x08000000U
5574 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
5575 #define RCC_APB1LPENR_DACLPEN 0x20000000U
5576 #define RCC_APB1LPENR_UART7LPEN 0x40000000U
5577 #define RCC_APB1LPENR_UART8LPEN 0x80000000U
5578 
5579 /******************** Bit definition for RCC_APB2LPENR register *************/
5580 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
5581 #define RCC_APB2LPENR_TIM8LPEN 0x00000002U
5582 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
5583 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
5584 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
5585 #define RCC_APB2LPENR_ADC2LPEN 0x00000200U
5586 #define RCC_APB2LPENR_ADC3LPEN 0x00000400U
5587 #define RCC_APB2LPENR_SDMMC1LPEN 0x00000800U
5588 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
5589 #define RCC_APB2LPENR_SPI4LPEN 0x00002000U
5590 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
5591 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
5592 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
5593 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
5594 #define RCC_APB2LPENR_SPI5LPEN 0x00100000U
5595 #define RCC_APB2LPENR_SPI6LPEN 0x00200000U
5596 #define RCC_APB2LPENR_SAI1LPEN 0x00400000U
5597 #define RCC_APB2LPENR_SAI2LPEN 0x00800000U
5598 
5599 /******************** Bit definition for RCC_BDCR register ******************/
5600 #define RCC_BDCR_LSEON 0x00000001U
5601 #define RCC_BDCR_LSERDY 0x00000002U
5602 #define RCC_BDCR_LSEBYP 0x00000004U
5603 #define RCC_BDCR_LSEDRV 0x00000018U
5604 #define RCC_BDCR_LSEDRV_0 0x00000008U
5605 #define RCC_BDCR_LSEDRV_1 0x00000010U
5606 #define RCC_BDCR_RTCSEL 0x00000300U
5607 #define RCC_BDCR_RTCSEL_0 0x00000100U
5608 #define RCC_BDCR_RTCSEL_1 0x00000200U
5609 #define RCC_BDCR_RTCEN 0x00008000U
5610 #define RCC_BDCR_BDRST 0x00010000U
5611 
5612 /******************** Bit definition for RCC_CSR register *******************/
5613 #define RCC_CSR_LSION 0x00000001U
5614 #define RCC_CSR_LSIRDY 0x00000002U
5615 #define RCC_CSR_RMVF 0x01000000U
5616 #define RCC_CSR_BORRSTF 0x02000000U
5617 #define RCC_CSR_PINRSTF 0x04000000U
5618 #define RCC_CSR_PORRSTF 0x08000000U
5619 #define RCC_CSR_SFTRSTF 0x10000000U
5620 #define RCC_CSR_IWDGRSTF 0x20000000U
5621 #define RCC_CSR_WWDGRSTF 0x40000000U
5622 #define RCC_CSR_LPWRRSTF 0x80000000U
5623 
5624 /******************** Bit definition for RCC_SSCGR register *****************/
5625 #define RCC_SSCGR_MODPER 0x00001FFFU
5626 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
5627 #define RCC_SSCGR_SPREADSEL 0x40000000U
5628 #define RCC_SSCGR_SSCGEN 0x80000000U
5629 
5630 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
5631 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
5632 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
5633 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
5634 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
5635 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
5636 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
5637 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
5638 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
5639 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
5640 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
5641 #define RCC_PLLI2SCFGR_PLLI2SP 0x00030000U
5642 #define RCC_PLLI2SCFGR_PLLI2SP_0 0x00010000U
5643 #define RCC_PLLI2SCFGR_PLLI2SP_1 0x00020000U
5644 #define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
5645 #define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
5646 #define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
5647 #define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
5648 #define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
5649 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
5650 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
5651 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
5652 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
5653 
5654 /******************** Bit definition for RCC_PLLSAICFGR register ************/
5655 #define RCC_PLLSAICFGR_PLLSAIN 0x00007FC0U
5656 #define RCC_PLLSAICFGR_PLLSAIN_0 0x00000040U
5657 #define RCC_PLLSAICFGR_PLLSAIN_1 0x00000080U
5658 #define RCC_PLLSAICFGR_PLLSAIN_2 0x00000100U
5659 #define RCC_PLLSAICFGR_PLLSAIN_3 0x00000200U
5660 #define RCC_PLLSAICFGR_PLLSAIN_4 0x00000400U
5661 #define RCC_PLLSAICFGR_PLLSAIN_5 0x00000800U
5662 #define RCC_PLLSAICFGR_PLLSAIN_6 0x00001000U
5663 #define RCC_PLLSAICFGR_PLLSAIN_7 0x00002000U
5664 #define RCC_PLLSAICFGR_PLLSAIN_8 0x00004000U
5665 #define RCC_PLLSAICFGR_PLLSAIP 0x00030000U
5666 #define RCC_PLLSAICFGR_PLLSAIP_0 0x00010000U
5667 #define RCC_PLLSAICFGR_PLLSAIP_1 0x00020000U
5668 #define RCC_PLLSAICFGR_PLLSAIQ 0x0F000000U
5669 #define RCC_PLLSAICFGR_PLLSAIQ_0 0x01000000U
5670 #define RCC_PLLSAICFGR_PLLSAIQ_1 0x02000000U
5671 #define RCC_PLLSAICFGR_PLLSAIQ_2 0x04000000U
5672 #define RCC_PLLSAICFGR_PLLSAIQ_3 0x08000000U
5673 #define RCC_PLLSAICFGR_PLLSAIR 0x70000000U
5674 #define RCC_PLLSAICFGR_PLLSAIR_0 0x10000000U
5675 #define RCC_PLLSAICFGR_PLLSAIR_1 0x20000000U
5676 #define RCC_PLLSAICFGR_PLLSAIR_2 0x40000000U
5677 
5678 /******************** Bit definition for RCC_DCKCFGR1 register ***************/
5679 #define RCC_DCKCFGR1_PLLI2SDIVQ 0x0000001FU
5680 #define RCC_DCKCFGR1_PLLI2SDIVQ_0 0x00000001U
5681 #define RCC_DCKCFGR1_PLLI2SDIVQ_1 0x00000002U
5682 #define RCC_DCKCFGR1_PLLI2SDIVQ_2 0x00000004U
5683 #define RCC_DCKCFGR1_PLLI2SDIVQ_3 0x00000008U
5684 #define RCC_DCKCFGR1_PLLI2SDIVQ_4 0x00000010U
5685 
5686 #define RCC_DCKCFGR1_PLLSAIDIVQ 0x00001F00U
5687 #define RCC_DCKCFGR1_PLLSAIDIVQ_0 0x00000100U
5688 #define RCC_DCKCFGR1_PLLSAIDIVQ_1 0x00000200U
5689 #define RCC_DCKCFGR1_PLLSAIDIVQ_2 0x00000400U
5690 #define RCC_DCKCFGR1_PLLSAIDIVQ_3 0x00000800U
5691 #define RCC_DCKCFGR1_PLLSAIDIVQ_4 0x00001000U
5692 
5693 #define RCC_DCKCFGR1_PLLSAIDIVR 0x00030000U
5694 #define RCC_DCKCFGR1_PLLSAIDIVR_0 0x00010000U
5695 #define RCC_DCKCFGR1_PLLSAIDIVR_1 0x00020000U
5696 
5697 #define RCC_DCKCFGR1_SAI1SEL 0x00300000U
5698 #define RCC_DCKCFGR1_SAI1SEL_0 0x00100000U
5699 #define RCC_DCKCFGR1_SAI1SEL_1 0x00200000U
5700 
5701 #define RCC_DCKCFGR1_SAI2SEL 0x00C00000U
5702 #define RCC_DCKCFGR1_SAI2SEL_0 0x00400000U
5703 #define RCC_DCKCFGR1_SAI2SEL_1 0x00800000U
5704 
5705 #define RCC_DCKCFGR1_TIMPRE 0x01000000U
5706 
5707 /******************** Bit definition for RCC_DCKCFGR2 register ***************/
5708 #define RCC_DCKCFGR2_USART1SEL 0x00000003U
5709 #define RCC_DCKCFGR2_USART1SEL_0 0x00000001U
5710 #define RCC_DCKCFGR2_USART1SEL_1 0x00000002U
5711 #define RCC_DCKCFGR2_USART2SEL 0x0000000CU
5712 #define RCC_DCKCFGR2_USART2SEL_0 0x00000004U
5713 #define RCC_DCKCFGR2_USART2SEL_1 0x00000008U
5714 #define RCC_DCKCFGR2_USART3SEL 0x00000030U
5715 #define RCC_DCKCFGR2_USART3SEL_0 0x00000010U
5716 #define RCC_DCKCFGR2_USART3SEL_1 0x00000020U
5717 #define RCC_DCKCFGR2_UART4SEL 0x000000C0U
5718 #define RCC_DCKCFGR2_UART4SEL_0 0x00000040U
5719 #define RCC_DCKCFGR2_UART4SEL_1 0x00000080U
5720 #define RCC_DCKCFGR2_UART5SEL 0x00000300U
5721 #define RCC_DCKCFGR2_UART5SEL_0 0x00000100U
5722 #define RCC_DCKCFGR2_UART5SEL_1 0x00000200U
5723 #define RCC_DCKCFGR2_USART6SEL 0x00000C00U
5724 #define RCC_DCKCFGR2_USART6SEL_0 0x00000400U
5725 #define RCC_DCKCFGR2_USART6SEL_1 0x00000800U
5726 #define RCC_DCKCFGR2_UART7SEL 0x00003000U
5727 #define RCC_DCKCFGR2_UART7SEL_0 0x00001000U
5728 #define RCC_DCKCFGR2_UART7SEL_1 0x00002000U
5729 #define RCC_DCKCFGR2_UART8SEL 0x0000C000U
5730 #define RCC_DCKCFGR2_UART8SEL_0 0x00004000U
5731 #define RCC_DCKCFGR2_UART8SEL_1 0x00008000U
5732 #define RCC_DCKCFGR2_I2C1SEL 0x00030000U
5733 #define RCC_DCKCFGR2_I2C1SEL_0 0x00010000U
5734 #define RCC_DCKCFGR2_I2C1SEL_1 0x00020000U
5735 #define RCC_DCKCFGR2_I2C2SEL 0x000C0000U
5736 #define RCC_DCKCFGR2_I2C2SEL_0 0x00040000U
5737 #define RCC_DCKCFGR2_I2C2SEL_1 0x00080000U
5738 #define RCC_DCKCFGR2_I2C3SEL 0x00300000U
5739 #define RCC_DCKCFGR2_I2C3SEL_0 0x00100000U
5740 #define RCC_DCKCFGR2_I2C3SEL_1 0x00200000U
5741 #define RCC_DCKCFGR2_I2C4SEL 0x00C00000U
5742 #define RCC_DCKCFGR2_I2C4SEL_0 0x00400000U
5743 #define RCC_DCKCFGR2_I2C4SEL_1 0x00800000U
5744 #define RCC_DCKCFGR2_LPTIM1SEL 0x03000000U
5745 #define RCC_DCKCFGR2_LPTIM1SEL_0 0x01000000U
5746 #define RCC_DCKCFGR2_LPTIM1SEL_1 0x02000000U
5747 #define RCC_DCKCFGR2_CECSEL 0x04000000U
5748 #define RCC_DCKCFGR2_CK48MSEL 0x08000000U
5749 #define RCC_DCKCFGR2_SDMMC1SEL 0x10000000U
5750 
5751 /******************************************************************************/
5752 /* */
5753 /* RNG */
5754 /* */
5755 /******************************************************************************/
5756 /******************** Bits definition for RNG_CR register *******************/
5757 #define RNG_CR_RNGEN 0x00000004U
5758 #define RNG_CR_IE 0x00000008U
5759 
5760 /******************** Bits definition for RNG_SR register *******************/
5761 #define RNG_SR_DRDY 0x00000001U
5762 #define RNG_SR_CECS 0x00000002U
5763 #define RNG_SR_SECS 0x00000004U
5764 #define RNG_SR_CEIS 0x00000020U
5765 #define RNG_SR_SEIS 0x00000040U
5766 
5767 /******************************************************************************/
5768 /* */
5769 /* Real-Time Clock (RTC) */
5770 /* */
5771 /******************************************************************************/
5772 /******************** Bits definition for RTC_TR register *******************/
5773 #define RTC_TR_PM 0x00400000U
5774 #define RTC_TR_HT 0x00300000U
5775 #define RTC_TR_HT_0 0x00100000U
5776 #define RTC_TR_HT_1 0x00200000U
5777 #define RTC_TR_HU 0x000F0000U
5778 #define RTC_TR_HU_0 0x00010000U
5779 #define RTC_TR_HU_1 0x00020000U
5780 #define RTC_TR_HU_2 0x00040000U
5781 #define RTC_TR_HU_3 0x00080000U
5782 #define RTC_TR_MNT 0x00007000U
5783 #define RTC_TR_MNT_0 0x00001000U
5784 #define RTC_TR_MNT_1 0x00002000U
5785 #define RTC_TR_MNT_2 0x00004000U
5786 #define RTC_TR_MNU 0x00000F00U
5787 #define RTC_TR_MNU_0 0x00000100U
5788 #define RTC_TR_MNU_1 0x00000200U
5789 #define RTC_TR_MNU_2 0x00000400U
5790 #define RTC_TR_MNU_3 0x00000800U
5791 #define RTC_TR_ST 0x00000070U
5792 #define RTC_TR_ST_0 0x00000010U
5793 #define RTC_TR_ST_1 0x00000020U
5794 #define RTC_TR_ST_2 0x00000040U
5795 #define RTC_TR_SU 0x0000000FU
5796 #define RTC_TR_SU_0 0x00000001U
5797 #define RTC_TR_SU_1 0x00000002U
5798 #define RTC_TR_SU_2 0x00000004U
5799 #define RTC_TR_SU_3 0x00000008U
5800 
5801 /******************** Bits definition for RTC_DR register *******************/
5802 #define RTC_DR_YT 0x00F00000U
5803 #define RTC_DR_YT_0 0x00100000U
5804 #define RTC_DR_YT_1 0x00200000U
5805 #define RTC_DR_YT_2 0x00400000U
5806 #define RTC_DR_YT_3 0x00800000U
5807 #define RTC_DR_YU 0x000F0000U
5808 #define RTC_DR_YU_0 0x00010000U
5809 #define RTC_DR_YU_1 0x00020000U
5810 #define RTC_DR_YU_2 0x00040000U
5811 #define RTC_DR_YU_3 0x00080000U
5812 #define RTC_DR_WDU 0x0000E000U
5813 #define RTC_DR_WDU_0 0x00002000U
5814 #define RTC_DR_WDU_1 0x00004000U
5815 #define RTC_DR_WDU_2 0x00008000U
5816 #define RTC_DR_MT 0x00001000U
5817 #define RTC_DR_MU 0x00000F00U
5818 #define RTC_DR_MU_0 0x00000100U
5819 #define RTC_DR_MU_1 0x00000200U
5820 #define RTC_DR_MU_2 0x00000400U
5821 #define RTC_DR_MU_3 0x00000800U
5822 #define RTC_DR_DT 0x00000030U
5823 #define RTC_DR_DT_0 0x00000010U
5824 #define RTC_DR_DT_1 0x00000020U
5825 #define RTC_DR_DU 0x0000000FU
5826 #define RTC_DR_DU_0 0x00000001U
5827 #define RTC_DR_DU_1 0x00000002U
5828 #define RTC_DR_DU_2 0x00000004U
5829 #define RTC_DR_DU_3 0x00000008U
5830 
5831 /******************** Bits definition for RTC_CR register *******************/
5832 #define RTC_CR_ITSE 0x01000000U
5833 #define RTC_CR_COE 0x00800000U
5834 #define RTC_CR_OSEL 0x00600000U
5835 #define RTC_CR_OSEL_0 0x00200000U
5836 #define RTC_CR_OSEL_1 0x00400000U
5837 #define RTC_CR_POL 0x00100000U
5838 #define RTC_CR_COSEL 0x00080000U
5839 #define RTC_CR_BCK 0x00040000U
5840 #define RTC_CR_SUB1H 0x00020000U
5841 #define RTC_CR_ADD1H 0x00010000U
5842 #define RTC_CR_TSIE 0x00008000U
5843 #define RTC_CR_WUTIE 0x00004000U
5844 #define RTC_CR_ALRBIE 0x00002000U
5845 #define RTC_CR_ALRAIE 0x00001000U
5846 #define RTC_CR_TSE 0x00000800U
5847 #define RTC_CR_WUTE 0x00000400U
5848 #define RTC_CR_ALRBE 0x00000200U
5849 #define RTC_CR_ALRAE 0x00000100U
5850 #define RTC_CR_FMT 0x00000040U
5851 #define RTC_CR_BYPSHAD 0x00000020U
5852 #define RTC_CR_REFCKON 0x00000010U
5853 #define RTC_CR_TSEDGE 0x00000008U
5854 #define RTC_CR_WUCKSEL 0x00000007U
5855 #define RTC_CR_WUCKSEL_0 0x00000001U
5856 #define RTC_CR_WUCKSEL_1 0x00000002U
5857 #define RTC_CR_WUCKSEL_2 0x00000004U
5858 
5859 /******************** Bits definition for RTC_ISR register ******************/
5860 #define RTC_ISR_ITSF 0x00020000U
5861 #define RTC_ISR_RECALPF 0x00010000U
5862 #define RTC_ISR_TAMP3F 0x00008000U
5863 #define RTC_ISR_TAMP2F 0x00004000U
5864 #define RTC_ISR_TAMP1F 0x00002000U
5865 #define RTC_ISR_TSOVF 0x00001000U
5866 #define RTC_ISR_TSF 0x00000800U
5867 #define RTC_ISR_WUTF 0x00000400U
5868 #define RTC_ISR_ALRBF 0x00000200U
5869 #define RTC_ISR_ALRAF 0x00000100U
5870 #define RTC_ISR_INIT 0x00000080U
5871 #define RTC_ISR_INITF 0x00000040U
5872 #define RTC_ISR_RSF 0x00000020U
5873 #define RTC_ISR_INITS 0x00000010U
5874 #define RTC_ISR_SHPF 0x00000008U
5875 #define RTC_ISR_WUTWF 0x00000004U
5876 #define RTC_ISR_ALRBWF 0x00000002U
5877 #define RTC_ISR_ALRAWF 0x00000001U
5878 
5879 /******************** Bits definition for RTC_PRER register *****************/
5880 #define RTC_PRER_PREDIV_A 0x007F0000U
5881 #define RTC_PRER_PREDIV_S 0x00007FFFU
5882 
5883 /******************** Bits definition for RTC_WUTR register *****************/
5884 #define RTC_WUTR_WUT 0x0000FFFFU
5885 
5886 /******************** Bits definition for RTC_ALRMAR register ***************/
5887 #define RTC_ALRMAR_MSK4 0x80000000U
5888 #define RTC_ALRMAR_WDSEL 0x40000000U
5889 #define RTC_ALRMAR_DT 0x30000000U
5890 #define RTC_ALRMAR_DT_0 0x10000000U
5891 #define RTC_ALRMAR_DT_1 0x20000000U
5892 #define RTC_ALRMAR_DU 0x0F000000U
5893 #define RTC_ALRMAR_DU_0 0x01000000U
5894 #define RTC_ALRMAR_DU_1 0x02000000U
5895 #define RTC_ALRMAR_DU_2 0x04000000U
5896 #define RTC_ALRMAR_DU_3 0x08000000U
5897 #define RTC_ALRMAR_MSK3 0x00800000U
5898 #define RTC_ALRMAR_PM 0x00400000U
5899 #define RTC_ALRMAR_HT 0x00300000U
5900 #define RTC_ALRMAR_HT_0 0x00100000U
5901 #define RTC_ALRMAR_HT_1 0x00200000U
5902 #define RTC_ALRMAR_HU 0x000F0000U
5903 #define RTC_ALRMAR_HU_0 0x00010000U
5904 #define RTC_ALRMAR_HU_1 0x00020000U
5905 #define RTC_ALRMAR_HU_2 0x00040000U
5906 #define RTC_ALRMAR_HU_3 0x00080000U
5907 #define RTC_ALRMAR_MSK2 0x00008000U
5908 #define RTC_ALRMAR_MNT 0x00007000U
5909 #define RTC_ALRMAR_MNT_0 0x00001000U
5910 #define RTC_ALRMAR_MNT_1 0x00002000U
5911 #define RTC_ALRMAR_MNT_2 0x00004000U
5912 #define RTC_ALRMAR_MNU 0x00000F00U
5913 #define RTC_ALRMAR_MNU_0 0x00000100U
5914 #define RTC_ALRMAR_MNU_1 0x00000200U
5915 #define RTC_ALRMAR_MNU_2 0x00000400U
5916 #define RTC_ALRMAR_MNU_3 0x00000800U
5917 #define RTC_ALRMAR_MSK1 0x00000080U
5918 #define RTC_ALRMAR_ST 0x00000070U
5919 #define RTC_ALRMAR_ST_0 0x00000010U
5920 #define RTC_ALRMAR_ST_1 0x00000020U
5921 #define RTC_ALRMAR_ST_2 0x00000040U
5922 #define RTC_ALRMAR_SU 0x0000000FU
5923 #define RTC_ALRMAR_SU_0 0x00000001U
5924 #define RTC_ALRMAR_SU_1 0x00000002U
5925 #define RTC_ALRMAR_SU_2 0x00000004U
5926 #define RTC_ALRMAR_SU_3 0x00000008U
5927 
5928 /******************** Bits definition for RTC_ALRMBR register ***************/
5929 #define RTC_ALRMBR_MSK4 0x80000000U
5930 #define RTC_ALRMBR_WDSEL 0x40000000U
5931 #define RTC_ALRMBR_DT 0x30000000U
5932 #define RTC_ALRMBR_DT_0 0x10000000U
5933 #define RTC_ALRMBR_DT_1 0x20000000U
5934 #define RTC_ALRMBR_DU 0x0F000000U
5935 #define RTC_ALRMBR_DU_0 0x01000000U
5936 #define RTC_ALRMBR_DU_1 0x02000000U
5937 #define RTC_ALRMBR_DU_2 0x04000000U
5938 #define RTC_ALRMBR_DU_3 0x08000000U
5939 #define RTC_ALRMBR_MSK3 0x00800000U
5940 #define RTC_ALRMBR_PM 0x00400000U
5941 #define RTC_ALRMBR_HT 0x00300000U
5942 #define RTC_ALRMBR_HT_0 0x00100000U
5943 #define RTC_ALRMBR_HT_1 0x00200000U
5944 #define RTC_ALRMBR_HU 0x000F0000U
5945 #define RTC_ALRMBR_HU_0 0x00010000U
5946 #define RTC_ALRMBR_HU_1 0x00020000U
5947 #define RTC_ALRMBR_HU_2 0x00040000U
5948 #define RTC_ALRMBR_HU_3 0x00080000U
5949 #define RTC_ALRMBR_MSK2 0x00008000U
5950 #define RTC_ALRMBR_MNT 0x00007000U
5951 #define RTC_ALRMBR_MNT_0 0x00001000U
5952 #define RTC_ALRMBR_MNT_1 0x00002000U
5953 #define RTC_ALRMBR_MNT_2 0x00004000U
5954 #define RTC_ALRMBR_MNU 0x00000F00U
5955 #define RTC_ALRMBR_MNU_0 0x00000100U
5956 #define RTC_ALRMBR_MNU_1 0x00000200U
5957 #define RTC_ALRMBR_MNU_2 0x00000400U
5958 #define RTC_ALRMBR_MNU_3 0x00000800U
5959 #define RTC_ALRMBR_MSK1 0x00000080U
5960 #define RTC_ALRMBR_ST 0x00000070U
5961 #define RTC_ALRMBR_ST_0 0x00000010U
5962 #define RTC_ALRMBR_ST_1 0x00000020U
5963 #define RTC_ALRMBR_ST_2 0x00000040U
5964 #define RTC_ALRMBR_SU 0x0000000FU
5965 #define RTC_ALRMBR_SU_0 0x00000001U
5966 #define RTC_ALRMBR_SU_1 0x00000002U
5967 #define RTC_ALRMBR_SU_2 0x00000004U
5968 #define RTC_ALRMBR_SU_3 0x00000008U
5969 
5970 /******************** Bits definition for RTC_WPR register ******************/
5971 #define RTC_WPR_KEY 0x000000FFU
5972 
5973 /******************** Bits definition for RTC_SSR register ******************/
5974 #define RTC_SSR_SS 0x0000FFFFU
5975 
5976 /******************** Bits definition for RTC_SHIFTR register ***************/
5977 #define RTC_SHIFTR_SUBFS 0x00007FFFU
5978 #define RTC_SHIFTR_ADD1S 0x80000000U
5979 
5980 /******************** Bits definition for RTC_TSTR register *****************/
5981 #define RTC_TSTR_PM 0x00400000U
5982 #define RTC_TSTR_HT 0x00300000U
5983 #define RTC_TSTR_HT_0 0x00100000U
5984 #define RTC_TSTR_HT_1 0x00200000U
5985 #define RTC_TSTR_HU 0x000F0000U
5986 #define RTC_TSTR_HU_0 0x00010000U
5987 #define RTC_TSTR_HU_1 0x00020000U
5988 #define RTC_TSTR_HU_2 0x00040000U
5989 #define RTC_TSTR_HU_3 0x00080000U
5990 #define RTC_TSTR_MNT 0x00007000U
5991 #define RTC_TSTR_MNT_0 0x00001000U
5992 #define RTC_TSTR_MNT_1 0x00002000U
5993 #define RTC_TSTR_MNT_2 0x00004000U
5994 #define RTC_TSTR_MNU 0x00000F00U
5995 #define RTC_TSTR_MNU_0 0x00000100U
5996 #define RTC_TSTR_MNU_1 0x00000200U
5997 #define RTC_TSTR_MNU_2 0x00000400U
5998 #define RTC_TSTR_MNU_3 0x00000800U
5999 #define RTC_TSTR_ST 0x00000070U
6000 #define RTC_TSTR_ST_0 0x00000010U
6001 #define RTC_TSTR_ST_1 0x00000020U
6002 #define RTC_TSTR_ST_2 0x00000040U
6003 #define RTC_TSTR_SU 0x0000000FU
6004 #define RTC_TSTR_SU_0 0x00000001U
6005 #define RTC_TSTR_SU_1 0x00000002U
6006 #define RTC_TSTR_SU_2 0x00000004U
6007 #define RTC_TSTR_SU_3 0x00000008U
6008 
6009 /******************** Bits definition for RTC_TSDR register *****************/
6010 #define RTC_TSDR_WDU 0x0000E000U
6011 #define RTC_TSDR_WDU_0 0x00002000U
6012 #define RTC_TSDR_WDU_1 0x00004000U
6013 #define RTC_TSDR_WDU_2 0x00008000U
6014 #define RTC_TSDR_MT 0x00001000U
6015 #define RTC_TSDR_MU 0x00000F00U
6016 #define RTC_TSDR_MU_0 0x00000100U
6017 #define RTC_TSDR_MU_1 0x00000200U
6018 #define RTC_TSDR_MU_2 0x00000400U
6019 #define RTC_TSDR_MU_3 0x00000800U
6020 #define RTC_TSDR_DT 0x00000030U
6021 #define RTC_TSDR_DT_0 0x00000010U
6022 #define RTC_TSDR_DT_1 0x00000020U
6023 #define RTC_TSDR_DU 0x0000000FU
6024 #define RTC_TSDR_DU_0 0x00000001U
6025 #define RTC_TSDR_DU_1 0x00000002U
6026 #define RTC_TSDR_DU_2 0x00000004U
6027 #define RTC_TSDR_DU_3 0x00000008U
6028 
6029 /******************** Bits definition for RTC_TSSSR register ****************/
6030 #define RTC_TSSSR_SS 0x0000FFFFU
6031 
6032 /******************** Bits definition for RTC_CAL register *****************/
6033 #define RTC_CALR_CALP 0x00008000U
6034 #define RTC_CALR_CALW8 0x00004000U
6035 #define RTC_CALR_CALW16 0x00002000U
6036 #define RTC_CALR_CALM 0x000001FFU
6037 #define RTC_CALR_CALM_0 0x00000001U
6038 #define RTC_CALR_CALM_1 0x00000002U
6039 #define RTC_CALR_CALM_2 0x00000004U
6040 #define RTC_CALR_CALM_3 0x00000008U
6041 #define RTC_CALR_CALM_4 0x00000010U
6042 #define RTC_CALR_CALM_5 0x00000020U
6043 #define RTC_CALR_CALM_6 0x00000040U
6044 #define RTC_CALR_CALM_7 0x00000080U
6045 #define RTC_CALR_CALM_8 0x00000100U
6046 
6047 /******************** Bits definition for RTC_TAMPCR register ****************/
6048 #define RTC_TAMPCR_TAMP3MF 0x01000000U
6049 #define RTC_TAMPCR_TAMP3NOERASE 0x00800000U
6050 #define RTC_TAMPCR_TAMP3IE 0x00400000U
6051 #define RTC_TAMPCR_TAMP2MF 0x00200000U
6052 #define RTC_TAMPCR_TAMP2NOERASE 0x00100000U
6053 #define RTC_TAMPCR_TAMP2IE 0x00080000U
6054 #define RTC_TAMPCR_TAMP1MF 0x00040000U
6055 #define RTC_TAMPCR_TAMP1NOERASE 0x00020000U
6056 #define RTC_TAMPCR_TAMP1IE 0x00010000U
6057 #define RTC_TAMPCR_TAMPPUDIS 0x00008000U
6058 #define RTC_TAMPCR_TAMPPRCH 0x00006000U
6059 #define RTC_TAMPCR_TAMPPRCH_0 0x00002000U
6060 #define RTC_TAMPCR_TAMPPRCH_1 0x00004000U
6061 #define RTC_TAMPCR_TAMPFLT 0x00001800U
6062 #define RTC_TAMPCR_TAMPFLT_0 0x00000800U
6063 #define RTC_TAMPCR_TAMPFLT_1 0x00001000U
6064 #define RTC_TAMPCR_TAMPFREQ 0x00000700U
6065 #define RTC_TAMPCR_TAMPFREQ_0 0x00000100U
6066 #define RTC_TAMPCR_TAMPFREQ_1 0x00000200U
6067 #define RTC_TAMPCR_TAMPFREQ_2 0x00000400U
6068 #define RTC_TAMPCR_TAMPTS 0x00000080U
6069 #define RTC_TAMPCR_TAMP3TRG 0x00000040U
6070 #define RTC_TAMPCR_TAMP3E 0x00000020U
6071 #define RTC_TAMPCR_TAMP2TRG 0x00000010U
6072 #define RTC_TAMPCR_TAMP2E 0x00000008U
6073 #define RTC_TAMPCR_TAMPIE 0x00000004U
6074 #define RTC_TAMPCR_TAMP1TRG 0x00000002U
6075 #define RTC_TAMPCR_TAMP1E 0x00000001U
6076 
6077 /* Legacy defines */
6078 #define RTC_TAMPCR_TAMP3_TRG RTC_TAMPCR_TAMP3TRG
6079 #define RTC_TAMPCR_TAMP2_TRG RTC_TAMPCR_TAMP2TRG
6080 #define RTC_TAMPCR_TAMP1_TRG RTC_TAMPCR_TAMP1TRG
6081 
6082 /******************** Bits definition for RTC_ALRMASSR register *************/
6083 #define RTC_ALRMASSR_MASKSS 0x0F000000U
6084 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
6085 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
6086 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
6087 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
6088 #define RTC_ALRMASSR_SS 0x00007FFFU
6089 
6090 /******************** Bits definition for RTC_ALRMBSSR register *************/
6091 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
6092 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
6093 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
6094 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
6095 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
6096 #define RTC_ALRMBSSR_SS 0x00007FFFU
6097 
6098 /******************** Bits definition for RTC_OR register ****************/
6099 #define RTC_OR_TSINSEL 0x00000006U
6100 #define RTC_OR_TSINSEL_0 0x00000002U
6101 #define RTC_OR_TSINSEL_1 0x00000004U
6102 #define RTC_OR_ALARMTYPE 0x00000008U
6103 
6104 /******************** Bits definition for RTC_BKP0R register ****************/
6105 #define RTC_BKP0R 0xFFFFFFFFU
6106 
6107 /******************** Bits definition for RTC_BKP1R register ****************/
6108 #define RTC_BKP1R 0xFFFFFFFFU
6109 
6110 /******************** Bits definition for RTC_BKP2R register ****************/
6111 #define RTC_BKP2R 0xFFFFFFFFU
6112 
6113 /******************** Bits definition for RTC_BKP3R register ****************/
6114 #define RTC_BKP3R 0xFFFFFFFFU
6115 
6116 /******************** Bits definition for RTC_BKP4R register ****************/
6117 #define RTC_BKP4R 0xFFFFFFFFU
6118 
6119 /******************** Bits definition for RTC_BKP5R register ****************/
6120 #define RTC_BKP5R 0xFFFFFFFFU
6121 
6122 /******************** Bits definition for RTC_BKP6R register ****************/
6123 #define RTC_BKP6R 0xFFFFFFFFU
6124 
6125 /******************** Bits definition for RTC_BKP7R register ****************/
6126 #define RTC_BKP7R 0xFFFFFFFFU
6127 
6128 /******************** Bits definition for RTC_BKP8R register ****************/
6129 #define RTC_BKP8R 0xFFFFFFFFU
6130 
6131 /******************** Bits definition for RTC_BKP9R register ****************/
6132 #define RTC_BKP9R 0xFFFFFFFFU
6133 
6134 /******************** Bits definition for RTC_BKP10R register ***************/
6135 #define RTC_BKP10R 0xFFFFFFFFU
6136 
6137 /******************** Bits definition for RTC_BKP11R register ***************/
6138 #define RTC_BKP11R 0xFFFFFFFFU
6139 
6140 /******************** Bits definition for RTC_BKP12R register ***************/
6141 #define RTC_BKP12R 0xFFFFFFFFU
6142 
6143 /******************** Bits definition for RTC_BKP13R register ***************/
6144 #define RTC_BKP13R 0xFFFFFFFFU
6145 
6146 /******************** Bits definition for RTC_BKP14R register ***************/
6147 #define RTC_BKP14R 0xFFFFFFFFU
6148 
6149 /******************** Bits definition for RTC_BKP15R register ***************/
6150 #define RTC_BKP15R 0xFFFFFFFFU
6151 
6152 /******************** Bits definition for RTC_BKP16R register ***************/
6153 #define RTC_BKP16R 0xFFFFFFFFU
6154 
6155 /******************** Bits definition for RTC_BKP17R register ***************/
6156 #define RTC_BKP17R 0xFFFFFFFFU
6157 
6158 /******************** Bits definition for RTC_BKP18R register ***************/
6159 #define RTC_BKP18R 0xFFFFFFFFU
6160 
6161 /******************** Bits definition for RTC_BKP19R register ***************/
6162 #define RTC_BKP19R 0xFFFFFFFFU
6163 
6164 /******************** Bits definition for RTC_BKP20R register ***************/
6165 #define RTC_BKP20R 0xFFFFFFFFU
6166 
6167 /******************** Bits definition for RTC_BKP21R register ***************/
6168 #define RTC_BKP21R 0xFFFFFFFFU
6169 
6170 /******************** Bits definition for RTC_BKP22R register ***************/
6171 #define RTC_BKP22R 0xFFFFFFFFU
6172 
6173 /******************** Bits definition for RTC_BKP23R register ***************/
6174 #define RTC_BKP23R 0xFFFFFFFFU
6175 
6176 /******************** Bits definition for RTC_BKP24R register ***************/
6177 #define RTC_BKP24R 0xFFFFFFFFU
6178 
6179 /******************** Bits definition for RTC_BKP25R register ***************/
6180 #define RTC_BKP25R 0xFFFFFFFFU
6181 
6182 /******************** Bits definition for RTC_BKP26R register ***************/
6183 #define RTC_BKP26R 0xFFFFFFFFU
6184 
6185 /******************** Bits definition for RTC_BKP27R register ***************/
6186 #define RTC_BKP27R 0xFFFFFFFFU
6187 
6188 /******************** Bits definition for RTC_BKP28R register ***************/
6189 #define RTC_BKP28R 0xFFFFFFFFU
6190 
6191 /******************** Bits definition for RTC_BKP29R register ***************/
6192 #define RTC_BKP29R 0xFFFFFFFFU
6193 
6194 /******************** Bits definition for RTC_BKP30R register ***************/
6195 #define RTC_BKP30R 0xFFFFFFFFU
6196 
6197 /******************** Bits definition for RTC_BKP31R register ***************/
6198 #define RTC_BKP31R 0xFFFFFFFFU
6199 
6200 /******************** Number of backup registers ******************************/
6201 #define RTC_BKP_NUMBER 0x00000020U
6202 
6203 
6204 /******************************************************************************/
6205 /* */
6206 /* Serial Audio Interface */
6207 /* */
6208 /******************************************************************************/
6209 /******************** Bit definition for SAI_GCR register *******************/
6210 #define SAI_GCR_SYNCIN 0x00000003U
6211 #define SAI_GCR_SYNCIN_0 0x00000001U
6212 #define SAI_GCR_SYNCIN_1 0x00000002U
6214 #define SAI_GCR_SYNCOUT 0x00000030U
6215 #define SAI_GCR_SYNCOUT_0 0x00000010U
6216 #define SAI_GCR_SYNCOUT_1 0x00000020U
6218 /******************* Bit definition for SAI_xCR1 register *******************/
6219 #define SAI_xCR1_MODE 0x00000003U
6220 #define SAI_xCR1_MODE_0 0x00000001U
6221 #define SAI_xCR1_MODE_1 0x00000002U
6223 #define SAI_xCR1_PRTCFG 0x0000000CU
6224 #define SAI_xCR1_PRTCFG_0 0x00000004U
6225 #define SAI_xCR1_PRTCFG_1 0x00000008U
6227 #define SAI_xCR1_DS 0x000000E0U
6228 #define SAI_xCR1_DS_0 0x00000020U
6229 #define SAI_xCR1_DS_1 0x00000040U
6230 #define SAI_xCR1_DS_2 0x00000080U
6232 #define SAI_xCR1_LSBFIRST 0x00000100U
6233 #define SAI_xCR1_CKSTR 0x00000200U
6235 #define SAI_xCR1_SYNCEN 0x00000C00U
6236 #define SAI_xCR1_SYNCEN_0 0x00000400U
6237 #define SAI_xCR1_SYNCEN_1 0x00000800U
6239 #define SAI_xCR1_MONO 0x00001000U
6240 #define SAI_xCR1_OUTDRIV 0x00002000U
6241 #define SAI_xCR1_SAIEN 0x00010000U
6242 #define SAI_xCR1_DMAEN 0x00020000U
6243 #define SAI_xCR1_NODIV 0x00080000U
6245 #define SAI_xCR1_MCKDIV 0x00F00000U
6246 #define SAI_xCR1_MCKDIV_0 0x00100000U
6247 #define SAI_xCR1_MCKDIV_1 0x00200000U
6248 #define SAI_xCR1_MCKDIV_2 0x00400000U
6249 #define SAI_xCR1_MCKDIV_3 0x00800000U
6251 /******************* Bit definition for SAI_xCR2 register *******************/
6252 #define SAI_xCR2_FTH 0x00000007U
6253 #define SAI_xCR2_FTH_0 0x00000001U
6254 #define SAI_xCR2_FTH_1 0x00000002U
6255 #define SAI_xCR2_FTH_2 0x00000004U
6257 #define SAI_xCR2_FFLUSH 0x00000008U
6258 #define SAI_xCR2_TRIS 0x00000010U
6259 #define SAI_xCR2_MUTE 0x00000020U
6260 #define SAI_xCR2_MUTEVAL 0x00000040U
6262 #define SAI_xCR2_MUTECNT 0x00001F80U
6263 #define SAI_xCR2_MUTECNT_0 0x00000080U
6264 #define SAI_xCR2_MUTECNT_1 0x00000100U
6265 #define SAI_xCR2_MUTECNT_2 0x00000200U
6266 #define SAI_xCR2_MUTECNT_3 0x00000400U
6267 #define SAI_xCR2_MUTECNT_4 0x00000800U
6268 #define SAI_xCR2_MUTECNT_5 0x00001000U
6270 #define SAI_xCR2_CPL 0x00002000U
6272 #define SAI_xCR2_COMP 0x0000C000U
6273 #define SAI_xCR2_COMP_0 0x00004000U
6274 #define SAI_xCR2_COMP_1 0x00008000U
6276 /****************** Bit definition for SAI_xFRCR register *******************/
6277 #define SAI_xFRCR_FRL 0x000000FFU
6278 #define SAI_xFRCR_FRL_0 0x00000001U
6279 #define SAI_xFRCR_FRL_1 0x00000002U
6280 #define SAI_xFRCR_FRL_2 0x00000004U
6281 #define SAI_xFRCR_FRL_3 0x00000008U
6282 #define SAI_xFRCR_FRL_4 0x00000010U
6283 #define SAI_xFRCR_FRL_5 0x00000020U
6284 #define SAI_xFRCR_FRL_6 0x00000040U
6285 #define SAI_xFRCR_FRL_7 0x00000080U
6287 #define SAI_xFRCR_FSALL 0x00007F00U
6288 #define SAI_xFRCR_FSALL_0 0x00000100U
6289 #define SAI_xFRCR_FSALL_1 0x00000200U
6290 #define SAI_xFRCR_FSALL_2 0x00000400U
6291 #define SAI_xFRCR_FSALL_3 0x00000800U
6292 #define SAI_xFRCR_FSALL_4 0x00001000U
6293 #define SAI_xFRCR_FSALL_5 0x00002000U
6294 #define SAI_xFRCR_FSALL_6 0x00004000U
6296 #define SAI_xFRCR_FSDEF 0x00010000U
6297 #define SAI_xFRCR_FSPOL 0x00020000U
6298 #define SAI_xFRCR_FSOFF 0x00040000U
6300 /* Legacy define */
6301 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
6302 
6303 /****************** Bit definition for SAI_xSLOTR register *******************/
6304 #define SAI_xSLOTR_FBOFF 0x0000001FU
6305 #define SAI_xSLOTR_FBOFF_0 0x00000001U
6306 #define SAI_xSLOTR_FBOFF_1 0x00000002U
6307 #define SAI_xSLOTR_FBOFF_2 0x00000004U
6308 #define SAI_xSLOTR_FBOFF_3 0x00000008U
6309 #define SAI_xSLOTR_FBOFF_4 0x00000010U
6311 #define SAI_xSLOTR_SLOTSZ 0x000000C0U
6312 #define SAI_xSLOTR_SLOTSZ_0 0x00000040U
6313 #define SAI_xSLOTR_SLOTSZ_1 0x00000080U
6315 #define SAI_xSLOTR_NBSLOT 0x00000F00U
6316 #define SAI_xSLOTR_NBSLOT_0 0x00000100U
6317 #define SAI_xSLOTR_NBSLOT_1 0x00000200U
6318 #define SAI_xSLOTR_NBSLOT_2 0x00000400U
6319 #define SAI_xSLOTR_NBSLOT_3 0x00000800U
6321 #define SAI_xSLOTR_SLOTEN 0xFFFF0000U
6323 /******************* Bit definition for SAI_xIMR register *******************/
6324 #define SAI_xIMR_OVRUDRIE 0x00000001U
6325 #define SAI_xIMR_MUTEDETIE 0x00000002U
6326 #define SAI_xIMR_WCKCFGIE 0x00000004U
6327 #define SAI_xIMR_FREQIE 0x00000008U
6328 #define SAI_xIMR_CNRDYIE 0x00000010U
6329 #define SAI_xIMR_AFSDETIE 0x00000020U
6330 #define SAI_xIMR_LFSDETIE 0x00000040U
6332 /******************** Bit definition for SAI_xSR register *******************/
6333 #define SAI_xSR_OVRUDR 0x00000001U
6334 #define SAI_xSR_MUTEDET 0x00000002U
6335 #define SAI_xSR_WCKCFG 0x00000004U
6336 #define SAI_xSR_FREQ 0x00000008U
6337 #define SAI_xSR_CNRDY 0x00000010U
6338 #define SAI_xSR_AFSDET 0x00000020U
6339 #define SAI_xSR_LFSDET 0x00000040U
6341 #define SAI_xSR_FLVL 0x00070000U
6342 #define SAI_xSR_FLVL_0 0x00010000U
6343 #define SAI_xSR_FLVL_1 0x00020000U
6344 #define SAI_xSR_FLVL_2 0x00040000U
6346 /****************** Bit definition for SAI_xCLRFR register ******************/
6347 #define SAI_xCLRFR_COVRUDR 0x00000001U
6348 #define SAI_xCLRFR_CMUTEDET 0x00000002U
6349 #define SAI_xCLRFR_CWCKCFG 0x00000004U
6350 #define SAI_xCLRFR_CFREQ 0x00000008U
6351 #define SAI_xCLRFR_CCNRDY 0x00000010U
6352 #define SAI_xCLRFR_CAFSDET 0x00000020U
6353 #define SAI_xCLRFR_CLFSDET 0x00000040U
6355 /****************** Bit definition for SAI_xDR register *********************/
6356 #define SAI_xDR_DATA 0xFFFFFFFFU
6357 
6358 /******************************************************************************/
6359 /* */
6360 /* SPDIF-RX Interface */
6361 /* */
6362 /******************************************************************************/
6363 /******************** Bit definition for SPDIF_CR register *******************/
6364 #define SPDIFRX_CR_SPDIFEN 0x00000003U
6365 #define SPDIFRX_CR_RXDMAEN 0x00000004U
6366 #define SPDIFRX_CR_RXSTEO 0x00000008U
6367 #define SPDIFRX_CR_DRFMT 0x00000030U
6368 #define SPDIFRX_CR_PMSK 0x00000040U
6369 #define SPDIFRX_CR_VMSK 0x00000080U
6370 #define SPDIFRX_CR_CUMSK 0x00000100U
6371 #define SPDIFRX_CR_PTMSK 0x00000200U
6372 #define SPDIFRX_CR_CBDMAEN 0x00000400U
6373 #define SPDIFRX_CR_CHSEL 0x00000800U
6374 #define SPDIFRX_CR_NBTR 0x00003000U
6375 #define SPDIFRX_CR_WFA 0x00004000U
6376 #define SPDIFRX_CR_INSEL 0x00070000U
6378 /******************* Bit definition for SPDIFRX_IMR register *******************/
6379 #define SPDIFRX_IMR_RXNEIE 0x00000001U
6380 #define SPDIFRX_IMR_CSRNEIE 0x00000002U
6381 #define SPDIFRX_IMR_PERRIE 0x00000004U
6382 #define SPDIFRX_IMR_OVRIE 0x00000008U
6383 #define SPDIFRX_IMR_SBLKIE 0x00000010U
6384 #define SPDIFRX_IMR_SYNCDIE 0x00000020U
6385 #define SPDIFRX_IMR_IFEIE 0x00000040U
6387 /******************* Bit definition for SPDIFRX_SR register *******************/
6388 #define SPDIFRX_SR_RXNE 0x00000001U
6389 #define SPDIFRX_SR_CSRNE 0x00000002U
6390 #define SPDIFRX_SR_PERR 0x00000004U
6391 #define SPDIFRX_SR_OVR 0x00000008U
6392 #define SPDIFRX_SR_SBD 0x00000010U
6393 #define SPDIFRX_SR_SYNCD 0x00000020U
6394 #define SPDIFRX_SR_FERR 0x00000040U
6395 #define SPDIFRX_SR_SERR 0x00000080U
6396 #define SPDIFRX_SR_TERR 0x00000100U
6397 #define SPDIFRX_SR_WIDTH5 0x7FFF0000U
6399 /******************* Bit definition for SPDIFRX_IFCR register *******************/
6400 #define SPDIFRX_IFCR_PERRCF 0x00000004U
6401 #define SPDIFRX_IFCR_OVRCF 0x00000008U
6402 #define SPDIFRX_IFCR_SBDCF 0x00000010U
6403 #define SPDIFRX_IFCR_SYNCDCF 0x00000020U
6405 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
6406 #define SPDIFRX_DR0_DR 0x00FFFFFFU
6407 #define SPDIFRX_DR0_PE 0x01000000U
6408 #define SPDIFRX_DR0_V 0x02000000U
6409 #define SPDIFRX_DR0_U 0x04000000U
6410 #define SPDIFRX_DR0_C 0x08000000U
6411 #define SPDIFRX_DR0_PT 0x30000000U
6413 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
6414 #define SPDIFRX_DR1_DR 0xFFFFFF00U
6415 #define SPDIFRX_DR1_PT 0x00000030U
6416 #define SPDIFRX_DR1_C 0x00000008U
6417 #define SPDIFRX_DR1_U 0x00000004U
6418 #define SPDIFRX_DR1_V 0x00000002U
6419 #define SPDIFRX_DR1_PE 0x00000001U
6421 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
6422 #define SPDIFRX_DR1_DRNL1 0xFFFF0000U
6423 #define SPDIFRX_DR1_DRNL2 0x0000FFFFU
6425 /******************* Bit definition for SPDIFRX_CSR register *******************/
6426 #define SPDIFRX_CSR_USR 0x0000FFFFU
6427 #define SPDIFRX_CSR_CS 0x00FF0000U
6428 #define SPDIFRX_CSR_SOB 0x01000000U
6430 /******************* Bit definition for SPDIFRX_DIR register *******************/
6431 #define SPDIFRX_DIR_THI 0x000013FFU
6432 #define SPDIFRX_DIR_TLO 0x1FFF0000U
6435 /******************************************************************************/
6436 /* */
6437 /* SD host Interface */
6438 /* */
6439 /******************************************************************************/
6440 /****************** Bit definition for SDMMC_POWER register ******************/
6441 #define SDMMC_POWER_PWRCTRL 0x03U
6442 #define SDMMC_POWER_PWRCTRL_0 0x01U
6443 #define SDMMC_POWER_PWRCTRL_1 0x02U
6445 /****************** Bit definition for SDMMC_CLKCR register ******************/
6446 #define SDMMC_CLKCR_CLKDIV 0x00FFU
6447 #define SDMMC_CLKCR_CLKEN 0x0100U
6448 #define SDMMC_CLKCR_PWRSAV 0x0200U
6449 #define SDMMC_CLKCR_BYPASS 0x0400U
6451 #define SDMMC_CLKCR_WIDBUS 0x1800U
6452 #define SDMMC_CLKCR_WIDBUS_0 0x0800U
6453 #define SDMMC_CLKCR_WIDBUS_1 0x1000U
6455 #define SDMMC_CLKCR_NEGEDGE 0x2000U
6456 #define SDMMC_CLKCR_HWFC_EN 0x4000U
6458 /******************* Bit definition for SDMMC_ARG register *******************/
6459 #define SDMMC_ARG_CMDARG 0xFFFFFFFFU
6461 /******************* Bit definition for SDMMC_CMD register *******************/
6462 #define SDMMC_CMD_CMDINDEX 0x003FU
6464 #define SDMMC_CMD_WAITRESP 0x00C0U
6465 #define SDMMC_CMD_WAITRESP_0 0x0040U
6466 #define SDMMC_CMD_WAITRESP_1 0x0080U
6468 #define SDMMC_CMD_WAITINT 0x0100U
6469 #define SDMMC_CMD_WAITPEND 0x0200U
6470 #define SDMMC_CMD_CPSMEN 0x0400U
6471 #define SDMMC_CMD_SDIOSUSPEND 0x0800U
6473 /***************** Bit definition for SDMMC_RESPCMD register *****************/
6474 #define SDMMC_RESPCMD_RESPCMD 0x3FU
6476 /****************** Bit definition for SDMMC_RESP0 register ******************/
6477 #define SDMMC_RESP0_CARDSTATUS0 0xFFFFFFFFU
6479 /****************** Bit definition for SDMMC_RESP1 register ******************/
6480 #define SDMMC_RESP1_CARDSTATUS1 0xFFFFFFFFU
6482 /****************** Bit definition for SDMMC_RESP2 register ******************/
6483 #define SDMMC_RESP2_CARDSTATUS2 0xFFFFFFFFU
6485 /****************** Bit definition for SDMMC_RESP3 register ******************/
6486 #define SDMMC_RESP3_CARDSTATUS3 0xFFFFFFFFU
6488 /****************** Bit definition for SDMMC_RESP4 register ******************/
6489 #define SDMMC_RESP4_CARDSTATUS4 0xFFFFFFFFU
6491 /****************** Bit definition for SDMMC_DTIMER register *****************/
6492 #define SDMMC_DTIMER_DATATIME 0xFFFFFFFFU
6494 /****************** Bit definition for SDMMC_DLEN register *******************/
6495 #define SDMMC_DLEN_DATALENGTH 0x01FFFFFFU
6497 /****************** Bit definition for SDMMC_DCTRL register ******************/
6498 #define SDMMC_DCTRL_DTEN 0x0001U
6499 #define SDMMC_DCTRL_DTDIR 0x0002U
6500 #define SDMMC_DCTRL_DTMODE 0x0004U
6501 #define SDMMC_DCTRL_DMAEN 0x0008U
6503 #define SDMMC_DCTRL_DBLOCKSIZE 0x00F0U
6504 #define SDMMC_DCTRL_DBLOCKSIZE_0 0x0010U
6505 #define SDMMC_DCTRL_DBLOCKSIZE_1 0x0020U
6506 #define SDMMC_DCTRL_DBLOCKSIZE_2 0x0040U
6507 #define SDMMC_DCTRL_DBLOCKSIZE_3 0x0080U
6509 #define SDMMC_DCTRL_RWSTART 0x0100U
6510 #define SDMMC_DCTRL_RWSTOP 0x0200U
6511 #define SDMMC_DCTRL_RWMOD 0x0400U
6512 #define SDMMC_DCTRL_SDIOEN 0x0800U
6514 /****************** Bit definition for SDMMC_DCOUNT register *****************/
6515 #define SDMMC_DCOUNT_DATACOUNT 0x01FFFFFFU
6517 /****************** Bit definition for SDMMC_STA registe ********************/
6518 #define SDMMC_STA_CCRCFAIL 0x00000001U
6519 #define SDMMC_STA_DCRCFAIL 0x00000002U
6520 #define SDMMC_STA_CTIMEOUT 0x00000004U
6521 #define SDMMC_STA_DTIMEOUT 0x00000008U
6522 #define SDMMC_STA_TXUNDERR 0x00000010U
6523 #define SDMMC_STA_RXOVERR 0x00000020U
6524 #define SDMMC_STA_CMDREND 0x00000040U
6525 #define SDMMC_STA_CMDSENT 0x00000080U
6526 #define SDMMC_STA_DATAEND 0x00000100U
6527 #define SDMMC_STA_DBCKEND 0x00000400U
6528 #define SDMMC_STA_CMDACT 0x00000800U
6529 #define SDMMC_STA_TXACT 0x00001000U
6530 #define SDMMC_STA_RXACT 0x00002000U
6531 #define SDMMC_STA_TXFIFOHE 0x00004000U
6532 #define SDMMC_STA_RXFIFOHF 0x00008000U
6533 #define SDMMC_STA_TXFIFOF 0x00010000U
6534 #define SDMMC_STA_RXFIFOF 0x00020000U
6535 #define SDMMC_STA_TXFIFOE 0x00040000U
6536 #define SDMMC_STA_RXFIFOE 0x00080000U
6537 #define SDMMC_STA_TXDAVL 0x00100000U
6538 #define SDMMC_STA_RXDAVL 0x00200000U
6539 #define SDMMC_STA_SDIOIT 0x00400000U
6541 /******************* Bit definition for SDMMC_ICR register *******************/
6542 #define SDMMC_ICR_CCRCFAILC 0x00000001U
6543 #define SDMMC_ICR_DCRCFAILC 0x00000002U
6544 #define SDMMC_ICR_CTIMEOUTC 0x00000004U
6545 #define SDMMC_ICR_DTIMEOUTC 0x00000008U
6546 #define SDMMC_ICR_TXUNDERRC 0x00000010U
6547 #define SDMMC_ICR_RXOVERRC 0x00000020U
6548 #define SDMMC_ICR_CMDRENDC 0x00000040U
6549 #define SDMMC_ICR_CMDSENTC 0x00000080U
6550 #define SDMMC_ICR_DATAENDC 0x00000100U
6551 #define SDMMC_ICR_DBCKENDC 0x00000400U
6552 #define SDMMC_ICR_SDIOITC 0x00400000U
6554 /****************** Bit definition for SDMMC_MASK register *******************/
6555 #define SDMMC_MASK_CCRCFAILIE 0x00000001U
6556 #define SDMMC_MASK_DCRCFAILIE 0x00000002U
6557 #define SDMMC_MASK_CTIMEOUTIE 0x00000004U
6558 #define SDMMC_MASK_DTIMEOUTIE 0x00000008U
6559 #define SDMMC_MASK_TXUNDERRIE 0x00000010U
6560 #define SDMMC_MASK_RXOVERRIE 0x00000020U
6561 #define SDMMC_MASK_CMDRENDIE 0x00000040U
6562 #define SDMMC_MASK_CMDSENTIE 0x00000080U
6563 #define SDMMC_MASK_DATAENDIE 0x00000100U
6564 #define SDMMC_MASK_DBCKENDIE 0x00000400U
6565 #define SDMMC_MASK_CMDACTIE 0x00000800U
6566 #define SDMMC_MASK_TXACTIE 0x00001000U
6567 #define SDMMC_MASK_RXACTIE 0x00002000U
6568 #define SDMMC_MASK_TXFIFOHEIE 0x00004000U
6569 #define SDMMC_MASK_RXFIFOHFIE 0x00008000U
6570 #define SDMMC_MASK_TXFIFOFIE 0x00010000U
6571 #define SDMMC_MASK_RXFIFOFIE 0x00020000U
6572 #define SDMMC_MASK_TXFIFOEIE 0x00040000U
6573 #define SDMMC_MASK_RXFIFOEIE 0x00080000U
6574 #define SDMMC_MASK_TXDAVLIE 0x00100000U
6575 #define SDMMC_MASK_RXDAVLIE 0x00200000U
6576 #define SDMMC_MASK_SDIOITIE 0x00400000U
6578 /***************** Bit definition for SDMMC_FIFOCNT register *****************/
6579 #define SDMMC_FIFOCNT_FIFOCOUNT 0x00FFFFFFU
6581 /****************** Bit definition for SDMMC_FIFO register *******************/
6582 #define SDMMC_FIFO_FIFODATA 0xFFFFFFFFU
6584 /******************************************************************************/
6585 /* */
6586 /* Serial Peripheral Interface (SPI) */
6587 /* */
6588 /******************************************************************************/
6589 /******************* Bit definition for SPI_CR1 register ********************/
6590 #define SPI_CR1_CPHA 0x00000001U
6591 #define SPI_CR1_CPOL 0x00000002U
6592 #define SPI_CR1_MSTR 0x00000004U
6593 #define SPI_CR1_BR 0x00000038U
6594 #define SPI_CR1_BR_0 0x00000008U
6595 #define SPI_CR1_BR_1 0x00000010U
6596 #define SPI_CR1_BR_2 0x00000020U
6597 #define SPI_CR1_SPE 0x00000040U
6598 #define SPI_CR1_LSBFIRST 0x00000080U
6599 #define SPI_CR1_SSI 0x00000100U
6600 #define SPI_CR1_SSM 0x00000200U
6601 #define SPI_CR1_RXONLY 0x00000400U
6602 #define SPI_CR1_CRCL 0x00000800U
6603 #define SPI_CR1_CRCNEXT 0x00001000U
6604 #define SPI_CR1_CRCEN 0x00002000U
6605 #define SPI_CR1_BIDIOE 0x00004000U
6606 #define SPI_CR1_BIDIMODE 0x00008000U
6608 /******************* Bit definition for SPI_CR2 register ********************/
6609 #define SPI_CR2_RXDMAEN 0x00000001U
6610 #define SPI_CR2_TXDMAEN 0x00000002U
6611 #define SPI_CR2_SSOE 0x00000004U
6612 #define SPI_CR2_NSSP 0x00000008U
6613 #define SPI_CR2_FRF 0x00000010U
6614 #define SPI_CR2_ERRIE 0x00000020U
6615 #define SPI_CR2_RXNEIE 0x00000040U
6616 #define SPI_CR2_TXEIE 0x00000080U
6617 #define SPI_CR2_DS 0x00000F00U
6618 #define SPI_CR2_DS_0 0x00000100U
6619 #define SPI_CR2_DS_1 0x00000200U
6620 #define SPI_CR2_DS_2 0x00000400U
6621 #define SPI_CR2_DS_3 0x00000800U
6622 #define SPI_CR2_FRXTH 0x00001000U
6623 #define SPI_CR2_LDMARX 0x00002000U
6624 #define SPI_CR2_LDMATX 0x00004000U
6626 /******************** Bit definition for SPI_SR register ********************/
6627 #define SPI_SR_RXNE 0x00000001U
6628 #define SPI_SR_TXE 0x00000002U
6629 #define SPI_SR_CHSIDE 0x00000004U
6630 #define SPI_SR_UDR 0x00000008U
6631 #define SPI_SR_CRCERR 0x00000010U
6632 #define SPI_SR_MODF 0x00000020U
6633 #define SPI_SR_OVR 0x00000040U
6634 #define SPI_SR_BSY 0x00000080U
6635 #define SPI_SR_FRE 0x00000100U
6636 #define SPI_SR_FRLVL 0x00000600U
6637 #define SPI_SR_FRLVL_0 0x00000200U
6638 #define SPI_SR_FRLVL_1 0x00000400U
6639 #define SPI_SR_FTLVL 0x00001800U
6640 #define SPI_SR_FTLVL_0 0x00000800U
6641 #define SPI_SR_FTLVL_1 0x00001000U
6643 /******************** Bit definition for SPI_DR register ********************/
6644 #define SPI_DR_DR 0xFFFFU
6646 /******************* Bit definition for SPI_CRCPR register ******************/
6647 #define SPI_CRCPR_CRCPOLY 0xFFFFU
6649 /****************** Bit definition for SPI_RXCRCR register ******************/
6650 #define SPI_RXCRCR_RXCRC 0xFFFFU
6652 /****************** Bit definition for SPI_TXCRCR register ******************/
6653 #define SPI_TXCRCR_TXCRC 0xFFFFU
6655 /****************** Bit definition for SPI_I2SCFGR register *****************/
6656 #define SPI_I2SCFGR_CHLEN 0x00000001U
6657 #define SPI_I2SCFGR_DATLEN 0x00000006U
6658 #define SPI_I2SCFGR_DATLEN_0 0x00000002U
6659 #define SPI_I2SCFGR_DATLEN_1 0x00000004U
6660 #define SPI_I2SCFGR_CKPOL 0x00000008U
6661 #define SPI_I2SCFGR_I2SSTD 0x00000030U
6662 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U
6663 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U
6664 #define SPI_I2SCFGR_PCMSYNC 0x00000080U
6665 #define SPI_I2SCFGR_I2SCFG 0x00000300U
6666 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U
6667 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U
6668 #define SPI_I2SCFGR_I2SE 0x00000400U
6669 #define SPI_I2SCFGR_I2SMOD 0x00000800U
6670 #define SPI_I2SCFGR_ASTRTEN 0x00001000U
6672 /****************** Bit definition for SPI_I2SPR register *******************/
6673 #define SPI_I2SPR_I2SDIV 0x00FFU
6674 #define SPI_I2SPR_ODD 0x0100U
6675 #define SPI_I2SPR_MCKOE 0x0200U
6678 /******************************************************************************/
6679 /* */
6680 /* SYSCFG */
6681 /* */
6682 /******************************************************************************/
6683 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
6684 #define SYSCFG_MEMRMP_MEM_BOOT 0x00000001U
6687 #define SYSCFG_MEMRMP_SWP_FMC 0x00000C00U
6688 #define SYSCFG_MEMRMP_SWP_FMC_0 0x00000400U
6689 #define SYSCFG_MEMRMP_SWP_FMC_1 0x00000800U
6690 
6691 /****************** Bit definition for SYSCFG_PMC register ******************/
6692 
6693 #define SYSCFG_PMC_ADCxDC2 0x00070000U
6694 #define SYSCFG_PMC_ADC1DC2 0x00010000U
6695 #define SYSCFG_PMC_ADC2DC2 0x00020000U
6696 #define SYSCFG_PMC_ADC3DC2 0x00040000U
6698 #define SYSCFG_PMC_MII_RMII_SEL 0x00800000U
6700 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
6701 #define SYSCFG_EXTICR1_EXTI0 0x000FU
6702 #define SYSCFG_EXTICR1_EXTI1 0x00F0U
6703 #define SYSCFG_EXTICR1_EXTI2 0x0F00U
6704 #define SYSCFG_EXTICR1_EXTI3 0xF000U
6708 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
6709 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
6710 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
6711 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
6712 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
6713 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
6714 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
6715 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
6716 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U
6717 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U
6718 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU
6723 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
6724 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
6725 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
6726 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
6727 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
6728 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
6729 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
6730 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
6731 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U
6732 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U
6733 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U
6738 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
6739 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
6740 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
6741 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
6742 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
6743 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
6744 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
6745 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
6746 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U
6747 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U
6748 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U
6753 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
6754 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
6755 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
6756 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
6757 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
6758 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
6759 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
6760 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
6761 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U
6762 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U
6763 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U
6765 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
6766 #define SYSCFG_EXTICR2_EXTI4 0x000FU
6767 #define SYSCFG_EXTICR2_EXTI5 0x00F0U
6768 #define SYSCFG_EXTICR2_EXTI6 0x0F00U
6769 #define SYSCFG_EXTICR2_EXTI7 0xF000U
6773 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
6774 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
6775 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
6776 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
6777 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
6778 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
6779 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
6780 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
6781 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U
6782 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U
6783 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU
6788 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
6789 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
6790 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
6791 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
6792 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
6793 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
6794 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
6795 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
6796 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U
6797 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U
6798 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U
6803 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
6804 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
6805 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
6806 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
6807 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
6808 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
6809 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
6810 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
6811 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U
6812 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U
6813 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U
6818 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
6819 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
6820 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
6821 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
6822 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
6823 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
6824 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
6825 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
6826 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U
6827 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U
6828 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U
6830 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
6831 #define SYSCFG_EXTICR3_EXTI8 0x000FU
6832 #define SYSCFG_EXTICR3_EXTI9 0x00F0U
6833 #define SYSCFG_EXTICR3_EXTI10 0x0F00U
6834 #define SYSCFG_EXTICR3_EXTI11 0xF000U
6839 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
6840 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
6841 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
6842 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
6843 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
6844 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
6845 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
6846 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
6847 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U
6848 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U
6853 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
6854 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
6855 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
6856 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
6857 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
6858 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
6859 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
6860 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
6861 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U
6862 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U
6867 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
6868 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
6869 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
6870 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
6871 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
6872 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
6873 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
6874 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
6875 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U
6876 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U
6881 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
6882 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
6883 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
6884 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
6885 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
6886 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
6887 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
6888 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
6889 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U
6890 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U
6893 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
6894 #define SYSCFG_EXTICR4_EXTI12 0x000FU
6895 #define SYSCFG_EXTICR4_EXTI13 0x00F0U
6896 #define SYSCFG_EXTICR4_EXTI14 0x0F00U
6897 #define SYSCFG_EXTICR4_EXTI15 0xF000U
6901 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
6902 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
6903 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
6904 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
6905 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
6906 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
6907 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
6908 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
6909 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U
6910 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U
6915 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
6916 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
6917 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
6918 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
6919 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
6920 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
6921 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
6922 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
6923 #define SYSCFG_EXTICR4_EXTI13_PI 0x0080U
6924 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0090U
6929 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
6930 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
6931 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
6932 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
6933 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
6934 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
6935 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
6936 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
6937 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U
6938 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U
6943 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
6944 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
6945 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
6946 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
6947 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
6948 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
6949 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
6950 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
6951 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U
6952 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U
6955 /****************** Bit definition for SYSCFG_CMPCR register ****************/
6956 #define SYSCFG_CMPCR_CMP_PD 0x00000001U
6957 #define SYSCFG_CMPCR_READY 0x00000100U
6959 /******************************************************************************/
6960 /* */
6961 /* TIM */
6962 /* */
6963 /******************************************************************************/
6964 /******************* Bit definition for TIM_CR1 register ********************/
6965 #define TIM_CR1_CEN 0x0001U
6966 #define TIM_CR1_UDIS 0x0002U
6967 #define TIM_CR1_URS 0x0004U
6968 #define TIM_CR1_OPM 0x0008U
6969 #define TIM_CR1_DIR 0x0010U
6971 #define TIM_CR1_CMS 0x0060U
6972 #define TIM_CR1_CMS_0 0x0020U
6973 #define TIM_CR1_CMS_1 0x0040U
6975 #define TIM_CR1_ARPE 0x0080U
6977 #define TIM_CR1_CKD 0x0300U
6978 #define TIM_CR1_CKD_0 0x0100U
6979 #define TIM_CR1_CKD_1 0x0200U
6980 #define TIM_CR1_UIFREMAP 0x0800U
6982 /******************* Bit definition for TIM_CR2 register ********************/
6983 #define TIM_CR2_CCPC 0x00000001U
6984 #define TIM_CR2_CCUS 0x00000004U
6985 #define TIM_CR2_CCDS 0x00000008U
6987 #define TIM_CR2_OIS5 0x00010000U
6988 #define TIM_CR2_OIS6 0x00040000U
6990 #define TIM_CR2_MMS 0x0070U
6991 #define TIM_CR2_MMS_0 0x0010U
6992 #define TIM_CR2_MMS_1 0x0020U
6993 #define TIM_CR2_MMS_2 0x0040U
6995 #define TIM_CR2_MMS2 0x00F00000U
6996 #define TIM_CR2_MMS2_0 0x00100000U
6997 #define TIM_CR2_MMS2_1 0x00200000U
6998 #define TIM_CR2_MMS2_2 0x00400000U
6999 #define TIM_CR2_MMS2_3 0x00800000U
7001 #define TIM_CR2_TI1S 0x0080U
7002 #define TIM_CR2_OIS1 0x0100U
7003 #define TIM_CR2_OIS1N 0x0200U
7004 #define TIM_CR2_OIS2 0x0400U
7005 #define TIM_CR2_OIS2N 0x0800U
7006 #define TIM_CR2_OIS3 0x1000U
7007 #define TIM_CR2_OIS3N 0x2000U
7008 #define TIM_CR2_OIS4 0x4000U
7010 /******************* Bit definition for TIM_SMCR register *******************/
7011 #define TIM_SMCR_SMS 0x00010007U
7012 #define TIM_SMCR_SMS_0 0x00000001U
7013 #define TIM_SMCR_SMS_1 0x00000002U
7014 #define TIM_SMCR_SMS_2 0x00000004U
7015 #define TIM_SMCR_SMS_3 0x00010000U
7016 #define TIM_SMCR_OCCS 0x00000008U
7018 #define TIM_SMCR_TS 0x0070U
7019 #define TIM_SMCR_TS_0 0x0010U
7020 #define TIM_SMCR_TS_1 0x0020U
7021 #define TIM_SMCR_TS_2 0x0040U
7023 #define TIM_SMCR_MSM 0x0080U
7025 #define TIM_SMCR_ETF 0x0F00U
7026 #define TIM_SMCR_ETF_0 0x0100U
7027 #define TIM_SMCR_ETF_1 0x0200U
7028 #define TIM_SMCR_ETF_2 0x0400U
7029 #define TIM_SMCR_ETF_3 0x0800U
7031 #define TIM_SMCR_ETPS 0x3000U
7032 #define TIM_SMCR_ETPS_0 0x1000U
7033 #define TIM_SMCR_ETPS_1 0x2000U
7035 #define TIM_SMCR_ECE 0x4000U
7036 #define TIM_SMCR_ETP 0x8000U
7038 /******************* Bit definition for TIM_DIER register *******************/
7039 #define TIM_DIER_UIE 0x0001U
7040 #define TIM_DIER_CC1IE 0x0002U
7041 #define TIM_DIER_CC2IE 0x0004U
7042 #define TIM_DIER_CC3IE 0x0008U
7043 #define TIM_DIER_CC4IE 0x0010U
7044 #define TIM_DIER_COMIE 0x0020U
7045 #define TIM_DIER_TIE 0x0040U
7046 #define TIM_DIER_BIE 0x0080U
7047 #define TIM_DIER_UDE 0x0100U
7048 #define TIM_DIER_CC1DE 0x0200U
7049 #define TIM_DIER_CC2DE 0x0400U
7050 #define TIM_DIER_CC3DE 0x0800U
7051 #define TIM_DIER_CC4DE 0x1000U
7052 #define TIM_DIER_COMDE 0x2000U
7053 #define TIM_DIER_TDE 0x4000U
7055 /******************** Bit definition for TIM_SR register ********************/
7056 #define TIM_SR_UIF 0x0001U
7057 #define TIM_SR_CC1IF 0x0002U
7058 #define TIM_SR_CC2IF 0x0004U
7059 #define TIM_SR_CC3IF 0x0008U
7060 #define TIM_SR_CC4IF 0x0010U
7061 #define TIM_SR_COMIF 0x0020U
7062 #define TIM_SR_TIF 0x0040U
7063 #define TIM_SR_BIF 0x0080U
7064 #define TIM_SR_B2IF 0x0100U
7065 #define TIM_SR_CC1OF 0x0200U
7066 #define TIM_SR_CC2OF 0x0400U
7067 #define TIM_SR_CC3OF 0x0800U
7068 #define TIM_SR_CC4OF 0x1000U
7070 /******************* Bit definition for TIM_EGR register ********************/
7071 #define TIM_EGR_UG 0x00000001U
7072 #define TIM_EGR_CC1G 0x00000002U
7073 #define TIM_EGR_CC2G 0x00000004U
7074 #define TIM_EGR_CC3G 0x00000008U
7075 #define TIM_EGR_CC4G 0x00000010U
7076 #define TIM_EGR_COMG 0x00000020U
7077 #define TIM_EGR_TG 0x00000040U
7078 #define TIM_EGR_BG 0x00000080U
7079 #define TIM_EGR_B2G 0x00000100U
7081 /****************** Bit definition for TIM_CCMR1 register *******************/
7082 #define TIM_CCMR1_CC1S 0x00000003U
7083 #define TIM_CCMR1_CC1S_0 0x00000001U
7084 #define TIM_CCMR1_CC1S_1 0x00000002U
7086 #define TIM_CCMR1_OC1FE 0x00000004U
7087 #define TIM_CCMR1_OC1PE 0x00000008U
7089 #define TIM_CCMR1_OC1M 0x00010070U
7090 #define TIM_CCMR1_OC1M_0 0x00000010U
7091 #define TIM_CCMR1_OC1M_1 0x00000020U
7092 #define TIM_CCMR1_OC1M_2 0x00000040U
7093 #define TIM_CCMR1_OC1M_3 0x00010000U
7095 #define TIM_CCMR1_OC1CE 0x00000080U
7097 #define TIM_CCMR1_CC2S 0x00000300U
7098 #define TIM_CCMR1_CC2S_0 0x00000100U
7099 #define TIM_CCMR1_CC2S_1 0x00000200U
7101 #define TIM_CCMR1_OC2FE 0x00000400U
7102 #define TIM_CCMR1_OC2PE 0x00000800U
7104 #define TIM_CCMR1_OC2M 0x01007000U
7105 #define TIM_CCMR1_OC2M_0 0x00001000U
7106 #define TIM_CCMR1_OC2M_1 0x00002000U
7107 #define TIM_CCMR1_OC2M_2 0x00004000U
7108 #define TIM_CCMR1_OC2M_3 0x01000000U
7110 #define TIM_CCMR1_OC2CE 0x00008000U
7112 /*----------------------------------------------------------------------------*/
7113 
7114 #define TIM_CCMR1_IC1PSC 0x000CU
7115 #define TIM_CCMR1_IC1PSC_0 0x0004U
7116 #define TIM_CCMR1_IC1PSC_1 0x0008U
7118 #define TIM_CCMR1_IC1F 0x00F0U
7119 #define TIM_CCMR1_IC1F_0 0x0010U
7120 #define TIM_CCMR1_IC1F_1 0x0020U
7121 #define TIM_CCMR1_IC1F_2 0x0040U
7122 #define TIM_CCMR1_IC1F_3 0x0080U
7124 #define TIM_CCMR1_IC2PSC 0x0C00U
7125 #define TIM_CCMR1_IC2PSC_0 0x0400U
7126 #define TIM_CCMR1_IC2PSC_1 0x0800U
7128 #define TIM_CCMR1_IC2F 0xF000U
7129 #define TIM_CCMR1_IC2F_0 0x1000U
7130 #define TIM_CCMR1_IC2F_1 0x2000U
7131 #define TIM_CCMR1_IC2F_2 0x4000U
7132 #define TIM_CCMR1_IC2F_3 0x8000U
7134 /****************** Bit definition for TIM_CCMR2 register *******************/
7135 #define TIM_CCMR2_CC3S 0x00000003U
7136 #define TIM_CCMR2_CC3S_0 0x00000001U
7137 #define TIM_CCMR2_CC3S_1 0x00000002U
7139 #define TIM_CCMR2_OC3FE 0x00000004U
7140 #define TIM_CCMR2_OC3PE 0x00000008U
7142 #define TIM_CCMR2_OC3M 0x00010070U
7143 #define TIM_CCMR2_OC3M_0 0x00000010U
7144 #define TIM_CCMR2_OC3M_1 0x00000020U
7145 #define TIM_CCMR2_OC3M_2 0x00000040U
7146 #define TIM_CCMR2_OC3M_3 0x00010000U
7150 #define TIM_CCMR2_OC3CE 0x00000080U
7152 #define TIM_CCMR2_CC4S 0x00000300U
7153 #define TIM_CCMR2_CC4S_0 0x00000100U
7154 #define TIM_CCMR2_CC4S_1 0x00000200U
7156 #define TIM_CCMR2_OC4FE 0x00000400U
7157 #define TIM_CCMR2_OC4PE 0x00000800U
7159 #define TIM_CCMR2_OC4M 0x01007000U
7160 #define TIM_CCMR2_OC4M_0 0x00001000U
7161 #define TIM_CCMR2_OC4M_1 0x00002000U
7162 #define TIM_CCMR2_OC4M_2 0x00004000U
7163 #define TIM_CCMR2_OC4M_3 0x01000000U
7165 #define TIM_CCMR2_OC4CE 0x8000U
7167 /*----------------------------------------------------------------------------*/
7168 
7169 #define TIM_CCMR2_IC3PSC 0x000CU
7170 #define TIM_CCMR2_IC3PSC_0 0x0004U
7171 #define TIM_CCMR2_IC3PSC_1 0x0008U
7173 #define TIM_CCMR2_IC3F 0x00F0U
7174 #define TIM_CCMR2_IC3F_0 0x0010U
7175 #define TIM_CCMR2_IC3F_1 0x0020U
7176 #define TIM_CCMR2_IC3F_2 0x0040U
7177 #define TIM_CCMR2_IC3F_3 0x0080U
7179 #define TIM_CCMR2_IC4PSC 0x0C00U
7180 #define TIM_CCMR2_IC4PSC_0 0x0400U
7181 #define TIM_CCMR2_IC4PSC_1 0x0800U
7183 #define TIM_CCMR2_IC4F 0xF000U
7184 #define TIM_CCMR2_IC4F_0 0x1000U
7185 #define TIM_CCMR2_IC4F_1 0x2000U
7186 #define TIM_CCMR2_IC4F_2 0x4000U
7187 #define TIM_CCMR2_IC4F_3 0x8000U
7189 /******************* Bit definition for TIM_CCER register *******************/
7190 #define TIM_CCER_CC1E 0x00000001U
7191 #define TIM_CCER_CC1P 0x00000002U
7192 #define TIM_CCER_CC1NE 0x00000004U
7193 #define TIM_CCER_CC1NP 0x00000008U
7194 #define TIM_CCER_CC2E 0x00000010U
7195 #define TIM_CCER_CC2P 0x00000020U
7196 #define TIM_CCER_CC2NE 0x00000040U
7197 #define TIM_CCER_CC2NP 0x00000080U
7198 #define TIM_CCER_CC3E 0x00000100U
7199 #define TIM_CCER_CC3P 0x00000200U
7200 #define TIM_CCER_CC3NE 0x00000400U
7201 #define TIM_CCER_CC3NP 0x00000800U
7202 #define TIM_CCER_CC4E 0x00001000U
7203 #define TIM_CCER_CC4P 0x00002000U
7204 #define TIM_CCER_CC4NP 0x00008000U
7205 #define TIM_CCER_CC5E 0x00010000U
7206 #define TIM_CCER_CC5P 0x00020000U
7207 #define TIM_CCER_CC6E 0x00100000U
7208 #define TIM_CCER_CC6P 0x00200000U
7211 /******************* Bit definition for TIM_CNT register ********************/
7212 #define TIM_CNT_CNT 0xFFFFU
7214 /******************* Bit definition for TIM_PSC register ********************/
7215 #define TIM_PSC_PSC 0xFFFFU
7217 /******************* Bit definition for TIM_ARR register ********************/
7218 #define TIM_ARR_ARR 0xFFFFU
7220 /******************* Bit definition for TIM_RCR register ********************/
7221 #define TIM_RCR_REP ((uint8_t)0xFFU)
7223 /******************* Bit definition for TIM_CCR1 register *******************/
7224 #define TIM_CCR1_CCR1 0xFFFFU
7226 /******************* Bit definition for TIM_CCR2 register *******************/
7227 #define TIM_CCR2_CCR2 0xFFFFU
7229 /******************* Bit definition for TIM_CCR3 register *******************/
7230 #define TIM_CCR3_CCR3 0xFFFFU
7232 /******************* Bit definition for TIM_CCR4 register *******************/
7233 #define TIM_CCR4_CCR4 0xFFFFU
7235 /******************* Bit definition for TIM_BDTR register *******************/
7236 #define TIM_BDTR_DTG 0x000000FFU
7237 #define TIM_BDTR_DTG_0 0x00000001U
7238 #define TIM_BDTR_DTG_1 0x00000002U
7239 #define TIM_BDTR_DTG_2 0x00000004U
7240 #define TIM_BDTR_DTG_3 0x00000008U
7241 #define TIM_BDTR_DTG_4 0x00000010U
7242 #define TIM_BDTR_DTG_5 0x00000020U
7243 #define TIM_BDTR_DTG_6 0x00000040U
7244 #define TIM_BDTR_DTG_7 0x00000080U
7246 #define TIM_BDTR_LOCK 0x00000300U
7247 #define TIM_BDTR_LOCK_0 0x00000100U
7248 #define TIM_BDTR_LOCK_1 0x00000200U
7250 #define TIM_BDTR_OSSI 0x00000400U
7251 #define TIM_BDTR_OSSR 0x00000800U
7252 #define TIM_BDTR_BKE 0x00001000U
7253 #define TIM_BDTR_BKP 0x00002000U
7254 #define TIM_BDTR_AOE 0x00004000U
7255 #define TIM_BDTR_MOE 0x00008000U
7256 #define TIM_BDTR_BKF 0x000F0000U
7257 #define TIM_BDTR_BK2F 0x00F00000U
7258 #define TIM_BDTR_BK2E 0x01000000U
7259 #define TIM_BDTR_BK2P 0x02000000U
7261 /******************* Bit definition for TIM_DCR register ********************/
7262 #define TIM_DCR_DBA 0x001FU
7263 #define TIM_DCR_DBA_0 0x0001U
7264 #define TIM_DCR_DBA_1 0x0002U
7265 #define TIM_DCR_DBA_2 0x0004U
7266 #define TIM_DCR_DBA_3 0x0008U
7267 #define TIM_DCR_DBA_4 0x0010U
7269 #define TIM_DCR_DBL 0x1F00U
7270 #define TIM_DCR_DBL_0 0x0100U
7271 #define TIM_DCR_DBL_1 0x0200U
7272 #define TIM_DCR_DBL_2 0x0400U
7273 #define TIM_DCR_DBL_3 0x0800U
7274 #define TIM_DCR_DBL_4 0x1000U
7276 /******************* Bit definition for TIM_DMAR register *******************/
7277 #define TIM_DMAR_DMAB 0xFFFFU
7279 /******************* Bit definition for TIM_OR regiter *********************/
7280 #define TIM_OR_TI4_RMP 0x00C0U
7281 #define TIM_OR_TI4_RMP_0 0x0040U
7282 #define TIM_OR_TI4_RMP_1 0x0080U
7283 #define TIM_OR_ITR1_RMP 0x0C00U
7284 #define TIM_OR_ITR1_RMP_0 0x0400U
7285 #define TIM_OR_ITR1_RMP_1 0x0800U
7287 /****************** Bit definition for TIM_CCMR3 register *******************/
7288 #define TIM_CCMR3_OC5FE 0x00000004U
7289 #define TIM_CCMR3_OC5PE 0x00000008U
7291 #define TIM_CCMR3_OC5M 0x00010070U
7292 #define TIM_CCMR3_OC5M_0 0x00000010U
7293 #define TIM_CCMR3_OC5M_1 0x00000020U
7294 #define TIM_CCMR3_OC5M_2 0x00000040U
7295 #define TIM_CCMR3_OC5M_3 0x00010000U
7297 #define TIM_CCMR3_OC5CE 0x00000080U
7299 #define TIM_CCMR3_OC6FE 0x00000400U
7300 #define TIM_CCMR3_OC6PE 0x00000800U
7302 #define TIM_CCMR3_OC6M 0x01007000U
7303 #define TIM_CCMR3_OC6M_0 0x00001000U
7304 #define TIM_CCMR3_OC6M_1 0x00002000U
7305 #define TIM_CCMR3_OC6M_2 0x00004000U
7306 #define TIM_CCMR3_OC6M_3 0x01000000U
7308 #define TIM_CCMR3_OC6CE 0x00008000U
7310 /******************* Bit definition for TIM_CCR5 register *******************/
7311 #define TIM_CCR5_CCR5 0xFFFFFFFFU
7312 #define TIM_CCR5_GC5C1 0x20000000U
7313 #define TIM_CCR5_GC5C2 0x40000000U
7314 #define TIM_CCR5_GC5C3 0x80000000U
7316 /******************* Bit definition for TIM_CCR6 register *******************/
7317 #define TIM_CCR6_CCR6 ((uint16_t)0xFFFFU)
7320 /******************************************************************************/
7321 /* */
7322 /* Low Power Timer (LPTIM) */
7323 /* */
7324 /******************************************************************************/
7325 /****************** Bit definition for LPTIM_ISR register *******************/
7326 #define LPTIM_ISR_CMPM 0x00000001U
7327 #define LPTIM_ISR_ARRM 0x00000002U
7328 #define LPTIM_ISR_EXTTRIG 0x00000004U
7329 #define LPTIM_ISR_CMPOK 0x00000008U
7330 #define LPTIM_ISR_ARROK 0x00000010U
7331 #define LPTIM_ISR_UP 0x00000020U
7332 #define LPTIM_ISR_DOWN 0x00000040U
7334 /****************** Bit definition for LPTIM_ICR register *******************/
7335 #define LPTIM_ICR_CMPMCF 0x00000001U
7336 #define LPTIM_ICR_ARRMCF 0x00000002U
7337 #define LPTIM_ICR_EXTTRIGCF 0x00000004U
7338 #define LPTIM_ICR_CMPOKCF 0x00000008U
7339 #define LPTIM_ICR_ARROKCF 0x00000010U
7340 #define LPTIM_ICR_UPCF 0x00000020U
7341 #define LPTIM_ICR_DOWNCF 0x00000040U
7343 /****************** Bit definition for LPTIM_IER register *******************/
7344 #define LPTIM_IER_CMPMIE 0x00000001U
7345 #define LPTIM_IER_ARRMIE 0x00000002U
7346 #define LPTIM_IER_EXTTRIGIE 0x00000004U
7347 #define LPTIM_IER_CMPOKIE 0x00000008U
7348 #define LPTIM_IER_ARROKIE 0x00000010U
7349 #define LPTIM_IER_UPIE 0x00000020U
7350 #define LPTIM_IER_DOWNIE 0x00000040U
7352 /****************** Bit definition for LPTIM_CFGR register*******************/
7353 #define LPTIM_CFGR_CKSEL 0x00000001U
7355 #define LPTIM_CFGR_CKPOL 0x00000006U
7356 #define LPTIM_CFGR_CKPOL_0 0x00000002U
7357 #define LPTIM_CFGR_CKPOL_1 0x00000004U
7359 #define LPTIM_CFGR_CKFLT 0x00000018U
7360 #define LPTIM_CFGR_CKFLT_0 0x00000008U
7361 #define LPTIM_CFGR_CKFLT_1 0x00000010U
7363 #define LPTIM_CFGR_TRGFLT 0x000000C0U
7364 #define LPTIM_CFGR_TRGFLT_0 0x00000040U
7365 #define LPTIM_CFGR_TRGFLT_1 0x00000080U
7367 #define LPTIM_CFGR_PRESC 0x00000E00U
7368 #define LPTIM_CFGR_PRESC_0 0x00000200U
7369 #define LPTIM_CFGR_PRESC_1 0x00000400U
7370 #define LPTIM_CFGR_PRESC_2 0x00000800U
7372 #define LPTIM_CFGR_TRIGSEL 0x0000E000U
7373 #define LPTIM_CFGR_TRIGSEL_0 0x00002000U
7374 #define LPTIM_CFGR_TRIGSEL_1 0x00004000U
7375 #define LPTIM_CFGR_TRIGSEL_2 0x00008000U
7377 #define LPTIM_CFGR_TRIGEN 0x00060000U
7378 #define LPTIM_CFGR_TRIGEN_0 0x00020000U
7379 #define LPTIM_CFGR_TRIGEN_1 0x00040000U
7381 #define LPTIM_CFGR_TIMOUT 0x00080000U
7382 #define LPTIM_CFGR_WAVE 0x00100000U
7383 #define LPTIM_CFGR_WAVPOL 0x00200000U
7384 #define LPTIM_CFGR_PRELOAD 0x00400000U
7385 #define LPTIM_CFGR_COUNTMODE 0x00800000U
7386 #define LPTIM_CFGR_ENC 0x01000000U
7388 /****************** Bit definition for LPTIM_CR register ********************/
7389 #define LPTIM_CR_ENABLE 0x00000001U
7390 #define LPTIM_CR_SNGSTRT 0x00000002U
7391 #define LPTIM_CR_CNTSTRT 0x00000004U
7393 /****************** Bit definition for LPTIM_CMP register *******************/
7394 #define LPTIM_CMP_CMP 0x0000FFFFU
7396 /****************** Bit definition for LPTIM_ARR register *******************/
7397 #define LPTIM_ARR_ARR 0x0000FFFFU
7399 /****************** Bit definition for LPTIM_CNT register *******************/
7400 #define LPTIM_CNT_CNT 0x0000FFFFU
7401 /******************************************************************************/
7402 /* */
7403 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
7404 /* */
7405 /******************************************************************************/
7406 /****************** Bit definition for USART_CR1 register *******************/
7407 #define USART_CR1_UE 0x00000001U
7408 #define USART_CR1_RE 0x00000004U
7409 #define USART_CR1_TE 0x00000008U
7410 #define USART_CR1_IDLEIE 0x00000010U
7411 #define USART_CR1_RXNEIE 0x00000020U
7412 #define USART_CR1_TCIE 0x00000040U
7413 #define USART_CR1_TXEIE 0x00000080U
7414 #define USART_CR1_PEIE 0x00000100U
7415 #define USART_CR1_PS 0x00000200U
7416 #define USART_CR1_PCE 0x00000400U
7417 #define USART_CR1_WAKE 0x00000800U
7418 #define USART_CR1_M 0x10001000U
7419 #define USART_CR1_M_0 0x00001000U
7420 #define USART_CR1_MME 0x00002000U
7421 #define USART_CR1_CMIE 0x00004000U
7422 #define USART_CR1_OVER8 0x00008000U
7423 #define USART_CR1_DEDT 0x001F0000U
7424 #define USART_CR1_DEDT_0 0x00010000U
7425 #define USART_CR1_DEDT_1 0x00020000U
7426 #define USART_CR1_DEDT_2 0x00040000U
7427 #define USART_CR1_DEDT_3 0x00080000U
7428 #define USART_CR1_DEDT_4 0x00100000U
7429 #define USART_CR1_DEAT 0x03E00000U
7430 #define USART_CR1_DEAT_0 0x00200000U
7431 #define USART_CR1_DEAT_1 0x00400000U
7432 #define USART_CR1_DEAT_2 0x00800000U
7433 #define USART_CR1_DEAT_3 0x01000000U
7434 #define USART_CR1_DEAT_4 0x02000000U
7435 #define USART_CR1_RTOIE 0x04000000U
7436 #define USART_CR1_EOBIE 0x08000000U
7437 #define USART_CR1_M_1 0x10000000U
7439 /****************** Bit definition for USART_CR2 register *******************/
7440 #define USART_CR2_ADDM7 0x00000010U
7441 #define USART_CR2_LBDL 0x00000020U
7442 #define USART_CR2_LBDIE 0x00000040U
7443 #define USART_CR2_LBCL 0x00000100U
7444 #define USART_CR2_CPHA 0x00000200U
7445 #define USART_CR2_CPOL 0x00000400U
7446 #define USART_CR2_CLKEN 0x00000800U
7447 #define USART_CR2_STOP 0x00003000U
7448 #define USART_CR2_STOP_0 0x00001000U
7449 #define USART_CR2_STOP_1 0x00002000U
7450 #define USART_CR2_LINEN 0x00004000U
7451 #define USART_CR2_SWAP 0x00008000U
7452 #define USART_CR2_RXINV 0x00010000U
7453 #define USART_CR2_TXINV 0x00020000U
7454 #define USART_CR2_DATAINV 0x00040000U
7455 #define USART_CR2_MSBFIRST 0x00080000U
7456 #define USART_CR2_ABREN 0x00100000U
7457 #define USART_CR2_ABRMODE 0x00600000U
7458 #define USART_CR2_ABRMODE_0 0x00200000U
7459 #define USART_CR2_ABRMODE_1 0x00400000U
7460 #define USART_CR2_RTOEN 0x00800000U
7461 #define USART_CR2_ADD 0xFF000000U
7463 /****************** Bit definition for USART_CR3 register *******************/
7464 #define USART_CR3_EIE 0x00000001U
7465 #define USART_CR3_IREN 0x00000002U
7466 #define USART_CR3_IRLP 0x00000004U
7467 #define USART_CR3_HDSEL 0x00000008U
7468 #define USART_CR3_NACK 0x00000010U
7469 #define USART_CR3_SCEN 0x00000020U
7470 #define USART_CR3_DMAR 0x00000040U
7471 #define USART_CR3_DMAT 0x00000080U
7472 #define USART_CR3_RTSE 0x00000100U
7473 #define USART_CR3_CTSE 0x00000200U
7474 #define USART_CR3_CTSIE 0x00000400U
7475 #define USART_CR3_ONEBIT 0x00000800U
7476 #define USART_CR3_OVRDIS 0x00001000U
7477 #define USART_CR3_DDRE 0x00002000U
7478 #define USART_CR3_DEM 0x00004000U
7479 #define USART_CR3_DEP 0x00008000U
7480 #define USART_CR3_SCARCNT 0x000E0000U
7481 #define USART_CR3_SCARCNT_0 0x00020000U
7482 #define USART_CR3_SCARCNT_1 0x00040000U
7483 #define USART_CR3_SCARCNT_2 0x00080000U
7486 /****************** Bit definition for USART_BRR register *******************/
7487 #define USART_BRR_DIV_FRACTION 0x000FU
7488 #define USART_BRR_DIV_MANTISSA 0xFFF0U
7490 /****************** Bit definition for USART_GTPR register ******************/
7491 #define USART_GTPR_PSC 0x00FFU
7492 #define USART_GTPR_GT 0xFF00U
7495 /******************* Bit definition for USART_RTOR register *****************/
7496 #define USART_RTOR_RTO 0x00FFFFFFU
7497 #define USART_RTOR_BLEN 0xFF000000U
7499 /******************* Bit definition for USART_RQR register ******************/
7500 #define USART_RQR_ABRRQ 0x0001U
7501 #define USART_RQR_SBKRQ 0x0002U
7502 #define USART_RQR_MMRQ 0x0004U
7503 #define USART_RQR_RXFRQ 0x0008U
7504 #define USART_RQR_TXFRQ 0x0010U
7506 /******************* Bit definition for USART_ISR register ******************/
7507 #define USART_ISR_PE 0x00000001U
7508 #define USART_ISR_FE 0x00000002U
7509 #define USART_ISR_NE 0x00000004U
7510 #define USART_ISR_ORE 0x00000008U
7511 #define USART_ISR_IDLE 0x00000010U
7512 #define USART_ISR_RXNE 0x00000020U
7513 #define USART_ISR_TC 0x00000040U
7514 #define USART_ISR_TXE 0x00000080U
7515 #define USART_ISR_LBDF 0x00000100U
7516 #define USART_ISR_CTSIF 0x00000200U
7517 #define USART_ISR_CTS 0x00000400U
7518 #define USART_ISR_RTOF 0x00000800U
7519 #define USART_ISR_EOBF 0x00001000U
7520 #define USART_ISR_ABRE 0x00004000U
7521 #define USART_ISR_ABRF 0x00008000U
7522 #define USART_ISR_BUSY 0x00010000U
7523 #define USART_ISR_CMF 0x00020000U
7524 #define USART_ISR_SBKF 0x00040000U
7525 #define USART_ISR_RWU 0x00080000U
7526 #define USART_ISR_WUF 0x00100000U
7527 #define USART_ISR_TEACK 0x00200000U
7528 #define USART_ISR_REACK 0x00400000U
7530 /* Legacy define */
7531 #define USART_ISR_LBD USART_ISR_LBDF
7532 
7533 /******************* Bit definition for USART_ICR register ******************/
7534 #define USART_ICR_PECF 0x00000001U
7535 #define USART_ICR_FECF 0x00000002U
7536 #define USART_ICR_NCF 0x00000004U
7537 #define USART_ICR_ORECF 0x00000008U
7538 #define USART_ICR_IDLECF 0x00000010U
7539 #define USART_ICR_TCCF 0x00000040U
7540 #define USART_ICR_LBDCF 0x00000100U
7541 #define USART_ICR_CTSCF 0x00000200U
7542 #define USART_ICR_RTOCF 0x00000800U
7543 #define USART_ICR_EOBCF 0x00001000U
7544 #define USART_ICR_CMCF 0x00020000U
7545 #define USART_ICR_WUCF 0x00100000U
7547 /******************* Bit definition for USART_RDR register ******************/
7548 #define USART_RDR_RDR 0x01FFU
7550 /******************* Bit definition for USART_TDR register ******************/
7551 #define USART_TDR_TDR 0x01FFU
7553 /******************************************************************************/
7554 /* */
7555 /* Window WATCHDOG */
7556 /* */
7557 /******************************************************************************/
7558 /******************* Bit definition for WWDG_CR register ********************/
7559 #define WWDG_CR_T 0x7FU
7560 #define WWDG_CR_T_0 0x01U
7561 #define WWDG_CR_T_1 0x02U
7562 #define WWDG_CR_T_2 0x04U
7563 #define WWDG_CR_T_3 0x08U
7564 #define WWDG_CR_T_4 0x10U
7565 #define WWDG_CR_T_5 0x20U
7566 #define WWDG_CR_T_6 0x40U
7568 /* Legacy defines */
7569 #define WWDG_CR_T0 WWDG_CR_T_0
7570 #define WWDG_CR_T1 WWDG_CR_T_1
7571 #define WWDG_CR_T2 WWDG_CR_T_2
7572 #define WWDG_CR_T3 WWDG_CR_T_3
7573 #define WWDG_CR_T4 WWDG_CR_T_4
7574 #define WWDG_CR_T5 WWDG_CR_T_5
7575 #define WWDG_CR_T6 WWDG_CR_T_6
7577 #define WWDG_CR_WDGA 0x80U
7579 /******************* Bit definition for WWDG_CFR register *******************/
7580 #define WWDG_CFR_W 0x007FU
7581 #define WWDG_CFR_W_0 0x0001U
7582 #define WWDG_CFR_W_1 0x0002U
7583 #define WWDG_CFR_W_2 0x0004U
7584 #define WWDG_CFR_W_3 0x0008U
7585 #define WWDG_CFR_W_4 0x0010U
7586 #define WWDG_CFR_W_5 0x0020U
7587 #define WWDG_CFR_W_6 0x0040U
7589 /* Legacy defines */
7590 #define WWDG_CFR_W0 WWDG_CFR_W_0
7591 #define WWDG_CFR_W1 WWDG_CFR_W_1
7592 #define WWDG_CFR_W2 WWDG_CFR_W_2
7593 #define WWDG_CFR_W3 WWDG_CFR_W_3
7594 #define WWDG_CFR_W4 WWDG_CFR_W_4
7595 #define WWDG_CFR_W5 WWDG_CFR_W_5
7596 #define WWDG_CFR_W6 WWDG_CFR_W_6
7598 #define WWDG_CFR_WDGTB 0x0180U
7599 #define WWDG_CFR_WDGTB_0 0x0080U
7600 #define WWDG_CFR_WDGTB_1 0x0100U
7602 /* Legacy defines */
7603 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
7604 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
7606 #define WWDG_CFR_EWI 0x0200U
7608 /******************* Bit definition for WWDG_SR register ********************/
7609 #define WWDG_SR_EWIF 0x01U
7611 /******************************************************************************/
7612 /* */
7613 /* DBG */
7614 /* */
7615 /******************************************************************************/
7616 /******************** Bit definition for DBGMCU_IDCODE register *************/
7617 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
7618 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
7619 
7620 /******************** Bit definition for DBGMCU_CR register *****************/
7621 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
7622 #define DBGMCU_CR_DBG_STOP 0x00000002U
7623 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
7624 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
7625 
7626 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
7627 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U
7628 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U
7630 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
7631 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
7632 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
7633 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
7634 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
7635 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
7636 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
7637 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
7638 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
7639 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
7640 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
7641 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
7642 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
7643 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
7644 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
7645 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
7646 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
7647 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
7648 
7649 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
7650 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
7651 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
7652 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
7653 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
7654 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
7655 
7656 /******************************************************************************/
7657 /* */
7658 /* Ethernet MAC Registers bits definitions */
7659 /* */
7660 /******************************************************************************/
7661 /* Bit definition for Ethernet MAC Control Register register */
7662 #define ETH_MACCR_WD 0x00800000U /* Watchdog disable */
7663 #define ETH_MACCR_JD 0x00400000U /* Jabber disable */
7664 #define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */
7665 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
7666 #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
7667 #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
7668 #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
7669 #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
7670 #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
7671 #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
7672 #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
7673 #define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */
7674 #define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */
7675 #define ETH_MACCR_ROD 0x00002000U /* Receive own disable */
7676 #define ETH_MACCR_LM 0x00001000U /* loopback mode */
7677 #define ETH_MACCR_DM 0x00000800U /* Duplex mode */
7678 #define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */
7679 #define ETH_MACCR_RD 0x00000200U /* Retry disable */
7680 #define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */
7681 #define ETH_MACCR_BL 0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling
7682  a transmission attempt during retries after a collision: 0 =< r <2^k */
7683 #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
7684 #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
7685 #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
7686 #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
7687 #define ETH_MACCR_DC 0x00000010U /* Defferal check */
7688 #define ETH_MACCR_TE 0x00000008U /* Transmitter enable */
7689 #define ETH_MACCR_RE 0x00000004U /* Receiver enable */
7690 
7691 /* Bit definition for Ethernet MAC Frame Filter Register */
7692 #define ETH_MACFFR_RA 0x80000000U /* Receive all */
7693 #define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */
7694 #define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */
7695 #define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */
7696 #define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */
7697 #define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */
7698 #define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
7699 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
7700 #define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */
7701 #define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */
7702 #define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */
7703 #define ETH_MACFFR_HM 0x00000004U /* Hash multicast */
7704 #define ETH_MACFFR_HU 0x00000002U /* Hash unicast */
7705 #define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */
7706 
7707 /* Bit definition for Ethernet MAC Hash Table High Register */
7708 #define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */
7709 
7710 /* Bit definition for Ethernet MAC Hash Table Low Register */
7711 #define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */
7712 
7713 /* Bit definition for Ethernet MAC MII Address Register */
7714 #define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */
7715 #define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */
7716 #define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */
7717 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
7718 #define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
7719 #define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
7720 #define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
7721 #define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
7722 #define ETH_MACMIIAR_MW 0x00000002U /* MII write */
7723 #define ETH_MACMIIAR_MB 0x00000001U /* MII busy */
7724 
7725 /* Bit definition for Ethernet MAC MII Data Register */
7726 #define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */
7727 
7728 /* Bit definition for Ethernet MAC Flow Control Register */
7729 #define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */
7730 #define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */
7731 #define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */
7732 #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
7733 #define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */
7734 #define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */
7735 #define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */
7736 #define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */
7737 #define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */
7738 #define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */
7739 #define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */
7740 
7741 /* Bit definition for Ethernet MAC VLAN Tag Register */
7742 #define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */
7743 #define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */
7744 
7745 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
7746 #define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */
7747 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
7748  Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
7749 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
7750  Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
7751  Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
7752  Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
7753  Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
7754  RSVD - Filter1 Command - RSVD - Filter0 Command
7755  Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
7756  Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
7757  Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
7758 
7759 /* Bit definition for Ethernet MAC PMT Control and Status Register */
7760 #define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
7761 #define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */
7762 #define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */
7763 #define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */
7764 #define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */
7765 #define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */
7766 #define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */
7767 
7768 /* Bit definition for Ethernet MAC Status Register */
7769 #define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */
7770 #define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */
7771 #define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */
7772 #define ETH_MACSR_MMCS 0x00000010U /* MMC status */
7773 #define ETH_MACSR_PMTS 0x00000008U /* PMT status */
7774 
7775 /* Bit definition for Ethernet MAC Interrupt Mask Register */
7776 #define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */
7777 #define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */
7778 
7779 /* Bit definition for Ethernet MAC Address0 High Register */
7780 #define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */
7781 
7782 /* Bit definition for Ethernet MAC Address0 Low Register */
7783 #define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */
7784 
7785 /* Bit definition for Ethernet MAC Address1 High Register */
7786 #define ETH_MACA1HR_AE 0x80000000U /* Address enable */
7787 #define ETH_MACA1HR_SA 0x40000000U /* Source address */
7788 #define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
7789  #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
7790  #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
7791  #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
7792  #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
7793  #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
7794  #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
7795 #define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */
7796 
7797 /* Bit definition for Ethernet MAC Address1 Low Register */
7798 #define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */
7799 
7800 /* Bit definition for Ethernet MAC Address2 High Register */
7801 #define ETH_MACA2HR_AE 0x80000000U /* Address enable */
7802 #define ETH_MACA2HR_SA 0x40000000U /* Source address */
7803 #define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */
7804  #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
7805  #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
7806  #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
7807  #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
7808  #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
7809  #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
7810 #define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */
7811 
7812 /* Bit definition for Ethernet MAC Address2 Low Register */
7813 #define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */
7814 
7815 /* Bit definition for Ethernet MAC Address3 High Register */
7816 #define ETH_MACA3HR_AE 0x80000000U /* Address enable */
7817 #define ETH_MACA3HR_SA 0x40000000U /* Source address */
7818 #define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */
7819  #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
7820  #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
7821  #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
7822  #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
7823  #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
7824  #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
7825 #define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */
7826 
7827 /* Bit definition for Ethernet MAC Address3 Low Register */
7828 #define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */
7829 
7830 /******************************************************************************/
7831 /* Ethernet MMC Registers bits definition */
7832 /******************************************************************************/
7833 
7834 /* Bit definition for Ethernet MMC Contol Register */
7835 #define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */
7836 #define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */
7837 #define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */
7838 #define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */
7839 #define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */
7840 #define ETH_MMCCR_CR 0x00000001U /* Counters Reset */
7841 
7842 /* Bit definition for Ethernet MMC Receive Interrupt Register */
7843 #define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
7844 #define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
7845 #define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
7846 
7847 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
7848 #define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
7849 #define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
7850 #define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
7851 
7852 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
7853 #define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
7854 #define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
7855 #define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
7856 
7857 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
7858 #define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
7859 #define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
7860 #define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
7861 
7862 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
7863 #define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
7864 
7865 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
7866 #define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
7867 
7868 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
7869 #define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */
7870 
7871 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
7872 #define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */
7873 
7874 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
7875 #define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
7876 
7877 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
7878 #define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */
7879 
7880 /******************************************************************************/
7881 /* Ethernet PTP Registers bits definition */
7882 /******************************************************************************/
7883 
7884 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
7885 #define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */
7886 #define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */
7887 #define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */
7888 #define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */
7889 #define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */
7890 #define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
7891 #define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
7892 #define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */
7893 #define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */
7894 
7895 #define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */
7896 #define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */
7897 #define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */
7898 #define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */
7899 #define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */
7900 #define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */
7901 
7902 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
7903 #define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */
7904 
7905 /* Bit definition for Ethernet PTP Time Stamp High Register */
7906 #define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */
7907 
7908 /* Bit definition for Ethernet PTP Time Stamp Low Register */
7909 #define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */
7910 #define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */
7911 
7912 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
7913 #define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */
7914 
7915 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
7916 #define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */
7917 #define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */
7918 
7919 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
7920 #define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */
7921 
7922 /* Bit definition for Ethernet PTP Target Time High Register */
7923 #define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */
7924 
7925 /* Bit definition for Ethernet PTP Target Time Low Register */
7926 #define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */
7927 
7928 /* Bit definition for Ethernet PTP Time Stamp Status Register */
7929 #define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */
7930 #define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */
7931 
7932 /******************************************************************************/
7933 /* Ethernet DMA Registers bits definition */
7934 /******************************************************************************/
7935 
7936 /* Bit definition for Ethernet DMA Bus Mode Register */
7937 #define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */
7938 #define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */
7939 #define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */
7940 #define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */
7941  #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
7942  #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
7943  #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
7944  #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
7945  #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
7946  #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
7947  #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
7948  #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
7949  #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
7950  #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
7951  #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
7952  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
7953 #define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */
7954 #define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */
7955  #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
7956  #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
7957  #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
7958  #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
7959 #define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */
7960  #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
7961  #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
7962  #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
7963  #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
7964  #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
7965  #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
7966  #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
7967  #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
7968  #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
7969  #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
7970  #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
7971  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
7972 #define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */
7973 #define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */
7974 #define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */
7975 #define ETH_DMABMR_SR 0x00000001U /* Software reset */
7976 
7977 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
7978 #define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */
7979 
7980 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
7981 #define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */
7982 
7983 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
7984 #define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */
7985 
7986 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
7987 #define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */
7988 
7989 /* Bit definition for Ethernet DMA Status Register */
7990 #define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */
7991 #define ETH_DMASR_PMTS 0x10000000U /* PMT status */
7992 #define ETH_DMASR_MMCS 0x08000000U /* MMC status */
7993 #define ETH_DMASR_EBS 0x03800000U /* Error bits status */
7994  /* combination with EBS[2:0] for GetFlagStatus function */
7995  #define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */
7996  #define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
7997  #define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
7998 #define ETH_DMASR_TPS 0x00700000U /* Transmit process state */
7999  #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
8000  #define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */
8001  #define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */
8002  #define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */
8003  #define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */
8004  #define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */
8005 #define ETH_DMASR_RPS 0x000E0000U /* Receive process state */
8006  #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
8007  #define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */
8008  #define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */
8009  #define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */
8010  #define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */
8011  #define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */
8012 #define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */
8013 #define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */
8014 #define ETH_DMASR_ERS 0x00004000U /* Early receive status */
8015 #define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */
8016 #define ETH_DMASR_ETS 0x00000400U /* Early transmit status */
8017 #define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */
8018 #define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */
8019 #define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */
8020 #define ETH_DMASR_RS 0x00000040U /* Receive status */
8021 #define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */
8022 #define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */
8023 #define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */
8024 #define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */
8025 #define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */
8026 #define ETH_DMASR_TS 0x00000001U /* Transmit status */
8027 
8028 /* Bit definition for Ethernet DMA Operation Mode Register */
8029 #define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
8030 #define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */
8031 #define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */
8032 #define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */
8033 #define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */
8034 #define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */
8035  #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
8036  #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
8037  #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
8038  #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
8039  #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
8040  #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
8041  #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
8042  #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
8043 #define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */
8044 #define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */
8045 #define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */
8046 #define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */
8047  #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
8048  #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
8049  #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
8050  #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
8051 #define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */
8052 #define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */
8053 
8054 /* Bit definition for Ethernet DMA Interrupt Enable Register */
8055 #define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */
8056 #define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */
8057 #define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */
8058 #define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */
8059 #define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */
8060 #define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */
8061 #define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */
8062 #define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */
8063 #define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */
8064 #define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */
8065 #define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */
8066 #define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */
8067 #define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */
8068 #define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */
8069 #define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */
8070 
8071 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
8072 #define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */
8073 #define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */
8074 #define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */
8075 #define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */
8076 
8077 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
8078 #define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */
8079 
8080 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
8081 #define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */
8082 
8083 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
8084 #define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */
8085 
8086 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
8087 #define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */
8088 
8089 /******************************************************************************/
8090 /* */
8091 /* USB_OTG */
8092 /* */
8093 /******************************************************************************/
8094 /******************** Bit definition for USB_OTG_GOTGCTL register ********************/
8095 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U
8096 #define USB_OTG_GOTGCTL_SRQ 0x00000002U
8097 #define USB_OTG_GOTGCTL_VBVALOEN 0x00000004U
8098 #define USB_OTG_GOTGCTL_VBVALOVAL 0x00000008U
8099 #define USB_OTG_GOTGCTL_AVALOEN 0x00000010U
8100 #define USB_OTG_GOTGCTL_AVALOVAL 0x00000020U
8101 #define USB_OTG_GOTGCTL_BVALOEN 0x00000040U
8102 #define USB_OTG_GOTGCTL_BVALOVAL 0x00000080U
8103 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U
8104 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U
8105 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U
8106 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U
8107 #define USB_OTG_GOTGCTL_EHEN 0x00001000U
8108 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U
8109 #define USB_OTG_GOTGCTL_DBCT 0x00020000U
8110 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U
8111 #define USB_OTG_GOTGCTL_BSESVLD 0x00080000U
8112 #define USB_OTG_GOTGCTL_OTGVER 0x00100000U
8114 /******************** Bit definition for USB_OTG_HCFG register ********************/
8115 #define USB_OTG_HCFG_FSLSPCS 0x00000003U
8116 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U
8117 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U
8118 #define USB_OTG_HCFG_FSLSS 0x00000004U
8120 /******************** Bit definition for USB_OTG_DCFG register ********************/
8121 #define USB_OTG_DCFG_DSPD 0x00000003U
8122 #define USB_OTG_DCFG_DSPD_0 0x00000001U
8123 #define USB_OTG_DCFG_DSPD_1 0x00000002U
8124 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U
8126 #define USB_OTG_DCFG_DAD 0x000007F0U
8127 #define USB_OTG_DCFG_DAD_0 0x00000010U
8128 #define USB_OTG_DCFG_DAD_1 0x00000020U
8129 #define USB_OTG_DCFG_DAD_2 0x00000040U
8130 #define USB_OTG_DCFG_DAD_3 0x00000080U
8131 #define USB_OTG_DCFG_DAD_4 0x00000100U
8132 #define USB_OTG_DCFG_DAD_5 0x00000200U
8133 #define USB_OTG_DCFG_DAD_6 0x00000400U
8135 #define USB_OTG_DCFG_PFIVL 0x00001800U
8136 #define USB_OTG_DCFG_PFIVL_0 0x00000800U
8137 #define USB_OTG_DCFG_PFIVL_1 0x00001000U
8139 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U
8140 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U
8141 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U
8143 /******************** Bit definition for USB_OTG_PCGCR register ********************/
8144 #define USB_OTG_PCGCR_STPPCLK 0x00000001U
8145 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U
8146 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U
8148 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
8149 #define USB_OTG_GOTGINT_SEDET 0x00000004U
8150 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U
8151 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U
8152 #define USB_OTG_GOTGINT_HNGDET 0x00020000U
8153 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U
8154 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U
8155 #define USB_OTG_GOTGINT_IDCHNG 0x00100000U
8157 /******************** Bit definition for USB_OTG_DCTL register ********************/
8158 #define USB_OTG_DCTL_RWUSIG 0x00000001U
8159 #define USB_OTG_DCTL_SDIS 0x00000002U
8160 #define USB_OTG_DCTL_GINSTS 0x00000004U
8161 #define USB_OTG_DCTL_GONSTS 0x00000008U
8163 #define USB_OTG_DCTL_TCTL 0x00000070U
8164 #define USB_OTG_DCTL_TCTL_0 0x00000010U
8165 #define USB_OTG_DCTL_TCTL_1 0x00000020U
8166 #define USB_OTG_DCTL_TCTL_2 0x00000040U
8167 #define USB_OTG_DCTL_SGINAK 0x00000080U
8168 #define USB_OTG_DCTL_CGINAK 0x00000100U
8169 #define USB_OTG_DCTL_SGONAK 0x00000200U
8170 #define USB_OTG_DCTL_CGONAK 0x00000400U
8171 #define USB_OTG_DCTL_POPRGDNE 0x00000800U
8173 /******************** Bit definition for USB_OTG_HFIR register ********************/
8174 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU
8176 /******************** Bit definition for USB_OTG_HFNUM register ********************/
8177 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU
8178 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U
8180 /******************** Bit definition for USB_OTG_DSTS register ********************/
8181 #define USB_OTG_DSTS_SUSPSTS 0x00000001U
8183 #define USB_OTG_DSTS_ENUMSPD 0x00000006U
8184 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U
8185 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U
8186 #define USB_OTG_DSTS_EERR 0x00000008U
8187 #define USB_OTG_DSTS_FNSOF 0x003FFF00U
8189 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
8190 #define USB_OTG_GAHBCFG_GINT 0x00000001U
8191 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU
8192 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U
8193 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U
8194 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U
8195 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U
8196 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U
8197 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U
8198 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U
8200 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
8201 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U
8202 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U
8203 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U
8204 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U
8205 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U
8206 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U
8207 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U
8208 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U
8209 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U
8210 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U
8211 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U
8212 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U
8213 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U
8214 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U
8215 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U
8216 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U
8217 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U
8218 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U
8219 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U
8220 #define USB_OTG_GUSBCFG_PCCI 0x00800000U
8221 #define USB_OTG_GUSBCFG_PTCI 0x01000000U
8222 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U
8223 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U
8224 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U
8225 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U
8227 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
8228 #define USB_OTG_GRSTCTL_CSRST 0x00000001U
8229 #define USB_OTG_GRSTCTL_HSRST 0x00000002U
8230 #define USB_OTG_GRSTCTL_FCRST 0x00000004U
8231 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U
8232 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U
8233 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U
8234 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U
8235 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U
8236 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U
8237 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U
8238 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U
8239 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U
8240 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U
8242 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
8243 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U
8244 #define USB_OTG_DIEPMSK_EPDM 0x00000002U
8245 #define USB_OTG_DIEPMSK_TOM 0x00000008U
8246 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U
8247 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U
8248 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U
8249 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U
8250 #define USB_OTG_DIEPMSK_BIM 0x00000200U
8252 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
8253 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU
8254 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U
8255 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U
8256 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U
8257 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U
8258 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U
8259 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U
8260 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U
8261 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U
8262 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U
8264 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U
8265 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U
8266 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U
8267 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U
8268 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U
8269 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U
8270 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U
8271 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U
8272 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U
8274 /******************** Bit definition for USB_OTG_HAINT register ********************/
8275 #define USB_OTG_HAINT_HAINT 0x0000FFFFU
8277 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
8278 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U
8279 #define USB_OTG_DOEPMSK_EPDM 0x00000002U
8280 #define USB_OTG_DOEPMSK_STUPM 0x00000008U
8281 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U
8282 #define USB_OTG_DOEPMSK_OTEPSPRM 0x00000020U
8283 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U
8284 #define USB_OTG_DOEPMSK_OPEM 0x00000100U
8285 #define USB_OTG_DOEPMSK_BOIM 0x00000200U
8287 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
8288 #define USB_OTG_GINTSTS_CMOD 0x00000001U
8289 #define USB_OTG_GINTSTS_MMIS 0x00000002U
8290 #define USB_OTG_GINTSTS_OTGINT 0x00000004U
8291 #define USB_OTG_GINTSTS_SOF 0x00000008U
8292 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U
8293 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U
8294 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U
8295 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U
8296 #define USB_OTG_GINTSTS_ESUSP 0x00000400U
8297 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U
8298 #define USB_OTG_GINTSTS_USBRST 0x00001000U
8299 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U
8300 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U
8301 #define USB_OTG_GINTSTS_EOPF 0x00008000U
8302 #define USB_OTG_GINTSTS_IEPINT 0x00040000U
8303 #define USB_OTG_GINTSTS_OEPINT 0x00080000U
8304 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U
8305 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U
8306 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U
8307 #define USB_OTG_GINTSTS_RSTDET 0x00800000U
8308 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U
8309 #define USB_OTG_GINTSTS_HCINT 0x02000000U
8310 #define USB_OTG_GINTSTS_PTXFE 0x04000000U
8311 #define USB_OTG_GINTSTS_LPMINT 0x08000000U
8312 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U
8313 #define USB_OTG_GINTSTS_DISCINT 0x20000000U
8314 #define USB_OTG_GINTSTS_SRQINT 0x40000000U
8315 #define USB_OTG_GINTSTS_WKUINT 0x80000000U
8317 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
8318 #define USB_OTG_GINTMSK_MMISM 0x00000002U
8319 #define USB_OTG_GINTMSK_OTGINT 0x00000004U
8320 #define USB_OTG_GINTMSK_SOFM 0x00000008U
8321 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U
8322 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U
8323 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U
8324 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U
8325 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U
8326 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U
8327 #define USB_OTG_GINTMSK_USBRST 0x00001000U
8328 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U
8329 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U
8330 #define USB_OTG_GINTMSK_EOPFM 0x00008000U
8331 #define USB_OTG_GINTMSK_EPMISM 0x00020000U
8332 #define USB_OTG_GINTMSK_IEPINT 0x00040000U
8333 #define USB_OTG_GINTMSK_OEPINT 0x00080000U
8334 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U
8335 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U
8336 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U
8337 #define USB_OTG_GINTMSK_RSTDEM 0x00800000U
8338 #define USB_OTG_GINTMSK_PRTIM 0x01000000U
8339 #define USB_OTG_GINTMSK_HCIM 0x02000000U
8340 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U
8341 #define USB_OTG_GINTMSK_LPMINTM 0x08000000U
8342 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U
8343 #define USB_OTG_GINTMSK_DISCINT 0x20000000U
8344 #define USB_OTG_GINTMSK_SRQIM 0x40000000U
8345 #define USB_OTG_GINTMSK_WUIM 0x80000000U
8347 /******************** Bit definition for USB_OTG_DAINT register ********************/
8348 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU
8349 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U
8351 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
8352 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU
8354 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
8355 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU
8356 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U
8357 #define USB_OTG_GRXSTSP_DPID 0x00018000U
8358 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U
8360 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
8361 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU
8362 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U
8364 /******************** Bit definition for OTG register ********************/
8365 
8366 #define USB_OTG_CHNUM 0x0000000FU
8367 #define USB_OTG_CHNUM_0 0x00000001U
8368 #define USB_OTG_CHNUM_1 0x00000002U
8369 #define USB_OTG_CHNUM_2 0x00000004U
8370 #define USB_OTG_CHNUM_3 0x00000008U
8371 #define USB_OTG_BCNT 0x00007FF0U
8373 #define USB_OTG_DPID 0x00018000U
8374 #define USB_OTG_DPID_0 0x00008000U
8375 #define USB_OTG_DPID_1 0x00010000U
8377 #define USB_OTG_PKTSTS 0x001E0000U
8378 #define USB_OTG_PKTSTS_0 0x00020000U
8379 #define USB_OTG_PKTSTS_1 0x00040000U
8380 #define USB_OTG_PKTSTS_2 0x00080000U
8381 #define USB_OTG_PKTSTS_3 0x00100000U
8383 #define USB_OTG_EPNUM 0x0000000FU
8384 #define USB_OTG_EPNUM_0 0x00000001U
8385 #define USB_OTG_EPNUM_1 0x00000002U
8386 #define USB_OTG_EPNUM_2 0x00000004U
8387 #define USB_OTG_EPNUM_3 0x00000008U
8389 #define USB_OTG_FRMNUM 0x01E00000U
8390 #define USB_OTG_FRMNUM_0 0x00200000U
8391 #define USB_OTG_FRMNUM_1 0x00400000U
8392 #define USB_OTG_FRMNUM_2 0x00800000U
8393 #define USB_OTG_FRMNUM_3 0x01000000U
8395 /******************** Bit definition for OTG register ********************/
8396 
8397 #define USB_OTG_CHNUM 0x0000000FU
8398 #define USB_OTG_CHNUM_0 0x00000001U
8399 #define USB_OTG_CHNUM_1 0x00000002U
8400 #define USB_OTG_CHNUM_2 0x00000004U
8401 #define USB_OTG_CHNUM_3 0x00000008U
8402 #define USB_OTG_BCNT 0x00007FF0U
8404 #define USB_OTG_DPID 0x00018000U
8405 #define USB_OTG_DPID_0 0x00008000U
8406 #define USB_OTG_DPID_1 0x00010000U
8408 #define USB_OTG_PKTSTS 0x001E0000U
8409 #define USB_OTG_PKTSTS_0 0x00020000U
8410 #define USB_OTG_PKTSTS_1 0x00040000U
8411 #define USB_OTG_PKTSTS_2 0x00080000U
8412 #define USB_OTG_PKTSTS_3 0x00100000U
8414 #define USB_OTG_EPNUM 0x0000000FU
8415 #define USB_OTG_EPNUM_0 0x00000001U
8416 #define USB_OTG_EPNUM_1 0x00000002U
8417 #define USB_OTG_EPNUM_2 0x00000004U
8418 #define USB_OTG_EPNUM_3 0x00000008U
8420 #define USB_OTG_FRMNUM 0x01E00000U
8421 #define USB_OTG_FRMNUM_0 0x00200000U
8422 #define USB_OTG_FRMNUM_1 0x00400000U
8423 #define USB_OTG_FRMNUM_2 0x00800000U
8424 #define USB_OTG_FRMNUM_3 0x01000000U
8426 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
8427 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU
8429 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
8430 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU
8432 /******************** Bit definition for OTG register ********************/
8433 #define USB_OTG_NPTXFSA 0x0000FFFFU
8434 #define USB_OTG_NPTXFD 0xFFFF0000U
8435 #define USB_OTG_TX0FSA 0x0000FFFFU
8436 #define USB_OTG_TX0FD 0xFFFF0000U
8438 /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
8439 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU
8441 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
8442 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU
8444 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U
8445 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U
8446 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U
8447 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U
8448 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U
8449 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U
8450 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U
8451 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U
8452 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U
8454 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U
8455 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U
8456 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U
8457 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U
8458 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U
8459 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U
8460 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U
8461 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U
8463 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
8464 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U
8465 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U
8467 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU
8468 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U
8469 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U
8470 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U
8471 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U
8472 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U
8473 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U
8474 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U
8475 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U
8476 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U
8477 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U
8479 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U
8480 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U
8481 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U
8482 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U
8483 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U
8484 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U
8485 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U
8486 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U
8487 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U
8488 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U
8489 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U
8491 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
8492 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU
8494 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
8495 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U
8496 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U
8498 /******************** Bit definition for USB_OTG_GCCFG register ********************/
8499 #define USB_OTG_GCCFG_PWRDWN 0x00010000U
8500 #define USB_OTG_GCCFG_VBDEN 0x00200000U
8502 /******************** Bit definition for USB_OTG_GPWRDN) register ********************/
8503 #define USB_OTG_GPWRDN_ADPMEN 0x00000001U
8504 #define USB_OTG_GPWRDN_ADPIF 0x00800000U
8506 /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
8507 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U
8508 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U
8510 /******************** Bit definition for USB_OTG_CID register ********************/
8511 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU
8513 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
8514 #define USB_OTG_GLPMCFG_LPMEN 0x00000001U
8515 #define USB_OTG_GLPMCFG_LPMACK 0x00000002U
8516 #define USB_OTG_GLPMCFG_BESL 0x0000003CU
8517 #define USB_OTG_GLPMCFG_REMWAKE 0x00000040U
8518 #define USB_OTG_GLPMCFG_L1SSEN 0x00000080U
8519 #define USB_OTG_GLPMCFG_BESLTHRS 0x00000F00U
8520 #define USB_OTG_GLPMCFG_L1DSEN 0x00001000U
8521 #define USB_OTG_GLPMCFG_LPMRSP 0x00006000U
8522 #define USB_OTG_GLPMCFG_SLPSTS 0x00008000U
8523 #define USB_OTG_GLPMCFG_L1RSMOK 0x00010000U
8524 #define USB_OTG_GLPMCFG_LPMCHIDX 0x001E0000U
8525 #define USB_OTG_GLPMCFG_LPMRCNT 0x00E00000U
8526 #define USB_OTG_GLPMCFG_SNDLPM 0x01000000U
8527 #define USB_OTG_GLPMCFG_LPMRCNTSTS 0x0E000000U
8528 #define USB_OTG_GLPMCFG_ENBESL 0x10000000U
8530 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
8531 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U
8532 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U
8533 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U
8534 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U
8535 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U
8536 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U
8537 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U
8538 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U
8539 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U
8541 /******************** Bit definition for USB_OTG_HPRT register ********************/
8542 #define USB_OTG_HPRT_PCSTS 0x00000001U
8543 #define USB_OTG_HPRT_PCDET 0x00000002U
8544 #define USB_OTG_HPRT_PENA 0x00000004U
8545 #define USB_OTG_HPRT_PENCHNG 0x00000008U
8546 #define USB_OTG_HPRT_POCA 0x00000010U
8547 #define USB_OTG_HPRT_POCCHNG 0x00000020U
8548 #define USB_OTG_HPRT_PRES 0x00000040U
8549 #define USB_OTG_HPRT_PSUSP 0x00000080U
8550 #define USB_OTG_HPRT_PRST 0x00000100U
8552 #define USB_OTG_HPRT_PLSTS 0x00000C00U
8553 #define USB_OTG_HPRT_PLSTS_0 0x00000400U
8554 #define USB_OTG_HPRT_PLSTS_1 0x00000800U
8555 #define USB_OTG_HPRT_PPWR 0x00001000U
8557 #define USB_OTG_HPRT_PTCTL 0x0001E000U
8558 #define USB_OTG_HPRT_PTCTL_0 0x00002000U
8559 #define USB_OTG_HPRT_PTCTL_1 0x00004000U
8560 #define USB_OTG_HPRT_PTCTL_2 0x00008000U
8561 #define USB_OTG_HPRT_PTCTL_3 0x00010000U
8563 #define USB_OTG_HPRT_PSPD 0x00060000U
8564 #define USB_OTG_HPRT_PSPD_0 0x00020000U
8565 #define USB_OTG_HPRT_PSPD_1 0x00040000U
8567 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
8568 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U
8569 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U
8570 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U
8571 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U
8572 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U
8573 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U
8574 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U
8575 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U
8576 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U
8577 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U
8578 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U
8580 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
8581 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU
8582 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U
8584 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
8585 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU
8586 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U
8587 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U
8588 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U
8590 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U
8591 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U
8592 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U
8593 #define USB_OTG_DIEPCTL_STALL 0x00200000U
8595 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U
8596 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U
8597 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U
8598 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U
8599 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U
8600 #define USB_OTG_DIEPCTL_CNAK 0x04000000U
8601 #define USB_OTG_DIEPCTL_SNAK 0x08000000U
8602 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U
8603 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U
8604 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U
8605 #define USB_OTG_DIEPCTL_EPENA 0x80000000U
8607 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
8608 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU
8610 #define USB_OTG_HCCHAR_EPNUM 0x00007800U
8611 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U
8612 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U
8613 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U
8614 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U
8615 #define USB_OTG_HCCHAR_EPDIR 0x00008000U
8616 #define USB_OTG_HCCHAR_LSDEV 0x00020000U
8618 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U
8619 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U
8620 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U
8622 #define USB_OTG_HCCHAR_MC 0x00300000U
8623 #define USB_OTG_HCCHAR_MC_0 0x00100000U
8624 #define USB_OTG_HCCHAR_MC_1 0x00200000U
8626 #define USB_OTG_HCCHAR_DAD 0x1FC00000U
8627 #define USB_OTG_HCCHAR_DAD_0 0x00400000U
8628 #define USB_OTG_HCCHAR_DAD_1 0x00800000U
8629 #define USB_OTG_HCCHAR_DAD_2 0x01000000U
8630 #define USB_OTG_HCCHAR_DAD_3 0x02000000U
8631 #define USB_OTG_HCCHAR_DAD_4 0x04000000U
8632 #define USB_OTG_HCCHAR_DAD_5 0x08000000U
8633 #define USB_OTG_HCCHAR_DAD_6 0x10000000U
8634 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U
8635 #define USB_OTG_HCCHAR_CHDIS 0x40000000U
8636 #define USB_OTG_HCCHAR_CHENA 0x80000000U
8638 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
8639 
8640 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU
8641 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U
8642 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U
8643 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U
8644 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U
8645 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U
8646 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U
8647 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U
8649 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U
8650 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U
8651 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U
8652 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U
8653 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U
8654 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U
8655 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U
8656 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U
8658 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U
8659 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U
8660 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U
8661 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U
8662 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U
8664 /******************** Bit definition for USB_OTG_HCINT register ********************/
8665 #define USB_OTG_HCINT_XFRC 0x00000001U
8666 #define USB_OTG_HCINT_CHH 0x00000002U
8667 #define USB_OTG_HCINT_AHBERR 0x00000004U
8668 #define USB_OTG_HCINT_STALL 0x00000008U
8669 #define USB_OTG_HCINT_NAK 0x00000010U
8670 #define USB_OTG_HCINT_ACK 0x00000020U
8671 #define USB_OTG_HCINT_NYET 0x00000040U
8672 #define USB_OTG_HCINT_TXERR 0x00000080U
8673 #define USB_OTG_HCINT_BBERR 0x00000100U
8674 #define USB_OTG_HCINT_FRMOR 0x00000200U
8675 #define USB_OTG_HCINT_DTERR 0x00000400U
8677 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
8678 #define USB_OTG_DIEPINT_XFRC 0x00000001U
8679 #define USB_OTG_DIEPINT_EPDISD 0x00000002U
8680 #define USB_OTG_DIEPINT_TOC 0x00000008U
8681 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U
8682 #define USB_OTG_DIEPINT_INEPNE 0x00000040U
8683 #define USB_OTG_DIEPINT_TXFE 0x00000080U
8684 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U
8685 #define USB_OTG_DIEPINT_BNA 0x00000200U
8686 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U
8687 #define USB_OTG_DIEPINT_BERR 0x00001000U
8688 #define USB_OTG_DIEPINT_NAK 0x00002000U
8690 /******************** Bit definition for USB_OTG_HCINTMSK register ********************/
8691 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U
8692 #define USB_OTG_HCINTMSK_CHHM 0x00000002U
8693 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U
8694 #define USB_OTG_HCINTMSK_STALLM 0x00000008U
8695 #define USB_OTG_HCINTMSK_NAKM 0x00000010U
8696 #define USB_OTG_HCINTMSK_ACKM 0x00000020U
8697 #define USB_OTG_HCINTMSK_NYET 0x00000040U
8698 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U
8699 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U
8700 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U
8701 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U
8703 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
8704 
8705 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU
8706 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U
8707 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U
8708 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
8709 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU
8710 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U
8711 #define USB_OTG_HCTSIZ_DOPING 0x80000000U
8712 #define USB_OTG_HCTSIZ_DPID 0x60000000U
8713 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U
8714 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U
8716 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
8717 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU
8719 /******************** Bit definition for USB_OTG_HCDMA register ********************/
8720 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU
8722 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
8723 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU
8725 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
8726 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU
8727 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U
8729 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
8730 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU
8731 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U
8732 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U
8733 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U
8734 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U
8735 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U
8736 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U
8737 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U
8738 #define USB_OTG_DOEPCTL_SNPM 0x00100000U
8739 #define USB_OTG_DOEPCTL_STALL 0x00200000U
8740 #define USB_OTG_DOEPCTL_CNAK 0x04000000U
8741 #define USB_OTG_DOEPCTL_SNAK 0x08000000U
8742 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U
8743 #define USB_OTG_DOEPCTL_EPENA 0x80000000U
8745 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
8746 #define USB_OTG_DOEPINT_XFRC 0x00000001U
8747 #define USB_OTG_DOEPINT_EPDISD 0x00000002U
8748 #define USB_OTG_DOEPINT_STUP 0x00000008U
8749 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U
8750 #define USB_OTG_DOEPINT_OTEPSPR 0x00000020U
8751 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U
8752 #define USB_OTG_DOEPINT_NYET 0x00004000U
8754 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
8755 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU
8756 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U
8758 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U
8759 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U
8760 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U
8762 /******************** Bit definition for PCGCCTL register ********************/
8763 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U
8764 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U
8765 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U
8781 /******************************* ADC Instances ********************************/
8782 #define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
8783  ((__INSTANCE__) == ADC2) || \
8784  ((__INSTANCE__) == ADC3))
8785 
8786 /******************************* CAN Instances ********************************/
8787 #define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
8788  ((__INSTANCE__) == CAN2))
8789 /******************************* CRC Instances ********************************/
8790 #define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
8791 
8792 /******************************* DAC Instances ********************************/
8793 #define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)
8794 
8795 /******************************* DCMI Instances *******************************/
8796 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
8797 
8798 
8799 /******************************* DMA2D Instances *******************************/
8800 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
8801 
8802 /******************************** DMA Instances *******************************/
8803 #define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
8804  ((__INSTANCE__) == DMA1_Stream1) || \
8805  ((__INSTANCE__) == DMA1_Stream2) || \
8806  ((__INSTANCE__) == DMA1_Stream3) || \
8807  ((__INSTANCE__) == DMA1_Stream4) || \
8808  ((__INSTANCE__) == DMA1_Stream5) || \
8809  ((__INSTANCE__) == DMA1_Stream6) || \
8810  ((__INSTANCE__) == DMA1_Stream7) || \
8811  ((__INSTANCE__) == DMA2_Stream0) || \
8812  ((__INSTANCE__) == DMA2_Stream1) || \
8813  ((__INSTANCE__) == DMA2_Stream2) || \
8814  ((__INSTANCE__) == DMA2_Stream3) || \
8815  ((__INSTANCE__) == DMA2_Stream4) || \
8816  ((__INSTANCE__) == DMA2_Stream5) || \
8817  ((__INSTANCE__) == DMA2_Stream6) || \
8818  ((__INSTANCE__) == DMA2_Stream7))
8819 
8820 /******************************* GPIO Instances *******************************/
8821 #define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
8822  ((__INSTANCE__) == GPIOB) || \
8823  ((__INSTANCE__) == GPIOC) || \
8824  ((__INSTANCE__) == GPIOD) || \
8825  ((__INSTANCE__) == GPIOE) || \
8826  ((__INSTANCE__) == GPIOF) || \
8827  ((__INSTANCE__) == GPIOG) || \
8828  ((__INSTANCE__) == GPIOH) || \
8829  ((__INSTANCE__) == GPIOI) || \
8830  ((__INSTANCE__) == GPIOJ) || \
8831  ((__INSTANCE__) == GPIOK))
8832 
8833 #define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
8834  ((__INSTANCE__) == GPIOB) || \
8835  ((__INSTANCE__) == GPIOC) || \
8836  ((__INSTANCE__) == GPIOD) || \
8837  ((__INSTANCE__) == GPIOE) || \
8838  ((__INSTANCE__) == GPIOF) || \
8839  ((__INSTANCE__) == GPIOG) || \
8840  ((__INSTANCE__) == GPIOH) || \
8841  ((__INSTANCE__) == GPIOI) || \
8842  ((__INSTANCE__) == GPIOJ) || \
8843  ((__INSTANCE__) == GPIOK))
8844 
8845 /****************************** CEC Instances *********************************/
8846 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
8847 
8848 /****************************** QSPI Instances *********************************/
8849 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
8850 
8851 
8852 /******************************** I2C Instances *******************************/
8853 #define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
8854  ((__INSTANCE__) == I2C2) || \
8855  ((__INSTANCE__) == I2C3) || \
8856  ((__INSTANCE__) == I2C4))
8857 
8858 /******************************** I2S Instances *******************************/
8859 #define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
8860  ((__INSTANCE__) == SPI2) || \
8861  ((__INSTANCE__) == SPI3))
8862 
8863 /******************************* LPTIM Instances ********************************/
8864 #define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
8865 
8866 
8867 
8868 
8869 /******************************* RNG Instances ********************************/
8870 #define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
8871 
8872 /****************************** RTC Instances *********************************/
8873 #define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)
8874 
8875 /******************************* SAI Instances ********************************/
8876 #define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
8877  ((__PERIPH__) == SAI1_Block_B) || \
8878  ((__PERIPH__) == SAI2_Block_A) || \
8879  ((__PERIPH__) == SAI2_Block_B))
8880 /* Legacy define */
8881 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
8882 
8883 /******************************** SDMMC Instances *******************************/
8884 #define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SDMMC1)
8885 
8886 /****************************** SPDIFRX Instances *********************************/
8887 #define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
8888 
8889 /******************************** SPI Instances *******************************/
8890 #define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
8891  ((__INSTANCE__) == SPI2) || \
8892  ((__INSTANCE__) == SPI3) || \
8893  ((__INSTANCE__) == SPI4) || \
8894  ((__INSTANCE__) == SPI5) || \
8895  ((__INSTANCE__) == SPI6))
8896 
8897 /****************** TIM Instances : All supported instances *******************/
8898 #define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
8899  ((__INSTANCE__) == TIM2) || \
8900  ((__INSTANCE__) == TIM3) || \
8901  ((__INSTANCE__) == TIM4) || \
8902  ((__INSTANCE__) == TIM5) || \
8903  ((__INSTANCE__) == TIM6) || \
8904  ((__INSTANCE__) == TIM7) || \
8905  ((__INSTANCE__) == TIM8) || \
8906  ((__INSTANCE__) == TIM9) || \
8907  ((__INSTANCE__) == TIM10) || \
8908  ((__INSTANCE__) == TIM11) || \
8909  ((__INSTANCE__) == TIM12) || \
8910  ((__INSTANCE__) == TIM13) || \
8911  ((__INSTANCE__) == TIM14))
8912 
8913 /************* TIM Instances : at least 1 capture/compare channel *************/
8914 #define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
8915  ((__INSTANCE__) == TIM2) || \
8916  ((__INSTANCE__) == TIM3) || \
8917  ((__INSTANCE__) == TIM4) || \
8918  ((__INSTANCE__) == TIM5) || \
8919  ((__INSTANCE__) == TIM8) || \
8920  ((__INSTANCE__) == TIM9) || \
8921  ((__INSTANCE__) == TIM10) || \
8922  ((__INSTANCE__) == TIM11) || \
8923  ((__INSTANCE__) == TIM12) || \
8924  ((__INSTANCE__) == TIM13) || \
8925  ((__INSTANCE__) == TIM14))
8926 
8927 /************ TIM Instances : at least 2 capture/compare channels *************/
8928 #define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
8929  ((__INSTANCE__) == TIM2) || \
8930  ((__INSTANCE__) == TIM3) || \
8931  ((__INSTANCE__) == TIM4) || \
8932  ((__INSTANCE__) == TIM5) || \
8933  ((__INSTANCE__) == TIM8) || \
8934  ((__INSTANCE__) == TIM9) || \
8935  ((__INSTANCE__) == TIM12))
8936 
8937 /************ TIM Instances : at least 3 capture/compare channels *************/
8938 #define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
8939  ((__INSTANCE__) == TIM2) || \
8940  ((__INSTANCE__) == TIM3) || \
8941  ((__INSTANCE__) == TIM4) || \
8942  ((__INSTANCE__) == TIM5) || \
8943  ((__INSTANCE__) == TIM8))
8944 
8945 /************ TIM Instances : at least 4 capture/compare channels *************/
8946 #define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
8947  ((__INSTANCE__) == TIM2) || \
8948  ((__INSTANCE__) == TIM3) || \
8949  ((__INSTANCE__) == TIM4) || \
8950  ((__INSTANCE__) == TIM5) || \
8951  ((__INSTANCE__) == TIM8))
8952 
8953 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
8954 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
8955  (((__INSTANCE__) == TIM1) || \
8956  ((__INSTANCE__) == TIM8))
8957 
8958 /****************** TIM Instances : supporting OCxREF clear *******************/
8959 #define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
8960  (((__INSTANCE__) == TIM1) || \
8961  ((__INSTANCE__) == TIM2) || \
8962  ((__INSTANCE__) == TIM3) || \
8963  ((__INSTANCE__) == TIM4) || \
8964  ((__INSTANCE__) == TIM8))
8965 
8966 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
8967 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
8968  (((__INSTANCE__) == TIM1) || \
8969  ((__INSTANCE__) == TIM2) || \
8970  ((__INSTANCE__) == TIM3) || \
8971  ((__INSTANCE__) == TIM4) || \
8972  ((__INSTANCE__) == TIM5) || \
8973  ((__INSTANCE__) == TIM8))
8974 
8975 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
8976 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
8977  (((__INSTANCE__) == TIM1) || \
8978  ((__INSTANCE__) == TIM2) || \
8979  ((__INSTANCE__) == TIM3) || \
8980  ((__INSTANCE__) == TIM4) || \
8981  ((__INSTANCE__) == TIM5) || \
8982  ((__INSTANCE__) == TIM8))
8983 /****************** TIM Instances : at least 5 capture/compare channels *******/
8984 #define IS_TIM_CC5_INSTANCE(__INSTANCE__)\
8985  (((__INSTANCE__) == TIM1) || \
8986  ((__INSTANCE__) == TIM8) )
8987 
8988 /****************** TIM Instances : at least 6 capture/compare channels *******/
8989 #define IS_TIM_CC6_INSTANCE(__INSTANCE__)\
8990  (((__INSTANCE__) == TIM1) || \
8991  ((__INSTANCE__) == TIM8))
8992 
8993 
8994 /******************** TIM Instances : Advanced-control timers *****************/
8995 #define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
8996  ((__INSTANCE__) == TIM8))
8997 
8998 /****************** TIM Instances : supporting 2 break inputs *****************/
8999 #define IS_TIM_BREAK_INSTANCE(__INSTANCE__)\
9000  (((__INSTANCE__) == TIM1) || \
9001  ((__INSTANCE__) == TIM8))
9002 
9003 /******************* TIM Instances : Timer input XOR function *****************/
9004 #define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9005  ((__INSTANCE__) == TIM2) || \
9006  ((__INSTANCE__) == TIM3) || \
9007  ((__INSTANCE__) == TIM4) || \
9008  ((__INSTANCE__) == TIM5) || \
9009  ((__INSTANCE__) == TIM8))
9010 
9011 /****************** TIM Instances : DMA requests generation (UDE) *************/
9012 #define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9013  ((__INSTANCE__) == TIM2) || \
9014  ((__INSTANCE__) == TIM3) || \
9015  ((__INSTANCE__) == TIM4) || \
9016  ((__INSTANCE__) == TIM5) || \
9017  ((__INSTANCE__) == TIM6) || \
9018  ((__INSTANCE__) == TIM7) || \
9019  ((__INSTANCE__) == TIM8))
9020 
9021 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
9022 #define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9023  ((__INSTANCE__) == TIM2) || \
9024  ((__INSTANCE__) == TIM3) || \
9025  ((__INSTANCE__) == TIM4) || \
9026  ((__INSTANCE__) == TIM5) || \
9027  ((__INSTANCE__) == TIM8))
9028 
9029 /************ TIM Instances : DMA requests generation (COMDE) *****************/
9030 #define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9031  ((__INSTANCE__) == TIM2) || \
9032  ((__INSTANCE__) == TIM3) || \
9033  ((__INSTANCE__) == TIM4) || \
9034  ((__INSTANCE__) == TIM5) || \
9035  ((__INSTANCE__) == TIM8))
9036 
9037 /******************** TIM Instances : DMA burst feature ***********************/
9038 #define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9039  ((__INSTANCE__) == TIM2) || \
9040  ((__INSTANCE__) == TIM3) || \
9041  ((__INSTANCE__) == TIM4) || \
9042  ((__INSTANCE__) == TIM5) || \
9043  ((__INSTANCE__) == TIM8))
9044 
9045 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
9046 #define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9047  ((__INSTANCE__) == TIM2) || \
9048  ((__INSTANCE__) == TIM3) || \
9049  ((__INSTANCE__) == TIM4) || \
9050  ((__INSTANCE__) == TIM5) || \
9051  ((__INSTANCE__) == TIM6) || \
9052  ((__INSTANCE__) == TIM7) || \
9053  ((__INSTANCE__) == TIM8) || \
9054  ((__INSTANCE__) == TIM13) || \
9055  ((__INSTANCE__) == TIM14))
9056 
9057 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
9058 #define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9059  ((__INSTANCE__) == TIM2) || \
9060  ((__INSTANCE__) == TIM3) || \
9061  ((__INSTANCE__) == TIM4) || \
9062  ((__INSTANCE__) == TIM5) || \
9063  ((__INSTANCE__) == TIM8) || \
9064  ((__INSTANCE__) == TIM9) || \
9065  ((__INSTANCE__) == TIM12))
9066 
9067 /********************** TIM Instances : 32 bit Counter ************************/
9068 #define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)(((__INSTANCE__) == TIM2) || \
9069  ((__INSTANCE__) == TIM5))
9070 
9071 /***************** TIM Instances : external trigger input available ************/
9072 #define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9073  ((__INSTANCE__) == TIM2) || \
9074  ((__INSTANCE__) == TIM3) || \
9075  ((__INSTANCE__) == TIM4) || \
9076  ((__INSTANCE__) == TIM5) || \
9077  ((__INSTANCE__) == TIM8))
9078 
9079 /****************** TIM Instances : remapping capability **********************/
9080 #define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
9081  ((__INSTANCE__) == TIM5) || \
9082  ((__INSTANCE__) == TIM11))
9083 
9084 /******************* TIM Instances : output(s) available **********************/
9085 #define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
9086  ((((__INSTANCE__) == TIM1) && \
9087  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9088  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9089  ((__CHANNEL__) == TIM_CHANNEL_3) || \
9090  ((__CHANNEL__) == TIM_CHANNEL_4))) \
9091  || \
9092  (((__INSTANCE__) == TIM2) && \
9093  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9094  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9095  ((__CHANNEL__) == TIM_CHANNEL_3) || \
9096  ((__CHANNEL__) == TIM_CHANNEL_4))) \
9097  || \
9098  (((__INSTANCE__) == TIM3) && \
9099  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9100  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9101  ((__CHANNEL__) == TIM_CHANNEL_3) || \
9102  ((__CHANNEL__) == TIM_CHANNEL_4))) \
9103  || \
9104  (((__INSTANCE__) == TIM4) && \
9105  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9106  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9107  ((__CHANNEL__) == TIM_CHANNEL_3) || \
9108  ((__CHANNEL__) == TIM_CHANNEL_4))) \
9109  || \
9110  (((__INSTANCE__) == TIM5) && \
9111  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9112  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9113  ((__CHANNEL__) == TIM_CHANNEL_3) || \
9114  ((__CHANNEL__) == TIM_CHANNEL_4))) \
9115  || \
9116  (((__INSTANCE__) == TIM8) && \
9117  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9118  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9119  ((__CHANNEL__) == TIM_CHANNEL_3) || \
9120  ((__CHANNEL__) == TIM_CHANNEL_4))) \
9121  || \
9122  (((__INSTANCE__) == TIM9) && \
9123  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9124  ((__CHANNEL__) == TIM_CHANNEL_2))) \
9125  || \
9126  (((__INSTANCE__) == TIM10) && \
9127  (((__CHANNEL__) == TIM_CHANNEL_1))) \
9128  || \
9129  (((__INSTANCE__) == TIM11) && \
9130  (((__CHANNEL__) == TIM_CHANNEL_1))) \
9131  || \
9132  (((__INSTANCE__) == TIM12) && \
9133  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9134  ((__CHANNEL__) == TIM_CHANNEL_2))) \
9135  || \
9136  (((__INSTANCE__) == TIM13) && \
9137  (((__CHANNEL__) == TIM_CHANNEL_1))) \
9138  || \
9139  (((__INSTANCE__) == TIM14) && \
9140  (((__CHANNEL__) == TIM_CHANNEL_1))))
9141 
9142 /************ TIM Instances : complementary output(s) available ***************/
9143 #define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
9144  ((((__INSTANCE__) == TIM1) && \
9145  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9146  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9147  ((__CHANNEL__) == TIM_CHANNEL_3))) \
9148  || \
9149  (((__INSTANCE__) == TIM8) && \
9150  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9151  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9152  ((__CHANNEL__) == TIM_CHANNEL_3))))
9153 
9154 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
9155 #define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
9156  (((__INSTANCE__) == TIM1) || \
9157  ((__INSTANCE__) == TIM8) )
9158 
9159 /****************** TIM Instances : supporting synchronization ****************/
9160 #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
9161  (((__INSTANCE__) == TIM1) || \
9162  ((__INSTANCE__) == TIM2) || \
9163  ((__INSTANCE__) == TIM3) || \
9164  ((__INSTANCE__) == TIM4) || \
9165  ((__INSTANCE__) == TIM5) || \
9166  ((__INSTANCE__) == TIM6) || \
9167  ((__INSTANCE__) == TIM7) || \
9168  ((__INSTANCE__) == TIM8))
9169 
9170 /******************** USART Instances : Synchronous mode **********************/
9171 #define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9172  ((__INSTANCE__) == USART2) || \
9173  ((__INSTANCE__) == USART3) || \
9174  ((__INSTANCE__) == USART6))
9175 
9176 /******************** UART Instances : Asynchronous mode **********************/
9177 #define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9178  ((__INSTANCE__) == USART2) || \
9179  ((__INSTANCE__) == USART3) || \
9180  ((__INSTANCE__) == UART4) || \
9181  ((__INSTANCE__) == UART5) || \
9182  ((__INSTANCE__) == USART6) || \
9183  ((__INSTANCE__) == UART7) || \
9184  ((__INSTANCE__) == UART8))
9185 
9186 /****************** UART Instances : Driver Enable *****************/
9187 #define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9188  ((__INSTANCE__) == USART2) || \
9189  ((__INSTANCE__) == USART3) || \
9190  ((__INSTANCE__) == UART4) || \
9191  ((__INSTANCE__) == UART5) || \
9192  ((__INSTANCE__) == USART6) || \
9193  ((__INSTANCE__) == UART7) || \
9194  ((__INSTANCE__) == UART8))
9195 
9196 /****************** UART Instances : Hardware Flow control ********************/
9197 #define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9198  ((__INSTANCE__) == USART2) || \
9199  ((__INSTANCE__) == USART3) || \
9200  ((__INSTANCE__) == UART4) || \
9201  ((__INSTANCE__) == UART5) || \
9202  ((__INSTANCE__) == USART6) || \
9203  ((__INSTANCE__) == UART7) || \
9204  ((__INSTANCE__) == UART8))
9205 
9206 /********************* UART Instances : Smart card mode ***********************/
9207 #define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9208  ((__INSTANCE__) == USART2) || \
9209  ((__INSTANCE__) == USART3) || \
9210  ((__INSTANCE__) == USART6))
9211 
9212 /*********************** UART Instances : IRDA mode ***************************/
9213 #define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9214  ((__INSTANCE__) == USART2) || \
9215  ((__INSTANCE__) == USART3) || \
9216  ((__INSTANCE__) == UART4) || \
9217  ((__INSTANCE__) == UART5) || \
9218  ((__INSTANCE__) == USART6) || \
9219  ((__INSTANCE__) == UART7) || \
9220  ((__INSTANCE__) == UART8))
9221 
9222 /****************************** IWDG Instances ********************************/
9223 #define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)
9224 
9225 /****************************** WWDG Instances ********************************/
9226 #define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)
9227 
9228 
9229 /******************************************************************************/
9230 /* For a painless codes migration between the STM32F7xx device product */
9231 /* lines, the aliases defined below are put in place to overcome the */
9232 /* differences in the interrupt handlers and IRQn definitions. */
9233 /* No need to update developed interrupt code when moving across */
9234 /* product lines within the same STM32F7 Family */
9235 /******************************************************************************/
9236 
9237 /* Aliases for __IRQn */
9238 #define HASH_RNG_IRQn RNG_IRQn
9239 
9240 /* Aliases for __IRQHandler */
9241 #define HASH_RNG_IRQHandler RNG_IRQHandler
9242 
9255 #ifdef __cplusplus
9256 }
9257 #endif /* __cplusplus */
9258 
9259 #endif /* __STM32F745xx_H */
9260 
9261 
9262 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
ETH_TypeDef::PTPTSLR
__IO uint32_t PTPTSLR
Definition: stm32f745xx.h:489
USART_TypeDef::GTPR
__IO uint32_t GTPR
Definition: stm32f745xx.h:934
SDMMC_TypeDef::DCTRL
__IO uint32_t DCTRL
Definition: stm32f745xx.h:826
SAI_Block_TypeDef::DR
__IO uint32_t DR
Definition: stm32f745xx.h:790
FMC_Bank3_TypeDef::SR
__IO uint32_t SR
Definition: stm32f745xx.h:571
QUADSPI_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32f745xx.h:865
SPI_TypeDef::I2SCFGR
__IO uint32_t I2SCFGR
Definition: stm32f745xx.h:850
RESERVED
#define RESERVED
Definition: usbh_cdc.h:68
CRC_TypeDef::INIT
__IO uint32_t INIT
Definition: stm32f745xx.h:328
USB_OTG_HostChannelTypeDef::HCSPLT
__IO uint32_t HCSPLT
Definition: stm32f745xx.h:1083
ADC_Common_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32f745xx.h:231
RTC_TypeDef::ALRMBR
__IO uint32_t ALRMBR
Definition: stm32f745xx.h:725
USB_OTG_INEndpointTypeDef::DIEPINT
__IO uint32_t DIEPINT
Definition: stm32f745xx.h:1039
SYSCFG_TypeDef::CMPCR
__IO uint32_t CMPCR
Definition: stm32f745xx.h:619
SPI_TypeDef::DR
__IO uint32_t DR
Definition: stm32f745xx.h:846
GPIO_TypeDef::IDR
__IO uint32_t IDR
Definition: stm32f745xx.h:602
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition: stm32f745xx.h:253
USB_OTG_GlobalTypeDef::GRSTCTL
__IO uint32_t GRSTCTL
Definition: stm32f745xx.h:980
DMA_TypeDef::LIFCR
__IO uint32_t LIFCR
Definition: stm32f745xx.h:404
SAI_Block_TypeDef::IMR
__IO uint32_t IMR
Definition: stm32f745xx.h:787
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f745xx.h:613
ADC_TypeDef::JOFR3
__IO uint32_t JOFR3
Definition: stm32f745xx.h:213
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f745xx.h:841
DAC_TypeDef::DHR8R2
__IO uint32_t DHR8R2
Definition: stm32f745xx.h:345
SAI_Block_TypeDef::SLOTR
__IO uint32_t SLOTR
Definition: stm32f745xx.h:786
SPI5_IRQn
Definition: stm32f745xx.h:163
DMA1_Stream2_IRQn
Definition: stm32f745xx.h:92
USB_OTG_DeviceTypeDef::DVBUSPULSE
__IO uint32_t DVBUSPULSE
Definition: stm32f745xx.h:1020
ETH_TypeDef::MMCRGUFCR
__IO uint32_t MMCRGUFCR
Definition: stm32f745xx.h:484
RCC_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32f745xx.h:701
CAN2_SCE_IRQn
Definition: stm32f745xx.h:145
ETH_TypeDef::MACA1LR
__IO uint32_t MACA1LR
Definition: stm32f745xx.h:464
GPIO_TypeDef::PUPDR
__IO uint32_t PUPDR
Definition: stm32f745xx.h:601
OTG_FS_WKUP_IRQn
Definition: stm32f745xx.h:121
QUADSPI_TypeDef::DLR
__IO uint32_t DLR
Definition: stm32f745xx.h:864
ADC_TypeDef::JSQR
__IO uint32_t JSQR
Definition: stm32f745xx.h:220
RTC_TypeDef::WUTR
__IO uint32_t WUTR
Definition: stm32f745xx.h:722
DAC_TypeDef::DHR12LD
__IO uint32_t DHR12LD
Definition: stm32f745xx.h:347
DAC_TypeDef::DHR12L2
__IO uint32_t DHR12L2
Definition: stm32f745xx.h:344
CAN_FilterRegister_TypeDef::FR2
__IO uint32_t FR2
Definition: stm32f745xx.h:268
RTC_TypeDef::SHIFTR
__IO uint32_t SHIFTR
Definition: stm32f745xx.h:728
USART_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32f745xx.h:938
I2C_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f745xx.h:634
SVCall_IRQn
Definition: stm32f745xx.h:74
ETH_TypeDef::MMCRIMR
__IO uint32_t MMCRIMR
Definition: stm32f745xx.h:473
I2C_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32f745xx.h:635
DMA2_Stream6_IRQn
Definition: stm32f745xx.h:148
OTG_HS_EP1_IN_IRQn
Definition: stm32f745xx.h:154
ADC_TypeDef::SQR2
__IO uint32_t SQR2
Definition: stm32f745xx.h:218
DMA2D_TypeDef::OOR
__IO uint32_t OOR
Definition: stm32f745xx.h:431
DMA2_Stream7_IRQn
Definition: stm32f745xx.h:149
EXTI4_IRQn
Definition: stm32f745xx.h:89
DMA_TypeDef::HIFCR
__IO uint32_t HIFCR
Definition: stm32f745xx.h:405
TIM4_IRQn
Definition: stm32f745xx.h:109
IWDG_TypeDef::RLR
__IO uint32_t RLR
Definition: stm32f745xx.h:649
ADC_TypeDef::JOFR4
__IO uint32_t JOFR4
Definition: stm32f745xx.h:214
ADC_Common_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32f745xx.h:230
DAC_TypeDef::DHR12RD
__IO uint32_t DHR12RD
Definition: stm32f745xx.h:346
QUADSPI_TypeDef::PSMKR
__IO uint32_t PSMKR
Definition: stm32f745xx.h:869
DMA2D_TypeDef::OPFCCR
__IO uint32_t OPFCCR
Definition: stm32f745xx.h:428
SDMMC_TypeDef::POWER
__IO uint32_t POWER
Definition: stm32f745xx.h:815
CAN_TypeDef::RF1R
__IO uint32_t RF1R
Definition: stm32f745xx.h:281
DMA2D_TypeDef::OCOLR
__IO uint32_t OCOLR
Definition: stm32f745xx.h:429
CAN_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32f745xx.h:293
ETH_TypeDef::DMARPDR
__IO uint32_t DMARPDR
Definition: stm32f745xx.h:500
LPTIM1_IRQn
Definition: stm32f745xx.h:169
ETH_TypeDef::MACA3LR
__IO uint32_t MACA3LR
Definition: stm32f745xx.h:468
SAI2_IRQn
Definition: stm32f745xx.h:167
ADC_IRQn
Definition: stm32f745xx.h:97
CAN1_SCE_IRQn
Definition: stm32f745xx.h:101
USB_OTG_OUTEndpointTypeDef::Reserved04
uint32_t Reserved04
Definition: stm32f745xx.h:1054
TIM_TypeDef::RCR
__IO uint32_t RCR
Definition: stm32f745xx.h:893
ETH_TypeDef::MACA0HR
__IO uint32_t MACA0HR
Definition: stm32f745xx.h:461
GPIO_TypeDef::OTYPER
__IO uint32_t OTYPER
Definition: stm32f745xx.h:599
WWDG_TypeDef::SR
__IO uint32_t SR
Definition: stm32f745xx.h:952
EXTI1_IRQn
Definition: stm32f745xx.h:86
USB_OTG_INEndpointTypeDef::DIEPTSIZ
__IO uint32_t DIEPTSIZ
Definition: stm32f745xx.h:1041
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f745xx.h:519
USB_OTG_HostChannelTypeDef::HCINTMSK
__IO uint32_t HCINTMSK
Definition: stm32f745xx.h:1085
DMA2_Stream1_IRQn
Definition: stm32f745xx.h:136
TIM_TypeDef::DMAR
__IO uint32_t DMAR
Definition: stm32f745xx.h:900
ETH_TypeDef::DMATPDR
__IO uint32_t DMATPDR
Definition: stm32f745xx.h:499
I2C4_EV_IRQn
Definition: stm32f745xx.h:171
EXTI15_10_IRQn
Definition: stm32f745xx.h:119
USB_OTG_DeviceTypeDef::DEACHINT
__IO uint32_t DEACHINT
Definition: stm32f745xx.h:1023
CRC_TypeDef::RESERVED1
uint16_t RESERVED1
Definition: stm32f745xx.h:325
SPI_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f745xx.h:843
RTC_TypeDef::BKP20R
__IO uint32_t BKP20R
Definition: stm32f745xx.h:757
SDMMC_TypeDef::DLEN
__IO uint32_t DLEN
Definition: stm32f745xx.h:825
ETH_TypeDef::PTPSSIR
__IO uint32_t PTPSSIR
Definition: stm32f745xx.h:487
CAN_TypeDef::FFA1R
__IO uint32_t FFA1R
Definition: stm32f745xx.h:294
USB_OTG_GlobalTypeDef::GPWRDN
__IO uint32_t GPWRDN
Definition: stm32f745xx.h:995
RNG_TypeDef::DR
__IO uint32_t DR
Definition: stm32f745xx.h:964
SDMMC_TypeDef::FIFO
__IO uint32_t FIFO
Definition: stm32f745xx.h:834
QUADSPI_TypeDef::ABR
__IO uint32_t ABR
Definition: stm32f745xx.h:867
DMA2D_TypeDef::FGPFCCR
__IO uint32_t FGPFCCR
Definition: stm32f745xx.h:422
FMC_Bank5_6_TypeDef::SDRTR
__IO uint32_t SDRTR
Definition: stm32f745xx.h:587
RCC_TypeDef::AHB1ENR
__IO uint32_t AHB1ENR
Definition: stm32f745xx.h:686
USB_OTG_GlobalTypeDef::GHWCFG3
__IO uint32_t GHWCFG3
Definition: stm32f745xx.h:992
SPDIFRX_TypeDef::IMR
__IO uint32_t IMR
Definition: stm32f745xx.h:800
DMA2D_TypeDef::BGMAR
__IO uint32_t BGMAR
Definition: stm32f745xx.h:420
SPDIFRX_TypeDef
SPDIF-RX Interface.
Definition: stm32f745xx.h:797
USB_OTG_DeviceTypeDef::DAINT
__IO uint32_t DAINT
Definition: stm32f745xx.h:1015
ETH_TypeDef::PTPTSCR
__IO uint32_t PTPTSCR
Definition: stm32f745xx.h:486
RTC_TypeDef::BKP7R
__IO uint32_t BKP7R
Definition: stm32f745xx.h:744
CEC_TypeDef
HDMI-CEC.
Definition: stm32f745xx.h:305
PWR_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f745xx.h:664
SPI4_IRQn
Definition: stm32f745xx.h:162
UART5_IRQn
Definition: stm32f745xx.h:132
SAI1_IRQn
Definition: stm32f745xx.h:165
TIM1_TRG_COM_TIM11_IRQn
Definition: stm32f745xx.h:105
QUADSPI_TypeDef::AR
__IO uint32_t AR
Definition: stm32f745xx.h:866
FMC_Bank3_TypeDef
Flexible Memory Controller Bank3.
Definition: stm32f745xx.h:568
LPTIM_TypeDef::CR
__IO uint32_t CR
Definition: stm32f745xx.h:917
TIM_TypeDef::CCR1
__IO uint32_t CCR1
Definition: stm32f745xx.h:894
I2C_TypeDef::TIMEOUTR
__IO uint32_t TIMEOUTR
Definition: stm32f745xx.h:633
ETH_TypeDef::MMCRIR
__IO uint32_t MMCRIR
Definition: stm32f745xx.h:471
DAC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f745xx.h:338
TIM_TypeDef::ARR
__IO uint32_t ARR
Definition: stm32f745xx.h:892
ETH_TypeDef::PTPTSHUR
__IO uint32_t PTPTSHUR
Definition: stm32f745xx.h:490
CRC_TypeDef
CRC calculation unit.
Definition: stm32f745xx.h:320
QUADSPI_TypeDef::DR
__IO uint32_t DR
Definition: stm32f745xx.h:868
RTC_TypeDef::BKP18R
__IO uint32_t BKP18R
Definition: stm32f745xx.h:755
LPTIM_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f745xx.h:913
DMA2D_TypeDef::FGMAR
__IO uint32_t FGMAR
Definition: stm32f745xx.h:418
DMA_Stream_TypeDef::NDTR
__IO uint32_t NDTR
Definition: stm32f745xx.h:393
USB_OTG_DeviceTypeDef::DIEPMSK
__IO uint32_t DIEPMSK
Definition: stm32f745xx.h:1013
SAI_TypeDef::GCR
__IO uint32_t GCR
Definition: stm32f745xx.h:778
USB_OTG_DeviceTypeDef::DIEPEMPMSK
__IO uint32_t DIEPEMPMSK
Definition: stm32f745xx.h:1022
EXTI9_5_IRQn
Definition: stm32f745xx.h:102
RCC_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32f745xx.h:682
DMA2D_TypeDef::IFCR
__IO uint32_t IFCR
Definition: stm32f745xx.h:417
RCC_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32f745xx.h:696
ETH_TypeDef::MMCTIMR
__IO uint32_t MMCTIMR
Definition: stm32f745xx.h:474
USART_TypeDef::TDR
__IO uint32_t TDR
Definition: stm32f745xx.h:940
RTC_TypeDef::TAMPCR
__IO uint32_t TAMPCR
Definition: stm32f745xx.h:733
EXTI_TypeDef::FTSR
__IO uint32_t FTSR
Definition: stm32f745xx.h:524
RTC_TypeDef::BKP14R
__IO uint32_t BKP14R
Definition: stm32f745xx.h:751
DCMI_TypeDef::RISR
__IO uint32_t RISR
Definition: stm32f745xx.h:375
RCC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32f745xx.h:689
FLASH_TypeDef::KEYR
__IO uint32_t KEYR
Definition: stm32f745xx.h:536
CAN_TypeDef::MSR
__IO uint32_t MSR
Definition: stm32f745xx.h:278
CAN1_RX1_IRQn
Definition: stm32f745xx.h:100
USB_OTG_OUTEndpointTypeDef::DOEPDMA
__IO uint32_t DOEPDMA
Definition: stm32f745xx.h:1058
RTC_TypeDef::ALRMBSSR
__IO uint32_t ALRMBSSR
Definition: stm32f745xx.h:735
DMA2D_TypeDef::BGCMAR
__IO uint32_t BGCMAR
Definition: stm32f745xx.h:427
CAN_TypeDef::ESR
__IO uint32_t ESR
Definition: stm32f745xx.h:283
SAI_Block_TypeDef::CLRFR
__IO uint32_t CLRFR
Definition: stm32f745xx.h:789
DMA2_Stream0_IRQn
Definition: stm32f745xx.h:135
RCC_TypeDef::BDCR
__IO uint32_t BDCR
Definition: stm32f745xx.h:700
USART_TypeDef::BRR
__IO uint32_t BRR
Definition: stm32f745xx.h:933
RCC_TypeDef::AHB1LPENR
__IO uint32_t AHB1LPENR
Definition: stm32f745xx.h:693
EXTI_TypeDef::IMR
__IO uint32_t IMR
Definition: stm32f745xx.h:521
CEC_IRQn
Definition: stm32f745xx.h:170
USB_OTG_INEndpointTypeDef
USB_OTG_IN_Endpoint-Specific_Register.
Definition: stm32f745xx.h:1035
TIM_TypeDef::CCR4
__IO uint32_t CCR4
Definition: stm32f745xx.h:897
SDMMC1_IRQn
Definition: stm32f745xx.h:128
RTC_TypeDef::BKP10R
__IO uint32_t BKP10R
Definition: stm32f745xx.h:747
LPTIM_TypeDef::CMP
__IO uint32_t CMP
Definition: stm32f745xx.h:918
RTC_TypeDef::BKP2R
__IO uint32_t BKP2R
Definition: stm32f745xx.h:739
LPTIM_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32f745xx.h:914
DCMI_TypeDef::CWSTRTR
__IO uint32_t CWSTRTR
Definition: stm32f745xx.h:381
DMA_TypeDef::LISR
__IO uint32_t LISR
Definition: stm32f745xx.h:402
SYSCFG_TypeDef::PMC
__IO uint32_t PMC
Definition: stm32f745xx.h:616
FMC_Bank3_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32f745xx.h:574
RCC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f745xx.h:675
RCC_TypeDef::APB1ENR
__IO uint32_t APB1ENR
Definition: stm32f745xx.h:690
I2C2_ER_IRQn
Definition: stm32f745xx.h:113
SAI_Block_TypeDef::FRCR
__IO uint32_t FRCR
Definition: stm32f745xx.h:785
DMA2_Stream4_IRQn
Definition: stm32f745xx.h:139
EXTI3_IRQn
Definition: stm32f745xx.h:88
ADC_TypeDef::JDR2
__IO uint32_t JDR2
Definition: stm32f745xx.h:222
CAN2_RX1_IRQn
Definition: stm32f745xx.h:144
FMC_Bank1E_TypeDef
Flexible Memory Controller Bank1E.
Definition: stm32f745xx.h:559
DMA_TypeDef
Definition: stm32f745xx.h:400
TAMP_STAMP_IRQn
Definition: stm32f745xx.h:81
USB_OTG_HostTypeDef::HPTXSTS
__IO uint32_t HPTXSTS
Definition: stm32f745xx.h:1072
DMA2D_TypeDef::FGOR
__IO uint32_t FGOR
Definition: stm32f745xx.h:419
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f745xx.h:948
DBGMCU_TypeDef::APB1FZ
__IO uint32_t APB1FZ
Definition: stm32f745xx.h:363
USB_OTG_GlobalTypeDef::GOTGCTL
__IO uint32_t GOTGCTL
Definition: stm32f745xx.h:976
QUADSPI_TypeDef::PSMAR
__IO uint32_t PSMAR
Definition: stm32f745xx.h:870
USB_OTG_GlobalTypeDef::GRXSTSP
__IO uint32_t GRXSTSP
Definition: stm32f745xx.h:984
USB_OTG_INEndpointTypeDef::Reserved18
uint32_t Reserved18
Definition: stm32f745xx.h:1044
DBGMCU_TypeDef::CR
__IO uint32_t CR
Definition: stm32f745xx.h:362
CRC_TypeDef::POL
__IO uint32_t POL
Definition: stm32f745xx.h:329
USB_OTG_DeviceTypeDef::DCFG
__IO uint32_t DCFG
Definition: stm32f745xx.h:1009
UART4_IRQn
Definition: stm32f745xx.h:131
RTC_TypeDef::PRER
__IO uint32_t PRER
Definition: stm32f745xx.h:721
DMA1_Stream6_IRQn
Definition: stm32f745xx.h:96
DMA_Stream_TypeDef::M1AR
__IO uint32_t M1AR
Definition: stm32f745xx.h:396
CAN_TypeDef::IER
__IO uint32_t IER
Definition: stm32f745xx.h:282
RTC_Alarm_IRQn
Definition: stm32f745xx.h:120
SPI_TypeDef::SR
__IO uint32_t SR
Definition: stm32f745xx.h:845
ETH_TypeDef::MMCRFAECR
__IO uint32_t MMCRFAECR
Definition: stm32f745xx.h:482
CAN_TypeDef::MCR
__IO uint32_t MCR
Definition: stm32f745xx.h:277
TIM_TypeDef::SMCR
__IO uint32_t SMCR
Definition: stm32f745xx.h:883
ADC_TypeDef::JDR1
__IO uint32_t JDR1
Definition: stm32f745xx.h:221
RTC_TypeDef::BKP17R
__IO uint32_t BKP17R
Definition: stm32f745xx.h:754
__I
#define __I
Definition: core_cm0.h:210
RTC_TypeDef::BKP8R
__IO uint32_t BKP8R
Definition: stm32f745xx.h:745
DAC_TypeDef::DHR12R2
__IO uint32_t DHR12R2
Definition: stm32f745xx.h:343
CRC_TypeDef::DR
__IO uint32_t DR
Definition: stm32f745xx.h:322
EXTI_TypeDef::PR
__IO uint32_t PR
Definition: stm32f745xx.h:526
DMA1_Stream5_IRQn
Definition: stm32f745xx.h:95
USB_OTG_DeviceTypeDef::Reserved40
uint32_t Reserved40
Definition: stm32f745xx.h:1025
CAN_FilterRegister_TypeDef::FR1
__IO uint32_t FR1
Definition: stm32f745xx.h:267
ETH_TypeDef::PTPTTLR
__IO uint32_t PTPTTLR
Definition: stm32f745xx.h:494
RCC_TypeDef::PLLSAICFGR
__IO uint32_t PLLSAICFGR
Definition: stm32f745xx.h:705
CRC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32f745xx.h:327
RTC_TypeDef::BKP19R
__IO uint32_t BKP19R
Definition: stm32f745xx.h:756
ETH_TypeDef::MACRWUFFR
__IO uint32_t MACRWUFFR
Definition: stm32f745xx.h:456
DAC_TypeDef::DHR12R1
__IO uint32_t DHR12R1
Definition: stm32f745xx.h:340
DMA2D_TypeDef::FGCMAR
__IO uint32_t FGCMAR
Definition: stm32f745xx.h:426
USB_OTG_HostChannelTypeDef::HCDMA
__IO uint32_t HCDMA
Definition: stm32f745xx.h:1087
SPI2_IRQn
Definition: stm32f745xx.h:115
USB_OTG_GlobalTypeDef::HNPTXSTS
__IO uint32_t HNPTXSTS
Definition: stm32f745xx.h:987
CRC_TypeDef::RESERVED0
uint8_t RESERVED0
Definition: stm32f745xx.h:324
USB_OTG_GlobalTypeDef::CID
__IO uint32_t CID
Definition: stm32f745xx.h:990
DMA2D_TypeDef::OMAR
__IO uint32_t OMAR
Definition: stm32f745xx.h:430
ETH_TypeDef::PTPTSHR
__IO uint32_t PTPTSHR
Definition: stm32f745xx.h:488
USART_TypeDef::RQR
__IO uint32_t RQR
Definition: stm32f745xx.h:936
USB_OTG_DeviceTypeDef::DOEPMSK
__IO uint32_t DOEPMSK
Definition: stm32f745xx.h:1014
USB_OTG_GlobalTypeDef::GLPMCFG
__IO uint32_t GLPMCFG
Definition: stm32f745xx.h:994
PWR_TypeDef::CSR2
__IO uint32_t CSR2
Definition: stm32f745xx.h:665
RTC_TypeDef::ALRMAR
__IO uint32_t ALRMAR
Definition: stm32f745xx.h:724
SYSCFG_TypeDef::MEMRMP
__IO uint32_t MEMRMP
Definition: stm32f745xx.h:615
DMA2D_TypeDef::NLR
__IO uint32_t NLR
Definition: stm32f745xx.h:432
RCC_TypeDef::DCKCFGR1
__IO uint32_t DCKCFGR1
Definition: stm32f745xx.h:706
USB_OTG_DeviceTypeDef::DVBUSDIS
__IO uint32_t DVBUSDIS
Definition: stm32f745xx.h:1019
USB_OTG_GlobalTypeDef
USB_OTG_Core_Registers.
Definition: stm32f745xx.h:974
DMA1_Stream1_IRQn
Definition: stm32f745xx.h:91
GPIO_TypeDef::LCKR
__IO uint32_t LCKR
Definition: stm32f745xx.h:605
RTC_TypeDef::BKP26R
__IO uint32_t BKP26R
Definition: stm32f745xx.h:763
RCC_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32f745xx.h:677
USB_OTG_INEndpointTypeDef::DIEPDMA
__IO uint32_t DIEPDMA
Definition: stm32f745xx.h:1042
ETH_TypeDef::MMCRFCECR
__IO uint32_t MMCRFCECR
Definition: stm32f745xx.h:481
SDMMC_TypeDef::DTIMER
__IO uint32_t DTIMER
Definition: stm32f745xx.h:824
USB_OTG_GlobalTypeDef::GDFIFOCFG
__IO uint32_t GDFIFOCFG
Definition: stm32f745xx.h:996
USB_OTG_DeviceTypeDef::DSTS
__IO uint32_t DSTS
Definition: stm32f745xx.h:1011
RCC_TypeDef::APB2RSTR
__IO uint32_t APB2RSTR
Definition: stm32f745xx.h:684
SDMMC_TypeDef::FIFOCNT
__I uint32_t FIFOCNT
Definition: stm32f745xx.h:832
SDMMC_TypeDef::RESP2
__I uint32_t RESP2
Definition: stm32f745xx.h:821
SAI_Block_TypeDef::SR
__IO uint32_t SR
Definition: stm32f745xx.h:788
ETH_TypeDef::MACA2LR
__IO uint32_t MACA2LR
Definition: stm32f745xx.h:466
DMA_TypeDef::HISR
__IO uint32_t HISR
Definition: stm32f745xx.h:403
RTC_TypeDef::BKP23R
__IO uint32_t BKP23R
Definition: stm32f745xx.h:760
FMC_Bank5_6_TypeDef::SDSR
__IO uint32_t SDSR
Definition: stm32f745xx.h:588
WWDG_TypeDef::CR
__IO uint32_t CR
Definition: stm32f745xx.h:950
USB_OTG_DeviceTypeDef::DEACHMSK
__IO uint32_t DEACHMSK
Definition: stm32f745xx.h:1024
ADC_Common_TypeDef::CDR
__IO uint32_t CDR
Definition: stm32f745xx.h:232
RTC_TypeDef::BKP31R
__IO uint32_t BKP31R
Definition: stm32f745xx.h:768
RTC_TypeDef::BKP3R
__IO uint32_t BKP3R
Definition: stm32f745xx.h:740
RTC_TypeDef::BKP21R
__IO uint32_t BKP21R
Definition: stm32f745xx.h:758
RTC_TypeDef::BKP4R
__IO uint32_t BKP4R
Definition: stm32f745xx.h:741
PWR_TypeDef::CSR1
__IO uint32_t CSR1
Definition: stm32f745xx.h:663
RTC_TypeDef::reserved
uint32_t reserved
Definition: stm32f745xx.h:723
ETH_TypeDef::MACSR
__IO uint32_t MACSR
Definition: stm32f745xx.h:459
DCMI_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32f745xx.h:378
PendSV_IRQn
Definition: stm32f745xx.h:76
UART7_IRQn
Definition: stm32f745xx.h:160
CAN_TxMailBox_TypeDef::TDHR
__IO uint32_t TDHR
Definition: stm32f745xx.h:246
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f745xx.h:596
DMA2D_TypeDef::BGOR
__IO uint32_t BGOR
Definition: stm32f745xx.h:421
ADC_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f745xx.h:208
BusFault_IRQn
Definition: stm32f745xx.h:72
CAN_TypeDef::FS1R
__IO uint32_t FS1R
Definition: stm32f745xx.h:292
TIM_TypeDef::BDTR
__IO uint32_t BDTR
Definition: stm32f745xx.h:898
DCMI_TypeDef::MISR
__IO uint32_t MISR
Definition: stm32f745xx.h:377
I2C2_EV_IRQn
Definition: stm32f745xx.h:112
RNG_TypeDef::CR
__IO uint32_t CR
Definition: stm32f745xx.h:962
USB_OTG_HostChannelTypeDef::HCTSIZ
__IO uint32_t HCTSIZ
Definition: stm32f745xx.h:1086
ETH_TypeDef::MACHTHR
__IO uint32_t MACHTHR
Definition: stm32f745xx.h:449
TIM8_TRG_COM_TIM14_IRQn
Definition: stm32f745xx.h:124
RTC_TypeDef::TSSSR
__IO uint32_t TSSSR
Definition: stm32f745xx.h:731
QUADSPI_TypeDef
QUAD Serial Peripheral Interface.
Definition: stm32f745xx.h:858
USB_OTG_HostTypeDef::HFIR
__IO uint32_t HFIR
Definition: stm32f745xx.h:1069
SDMMC_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32f745xx.h:829
RCC_TypeDef::AHB2LPENR
__IO uint32_t AHB2LPENR
Definition: stm32f745xx.h:694
DMA_Stream_TypeDef::M0AR
__IO uint32_t M0AR
Definition: stm32f745xx.h:395
CAN_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32f745xx.h:295
DCMI_TypeDef::SR
__IO uint32_t SR
Definition: stm32f745xx.h:374
USB_OTG_GlobalTypeDef::GINTSTS
__IO uint32_t GINTSTS
Definition: stm32f745xx.h:981
QUADSPI_TypeDef::FCR
__IO uint32_t FCR
Definition: stm32f745xx.h:863
DBGMCU_TypeDef::IDCODE
__IO uint32_t IDCODE
Definition: stm32f745xx.h:361
CAN2_TX_IRQn
Definition: stm32f745xx.h:142
TIM_TypeDef::CNT
__IO uint32_t CNT
Definition: stm32f745xx.h:890
FMC_Bank5_6_TypeDef::SDCMR
__IO uint32_t SDCMR
Definition: stm32f745xx.h:586
RTC_TypeDef::BKP11R
__IO uint32_t BKP11R
Definition: stm32f745xx.h:748
TIM_TypeDef::CCR5
__IO uint32_t CCR5
Definition: stm32f745xx.h:903
ETH_TypeDef::DMAMFBOCR
__IO uint32_t DMAMFBOCR
Definition: stm32f745xx.h:506
I2C1_EV_IRQn
Definition: stm32f745xx.h:110
CAN_TypeDef
Controller Area Network.
Definition: stm32f745xx.h:275
RTC_TypeDef::BKP13R
__IO uint32_t BKP13R
Definition: stm32f745xx.h:750
LPTIM_TypeDef
LPTIMIMER.
Definition: stm32f745xx.h:911
FMC_IRQn
Definition: stm32f745xx.h:127
USB_OTG_OUTEndpointTypeDef::DOEPCTL
__IO uint32_t DOEPCTL
Definition: stm32f745xx.h:1053
ETH_TypeDef::MACPMTCSR
__IO uint32_t MACPMTCSR
Definition: stm32f745xx.h:457
RTC_TypeDef::TSDR
__IO uint32_t TSDR
Definition: stm32f745xx.h:730
DCMI_IRQn
Definition: stm32f745xx.h:157
TIM7_IRQn
Definition: stm32f745xx.h:134
USB_OTG_DeviceTypeDef::Reserved0C
uint32_t Reserved0C
Definition: stm32f745xx.h:1012
SDMMC_TypeDef::RESPCMD
__I uint32_t RESPCMD
Definition: stm32f745xx.h:819
I2C_TypeDef::TXDR
__IO uint32_t TXDR
Definition: stm32f745xx.h:638
DMA2D_TypeDef
DMA2D Controller.
Definition: stm32f745xx.h:413
RCC_IRQn
Definition: stm32f745xx.h:84
USB_OTG_GlobalTypeDef::GCCFG
__IO uint32_t GCCFG
Definition: stm32f745xx.h:989
I2C3_EV_IRQn
Definition: stm32f745xx.h:151
ETH_TypeDef::DMAIER
__IO uint32_t DMAIER
Definition: stm32f745xx.h:505
RCC_TypeDef::AHB2RSTR
__IO uint32_t AHB2RSTR
Definition: stm32f745xx.h:680
ETH_TypeDef::MACVLANTR
__IO uint32_t MACVLANTR
Definition: stm32f745xx.h:454
__IO
#define __IO
Definition: core_cm0.h:213
ETH_TypeDef::DMABMR
__IO uint32_t DMABMR
Definition: stm32f745xx.h:498
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32f745xx.h:204
I2C_TypeDef::OAR1
__IO uint32_t OAR1
Definition: stm32f745xx.h:630
FLASH_TypeDef::SR
__IO uint32_t SR
Definition: stm32f745xx.h:538
LPTIM_TypeDef::CNT
__IO uint32_t CNT
Definition: stm32f745xx.h:920
ETH_TypeDef::MACA0LR
__IO uint32_t MACA0LR
Definition: stm32f745xx.h:462
SysTick_IRQn
Definition: stm32f745xx.h:77
DAC_TypeDef::DOR2
__IO uint32_t DOR2
Definition: stm32f745xx.h:350
USB_OTG_DeviceTypeDef::Reserved9
uint32_t Reserved9
Definition: stm32f745xx.h:1018
USB_OTG_HostTypeDef::HCFG
__IO uint32_t HCFG
Definition: stm32f745xx.h:1068
IWDG_TypeDef::WINR
__IO uint32_t WINR
Definition: stm32f745xx.h:651
GPIO_TypeDef::MODER
__IO uint32_t MODER
Definition: stm32f745xx.h:598
TIM_TypeDef::CCMR3
__IO uint32_t CCMR3
Definition: stm32f745xx.h:902
SAI_TypeDef
Serial Audio Interface.
Definition: stm32f745xx.h:776
TIM_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f745xx.h:882
TIM_TypeDef::SR
__IO uint32_t SR
Definition: stm32f745xx.h:885
DMA1_Stream0_IRQn
Definition: stm32f745xx.h:90
USB_OTG_HostTypeDef::HFNUM
__IO uint32_t HFNUM
Definition: stm32f745xx.h:1070
RTC_TypeDef::BKP6R
__IO uint32_t BKP6R
Definition: stm32f745xx.h:743
ETH_TypeDef::DMARSWTR
__IO uint32_t DMARSWTR
Definition: stm32f745xx.h:507
CEC_TypeDef::RXDR
__IO uint32_t RXDR
Definition: stm32f745xx.h:310
TIM_TypeDef::CCMR1
__IO uint32_t CCMR1
Definition: stm32f745xx.h:887
FLASH_TypeDef::CR
__IO uint32_t CR
Definition: stm32f745xx.h:539
ETH_TypeDef::MMCTGFCR
__IO uint32_t MMCTGFCR
Definition: stm32f745xx.h:479
ETH_TypeDef::MACCR
__IO uint32_t MACCR
Definition: stm32f745xx.h:447
USB_OTG_HostTypeDef
USB_OTG_Host_Mode_Register_Structures.
Definition: stm32f745xx.h:1066
USB_OTG_DeviceTypeDef::DTHRCTL
__IO uint32_t DTHRCTL
Definition: stm32f745xx.h:1021
IRQn_Type
IRQn_Type
STM32F7xx Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f745xx.h:67
ETH_TypeDef::MMCTIR
__IO uint32_t MMCTIR
Definition: stm32f745xx.h:472
SDMMC_TypeDef::CMD
__IO uint32_t CMD
Definition: stm32f745xx.h:818
QUADSPI_IRQn
Definition: stm32f745xx.h:168
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition: stm32f745xx.h:241
ETH_TypeDef
Ethernet MAC.
Definition: stm32f745xx.h:445
ADC_TypeDef::JDR4
__IO uint32_t JDR4
Definition: stm32f745xx.h:224
TIM2_IRQn
Definition: stm32f745xx.h:107
USART_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f745xx.h:930
RCC_TypeDef::APB2ENR
__IO uint32_t APB2ENR
Definition: stm32f745xx.h:691
SPI3_IRQn
Definition: stm32f745xx.h:130
ETH_TypeDef::MACMIIAR
__IO uint32_t MACMIIAR
Definition: stm32f745xx.h:451
ETH_TypeDef::DMASR
__IO uint32_t DMASR
Definition: stm32f745xx.h:503
TIM_TypeDef::CCER
__IO uint32_t CCER
Definition: stm32f745xx.h:889
USB_OTG_GlobalTypeDef::GINTMSK
__IO uint32_t GINTMSK
Definition: stm32f745xx.h:982
QUADSPI_TypeDef::SR
__IO uint32_t SR
Definition: stm32f745xx.h:862
DCMI_TypeDef::CWSIZER
__IO uint32_t CWSIZER
Definition: stm32f745xx.h:382
ETH_TypeDef::MMCTGFSCCR
__IO uint32_t MMCTGFSCCR
Definition: stm32f745xx.h:476
SAI_Block_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f745xx.h:783
DAC_TypeDef::DHR8R1
__IO uint32_t DHR8R1
Definition: stm32f745xx.h:342
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f745xx.h:928
RTC_TypeDef::BKP24R
__IO uint32_t BKP24R
Definition: stm32f745xx.h:761
DMA2D_TypeDef::CR
__IO uint32_t CR
Definition: stm32f745xx.h:415
FMC_Bank3_TypeDef::ECCR
__IO uint32_t ECCR
Definition: stm32f745xx.h:575
TIM_TypeDef
TIM.
Definition: stm32f745xx.h:879
DMA_Stream_TypeDef::PAR
__IO uint32_t PAR
Definition: stm32f745xx.h:394
SAI_Block_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f745xx.h:784
DMA1_Stream7_IRQn
Definition: stm32f745xx.h:126
DMA2_Stream5_IRQn
Definition: stm32f745xx.h:147
USART1_IRQn
Definition: stm32f745xx.h:116
USB_OTG_GlobalTypeDef::HPTXFSIZ
__IO uint32_t HPTXFSIZ
Definition: stm32f745xx.h:999
GPIO_TypeDef::BSRR
__IO uint32_t BSRR
Definition: stm32f745xx.h:604
LPTIM_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32f745xx.h:916
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f745xx.h:390
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32f745xx.h:336
USB_OTG_HostChannelTypeDef
USB_OTG_Host_Channel_Specific_Registers.
Definition: stm32f745xx.h:1080
DCMI_TypeDef::DR
__IO uint32_t DR
Definition: stm32f745xx.h:383
OTG_HS_WKUP_IRQn
Definition: stm32f745xx.h:155
RTC_TypeDef::BKP29R
__IO uint32_t BKP29R
Definition: stm32f745xx.h:766
I2C4_ER_IRQn
Definition: stm32f745xx.h:172
RTC_TypeDef::BKP0R
__IO uint32_t BKP0R
Definition: stm32f745xx.h:737
FLASH_TypeDef
FLASH Registers.
Definition: stm32f745xx.h:533
I2C_TypeDef::PECR
__IO uint32_t PECR
Definition: stm32f745xx.h:636
ETH_TypeDef::DMACHRBAR
__IO uint32_t DMACHRBAR
Definition: stm32f745xx.h:512
RTC_TypeDef::TR
__IO uint32_t TR
Definition: stm32f745xx.h:717
CAN_TxMailBox_TypeDef::TDTR
__IO uint32_t TDTR
Definition: stm32f745xx.h:244
USB_OTG_HostTypeDef::HAINTMSK
__IO uint32_t HAINTMSK
Definition: stm32f745xx.h:1074
ETH_TypeDef::MMCCR
__IO uint32_t MMCCR
Definition: stm32f745xx.h:470
DCMI_TypeDef::IER
__IO uint32_t IER
Definition: stm32f745xx.h:376
DMA2_Stream2_IRQn
Definition: stm32f745xx.h:137
DCMI_TypeDef::CR
__IO uint32_t CR
Definition: stm32f745xx.h:373
LPTIM_TypeDef::IER
__IO uint32_t IER
Definition: stm32f745xx.h:915
PWR_TypeDef
Power Control.
Definition: stm32f745xx.h:660
USB_OTG_GlobalTypeDef::GADPCTL
__IO uint32_t GADPCTL
Definition: stm32f745xx.h:997
ETH_TypeDef::PTPTSAR
__IO uint32_t PTPTSAR
Definition: stm32f745xx.h:492
PVD_IRQn
Definition: stm32f745xx.h:80
RCC_TypeDef::AHB1RSTR
__IO uint32_t AHB1RSTR
Definition: stm32f745xx.h:679
ETH_IRQn
Definition: stm32f745xx.h:140
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f745xx.h:645
RCC_TypeDef::APB1RSTR
__IO uint32_t APB1RSTR
Definition: stm32f745xx.h:683
WWDG_TypeDef::CFR
__IO uint32_t CFR
Definition: stm32f745xx.h:951
ADC_TypeDef::JOFR1
__IO uint32_t JOFR1
Definition: stm32f745xx.h:211
FPU_IRQn
Definition: stm32f745xx.h:159
SPI_TypeDef::TXCRCR
__IO uint32_t TXCRCR
Definition: stm32f745xx.h:849
CAN_FIFOMailBox_TypeDef::RDLR
__IO uint32_t RDLR
Definition: stm32f745xx.h:257
RTC_TypeDef::BKP9R
__IO uint32_t BKP9R
Definition: stm32f745xx.h:746
OTG_HS_EP1_OUT_IRQn
Definition: stm32f745xx.h:153
DMA2D_TypeDef::BGPFCCR
__IO uint32_t BGPFCCR
Definition: stm32f745xx.h:424
SDMMC_TypeDef::MASK
__IO uint32_t MASK
Definition: stm32f745xx.h:830
DCMI_TypeDef::ESCR
__IO uint32_t ESCR
Definition: stm32f745xx.h:379
SPDIFRX_TypeDef::CR
__IO uint32_t CR
Definition: stm32f745xx.h:799
USB_OTG_DeviceTypeDef::DCTL
__IO uint32_t DCTL
Definition: stm32f745xx.h:1010
ADC_Common_TypeDef
Definition: stm32f745xx.h:228
DMA1_Stream3_IRQn
Definition: stm32f745xx.h:93
RTC_WKUP_IRQn
Definition: stm32f745xx.h:82
ETH_TypeDef::RESERVED8
__IO uint32_t RESERVED8
Definition: stm32f745xx.h:495
SDMMC_TypeDef::RESP4
__I uint32_t RESP4
Definition: stm32f745xx.h:823
CRC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f745xx.h:326
RTC_TypeDef::TSTR
__IO uint32_t TSTR
Definition: stm32f745xx.h:729
CAN_TypeDef::FM1R
__IO uint32_t FM1R
Definition: stm32f745xx.h:290
DMA_Stream_TypeDef::CR
__IO uint32_t CR
Definition: stm32f745xx.h:392
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f745xx.h:673
ADC_TypeDef::LTR
__IO uint32_t LTR
Definition: stm32f745xx.h:216
QUADSPI_TypeDef::DCR
__IO uint32_t DCR
Definition: stm32f745xx.h:861
WWDG_IRQn
Definition: stm32f745xx.h:79
SPDIFRX_TypeDef::IFCR
__IO uint32_t IFCR
Definition: stm32f745xx.h:802
CAN2_RX0_IRQn
Definition: stm32f745xx.h:143
IWDG_TypeDef::SR
__IO uint32_t SR
Definition: stm32f745xx.h:650
RTC_TypeDef::SSR
__IO uint32_t SSR
Definition: stm32f745xx.h:727
CEC_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f745xx.h:311
TIM8_BRK_TIM12_IRQn
Definition: stm32f745xx.h:122
ETH_TypeDef::MACA2HR
__IO uint32_t MACA2HR
Definition: stm32f745xx.h:465
I2C_TypeDef::TIMINGR
__IO uint32_t TIMINGR
Definition: stm32f745xx.h:632
ETH_TypeDef::MACA3HR
__IO uint32_t MACA3HR
Definition: stm32f745xx.h:467
DMA2D_IRQn
Definition: stm32f745xx.h:166
I2C3_ER_IRQn
Definition: stm32f745xx.h:152
RTC_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f745xx.h:720
ADC_TypeDef::JOFR2
__IO uint32_t JOFR2
Definition: stm32f745xx.h:212
CAN_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32f745xx.h:291
CAN_TypeDef::RF0R
__IO uint32_t RF0R
Definition: stm32f745xx.h:280
ADC_TypeDef::HTR
__IO uint32_t HTR
Definition: stm32f745xx.h:215
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition: stm32f745xx.h:265
RCC_TypeDef::SSCGR
__IO uint32_t SSCGR
Definition: stm32f745xx.h:703
CAN_TypeDef::BTR
__IO uint32_t BTR
Definition: stm32f745xx.h:284
CAN1_TX_IRQn
Definition: stm32f745xx.h:98
CEC_TypeDef::TXDR
__IO uint32_t TXDR
Definition: stm32f745xx.h:309
CAN_FIFOMailBox_TypeDef::RDHR
__IO uint32_t RDHR
Definition: stm32f745xx.h:258
RTC_TypeDef::BKP12R
__IO uint32_t BKP12R
Definition: stm32f745xx.h:749
RTC_TypeDef::BKP15R
__IO uint32_t BKP15R
Definition: stm32f745xx.h:752
DebugMonitor_IRQn
Definition: stm32f745xx.h:75
DMA2D_TypeDef::AMTCR
__IO uint32_t AMTCR
Definition: stm32f745xx.h:434
CAN_TxMailBox_TypeDef::TDLR
__IO uint32_t TDLR
Definition: stm32f745xx.h:245
USB_OTG_GlobalTypeDef::Reserved6
uint32_t Reserved6
Definition: stm32f745xx.h:993
ETH_TypeDef::DMARDLAR
__IO uint32_t DMARDLAR
Definition: stm32f745xx.h:501
TIM_TypeDef::CCR3
__IO uint32_t CCR3
Definition: stm32f745xx.h:896
FMC_Bank1_TypeDef
Flexible Memory Controller.
Definition: stm32f745xx.h:550
USART_TypeDef::RTOR
__IO uint32_t RTOR
Definition: stm32f745xx.h:935
USB_OTG_HostChannelTypeDef::HCCHAR
__IO uint32_t HCCHAR
Definition: stm32f745xx.h:1082
DMA1_Stream4_IRQn
Definition: stm32f745xx.h:94
TIM6_DAC_IRQn
Definition: stm32f745xx.h:133
RCC_TypeDef::APB2LPENR
__IO uint32_t APB2LPENR
Definition: stm32f745xx.h:698
SPDIFRX_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32f745xx.h:804
SPDIF_RX_IRQn
Definition: stm32f745xx.h:173
RCC_TypeDef::PLLI2SCFGR
__IO uint32_t PLLI2SCFGR
Definition: stm32f745xx.h:704
CAN_FIFOMailBox_TypeDef::RIR
__IO uint32_t RIR
Definition: stm32f745xx.h:255
RTC_TypeDef
Real-Time Clock.
Definition: stm32f745xx.h:715
ETH_WKUP_IRQn
Definition: stm32f745xx.h:141
ETH_TypeDef::DMACHTBAR
__IO uint32_t DMACHTBAR
Definition: stm32f745xx.h:511
TIM_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f745xx.h:881
DCMI_TypeDef
DCMI.
Definition: stm32f745xx.h:371
I2C1_ER_IRQn
Definition: stm32f745xx.h:111
ETH_TypeDef::MACMIIDR
__IO uint32_t MACMIIDR
Definition: stm32f745xx.h:452
GPIO_TypeDef::OSPEEDR
__IO uint32_t OSPEEDR
Definition: stm32f745xx.h:600
DMA2D_TypeDef::LWR
__IO uint32_t LWR
Definition: stm32f745xx.h:433
FMC_Bank5_6_TypeDef
Flexible Memory Controller Bank5_6.
Definition: stm32f745xx.h:582
CEC_TypeDef::IER
__IO uint32_t IER
Definition: stm32f745xx.h:312
TIM_TypeDef::PSC
__IO uint32_t PSC
Definition: stm32f745xx.h:891
OTG_HS_IRQn
Definition: stm32f745xx.h:156
SDMMC_TypeDef::ARG
__IO uint32_t ARG
Definition: stm32f745xx.h:817
DAC_TypeDef::DHR12L1
__IO uint32_t DHR12L1
Definition: stm32f745xx.h:341
TIM1_CC_IRQn
Definition: stm32f745xx.h:106
RTC_TypeDef::BKP22R
__IO uint32_t BKP22R
Definition: stm32f745xx.h:759
ETH_TypeDef::MACHTLR
__IO uint32_t MACHTLR
Definition: stm32f745xx.h:450
RNG_IRQn
Definition: stm32f745xx.h:158
RCC_TypeDef::CIR
__IO uint32_t CIR
Definition: stm32f745xx.h:678
DMA2D_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f745xx.h:416
FMC_Bank3_TypeDef::PATT
__IO uint32_t PATT
Definition: stm32f745xx.h:573
EXTI_TypeDef::RTSR
__IO uint32_t RTSR
Definition: stm32f745xx.h:523
RTC_TypeDef::BKP28R
__IO uint32_t BKP28R
Definition: stm32f745xx.h:765
FMC_Bank3_TypeDef::PCR
__IO uint32_t PCR
Definition: stm32f745xx.h:570
QUADSPI_TypeDef::CR
__IO uint32_t CR
Definition: stm32f745xx.h:860
FLASH_IRQn
Definition: stm32f745xx.h:83
USB_OTG_INEndpointTypeDef::Reserved04
uint32_t Reserved04
Definition: stm32f745xx.h:1038
DMA2_Stream3_IRQn
Definition: stm32f745xx.h:138
SPI_TypeDef::RXCRCR
__IO uint32_t RXCRCR
Definition: stm32f745xx.h:848
USART_TypeDef::RDR
__IO uint32_t RDR
Definition: stm32f745xx.h:939
CAN_TxMailBox_TypeDef::TIR
__IO uint32_t TIR
Definition: stm32f745xx.h:243
CAN_TypeDef::FA1R
__IO uint32_t FA1R
Definition: stm32f745xx.h:296
SDMMC_TypeDef::DCOUNT
__I uint32_t DCOUNT
Definition: stm32f745xx.h:827
RTC_TypeDef::BKP1R
__IO uint32_t BKP1R
Definition: stm32f745xx.h:738
RTC_TypeDef::WPR
__IO uint32_t WPR
Definition: stm32f745xx.h:726
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f745xx.h:626
TIM8_UP_TIM13_IRQn
Definition: stm32f745xx.h:123
TIM_TypeDef::CCR2
__IO uint32_t CCR2
Definition: stm32f745xx.h:895
RTC_TypeDef::DR
__IO uint32_t DR
Definition: stm32f745xx.h:718
ETH_TypeDef::MACIMR
__IO uint32_t MACIMR
Definition: stm32f745xx.h:460
I2C_TypeDef::RXDR
__IO uint32_t RXDR
Definition: stm32f745xx.h:637
RTC_TypeDef::ALRMASSR
__IO uint32_t ALRMASSR
Definition: stm32f745xx.h:734
ADC_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f745xx.h:207
RCC_TypeDef::APB1LPENR
__IO uint32_t APB1LPENR
Definition: stm32f745xx.h:697
ADC_TypeDef::SMPR1
__IO uint32_t SMPR1
Definition: stm32f745xx.h:209
ADC_TypeDef::SQR3
__IO uint32_t SQR3
Definition: stm32f745xx.h:219
FLASH_TypeDef::OPTCR1
__IO uint32_t OPTCR1
Definition: stm32f745xx.h:541
SPI_TypeDef::I2SPR
__IO uint32_t I2SPR
Definition: stm32f745xx.h:851
LPTIM_TypeDef::ARR
__IO uint32_t ARR
Definition: stm32f745xx.h:919
USB_OTG_GlobalTypeDef::GRXFSIZ
__IO uint32_t GRXFSIZ
Definition: stm32f745xx.h:985
RTC_TypeDef::CALR
__IO uint32_t CALR
Definition: stm32f745xx.h:732
TIM_TypeDef::DIER
__IO uint32_t DIER
Definition: stm32f745xx.h:884
USART_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f745xx.h:931
RNG_TypeDef::SR
__IO uint32_t SR
Definition: stm32f745xx.h:963
USB_OTG_GlobalTypeDef::GRXSTSR
__IO uint32_t GRXSTSR
Definition: stm32f745xx.h:983
RNG_TypeDef
RNG.
Definition: stm32f745xx.h:960
QUADSPI_TypeDef::PIR
__IO uint32_t PIR
Definition: stm32f745xx.h:871
GPIO_TypeDef::ODR
__IO uint32_t ODR
Definition: stm32f745xx.h:603
ETH_TypeDef::DMACHTDR
__IO uint32_t DMACHTDR
Definition: stm32f745xx.h:509
FLASH_TypeDef::ACR
__IO uint32_t ACR
Definition: stm32f745xx.h:535
SPI6_IRQn
Definition: stm32f745xx.h:164
USB_OTG_DeviceTypeDef::DINEP1MSK
__IO uint32_t DINEP1MSK
Definition: stm32f745xx.h:1026
TIM1_BRK_TIM9_IRQn
Definition: stm32f745xx.h:103
TIM1_UP_TIM10_IRQn
Definition: stm32f745xx.h:104
SPDIFRX_TypeDef::DR
__IO uint32_t DR
Definition: stm32f745xx.h:803
TIM_TypeDef::CCR6
__IO uint32_t CCR6
Definition: stm32f745xx.h:904
USART_TypeDef::CR3
__IO uint32_t CR3
Definition: stm32f745xx.h:932
ETH_TypeDef::MACFCR
__IO uint32_t MACFCR
Definition: stm32f745xx.h:453
ADC_TypeDef::SMPR2
__IO uint32_t SMPR2
Definition: stm32f745xx.h:210
EXTI_TypeDef::SWIER
__IO uint32_t SWIER
Definition: stm32f745xx.h:525
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f745xx.h:359
RTC_TypeDef::OR
__IO uint32_t OR
Definition: stm32f745xx.h:736
USART_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f745xx.h:937
USB_OTG_GlobalTypeDef::GAHBCFG
__IO uint32_t GAHBCFG
Definition: stm32f745xx.h:978
CEC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f745xx.h:307
SPI1_IRQn
Definition: stm32f745xx.h:114
TIM3_IRQn
Definition: stm32f745xx.h:108
DMA2D_TypeDef::FGCOLR
__IO uint32_t FGCOLR
Definition: stm32f745xx.h:423
DAC_TypeDef::SWTRIGR
__IO uint32_t SWTRIGR
Definition: stm32f745xx.h:339
USB_OTG_HostTypeDef::HAINT
__IO uint32_t HAINT
Definition: stm32f745xx.h:1073
USB_OTG_INEndpointTypeDef::DTXFSTS
__IO uint32_t DTXFSTS
Definition: stm32f745xx.h:1043
ETH_TypeDef::MACA1HR
__IO uint32_t MACA1HR
Definition: stm32f745xx.h:463
RCC_TypeDef::AHB3LPENR
__IO uint32_t AHB3LPENR
Definition: stm32f745xx.h:695
ETH_TypeDef::PTPTSLUR
__IO uint32_t PTPTSLUR
Definition: stm32f745xx.h:491
NonMaskableInt_IRQn
Definition: stm32f745xx.h:70
SDMMC_TypeDef
SD host Interface.
Definition: stm32f745xx.h:813
TIM8_CC_IRQn
Definition: stm32f745xx.h:125
ETH_TypeDef::PTPTTHR
__IO uint32_t PTPTTHR
Definition: stm32f745xx.h:493
USB_OTG_HostChannelTypeDef::HCINT
__IO uint32_t HCINT
Definition: stm32f745xx.h:1084
USB_OTG_INEndpointTypeDef::Reserved0C
uint32_t Reserved0C
Definition: stm32f745xx.h:1040
DAC_TypeDef::DOR1
__IO uint32_t DOR1
Definition: stm32f745xx.h:349
SAI_Block_TypeDef
Definition: stm32f745xx.h:781
CEC_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32f745xx.h:308
EXTI0_IRQn
Definition: stm32f745xx.h:85
I2C_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f745xx.h:628
USB_OTG_OUTEndpointTypeDef::DOEPINT
__IO uint32_t DOEPINT
Definition: stm32f745xx.h:1055
ETH_TypeDef::PTPTSSR
__IO uint32_t PTPTSSR
Definition: stm32f745xx.h:496
USB_OTG_GlobalTypeDef::GUSBCFG
__IO uint32_t GUSBCFG
Definition: stm32f745xx.h:979
ETH_TypeDef::MACFFR
__IO uint32_t MACFFR
Definition: stm32f745xx.h:448
RCC_TypeDef::AHB3RSTR
__IO uint32_t AHB3RSTR
Definition: stm32f745xx.h:681
DAC_TypeDef::DHR8RD
__IO uint32_t DHR8RD
Definition: stm32f745xx.h:348
USB_OTG_HostTypeDef::Reserved40C
uint32_t Reserved40C
Definition: stm32f745xx.h:1071
TIM_TypeDef::OR
__IO uint32_t OR
Definition: stm32f745xx.h:901
DMA2D_TypeDef::BGCOLR
__IO uint32_t BGCOLR
Definition: stm32f745xx.h:425
RCC_TypeDef::AHB3ENR
__IO uint32_t AHB3ENR
Definition: stm32f745xx.h:688
QUADSPI_TypeDef::LPTR
__IO uint32_t LPTR
Definition: stm32f745xx.h:872
RTC_TypeDef::BKP25R
__IO uint32_t BKP25R
Definition: stm32f745xx.h:762
DCMI_TypeDef::ESUR
__IO uint32_t ESUR
Definition: stm32f745xx.h:380
CAN_TypeDef::TSR
__IO uint32_t TSR
Definition: stm32f745xx.h:279
ADC_TypeDef::SQR1
__IO uint32_t SQR1
Definition: stm32f745xx.h:217
EXTI2_IRQn
Definition: stm32f745xx.h:87
USB_OTG_OUTEndpointTypeDef
USB_OTG_OUT_Endpoint-Specific_Registers.
Definition: stm32f745xx.h:1051
IWDG_TypeDef::KR
__IO uint32_t KR
Definition: stm32f745xx.h:647
USART3_IRQn
Definition: stm32f745xx.h:118
ETH_TypeDef::DMAOMR
__IO uint32_t DMAOMR
Definition: stm32f745xx.h:504
SPI_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f745xx.h:844
CAN_TypeDef::FMR
__IO uint32_t FMR
Definition: stm32f745xx.h:289
ADC_TypeDef::SR
__IO uint32_t SR
Definition: stm32f745xx.h:206
EXTI_TypeDef::EMR
__IO uint32_t EMR
Definition: stm32f745xx.h:522
FLASH_TypeDef::OPTKEYR
__IO uint32_t OPTKEYR
Definition: stm32f745xx.h:537
RTC_TypeDef::BKP16R
__IO uint32_t BKP16R
Definition: stm32f745xx.h:753
DBGMCU_TypeDef::APB2FZ
__IO uint32_t APB2FZ
Definition: stm32f745xx.h:364
FLASH_TypeDef::OPTCR
__IO uint32_t OPTCR
Definition: stm32f745xx.h:540
SDMMC_TypeDef::CLKCR
__IO uint32_t CLKCR
Definition: stm32f745xx.h:816
SDMMC_TypeDef::RESP1
__I uint32_t RESP1
Definition: stm32f745xx.h:820
USART2_IRQn
Definition: stm32f745xx.h:117
RTC_TypeDef::BKP27R
__IO uint32_t BKP27R
Definition: stm32f745xx.h:764
TIM_TypeDef::DCR
__IO uint32_t DCR
Definition: stm32f745xx.h:899
SDMMC_TypeDef::RESP3
__I uint32_t RESP3
Definition: stm32f745xx.h:822
RTC_TypeDef::BKP30R
__IO uint32_t BKP30R
Definition: stm32f745xx.h:767
ETH_TypeDef::DMATDLAR
__IO uint32_t DMATDLAR
Definition: stm32f745xx.h:502
SPI_TypeDef::CRCPR
__IO uint32_t CRCPR
Definition: stm32f745xx.h:847
ADC_TypeDef::JDR3
__IO uint32_t JDR3
Definition: stm32f745xx.h:223
DAC_TypeDef::SR
__IO uint32_t SR
Definition: stm32f745xx.h:351
USB_OTG_OUTEndpointTypeDef::DOEPTSIZ
__IO uint32_t DOEPTSIZ
Definition: stm32f745xx.h:1057
USB_OTG_OUTEndpointTypeDef::Reserved0C
uint32_t Reserved0C
Definition: stm32f745xx.h:1056
USB_OTG_DeviceTypeDef::DAINTMSK
__IO uint32_t DAINTMSK
Definition: stm32f745xx.h:1016
ETH_TypeDef::MMCTGFMSCCR
__IO uint32_t MMCTGFMSCCR
Definition: stm32f745xx.h:477
USB_OTG_INEndpointTypeDef::DIEPCTL
__IO uint32_t DIEPCTL
Definition: stm32f745xx.h:1037
UART8_IRQn
Definition: stm32f745xx.h:161
USB_OTG_GlobalTypeDef::GOTGINT
__IO uint32_t GOTGINT
Definition: stm32f745xx.h:977
RCC_TypeDef::PLLCFGR
__IO uint32_t PLLCFGR
Definition: stm32f745xx.h:676
RCC_TypeDef::AHB2ENR
__IO uint32_t AHB2ENR
Definition: stm32f745xx.h:687
TIM_TypeDef::EGR
__IO uint32_t EGR
Definition: stm32f745xx.h:886
PWR_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f745xx.h:662
OTG_FS_IRQn
Definition: stm32f745xx.h:146
UsageFault_IRQn
Definition: stm32f745xx.h:73
USB_OTG_DeviceTypeDef::Reserved20
uint32_t Reserved20
Definition: stm32f745xx.h:1017
USB_OTG_DeviceTypeDef::DOUTEP1MSK
__IO uint32_t DOUTEP1MSK
Definition: stm32f745xx.h:1028
RTC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f745xx.h:719
ADC_TypeDef::DR
__IO uint32_t DR
Definition: stm32f745xx.h:225
TIM_TypeDef::CCMR2
__IO uint32_t CCMR2
Definition: stm32f745xx.h:888
MemoryManagement_IRQn
Definition: stm32f745xx.h:71
USB_OTG_DeviceTypeDef
USB_OTG_device_Registers.
Definition: stm32f745xx.h:1007
SDMMC_TypeDef::STA
__I uint32_t STA
Definition: stm32f745xx.h:828
ETH_TypeDef::DMACHRDR
__IO uint32_t DMACHRDR
Definition: stm32f745xx.h:510
TIM5_IRQn
Definition: stm32f745xx.h:129
SPDIFRX_TypeDef::DIR
__IO uint32_t DIR
Definition: stm32f745xx.h:805
I2C_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f745xx.h:629
SPDIFRX_TypeDef::SR
__IO uint32_t SR
Definition: stm32f745xx.h:801
RCC_TypeDef::DCKCFGR2
__IO uint32_t DCKCFGR2
Definition: stm32f745xx.h:707
USART6_IRQn
Definition: stm32f745xx.h:150
IWDG_TypeDef::PR
__IO uint32_t PR
Definition: stm32f745xx.h:648
USB_OTG_GlobalTypeDef::DIEPTXF0_HNPTXFSIZ
__IO uint32_t DIEPTXF0_HNPTXFSIZ
Definition: stm32f745xx.h:986
CRC_TypeDef::IDR
__IO uint8_t IDR
Definition: stm32f745xx.h:323
CAN1_RX0_IRQn
Definition: stm32f745xx.h:99
RTC_TypeDef::BKP5R
__IO uint32_t BKP5R
Definition: stm32f745xx.h:742
I2C_TypeDef::OAR2
__IO uint32_t OAR2
Definition: stm32f745xx.h:631
FMC_Bank3_TypeDef::PMEM
__IO uint32_t PMEM
Definition: stm32f745xx.h:572
DMA_Stream_TypeDef::FCR
__IO uint32_t FCR
Definition: stm32f745xx.h:397
CAN_FIFOMailBox_TypeDef::RDTR
__IO uint32_t RDTR
Definition: stm32f745xx.h:256
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