TPI_Type Struct Reference

Structure type to access the Trace Port Interface Register (TPI). More...

#include <core_cm3.h>

Data Fields
__IOM uint32_t	SSPSR
__IOM uint32_t	CSPSR
uint32_t	RESERVED0 [2U]
__IOM uint32_t	ACPR
uint32_t	RESERVED1 [55U]
__IOM uint32_t	SPPR
uint32_t	RESERVED2 [131U]
__IM uint32_t	FFSR
__IOM uint32_t	FFCR
__IM uint32_t	FSCR
uint32_t	RESERVED3 [759U]
__IM uint32_t	TRIGGER
__IM uint32_t	FIFO0
__IM uint32_t	ITATBCTR2
uint32_t	RESERVED4 [1U]
__IM uint32_t	ITATBCTR0
__IM uint32_t	FIFO1
__IOM uint32_t	ITCTRL
uint32_t	RESERVED5 [39U]
__IOM uint32_t	CLAIMSET
__IOM uint32_t	CLAIMCLR
uint32_t	RESERVED7 [8U]
__IM uint32_t	DEVID
__IM uint32_t	DEVTYPE

Detailed Description

Structure type to access the Trace Port Interface Register (TPI).

Definition at line 985 of file core_cm3.h.

Field Documentation

__IOM uint32_t ACPR

Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register

Definition at line 990 of file core_cm3.h.

__IOM uint32_t CLAIMCLR

Offset: 0xFA4 (R/W) Claim tag clear

Definition at line 1007 of file core_cm3.h.

__IOM uint32_t CLAIMSET

Offset: 0xFA0 (R/W) Claim tag set

Definition at line 1006 of file core_cm3.h.

__IOM uint32_t CSPSR

Offset: 0x004 (R/W) Current Parallel Port Size Register

Definition at line 988 of file core_cm3.h.

__IM uint32_t DEVID

Offset: 0xFC8 (R/ ) TPIU_DEVID

Definition at line 1009 of file core_cm3.h.

__IM uint32_t DEVTYPE

Offset: 0xFCC (R/ ) TPIU_DEVTYPE

Definition at line 1010 of file core_cm3.h.

__IOM uint32_t FFCR

Offset: 0x304 (R/W) Formatter and Flush Control Register

Definition at line 995 of file core_cm3.h.

__IM uint32_t FFSR

Offset: 0x300 (R/ ) Formatter and Flush Status Register

Definition at line 994 of file core_cm3.h.

__IM uint32_t FIFO0

Offset: 0xEEC (R/ ) Integration ETM Data

Definition at line 999 of file core_cm3.h.

__IM uint32_t FIFO1

Offset: 0xEFC (R/ ) Integration ITM Data

Definition at line 1003 of file core_cm3.h.

__IM uint32_t FSCR

Offset: 0x308 (R/ ) Formatter Synchronization Counter Register

Definition at line 996 of file core_cm3.h.

__IM uint32_t ITATBCTR0

Offset: 0xEF8 (R/ ) ITATBCTR0

Definition at line 1002 of file core_cm3.h.

__IM uint32_t ITATBCTR2

Offset: 0xEF0 (R/ ) ITATBCTR2

Definition at line 1000 of file core_cm3.h.

__IOM uint32_t ITCTRL

Offset: 0xF00 (R/W) Integration Mode Control

Definition at line 1004 of file core_cm3.h.

uint32_t RESERVED0

Definition at line 989 of file core_cm3.h.

uint32_t RESERVED1

Definition at line 991 of file core_cm3.h.

uint32_t RESERVED2

Definition at line 993 of file core_cm3.h.

uint32_t RESERVED3

Definition at line 997 of file core_cm3.h.

uint32_t RESERVED4

Definition at line 1001 of file core_cm3.h.

uint32_t RESERVED5

Definition at line 1005 of file core_cm3.h.

uint32_t RESERVED7

Definition at line 1008 of file core_cm3.h.

__IOM uint32_t SPPR

Offset: 0x0F0 (R/W) Selected Pin Protocol Register

Definition at line 992 of file core_cm3.h.

__IOM uint32_t SSPSR

Offset: 0x000 (R/ ) Supported Parallel Port Size Register

Definition at line 987 of file core_cm3.h.

__IM uint32_t TRIGGER

Offset: 0xEE8 (R/ ) TRIGGER

Definition at line 998 of file core_cm3.h.

---

The documentation for this struct was generated from the following files:

• C:/Users/Torsten/Documents/Eclipse_WS2/STM32F769IDiscovery/CMSIS/core/core_cm3.h
• C:/Users/Torsten/Documents/Eclipse_WS2/STM32F769IDiscovery/CMSIS/core/core_cm4.h
• C:/Users/Torsten/Documents/Eclipse_WS2/STM32F769IDiscovery/CMSIS/core/core_cm7.h
• C:/Users/Torsten/Documents/Eclipse_WS2/STM32F769IDiscovery/CMSIS/core/core_sc300.h