STM32F769IDiscovery  1.00
uDANTE Audio Networking with STM32F7 DISCO board
core_cm4.h
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1 /**************************************************************************/
7 /* Copyright (c) 2009 - 2015 ARM LIMITED
8 
9  All rights reserved.
10  Redistribution and use in source and binary forms, with or without
11  modification, are permitted provided that the following conditions are met:
12  - Redistributions of source code must retain the above copyright
13  notice, this list of conditions and the following disclaimer.
14  - Redistributions in binary form must reproduce the above copyright
15  notice, this list of conditions and the following disclaimer in the
16  documentation and/or other materials provided with the distribution.
17  - Neither the name of ARM nor the names of its contributors may be used
18  to endorse or promote products derived from this software without
19  specific prior written permission.
20  *
21  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
25  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  POSSIBILITY OF SUCH DAMAGE.
32  ---------------------------------------------------------------------------*/
33 
34 
35 #if defined ( __ICCARM__ )
36  #pragma system_include /* treat file as system include file for MISRA check */
37 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
38  #pragma clang system_header /* treat file as system include file */
39 #endif
40 
41 #ifndef __CORE_CM4_H_GENERIC
42 #define __CORE_CM4_H_GENERIC
43 
44 #include <stdint.h>
45 
46 #ifdef __cplusplus
47  extern "C" {
48 #endif
49 
65 /*******************************************************************************
66  * CMSIS definitions
67  ******************************************************************************/
73 /* CMSIS CM4 definitions */
74 #define __CM4_CMSIS_VERSION_MAIN (0x04U)
75 #define __CM4_CMSIS_VERSION_SUB (0x1EU)
76 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
77  __CM4_CMSIS_VERSION_SUB )
79 #define __CORTEX_M (0x04U)
82 #if defined ( __CC_ARM )
83  #define __ASM __asm
84  #define __INLINE __inline
85  #define __STATIC_INLINE static __inline
86 
87 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
88  #define __ASM __asm
89  #define __INLINE __inline
90  #define __STATIC_INLINE static __inline
91 
92 #elif defined ( __GNUC__ )
93  #define __ASM __asm
94  #define __INLINE inline
95  #define __STATIC_INLINE static inline
96 
97 #elif defined ( __ICCARM__ )
98  #define __ASM __asm
99  #define __INLINE inline
100  #define __STATIC_INLINE static inline
101 
102 #elif defined ( __TMS470__ )
103  #define __ASM __asm
104  #define __STATIC_INLINE static inline
105 
106 #elif defined ( __TASKING__ )
107  #define __ASM __asm
108  #define __INLINE inline
109  #define __STATIC_INLINE static inline
110 
111 #elif defined ( __CSMC__ )
112  #define __packed
113  #define __ASM _asm
114  #define __INLINE inline
115  #define __STATIC_INLINE static inline
116 
117 #else
118  #error Unknown compiler
119 #endif
120 
124 #if defined ( __CC_ARM )
125  #if defined __TARGET_FPU_VFP
126  #if (__FPU_PRESENT == 1U)
127  #define __FPU_USED 1U
128  #else
129  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
130  #define __FPU_USED 0U
131  #endif
132  #else
133  #define __FPU_USED 0U
134  #endif
135 
136 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
137  #if defined __ARM_PCS_VFP
138  #if (__FPU_PRESENT == 1)
139  #define __FPU_USED 1U
140  #else
141  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
142  #define __FPU_USED 0U
143  #endif
144  #else
145  #define __FPU_USED 0U
146  #endif
147 
148 #elif defined ( __GNUC__ )
149  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
150  #if (__FPU_PRESENT == 1U)
151  #define __FPU_USED 1U
152  #else
153  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
154  #define __FPU_USED 0U
155  #endif
156  #else
157  #define __FPU_USED 0U
158  #endif
159 
160 #elif defined ( __ICCARM__ )
161  #if defined __ARMVFP__
162  #if (__FPU_PRESENT == 1U)
163  #define __FPU_USED 1U
164  #else
165  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
166  #define __FPU_USED 0U
167  #endif
168  #else
169  #define __FPU_USED 0U
170  #endif
171 
172 #elif defined ( __TMS470__ )
173  #if defined __TI_VFP_SUPPORT__
174  #if (__FPU_PRESENT == 1U)
175  #define __FPU_USED 1U
176  #else
177  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
178  #define __FPU_USED 0U
179  #endif
180  #else
181  #define __FPU_USED 0U
182  #endif
183 
184 #elif defined ( __TASKING__ )
185  #if defined __FPU_VFP__
186  #if (__FPU_PRESENT == 1U)
187  #define __FPU_USED 1U
188  #else
189  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
190  #define __FPU_USED 0U
191  #endif
192  #else
193  #define __FPU_USED 0U
194  #endif
195 
196 #elif defined ( __CSMC__ )
197  #if ( __CSMC__ & 0x400U)
198  #if (__FPU_PRESENT == 1U)
199  #define __FPU_USED 1U
200  #else
201  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
202  #define __FPU_USED 0U
203  #endif
204  #else
205  #define __FPU_USED 0U
206  #endif
207 
208 #endif
209 
210 #include "core_cmInstr.h" /* Core Instruction Access */
211 #include "core_cmFunc.h" /* Core Function Access */
212 #include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */
213 
214 #ifdef __cplusplus
215 }
216 #endif
217 
218 #endif /* __CORE_CM4_H_GENERIC */
219 
220 #ifndef __CMSIS_GENERIC
221 
222 #ifndef __CORE_CM4_H_DEPENDANT
223 #define __CORE_CM4_H_DEPENDANT
224 
225 #ifdef __cplusplus
226  extern "C" {
227 #endif
228 
229 /* check device defines and use defaults */
230 #if defined __CHECK_DEVICE_DEFINES
231  #ifndef __CM4_REV
232  #define __CM4_REV 0x0000U
233  #warning "__CM4_REV not defined in device header file; using default!"
234  #endif
235 
236  #ifndef __FPU_PRESENT
237  #define __FPU_PRESENT 0U
238  #warning "__FPU_PRESENT not defined in device header file; using default!"
239  #endif
240 
241  #ifndef __MPU_PRESENT
242  #define __MPU_PRESENT 0U
243  #warning "__MPU_PRESENT not defined in device header file; using default!"
244  #endif
245 
246  #ifndef __NVIC_PRIO_BITS
247  #define __NVIC_PRIO_BITS 4U
248  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
249  #endif
250 
251  #ifndef __Vendor_SysTickConfig
252  #define __Vendor_SysTickConfig 0U
253  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
254  #endif
255 #endif
256 
257 /* IO definitions (access restrictions to peripheral registers) */
265 #ifdef __cplusplus
266  #define __I volatile
267 #else
268  #define __I volatile const
269 #endif
270 #define __O volatile
271 #define __IO volatile
273 /* following defines should be used for structure members */
274 #define __IM volatile const
275 #define __OM volatile
276 #define __IOM volatile
278 
282 /*******************************************************************************
283  * Register Abstraction
284  Core Register contain:
285  - Core Register
286  - Core NVIC Register
287  - Core SCB Register
288  - Core SysTick Register
289  - Core Debug Register
290  - Core MPU Register
291  - Core FPU Register
292  ******************************************************************************/
293 
308 typedef union
309 {
310  struct
311  {
312  uint32_t _reserved0:16;
313  uint32_t GE:4;
314  uint32_t _reserved1:7;
315  uint32_t Q:1;
316  uint32_t V:1;
317  uint32_t C:1;
318  uint32_t Z:1;
319  uint32_t N:1;
320  } b;
321  uint32_t w;
322 } APSR_Type;
323 
324 /* APSR Register Definitions */
325 #define APSR_N_Pos 31U
326 #define APSR_N_Msk (1UL << APSR_N_Pos)
328 #define APSR_Z_Pos 30U
329 #define APSR_Z_Msk (1UL << APSR_Z_Pos)
331 #define APSR_C_Pos 29U
332 #define APSR_C_Msk (1UL << APSR_C_Pos)
334 #define APSR_V_Pos 28U
335 #define APSR_V_Msk (1UL << APSR_V_Pos)
337 #define APSR_Q_Pos 27U
338 #define APSR_Q_Msk (1UL << APSR_Q_Pos)
340 #define APSR_GE_Pos 16U
341 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos)
347 typedef union
348 {
349  struct
350  {
351  uint32_t ISR:9;
352  uint32_t _reserved0:23;
353  } b;
354  uint32_t w;
355 } IPSR_Type;
356 
357 /* IPSR Register Definitions */
358 #define IPSR_ISR_Pos 0U
359 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
365 typedef union
366 {
367  struct
368  {
369  uint32_t ISR:9;
370  uint32_t _reserved0:7;
371  uint32_t GE:4;
372  uint32_t _reserved1:4;
373  uint32_t T:1;
374  uint32_t IT:2;
375  uint32_t Q:1;
376  uint32_t V:1;
377  uint32_t C:1;
378  uint32_t Z:1;
379  uint32_t N:1;
380  } b;
381  uint32_t w;
382 } xPSR_Type;
383 
384 /* xPSR Register Definitions */
385 #define xPSR_N_Pos 31U
386 #define xPSR_N_Msk (1UL << xPSR_N_Pos)
388 #define xPSR_Z_Pos 30U
389 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
391 #define xPSR_C_Pos 29U
392 #define xPSR_C_Msk (1UL << xPSR_C_Pos)
394 #define xPSR_V_Pos 28U
395 #define xPSR_V_Msk (1UL << xPSR_V_Pos)
397 #define xPSR_Q_Pos 27U
398 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos)
400 #define xPSR_IT_Pos 25U
401 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos)
403 #define xPSR_T_Pos 24U
404 #define xPSR_T_Msk (1UL << xPSR_T_Pos)
406 #define xPSR_GE_Pos 16U
407 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)
409 #define xPSR_ISR_Pos 0U
410 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
416 typedef union
417 {
418  struct
419  {
420  uint32_t nPRIV:1;
421  uint32_t SPSEL:1;
422  uint32_t FPCA:1;
423  uint32_t _reserved0:29;
424  } b;
425  uint32_t w;
426 } CONTROL_Type;
427 
428 /* CONTROL Register Definitions */
429 #define CONTROL_FPCA_Pos 2U
430 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)
432 #define CONTROL_SPSEL_Pos 1U
433 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
435 #define CONTROL_nPRIV_Pos 0U
436 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)
438 
451 typedef struct
452 {
453  __IOM uint32_t ISER[8U];
454  uint32_t RESERVED0[24U];
455  __IOM uint32_t ICER[8U];
456  uint32_t RSERVED1[24U];
457  __IOM uint32_t ISPR[8U];
458  uint32_t RESERVED2[24U];
459  __IOM uint32_t ICPR[8U];
460  uint32_t RESERVED3[24U];
461  __IOM uint32_t IABR[8U];
462  uint32_t RESERVED4[56U];
463  __IOM uint8_t IP[240U];
464  uint32_t RESERVED5[644U];
465  __OM uint32_t STIR;
466 } NVIC_Type;
467 
468 /* Software Triggered Interrupt Register Definitions */
469 #define NVIC_STIR_INTID_Pos 0U
470 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
472 
485 typedef struct
486 {
487  __IM uint32_t CPUID;
488  __IOM uint32_t ICSR;
489  __IOM uint32_t VTOR;
490  __IOM uint32_t AIRCR;
491  __IOM uint32_t SCR;
492  __IOM uint32_t CCR;
493  __IOM uint8_t SHP[12U];
494  __IOM uint32_t SHCSR;
495  __IOM uint32_t CFSR;
496  __IOM uint32_t HFSR;
497  __IOM uint32_t DFSR;
498  __IOM uint32_t MMFAR;
499  __IOM uint32_t BFAR;
500  __IOM uint32_t AFSR;
501  __IM uint32_t PFR[2U];
502  __IM uint32_t DFR;
503  __IM uint32_t ADR;
504  __IM uint32_t MMFR[4U];
505  __IM uint32_t ISAR[5U];
506  uint32_t RESERVED0[5U];
507  __IOM uint32_t CPACR;
508 } SCB_Type;
509 
510 /* SCB CPUID Register Definitions */
511 #define SCB_CPUID_IMPLEMENTER_Pos 24U
512 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
514 #define SCB_CPUID_VARIANT_Pos 20U
515 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
517 #define SCB_CPUID_ARCHITECTURE_Pos 16U
518 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
520 #define SCB_CPUID_PARTNO_Pos 4U
521 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
523 #define SCB_CPUID_REVISION_Pos 0U
524 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
526 /* SCB Interrupt Control State Register Definitions */
527 #define SCB_ICSR_NMIPENDSET_Pos 31U
528 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
530 #define SCB_ICSR_PENDSVSET_Pos 28U
531 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
533 #define SCB_ICSR_PENDSVCLR_Pos 27U
534 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
536 #define SCB_ICSR_PENDSTSET_Pos 26U
537 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
539 #define SCB_ICSR_PENDSTCLR_Pos 25U
540 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
542 #define SCB_ICSR_ISRPREEMPT_Pos 23U
543 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
545 #define SCB_ICSR_ISRPENDING_Pos 22U
546 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
548 #define SCB_ICSR_VECTPENDING_Pos 12U
549 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
551 #define SCB_ICSR_RETTOBASE_Pos 11U
552 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
554 #define SCB_ICSR_VECTACTIVE_Pos 0U
555 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
557 /* SCB Vector Table Offset Register Definitions */
558 #define SCB_VTOR_TBLOFF_Pos 7U
559 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
561 /* SCB Application Interrupt and Reset Control Register Definitions */
562 #define SCB_AIRCR_VECTKEY_Pos 16U
563 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
565 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U
566 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
568 #define SCB_AIRCR_ENDIANESS_Pos 15U
569 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
571 #define SCB_AIRCR_PRIGROUP_Pos 8U
572 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
574 #define SCB_AIRCR_SYSRESETREQ_Pos 2U
575 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
577 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
578 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
580 #define SCB_AIRCR_VECTRESET_Pos 0U
581 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
583 /* SCB System Control Register Definitions */
584 #define SCB_SCR_SEVONPEND_Pos 4U
585 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
587 #define SCB_SCR_SLEEPDEEP_Pos 2U
588 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
590 #define SCB_SCR_SLEEPONEXIT_Pos 1U
591 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
593 /* SCB Configuration Control Register Definitions */
594 #define SCB_CCR_STKALIGN_Pos 9U
595 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
597 #define SCB_CCR_BFHFNMIGN_Pos 8U
598 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
600 #define SCB_CCR_DIV_0_TRP_Pos 4U
601 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
603 #define SCB_CCR_UNALIGN_TRP_Pos 3U
604 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
606 #define SCB_CCR_USERSETMPEND_Pos 1U
607 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
609 #define SCB_CCR_NONBASETHRDENA_Pos 0U
610 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
612 /* SCB System Handler Control and State Register Definitions */
613 #define SCB_SHCSR_USGFAULTENA_Pos 18U
614 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
616 #define SCB_SHCSR_BUSFAULTENA_Pos 17U
617 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
619 #define SCB_SHCSR_MEMFAULTENA_Pos 16U
620 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
622 #define SCB_SHCSR_SVCALLPENDED_Pos 15U
623 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
625 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U
626 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
628 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U
629 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
631 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U
632 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
634 #define SCB_SHCSR_SYSTICKACT_Pos 11U
635 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
637 #define SCB_SHCSR_PENDSVACT_Pos 10U
638 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
640 #define SCB_SHCSR_MONITORACT_Pos 8U
641 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
643 #define SCB_SHCSR_SVCALLACT_Pos 7U
644 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
646 #define SCB_SHCSR_USGFAULTACT_Pos 3U
647 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
649 #define SCB_SHCSR_BUSFAULTACT_Pos 1U
650 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
652 #define SCB_SHCSR_MEMFAULTACT_Pos 0U
653 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
655 /* SCB Configurable Fault Status Register Definitions */
656 #define SCB_CFSR_USGFAULTSR_Pos 16U
657 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
659 #define SCB_CFSR_BUSFAULTSR_Pos 8U
660 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
662 #define SCB_CFSR_MEMFAULTSR_Pos 0U
663 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
665 /* SCB Hard Fault Status Register Definitions */
666 #define SCB_HFSR_DEBUGEVT_Pos 31U
667 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
669 #define SCB_HFSR_FORCED_Pos 30U
670 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
672 #define SCB_HFSR_VECTTBL_Pos 1U
673 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
675 /* SCB Debug Fault Status Register Definitions */
676 #define SCB_DFSR_EXTERNAL_Pos 4U
677 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
679 #define SCB_DFSR_VCATCH_Pos 3U
680 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
682 #define SCB_DFSR_DWTTRAP_Pos 2U
683 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
685 #define SCB_DFSR_BKPT_Pos 1U
686 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
688 #define SCB_DFSR_HALTED_Pos 0U
689 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)
691 
704 typedef struct
705 {
706  uint32_t RESERVED0[1U];
707  __IM uint32_t ICTR;
708  __IOM uint32_t ACTLR;
709 } SCnSCB_Type;
710 
711 /* Interrupt Controller Type Register Definitions */
712 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U
713 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
715 /* Auxiliary Control Register Definitions */
716 #define SCnSCB_ACTLR_DISOOFP_Pos 9U
717 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos)
719 #define SCnSCB_ACTLR_DISFPCA_Pos 8U
720 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos)
722 #define SCnSCB_ACTLR_DISFOLD_Pos 2U
723 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)
725 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U
726 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)
728 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U
729 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)
731 
744 typedef struct
745 {
746  __IOM uint32_t CTRL;
747  __IOM uint32_t LOAD;
748  __IOM uint32_t VAL;
749  __IM uint32_t CALIB;
750 } SysTick_Type;
751 
752 /* SysTick Control / Status Register Definitions */
753 #define SysTick_CTRL_COUNTFLAG_Pos 16U
754 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
756 #define SysTick_CTRL_CLKSOURCE_Pos 2U
757 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
759 #define SysTick_CTRL_TICKINT_Pos 1U
760 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
762 #define SysTick_CTRL_ENABLE_Pos 0U
763 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
765 /* SysTick Reload Register Definitions */
766 #define SysTick_LOAD_RELOAD_Pos 0U
767 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
769 /* SysTick Current Register Definitions */
770 #define SysTick_VAL_CURRENT_Pos 0U
771 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
773 /* SysTick Calibration Register Definitions */
774 #define SysTick_CALIB_NOREF_Pos 31U
775 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
777 #define SysTick_CALIB_SKEW_Pos 30U
778 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
780 #define SysTick_CALIB_TENMS_Pos 0U
781 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
783 
796 typedef struct
797 {
798  __OM union
799  {
800  __OM uint8_t u8;
801  __OM uint16_t u16;
802  __OM uint32_t u32;
803  } PORT [32U];
804  uint32_t RESERVED0[864U];
805  __IOM uint32_t TER;
806  uint32_t RESERVED1[15U];
807  __IOM uint32_t TPR;
808  uint32_t RESERVED2[15U];
809  __IOM uint32_t TCR;
810  uint32_t RESERVED3[29U];
811  __OM uint32_t IWR;
812  __IM uint32_t IRR;
813  __IOM uint32_t IMCR;
814  uint32_t RESERVED4[43U];
815  __OM uint32_t LAR;
816  __IM uint32_t LSR;
817  uint32_t RESERVED5[6U];
818  __IM uint32_t PID4;
819  __IM uint32_t PID5;
820  __IM uint32_t PID6;
821  __IM uint32_t PID7;
822  __IM uint32_t PID0;
823  __IM uint32_t PID1;
824  __IM uint32_t PID2;
825  __IM uint32_t PID3;
826  __IM uint32_t CID0;
827  __IM uint32_t CID1;
828  __IM uint32_t CID2;
829  __IM uint32_t CID3;
830 } ITM_Type;
831 
832 /* ITM Trace Privilege Register Definitions */
833 #define ITM_TPR_PRIVMASK_Pos 0U
834 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
836 /* ITM Trace Control Register Definitions */
837 #define ITM_TCR_BUSY_Pos 23U
838 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
840 #define ITM_TCR_TraceBusID_Pos 16U
841 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)
843 #define ITM_TCR_GTSFREQ_Pos 10U
844 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
846 #define ITM_TCR_TSPrescale_Pos 8U
847 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)
849 #define ITM_TCR_SWOENA_Pos 4U
850 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
852 #define ITM_TCR_DWTENA_Pos 3U
853 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
855 #define ITM_TCR_SYNCENA_Pos 2U
856 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
858 #define ITM_TCR_TSENA_Pos 1U
859 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
861 #define ITM_TCR_ITMENA_Pos 0U
862 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)
864 /* ITM Integration Write Register Definitions */
865 #define ITM_IWR_ATVALIDM_Pos 0U
866 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)
868 /* ITM Integration Read Register Definitions */
869 #define ITM_IRR_ATREADYM_Pos 0U
870 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)
872 /* ITM Integration Mode Control Register Definitions */
873 #define ITM_IMCR_INTEGRATION_Pos 0U
874 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)
876 /* ITM Lock Status Register Definitions */
877 #define ITM_LSR_ByteAcc_Pos 2U
878 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
880 #define ITM_LSR_Access_Pos 1U
881 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
883 #define ITM_LSR_Present_Pos 0U
884 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)
886  /* end of group CMSIS_ITM */
887 
888 
899 typedef struct
900 {
901  __IOM uint32_t CTRL;
902  __IOM uint32_t CYCCNT;
903  __IOM uint32_t CPICNT;
904  __IOM uint32_t EXCCNT;
905  __IOM uint32_t SLEEPCNT;
906  __IOM uint32_t LSUCNT;
907  __IOM uint32_t FOLDCNT;
908  __IM uint32_t PCSR;
909  __IOM uint32_t COMP0;
910  __IOM uint32_t MASK0;
911  __IOM uint32_t FUNCTION0;
912  uint32_t RESERVED0[1U];
913  __IOM uint32_t COMP1;
914  __IOM uint32_t MASK1;
915  __IOM uint32_t FUNCTION1;
916  uint32_t RESERVED1[1U];
917  __IOM uint32_t COMP2;
918  __IOM uint32_t MASK2;
919  __IOM uint32_t FUNCTION2;
920  uint32_t RESERVED2[1U];
921  __IOM uint32_t COMP3;
922  __IOM uint32_t MASK3;
923  __IOM uint32_t FUNCTION3;
924 } DWT_Type;
925 
926 /* DWT Control Register Definitions */
927 #define DWT_CTRL_NUMCOMP_Pos 28U
928 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
930 #define DWT_CTRL_NOTRCPKT_Pos 27U
931 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
933 #define DWT_CTRL_NOEXTTRIG_Pos 26U
934 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
936 #define DWT_CTRL_NOCYCCNT_Pos 25U
937 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
939 #define DWT_CTRL_NOPRFCNT_Pos 24U
940 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
942 #define DWT_CTRL_CYCEVTENA_Pos 22U
943 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
945 #define DWT_CTRL_FOLDEVTENA_Pos 21U
946 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
948 #define DWT_CTRL_LSUEVTENA_Pos 20U
949 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
951 #define DWT_CTRL_SLEEPEVTENA_Pos 19U
952 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
954 #define DWT_CTRL_EXCEVTENA_Pos 18U
955 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
957 #define DWT_CTRL_CPIEVTENA_Pos 17U
958 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
960 #define DWT_CTRL_EXCTRCENA_Pos 16U
961 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
963 #define DWT_CTRL_PCSAMPLENA_Pos 12U
964 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
966 #define DWT_CTRL_SYNCTAP_Pos 10U
967 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
969 #define DWT_CTRL_CYCTAP_Pos 9U
970 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
972 #define DWT_CTRL_POSTINIT_Pos 5U
973 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
975 #define DWT_CTRL_POSTPRESET_Pos 1U
976 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
978 #define DWT_CTRL_CYCCNTENA_Pos 0U
979 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
981 /* DWT CPI Count Register Definitions */
982 #define DWT_CPICNT_CPICNT_Pos 0U
983 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
985 /* DWT Exception Overhead Count Register Definitions */
986 #define DWT_EXCCNT_EXCCNT_Pos 0U
987 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
989 /* DWT Sleep Count Register Definitions */
990 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U
991 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
993 /* DWT LSU Count Register Definitions */
994 #define DWT_LSUCNT_LSUCNT_Pos 0U
995 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
997 /* DWT Folded-instruction Count Register Definitions */
998 #define DWT_FOLDCNT_FOLDCNT_Pos 0U
999 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
1001 /* DWT Comparator Mask Register Definitions */
1002 #define DWT_MASK_MASK_Pos 0U
1003 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/)
1005 /* DWT Comparator Function Register Definitions */
1006 #define DWT_FUNCTION_MATCHED_Pos 24U
1007 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
1009 #define DWT_FUNCTION_DATAVADDR1_Pos 16U
1010 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
1012 #define DWT_FUNCTION_DATAVADDR0_Pos 12U
1013 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
1015 #define DWT_FUNCTION_DATAVSIZE_Pos 10U
1016 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
1018 #define DWT_FUNCTION_LNK1ENA_Pos 9U
1019 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
1021 #define DWT_FUNCTION_DATAVMATCH_Pos 8U
1022 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
1024 #define DWT_FUNCTION_CYCMATCH_Pos 7U
1025 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
1027 #define DWT_FUNCTION_EMITRANGE_Pos 5U
1028 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
1030 #define DWT_FUNCTION_FUNCTION_Pos 0U
1031 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)
1033  /* end of group CMSIS_DWT */
1034 
1035 
1046 typedef struct
1047 {
1048  __IOM uint32_t SSPSR;
1049  __IOM uint32_t CSPSR;
1050  uint32_t RESERVED0[2U];
1051  __IOM uint32_t ACPR;
1052  uint32_t RESERVED1[55U];
1053  __IOM uint32_t SPPR;
1054  uint32_t RESERVED2[131U];
1055  __IM uint32_t FFSR;
1056  __IOM uint32_t FFCR;
1057  __IM uint32_t FSCR;
1058  uint32_t RESERVED3[759U];
1059  __IM uint32_t TRIGGER;
1060  __IM uint32_t FIFO0;
1061  __IM uint32_t ITATBCTR2;
1062  uint32_t RESERVED4[1U];
1063  __IM uint32_t ITATBCTR0;
1064  __IM uint32_t FIFO1;
1065  __IOM uint32_t ITCTRL;
1066  uint32_t RESERVED5[39U];
1067  __IOM uint32_t CLAIMSET;
1068  __IOM uint32_t CLAIMCLR;
1069  uint32_t RESERVED7[8U];
1070  __IM uint32_t DEVID;
1071  __IM uint32_t DEVTYPE;
1072 } TPI_Type;
1073 
1074 /* TPI Asynchronous Clock Prescaler Register Definitions */
1075 #define TPI_ACPR_PRESCALER_Pos 0U
1076 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
1078 /* TPI Selected Pin Protocol Register Definitions */
1079 #define TPI_SPPR_TXMODE_Pos 0U
1080 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
1082 /* TPI Formatter and Flush Status Register Definitions */
1083 #define TPI_FFSR_FtNonStop_Pos 3U
1084 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
1086 #define TPI_FFSR_TCPresent_Pos 2U
1087 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
1089 #define TPI_FFSR_FtStopped_Pos 1U
1090 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
1092 #define TPI_FFSR_FlInProg_Pos 0U
1093 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
1095 /* TPI Formatter and Flush Control Register Definitions */
1096 #define TPI_FFCR_TrigIn_Pos 8U
1097 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
1099 #define TPI_FFCR_EnFCont_Pos 1U
1100 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
1102 /* TPI TRIGGER Register Definitions */
1103 #define TPI_TRIGGER_TRIGGER_Pos 0U
1104 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
1106 /* TPI Integration ETM Data Register Definitions (FIFO0) */
1107 #define TPI_FIFO0_ITM_ATVALID_Pos 29U
1108 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
1110 #define TPI_FIFO0_ITM_bytecount_Pos 27U
1111 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
1113 #define TPI_FIFO0_ETM_ATVALID_Pos 26U
1114 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
1116 #define TPI_FIFO0_ETM_bytecount_Pos 24U
1117 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
1119 #define TPI_FIFO0_ETM2_Pos 16U
1120 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
1122 #define TPI_FIFO0_ETM1_Pos 8U
1123 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
1125 #define TPI_FIFO0_ETM0_Pos 0U
1126 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)
1128 /* TPI ITATBCTR2 Register Definitions */
1129 #define TPI_ITATBCTR2_ATREADY_Pos 0U
1130 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)
1132 /* TPI Integration ITM Data Register Definitions (FIFO1) */
1133 #define TPI_FIFO1_ITM_ATVALID_Pos 29U
1134 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
1136 #define TPI_FIFO1_ITM_bytecount_Pos 27U
1137 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
1139 #define TPI_FIFO1_ETM_ATVALID_Pos 26U
1140 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
1142 #define TPI_FIFO1_ETM_bytecount_Pos 24U
1143 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
1145 #define TPI_FIFO1_ITM2_Pos 16U
1146 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
1148 #define TPI_FIFO1_ITM1_Pos 8U
1149 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
1151 #define TPI_FIFO1_ITM0_Pos 0U
1152 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)
1154 /* TPI ITATBCTR0 Register Definitions */
1155 #define TPI_ITATBCTR0_ATREADY_Pos 0U
1156 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)
1158 /* TPI Integration Mode Control Register Definitions */
1159 #define TPI_ITCTRL_Mode_Pos 0U
1160 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)
1162 /* TPI DEVID Register Definitions */
1163 #define TPI_DEVID_NRZVALID_Pos 11U
1164 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
1166 #define TPI_DEVID_MANCVALID_Pos 10U
1167 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
1169 #define TPI_DEVID_PTINVALID_Pos 9U
1170 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
1172 #define TPI_DEVID_MinBufSz_Pos 6U
1173 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
1175 #define TPI_DEVID_AsynClkIn_Pos 5U
1176 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
1178 #define TPI_DEVID_NrTraceInput_Pos 0U
1179 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
1181 /* TPI DEVTYPE Register Definitions */
1182 #define TPI_DEVTYPE_MajorType_Pos 4U
1183 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
1185 #define TPI_DEVTYPE_SubType_Pos 0U
1186 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
1188  /* end of group CMSIS_TPI */
1189 
1190 
1191 #if (__MPU_PRESENT == 1U)
1192 
1202 typedef struct
1203 {
1204  __IM uint32_t TYPE;
1205  __IOM uint32_t CTRL;
1206  __IOM uint32_t RNR;
1207  __IOM uint32_t RBAR;
1208  __IOM uint32_t RASR;
1209  __IOM uint32_t RBAR_A1;
1210  __IOM uint32_t RASR_A1;
1211  __IOM uint32_t RBAR_A2;
1212  __IOM uint32_t RASR_A2;
1213  __IOM uint32_t RBAR_A3;
1214  __IOM uint32_t RASR_A3;
1215 } MPU_Type;
1216 
1217 /* MPU Type Register Definitions */
1218 #define MPU_TYPE_IREGION_Pos 16U
1219 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
1221 #define MPU_TYPE_DREGION_Pos 8U
1222 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
1224 #define MPU_TYPE_SEPARATE_Pos 0U
1225 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
1227 /* MPU Control Register Definitions */
1228 #define MPU_CTRL_PRIVDEFENA_Pos 2U
1229 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
1231 #define MPU_CTRL_HFNMIENA_Pos 1U
1232 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
1234 #define MPU_CTRL_ENABLE_Pos 0U
1235 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
1237 /* MPU Region Number Register Definitions */
1238 #define MPU_RNR_REGION_Pos 0U
1239 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
1241 /* MPU Region Base Address Register Definitions */
1242 #define MPU_RBAR_ADDR_Pos 5U
1243 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
1245 #define MPU_RBAR_VALID_Pos 4U
1246 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
1248 #define MPU_RBAR_REGION_Pos 0U
1249 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
1251 /* MPU Region Attribute and Size Register Definitions */
1252 #define MPU_RASR_ATTRS_Pos 16U
1253 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
1255 #define MPU_RASR_XN_Pos 28U
1256 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
1258 #define MPU_RASR_AP_Pos 24U
1259 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
1261 #define MPU_RASR_TEX_Pos 19U
1262 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
1264 #define MPU_RASR_S_Pos 18U
1265 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
1267 #define MPU_RASR_C_Pos 17U
1268 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
1270 #define MPU_RASR_B_Pos 16U
1271 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
1273 #define MPU_RASR_SRD_Pos 8U
1274 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
1276 #define MPU_RASR_SIZE_Pos 1U
1277 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
1279 #define MPU_RASR_ENABLE_Pos 0U
1280 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/)
1282 
1283 #endif
1284 
1285 
1286 #if (__FPU_PRESENT == 1U)
1287 
1297 typedef struct
1298 {
1299  uint32_t RESERVED0[1U];
1300  __IOM uint32_t FPCCR;
1301  __IOM uint32_t FPCAR;
1302  __IOM uint32_t FPDSCR;
1303  __IM uint32_t MVFR0;
1304  __IM uint32_t MVFR1;
1305 } FPU_Type;
1306 
1307 /* Floating-Point Context Control Register Definitions */
1308 #define FPU_FPCCR_ASPEN_Pos 31U
1309 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
1311 #define FPU_FPCCR_LSPEN_Pos 30U
1312 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
1314 #define FPU_FPCCR_MONRDY_Pos 8U
1315 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
1317 #define FPU_FPCCR_BFRDY_Pos 6U
1318 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
1320 #define FPU_FPCCR_MMRDY_Pos 5U
1321 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
1323 #define FPU_FPCCR_HFRDY_Pos 4U
1324 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
1326 #define FPU_FPCCR_THREAD_Pos 3U
1327 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
1329 #define FPU_FPCCR_USER_Pos 1U
1330 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
1332 #define FPU_FPCCR_LSPACT_Pos 0U
1333 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
1335 /* Floating-Point Context Address Register Definitions */
1336 #define FPU_FPCAR_ADDRESS_Pos 3U
1337 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
1339 /* Floating-Point Default Status Control Register Definitions */
1340 #define FPU_FPDSCR_AHP_Pos 26U
1341 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
1343 #define FPU_FPDSCR_DN_Pos 25U
1344 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
1346 #define FPU_FPDSCR_FZ_Pos 24U
1347 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
1349 #define FPU_FPDSCR_RMode_Pos 22U
1350 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
1352 /* Media and FP Feature Register 0 Definitions */
1353 #define FPU_MVFR0_FP_rounding_modes_Pos 28U
1354 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
1356 #define FPU_MVFR0_Short_vectors_Pos 24U
1357 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)
1359 #define FPU_MVFR0_Square_root_Pos 20U
1360 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)
1362 #define FPU_MVFR0_Divide_Pos 16U
1363 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)
1365 #define FPU_MVFR0_FP_excep_trapping_Pos 12U
1366 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
1368 #define FPU_MVFR0_Double_precision_Pos 8U
1369 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)
1371 #define FPU_MVFR0_Single_precision_Pos 4U
1372 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)
1374 #define FPU_MVFR0_A_SIMD_registers_Pos 0U
1375 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
1377 /* Media and FP Feature Register 1 Definitions */
1378 #define FPU_MVFR1_FP_fused_MAC_Pos 28U
1379 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
1381 #define FPU_MVFR1_FP_HPFP_Pos 24U
1382 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
1384 #define FPU_MVFR1_D_NaN_mode_Pos 4U
1385 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
1387 #define FPU_MVFR1_FtZ_mode_Pos 0U
1388 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
1390 
1391 #endif
1392 
1393 
1404 typedef struct
1405 {
1406  __IOM uint32_t DHCSR;
1407  __OM uint32_t DCRSR;
1408  __IOM uint32_t DCRDR;
1409  __IOM uint32_t DEMCR;
1410 } CoreDebug_Type;
1411 
1412 /* Debug Halting Control and Status Register Definitions */
1413 #define CoreDebug_DHCSR_DBGKEY_Pos 16U
1414 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1416 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U
1417 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1419 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
1420 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1422 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U
1423 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1425 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U
1426 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1428 #define CoreDebug_DHCSR_S_HALT_Pos 17U
1429 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1431 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U
1432 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1434 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
1435 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
1437 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U
1438 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1440 #define CoreDebug_DHCSR_C_STEP_Pos 2U
1441 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1443 #define CoreDebug_DHCSR_C_HALT_Pos 1U
1444 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1446 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
1447 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
1449 /* Debug Core Register Selector Register Definitions */
1450 #define CoreDebug_DCRSR_REGWnR_Pos 16U
1451 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1453 #define CoreDebug_DCRSR_REGSEL_Pos 0U
1454 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
1456 /* Debug Exception and Monitor Control Register Definitions */
1457 #define CoreDebug_DEMCR_TRCENA_Pos 24U
1458 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
1460 #define CoreDebug_DEMCR_MON_REQ_Pos 19U
1461 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
1463 #define CoreDebug_DEMCR_MON_STEP_Pos 18U
1464 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
1466 #define CoreDebug_DEMCR_MON_PEND_Pos 17U
1467 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
1469 #define CoreDebug_DEMCR_MON_EN_Pos 16U
1470 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
1472 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U
1473 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1475 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U
1476 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
1478 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U
1479 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
1481 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U
1482 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
1484 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U
1485 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
1487 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
1488 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
1490 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U
1491 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
1493 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U
1494 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
1496 
1512 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
1513 
1520 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
1521 
1532 /* Memory mapping of Cortex-M4 Hardware */
1533 #define SCS_BASE (0xE000E000UL)
1534 #define ITM_BASE (0xE0000000UL)
1535 #define DWT_BASE (0xE0001000UL)
1536 #define TPI_BASE (0xE0040000UL)
1537 #define CoreDebug_BASE (0xE000EDF0UL)
1538 #define SysTick_BASE (SCS_BASE + 0x0010UL)
1539 #define NVIC_BASE (SCS_BASE + 0x0100UL)
1540 #define SCB_BASE (SCS_BASE + 0x0D00UL)
1542 #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
1543 #define SCB ((SCB_Type *) SCB_BASE )
1544 #define SysTick ((SysTick_Type *) SysTick_BASE )
1545 #define NVIC ((NVIC_Type *) NVIC_BASE )
1546 #define ITM ((ITM_Type *) ITM_BASE )
1547 #define DWT ((DWT_Type *) DWT_BASE )
1548 #define TPI ((TPI_Type *) TPI_BASE )
1549 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)
1551 #if (__MPU_PRESENT == 1U)
1552  #define MPU_BASE (SCS_BASE + 0x0D90UL)
1553  #define MPU ((MPU_Type *) MPU_BASE )
1554 #endif
1555 
1556 #if (__FPU_PRESENT == 1U)
1557  #define FPU_BASE (SCS_BASE + 0x0F30UL)
1558  #define FPU ((FPU_Type *) FPU_BASE )
1559 #endif
1560 
1565 /*******************************************************************************
1566  * Hardware Abstraction Layer
1567  Core Function Interface contains:
1568  - Core NVIC Functions
1569  - Core SysTick Functions
1570  - Core Debug Functions
1571  - Core Register Access Functions
1572  ******************************************************************************/
1579 /* ########################## NVIC functions #################################### */
1596 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1597 {
1598  uint32_t reg_value;
1599  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1600 
1601  reg_value = SCB->AIRCR; /* read old register configuration */
1602  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
1603  reg_value = (reg_value |
1604  ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1605  (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
1606  SCB->AIRCR = reg_value;
1607 }
1608 
1609 
1615 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1616 {
1617  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1618 }
1619 
1620 
1626 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1627 {
1628  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1629 }
1630 
1631 
1637 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1638 {
1639  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1640 }
1641 
1642 
1650 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1651 {
1652  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1653 }
1654 
1655 
1661 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1662 {
1663  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1664 }
1665 
1666 
1672 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1673 {
1674  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1675 }
1676 
1677 
1685 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1686 {
1687  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1688 }
1689 
1690 
1698 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1699 {
1700  if ((int32_t)(IRQn) < 0)
1701  {
1702  SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1703  }
1704  else
1705  {
1706  NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1707  }
1708 }
1709 
1710 
1720 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1721 {
1722 
1723  if ((int32_t)(IRQn) < 0)
1724  {
1725  return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
1726  }
1727  else
1728  {
1729  return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
1730  }
1731 }
1732 
1733 
1745 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1746 {
1747  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1748  uint32_t PreemptPriorityBits;
1749  uint32_t SubPriorityBits;
1750 
1751  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1752  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1753 
1754  return (
1755  ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1756  ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1757  );
1758 }
1759 
1760 
1772 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
1773 {
1774  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1775  uint32_t PreemptPriorityBits;
1776  uint32_t SubPriorityBits;
1777 
1778  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1779  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1780 
1781  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1782  *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1783 }
1784 
1785 
1790 __STATIC_INLINE void NVIC_SystemReset(void)
1791 {
1792  __DSB(); /* Ensure all outstanding memory accesses included
1793  buffered write are completed before reset */
1794  SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1795  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1796  SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
1797  __DSB(); /* Ensure completion of memory access */
1798 
1799  for(;;) /* wait until reset */
1800  {
1801  __NOP();
1802  }
1803 }
1804 
1809 /* ################################## SysTick function ############################################ */
1817 #if (__Vendor_SysTickConfig == 0U)
1818 
1830 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1831 {
1832  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
1833  {
1834  return (1UL); /* Reload value impossible */
1835  }
1836 
1837  SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1838  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1839  SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
1840  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1841  SysTick_CTRL_TICKINT_Msk |
1842  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1843  return (0UL); /* Function successful */
1844 }
1845 
1846 #endif
1847 
1852 /* ##################################### Debug In/Output function ########################################### */
1860 extern volatile int32_t ITM_RxBuffer;
1861 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5U
1872 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
1873 {
1874  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
1875  ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
1876  {
1877  while (ITM->PORT[0U].u32 == 0UL)
1878  {
1879  __NOP();
1880  }
1881  ITM->PORT[0U].u8 = (uint8_t)ch;
1882  }
1883  return (ch);
1884 }
1885 
1886 
1893 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
1894 {
1895  int32_t ch = -1; /* no character available */
1896 
1897  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
1898  {
1899  ch = ITM_RxBuffer;
1900  ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1901  }
1902 
1903  return (ch);
1904 }
1905 
1906 
1913 __STATIC_INLINE int32_t ITM_CheckChar (void)
1914 {
1915 
1916  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
1917  {
1918  return (0); /* no character available */
1919  }
1920  else
1921  {
1922  return (1); /* character available */
1923  }
1924 }
1925 
1931 #ifdef __cplusplus
1932 }
1933 #endif
1934 
1935 #endif /* __CORE_CM4_H_DEPENDANT */
1936 
1937 #endif /* __CMSIS_GENERIC */
ITM
#define ITM
Definition: core_cm4.h:1546
core_cmFunc.h
CMSIS Cortex-M Core Function Access Header File.
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: core_cm3.h:838
__NOP
#define __NOP
No Operation.
Definition: cmsis_armcc.h:313
SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
Definition: core_cm4.h:572
NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_cm0.h:653
NVIC_SetPendingIRQ
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_cm0.h:664
NVIC_GetPriorityGrouping
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
Definition: core_cm3.h:1441
SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
Definition: core_cm4.h:563
ch
return ch
Definition: lcd_log.c:311
SysTick
#define SysTick
Definition: core_cm4.h:1544
ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Definition: core_cm4.h:1861
__OM
#define __OM
Definition: core_cm4.h:275
ITM_RxBuffer
volatile int32_t ITM_RxBuffer
ITM_ReceiveChar
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition: core_cm3.h:1719
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_cm0.h:277
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition: core_cm3.h:985
ITM_CheckChar
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition: core_cm3.h:1739
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: core_cm3.h:1598
__DSB
#define __DSB()
Data Synchronization Barrier.
Definition: cmsis_armcc.h:355
NVIC
#define NVIC
Definition: core_cm4.h:1545
NVIC_EnableIRQ
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable External Interrupt.
Definition: core_cm0.h:629
SysTick_IRQn
Definition: stm32f745xx.h:77
CoreDebug_Type
Structure type to access the Core Debug Register (CoreDebug).
Definition: core_cm3.h:1235
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: core_cm0.h:389
ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
Definition: core_cm4.h:862
SCB
#define SCB
Definition: core_cm4.h:1543
ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition: core_cm3.h:735
core_cmSimd.h
CMSIS Cortex-M SIMD Header File.
IRQn_Type
IRQn_Type
STM32F7xx Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f745xx.h:67
NVIC_SetPriorityGrouping
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
Definition: core_cm3.h:1422
SysTick_Config
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
System Tick Configuration.
Definition: core_cm0.h:769
NVIC_GetPriority
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_cm0.h:712
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: stm32f745xx.h:185
SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
Definition: core_cm4.h:571
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition: core_cm3.h:644
NVIC_SetPriority
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_cm0.h:688
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_cm0.h:362
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: core_cm0.h:496
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_cm4.h:562
NVIC_SystemReset
__STATIC_INLINE void NVIC_SystemReset(void)
System Reset.
Definition: core_cm0.h:730
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_cm4.h:575
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: core_cm0.h:247
NVIC_DisableIRQ
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Disable External Interrupt.
Definition: core_cm0.h:640
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_cm4.h:767
__IM
#define __IM
Definition: core_cm4.h:274
__IOM
#define __IOM
Definition: core_cm4.h:276
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: core_cm0.h:334
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_cm4.h:757
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_cm4.h:763
SCnSCB_Type::ACTLR
__IOM uint32_t ACTLR
Definition: core_cm4.h:708
NVIC_ClearPendingIRQ
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_cm0.h:675
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: core_cm3.h:1571
core_cmInstr.h
CMSIS Cortex-M Core Instruction Access Header File.
NVIC_GetActive
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: core_cm3.h:1511
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_cm0.h:295
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_cm4.h:760
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