STM32F769IDiscovery  1.00
uDANTE Audio Networking with STM32F7 DISCO board
stm32f765xx.h
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1 
52 #ifndef __STM32F765xx_H
53 #define __STM32F765xx_H
54 
55 #ifdef __cplusplus
56  extern "C" {
57 #endif /* __cplusplus */
58 
67 typedef enum
68 {
69 /****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/
70  NonMaskableInt_IRQn = -14,
71  MemoryManagement_IRQn = -12,
72  BusFault_IRQn = -11,
73  UsageFault_IRQn = -10,
74  SVCall_IRQn = -5,
75  DebugMonitor_IRQn = -4,
76  PendSV_IRQn = -2,
77  SysTick_IRQn = -1,
78 /****** STM32 specific Interrupt Numbers **********************************************************************/
79  WWDG_IRQn = 0,
80  PVD_IRQn = 1,
81  TAMP_STAMP_IRQn = 2,
82  RTC_WKUP_IRQn = 3,
83  FLASH_IRQn = 4,
84  RCC_IRQn = 5,
85  EXTI0_IRQn = 6,
86  EXTI1_IRQn = 7,
87  EXTI2_IRQn = 8,
88  EXTI3_IRQn = 9,
89  EXTI4_IRQn = 10,
90  DMA1_Stream0_IRQn = 11,
91  DMA1_Stream1_IRQn = 12,
92  DMA1_Stream2_IRQn = 13,
93  DMA1_Stream3_IRQn = 14,
94  DMA1_Stream4_IRQn = 15,
95  DMA1_Stream5_IRQn = 16,
96  DMA1_Stream6_IRQn = 17,
97  ADC_IRQn = 18,
98  CAN1_TX_IRQn = 19,
99  CAN1_RX0_IRQn = 20,
100  CAN1_RX1_IRQn = 21,
101  CAN1_SCE_IRQn = 22,
102  EXTI9_5_IRQn = 23,
103  TIM1_BRK_TIM9_IRQn = 24,
104  TIM1_UP_TIM10_IRQn = 25,
105  TIM1_TRG_COM_TIM11_IRQn = 26,
106  TIM1_CC_IRQn = 27,
107  TIM2_IRQn = 28,
108  TIM3_IRQn = 29,
109  TIM4_IRQn = 30,
110  I2C1_EV_IRQn = 31,
111  I2C1_ER_IRQn = 32,
112  I2C2_EV_IRQn = 33,
113  I2C2_ER_IRQn = 34,
114  SPI1_IRQn = 35,
115  SPI2_IRQn = 36,
116  USART1_IRQn = 37,
117  USART2_IRQn = 38,
118  USART3_IRQn = 39,
119  EXTI15_10_IRQn = 40,
120  RTC_Alarm_IRQn = 41,
121  OTG_FS_WKUP_IRQn = 42,
122  TIM8_BRK_TIM12_IRQn = 43,
123  TIM8_UP_TIM13_IRQn = 44,
124  TIM8_TRG_COM_TIM14_IRQn = 45,
125  TIM8_CC_IRQn = 46,
126  DMA1_Stream7_IRQn = 47,
127  FMC_IRQn = 48,
128  SDMMC1_IRQn = 49,
129  TIM5_IRQn = 50,
130  SPI3_IRQn = 51,
131  UART4_IRQn = 52,
132  UART5_IRQn = 53,
133  TIM6_DAC_IRQn = 54,
134  TIM7_IRQn = 55,
135  DMA2_Stream0_IRQn = 56,
136  DMA2_Stream1_IRQn = 57,
137  DMA2_Stream2_IRQn = 58,
138  DMA2_Stream3_IRQn = 59,
139  DMA2_Stream4_IRQn = 60,
140  ETH_IRQn = 61,
141  ETH_WKUP_IRQn = 62,
142  CAN2_TX_IRQn = 63,
143  CAN2_RX0_IRQn = 64,
144  CAN2_RX1_IRQn = 65,
145  CAN2_SCE_IRQn = 66,
146  OTG_FS_IRQn = 67,
147  DMA2_Stream5_IRQn = 68,
148  DMA2_Stream6_IRQn = 69,
149  DMA2_Stream7_IRQn = 70,
150  USART6_IRQn = 71,
151  I2C3_EV_IRQn = 72,
152  I2C3_ER_IRQn = 73,
153  OTG_HS_EP1_OUT_IRQn = 74,
154  OTG_HS_EP1_IN_IRQn = 75,
155  OTG_HS_WKUP_IRQn = 76,
156  OTG_HS_IRQn = 77,
157  DCMI_IRQn = 78,
158  RNG_IRQn = 80,
159  FPU_IRQn = 81,
160  UART7_IRQn = 82,
161  UART8_IRQn = 83,
162  SPI4_IRQn = 84,
163  SPI5_IRQn = 85,
164  SPI6_IRQn = 86,
165  SAI1_IRQn = 87,
166  DMA2D_IRQn = 90,
167  SAI2_IRQn = 91,
168  QUADSPI_IRQn = 92,
169  LPTIM1_IRQn = 93,
170  CEC_IRQn = 94,
171  I2C4_EV_IRQn = 95,
172  I2C4_ER_IRQn = 96,
173  SPDIF_RX_IRQn = 97,
174  DFSDM1_FLT0_IRQn = 99,
175  DFSDM1_FLT1_IRQn = 100,
176  DFSDM1_FLT2_IRQn = 101,
177  DFSDM1_FLT3_IRQn = 102,
178  SDMMC2_IRQn = 103,
179  CAN3_TX_IRQn = 104,
180  CAN3_RX0_IRQn = 105,
181  CAN3_RX1_IRQn = 106,
182  CAN3_SCE_IRQn = 107,
183  MDIOS_IRQn = 109
184 } IRQn_Type;
185 
193 #define __CM7_REV 0x0100U
194 #define __MPU_PRESENT 1
195 #define __NVIC_PRIO_BITS 4
196 #define __Vendor_SysTickConfig 0
197 #define __FPU_PRESENT 1
198 #define __ICACHE_PRESENT 1
199 #define __DCACHE_PRESENT 1
200 #include "core_cm7.h"
203 #include "system_stm32f7xx.h"
204 #include <stdint.h>
205 
214 typedef struct
215 {
216  __IO uint32_t SR;
217  __IO uint32_t CR1;
218  __IO uint32_t CR2;
219  __IO uint32_t SMPR1;
220  __IO uint32_t SMPR2;
221  __IO uint32_t JOFR1;
222  __IO uint32_t JOFR2;
223  __IO uint32_t JOFR3;
224  __IO uint32_t JOFR4;
225  __IO uint32_t HTR;
226  __IO uint32_t LTR;
227  __IO uint32_t SQR1;
228  __IO uint32_t SQR2;
229  __IO uint32_t SQR3;
230  __IO uint32_t JSQR;
231  __IO uint32_t JDR1;
232  __IO uint32_t JDR2;
233  __IO uint32_t JDR3;
234  __IO uint32_t JDR4;
235  __IO uint32_t DR;
236 } ADC_TypeDef;
237 
238 typedef struct
239 {
240  __IO uint32_t CSR;
241  __IO uint32_t CCR;
242  __IO uint32_t CDR;
244 } ADC_Common_TypeDef;
245 
246 
251 typedef struct
252 {
253  __IO uint32_t TIR;
254  __IO uint32_t TDTR;
255  __IO uint32_t TDLR;
256  __IO uint32_t TDHR;
257 } CAN_TxMailBox_TypeDef;
258 
263 typedef struct
264 {
265  __IO uint32_t RIR;
266  __IO uint32_t RDTR;
267  __IO uint32_t RDLR;
268  __IO uint32_t RDHR;
269 } CAN_FIFOMailBox_TypeDef;
270 
275 typedef struct
276 {
277  __IO uint32_t FR1;
278  __IO uint32_t FR2;
279 } CAN_FilterRegister_TypeDef;
280 
285 typedef struct
286 {
287  __IO uint32_t MCR;
288  __IO uint32_t MSR;
289  __IO uint32_t TSR;
290  __IO uint32_t RF0R;
291  __IO uint32_t RF1R;
292  __IO uint32_t IER;
293  __IO uint32_t ESR;
294  __IO uint32_t BTR;
295  uint32_t RESERVED0[88];
296  CAN_TxMailBox_TypeDef sTxMailBox[3];
297  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
298  uint32_t RESERVED1[12];
299  __IO uint32_t FMR;
300  __IO uint32_t FM1R;
301  uint32_t RESERVED2;
302  __IO uint32_t FS1R;
303  uint32_t RESERVED3;
304  __IO uint32_t FFA1R;
305  uint32_t RESERVED4;
306  __IO uint32_t FA1R;
307  uint32_t RESERVED5[8];
308  CAN_FilterRegister_TypeDef sFilterRegister[28];
309 } CAN_TypeDef;
310 
315 typedef struct
316 {
317  __IO uint32_t CR;
318  __IO uint32_t CFGR;
319  __IO uint32_t TXDR;
320  __IO uint32_t RXDR;
321  __IO uint32_t ISR;
322  __IO uint32_t IER;
323 }CEC_TypeDef;
324 
325 
330 typedef struct
331 {
332  __IO uint32_t DR;
333  __IO uint8_t IDR;
334  uint8_t RESERVED0;
335  uint16_t RESERVED1;
336  __IO uint32_t CR;
337  uint32_t RESERVED2;
338  __IO uint32_t INIT;
339  __IO uint32_t POL;
340 } CRC_TypeDef;
341 
346 typedef struct
347 {
348  __IO uint32_t CR;
349  __IO uint32_t SWTRIGR;
350  __IO uint32_t DHR12R1;
351  __IO uint32_t DHR12L1;
352  __IO uint32_t DHR8R1;
353  __IO uint32_t DHR12R2;
354  __IO uint32_t DHR12L2;
355  __IO uint32_t DHR8R2;
356  __IO uint32_t DHR12RD;
357  __IO uint32_t DHR12LD;
358  __IO uint32_t DHR8RD;
359  __IO uint32_t DOR1;
360  __IO uint32_t DOR2;
361  __IO uint32_t SR;
362 } DAC_TypeDef;
363 
367 typedef struct
368 {
369  __IO uint32_t FLTCR1;
370  __IO uint32_t FLTCR2;
371  __IO uint32_t FLTISR;
372  __IO uint32_t FLTICR;
373  __IO uint32_t FLTJCHGR;
374  __IO uint32_t FLTFCR;
375  __IO uint32_t FLTJDATAR;
376  __IO uint32_t FLTRDATAR;
377  __IO uint32_t FLTAWHTR;
378  __IO uint32_t FLTAWLTR;
379  __IO uint32_t FLTAWSR;
380  __IO uint32_t FLTAWCFR;
381  __IO uint32_t FLTEXMAX;
382  __IO uint32_t FLTEXMIN;
383  __IO uint32_t FLTCNVTIMR;
384 } DFSDM_Filter_TypeDef;
385 
389 typedef struct
390 {
391  __IO uint32_t CHCFGR1;
392  __IO uint32_t CHCFGR2;
393  __IO uint32_t CHAWSCDR;
395  __IO uint32_t CHWDATAR;
396  __IO uint32_t CHDATINR;
397 } DFSDM_Channel_TypeDef;
398 
403 typedef struct
404 {
405  __IO uint32_t IDCODE;
406  __IO uint32_t CR;
407  __IO uint32_t APB1FZ;
408  __IO uint32_t APB2FZ;
409 }DBGMCU_TypeDef;
410 
415 typedef struct
416 {
417  __IO uint32_t CR;
418  __IO uint32_t SR;
419  __IO uint32_t RISR;
420  __IO uint32_t IER;
421  __IO uint32_t MISR;
422  __IO uint32_t ICR;
423  __IO uint32_t ESCR;
424  __IO uint32_t ESUR;
425  __IO uint32_t CWSTRTR;
426  __IO uint32_t CWSIZER;
427  __IO uint32_t DR;
428 } DCMI_TypeDef;
429 
434 typedef struct
435 {
436  __IO uint32_t CR;
437  __IO uint32_t NDTR;
438  __IO uint32_t PAR;
439  __IO uint32_t M0AR;
440  __IO uint32_t M1AR;
441  __IO uint32_t FCR;
442 } DMA_Stream_TypeDef;
443 
444 typedef struct
445 {
446  __IO uint32_t LISR;
447  __IO uint32_t HISR;
448  __IO uint32_t LIFCR;
449  __IO uint32_t HIFCR;
450 } DMA_TypeDef;
451 
452 
457 typedef struct
458 {
459  __IO uint32_t CR;
460  __IO uint32_t ISR;
461  __IO uint32_t IFCR;
462  __IO uint32_t FGMAR;
463  __IO uint32_t FGOR;
464  __IO uint32_t BGMAR;
465  __IO uint32_t BGOR;
466  __IO uint32_t FGPFCCR;
467  __IO uint32_t FGCOLR;
468  __IO uint32_t BGPFCCR;
469  __IO uint32_t BGCOLR;
470  __IO uint32_t FGCMAR;
471  __IO uint32_t BGCMAR;
472  __IO uint32_t OPFCCR;
473  __IO uint32_t OCOLR;
474  __IO uint32_t OMAR;
475  __IO uint32_t OOR;
476  __IO uint32_t NLR;
477  __IO uint32_t LWR;
478  __IO uint32_t AMTCR;
479  uint32_t RESERVED[236];
480  __IO uint32_t FGCLUT[256];
481  __IO uint32_t BGCLUT[256];
482 } DMA2D_TypeDef;
483 
484 
489 typedef struct
490 {
491  __IO uint32_t MACCR;
492  __IO uint32_t MACFFR;
493  __IO uint32_t MACHTHR;
494  __IO uint32_t MACHTLR;
495  __IO uint32_t MACMIIAR;
496  __IO uint32_t MACMIIDR;
497  __IO uint32_t MACFCR;
498  __IO uint32_t MACVLANTR; /* 8 */
499  uint32_t RESERVED0[2];
500  __IO uint32_t MACRWUFFR; /* 11 */
501  __IO uint32_t MACPMTCSR;
502  uint32_t RESERVED1[2];
503  __IO uint32_t MACSR; /* 15 */
504  __IO uint32_t MACIMR;
505  __IO uint32_t MACA0HR;
506  __IO uint32_t MACA0LR;
507  __IO uint32_t MACA1HR;
508  __IO uint32_t MACA1LR;
509  __IO uint32_t MACA2HR;
510  __IO uint32_t MACA2LR;
511  __IO uint32_t MACA3HR;
512  __IO uint32_t MACA3LR; /* 24 */
513  uint32_t RESERVED2[40];
514  __IO uint32_t MMCCR; /* 65 */
515  __IO uint32_t MMCRIR;
516  __IO uint32_t MMCTIR;
517  __IO uint32_t MMCRIMR;
518  __IO uint32_t MMCTIMR; /* 69 */
519  uint32_t RESERVED3[14];
520  __IO uint32_t MMCTGFSCCR; /* 84 */
521  __IO uint32_t MMCTGFMSCCR;
522  uint32_t RESERVED4[5];
523  __IO uint32_t MMCTGFCR;
524  uint32_t RESERVED5[10];
525  __IO uint32_t MMCRFCECR;
526  __IO uint32_t MMCRFAECR;
527  uint32_t RESERVED6[10];
528  __IO uint32_t MMCRGUFCR;
529  uint32_t RESERVED7[334];
530  __IO uint32_t PTPTSCR;
531  __IO uint32_t PTPSSIR;
532  __IO uint32_t PTPTSHR;
533  __IO uint32_t PTPTSLR;
534  __IO uint32_t PTPTSHUR;
535  __IO uint32_t PTPTSLUR;
536  __IO uint32_t PTPTSAR;
537  __IO uint32_t PTPTTHR;
538  __IO uint32_t PTPTTLR;
539  __IO uint32_t RESERVED8;
540  __IO uint32_t PTPTSSR;
541  uint32_t RESERVED9[565];
542  __IO uint32_t DMABMR;
543  __IO uint32_t DMATPDR;
544  __IO uint32_t DMARPDR;
545  __IO uint32_t DMARDLAR;
546  __IO uint32_t DMATDLAR;
547  __IO uint32_t DMASR;
548  __IO uint32_t DMAOMR;
549  __IO uint32_t DMAIER;
550  __IO uint32_t DMAMFBOCR;
551  __IO uint32_t DMARSWTR;
552  uint32_t RESERVED10[8];
553  __IO uint32_t DMACHTDR;
554  __IO uint32_t DMACHRDR;
555  __IO uint32_t DMACHTBAR;
556  __IO uint32_t DMACHRBAR;
557 } ETH_TypeDef;
558 
563 typedef struct
564 {
565  __IO uint32_t IMR;
566  __IO uint32_t EMR;
567  __IO uint32_t RTSR;
568  __IO uint32_t FTSR;
569  __IO uint32_t SWIER;
570  __IO uint32_t PR;
571 } EXTI_TypeDef;
572 
577 typedef struct
578 {
579  __IO uint32_t ACR;
580  __IO uint32_t KEYR;
581  __IO uint32_t OPTKEYR;
582  __IO uint32_t SR;
583  __IO uint32_t CR;
584  __IO uint32_t OPTCR;
585  __IO uint32_t OPTCR1;
586 } FLASH_TypeDef;
587 
588 
589 
594 typedef struct
595 {
596  __IO uint32_t BTCR[8];
597 } FMC_Bank1_TypeDef;
598 
603 typedef struct
604 {
605  __IO uint32_t BWTR[7];
606 } FMC_Bank1E_TypeDef;
607 
612 typedef struct
613 {
614  __IO uint32_t PCR;
615  __IO uint32_t SR;
616  __IO uint32_t PMEM;
617  __IO uint32_t PATT;
618  uint32_t RESERVED0;
619  __IO uint32_t ECCR;
620 } FMC_Bank3_TypeDef;
621 
626 typedef struct
627 {
628  __IO uint32_t SDCR[2];
629  __IO uint32_t SDTR[2];
630  __IO uint32_t SDCMR;
631  __IO uint32_t SDRTR;
632  __IO uint32_t SDSR;
633 } FMC_Bank5_6_TypeDef;
634 
635 
640 typedef struct
641 {
642  __IO uint32_t MODER;
643  __IO uint32_t OTYPER;
644  __IO uint32_t OSPEEDR;
645  __IO uint32_t PUPDR;
646  __IO uint32_t IDR;
647  __IO uint32_t ODR;
648  __IO uint32_t BSRR;
649  __IO uint32_t LCKR;
650  __IO uint32_t AFR[2];
651 } GPIO_TypeDef;
652 
657 typedef struct
658 {
659  __IO uint32_t MEMRMP;
660  __IO uint32_t PMC;
661  __IO uint32_t EXTICR[4];
662  uint32_t RESERVED;
663  __IO uint32_t CBR;
664  __IO uint32_t CMPCR;
665 } SYSCFG_TypeDef;
666 
671 typedef struct
672 {
673  __IO uint32_t CR1;
674  __IO uint32_t CR2;
675  __IO uint32_t OAR1;
676  __IO uint32_t OAR2;
677  __IO uint32_t TIMINGR;
678  __IO uint32_t TIMEOUTR;
679  __IO uint32_t ISR;
680  __IO uint32_t ICR;
681  __IO uint32_t PECR;
682  __IO uint32_t RXDR;
683  __IO uint32_t TXDR;
684 } I2C_TypeDef;
685 
690 typedef struct
691 {
692  __IO uint32_t KR;
693  __IO uint32_t PR;
694  __IO uint32_t RLR;
695  __IO uint32_t SR;
696  __IO uint32_t WINR;
697 } IWDG_TypeDef;
698 
699 
700 
705 typedef struct
706 {
707  __IO uint32_t CR1;
708  __IO uint32_t CSR1;
709  __IO uint32_t CR2;
710  __IO uint32_t CSR2;
711 } PWR_TypeDef;
712 
713 
718 typedef struct
719 {
720  __IO uint32_t CR;
721  __IO uint32_t PLLCFGR;
722  __IO uint32_t CFGR;
723  __IO uint32_t CIR;
724  __IO uint32_t AHB1RSTR;
725  __IO uint32_t AHB2RSTR;
726  __IO uint32_t AHB3RSTR;
727  uint32_t RESERVED0;
728  __IO uint32_t APB1RSTR;
729  __IO uint32_t APB2RSTR;
730  uint32_t RESERVED1[2];
731  __IO uint32_t AHB1ENR;
732  __IO uint32_t AHB2ENR;
733  __IO uint32_t AHB3ENR;
734  uint32_t RESERVED2;
735  __IO uint32_t APB1ENR;
736  __IO uint32_t APB2ENR;
737  uint32_t RESERVED3[2];
738  __IO uint32_t AHB1LPENR;
739  __IO uint32_t AHB2LPENR;
740  __IO uint32_t AHB3LPENR;
741  uint32_t RESERVED4;
742  __IO uint32_t APB1LPENR;
743  __IO uint32_t APB2LPENR;
744  uint32_t RESERVED5[2];
745  __IO uint32_t BDCR;
746  __IO uint32_t CSR;
747  uint32_t RESERVED6[2];
748  __IO uint32_t SSCGR;
749  __IO uint32_t PLLI2SCFGR;
750  __IO uint32_t PLLSAICFGR;
751  __IO uint32_t DCKCFGR1;
752  __IO uint32_t DCKCFGR2;
754 } RCC_TypeDef;
755 
760 typedef struct
761 {
762  __IO uint32_t TR;
763  __IO uint32_t DR;
764  __IO uint32_t CR;
765  __IO uint32_t ISR;
766  __IO uint32_t PRER;
767  __IO uint32_t WUTR;
768  uint32_t reserved;
769  __IO uint32_t ALRMAR;
770  __IO uint32_t ALRMBR;
771  __IO uint32_t WPR;
772  __IO uint32_t SSR;
773  __IO uint32_t SHIFTR;
774  __IO uint32_t TSTR;
775  __IO uint32_t TSDR;
776  __IO uint32_t TSSSR;
777  __IO uint32_t CALR;
778  __IO uint32_t TAMPCR;
779  __IO uint32_t ALRMASSR;
780  __IO uint32_t ALRMBSSR;
781  __IO uint32_t OR;
782  __IO uint32_t BKP0R;
783  __IO uint32_t BKP1R;
784  __IO uint32_t BKP2R;
785  __IO uint32_t BKP3R;
786  __IO uint32_t BKP4R;
787  __IO uint32_t BKP5R;
788  __IO uint32_t BKP6R;
789  __IO uint32_t BKP7R;
790  __IO uint32_t BKP8R;
791  __IO uint32_t BKP9R;
792  __IO uint32_t BKP10R;
793  __IO uint32_t BKP11R;
794  __IO uint32_t BKP12R;
795  __IO uint32_t BKP13R;
796  __IO uint32_t BKP14R;
797  __IO uint32_t BKP15R;
798  __IO uint32_t BKP16R;
799  __IO uint32_t BKP17R;
800  __IO uint32_t BKP18R;
801  __IO uint32_t BKP19R;
802  __IO uint32_t BKP20R;
803  __IO uint32_t BKP21R;
804  __IO uint32_t BKP22R;
805  __IO uint32_t BKP23R;
806  __IO uint32_t BKP24R;
807  __IO uint32_t BKP25R;
808  __IO uint32_t BKP26R;
809  __IO uint32_t BKP27R;
810  __IO uint32_t BKP28R;
811  __IO uint32_t BKP29R;
812  __IO uint32_t BKP30R;
813  __IO uint32_t BKP31R;
814 } RTC_TypeDef;
815 
816 
821 typedef struct
822 {
823  __IO uint32_t GCR;
824 } SAI_TypeDef;
825 
826 typedef struct
827 {
828  __IO uint32_t CR1;
829  __IO uint32_t CR2;
830  __IO uint32_t FRCR;
831  __IO uint32_t SLOTR;
832  __IO uint32_t IMR;
833  __IO uint32_t SR;
834  __IO uint32_t CLRFR;
835  __IO uint32_t DR;
836 } SAI_Block_TypeDef;
837 
842 typedef struct
843 {
844  __IO uint32_t CR;
845  __IO uint32_t IMR;
846  __IO uint32_t SR;
847  __IO uint32_t IFCR;
848  __IO uint32_t DR;
849  __IO uint32_t CSR;
850  __IO uint32_t DIR;
851 } SPDIFRX_TypeDef;
852 
853 
858 typedef struct
859 {
860  __IO uint32_t POWER;
861  __IO uint32_t CLKCR;
862  __IO uint32_t ARG;
863  __IO uint32_t CMD;
864  __I uint32_t RESPCMD;
865  __I uint32_t RESP1;
866  __I uint32_t RESP2;
867  __I uint32_t RESP3;
868  __I uint32_t RESP4;
869  __IO uint32_t DTIMER;
870  __IO uint32_t DLEN;
871  __IO uint32_t DCTRL;
872  __I uint32_t DCOUNT;
873  __I uint32_t STA;
874  __IO uint32_t ICR;
875  __IO uint32_t MASK;
876  uint32_t RESERVED0[2];
877  __I uint32_t FIFOCNT;
878  uint32_t RESERVED1[13];
879  __IO uint32_t FIFO;
880 } SDMMC_TypeDef;
881 
886 typedef struct
887 {
888  __IO uint32_t CR1;
889  __IO uint32_t CR2;
890  __IO uint32_t SR;
891  __IO uint32_t DR;
892  __IO uint32_t CRCPR;
893  __IO uint32_t RXCRCR;
894  __IO uint32_t TXCRCR;
895  __IO uint32_t I2SCFGR;
896  __IO uint32_t I2SPR;
897 } SPI_TypeDef;
898 
903 typedef struct
904 {
905  __IO uint32_t CR;
906  __IO uint32_t DCR;
907  __IO uint32_t SR;
908  __IO uint32_t FCR;
909  __IO uint32_t DLR;
910  __IO uint32_t CCR;
911  __IO uint32_t AR;
912  __IO uint32_t ABR;
913  __IO uint32_t DR;
914  __IO uint32_t PSMKR;
915  __IO uint32_t PSMAR;
916  __IO uint32_t PIR;
917  __IO uint32_t LPTR;
918 } QUADSPI_TypeDef;
919 
924 typedef struct
925 {
926  __IO uint32_t CR1;
927  __IO uint32_t CR2;
928  __IO uint32_t SMCR;
929  __IO uint32_t DIER;
930  __IO uint32_t SR;
931  __IO uint32_t EGR;
932  __IO uint32_t CCMR1;
933  __IO uint32_t CCMR2;
934  __IO uint32_t CCER;
935  __IO uint32_t CNT;
936  __IO uint32_t PSC;
937  __IO uint32_t ARR;
938  __IO uint32_t RCR;
939  __IO uint32_t CCR1;
940  __IO uint32_t CCR2;
941  __IO uint32_t CCR3;
942  __IO uint32_t CCR4;
943  __IO uint32_t BDTR;
944  __IO uint32_t DCR;
945  __IO uint32_t DMAR;
946  __IO uint32_t OR;
947  __IO uint32_t CCMR3;
948  __IO uint32_t CCR5;
949  __IO uint32_t CCR6;
950  __IO uint32_t AF1;
951  __IO uint32_t AF2;
953 } TIM_TypeDef;
954 
958 typedef struct
959 {
960  __IO uint32_t ISR;
961  __IO uint32_t ICR;
962  __IO uint32_t IER;
963  __IO uint32_t CFGR;
964  __IO uint32_t CR;
965  __IO uint32_t CMP;
966  __IO uint32_t ARR;
967  __IO uint32_t CNT;
968 } LPTIM_TypeDef;
969 
970 
975 typedef struct
976 {
977  __IO uint32_t CR1;
978  __IO uint32_t CR2;
979  __IO uint32_t CR3;
980  __IO uint32_t BRR;
981  __IO uint32_t GTPR;
982  __IO uint32_t RTOR;
983  __IO uint32_t RQR;
984  __IO uint32_t ISR;
985  __IO uint32_t ICR;
986  __IO uint32_t RDR;
987  __IO uint32_t TDR;
988 } USART_TypeDef;
989 
990 
995 typedef struct
996 {
997  __IO uint32_t CR;
998  __IO uint32_t CFR;
999  __IO uint32_t SR;
1000 } WWDG_TypeDef;
1001 
1002 
1007 typedef struct
1008 {
1009  __IO uint32_t CR;
1010  __IO uint32_t SR;
1011  __IO uint32_t DR;
1012 } RNG_TypeDef;
1013 
1021 typedef struct
1022 {
1023  __IO uint32_t GOTGCTL;
1024  __IO uint32_t GOTGINT;
1025  __IO uint32_t GAHBCFG;
1026  __IO uint32_t GUSBCFG;
1027  __IO uint32_t GRSTCTL;
1028  __IO uint32_t GINTSTS;
1029  __IO uint32_t GINTMSK;
1030  __IO uint32_t GRXSTSR;
1031  __IO uint32_t GRXSTSP;
1032  __IO uint32_t GRXFSIZ;
1033  __IO uint32_t DIEPTXF0_HNPTXFSIZ;
1034  __IO uint32_t HNPTXSTS;
1035  uint32_t Reserved30[2];
1036  __IO uint32_t GCCFG;
1037  __IO uint32_t CID;
1038  uint32_t Reserved5[3];
1039  __IO uint32_t GHWCFG3;
1040  uint32_t Reserved6;
1041  __IO uint32_t GLPMCFG;
1042  __IO uint32_t GPWRDN;
1043  __IO uint32_t GDFIFOCFG;
1044  __IO uint32_t GADPCTL;
1045  uint32_t Reserved43[39];
1046  __IO uint32_t HPTXFSIZ;
1047  __IO uint32_t DIEPTXF[0x0F];
1048 } USB_OTG_GlobalTypeDef;
1049 
1050 
1054 typedef struct
1055 {
1056  __IO uint32_t DCFG;
1057  __IO uint32_t DCTL;
1058  __IO uint32_t DSTS;
1059  uint32_t Reserved0C;
1060  __IO uint32_t DIEPMSK;
1061  __IO uint32_t DOEPMSK;
1062  __IO uint32_t DAINT;
1063  __IO uint32_t DAINTMSK;
1064  uint32_t Reserved20;
1065  uint32_t Reserved9;
1066  __IO uint32_t DVBUSDIS;
1067  __IO uint32_t DVBUSPULSE;
1068  __IO uint32_t DTHRCTL;
1069  __IO uint32_t DIEPEMPMSK;
1070  __IO uint32_t DEACHINT;
1071  __IO uint32_t DEACHMSK;
1072  uint32_t Reserved40;
1073  __IO uint32_t DINEP1MSK;
1074  uint32_t Reserved44[15];
1075  __IO uint32_t DOUTEP1MSK;
1076 } USB_OTG_DeviceTypeDef;
1077 
1078 
1082 typedef struct
1083 {
1084  __IO uint32_t DIEPCTL;
1085  uint32_t Reserved04;
1086  __IO uint32_t DIEPINT;
1087  uint32_t Reserved0C;
1088  __IO uint32_t DIEPTSIZ;
1089  __IO uint32_t DIEPDMA;
1090  __IO uint32_t DTXFSTS;
1091  uint32_t Reserved18;
1092 } USB_OTG_INEndpointTypeDef;
1093 
1094 
1098 typedef struct
1099 {
1100  __IO uint32_t DOEPCTL;
1101  uint32_t Reserved04;
1102  __IO uint32_t DOEPINT;
1103  uint32_t Reserved0C;
1104  __IO uint32_t DOEPTSIZ;
1105  __IO uint32_t DOEPDMA;
1106  uint32_t Reserved18[2];
1107 } USB_OTG_OUTEndpointTypeDef;
1108 
1109 
1113 typedef struct
1114 {
1115  __IO uint32_t HCFG;
1116  __IO uint32_t HFIR;
1117  __IO uint32_t HFNUM;
1118  uint32_t Reserved40C;
1119  __IO uint32_t HPTXSTS;
1120  __IO uint32_t HAINT;
1121  __IO uint32_t HAINTMSK;
1122 } USB_OTG_HostTypeDef;
1123 
1127 typedef struct
1128 {
1129  __IO uint32_t HCCHAR;
1130  __IO uint32_t HCSPLT;
1131  __IO uint32_t HCINT;
1132  __IO uint32_t HCINTMSK;
1133  __IO uint32_t HCTSIZ;
1134  __IO uint32_t HCDMA;
1135  uint32_t Reserved[2];
1136 } USB_OTG_HostChannelTypeDef;
1146 typedef struct
1147 {
1148  __IO uint32_t CR;
1149  __IO uint32_t WRFR;
1150  __IO uint32_t CWRFR;
1151  __IO uint32_t RDFR;
1152  __IO uint32_t CRDFR;
1153  __IO uint32_t SR;
1154  __IO uint32_t CLRFR;
1155  uint32_t RESERVED0[57]; /* Reserved Address offset: 1Ch */
1156  __IO uint32_t DINR0;
1157  __IO uint32_t DINR1;
1158  __IO uint32_t DINR2;
1159  __IO uint32_t DINR3;
1160  __IO uint32_t DINR4;
1161  __IO uint32_t DINR5;
1162  __IO uint32_t DINR6;
1163  __IO uint32_t DINR7;
1164  __IO uint32_t DINR8;
1165  __IO uint32_t DINR9;
1166  __IO uint32_t DINR10;
1167  __IO uint32_t DINR11;
1168  __IO uint32_t DINR12;
1169  __IO uint32_t DINR13;
1170  __IO uint32_t DINR14;
1171  __IO uint32_t DINR15;
1172  __IO uint32_t DINR16;
1173  __IO uint32_t DINR17;
1174  __IO uint32_t DINR18;
1175  __IO uint32_t DINR19;
1176  __IO uint32_t DINR20;
1177  __IO uint32_t DINR21;
1178  __IO uint32_t DINR22;
1179  __IO uint32_t DINR23;
1180  __IO uint32_t DINR24;
1181  __IO uint32_t DINR25;
1182  __IO uint32_t DINR26;
1183  __IO uint32_t DINR27;
1184  __IO uint32_t DINR28;
1185  __IO uint32_t DINR29;
1186  __IO uint32_t DINR30;
1187  __IO uint32_t DINR31;
1188  __IO uint32_t DOUTR0;
1189  __IO uint32_t DOUTR1;
1190  __IO uint32_t DOUTR2;
1191  __IO uint32_t DOUTR3;
1192  __IO uint32_t DOUTR4;
1193  __IO uint32_t DOUTR5;
1194  __IO uint32_t DOUTR6;
1195  __IO uint32_t DOUTR7;
1196  __IO uint32_t DOUTR8;
1197  __IO uint32_t DOUTR9;
1198  __IO uint32_t DOUTR10;
1199  __IO uint32_t DOUTR11;
1200  __IO uint32_t DOUTR12;
1201  __IO uint32_t DOUTR13;
1202  __IO uint32_t DOUTR14;
1203  __IO uint32_t DOUTR15;
1204  __IO uint32_t DOUTR16;
1205  __IO uint32_t DOUTR17;
1206  __IO uint32_t DOUTR18;
1207  __IO uint32_t DOUTR19;
1208  __IO uint32_t DOUTR20;
1209  __IO uint32_t DOUTR21;
1210  __IO uint32_t DOUTR22;
1211  __IO uint32_t DOUTR23;
1212  __IO uint32_t DOUTR24;
1213  __IO uint32_t DOUTR25;
1214  __IO uint32_t DOUTR26;
1215  __IO uint32_t DOUTR27;
1216  __IO uint32_t DOUTR28;
1217  __IO uint32_t DOUTR29;
1218  __IO uint32_t DOUTR30;
1219  __IO uint32_t DOUTR31;
1220 } MDIOS_TypeDef;
1221 
1222 
1226 #define RAMITCM_BASE 0x00000000U
1227 #define FLASHITCM_BASE 0x00200000U
1228 #define FLASHAXI_BASE 0x08000000U
1229 #define RAMDTCM_BASE 0x20000000U
1230 #define PERIPH_BASE 0x40000000U
1231 #define BKPSRAM_BASE 0x40024000U
1232 #define QSPI_BASE 0x90000000U
1233 #define FMC_R_BASE 0xA0000000U
1234 #define QSPI_R_BASE 0xA0001000U
1235 #define SRAM1_BASE 0x20020000U
1236 #define SRAM2_BASE 0x2007C000U
1237 #define FLASH_END 0x081FFFFFU
1239 /* Legacy define */
1240 #define FLASH_BASE FLASHAXI_BASE
1241 
1243 #define APB1PERIPH_BASE PERIPH_BASE
1244 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
1245 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
1246 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
1247 
1249 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
1250 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
1251 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
1252 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
1253 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
1254 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
1255 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
1256 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
1257 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
1258 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
1259 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
1260 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
1261 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
1262 #define CAN3_BASE (APB1PERIPH_BASE + 0x3400U)
1263 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
1264 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
1265 #define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U)
1266 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
1267 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
1268 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
1269 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
1270 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
1271 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
1272 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
1273 #define I2C4_BASE (APB1PERIPH_BASE + 0x6000U)
1274 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
1275 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
1276 #define CEC_BASE (APB1PERIPH_BASE + 0x6C00U)
1277 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
1278 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
1279 #define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
1280 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
1281 
1283 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
1284 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
1285 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
1286 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
1287 #define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00U)
1288 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
1289 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
1290 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
1291 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
1292 #define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U)
1293 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1294 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
1295 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
1296 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
1297 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
1298 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
1299 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
1300 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
1301 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
1302 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
1303 #define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U)
1304 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
1305 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
1306 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004U)
1307 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024U)
1308 #define DFSDM1_BASE (APB2PERIPH_BASE + 0x7400U)
1309 #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U)
1310 #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U)
1311 #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U)
1312 #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U)
1313 #define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80U)
1314 #define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0U)
1315 #define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0U)
1316 #define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0U)
1317 #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U)
1318 #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)
1319 #define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200U)
1320 #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280U)
1321 #define MDIOS_BASE (APB2PERIPH_BASE + 0x7800U)
1322 
1323 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
1324 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
1325 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
1326 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
1327 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
1328 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
1329 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
1330 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
1331 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
1332 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
1333 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
1334 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1335 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
1336 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
1337 #define UID_BASE 0x1FF0F420U
1338 #define FLASHSIZE_BASE 0x1FF0F442U
1339 #define PACKAGESIZE_BASE 0x1FFF7BF0U
1340 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
1341 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
1342 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
1343 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
1344 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
1345 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
1346 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
1347 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
1348 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
1349 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
1350 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
1351 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
1352 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
1353 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
1354 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
1355 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
1356 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
1357 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
1358 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
1359 #define ETH_MAC_BASE (ETH_BASE)
1360 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
1361 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
1362 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
1363 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
1364 
1365 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
1366 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
1367 
1368 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
1369 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
1370 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
1371 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
1372 
1373 /* Debug MCU registers base address */
1374 #define DBGMCU_BASE 0xE0042000U
1375 
1377 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
1378 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
1379 
1380 #define USB_OTG_GLOBAL_BASE 0x000U
1381 #define USB_OTG_DEVICE_BASE 0x800U
1382 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
1383 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
1384 #define USB_OTG_EP_REG_SIZE 0x20U
1385 #define USB_OTG_HOST_BASE 0x400U
1386 #define USB_OTG_HOST_PORT_BASE 0x440U
1387 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
1388 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
1389 #define USB_OTG_PCGCCTL_BASE 0xE00U
1390 #define USB_OTG_FIFO_BASE 0x1000U
1391 #define USB_OTG_FIFO_SIZE 0x1000U
1392 
1400 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1401 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1402 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1403 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1404 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1405 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1406 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1407 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1408 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1409 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1410 #define RTC ((RTC_TypeDef *) RTC_BASE)
1411 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1412 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1413 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1414 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1415 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
1416 #define USART2 ((USART_TypeDef *) USART2_BASE)
1417 #define USART3 ((USART_TypeDef *) USART3_BASE)
1418 #define UART4 ((USART_TypeDef *) UART4_BASE)
1419 #define UART5 ((USART_TypeDef *) UART5_BASE)
1420 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1421 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1422 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1423 #define I2C4 ((I2C_TypeDef *) I2C4_BASE)
1424 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1425 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1426 #define CEC ((CEC_TypeDef *) CEC_BASE)
1427 #define PWR ((PWR_TypeDef *) PWR_BASE)
1428 #define DAC ((DAC_TypeDef *) DAC_BASE)
1429 #define UART7 ((USART_TypeDef *) UART7_BASE)
1430 #define UART8 ((USART_TypeDef *) UART8_BASE)
1431 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1432 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1433 #define USART1 ((USART_TypeDef *) USART1_BASE)
1434 #define USART6 ((USART_TypeDef *) USART6_BASE)
1435 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1436 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1437 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1438 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1439 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
1440 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1441 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1442 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1443 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1444 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1445 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1446 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1447 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1448 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
1449 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1450 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
1451 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1452 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1453 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
1454 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
1455 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1456 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1457 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1458 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1459 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1460 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1461 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1462 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1463 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1464 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
1465 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
1466 #define CRC ((CRC_TypeDef *) CRC_BASE)
1467 #define RCC ((RCC_TypeDef *) RCC_BASE)
1468 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1469 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1470 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1471 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1472 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1473 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1474 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1475 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1476 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1477 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1478 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1479 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1480 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1481 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1482 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1483 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1484 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1485 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1486 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1487 #define ETH ((ETH_TypeDef *) ETH_BASE)
1488 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1489 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1490 #define RNG ((RNG_TypeDef *) RNG_BASE)
1491 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1492 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1493 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1494 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1495 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1496 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1497 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1498 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1499 #define CAN3 ((CAN_TypeDef *) CAN3_BASE)
1500 #define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
1501 #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
1502 #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
1503 #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
1504 #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
1505 #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
1506 #define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
1507 #define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
1508 #define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
1509 #define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
1510 #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
1511 #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
1512 #define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
1513 #define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
1514 
1527 /******************************************************************************/
1528 /* Peripheral Registers_Bits_Definition */
1529 /******************************************************************************/
1530 
1531 /******************************************************************************/
1532 /* */
1533 /* Analog to Digital Converter */
1534 /* */
1535 /******************************************************************************/
1536 /******************** Bit definition for ADC_SR register ********************/
1537 #define ADC_SR_AWD 0x00000001U
1538 #define ADC_SR_EOC 0x00000002U
1539 #define ADC_SR_JEOC 0x00000004U
1540 #define ADC_SR_JSTRT 0x00000008U
1541 #define ADC_SR_STRT 0x00000010U
1542 #define ADC_SR_OVR 0x00000020U
1544 /******************* Bit definition for ADC_CR1 register ********************/
1545 #define ADC_CR1_AWDCH 0x0000001FU
1546 #define ADC_CR1_AWDCH_0 0x00000001U
1547 #define ADC_CR1_AWDCH_1 0x00000002U
1548 #define ADC_CR1_AWDCH_2 0x00000004U
1549 #define ADC_CR1_AWDCH_3 0x00000008U
1550 #define ADC_CR1_AWDCH_4 0x00000010U
1551 #define ADC_CR1_EOCIE 0x00000020U
1552 #define ADC_CR1_AWDIE 0x00000040U
1553 #define ADC_CR1_JEOCIE 0x00000080U
1554 #define ADC_CR1_SCAN 0x00000100U
1555 #define ADC_CR1_AWDSGL 0x00000200U
1556 #define ADC_CR1_JAUTO 0x00000400U
1557 #define ADC_CR1_DISCEN 0x00000800U
1558 #define ADC_CR1_JDISCEN 0x00001000U
1559 #define ADC_CR1_DISCNUM 0x0000E000U
1560 #define ADC_CR1_DISCNUM_0 0x00002000U
1561 #define ADC_CR1_DISCNUM_1 0x00004000U
1562 #define ADC_CR1_DISCNUM_2 0x00008000U
1563 #define ADC_CR1_JAWDEN 0x00400000U
1564 #define ADC_CR1_AWDEN 0x00800000U
1565 #define ADC_CR1_RES 0x03000000U
1566 #define ADC_CR1_RES_0 0x01000000U
1567 #define ADC_CR1_RES_1 0x02000000U
1568 #define ADC_CR1_OVRIE 0x04000000U
1570 /******************* Bit definition for ADC_CR2 register ********************/
1571 #define ADC_CR2_ADON 0x00000001U
1572 #define ADC_CR2_CONT 0x00000002U
1573 #define ADC_CR2_DMA 0x00000100U
1574 #define ADC_CR2_DDS 0x00000200U
1575 #define ADC_CR2_EOCS 0x00000400U
1576 #define ADC_CR2_ALIGN 0x00000800U
1577 #define ADC_CR2_JEXTSEL 0x000F0000U
1578 #define ADC_CR2_JEXTSEL_0 0x00010000U
1579 #define ADC_CR2_JEXTSEL_1 0x00020000U
1580 #define ADC_CR2_JEXTSEL_2 0x00040000U
1581 #define ADC_CR2_JEXTSEL_3 0x00080000U
1582 #define ADC_CR2_JEXTEN 0x00300000U
1583 #define ADC_CR2_JEXTEN_0 0x00100000U
1584 #define ADC_CR2_JEXTEN_1 0x00200000U
1585 #define ADC_CR2_JSWSTART 0x00400000U
1586 #define ADC_CR2_EXTSEL 0x0F000000U
1587 #define ADC_CR2_EXTSEL_0 0x01000000U
1588 #define ADC_CR2_EXTSEL_1 0x02000000U
1589 #define ADC_CR2_EXTSEL_2 0x04000000U
1590 #define ADC_CR2_EXTSEL_3 0x08000000U
1591 #define ADC_CR2_EXTEN 0x30000000U
1592 #define ADC_CR2_EXTEN_0 0x10000000U
1593 #define ADC_CR2_EXTEN_1 0x20000000U
1594 #define ADC_CR2_SWSTART 0x40000000U
1596 /****************** Bit definition for ADC_SMPR1 register *******************/
1597 #define ADC_SMPR1_SMP10 0x00000007U
1598 #define ADC_SMPR1_SMP10_0 0x00000001U
1599 #define ADC_SMPR1_SMP10_1 0x00000002U
1600 #define ADC_SMPR1_SMP10_2 0x00000004U
1601 #define ADC_SMPR1_SMP11 0x00000038U
1602 #define ADC_SMPR1_SMP11_0 0x00000008U
1603 #define ADC_SMPR1_SMP11_1 0x00000010U
1604 #define ADC_SMPR1_SMP11_2 0x00000020U
1605 #define ADC_SMPR1_SMP12 0x000001C0U
1606 #define ADC_SMPR1_SMP12_0 0x00000040U
1607 #define ADC_SMPR1_SMP12_1 0x00000080U
1608 #define ADC_SMPR1_SMP12_2 0x00000100U
1609 #define ADC_SMPR1_SMP13 0x00000E00U
1610 #define ADC_SMPR1_SMP13_0 0x00000200U
1611 #define ADC_SMPR1_SMP13_1 0x00000400U
1612 #define ADC_SMPR1_SMP13_2 0x00000800U
1613 #define ADC_SMPR1_SMP14 0x00007000U
1614 #define ADC_SMPR1_SMP14_0 0x00001000U
1615 #define ADC_SMPR1_SMP14_1 0x00002000U
1616 #define ADC_SMPR1_SMP14_2 0x00004000U
1617 #define ADC_SMPR1_SMP15 0x00038000U
1618 #define ADC_SMPR1_SMP15_0 0x00008000U
1619 #define ADC_SMPR1_SMP15_1 0x00010000U
1620 #define ADC_SMPR1_SMP15_2 0x00020000U
1621 #define ADC_SMPR1_SMP16 0x001C0000U
1622 #define ADC_SMPR1_SMP16_0 0x00040000U
1623 #define ADC_SMPR1_SMP16_1 0x00080000U
1624 #define ADC_SMPR1_SMP16_2 0x00100000U
1625 #define ADC_SMPR1_SMP17 0x00E00000U
1626 #define ADC_SMPR1_SMP17_0 0x00200000U
1627 #define ADC_SMPR1_SMP17_1 0x00400000U
1628 #define ADC_SMPR1_SMP17_2 0x00800000U
1629 #define ADC_SMPR1_SMP18 0x07000000U
1630 #define ADC_SMPR1_SMP18_0 0x01000000U
1631 #define ADC_SMPR1_SMP18_1 0x02000000U
1632 #define ADC_SMPR1_SMP18_2 0x04000000U
1634 /****************** Bit definition for ADC_SMPR2 register *******************/
1635 #define ADC_SMPR2_SMP0 0x00000007U
1636 #define ADC_SMPR2_SMP0_0 0x00000001U
1637 #define ADC_SMPR2_SMP0_1 0x00000002U
1638 #define ADC_SMPR2_SMP0_2 0x00000004U
1639 #define ADC_SMPR2_SMP1 0x00000038U
1640 #define ADC_SMPR2_SMP1_0 0x00000008U
1641 #define ADC_SMPR2_SMP1_1 0x00000010U
1642 #define ADC_SMPR2_SMP1_2 0x00000020U
1643 #define ADC_SMPR2_SMP2 0x000001C0U
1644 #define ADC_SMPR2_SMP2_0 0x00000040U
1645 #define ADC_SMPR2_SMP2_1 0x00000080U
1646 #define ADC_SMPR2_SMP2_2 0x00000100U
1647 #define ADC_SMPR2_SMP3 0x00000E00U
1648 #define ADC_SMPR2_SMP3_0 0x00000200U
1649 #define ADC_SMPR2_SMP3_1 0x00000400U
1650 #define ADC_SMPR2_SMP3_2 0x00000800U
1651 #define ADC_SMPR2_SMP4 0x00007000U
1652 #define ADC_SMPR2_SMP4_0 0x00001000U
1653 #define ADC_SMPR2_SMP4_1 0x00002000U
1654 #define ADC_SMPR2_SMP4_2 0x00004000U
1655 #define ADC_SMPR2_SMP5 0x00038000U
1656 #define ADC_SMPR2_SMP5_0 0x00008000U
1657 #define ADC_SMPR2_SMP5_1 0x00010000U
1658 #define ADC_SMPR2_SMP5_2 0x00020000U
1659 #define ADC_SMPR2_SMP6 0x001C0000U
1660 #define ADC_SMPR2_SMP6_0 0x00040000U
1661 #define ADC_SMPR2_SMP6_1 0x00080000U
1662 #define ADC_SMPR2_SMP6_2 0x00100000U
1663 #define ADC_SMPR2_SMP7 0x00E00000U
1664 #define ADC_SMPR2_SMP7_0 0x00200000U
1665 #define ADC_SMPR2_SMP7_1 0x00400000U
1666 #define ADC_SMPR2_SMP7_2 0x00800000U
1667 #define ADC_SMPR2_SMP8 0x07000000U
1668 #define ADC_SMPR2_SMP8_0 0x01000000U
1669 #define ADC_SMPR2_SMP8_1 0x02000000U
1670 #define ADC_SMPR2_SMP8_2 0x04000000U
1671 #define ADC_SMPR2_SMP9 0x38000000U
1672 #define ADC_SMPR2_SMP9_0 0x08000000U
1673 #define ADC_SMPR2_SMP9_1 0x10000000U
1674 #define ADC_SMPR2_SMP9_2 0x20000000U
1676 /****************** Bit definition for ADC_JOFR1 register *******************/
1677 #define ADC_JOFR1_JOFFSET1 0x0FFFU
1679 /****************** Bit definition for ADC_JOFR2 register *******************/
1680 #define ADC_JOFR2_JOFFSET2 0x0FFFU
1682 /****************** Bit definition for ADC_JOFR3 register *******************/
1683 #define ADC_JOFR3_JOFFSET3 0x0FFFU
1685 /****************** Bit definition for ADC_JOFR4 register *******************/
1686 #define ADC_JOFR4_JOFFSET4 0x0FFFU
1688 /******************* Bit definition for ADC_HTR register ********************/
1689 #define ADC_HTR_HT 0x0FFFU
1691 /******************* Bit definition for ADC_LTR register ********************/
1692 #define ADC_LTR_LT 0x0FFFU
1694 /******************* Bit definition for ADC_SQR1 register *******************/
1695 #define ADC_SQR1_SQ13 0x0000001FU
1696 #define ADC_SQR1_SQ13_0 0x00000001U
1697 #define ADC_SQR1_SQ13_1 0x00000002U
1698 #define ADC_SQR1_SQ13_2 0x00000004U
1699 #define ADC_SQR1_SQ13_3 0x00000008U
1700 #define ADC_SQR1_SQ13_4 0x00000010U
1701 #define ADC_SQR1_SQ14 0x000003E0U
1702 #define ADC_SQR1_SQ14_0 0x00000020U
1703 #define ADC_SQR1_SQ14_1 0x00000040U
1704 #define ADC_SQR1_SQ14_2 0x00000080U
1705 #define ADC_SQR1_SQ14_3 0x00000100U
1706 #define ADC_SQR1_SQ14_4 0x00000200U
1707 #define ADC_SQR1_SQ15 0x00007C00U
1708 #define ADC_SQR1_SQ15_0 0x00000400U
1709 #define ADC_SQR1_SQ15_1 0x00000800U
1710 #define ADC_SQR1_SQ15_2 0x00001000U
1711 #define ADC_SQR1_SQ15_3 0x00002000U
1712 #define ADC_SQR1_SQ15_4 0x00004000U
1713 #define ADC_SQR1_SQ16 0x000F8000U
1714 #define ADC_SQR1_SQ16_0 0x00008000U
1715 #define ADC_SQR1_SQ16_1 0x00010000U
1716 #define ADC_SQR1_SQ16_2 0x00020000U
1717 #define ADC_SQR1_SQ16_3 0x00040000U
1718 #define ADC_SQR1_SQ16_4 0x00080000U
1719 #define ADC_SQR1_L 0x00F00000U
1720 #define ADC_SQR1_L_0 0x00100000U
1721 #define ADC_SQR1_L_1 0x00200000U
1722 #define ADC_SQR1_L_2 0x00400000U
1723 #define ADC_SQR1_L_3 0x00800000U
1725 /******************* Bit definition for ADC_SQR2 register *******************/
1726 #define ADC_SQR2_SQ7 0x0000001FU
1727 #define ADC_SQR2_SQ7_0 0x00000001U
1728 #define ADC_SQR2_SQ7_1 0x00000002U
1729 #define ADC_SQR2_SQ7_2 0x00000004U
1730 #define ADC_SQR2_SQ7_3 0x00000008U
1731 #define ADC_SQR2_SQ7_4 0x00000010U
1732 #define ADC_SQR2_SQ8 0x000003E0U
1733 #define ADC_SQR2_SQ8_0 0x00000020U
1734 #define ADC_SQR2_SQ8_1 0x00000040U
1735 #define ADC_SQR2_SQ8_2 0x00000080U
1736 #define ADC_SQR2_SQ8_3 0x00000100U
1737 #define ADC_SQR2_SQ8_4 0x00000200U
1738 #define ADC_SQR2_SQ9 0x00007C00U
1739 #define ADC_SQR2_SQ9_0 0x00000400U
1740 #define ADC_SQR2_SQ9_1 0x00000800U
1741 #define ADC_SQR2_SQ9_2 0x00001000U
1742 #define ADC_SQR2_SQ9_3 0x00002000U
1743 #define ADC_SQR2_SQ9_4 0x00004000U
1744 #define ADC_SQR2_SQ10 0x000F8000U
1745 #define ADC_SQR2_SQ10_0 0x00008000U
1746 #define ADC_SQR2_SQ10_1 0x00010000U
1747 #define ADC_SQR2_SQ10_2 0x00020000U
1748 #define ADC_SQR2_SQ10_3 0x00040000U
1749 #define ADC_SQR2_SQ10_4 0x00080000U
1750 #define ADC_SQR2_SQ11 0x01F00000U
1751 #define ADC_SQR2_SQ11_0 0x00100000U
1752 #define ADC_SQR2_SQ11_1 0x00200000U
1753 #define ADC_SQR2_SQ11_2 0x00400000U
1754 #define ADC_SQR2_SQ11_3 0x00800000U
1755 #define ADC_SQR2_SQ11_4 0x01000000U
1756 #define ADC_SQR2_SQ12 0x3E000000U
1757 #define ADC_SQR2_SQ12_0 0x02000000U
1758 #define ADC_SQR2_SQ12_1 0x04000000U
1759 #define ADC_SQR2_SQ12_2 0x08000000U
1760 #define ADC_SQR2_SQ12_3 0x10000000U
1761 #define ADC_SQR2_SQ12_4 0x20000000U
1763 /******************* Bit definition for ADC_SQR3 register *******************/
1764 #define ADC_SQR3_SQ1 0x0000001FU
1765 #define ADC_SQR3_SQ1_0 0x00000001U
1766 #define ADC_SQR3_SQ1_1 0x00000002U
1767 #define ADC_SQR3_SQ1_2 0x00000004U
1768 #define ADC_SQR3_SQ1_3 0x00000008U
1769 #define ADC_SQR3_SQ1_4 0x00000010U
1770 #define ADC_SQR3_SQ2 0x000003E0U
1771 #define ADC_SQR3_SQ2_0 0x00000020U
1772 #define ADC_SQR3_SQ2_1 0x00000040U
1773 #define ADC_SQR3_SQ2_2 0x00000080U
1774 #define ADC_SQR3_SQ2_3 0x00000100U
1775 #define ADC_SQR3_SQ2_4 0x00000200U
1776 #define ADC_SQR3_SQ3 0x00007C00U
1777 #define ADC_SQR3_SQ3_0 0x00000400U
1778 #define ADC_SQR3_SQ3_1 0x00000800U
1779 #define ADC_SQR3_SQ3_2 0x00001000U
1780 #define ADC_SQR3_SQ3_3 0x00002000U
1781 #define ADC_SQR3_SQ3_4 0x00004000U
1782 #define ADC_SQR3_SQ4 0x000F8000U
1783 #define ADC_SQR3_SQ4_0 0x00008000U
1784 #define ADC_SQR3_SQ4_1 0x00010000U
1785 #define ADC_SQR3_SQ4_2 0x00020000U
1786 #define ADC_SQR3_SQ4_3 0x00040000U
1787 #define ADC_SQR3_SQ4_4 0x00080000U
1788 #define ADC_SQR3_SQ5 0x01F00000U
1789 #define ADC_SQR3_SQ5_0 0x00100000U
1790 #define ADC_SQR3_SQ5_1 0x00200000U
1791 #define ADC_SQR3_SQ5_2 0x00400000U
1792 #define ADC_SQR3_SQ5_3 0x00800000U
1793 #define ADC_SQR3_SQ5_4 0x01000000U
1794 #define ADC_SQR3_SQ6 0x3E000000U
1795 #define ADC_SQR3_SQ6_0 0x02000000U
1796 #define ADC_SQR3_SQ6_1 0x04000000U
1797 #define ADC_SQR3_SQ6_2 0x08000000U
1798 #define ADC_SQR3_SQ6_3 0x10000000U
1799 #define ADC_SQR3_SQ6_4 0x20000000U
1801 /******************* Bit definition for ADC_JSQR register *******************/
1802 #define ADC_JSQR_JSQ1 0x0000001FU
1803 #define ADC_JSQR_JSQ1_0 0x00000001U
1804 #define ADC_JSQR_JSQ1_1 0x00000002U
1805 #define ADC_JSQR_JSQ1_2 0x00000004U
1806 #define ADC_JSQR_JSQ1_3 0x00000008U
1807 #define ADC_JSQR_JSQ1_4 0x00000010U
1808 #define ADC_JSQR_JSQ2 0x000003E0U
1809 #define ADC_JSQR_JSQ2_0 0x00000020U
1810 #define ADC_JSQR_JSQ2_1 0x00000040U
1811 #define ADC_JSQR_JSQ2_2 0x00000080U
1812 #define ADC_JSQR_JSQ2_3 0x00000100U
1813 #define ADC_JSQR_JSQ2_4 0x00000200U
1814 #define ADC_JSQR_JSQ3 0x00007C00U
1815 #define ADC_JSQR_JSQ3_0 0x00000400U
1816 #define ADC_JSQR_JSQ3_1 0x00000800U
1817 #define ADC_JSQR_JSQ3_2 0x00001000U
1818 #define ADC_JSQR_JSQ3_3 0x00002000U
1819 #define ADC_JSQR_JSQ3_4 0x00004000U
1820 #define ADC_JSQR_JSQ4 0x000F8000U
1821 #define ADC_JSQR_JSQ4_0 0x00008000U
1822 #define ADC_JSQR_JSQ4_1 0x00010000U
1823 #define ADC_JSQR_JSQ4_2 0x00020000U
1824 #define ADC_JSQR_JSQ4_3 0x00040000U
1825 #define ADC_JSQR_JSQ4_4 0x00080000U
1826 #define ADC_JSQR_JL 0x00300000U
1827 #define ADC_JSQR_JL_0 0x00100000U
1828 #define ADC_JSQR_JL_1 0x00200000U
1830 /******************* Bit definition for ADC_JDR1 register *******************/
1831 #define ADC_JDR1_JDATA ((uint16_t)0xFFFFU)
1833 /******************* Bit definition for ADC_JDR2 register *******************/
1834 #define ADC_JDR2_JDATA ((uint16_t)0xFFFFU)
1836 /******************* Bit definition for ADC_JDR3 register *******************/
1837 #define ADC_JDR3_JDATA ((uint16_t)0xFFFFU)
1839 /******************* Bit definition for ADC_JDR4 register *******************/
1840 #define ADC_JDR4_JDATA ((uint16_t)0xFFFFU)
1842 /******************** Bit definition for ADC_DR register ********************/
1843 #define ADC_DR_DATA 0x0000FFFFU
1844 #define ADC_DR_ADC2DATA 0xFFFF0000U
1846 /******************* Bit definition for ADC_CSR register ********************/
1847 #define ADC_CSR_AWD1 0x00000001U
1848 #define ADC_CSR_EOC1 0x00000002U
1849 #define ADC_CSR_JEOC1 0x00000004U
1850 #define ADC_CSR_JSTRT1 0x00000008U
1851 #define ADC_CSR_STRT1 0x00000010U
1852 #define ADC_CSR_OVR1 0x00000020U
1853 #define ADC_CSR_AWD2 0x00000100U
1854 #define ADC_CSR_EOC2 0x00000200U
1855 #define ADC_CSR_JEOC2 0x00000400U
1856 #define ADC_CSR_JSTRT2 0x00000800U
1857 #define ADC_CSR_STRT2 0x00001000U
1858 #define ADC_CSR_OVR2 0x00002000U
1859 #define ADC_CSR_AWD3 0x00010000U
1860 #define ADC_CSR_EOC3 0x00020000U
1861 #define ADC_CSR_JEOC3 0x00040000U
1862 #define ADC_CSR_JSTRT3 0x00080000U
1863 #define ADC_CSR_STRT3 0x00100000U
1864 #define ADC_CSR_OVR3 0x00200000U
1866 /* Legacy defines */
1867 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1868 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
1869 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
1870 
1871 
1872 /******************* Bit definition for ADC_CCR register ********************/
1873 #define ADC_CCR_MULTI 0x0000001FU
1874 #define ADC_CCR_MULTI_0 0x00000001U
1875 #define ADC_CCR_MULTI_1 0x00000002U
1876 #define ADC_CCR_MULTI_2 0x00000004U
1877 #define ADC_CCR_MULTI_3 0x00000008U
1878 #define ADC_CCR_MULTI_4 0x00000010U
1879 #define ADC_CCR_DELAY 0x00000F00U
1880 #define ADC_CCR_DELAY_0 0x00000100U
1881 #define ADC_CCR_DELAY_1 0x00000200U
1882 #define ADC_CCR_DELAY_2 0x00000400U
1883 #define ADC_CCR_DELAY_3 0x00000800U
1884 #define ADC_CCR_DDS 0x00002000U
1885 #define ADC_CCR_DMA 0x0000C000U
1886 #define ADC_CCR_DMA_0 0x00004000U
1887 #define ADC_CCR_DMA_1 0x00008000U
1888 #define ADC_CCR_ADCPRE 0x00030000U
1889 #define ADC_CCR_ADCPRE_0 0x00010000U
1890 #define ADC_CCR_ADCPRE_1 0x00020000U
1891 #define ADC_CCR_VBATE 0x00400000U
1892 #define ADC_CCR_TSVREFE 0x00800000U
1894 /******************* Bit definition for ADC_CDR register ********************/
1895 #define ADC_CDR_DATA1 0x0000FFFFU
1896 #define ADC_CDR_DATA2 0xFFFF0000U
1898 /******************************************************************************/
1899 /* */
1900 /* Controller Area Network */
1901 /* */
1902 /******************************************************************************/
1904 /******************* Bit definition for CAN_MCR register ********************/
1905 #define CAN_MCR_INRQ 0x00000001U
1906 #define CAN_MCR_SLEEP 0x00000002U
1907 #define CAN_MCR_TXFP 0x00000004U
1908 #define CAN_MCR_RFLM 0x00000008U
1909 #define CAN_MCR_NART 0x00000010U
1910 #define CAN_MCR_AWUM 0x00000020U
1911 #define CAN_MCR_ABOM 0x00000040U
1912 #define CAN_MCR_TTCM 0x00000080U
1913 #define CAN_MCR_RESET 0x00008000U
1915 /******************* Bit definition for CAN_MSR register ********************/
1916 #define CAN_MSR_INAK 0x00000001U
1917 #define CAN_MSR_SLAK 0x00000002U
1918 #define CAN_MSR_ERRI 0x00000004U
1919 #define CAN_MSR_WKUI 0x00000008U
1920 #define CAN_MSR_SLAKI 0x00000010U
1921 #define CAN_MSR_TXM 0x00000100U
1922 #define CAN_MSR_RXM 0x00000200U
1923 #define CAN_MSR_SAMP 0x00000400U
1924 #define CAN_MSR_RX 0x00000800U
1926 /******************* Bit definition for CAN_TSR register ********************/
1927 #define CAN_TSR_RQCP0 0x00000001U
1928 #define CAN_TSR_TXOK0 0x00000002U
1929 #define CAN_TSR_ALST0 0x00000004U
1930 #define CAN_TSR_TERR0 0x00000008U
1931 #define CAN_TSR_ABRQ0 0x00000080U
1932 #define CAN_TSR_RQCP1 0x00000100U
1933 #define CAN_TSR_TXOK1 0x00000200U
1934 #define CAN_TSR_ALST1 0x00000400U
1935 #define CAN_TSR_TERR1 0x00000800U
1936 #define CAN_TSR_ABRQ1 0x00008000U
1937 #define CAN_TSR_RQCP2 0x00010000U
1938 #define CAN_TSR_TXOK2 0x00020000U
1939 #define CAN_TSR_ALST2 0x00040000U
1940 #define CAN_TSR_TERR2 0x00080000U
1941 #define CAN_TSR_ABRQ2 0x00800000U
1942 #define CAN_TSR_CODE 0x03000000U
1944 #define CAN_TSR_TME 0x1C000000U
1945 #define CAN_TSR_TME0 0x04000000U
1946 #define CAN_TSR_TME1 0x08000000U
1947 #define CAN_TSR_TME2 0x10000000U
1949 #define CAN_TSR_LOW 0xE0000000U
1950 #define CAN_TSR_LOW0 0x20000000U
1951 #define CAN_TSR_LOW1 0x40000000U
1952 #define CAN_TSR_LOW2 0x80000000U
1954 /******************* Bit definition for CAN_RF0R register *******************/
1955 #define CAN_RF0R_FMP0 0x00000003U
1956 #define CAN_RF0R_FULL0 0x00000008U
1957 #define CAN_RF0R_FOVR0 0x00000010U
1958 #define CAN_RF0R_RFOM0 0x00000020U
1960 /******************* Bit definition for CAN_RF1R register *******************/
1961 #define CAN_RF1R_FMP1 0x00000003U
1962 #define CAN_RF1R_FULL1 0x00000008U
1963 #define CAN_RF1R_FOVR1 0x00000010U
1964 #define CAN_RF1R_RFOM1 0x00000020U
1966 /******************** Bit definition for CAN_IER register *******************/
1967 #define CAN_IER_TMEIE 0x00000001U
1968 #define CAN_IER_FMPIE0 0x00000002U
1969 #define CAN_IER_FFIE0 0x00000004U
1970 #define CAN_IER_FOVIE0 0x00000008U
1971 #define CAN_IER_FMPIE1 0x00000010U
1972 #define CAN_IER_FFIE1 0x00000020U
1973 #define CAN_IER_FOVIE1 0x00000040U
1974 #define CAN_IER_EWGIE 0x00000100U
1975 #define CAN_IER_EPVIE 0x00000200U
1976 #define CAN_IER_BOFIE 0x00000400U
1977 #define CAN_IER_LECIE 0x00000800U
1978 #define CAN_IER_ERRIE 0x00008000U
1979 #define CAN_IER_WKUIE 0x00010000U
1980 #define CAN_IER_SLKIE 0x00020000U
1982 /******************** Bit definition for CAN_ESR register *******************/
1983 #define CAN_ESR_EWGF 0x00000001U
1984 #define CAN_ESR_EPVF 0x00000002U
1985 #define CAN_ESR_BOFF 0x00000004U
1987 #define CAN_ESR_LEC 0x00000070U
1988 #define CAN_ESR_LEC_0 0x00000010U
1989 #define CAN_ESR_LEC_1 0x00000020U
1990 #define CAN_ESR_LEC_2 0x00000040U
1992 #define CAN_ESR_TEC 0x00FF0000U
1993 #define CAN_ESR_REC 0xFF000000U
1995 /******************* Bit definition for CAN_BTR register ********************/
1996 #define CAN_BTR_BRP 0x000003FFU
1997 #define CAN_BTR_TS1 0x000F0000U
1998 #define CAN_BTR_TS1_0 0x00010000U
1999 #define CAN_BTR_TS1_1 0x00020000U
2000 #define CAN_BTR_TS1_2 0x00040000U
2001 #define CAN_BTR_TS1_3 0x00080000U
2002 #define CAN_BTR_TS2 0x00700000U
2003 #define CAN_BTR_TS2_0 0x00100000U
2004 #define CAN_BTR_TS2_1 0x00200000U
2005 #define CAN_BTR_TS2_2 0x00400000U
2006 #define CAN_BTR_SJW 0x03000000U
2007 #define CAN_BTR_SJW_0 0x01000000U
2008 #define CAN_BTR_SJW_1 0x02000000U
2009 #define CAN_BTR_LBKM 0x40000000U
2010 #define CAN_BTR_SILM 0x80000000U
2013 /****************** Bit definition for CAN_TI0R register ********************/
2014 #define CAN_TI0R_TXRQ 0x00000001U
2015 #define CAN_TI0R_RTR 0x00000002U
2016 #define CAN_TI0R_IDE 0x00000004U
2017 #define CAN_TI0R_EXID 0x001FFFF8U
2018 #define CAN_TI0R_STID 0xFFE00000U
2020 /****************** Bit definition for CAN_TDT0R register *******************/
2021 #define CAN_TDT0R_DLC 0x0000000FU
2022 #define CAN_TDT0R_TGT 0x00000100U
2023 #define CAN_TDT0R_TIME 0xFFFF0000U
2025 /****************** Bit definition for CAN_TDL0R register *******************/
2026 #define CAN_TDL0R_DATA0 0x000000FFU
2027 #define CAN_TDL0R_DATA1 0x0000FF00U
2028 #define CAN_TDL0R_DATA2 0x00FF0000U
2029 #define CAN_TDL0R_DATA3 0xFF000000U
2031 /****************** Bit definition for CAN_TDH0R register *******************/
2032 #define CAN_TDH0R_DATA4 0x000000FFU
2033 #define CAN_TDH0R_DATA5 0x0000FF00U
2034 #define CAN_TDH0R_DATA6 0x00FF0000U
2035 #define CAN_TDH0R_DATA7 0xFF000000U
2037 /******************* Bit definition for CAN_TI1R register *******************/
2038 #define CAN_TI1R_TXRQ 0x00000001U
2039 #define CAN_TI1R_RTR 0x00000002U
2040 #define CAN_TI1R_IDE 0x00000004U
2041 #define CAN_TI1R_EXID 0x001FFFF8U
2042 #define CAN_TI1R_STID 0xFFE00000U
2044 /******************* Bit definition for CAN_TDT1R register ******************/
2045 #define CAN_TDT1R_DLC 0x0000000FU
2046 #define CAN_TDT1R_TGT 0x00000100U
2047 #define CAN_TDT1R_TIME 0xFFFF0000U
2049 /******************* Bit definition for CAN_TDL1R register ******************/
2050 #define CAN_TDL1R_DATA0 0x000000FFU
2051 #define CAN_TDL1R_DATA1 0x0000FF00U
2052 #define CAN_TDL1R_DATA2 0x00FF0000U
2053 #define CAN_TDL1R_DATA3 0xFF000000U
2055 /******************* Bit definition for CAN_TDH1R register ******************/
2056 #define CAN_TDH1R_DATA4 0x000000FFU
2057 #define CAN_TDH1R_DATA5 0x0000FF00U
2058 #define CAN_TDH1R_DATA6 0x00FF0000U
2059 #define CAN_TDH1R_DATA7 0xFF000000U
2061 /******************* Bit definition for CAN_TI2R register *******************/
2062 #define CAN_TI2R_TXRQ 0x00000001U
2063 #define CAN_TI2R_RTR 0x00000002U
2064 #define CAN_TI2R_IDE 0x00000004U
2065 #define CAN_TI2R_EXID 0x001FFFF8U
2066 #define CAN_TI2R_STID 0xFFE00000U
2068 /******************* Bit definition for CAN_TDT2R register ******************/
2069 #define CAN_TDT2R_DLC 0x0000000FU
2070 #define CAN_TDT2R_TGT 0x00000100U
2071 #define CAN_TDT2R_TIME 0xFFFF0000U
2073 /******************* Bit definition for CAN_TDL2R register ******************/
2074 #define CAN_TDL2R_DATA0 0x000000FFU
2075 #define CAN_TDL2R_DATA1 0x0000FF00U
2076 #define CAN_TDL2R_DATA2 0x00FF0000U
2077 #define CAN_TDL2R_DATA3 0xFF000000U
2079 /******************* Bit definition for CAN_TDH2R register ******************/
2080 #define CAN_TDH2R_DATA4 0x000000FFU
2081 #define CAN_TDH2R_DATA5 0x0000FF00U
2082 #define CAN_TDH2R_DATA6 0x00FF0000U
2083 #define CAN_TDH2R_DATA7 0xFF000000U
2085 /******************* Bit definition for CAN_RI0R register *******************/
2086 #define CAN_RI0R_RTR 0x00000002U
2087 #define CAN_RI0R_IDE 0x00000004U
2088 #define CAN_RI0R_EXID 0x001FFFF8U
2089 #define CAN_RI0R_STID 0xFFE00000U
2091 /******************* Bit definition for CAN_RDT0R register ******************/
2092 #define CAN_RDT0R_DLC 0x0000000FU
2093 #define CAN_RDT0R_FMI 0x0000FF00U
2094 #define CAN_RDT0R_TIME 0xFFFF0000U
2096 /******************* Bit definition for CAN_RDL0R register ******************/
2097 #define CAN_RDL0R_DATA0 0x000000FFU
2098 #define CAN_RDL0R_DATA1 0x0000FF00U
2099 #define CAN_RDL0R_DATA2 0x00FF0000U
2100 #define CAN_RDL0R_DATA3 0xFF000000U
2102 /******************* Bit definition for CAN_RDH0R register ******************/
2103 #define CAN_RDH0R_DATA4 0x000000FFU
2104 #define CAN_RDH0R_DATA5 0x0000FF00U
2105 #define CAN_RDH0R_DATA6 0x00FF0000U
2106 #define CAN_RDH0R_DATA7 0xFF000000U
2108 /******************* Bit definition for CAN_RI1R register *******************/
2109 #define CAN_RI1R_RTR 0x00000002U
2110 #define CAN_RI1R_IDE 0x00000004U
2111 #define CAN_RI1R_EXID 0x001FFFF8U
2112 #define CAN_RI1R_STID 0xFFE00000U
2114 /******************* Bit definition for CAN_RDT1R register ******************/
2115 #define CAN_RDT1R_DLC 0x0000000FU
2116 #define CAN_RDT1R_FMI 0x0000FF00U
2117 #define CAN_RDT1R_TIME 0xFFFF0000U
2119 /******************* Bit definition for CAN_RDL1R register ******************/
2120 #define CAN_RDL1R_DATA0 0x000000FFU
2121 #define CAN_RDL1R_DATA1 0x0000FF00U
2122 #define CAN_RDL1R_DATA2 0x00FF0000U
2123 #define CAN_RDL1R_DATA3 0xFF000000U
2125 /******************* Bit definition for CAN_RDH1R register ******************/
2126 #define CAN_RDH1R_DATA4 0x000000FFU
2127 #define CAN_RDH1R_DATA5 0x0000FF00U
2128 #define CAN_RDH1R_DATA6 0x00FF0000U
2129 #define CAN_RDH1R_DATA7 0xFF000000U
2132 /******************* Bit definition for CAN_FMR register ********************/
2133 #define CAN_FMR_FINIT ((uint8_t)0x01U)
2134 #define CAN_FMR_CAN2SB 0x00003F00U
2136 /******************* Bit definition for CAN_FM1R register *******************/
2137 #define CAN_FM1R_FBM 0x3FFFU
2138 #define CAN_FM1R_FBM0 0x0001U
2139 #define CAN_FM1R_FBM1 0x0002U
2140 #define CAN_FM1R_FBM2 0x0004U
2141 #define CAN_FM1R_FBM3 0x0008U
2142 #define CAN_FM1R_FBM4 0x0010U
2143 #define CAN_FM1R_FBM5 0x0020U
2144 #define CAN_FM1R_FBM6 0x0040U
2145 #define CAN_FM1R_FBM7 0x0080U
2146 #define CAN_FM1R_FBM8 0x0100U
2147 #define CAN_FM1R_FBM9 0x0200U
2148 #define CAN_FM1R_FBM10 0x0400U
2149 #define CAN_FM1R_FBM11 0x0800U
2150 #define CAN_FM1R_FBM12 0x1000U
2151 #define CAN_FM1R_FBM13 0x2000U
2153 /******************* Bit definition for CAN_FS1R register *******************/
2154 #define CAN_FS1R_FSC 0x00003FFFU
2155 #define CAN_FS1R_FSC0 0x00000001U
2156 #define CAN_FS1R_FSC1 0x00000002U
2157 #define CAN_FS1R_FSC2 0x00000004U
2158 #define CAN_FS1R_FSC3 0x00000008U
2159 #define CAN_FS1R_FSC4 0x00000010U
2160 #define CAN_FS1R_FSC5 0x00000020U
2161 #define CAN_FS1R_FSC6 0x00000040U
2162 #define CAN_FS1R_FSC7 0x00000080U
2163 #define CAN_FS1R_FSC8 0x00000100U
2164 #define CAN_FS1R_FSC9 0x00000200U
2165 #define CAN_FS1R_FSC10 0x00000400U
2166 #define CAN_FS1R_FSC11 0x00000800U
2167 #define CAN_FS1R_FSC12 0x00001000U
2168 #define CAN_FS1R_FSC13 0x00002000U
2170 /****************** Bit definition for CAN_FFA1R register *******************/
2171 #define CAN_FFA1R_FFA 0x00003FFFU
2172 #define CAN_FFA1R_FFA0 0x00000001U
2173 #define CAN_FFA1R_FFA1 0x00000002U
2174 #define CAN_FFA1R_FFA2 0x00000004U
2175 #define CAN_FFA1R_FFA3 0x00000008U
2176 #define CAN_FFA1R_FFA4 0x00000010U
2177 #define CAN_FFA1R_FFA5 0x00000020U
2178 #define CAN_FFA1R_FFA6 0x00000040U
2179 #define CAN_FFA1R_FFA7 0x00000080U
2180 #define CAN_FFA1R_FFA8 0x00000100U
2181 #define CAN_FFA1R_FFA9 0x00000200U
2182 #define CAN_FFA1R_FFA10 0x00000400U
2183 #define CAN_FFA1R_FFA11 0x00000800U
2184 #define CAN_FFA1R_FFA12 0x00001000U
2185 #define CAN_FFA1R_FFA13 0x00002000U
2187 /******************* Bit definition for CAN_FA1R register *******************/
2188 #define CAN_FA1R_FACT 0x00003FFFU
2189 #define CAN_FA1R_FACT0 0x00000001U
2190 #define CAN_FA1R_FACT1 0x00000002U
2191 #define CAN_FA1R_FACT2 0x00000004U
2192 #define CAN_FA1R_FACT3 0x00000008U
2193 #define CAN_FA1R_FACT4 0x00000010U
2194 #define CAN_FA1R_FACT5 0x00000020U
2195 #define CAN_FA1R_FACT6 0x00000040U
2196 #define CAN_FA1R_FACT7 0x00000080U
2197 #define CAN_FA1R_FACT8 0x00000100U
2198 #define CAN_FA1R_FACT9 0x00000200U
2199 #define CAN_FA1R_FACT10 0x00000400U
2200 #define CAN_FA1R_FACT11 0x00000800U
2201 #define CAN_FA1R_FACT12 0x00001000U
2202 #define CAN_FA1R_FACT13 0x00002000U
2204 /******************* Bit definition for CAN_F0R1 register *******************/
2205 #define CAN_F0R1_FB0 0x00000001U
2206 #define CAN_F0R1_FB1 0x00000002U
2207 #define CAN_F0R1_FB2 0x00000004U
2208 #define CAN_F0R1_FB3 0x00000008U
2209 #define CAN_F0R1_FB4 0x00000010U
2210 #define CAN_F0R1_FB5 0x00000020U
2211 #define CAN_F0R1_FB6 0x00000040U
2212 #define CAN_F0R1_FB7 0x00000080U
2213 #define CAN_F0R1_FB8 0x00000100U
2214 #define CAN_F0R1_FB9 0x00000200U
2215 #define CAN_F0R1_FB10 0x00000400U
2216 #define CAN_F0R1_FB11 0x00000800U
2217 #define CAN_F0R1_FB12 0x00001000U
2218 #define CAN_F0R1_FB13 0x00002000U
2219 #define CAN_F0R1_FB14 0x00004000U
2220 #define CAN_F0R1_FB15 0x00008000U
2221 #define CAN_F0R1_FB16 0x00010000U
2222 #define CAN_F0R1_FB17 0x00020000U
2223 #define CAN_F0R1_FB18 0x00040000U
2224 #define CAN_F0R1_FB19 0x00080000U
2225 #define CAN_F0R1_FB20 0x00100000U
2226 #define CAN_F0R1_FB21 0x00200000U
2227 #define CAN_F0R1_FB22 0x00400000U
2228 #define CAN_F0R1_FB23 0x00800000U
2229 #define CAN_F0R1_FB24 0x01000000U
2230 #define CAN_F0R1_FB25 0x02000000U
2231 #define CAN_F0R1_FB26 0x04000000U
2232 #define CAN_F0R1_FB27 0x08000000U
2233 #define CAN_F0R1_FB28 0x10000000U
2234 #define CAN_F0R1_FB29 0x20000000U
2235 #define CAN_F0R1_FB30 0x40000000U
2236 #define CAN_F0R1_FB31 0x80000000U
2238 /******************* Bit definition for CAN_F1R1 register *******************/
2239 #define CAN_F1R1_FB0 0x00000001U
2240 #define CAN_F1R1_FB1 0x00000002U
2241 #define CAN_F1R1_FB2 0x00000004U
2242 #define CAN_F1R1_FB3 0x00000008U
2243 #define CAN_F1R1_FB4 0x00000010U
2244 #define CAN_F1R1_FB5 0x00000020U
2245 #define CAN_F1R1_FB6 0x00000040U
2246 #define CAN_F1R1_FB7 0x00000080U
2247 #define CAN_F1R1_FB8 0x00000100U
2248 #define CAN_F1R1_FB9 0x00000200U
2249 #define CAN_F1R1_FB10 0x00000400U
2250 #define CAN_F1R1_FB11 0x00000800U
2251 #define CAN_F1R1_FB12 0x00001000U
2252 #define CAN_F1R1_FB13 0x00002000U
2253 #define CAN_F1R1_FB14 0x00004000U
2254 #define CAN_F1R1_FB15 0x00008000U
2255 #define CAN_F1R1_FB16 0x00010000U
2256 #define CAN_F1R1_FB17 0x00020000U
2257 #define CAN_F1R1_FB18 0x00040000U
2258 #define CAN_F1R1_FB19 0x00080000U
2259 #define CAN_F1R1_FB20 0x00100000U
2260 #define CAN_F1R1_FB21 0x00200000U
2261 #define CAN_F1R1_FB22 0x00400000U
2262 #define CAN_F1R1_FB23 0x00800000U
2263 #define CAN_F1R1_FB24 0x01000000U
2264 #define CAN_F1R1_FB25 0x02000000U
2265 #define CAN_F1R1_FB26 0x04000000U
2266 #define CAN_F1R1_FB27 0x08000000U
2267 #define CAN_F1R1_FB28 0x10000000U
2268 #define CAN_F1R1_FB29 0x20000000U
2269 #define CAN_F1R1_FB30 0x40000000U
2270 #define CAN_F1R1_FB31 0x80000000U
2272 /******************* Bit definition for CAN_F2R1 register *******************/
2273 #define CAN_F2R1_FB0 0x00000001U
2274 #define CAN_F2R1_FB1 0x00000002U
2275 #define CAN_F2R1_FB2 0x00000004U
2276 #define CAN_F2R1_FB3 0x00000008U
2277 #define CAN_F2R1_FB4 0x00000010U
2278 #define CAN_F2R1_FB5 0x00000020U
2279 #define CAN_F2R1_FB6 0x00000040U
2280 #define CAN_F2R1_FB7 0x00000080U
2281 #define CAN_F2R1_FB8 0x00000100U
2282 #define CAN_F2R1_FB9 0x00000200U
2283 #define CAN_F2R1_FB10 0x00000400U
2284 #define CAN_F2R1_FB11 0x00000800U
2285 #define CAN_F2R1_FB12 0x00001000U
2286 #define CAN_F2R1_FB13 0x00002000U
2287 #define CAN_F2R1_FB14 0x00004000U
2288 #define CAN_F2R1_FB15 0x00008000U
2289 #define CAN_F2R1_FB16 0x00010000U
2290 #define CAN_F2R1_FB17 0x00020000U
2291 #define CAN_F2R1_FB18 0x00040000U
2292 #define CAN_F2R1_FB19 0x00080000U
2293 #define CAN_F2R1_FB20 0x00100000U
2294 #define CAN_F2R1_FB21 0x00200000U
2295 #define CAN_F2R1_FB22 0x00400000U
2296 #define CAN_F2R1_FB23 0x00800000U
2297 #define CAN_F2R1_FB24 0x01000000U
2298 #define CAN_F2R1_FB25 0x02000000U
2299 #define CAN_F2R1_FB26 0x04000000U
2300 #define CAN_F2R1_FB27 0x08000000U
2301 #define CAN_F2R1_FB28 0x10000000U
2302 #define CAN_F2R1_FB29 0x20000000U
2303 #define CAN_F2R1_FB30 0x40000000U
2304 #define CAN_F2R1_FB31 0x80000000U
2306 /******************* Bit definition for CAN_F3R1 register *******************/
2307 #define CAN_F3R1_FB0 0x00000001U
2308 #define CAN_F3R1_FB1 0x00000002U
2309 #define CAN_F3R1_FB2 0x00000004U
2310 #define CAN_F3R1_FB3 0x00000008U
2311 #define CAN_F3R1_FB4 0x00000010U
2312 #define CAN_F3R1_FB5 0x00000020U
2313 #define CAN_F3R1_FB6 0x00000040U
2314 #define CAN_F3R1_FB7 0x00000080U
2315 #define CAN_F3R1_FB8 0x00000100U
2316 #define CAN_F3R1_FB9 0x00000200U
2317 #define CAN_F3R1_FB10 0x00000400U
2318 #define CAN_F3R1_FB11 0x00000800U
2319 #define CAN_F3R1_FB12 0x00001000U
2320 #define CAN_F3R1_FB13 0x00002000U
2321 #define CAN_F3R1_FB14 0x00004000U
2322 #define CAN_F3R1_FB15 0x00008000U
2323 #define CAN_F3R1_FB16 0x00010000U
2324 #define CAN_F3R1_FB17 0x00020000U
2325 #define CAN_F3R1_FB18 0x00040000U
2326 #define CAN_F3R1_FB19 0x00080000U
2327 #define CAN_F3R1_FB20 0x00100000U
2328 #define CAN_F3R1_FB21 0x00200000U
2329 #define CAN_F3R1_FB22 0x00400000U
2330 #define CAN_F3R1_FB23 0x00800000U
2331 #define CAN_F3R1_FB24 0x01000000U
2332 #define CAN_F3R1_FB25 0x02000000U
2333 #define CAN_F3R1_FB26 0x04000000U
2334 #define CAN_F3R1_FB27 0x08000000U
2335 #define CAN_F3R1_FB28 0x10000000U
2336 #define CAN_F3R1_FB29 0x20000000U
2337 #define CAN_F3R1_FB30 0x40000000U
2338 #define CAN_F3R1_FB31 0x80000000U
2340 /******************* Bit definition for CAN_F4R1 register *******************/
2341 #define CAN_F4R1_FB0 0x00000001U
2342 #define CAN_F4R1_FB1 0x00000002U
2343 #define CAN_F4R1_FB2 0x00000004U
2344 #define CAN_F4R1_FB3 0x00000008U
2345 #define CAN_F4R1_FB4 0x00000010U
2346 #define CAN_F4R1_FB5 0x00000020U
2347 #define CAN_F4R1_FB6 0x00000040U
2348 #define CAN_F4R1_FB7 0x00000080U
2349 #define CAN_F4R1_FB8 0x00000100U
2350 #define CAN_F4R1_FB9 0x00000200U
2351 #define CAN_F4R1_FB10 0x00000400U
2352 #define CAN_F4R1_FB11 0x00000800U
2353 #define CAN_F4R1_FB12 0x00001000U
2354 #define CAN_F4R1_FB13 0x00002000U
2355 #define CAN_F4R1_FB14 0x00004000U
2356 #define CAN_F4R1_FB15 0x00008000U
2357 #define CAN_F4R1_FB16 0x00010000U
2358 #define CAN_F4R1_FB17 0x00020000U
2359 #define CAN_F4R1_FB18 0x00040000U
2360 #define CAN_F4R1_FB19 0x00080000U
2361 #define CAN_F4R1_FB20 0x00100000U
2362 #define CAN_F4R1_FB21 0x00200000U
2363 #define CAN_F4R1_FB22 0x00400000U
2364 #define CAN_F4R1_FB23 0x00800000U
2365 #define CAN_F4R1_FB24 0x01000000U
2366 #define CAN_F4R1_FB25 0x02000000U
2367 #define CAN_F4R1_FB26 0x04000000U
2368 #define CAN_F4R1_FB27 0x08000000U
2369 #define CAN_F4R1_FB28 0x10000000U
2370 #define CAN_F4R1_FB29 0x20000000U
2371 #define CAN_F4R1_FB30 0x40000000U
2372 #define CAN_F4R1_FB31 0x80000000U
2374 /******************* Bit definition for CAN_F5R1 register *******************/
2375 #define CAN_F5R1_FB0 0x00000001U
2376 #define CAN_F5R1_FB1 0x00000002U
2377 #define CAN_F5R1_FB2 0x00000004U
2378 #define CAN_F5R1_FB3 0x00000008U
2379 #define CAN_F5R1_FB4 0x00000010U
2380 #define CAN_F5R1_FB5 0x00000020U
2381 #define CAN_F5R1_FB6 0x00000040U
2382 #define CAN_F5R1_FB7 0x00000080U
2383 #define CAN_F5R1_FB8 0x00000100U
2384 #define CAN_F5R1_FB9 0x00000200U
2385 #define CAN_F5R1_FB10 0x00000400U
2386 #define CAN_F5R1_FB11 0x00000800U
2387 #define CAN_F5R1_FB12 0x00001000U
2388 #define CAN_F5R1_FB13 0x00002000U
2389 #define CAN_F5R1_FB14 0x00004000U
2390 #define CAN_F5R1_FB15 0x00008000U
2391 #define CAN_F5R1_FB16 0x00010000U
2392 #define CAN_F5R1_FB17 0x00020000U
2393 #define CAN_F5R1_FB18 0x00040000U
2394 #define CAN_F5R1_FB19 0x00080000U
2395 #define CAN_F5R1_FB20 0x00100000U
2396 #define CAN_F5R1_FB21 0x00200000U
2397 #define CAN_F5R1_FB22 0x00400000U
2398 #define CAN_F5R1_FB23 0x00800000U
2399 #define CAN_F5R1_FB24 0x01000000U
2400 #define CAN_F5R1_FB25 0x02000000U
2401 #define CAN_F5R1_FB26 0x04000000U
2402 #define CAN_F5R1_FB27 0x08000000U
2403 #define CAN_F5R1_FB28 0x10000000U
2404 #define CAN_F5R1_FB29 0x20000000U
2405 #define CAN_F5R1_FB30 0x40000000U
2406 #define CAN_F5R1_FB31 0x80000000U
2408 /******************* Bit definition for CAN_F6R1 register *******************/
2409 #define CAN_F6R1_FB0 0x00000001U
2410 #define CAN_F6R1_FB1 0x00000002U
2411 #define CAN_F6R1_FB2 0x00000004U
2412 #define CAN_F6R1_FB3 0x00000008U
2413 #define CAN_F6R1_FB4 0x00000010U
2414 #define CAN_F6R1_FB5 0x00000020U
2415 #define CAN_F6R1_FB6 0x00000040U
2416 #define CAN_F6R1_FB7 0x00000080U
2417 #define CAN_F6R1_FB8 0x00000100U
2418 #define CAN_F6R1_FB9 0x00000200U
2419 #define CAN_F6R1_FB10 0x00000400U
2420 #define CAN_F6R1_FB11 0x00000800U
2421 #define CAN_F6R1_FB12 0x00001000U
2422 #define CAN_F6R1_FB13 0x00002000U
2423 #define CAN_F6R1_FB14 0x00004000U
2424 #define CAN_F6R1_FB15 0x00008000U
2425 #define CAN_F6R1_FB16 0x00010000U
2426 #define CAN_F6R1_FB17 0x00020000U
2427 #define CAN_F6R1_FB18 0x00040000U
2428 #define CAN_F6R1_FB19 0x00080000U
2429 #define CAN_F6R1_FB20 0x00100000U
2430 #define CAN_F6R1_FB21 0x00200000U
2431 #define CAN_F6R1_FB22 0x00400000U
2432 #define CAN_F6R1_FB23 0x00800000U
2433 #define CAN_F6R1_FB24 0x01000000U
2434 #define CAN_F6R1_FB25 0x02000000U
2435 #define CAN_F6R1_FB26 0x04000000U
2436 #define CAN_F6R1_FB27 0x08000000U
2437 #define CAN_F6R1_FB28 0x10000000U
2438 #define CAN_F6R1_FB29 0x20000000U
2439 #define CAN_F6R1_FB30 0x40000000U
2440 #define CAN_F6R1_FB31 0x80000000U
2442 /******************* Bit definition for CAN_F7R1 register *******************/
2443 #define CAN_F7R1_FB0 0x00000001U
2444 #define CAN_F7R1_FB1 0x00000002U
2445 #define CAN_F7R1_FB2 0x00000004U
2446 #define CAN_F7R1_FB3 0x00000008U
2447 #define CAN_F7R1_FB4 0x00000010U
2448 #define CAN_F7R1_FB5 0x00000020U
2449 #define CAN_F7R1_FB6 0x00000040U
2450 #define CAN_F7R1_FB7 0x00000080U
2451 #define CAN_F7R1_FB8 0x00000100U
2452 #define CAN_F7R1_FB9 0x00000200U
2453 #define CAN_F7R1_FB10 0x00000400U
2454 #define CAN_F7R1_FB11 0x00000800U
2455 #define CAN_F7R1_FB12 0x00001000U
2456 #define CAN_F7R1_FB13 0x00002000U
2457 #define CAN_F7R1_FB14 0x00004000U
2458 #define CAN_F7R1_FB15 0x00008000U
2459 #define CAN_F7R1_FB16 0x00010000U
2460 #define CAN_F7R1_FB17 0x00020000U
2461 #define CAN_F7R1_FB18 0x00040000U
2462 #define CAN_F7R1_FB19 0x00080000U
2463 #define CAN_F7R1_FB20 0x00100000U
2464 #define CAN_F7R1_FB21 0x00200000U
2465 #define CAN_F7R1_FB22 0x00400000U
2466 #define CAN_F7R1_FB23 0x00800000U
2467 #define CAN_F7R1_FB24 0x01000000U
2468 #define CAN_F7R1_FB25 0x02000000U
2469 #define CAN_F7R1_FB26 0x04000000U
2470 #define CAN_F7R1_FB27 0x08000000U
2471 #define CAN_F7R1_FB28 0x10000000U
2472 #define CAN_F7R1_FB29 0x20000000U
2473 #define CAN_F7R1_FB30 0x40000000U
2474 #define CAN_F7R1_FB31 0x80000000U
2476 /******************* Bit definition for CAN_F8R1 register *******************/
2477 #define CAN_F8R1_FB0 0x00000001U
2478 #define CAN_F8R1_FB1 0x00000002U
2479 #define CAN_F8R1_FB2 0x00000004U
2480 #define CAN_F8R1_FB3 0x00000008U
2481 #define CAN_F8R1_FB4 0x00000010U
2482 #define CAN_F8R1_FB5 0x00000020U
2483 #define CAN_F8R1_FB6 0x00000040U
2484 #define CAN_F8R1_FB7 0x00000080U
2485 #define CAN_F8R1_FB8 0x00000100U
2486 #define CAN_F8R1_FB9 0x00000200U
2487 #define CAN_F8R1_FB10 0x00000400U
2488 #define CAN_F8R1_FB11 0x00000800U
2489 #define CAN_F8R1_FB12 0x00001000U
2490 #define CAN_F8R1_FB13 0x00002000U
2491 #define CAN_F8R1_FB14 0x00004000U
2492 #define CAN_F8R1_FB15 0x00008000U
2493 #define CAN_F8R1_FB16 0x00010000U
2494 #define CAN_F8R1_FB17 0x00020000U
2495 #define CAN_F8R1_FB18 0x00040000U
2496 #define CAN_F8R1_FB19 0x00080000U
2497 #define CAN_F8R1_FB20 0x00100000U
2498 #define CAN_F8R1_FB21 0x00200000U
2499 #define CAN_F8R1_FB22 0x00400000U
2500 #define CAN_F8R1_FB23 0x00800000U
2501 #define CAN_F8R1_FB24 0x01000000U
2502 #define CAN_F8R1_FB25 0x02000000U
2503 #define CAN_F8R1_FB26 0x04000000U
2504 #define CAN_F8R1_FB27 0x08000000U
2505 #define CAN_F8R1_FB28 0x10000000U
2506 #define CAN_F8R1_FB29 0x20000000U
2507 #define CAN_F8R1_FB30 0x40000000U
2508 #define CAN_F8R1_FB31 0x80000000U
2510 /******************* Bit definition for CAN_F9R1 register *******************/
2511 #define CAN_F9R1_FB0 0x00000001U
2512 #define CAN_F9R1_FB1 0x00000002U
2513 #define CAN_F9R1_FB2 0x00000004U
2514 #define CAN_F9R1_FB3 0x00000008U
2515 #define CAN_F9R1_FB4 0x00000010U
2516 #define CAN_F9R1_FB5 0x00000020U
2517 #define CAN_F9R1_FB6 0x00000040U
2518 #define CAN_F9R1_FB7 0x00000080U
2519 #define CAN_F9R1_FB8 0x00000100U
2520 #define CAN_F9R1_FB9 0x00000200U
2521 #define CAN_F9R1_FB10 0x00000400U
2522 #define CAN_F9R1_FB11 0x00000800U
2523 #define CAN_F9R1_FB12 0x00001000U
2524 #define CAN_F9R1_FB13 0x00002000U
2525 #define CAN_F9R1_FB14 0x00004000U
2526 #define CAN_F9R1_FB15 0x00008000U
2527 #define CAN_F9R1_FB16 0x00010000U
2528 #define CAN_F9R1_FB17 0x00020000U
2529 #define CAN_F9R1_FB18 0x00040000U
2530 #define CAN_F9R1_FB19 0x00080000U
2531 #define CAN_F9R1_FB20 0x00100000U
2532 #define CAN_F9R1_FB21 0x00200000U
2533 #define CAN_F9R1_FB22 0x00400000U
2534 #define CAN_F9R1_FB23 0x00800000U
2535 #define CAN_F9R1_FB24 0x01000000U
2536 #define CAN_F9R1_FB25 0x02000000U
2537 #define CAN_F9R1_FB26 0x04000000U
2538 #define CAN_F9R1_FB27 0x08000000U
2539 #define CAN_F9R1_FB28 0x10000000U
2540 #define CAN_F9R1_FB29 0x20000000U
2541 #define CAN_F9R1_FB30 0x40000000U
2542 #define CAN_F9R1_FB31 0x80000000U
2544 /******************* Bit definition for CAN_F10R1 register ******************/
2545 #define CAN_F10R1_FB0 0x00000001U
2546 #define CAN_F10R1_FB1 0x00000002U
2547 #define CAN_F10R1_FB2 0x00000004U
2548 #define CAN_F10R1_FB3 0x00000008U
2549 #define CAN_F10R1_FB4 0x00000010U
2550 #define CAN_F10R1_FB5 0x00000020U
2551 #define CAN_F10R1_FB6 0x00000040U
2552 #define CAN_F10R1_FB7 0x00000080U
2553 #define CAN_F10R1_FB8 0x00000100U
2554 #define CAN_F10R1_FB9 0x00000200U
2555 #define CAN_F10R1_FB10 0x00000400U
2556 #define CAN_F10R1_FB11 0x00000800U
2557 #define CAN_F10R1_FB12 0x00001000U
2558 #define CAN_F10R1_FB13 0x00002000U
2559 #define CAN_F10R1_FB14 0x00004000U
2560 #define CAN_F10R1_FB15 0x00008000U
2561 #define CAN_F10R1_FB16 0x00010000U
2562 #define CAN_F10R1_FB17 0x00020000U
2563 #define CAN_F10R1_FB18 0x00040000U
2564 #define CAN_F10R1_FB19 0x00080000U
2565 #define CAN_F10R1_FB20 0x00100000U
2566 #define CAN_F10R1_FB21 0x00200000U
2567 #define CAN_F10R1_FB22 0x00400000U
2568 #define CAN_F10R1_FB23 0x00800000U
2569 #define CAN_F10R1_FB24 0x01000000U
2570 #define CAN_F10R1_FB25 0x02000000U
2571 #define CAN_F10R1_FB26 0x04000000U
2572 #define CAN_F10R1_FB27 0x08000000U
2573 #define CAN_F10R1_FB28 0x10000000U
2574 #define CAN_F10R1_FB29 0x20000000U
2575 #define CAN_F10R1_FB30 0x40000000U
2576 #define CAN_F10R1_FB31 0x80000000U
2578 /******************* Bit definition for CAN_F11R1 register ******************/
2579 #define CAN_F11R1_FB0 0x00000001U
2580 #define CAN_F11R1_FB1 0x00000002U
2581 #define CAN_F11R1_FB2 0x00000004U
2582 #define CAN_F11R1_FB3 0x00000008U
2583 #define CAN_F11R1_FB4 0x00000010U
2584 #define CAN_F11R1_FB5 0x00000020U
2585 #define CAN_F11R1_FB6 0x00000040U
2586 #define CAN_F11R1_FB7 0x00000080U
2587 #define CAN_F11R1_FB8 0x00000100U
2588 #define CAN_F11R1_FB9 0x00000200U
2589 #define CAN_F11R1_FB10 0x00000400U
2590 #define CAN_F11R1_FB11 0x00000800U
2591 #define CAN_F11R1_FB12 0x00001000U
2592 #define CAN_F11R1_FB13 0x00002000U
2593 #define CAN_F11R1_FB14 0x00004000U
2594 #define CAN_F11R1_FB15 0x00008000U
2595 #define CAN_F11R1_FB16 0x00010000U
2596 #define CAN_F11R1_FB17 0x00020000U
2597 #define CAN_F11R1_FB18 0x00040000U
2598 #define CAN_F11R1_FB19 0x00080000U
2599 #define CAN_F11R1_FB20 0x00100000U
2600 #define CAN_F11R1_FB21 0x00200000U
2601 #define CAN_F11R1_FB22 0x00400000U
2602 #define CAN_F11R1_FB23 0x00800000U
2603 #define CAN_F11R1_FB24 0x01000000U
2604 #define CAN_F11R1_FB25 0x02000000U
2605 #define CAN_F11R1_FB26 0x04000000U
2606 #define CAN_F11R1_FB27 0x08000000U
2607 #define CAN_F11R1_FB28 0x10000000U
2608 #define CAN_F11R1_FB29 0x20000000U
2609 #define CAN_F11R1_FB30 0x40000000U
2610 #define CAN_F11R1_FB31 0x80000000U
2612 /******************* Bit definition for CAN_F12R1 register ******************/
2613 #define CAN_F12R1_FB0 0x00000001U
2614 #define CAN_F12R1_FB1 0x00000002U
2615 #define CAN_F12R1_FB2 0x00000004U
2616 #define CAN_F12R1_FB3 0x00000008U
2617 #define CAN_F12R1_FB4 0x00000010U
2618 #define CAN_F12R1_FB5 0x00000020U
2619 #define CAN_F12R1_FB6 0x00000040U
2620 #define CAN_F12R1_FB7 0x00000080U
2621 #define CAN_F12R1_FB8 0x00000100U
2622 #define CAN_F12R1_FB9 0x00000200U
2623 #define CAN_F12R1_FB10 0x00000400U
2624 #define CAN_F12R1_FB11 0x00000800U
2625 #define CAN_F12R1_FB12 0x00001000U
2626 #define CAN_F12R1_FB13 0x00002000U
2627 #define CAN_F12R1_FB14 0x00004000U
2628 #define CAN_F12R1_FB15 0x00008000U
2629 #define CAN_F12R1_FB16 0x00010000U
2630 #define CAN_F12R1_FB17 0x00020000U
2631 #define CAN_F12R1_FB18 0x00040000U
2632 #define CAN_F12R1_FB19 0x00080000U
2633 #define CAN_F12R1_FB20 0x00100000U
2634 #define CAN_F12R1_FB21 0x00200000U
2635 #define CAN_F12R1_FB22 0x00400000U
2636 #define CAN_F12R1_FB23 0x00800000U
2637 #define CAN_F12R1_FB24 0x01000000U
2638 #define CAN_F12R1_FB25 0x02000000U
2639 #define CAN_F12R1_FB26 0x04000000U
2640 #define CAN_F12R1_FB27 0x08000000U
2641 #define CAN_F12R1_FB28 0x10000000U
2642 #define CAN_F12R1_FB29 0x20000000U
2643 #define CAN_F12R1_FB30 0x40000000U
2644 #define CAN_F12R1_FB31 0x80000000U
2646 /******************* Bit definition for CAN_F13R1 register ******************/
2647 #define CAN_F13R1_FB0 0x00000001U
2648 #define CAN_F13R1_FB1 0x00000002U
2649 #define CAN_F13R1_FB2 0x00000004U
2650 #define CAN_F13R1_FB3 0x00000008U
2651 #define CAN_F13R1_FB4 0x00000010U
2652 #define CAN_F13R1_FB5 0x00000020U
2653 #define CAN_F13R1_FB6 0x00000040U
2654 #define CAN_F13R1_FB7 0x00000080U
2655 #define CAN_F13R1_FB8 0x00000100U
2656 #define CAN_F13R1_FB9 0x00000200U
2657 #define CAN_F13R1_FB10 0x00000400U
2658 #define CAN_F13R1_FB11 0x00000800U
2659 #define CAN_F13R1_FB12 0x00001000U
2660 #define CAN_F13R1_FB13 0x00002000U
2661 #define CAN_F13R1_FB14 0x00004000U
2662 #define CAN_F13R1_FB15 0x00008000U
2663 #define CAN_F13R1_FB16 0x00010000U
2664 #define CAN_F13R1_FB17 0x00020000U
2665 #define CAN_F13R1_FB18 0x00040000U
2666 #define CAN_F13R1_FB19 0x00080000U
2667 #define CAN_F13R1_FB20 0x00100000U
2668 #define CAN_F13R1_FB21 0x00200000U
2669 #define CAN_F13R1_FB22 0x00400000U
2670 #define CAN_F13R1_FB23 0x00800000U
2671 #define CAN_F13R1_FB24 0x01000000U
2672 #define CAN_F13R1_FB25 0x02000000U
2673 #define CAN_F13R1_FB26 0x04000000U
2674 #define CAN_F13R1_FB27 0x08000000U
2675 #define CAN_F13R1_FB28 0x10000000U
2676 #define CAN_F13R1_FB29 0x20000000U
2677 #define CAN_F13R1_FB30 0x40000000U
2678 #define CAN_F13R1_FB31 0x80000000U
2680 /******************* Bit definition for CAN_F0R2 register *******************/
2681 #define CAN_F0R2_FB0 0x00000001U
2682 #define CAN_F0R2_FB1 0x00000002U
2683 #define CAN_F0R2_FB2 0x00000004U
2684 #define CAN_F0R2_FB3 0x00000008U
2685 #define CAN_F0R2_FB4 0x00000010U
2686 #define CAN_F0R2_FB5 0x00000020U
2687 #define CAN_F0R2_FB6 0x00000040U
2688 #define CAN_F0R2_FB7 0x00000080U
2689 #define CAN_F0R2_FB8 0x00000100U
2690 #define CAN_F0R2_FB9 0x00000200U
2691 #define CAN_F0R2_FB10 0x00000400U
2692 #define CAN_F0R2_FB11 0x00000800U
2693 #define CAN_F0R2_FB12 0x00001000U
2694 #define CAN_F0R2_FB13 0x00002000U
2695 #define CAN_F0R2_FB14 0x00004000U
2696 #define CAN_F0R2_FB15 0x00008000U
2697 #define CAN_F0R2_FB16 0x00010000U
2698 #define CAN_F0R2_FB17 0x00020000U
2699 #define CAN_F0R2_FB18 0x00040000U
2700 #define CAN_F0R2_FB19 0x00080000U
2701 #define CAN_F0R2_FB20 0x00100000U
2702 #define CAN_F0R2_FB21 0x00200000U
2703 #define CAN_F0R2_FB22 0x00400000U
2704 #define CAN_F0R2_FB23 0x00800000U
2705 #define CAN_F0R2_FB24 0x01000000U
2706 #define CAN_F0R2_FB25 0x02000000U
2707 #define CAN_F0R2_FB26 0x04000000U
2708 #define CAN_F0R2_FB27 0x08000000U
2709 #define CAN_F0R2_FB28 0x10000000U
2710 #define CAN_F0R2_FB29 0x20000000U
2711 #define CAN_F0R2_FB30 0x40000000U
2712 #define CAN_F0R2_FB31 0x80000000U
2714 /******************* Bit definition for CAN_F1R2 register *******************/
2715 #define CAN_F1R2_FB0 0x00000001U
2716 #define CAN_F1R2_FB1 0x00000002U
2717 #define CAN_F1R2_FB2 0x00000004U
2718 #define CAN_F1R2_FB3 0x00000008U
2719 #define CAN_F1R2_FB4 0x00000010U
2720 #define CAN_F1R2_FB5 0x00000020U
2721 #define CAN_F1R2_FB6 0x00000040U
2722 #define CAN_F1R2_FB7 0x00000080U
2723 #define CAN_F1R2_FB8 0x00000100U
2724 #define CAN_F1R2_FB9 0x00000200U
2725 #define CAN_F1R2_FB10 0x00000400U
2726 #define CAN_F1R2_FB11 0x00000800U
2727 #define CAN_F1R2_FB12 0x00001000U
2728 #define CAN_F1R2_FB13 0x00002000U
2729 #define CAN_F1R2_FB14 0x00004000U
2730 #define CAN_F1R2_FB15 0x00008000U
2731 #define CAN_F1R2_FB16 0x00010000U
2732 #define CAN_F1R2_FB17 0x00020000U
2733 #define CAN_F1R2_FB18 0x00040000U
2734 #define CAN_F1R2_FB19 0x00080000U
2735 #define CAN_F1R2_FB20 0x00100000U
2736 #define CAN_F1R2_FB21 0x00200000U
2737 #define CAN_F1R2_FB22 0x00400000U
2738 #define CAN_F1R2_FB23 0x00800000U
2739 #define CAN_F1R2_FB24 0x01000000U
2740 #define CAN_F1R2_FB25 0x02000000U
2741 #define CAN_F1R2_FB26 0x04000000U
2742 #define CAN_F1R2_FB27 0x08000000U
2743 #define CAN_F1R2_FB28 0x10000000U
2744 #define CAN_F1R2_FB29 0x20000000U
2745 #define CAN_F1R2_FB30 0x40000000U
2746 #define CAN_F1R2_FB31 0x80000000U
2748 /******************* Bit definition for CAN_F2R2 register *******************/
2749 #define CAN_F2R2_FB0 0x00000001U
2750 #define CAN_F2R2_FB1 0x00000002U
2751 #define CAN_F2R2_FB2 0x00000004U
2752 #define CAN_F2R2_FB3 0x00000008U
2753 #define CAN_F2R2_FB4 0x00000010U
2754 #define CAN_F2R2_FB5 0x00000020U
2755 #define CAN_F2R2_FB6 0x00000040U
2756 #define CAN_F2R2_FB7 0x00000080U
2757 #define CAN_F2R2_FB8 0x00000100U
2758 #define CAN_F2R2_FB9 0x00000200U
2759 #define CAN_F2R2_FB10 0x00000400U
2760 #define CAN_F2R2_FB11 0x00000800U
2761 #define CAN_F2R2_FB12 0x00001000U
2762 #define CAN_F2R2_FB13 0x00002000U
2763 #define CAN_F2R2_FB14 0x00004000U
2764 #define CAN_F2R2_FB15 0x00008000U
2765 #define CAN_F2R2_FB16 0x00010000U
2766 #define CAN_F2R2_FB17 0x00020000U
2767 #define CAN_F2R2_FB18 0x00040000U
2768 #define CAN_F2R2_FB19 0x00080000U
2769 #define CAN_F2R2_FB20 0x00100000U
2770 #define CAN_F2R2_FB21 0x00200000U
2771 #define CAN_F2R2_FB22 0x00400000U
2772 #define CAN_F2R2_FB23 0x00800000U
2773 #define CAN_F2R2_FB24 0x01000000U
2774 #define CAN_F2R2_FB25 0x02000000U
2775 #define CAN_F2R2_FB26 0x04000000U
2776 #define CAN_F2R2_FB27 0x08000000U
2777 #define CAN_F2R2_FB28 0x10000000U
2778 #define CAN_F2R2_FB29 0x20000000U
2779 #define CAN_F2R2_FB30 0x40000000U
2780 #define CAN_F2R2_FB31 0x80000000U
2782 /******************* Bit definition for CAN_F3R2 register *******************/
2783 #define CAN_F3R2_FB0 0x00000001U
2784 #define CAN_F3R2_FB1 0x00000002U
2785 #define CAN_F3R2_FB2 0x00000004U
2786 #define CAN_F3R2_FB3 0x00000008U
2787 #define CAN_F3R2_FB4 0x00000010U
2788 #define CAN_F3R2_FB5 0x00000020U
2789 #define CAN_F3R2_FB6 0x00000040U
2790 #define CAN_F3R2_FB7 0x00000080U
2791 #define CAN_F3R2_FB8 0x00000100U
2792 #define CAN_F3R2_FB9 0x00000200U
2793 #define CAN_F3R2_FB10 0x00000400U
2794 #define CAN_F3R2_FB11 0x00000800U
2795 #define CAN_F3R2_FB12 0x00001000U
2796 #define CAN_F3R2_FB13 0x00002000U
2797 #define CAN_F3R2_FB14 0x00004000U
2798 #define CAN_F3R2_FB15 0x00008000U
2799 #define CAN_F3R2_FB16 0x00010000U
2800 #define CAN_F3R2_FB17 0x00020000U
2801 #define CAN_F3R2_FB18 0x00040000U
2802 #define CAN_F3R2_FB19 0x00080000U
2803 #define CAN_F3R2_FB20 0x00100000U
2804 #define CAN_F3R2_FB21 0x00200000U
2805 #define CAN_F3R2_FB22 0x00400000U
2806 #define CAN_F3R2_FB23 0x00800000U
2807 #define CAN_F3R2_FB24 0x01000000U
2808 #define CAN_F3R2_FB25 0x02000000U
2809 #define CAN_F3R2_FB26 0x04000000U
2810 #define CAN_F3R2_FB27 0x08000000U
2811 #define CAN_F3R2_FB28 0x10000000U
2812 #define CAN_F3R2_FB29 0x20000000U
2813 #define CAN_F3R2_FB30 0x40000000U
2814 #define CAN_F3R2_FB31 0x80000000U
2816 /******************* Bit definition for CAN_F4R2 register *******************/
2817 #define CAN_F4R2_FB0 0x00000001U
2818 #define CAN_F4R2_FB1 0x00000002U
2819 #define CAN_F4R2_FB2 0x00000004U
2820 #define CAN_F4R2_FB3 0x00000008U
2821 #define CAN_F4R2_FB4 0x00000010U
2822 #define CAN_F4R2_FB5 0x00000020U
2823 #define CAN_F4R2_FB6 0x00000040U
2824 #define CAN_F4R2_FB7 0x00000080U
2825 #define CAN_F4R2_FB8 0x00000100U
2826 #define CAN_F4R2_FB9 0x00000200U
2827 #define CAN_F4R2_FB10 0x00000400U
2828 #define CAN_F4R2_FB11 0x00000800U
2829 #define CAN_F4R2_FB12 0x00001000U
2830 #define CAN_F4R2_FB13 0x00002000U
2831 #define CAN_F4R2_FB14 0x00004000U
2832 #define CAN_F4R2_FB15 0x00008000U
2833 #define CAN_F4R2_FB16 0x00010000U
2834 #define CAN_F4R2_FB17 0x00020000U
2835 #define CAN_F4R2_FB18 0x00040000U
2836 #define CAN_F4R2_FB19 0x00080000U
2837 #define CAN_F4R2_FB20 0x00100000U
2838 #define CAN_F4R2_FB21 0x00200000U
2839 #define CAN_F4R2_FB22 0x00400000U
2840 #define CAN_F4R2_FB23 0x00800000U
2841 #define CAN_F4R2_FB24 0x01000000U
2842 #define CAN_F4R2_FB25 0x02000000U
2843 #define CAN_F4R2_FB26 0x04000000U
2844 #define CAN_F4R2_FB27 0x08000000U
2845 #define CAN_F4R2_FB28 0x10000000U
2846 #define CAN_F4R2_FB29 0x20000000U
2847 #define CAN_F4R2_FB30 0x40000000U
2848 #define CAN_F4R2_FB31 0x80000000U
2850 /******************* Bit definition for CAN_F5R2 register *******************/
2851 #define CAN_F5R2_FB0 0x00000001U
2852 #define CAN_F5R2_FB1 0x00000002U
2853 #define CAN_F5R2_FB2 0x00000004U
2854 #define CAN_F5R2_FB3 0x00000008U
2855 #define CAN_F5R2_FB4 0x00000010U
2856 #define CAN_F5R2_FB5 0x00000020U
2857 #define CAN_F5R2_FB6 0x00000040U
2858 #define CAN_F5R2_FB7 0x00000080U
2859 #define CAN_F5R2_FB8 0x00000100U
2860 #define CAN_F5R2_FB9 0x00000200U
2861 #define CAN_F5R2_FB10 0x00000400U
2862 #define CAN_F5R2_FB11 0x00000800U
2863 #define CAN_F5R2_FB12 0x00001000U
2864 #define CAN_F5R2_FB13 0x00002000U
2865 #define CAN_F5R2_FB14 0x00004000U
2866 #define CAN_F5R2_FB15 0x00008000U
2867 #define CAN_F5R2_FB16 0x00010000U
2868 #define CAN_F5R2_FB17 0x00020000U
2869 #define CAN_F5R2_FB18 0x00040000U
2870 #define CAN_F5R2_FB19 0x00080000U
2871 #define CAN_F5R2_FB20 0x00100000U
2872 #define CAN_F5R2_FB21 0x00200000U
2873 #define CAN_F5R2_FB22 0x00400000U
2874 #define CAN_F5R2_FB23 0x00800000U
2875 #define CAN_F5R2_FB24 0x01000000U
2876 #define CAN_F5R2_FB25 0x02000000U
2877 #define CAN_F5R2_FB26 0x04000000U
2878 #define CAN_F5R2_FB27 0x08000000U
2879 #define CAN_F5R2_FB28 0x10000000U
2880 #define CAN_F5R2_FB29 0x20000000U
2881 #define CAN_F5R2_FB30 0x40000000U
2882 #define CAN_F5R2_FB31 0x80000000U
2884 /******************* Bit definition for CAN_F6R2 register *******************/
2885 #define CAN_F6R2_FB0 0x00000001U
2886 #define CAN_F6R2_FB1 0x00000002U
2887 #define CAN_F6R2_FB2 0x00000004U
2888 #define CAN_F6R2_FB3 0x00000008U
2889 #define CAN_F6R2_FB4 0x00000010U
2890 #define CAN_F6R2_FB5 0x00000020U
2891 #define CAN_F6R2_FB6 0x00000040U
2892 #define CAN_F6R2_FB7 0x00000080U
2893 #define CAN_F6R2_FB8 0x00000100U
2894 #define CAN_F6R2_FB9 0x00000200U
2895 #define CAN_F6R2_FB10 0x00000400U
2896 #define CAN_F6R2_FB11 0x00000800U
2897 #define CAN_F6R2_FB12 0x00001000U
2898 #define CAN_F6R2_FB13 0x00002000U
2899 #define CAN_F6R2_FB14 0x00004000U
2900 #define CAN_F6R2_FB15 0x00008000U
2901 #define CAN_F6R2_FB16 0x00010000U
2902 #define CAN_F6R2_FB17 0x00020000U
2903 #define CAN_F6R2_FB18 0x00040000U
2904 #define CAN_F6R2_FB19 0x00080000U
2905 #define CAN_F6R2_FB20 0x00100000U
2906 #define CAN_F6R2_FB21 0x00200000U
2907 #define CAN_F6R2_FB22 0x00400000U
2908 #define CAN_F6R2_FB23 0x00800000U
2909 #define CAN_F6R2_FB24 0x01000000U
2910 #define CAN_F6R2_FB25 0x02000000U
2911 #define CAN_F6R2_FB26 0x04000000U
2912 #define CAN_F6R2_FB27 0x08000000U
2913 #define CAN_F6R2_FB28 0x10000000U
2914 #define CAN_F6R2_FB29 0x20000000U
2915 #define CAN_F6R2_FB30 0x40000000U
2916 #define CAN_F6R2_FB31 0x80000000U
2918 /******************* Bit definition for CAN_F7R2 register *******************/
2919 #define CAN_F7R2_FB0 0x00000001U
2920 #define CAN_F7R2_FB1 0x00000002U
2921 #define CAN_F7R2_FB2 0x00000004U
2922 #define CAN_F7R2_FB3 0x00000008U
2923 #define CAN_F7R2_FB4 0x00000010U
2924 #define CAN_F7R2_FB5 0x00000020U
2925 #define CAN_F7R2_FB6 0x00000040U
2926 #define CAN_F7R2_FB7 0x00000080U
2927 #define CAN_F7R2_FB8 0x00000100U
2928 #define CAN_F7R2_FB9 0x00000200U
2929 #define CAN_F7R2_FB10 0x00000400U
2930 #define CAN_F7R2_FB11 0x00000800U
2931 #define CAN_F7R2_FB12 0x00001000U
2932 #define CAN_F7R2_FB13 0x00002000U
2933 #define CAN_F7R2_FB14 0x00004000U
2934 #define CAN_F7R2_FB15 0x00008000U
2935 #define CAN_F7R2_FB16 0x00010000U
2936 #define CAN_F7R2_FB17 0x00020000U
2937 #define CAN_F7R2_FB18 0x00040000U
2938 #define CAN_F7R2_FB19 0x00080000U
2939 #define CAN_F7R2_FB20 0x00100000U
2940 #define CAN_F7R2_FB21 0x00200000U
2941 #define CAN_F7R2_FB22 0x00400000U
2942 #define CAN_F7R2_FB23 0x00800000U
2943 #define CAN_F7R2_FB24 0x01000000U
2944 #define CAN_F7R2_FB25 0x02000000U
2945 #define CAN_F7R2_FB26 0x04000000U
2946 #define CAN_F7R2_FB27 0x08000000U
2947 #define CAN_F7R2_FB28 0x10000000U
2948 #define CAN_F7R2_FB29 0x20000000U
2949 #define CAN_F7R2_FB30 0x40000000U
2950 #define CAN_F7R2_FB31 0x80000000U
2952 /******************* Bit definition for CAN_F8R2 register *******************/
2953 #define CAN_F8R2_FB0 0x00000001U
2954 #define CAN_F8R2_FB1 0x00000002U
2955 #define CAN_F8R2_FB2 0x00000004U
2956 #define CAN_F8R2_FB3 0x00000008U
2957 #define CAN_F8R2_FB4 0x00000010U
2958 #define CAN_F8R2_FB5 0x00000020U
2959 #define CAN_F8R2_FB6 0x00000040U
2960 #define CAN_F8R2_FB7 0x00000080U
2961 #define CAN_F8R2_FB8 0x00000100U
2962 #define CAN_F8R2_FB9 0x00000200U
2963 #define CAN_F8R2_FB10 0x00000400U
2964 #define CAN_F8R2_FB11 0x00000800U
2965 #define CAN_F8R2_FB12 0x00001000U
2966 #define CAN_F8R2_FB13 0x00002000U
2967 #define CAN_F8R2_FB14 0x00004000U
2968 #define CAN_F8R2_FB15 0x00008000U
2969 #define CAN_F8R2_FB16 0x00010000U
2970 #define CAN_F8R2_FB17 0x00020000U
2971 #define CAN_F8R2_FB18 0x00040000U
2972 #define CAN_F8R2_FB19 0x00080000U
2973 #define CAN_F8R2_FB20 0x00100000U
2974 #define CAN_F8R2_FB21 0x00200000U
2975 #define CAN_F8R2_FB22 0x00400000U
2976 #define CAN_F8R2_FB23 0x00800000U
2977 #define CAN_F8R2_FB24 0x01000000U
2978 #define CAN_F8R2_FB25 0x02000000U
2979 #define CAN_F8R2_FB26 0x04000000U
2980 #define CAN_F8R2_FB27 0x08000000U
2981 #define CAN_F8R2_FB28 0x10000000U
2982 #define CAN_F8R2_FB29 0x20000000U
2983 #define CAN_F8R2_FB30 0x40000000U
2984 #define CAN_F8R2_FB31 0x80000000U
2986 /******************* Bit definition for CAN_F9R2 register *******************/
2987 #define CAN_F9R2_FB0 0x00000001U
2988 #define CAN_F9R2_FB1 0x00000002U
2989 #define CAN_F9R2_FB2 0x00000004U
2990 #define CAN_F9R2_FB3 0x00000008U
2991 #define CAN_F9R2_FB4 0x00000010U
2992 #define CAN_F9R2_FB5 0x00000020U
2993 #define CAN_F9R2_FB6 0x00000040U
2994 #define CAN_F9R2_FB7 0x00000080U
2995 #define CAN_F9R2_FB8 0x00000100U
2996 #define CAN_F9R2_FB9 0x00000200U
2997 #define CAN_F9R2_FB10 0x00000400U
2998 #define CAN_F9R2_FB11 0x00000800U
2999 #define CAN_F9R2_FB12 0x00001000U
3000 #define CAN_F9R2_FB13 0x00002000U
3001 #define CAN_F9R2_FB14 0x00004000U
3002 #define CAN_F9R2_FB15 0x00008000U
3003 #define CAN_F9R2_FB16 0x00010000U
3004 #define CAN_F9R2_FB17 0x00020000U
3005 #define CAN_F9R2_FB18 0x00040000U
3006 #define CAN_F9R2_FB19 0x00080000U
3007 #define CAN_F9R2_FB20 0x00100000U
3008 #define CAN_F9R2_FB21 0x00200000U
3009 #define CAN_F9R2_FB22 0x00400000U
3010 #define CAN_F9R2_FB23 0x00800000U
3011 #define CAN_F9R2_FB24 0x01000000U
3012 #define CAN_F9R2_FB25 0x02000000U
3013 #define CAN_F9R2_FB26 0x04000000U
3014 #define CAN_F9R2_FB27 0x08000000U
3015 #define CAN_F9R2_FB28 0x10000000U
3016 #define CAN_F9R2_FB29 0x20000000U
3017 #define CAN_F9R2_FB30 0x40000000U
3018 #define CAN_F9R2_FB31 0x80000000U
3020 /******************* Bit definition for CAN_F10R2 register ******************/
3021 #define CAN_F10R2_FB0 0x00000001U
3022 #define CAN_F10R2_FB1 0x00000002U
3023 #define CAN_F10R2_FB2 0x00000004U
3024 #define CAN_F10R2_FB3 0x00000008U
3025 #define CAN_F10R2_FB4 0x00000010U
3026 #define CAN_F10R2_FB5 0x00000020U
3027 #define CAN_F10R2_FB6 0x00000040U
3028 #define CAN_F10R2_FB7 0x00000080U
3029 #define CAN_F10R2_FB8 0x00000100U
3030 #define CAN_F10R2_FB9 0x00000200U
3031 #define CAN_F10R2_FB10 0x00000400U
3032 #define CAN_F10R2_FB11 0x00000800U
3033 #define CAN_F10R2_FB12 0x00001000U
3034 #define CAN_F10R2_FB13 0x00002000U
3035 #define CAN_F10R2_FB14 0x00004000U
3036 #define CAN_F10R2_FB15 0x00008000U
3037 #define CAN_F10R2_FB16 0x00010000U
3038 #define CAN_F10R2_FB17 0x00020000U
3039 #define CAN_F10R2_FB18 0x00040000U
3040 #define CAN_F10R2_FB19 0x00080000U
3041 #define CAN_F10R2_FB20 0x00100000U
3042 #define CAN_F10R2_FB21 0x00200000U
3043 #define CAN_F10R2_FB22 0x00400000U
3044 #define CAN_F10R2_FB23 0x00800000U
3045 #define CAN_F10R2_FB24 0x01000000U
3046 #define CAN_F10R2_FB25 0x02000000U
3047 #define CAN_F10R2_FB26 0x04000000U
3048 #define CAN_F10R2_FB27 0x08000000U
3049 #define CAN_F10R2_FB28 0x10000000U
3050 #define CAN_F10R2_FB29 0x20000000U
3051 #define CAN_F10R2_FB30 0x40000000U
3052 #define CAN_F10R2_FB31 0x80000000U
3054 /******************* Bit definition for CAN_F11R2 register ******************/
3055 #define CAN_F11R2_FB0 0x00000001U
3056 #define CAN_F11R2_FB1 0x00000002U
3057 #define CAN_F11R2_FB2 0x00000004U
3058 #define CAN_F11R2_FB3 0x00000008U
3059 #define CAN_F11R2_FB4 0x00000010U
3060 #define CAN_F11R2_FB5 0x00000020U
3061 #define CAN_F11R2_FB6 0x00000040U
3062 #define CAN_F11R2_FB7 0x00000080U
3063 #define CAN_F11R2_FB8 0x00000100U
3064 #define CAN_F11R2_FB9 0x00000200U
3065 #define CAN_F11R2_FB10 0x00000400U
3066 #define CAN_F11R2_FB11 0x00000800U
3067 #define CAN_F11R2_FB12 0x00001000U
3068 #define CAN_F11R2_FB13 0x00002000U
3069 #define CAN_F11R2_FB14 0x00004000U
3070 #define CAN_F11R2_FB15 0x00008000U
3071 #define CAN_F11R2_FB16 0x00010000U
3072 #define CAN_F11R2_FB17 0x00020000U
3073 #define CAN_F11R2_FB18 0x00040000U
3074 #define CAN_F11R2_FB19 0x00080000U
3075 #define CAN_F11R2_FB20 0x00100000U
3076 #define CAN_F11R2_FB21 0x00200000U
3077 #define CAN_F11R2_FB22 0x00400000U
3078 #define CAN_F11R2_FB23 0x00800000U
3079 #define CAN_F11R2_FB24 0x01000000U
3080 #define CAN_F11R2_FB25 0x02000000U
3081 #define CAN_F11R2_FB26 0x04000000U
3082 #define CAN_F11R2_FB27 0x08000000U
3083 #define CAN_F11R2_FB28 0x10000000U
3084 #define CAN_F11R2_FB29 0x20000000U
3085 #define CAN_F11R2_FB30 0x40000000U
3086 #define CAN_F11R2_FB31 0x80000000U
3088 /******************* Bit definition for CAN_F12R2 register ******************/
3089 #define CAN_F12R2_FB0 0x00000001U
3090 #define CAN_F12R2_FB1 0x00000002U
3091 #define CAN_F12R2_FB2 0x00000004U
3092 #define CAN_F12R2_FB3 0x00000008U
3093 #define CAN_F12R2_FB4 0x00000010U
3094 #define CAN_F12R2_FB5 0x00000020U
3095 #define CAN_F12R2_FB6 0x00000040U
3096 #define CAN_F12R2_FB7 0x00000080U
3097 #define CAN_F12R2_FB8 0x00000100U
3098 #define CAN_F12R2_FB9 0x00000200U
3099 #define CAN_F12R2_FB10 0x00000400U
3100 #define CAN_F12R2_FB11 0x00000800U
3101 #define CAN_F12R2_FB12 0x00001000U
3102 #define CAN_F12R2_FB13 0x00002000U
3103 #define CAN_F12R2_FB14 0x00004000U
3104 #define CAN_F12R2_FB15 0x00008000U
3105 #define CAN_F12R2_FB16 0x00010000U
3106 #define CAN_F12R2_FB17 0x00020000U
3107 #define CAN_F12R2_FB18 0x00040000U
3108 #define CAN_F12R2_FB19 0x00080000U
3109 #define CAN_F12R2_FB20 0x00100000U
3110 #define CAN_F12R2_FB21 0x00200000U
3111 #define CAN_F12R2_FB22 0x00400000U
3112 #define CAN_F12R2_FB23 0x00800000U
3113 #define CAN_F12R2_FB24 0x01000000U
3114 #define CAN_F12R2_FB25 0x02000000U
3115 #define CAN_F12R2_FB26 0x04000000U
3116 #define CAN_F12R2_FB27 0x08000000U
3117 #define CAN_F12R2_FB28 0x10000000U
3118 #define CAN_F12R2_FB29 0x20000000U
3119 #define CAN_F12R2_FB30 0x40000000U
3120 #define CAN_F12R2_FB31 0x80000000U
3122 /******************* Bit definition for CAN_F13R2 register ******************/
3123 #define CAN_F13R2_FB0 0x00000001U
3124 #define CAN_F13R2_FB1 0x00000002U
3125 #define CAN_F13R2_FB2 0x00000004U
3126 #define CAN_F13R2_FB3 0x00000008U
3127 #define CAN_F13R2_FB4 0x00000010U
3128 #define CAN_F13R2_FB5 0x00000020U
3129 #define CAN_F13R2_FB6 0x00000040U
3130 #define CAN_F13R2_FB7 0x00000080U
3131 #define CAN_F13R2_FB8 0x00000100U
3132 #define CAN_F13R2_FB9 0x00000200U
3133 #define CAN_F13R2_FB10 0x00000400U
3134 #define CAN_F13R2_FB11 0x00000800U
3135 #define CAN_F13R2_FB12 0x00001000U
3136 #define CAN_F13R2_FB13 0x00002000U
3137 #define CAN_F13R2_FB14 0x00004000U
3138 #define CAN_F13R2_FB15 0x00008000U
3139 #define CAN_F13R2_FB16 0x00010000U
3140 #define CAN_F13R2_FB17 0x00020000U
3141 #define CAN_F13R2_FB18 0x00040000U
3142 #define CAN_F13R2_FB19 0x00080000U
3143 #define CAN_F13R2_FB20 0x00100000U
3144 #define CAN_F13R2_FB21 0x00200000U
3145 #define CAN_F13R2_FB22 0x00400000U
3146 #define CAN_F13R2_FB23 0x00800000U
3147 #define CAN_F13R2_FB24 0x01000000U
3148 #define CAN_F13R2_FB25 0x02000000U
3149 #define CAN_F13R2_FB26 0x04000000U
3150 #define CAN_F13R2_FB27 0x08000000U
3151 #define CAN_F13R2_FB28 0x10000000U
3152 #define CAN_F13R2_FB29 0x20000000U
3153 #define CAN_F13R2_FB30 0x40000000U
3154 #define CAN_F13R2_FB31 0x80000000U
3156 /******************************************************************************/
3157 /* */
3158 /* HDMI-CEC (CEC) */
3159 /* */
3160 /******************************************************************************/
3161 
3162 /******************* Bit definition for CEC_CR register *********************/
3163 #define CEC_CR_CECEN 0x00000001U
3164 #define CEC_CR_TXSOM 0x00000002U
3165 #define CEC_CR_TXEOM 0x00000004U
3167 /******************* Bit definition for CEC_CFGR register *******************/
3168 #define CEC_CFGR_SFT 0x00000007U
3169 #define CEC_CFGR_RXTOL 0x00000008U
3170 #define CEC_CFGR_BRESTP 0x00000010U
3171 #define CEC_CFGR_BREGEN 0x00000020U
3172 #define CEC_CFGR_LBPEGEN 0x00000040U
3173 #define CEC_CFGR_BRDNOGEN 0x00000080U
3174 #define CEC_CFGR_SFTOPT 0x00000100U
3175 #define CEC_CFGR_OAR 0x7FFF0000U
3176 #define CEC_CFGR_LSTN 0x80000000U
3178 /******************* Bit definition for CEC_TXDR register *******************/
3179 #define CEC_TXDR_TXD 0x000000FFU
3181 /******************* Bit definition for CEC_RXDR register *******************/
3182 #define CEC_TXDR_RXD 0x000000FFU
3184 /******************* Bit definition for CEC_ISR register ********************/
3185 #define CEC_ISR_RXBR 0x00000001U
3186 #define CEC_ISR_RXEND 0x00000002U
3187 #define CEC_ISR_RXOVR 0x00000004U
3188 #define CEC_ISR_BRE 0x00000008U
3189 #define CEC_ISR_SBPE 0x00000010U
3190 #define CEC_ISR_LBPE 0x00000020U
3191 #define CEC_ISR_RXACKE 0x00000040U
3192 #define CEC_ISR_ARBLST 0x00000080U
3193 #define CEC_ISR_TXBR 0x00000100U
3194 #define CEC_ISR_TXEND 0x00000200U
3195 #define CEC_ISR_TXUDR 0x00000400U
3196 #define CEC_ISR_TXERR 0x00000800U
3197 #define CEC_ISR_TXACKE 0x00001000U
3199 /******************* Bit definition for CEC_IER register ********************/
3200 #define CEC_IER_RXBRIE 0x00000001U
3201 #define CEC_IER_RXENDIE 0x00000002U
3202 #define CEC_IER_RXOVRIE 0x00000004U
3203 #define CEC_IER_BREIE 0x00000008U
3204 #define CEC_IER_SBPEIE 0x00000010U
3205 #define CEC_IER_LBPEIE 0x00000020U
3206 #define CEC_IER_RXACKEIE 0x00000040U
3207 #define CEC_IER_ARBLSTIE 0x00000080U
3208 #define CEC_IER_TXBRIE 0x00000100U
3209 #define CEC_IER_TXENDIE 0x00000200U
3210 #define CEC_IER_TXUDRIE 0x00000400U
3211 #define CEC_IER_TXERRIE 0x00000800U
3212 #define CEC_IER_TXACKEIE 0x00001000U
3214 /******************************************************************************/
3215 /* */
3216 /* CRC calculation unit */
3217 /* */
3218 /******************************************************************************/
3219 /******************* Bit definition for CRC_DR register *********************/
3220 #define CRC_DR_DR 0xFFFFFFFFU
3222 /******************* Bit definition for CRC_IDR register ********************/
3223 #define CRC_IDR_IDR 0x000000FFU
3225 /******************** Bit definition for CRC_CR register ********************/
3226 #define CRC_CR_RESET 0x00000001U
3227 #define CRC_CR_POLYSIZE 0x00000018U
3228 #define CRC_CR_POLYSIZE_0 0x00000008U
3229 #define CRC_CR_POLYSIZE_1 0x00000010U
3230 #define CRC_CR_REV_IN 0x00000060U
3231 #define CRC_CR_REV_IN_0 0x00000020U
3232 #define CRC_CR_REV_IN_1 0x00000040U
3233 #define CRC_CR_REV_OUT 0x00000080U
3235 /******************* Bit definition for CRC_INIT register *******************/
3236 #define CRC_INIT_INIT 0xFFFFFFFFU
3238 /******************* Bit definition for CRC_POL register ********************/
3239 #define CRC_POL_POL 0xFFFFFFFFU
3242 /******************************************************************************/
3243 /* */
3244 /* Digital to Analog Converter */
3245 /* */
3246 /******************************************************************************/
3247 /******************** Bit definition for DAC_CR register ********************/
3248 #define DAC_CR_EN1 0x00000001U
3249 #define DAC_CR_BOFF1 0x00000002U
3250 #define DAC_CR_TEN1 0x00000004U
3251 #define DAC_CR_TSEL1 0x00000038U
3252 #define DAC_CR_TSEL1_0 0x00000008U
3253 #define DAC_CR_TSEL1_1 0x00000010U
3254 #define DAC_CR_TSEL1_2 0x00000020U
3255 #define DAC_CR_WAVE1 0x000000C0U
3256 #define DAC_CR_WAVE1_0 0x00000040U
3257 #define DAC_CR_WAVE1_1 0x00000080U
3258 #define DAC_CR_MAMP1 0x00000F00U
3259 #define DAC_CR_MAMP1_0 0x00000100U
3260 #define DAC_CR_MAMP1_1 0x00000200U
3261 #define DAC_CR_MAMP1_2 0x00000400U
3262 #define DAC_CR_MAMP1_3 0x00000800U
3263 #define DAC_CR_DMAEN1 0x00001000U
3264 #define DAC_CR_DMAUDRIE1 0x00002000U
3265 #define DAC_CR_EN2 0x00010000U
3266 #define DAC_CR_BOFF2 0x00020000U
3267 #define DAC_CR_TEN2 0x00040000U
3268 #define DAC_CR_TSEL2 0x00380000U
3269 #define DAC_CR_TSEL2_0 0x00080000U
3270 #define DAC_CR_TSEL2_1 0x00100000U
3271 #define DAC_CR_TSEL2_2 0x00200000U
3272 #define DAC_CR_WAVE2 0x00C00000U
3273 #define DAC_CR_WAVE2_0 0x00400000U
3274 #define DAC_CR_WAVE2_1 0x00800000U
3275 #define DAC_CR_MAMP2 0x0F000000U
3276 #define DAC_CR_MAMP2_0 0x01000000U
3277 #define DAC_CR_MAMP2_1 0x02000000U
3278 #define DAC_CR_MAMP2_2 0x04000000U
3279 #define DAC_CR_MAMP2_3 0x08000000U
3280 #define DAC_CR_DMAEN2 0x10000000U
3281 #define DAC_CR_DMAUDRIE2 0x20000000U
3283 /***************** Bit definition for DAC_SWTRIGR register ******************/
3284 #define DAC_SWTRIGR_SWTRIG1 0x01U
3285 #define DAC_SWTRIGR_SWTRIG2 0x02U
3287 /***************** Bit definition for DAC_DHR12R1 register ******************/
3288 #define DAC_DHR12R1_DACC1DHR 0x0FFFU
3290 /***************** Bit definition for DAC_DHR12L1 register ******************/
3291 #define DAC_DHR12L1_DACC1DHR 0xFFF0U
3293 /****************** Bit definition for DAC_DHR8R1 register ******************/
3294 #define DAC_DHR8R1_DACC1DHR 0xFFU
3296 /***************** Bit definition for DAC_DHR12R2 register ******************/
3297 #define DAC_DHR12R2_DACC2DHR 0x0FFFU
3299 /***************** Bit definition for DAC_DHR12L2 register ******************/
3300 #define DAC_DHR12L2_DACC2DHR 0xFFF0U
3302 /****************** Bit definition for DAC_DHR8R2 register ******************/
3303 #define DAC_DHR8R2_DACC2DHR 0xFFU
3305 /***************** Bit definition for DAC_DHR12RD register ******************/
3306 #define DAC_DHR12RD_DACC1DHR 0x00000FFFU
3307 #define DAC_DHR12RD_DACC2DHR 0x0FFF0000U
3309 /***************** Bit definition for DAC_DHR12LD register ******************/
3310 #define DAC_DHR12LD_DACC1DHR 0x0000FFF0U
3311 #define DAC_DHR12LD_DACC2DHR 0xFFF00000U
3313 /****************** Bit definition for DAC_DHR8RD register ******************/
3314 #define DAC_DHR8RD_DACC1DHR 0x00FFU
3315 #define DAC_DHR8RD_DACC2DHR 0xFF00U
3317 /******************* Bit definition for DAC_DOR1 register *******************/
3318 #define DAC_DOR1_DACC1DOR 0x0FFFU
3320 /******************* Bit definition for DAC_DOR2 register *******************/
3321 #define DAC_DOR2_DACC2DOR 0x0FFFU
3323 /******************** Bit definition for DAC_SR register ********************/
3324 #define DAC_SR_DMAUDR1 0x00002000U
3325 #define DAC_SR_DMAUDR2 0x20000000U
3327 /******************************************************************************/
3328 /* */
3329 /* Digital Filter for Sigma Delta Modulators */
3330 /* */
3331 /******************************************************************************/
3332 
3333 /**************** DFSDM channel configuration registers ********************/
3334 
3335 /*************** Bit definition for DFSDM_CHCFGR1 register ******************/
3336 #define DFSDM_CHCFGR1_DFSDMEN 0x80000000U
3337 #define DFSDM_CHCFGR1_CKOUTSRC 0x40000000U
3338 #define DFSDM_CHCFGR1_CKOUTDIV 0x00FF0000U
3339 #define DFSDM_CHCFGR1_DATPACK 0x0000C000U
3340 #define DFSDM_CHCFGR1_DATPACK_1 0x00008000U
3341 #define DFSDM_CHCFGR1_DATPACK_0 0x00004000U
3342 #define DFSDM_CHCFGR1_DATMPX 0x00003000U
3343 #define DFSDM_CHCFGR1_DATMPX_1 0x00002000U
3344 #define DFSDM_CHCFGR1_DATMPX_0 0x00001000U
3345 #define DFSDM_CHCFGR1_CHINSEL 0x00000100U
3346 #define DFSDM_CHCFGR1_CHEN 0x00000080U
3347 #define DFSDM_CHCFGR1_CKABEN 0x00000040U
3348 #define DFSDM_CHCFGR1_SCDEN 0x00000020U
3349 #define DFSDM_CHCFGR1_SPICKSEL 0x0000000CU
3350 #define DFSDM_CHCFGR1_SPICKSEL_1 0x00000008U
3351 #define DFSDM_CHCFGR1_SPICKSEL_0 0x00000004U
3352 #define DFSDM_CHCFGR1_SITP 0x00000003U
3353 #define DFSDM_CHCFGR1_SITP_1 0x00000002U
3354 #define DFSDM_CHCFGR1_SITP_0 0x00000001U
3356 /*************** Bit definition for DFSDM_CHCFGR2 register ******************/
3357 #define DFSDM_CHCFGR2_OFFSET 0xFFFFFF00U
3358 #define DFSDM_CHCFGR2_DTRBS 0x000000F8U
3360 /****************** Bit definition for DFSDM_CHAWSCDR register *****************/
3361 #define DFSDM_CHAWSCDR_AWFORD 0x00C00000U
3362 #define DFSDM_CHAWSCDR_AWFORD_1 0x00800000U
3363 #define DFSDM_CHAWSCDR_AWFORD_0 0x00400000U
3364 #define DFSDM_CHAWSCDR_AWFOSR 0x001F0000U
3365 #define DFSDM_CHAWSCDR_BKSCD 0x0000F000U
3366 #define DFSDM_CHAWSCDR_SCDT 0x000000FFU
3368 /**************** Bit definition for DFSDM_CHWDATR register *******************/
3369 #define DFSDM_CHWDATR_WDATA 0x0000FFFFU
3371 /**************** Bit definition for DFSDM_CHDATINR register *****************/
3372 #define DFSDM_CHDATINR_INDAT0 0x0000FFFFU
3373 #define DFSDM_CHDATINR_INDAT1 0xFFFF0000U
3375 /************************ DFSDM module registers ****************************/
3376 
3377 /******************** Bit definition for DFSDM_FLTCR1 register *******************/
3378 #define DFSDM_FLTCR1_AWFSEL 0x40000000U
3379 #define DFSDM_FLTCR1_FAST 0x20000000U
3380 #define DFSDM_FLTCR1_RCH 0x07000000U
3381 #define DFSDM_FLTCR1_RDMAEN 0x00200000U
3382 #define DFSDM_FLTCR1_RSYNC 0x00080000U
3383 #define DFSDM_FLTCR1_RCONT 0x00040000U
3384 #define DFSDM_FLTCR1_RSWSTART 0x00020000U
3385 #define DFSDM_FLTCR1_JEXTEN 0x00006000U
3386 #define DFSDM_FLTCR1_JEXTEN_1 0x00004000U
3387 #define DFSDM_FLTCR1_JEXTEN_0 0x00002000U
3388 #define DFSDM_FLTCR1_JEXTSEL 0x00001F00U
3389 #define DFSDM_FLTCR1_JEXTSEL_0 0x00000100U
3390 #define DFSDM_FLTCR1_JEXTSEL_1 0x00000200U
3391 #define DFSDM_FLTCR1_JEXTSEL_2 0x00000400U
3392 #define DFSDM_FLTCR1_JEXTSEL_3 0x00000800U
3393 #define DFSDM_FLTCR1_JEXTSEL_4 0x00001000U
3394 #define DFSDM_FLTCR1_JDMAEN 0x00000020U
3395 #define DFSDM_FLTCR1_JSCAN 0x00000010U
3396 #define DFSDM_FLTCR1_JSYNC 0x00000008U
3397 #define DFSDM_FLTCR1_JSWSTART 0x00000002U
3398 #define DFSDM_FLTCR1_DFEN 0x00000001U
3400 /******************** Bit definition for DFSDM_FLTCR2 register *******************/
3401 #define DFSDM_FLTCR2_AWDCH 0x00FF0000U
3402 #define DFSDM_FLTCR2_EXCH 0x0000FF00U
3403 #define DFSDM_FLTCR2_CKABIE 0x00000040U
3404 #define DFSDM_FLTCR2_SCDIE 0x00000020U
3405 #define DFSDM_FLTCR2_AWDIE 0x00000010U
3406 #define DFSDM_FLTCR2_ROVRIE 0x00000008U
3407 #define DFSDM_FLTCR2_JOVRIE 0x00000004U
3408 #define DFSDM_FLTCR2_REOCIE 0x00000002U
3409 #define DFSDM_FLTCR2_JEOCIE 0x00000001U
3411 /******************** Bit definition for DFSDM_FLTISR register *******************/
3412 #define DFSDM_FLTISR_SCDF 0xFF000000U
3413 #define DFSDM_FLTISR_CKABF 0x00FF0000U
3414 #define DFSDM_FLTISR_RCIP 0x00004000U
3415 #define DFSDM_FLTISR_JCIP 0x00002000U
3416 #define DFSDM_FLTISR_AWDF 0x00000010U
3417 #define DFSDM_FLTISR_ROVRF 0x00000008U
3418 #define DFSDM_FLTISR_JOVRF 0x00000004U
3419 #define DFSDM_FLTISR_REOCF 0x00000002U
3420 #define DFSDM_FLTISR_JEOCF 0x00000001U
3422 /******************** Bit definition for DFSDM_FLTICR register *******************/
3423 #define DFSDM_FLTICR_CLRSCSDF 0xFF000000U
3424 #define DFSDM_FLTICR_CLRCKABF 0x00FF0000U
3425 #define DFSDM_FLTICR_CLRROVRF 0x00000008U
3426 #define DFSDM_FLTICR_CLRJOVRF 0x00000004U
3428 /******************* Bit definition for DFSDM_FLTJCHGR register ******************/
3429 #define DFSDM_FLTJCHGR_JCHG 0x000000FFU
3431 /******************** Bit definition for DFSDM_FLTFCR register *******************/
3432 #define DFSDM_FLTFCR_FORD 0xE0000000U
3433 #define DFSDM_FLTFCR_FORD_2 0x80000000U
3434 #define DFSDM_FLTFCR_FORD_1 0x40000000U
3435 #define DFSDM_FLTFCR_FORD_0 0x20000000U
3436 #define DFSDM_FLTFCR_FOSR 0x03FF0000U
3437 #define DFSDM_FLTFCR_IOSR 0x000000FFU
3439 /****************** Bit definition for DFSDM_FLTJDATAR register *****************/
3440 #define DFSDM_FLTJDATAR_JDATA 0xFFFFFF00U
3441 #define DFSDM_FLTJDATAR_JDATACH 0x00000007U
3443 /****************** Bit definition for DFSDM_FLTRDATAR register *****************/
3444 #define DFSDM_FLTRDATAR_RDATA 0xFFFFFF00U
3445 #define DFSDM_FLTRDATAR_RPEND 0x00000010U
3446 #define DFSDM_FLTRDATAR_RDATACH 0x00000007U
3448 /****************** Bit definition for DFSDM_FLTAWHTR register ******************/
3449 #define DFSDM_FLTAWHTR_AWHT 0xFFFFFF00U
3450 #define DFSDM_FLTAWHTR_BKAWH 0x0000000FU
3452 /****************** Bit definition for DFSDM_FLTAWLTR register ******************/
3453 #define DFSDM_FLTAWLTR_AWLT 0xFFFFFF00U
3454 #define DFSDM_FLTAWLTR_BKAWL 0x0000000FU
3456 /****************** Bit definition for DFSDM_FLTAWSR register ******************/
3457 #define DFSDM_FLTAWSR_AWHTF 0x0000FF00U
3458 #define DFSDM_FLTAWSR_AWLTF 0x000000FFU
3460 /****************** Bit definition for DFSDM_FLTAWCFR register *****************/
3461 #define DFSDM_FLTAWCFR_CLRAWHTF 0x0000FF00U
3462 #define DFSDM_FLTAWCFR_CLRAWLTF 0x000000FFU
3464 /****************** Bit definition for DFSDM_FLTEXMAX register ******************/
3465 #define DFSDM_FLTEXMAX_EXMAX 0xFFFFFF00U
3466 #define DFSDM_FLTEXMAX_EXMAXCH 0x00000007U
3468 /****************** Bit definition for DFSDM_FLTEXMIN register ******************/
3469 #define DFSDM_FLTEXMIN_EXMIN 0xFFFFFF00U
3470 #define DFSDM_FLTEXMIN_EXMINCH 0x00000007U
3472 /****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/
3473 #define DFSDM_FLTCNVTIMR_CNVCNT 0xFFFFFFF0U
3475 /******************************************************************************/
3476 /* */
3477 /* Debug MCU */
3478 /* */
3479 /******************************************************************************/
3480 
3481 /******************************************************************************/
3482 /* */
3483 /* DCMI */
3484 /* */
3485 /******************************************************************************/
3486 /******************** Bits definition for DCMI_CR register ******************/
3487 #define DCMI_CR_CAPTURE 0x00000001U
3488 #define DCMI_CR_CM 0x00000002U
3489 #define DCMI_CR_CROP 0x00000004U
3490 #define DCMI_CR_JPEG 0x00000008U
3491 #define DCMI_CR_ESS 0x00000010U
3492 #define DCMI_CR_PCKPOL 0x00000020U
3493 #define DCMI_CR_HSPOL 0x00000040U
3494 #define DCMI_CR_VSPOL 0x00000080U
3495 #define DCMI_CR_FCRC_0 0x00000100U
3496 #define DCMI_CR_FCRC_1 0x00000200U
3497 #define DCMI_CR_EDM_0 0x00000400U
3498 #define DCMI_CR_EDM_1 0x00000800U
3499 #define DCMI_CR_CRE 0x00001000U
3500 #define DCMI_CR_ENABLE 0x00004000U
3501 #define DCMI_CR_BSM 0x00030000U
3502 #define DCMI_CR_BSM_0 0x00010000U
3503 #define DCMI_CR_BSM_1 0x00020000U
3504 #define DCMI_CR_OEBS 0x00040000U
3505 #define DCMI_CR_LSM 0x00080000U
3506 #define DCMI_CR_OELS 0x00100000U
3507 
3508 /******************** Bits definition for DCMI_SR register ******************/
3509 #define DCMI_SR_HSYNC 0x00000001U
3510 #define DCMI_SR_VSYNC 0x00000002U
3511 #define DCMI_SR_FNE 0x00000004U
3512 
3513 /******************** Bits definition for DCMI_RIS register ****************/
3514 #define DCMI_RIS_FRAME_RIS 0x00000001U
3515 #define DCMI_RIS_OVR_RIS 0x00000002U
3516 #define DCMI_RIS_ERR_RIS 0x00000004U
3517 #define DCMI_RIS_VSYNC_RIS 0x00000008U
3518 #define DCMI_RIS_LINE_RIS 0x00000010U
3519 
3520 /* Legacy defines */
3521 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
3522 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
3523 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
3524 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
3525 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
3526 
3527 /******************** Bits definition for DCMI_IER register *****************/
3528 #define DCMI_IER_FRAME_IE 0x00000001U
3529 #define DCMI_IER_OVR_IE 0x00000002U
3530 #define DCMI_IER_ERR_IE 0x00000004U
3531 #define DCMI_IER_VSYNC_IE 0x00000008U
3532 #define DCMI_IER_LINE_IE 0x00000010U
3533 
3534 
3535 /******************** Bits definition for DCMI_MIS register *****************/
3536 #define DCMI_MIS_FRAME_MIS 0x00000001U
3537 #define DCMI_MIS_OVR_MIS 0x00000002U
3538 #define DCMI_MIS_ERR_MIS 0x00000004U
3539 #define DCMI_MIS_VSYNC_MIS 0x00000008U
3540 #define DCMI_MIS_LINE_MIS 0x00000010U
3541 
3542 
3543 /******************** Bits definition for DCMI_ICR register *****************/
3544 #define DCMI_ICR_FRAME_ISC 0x00000001U
3545 #define DCMI_ICR_OVR_ISC 0x00000002U
3546 #define DCMI_ICR_ERR_ISC 0x00000004U
3547 #define DCMI_ICR_VSYNC_ISC 0x00000008U
3548 #define DCMI_ICR_LINE_ISC 0x00000010U
3549 
3550 
3551 /******************** Bits definition for DCMI_ESCR register ******************/
3552 #define DCMI_ESCR_FSC 0x000000FFU
3553 #define DCMI_ESCR_LSC 0x0000FF00U
3554 #define DCMI_ESCR_LEC 0x00FF0000U
3555 #define DCMI_ESCR_FEC 0xFF000000U
3556 
3557 /******************** Bits definition for DCMI_ESUR register ******************/
3558 #define DCMI_ESUR_FSU 0x000000FFU
3559 #define DCMI_ESUR_LSU 0x0000FF00U
3560 #define DCMI_ESUR_LEU 0x00FF0000U
3561 #define DCMI_ESUR_FEU 0xFF000000U
3562 
3563 /******************** Bits definition for DCMI_CWSTRT register ******************/
3564 #define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
3565 #define DCMI_CWSTRT_VST 0x1FFF0000U
3566 
3567 /******************** Bits definition for DCMI_CWSIZE register ******************/
3568 #define DCMI_CWSIZE_CAPCNT 0x00003FFFU
3569 #define DCMI_CWSIZE_VLINE 0x3FFF0000U
3570 
3571 /******************** Bits definition for DCMI_DR register ******************/
3572 #define DCMI_DR_BYTE0 0x000000FFU
3573 #define DCMI_DR_BYTE1 0x0000FF00U
3574 #define DCMI_DR_BYTE2 0x00FF0000U
3575 #define DCMI_DR_BYTE3 0xFF000000U
3576 
3577 /******************************************************************************/
3578 /* */
3579 /* DMA Controller */
3580 /* */
3581 /******************************************************************************/
3582 /******************** Bits definition for DMA_SxCR register *****************/
3583 #define DMA_SxCR_CHSEL 0x1E000000U
3584 #define DMA_SxCR_CHSEL_0 0x02000000U
3585 #define DMA_SxCR_CHSEL_1 0x04000000U
3586 #define DMA_SxCR_CHSEL_2 0x08000000U
3587 #define DMA_SxCR_CHSEL_3 0x10000000U
3588 #define DMA_SxCR_MBURST 0x01800000U
3589 #define DMA_SxCR_MBURST_0 0x00800000U
3590 #define DMA_SxCR_MBURST_1 0x01000000U
3591 #define DMA_SxCR_PBURST 0x00600000U
3592 #define DMA_SxCR_PBURST_0 0x00200000U
3593 #define DMA_SxCR_PBURST_1 0x00400000U
3594 #define DMA_SxCR_CT 0x00080000U
3595 #define DMA_SxCR_DBM 0x00040000U
3596 #define DMA_SxCR_PL 0x00030000U
3597 #define DMA_SxCR_PL_0 0x00010000U
3598 #define DMA_SxCR_PL_1 0x00020000U
3599 #define DMA_SxCR_PINCOS 0x00008000U
3600 #define DMA_SxCR_MSIZE 0x00006000U
3601 #define DMA_SxCR_MSIZE_0 0x00002000U
3602 #define DMA_SxCR_MSIZE_1 0x00004000U
3603 #define DMA_SxCR_PSIZE 0x00001800U
3604 #define DMA_SxCR_PSIZE_0 0x00000800U
3605 #define DMA_SxCR_PSIZE_1 0x00001000U
3606 #define DMA_SxCR_MINC 0x00000400U
3607 #define DMA_SxCR_PINC 0x00000200U
3608 #define DMA_SxCR_CIRC 0x00000100U
3609 #define DMA_SxCR_DIR 0x000000C0U
3610 #define DMA_SxCR_DIR_0 0x00000040U
3611 #define DMA_SxCR_DIR_1 0x00000080U
3612 #define DMA_SxCR_PFCTRL 0x00000020U
3613 #define DMA_SxCR_TCIE 0x00000010U
3614 #define DMA_SxCR_HTIE 0x00000008U
3615 #define DMA_SxCR_TEIE 0x00000004U
3616 #define DMA_SxCR_DMEIE 0x00000002U
3617 #define DMA_SxCR_EN 0x00000001U
3618 
3619 /******************** Bits definition for DMA_SxCNDTR register **************/
3620 #define DMA_SxNDT 0x0000FFFFU
3621 #define DMA_SxNDT_0 0x00000001U
3622 #define DMA_SxNDT_1 0x00000002U
3623 #define DMA_SxNDT_2 0x00000004U
3624 #define DMA_SxNDT_3 0x00000008U
3625 #define DMA_SxNDT_4 0x00000010U
3626 #define DMA_SxNDT_5 0x00000020U
3627 #define DMA_SxNDT_6 0x00000040U
3628 #define DMA_SxNDT_7 0x00000080U
3629 #define DMA_SxNDT_8 0x00000100U
3630 #define DMA_SxNDT_9 0x00000200U
3631 #define DMA_SxNDT_10 0x00000400U
3632 #define DMA_SxNDT_11 0x00000800U
3633 #define DMA_SxNDT_12 0x00001000U
3634 #define DMA_SxNDT_13 0x00002000U
3635 #define DMA_SxNDT_14 0x00004000U
3636 #define DMA_SxNDT_15 0x00008000U
3637 
3638 /******************** Bits definition for DMA_SxFCR register ****************/
3639 #define DMA_SxFCR_FEIE 0x00000080U
3640 #define DMA_SxFCR_FS 0x00000038U
3641 #define DMA_SxFCR_FS_0 0x00000008U
3642 #define DMA_SxFCR_FS_1 0x00000010U
3643 #define DMA_SxFCR_FS_2 0x00000020U
3644 #define DMA_SxFCR_DMDIS 0x00000004U
3645 #define DMA_SxFCR_FTH 0x00000003U
3646 #define DMA_SxFCR_FTH_0 0x00000001U
3647 #define DMA_SxFCR_FTH_1 0x00000002U
3648 
3649 /******************** Bits definition for DMA_LISR register *****************/
3650 #define DMA_LISR_TCIF3 0x08000000U
3651 #define DMA_LISR_HTIF3 0x04000000U
3652 #define DMA_LISR_TEIF3 0x02000000U
3653 #define DMA_LISR_DMEIF3 0x01000000U
3654 #define DMA_LISR_FEIF3 0x00400000U
3655 #define DMA_LISR_TCIF2 0x00200000U
3656 #define DMA_LISR_HTIF2 0x00100000U
3657 #define DMA_LISR_TEIF2 0x00080000U
3658 #define DMA_LISR_DMEIF2 0x00040000U
3659 #define DMA_LISR_FEIF2 0x00010000U
3660 #define DMA_LISR_TCIF1 0x00000800U
3661 #define DMA_LISR_HTIF1 0x00000400U
3662 #define DMA_LISR_TEIF1 0x00000200U
3663 #define DMA_LISR_DMEIF1 0x00000100U
3664 #define DMA_LISR_FEIF1 0x00000040U
3665 #define DMA_LISR_TCIF0 0x00000020U
3666 #define DMA_LISR_HTIF0 0x00000010U
3667 #define DMA_LISR_TEIF0 0x00000008U
3668 #define DMA_LISR_DMEIF0 0x00000004U
3669 #define DMA_LISR_FEIF0 0x00000001U
3670 
3671 /******************** Bits definition for DMA_HISR register *****************/
3672 #define DMA_HISR_TCIF7 0x08000000U
3673 #define DMA_HISR_HTIF7 0x04000000U
3674 #define DMA_HISR_TEIF7 0x02000000U
3675 #define DMA_HISR_DMEIF7 0x01000000U
3676 #define DMA_HISR_FEIF7 0x00400000U
3677 #define DMA_HISR_TCIF6 0x00200000U
3678 #define DMA_HISR_HTIF6 0x00100000U
3679 #define DMA_HISR_TEIF6 0x00080000U
3680 #define DMA_HISR_DMEIF6 0x00040000U
3681 #define DMA_HISR_FEIF6 0x00010000U
3682 #define DMA_HISR_TCIF5 0x00000800U
3683 #define DMA_HISR_HTIF5 0x00000400U
3684 #define DMA_HISR_TEIF5 0x00000200U
3685 #define DMA_HISR_DMEIF5 0x00000100U
3686 #define DMA_HISR_FEIF5 0x00000040U
3687 #define DMA_HISR_TCIF4 0x00000020U
3688 #define DMA_HISR_HTIF4 0x00000010U
3689 #define DMA_HISR_TEIF4 0x00000008U
3690 #define DMA_HISR_DMEIF4 0x00000004U
3691 #define DMA_HISR_FEIF4 0x00000001U
3692 
3693 /******************** Bits definition for DMA_LIFCR register ****************/
3694 #define DMA_LIFCR_CTCIF3 0x08000000U
3695 #define DMA_LIFCR_CHTIF3 0x04000000U
3696 #define DMA_LIFCR_CTEIF3 0x02000000U
3697 #define DMA_LIFCR_CDMEIF3 0x01000000U
3698 #define DMA_LIFCR_CFEIF3 0x00400000U
3699 #define DMA_LIFCR_CTCIF2 0x00200000U
3700 #define DMA_LIFCR_CHTIF2 0x00100000U
3701 #define DMA_LIFCR_CTEIF2 0x00080000U
3702 #define DMA_LIFCR_CDMEIF2 0x00040000U
3703 #define DMA_LIFCR_CFEIF2 0x00010000U
3704 #define DMA_LIFCR_CTCIF1 0x00000800U
3705 #define DMA_LIFCR_CHTIF1 0x00000400U
3706 #define DMA_LIFCR_CTEIF1 0x00000200U
3707 #define DMA_LIFCR_CDMEIF1 0x00000100U
3708 #define DMA_LIFCR_CFEIF1 0x00000040U
3709 #define DMA_LIFCR_CTCIF0 0x00000020U
3710 #define DMA_LIFCR_CHTIF0 0x00000010U
3711 #define DMA_LIFCR_CTEIF0 0x00000008U
3712 #define DMA_LIFCR_CDMEIF0 0x00000004U
3713 #define DMA_LIFCR_CFEIF0 0x00000001U
3714 
3715 /******************** Bits definition for DMA_HIFCR register ****************/
3716 #define DMA_HIFCR_CTCIF7 0x08000000U
3717 #define DMA_HIFCR_CHTIF7 0x04000000U
3718 #define DMA_HIFCR_CTEIF7 0x02000000U
3719 #define DMA_HIFCR_CDMEIF7 0x01000000U
3720 #define DMA_HIFCR_CFEIF7 0x00400000U
3721 #define DMA_HIFCR_CTCIF6 0x00200000U
3722 #define DMA_HIFCR_CHTIF6 0x00100000U
3723 #define DMA_HIFCR_CTEIF6 0x00080000U
3724 #define DMA_HIFCR_CDMEIF6 0x00040000U
3725 #define DMA_HIFCR_CFEIF6 0x00010000U
3726 #define DMA_HIFCR_CTCIF5 0x00000800U
3727 #define DMA_HIFCR_CHTIF5 0x00000400U
3728 #define DMA_HIFCR_CTEIF5 0x00000200U
3729 #define DMA_HIFCR_CDMEIF5 0x00000100U
3730 #define DMA_HIFCR_CFEIF5 0x00000040U
3731 #define DMA_HIFCR_CTCIF4 0x00000020U
3732 #define DMA_HIFCR_CHTIF4 0x00000010U
3733 #define DMA_HIFCR_CTEIF4 0x00000008U
3734 #define DMA_HIFCR_CDMEIF4 0x00000004U
3735 #define DMA_HIFCR_CFEIF4 0x00000001U
3736 
3737 /******************************************************************************/
3738 /* */
3739 /* AHB Master DMA2D Controller (DMA2D) */
3740 /* */
3741 /******************************************************************************/
3742 
3743 /******************** Bit definition for DMA2D_CR register ******************/
3744 
3745 #define DMA2D_CR_START 0x00000001U
3746 #define DMA2D_CR_SUSP 0x00000002U
3747 #define DMA2D_CR_ABORT 0x00000004U
3748 #define DMA2D_CR_TEIE 0x00000100U
3749 #define DMA2D_CR_TCIE 0x00000200U
3750 #define DMA2D_CR_TWIE 0x00000400U
3751 #define DMA2D_CR_CAEIE 0x00000800U
3752 #define DMA2D_CR_CTCIE 0x00001000U
3753 #define DMA2D_CR_CEIE 0x00002000U
3754 #define DMA2D_CR_MODE 0x00030000U
3755 #define DMA2D_CR_MODE_0 0x00010000U
3756 #define DMA2D_CR_MODE_1 0x00020000U
3758 /******************** Bit definition for DMA2D_ISR register *****************/
3759 
3760 #define DMA2D_ISR_TEIF 0x00000001U
3761 #define DMA2D_ISR_TCIF 0x00000002U
3762 #define DMA2D_ISR_TWIF 0x00000004U
3763 #define DMA2D_ISR_CAEIF 0x00000008U
3764 #define DMA2D_ISR_CTCIF 0x00000010U
3765 #define DMA2D_ISR_CEIF 0x00000020U
3767 /******************** Bit definition for DMA2D_IFCR register ****************/
3768 
3769 #define DMA2D_IFCR_CTEIF 0x00000001U
3770 #define DMA2D_IFCR_CTCIF 0x00000002U
3771 #define DMA2D_IFCR_CTWIF 0x00000004U
3772 #define DMA2D_IFCR_CAECIF 0x00000008U
3773 #define DMA2D_IFCR_CCTCIF 0x00000010U
3774 #define DMA2D_IFCR_CCEIF 0x00000020U
3776 /* Legacy defines */
3777 #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF
3778 #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF
3779 #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF
3780 #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF
3781 #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF
3782 #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF
3784 /******************** Bit definition for DMA2D_FGMAR register ***************/
3785 
3786 #define DMA2D_FGMAR_MA 0xFFFFFFFFU
3788 /******************** Bit definition for DMA2D_FGOR register ****************/
3789 
3790 #define DMA2D_FGOR_LO 0x00003FFFU
3792 /******************** Bit definition for DMA2D_BGMAR register ***************/
3793 
3794 #define DMA2D_BGMAR_MA 0xFFFFFFFFU
3796 /******************** Bit definition for DMA2D_BGOR register ****************/
3797 
3798 #define DMA2D_BGOR_LO 0x00003FFFU
3800 /******************** Bit definition for DMA2D_FGPFCCR register *************/
3801 
3802 #define DMA2D_FGPFCCR_CM 0x0000000FU
3803 #define DMA2D_FGPFCCR_CM_0 0x00000001U
3804 #define DMA2D_FGPFCCR_CM_1 0x00000002U
3805 #define DMA2D_FGPFCCR_CM_2 0x00000004U
3806 #define DMA2D_FGPFCCR_CM_3 0x00000008U
3807 #define DMA2D_FGPFCCR_CCM 0x00000010U
3808 #define DMA2D_FGPFCCR_START 0x00000020U
3809 #define DMA2D_FGPFCCR_CS 0x0000FF00U
3810 #define DMA2D_FGPFCCR_AM 0x00030000U
3811 #define DMA2D_FGPFCCR_AM_0 0x00010000U
3812 #define DMA2D_FGPFCCR_AM_1 0x00020000U
3813 #define DMA2D_FGPFCCR_AI 0x00100000U
3814 #define DMA2D_FGPFCCR_RBS 0x00200000U
3815 #define DMA2D_FGPFCCR_ALPHA 0xFF000000U
3817 /******************** Bit definition for DMA2D_FGCOLR register **************/
3818 
3819 #define DMA2D_FGCOLR_BLUE 0x000000FFU
3820 #define DMA2D_FGCOLR_GREEN 0x0000FF00U
3821 #define DMA2D_FGCOLR_RED 0x00FF0000U
3823 /******************** Bit definition for DMA2D_BGPFCCR register *************/
3824 
3825 #define DMA2D_BGPFCCR_CM 0x0000000FU
3826 #define DMA2D_BGPFCCR_CM_0 0x00000001U
3827 #define DMA2D_BGPFCCR_CM_1 0x00000002U
3828 #define DMA2D_BGPFCCR_CM_2 0x00000004U
3829 #define DMA2D_FGPFCCR_CM_3 0x00000008U
3830 #define DMA2D_BGPFCCR_CCM 0x00000010U
3831 #define DMA2D_BGPFCCR_START 0x00000020U
3832 #define DMA2D_BGPFCCR_CS 0x0000FF00U
3833 #define DMA2D_BGPFCCR_AM 0x00030000U
3834 #define DMA2D_BGPFCCR_AM_0 0x00010000U
3835 #define DMA2D_BGPFCCR_AM_1 0x00020000U
3836 #define DMA2D_BGPFCCR_AI 0x00100000U
3837 #define DMA2D_BGPFCCR_RBS 0x00200000U
3838 #define DMA2D_BGPFCCR_ALPHA 0xFF000000U
3840 /******************** Bit definition for DMA2D_BGCOLR register **************/
3841 
3842 #define DMA2D_BGCOLR_BLUE 0x000000FFU
3843 #define DMA2D_BGCOLR_GREEN 0x0000FF00U
3844 #define DMA2D_BGCOLR_RED 0x00FF0000U
3846 /******************** Bit definition for DMA2D_FGCMAR register **************/
3847 
3848 #define DMA2D_FGCMAR_MA 0xFFFFFFFFU
3850 /******************** Bit definition for DMA2D_BGCMAR register **************/
3851 
3852 #define DMA2D_BGCMAR_MA 0xFFFFFFFFU
3854 /******************** Bit definition for DMA2D_OPFCCR register **************/
3855 
3856 #define DMA2D_OPFCCR_CM 0x00000007U
3857 #define DMA2D_OPFCCR_CM_0 0x00000001U
3858 #define DMA2D_OPFCCR_CM_1 0x00000002U
3859 #define DMA2D_OPFCCR_CM_2 0x00000004U
3860 #define DMA2D_OPFCCR_AI 0x00100000U
3861 #define DMA2D_OPFCCR_RBS 0x00200000U
3863 /******************** Bit definition for DMA2D_OCOLR register ***************/
3864 
3867 #define DMA2D_OCOLR_BLUE_1 0x000000FFU
3868 #define DMA2D_OCOLR_GREEN_1 0x0000FF00U
3869 #define DMA2D_OCOLR_RED_1 0x00FF0000U
3870 #define DMA2D_OCOLR_ALPHA_1 0xFF000000U
3873 #define DMA2D_OCOLR_BLUE_2 0x0000001FU
3874 #define DMA2D_OCOLR_GREEN_2 0x000007E0U
3875 #define DMA2D_OCOLR_RED_2 0x0000F800U
3878 #define DMA2D_OCOLR_BLUE_3 0x0000001FU
3879 #define DMA2D_OCOLR_GREEN_3 0x000003E0U
3880 #define DMA2D_OCOLR_RED_3 0x00007C00U
3881 #define DMA2D_OCOLR_ALPHA_3 0x00008000U
3884 #define DMA2D_OCOLR_BLUE_4 0x0000000FU
3885 #define DMA2D_OCOLR_GREEN_4 0x000000F0U
3886 #define DMA2D_OCOLR_RED_4 0x00000F00U
3887 #define DMA2D_OCOLR_ALPHA_4 0x0000F000U
3889 /******************** Bit definition for DMA2D_OMAR register ****************/
3890 
3891 #define DMA2D_OMAR_MA 0xFFFFFFFFU
3893 /******************** Bit definition for DMA2D_OOR register *****************/
3894 
3895 #define DMA2D_OOR_LO 0x00003FFFU
3897 /******************** Bit definition for DMA2D_NLR register *****************/
3898 
3899 #define DMA2D_NLR_NL 0x0000FFFFU
3900 #define DMA2D_NLR_PL 0x3FFF0000U
3902 /******************** Bit definition for DMA2D_LWR register *****************/
3903 
3904 #define DMA2D_LWR_LW 0x0000FFFFU
3906 /******************** Bit definition for DMA2D_AMTCR register ***************/
3907 
3908 #define DMA2D_AMTCR_EN 0x00000001U
3909 #define DMA2D_AMTCR_DT 0x0000FF00U
3912 /******************** Bit definition for DMA2D_FGCLUT register **************/
3913 
3914 /******************** Bit definition for DMA2D_BGCLUT register **************/
3915 
3916 
3917 /******************************************************************************/
3918 /* */
3919 /* External Interrupt/Event Controller */
3920 /* */
3921 /******************************************************************************/
3922 /******************* Bit definition for EXTI_IMR register *******************/
3923 #define EXTI_IMR_MR0 0x00000001U
3924 #define EXTI_IMR_MR1 0x00000002U
3925 #define EXTI_IMR_MR2 0x00000004U
3926 #define EXTI_IMR_MR3 0x00000008U
3927 #define EXTI_IMR_MR4 0x00000010U
3928 #define EXTI_IMR_MR5 0x00000020U
3929 #define EXTI_IMR_MR6 0x00000040U
3930 #define EXTI_IMR_MR7 0x00000080U
3931 #define EXTI_IMR_MR8 0x00000100U
3932 #define EXTI_IMR_MR9 0x00000200U
3933 #define EXTI_IMR_MR10 0x00000400U
3934 #define EXTI_IMR_MR11 0x00000800U
3935 #define EXTI_IMR_MR12 0x00001000U
3936 #define EXTI_IMR_MR13 0x00002000U
3937 #define EXTI_IMR_MR14 0x00004000U
3938 #define EXTI_IMR_MR15 0x00008000U
3939 #define EXTI_IMR_MR16 0x00010000U
3940 #define EXTI_IMR_MR17 0x00020000U
3941 #define EXTI_IMR_MR18 0x00040000U
3942 #define EXTI_IMR_MR19 0x00080000U
3943 #define EXTI_IMR_MR20 0x00100000U
3944 #define EXTI_IMR_MR21 0x00200000U
3945 #define EXTI_IMR_MR22 0x00400000U
3946 #define EXTI_IMR_MR23 0x00800000U
3947 #define EXTI_IMR_MR24 0x01000000U
3949 /* Reference Defines */
3950 #define EXTI_IMR_IM0 EXTI_IMR_MR0
3951 #define EXTI_IMR_IM1 EXTI_IMR_MR1
3952 #define EXTI_IMR_IM2 EXTI_IMR_MR2
3953 #define EXTI_IMR_IM3 EXTI_IMR_MR3
3954 #define EXTI_IMR_IM4 EXTI_IMR_MR4
3955 #define EXTI_IMR_IM5 EXTI_IMR_MR5
3956 #define EXTI_IMR_IM6 EXTI_IMR_MR6
3957 #define EXTI_IMR_IM7 EXTI_IMR_MR7
3958 #define EXTI_IMR_IM8 EXTI_IMR_MR8
3959 #define EXTI_IMR_IM9 EXTI_IMR_MR9
3960 #define EXTI_IMR_IM10 EXTI_IMR_MR10
3961 #define EXTI_IMR_IM11 EXTI_IMR_MR11
3962 #define EXTI_IMR_IM12 EXTI_IMR_MR12
3963 #define EXTI_IMR_IM13 EXTI_IMR_MR13
3964 #define EXTI_IMR_IM14 EXTI_IMR_MR14
3965 #define EXTI_IMR_IM15 EXTI_IMR_MR15
3966 #define EXTI_IMR_IM16 EXTI_IMR_MR16
3967 #define EXTI_IMR_IM17 EXTI_IMR_MR17
3968 #define EXTI_IMR_IM18 EXTI_IMR_MR18
3969 #define EXTI_IMR_IM19 EXTI_IMR_MR19
3970 #define EXTI_IMR_IM20 EXTI_IMR_MR20
3971 #define EXTI_IMR_IM21 EXTI_IMR_MR21
3972 #define EXTI_IMR_IM22 EXTI_IMR_MR22
3973 #define EXTI_IMR_IM23 EXTI_IMR_MR23
3974 #define EXTI_IMR_IM24 EXTI_IMR_MR24
3975 
3976 #define EXTI_IMR_IM 0x01FFFFFFU
3978 /******************* Bit definition for EXTI_EMR register *******************/
3979 #define EXTI_EMR_MR0 0x00000001U
3980 #define EXTI_EMR_MR1 0x00000002U
3981 #define EXTI_EMR_MR2 0x00000004U
3982 #define EXTI_EMR_MR3 0x00000008U
3983 #define EXTI_EMR_MR4 0x00000010U
3984 #define EXTI_EMR_MR5 0x00000020U
3985 #define EXTI_EMR_MR6 0x00000040U
3986 #define EXTI_EMR_MR7 0x00000080U
3987 #define EXTI_EMR_MR8 0x00000100U
3988 #define EXTI_EMR_MR9 0x00000200U
3989 #define EXTI_EMR_MR10 0x00000400U
3990 #define EXTI_EMR_MR11 0x00000800U
3991 #define EXTI_EMR_MR12 0x00001000U
3992 #define EXTI_EMR_MR13 0x00002000U
3993 #define EXTI_EMR_MR14 0x00004000U
3994 #define EXTI_EMR_MR15 0x00008000U
3995 #define EXTI_EMR_MR16 0x00010000U
3996 #define EXTI_EMR_MR17 0x00020000U
3997 #define EXTI_EMR_MR18 0x00040000U
3998 #define EXTI_EMR_MR19 0x00080000U
3999 #define EXTI_EMR_MR20 0x00100000U
4000 #define EXTI_EMR_MR21 0x00200000U
4001 #define EXTI_EMR_MR22 0x00400000U
4002 #define EXTI_EMR_MR23 0x00800000U
4003 #define EXTI_EMR_MR24 0x01000000U
4005 /* Reference Defines */
4006 #define EXTI_EMR_EM0 EXTI_EMR_MR0
4007 #define EXTI_EMR_EM1 EXTI_EMR_MR1
4008 #define EXTI_EMR_EM2 EXTI_EMR_MR2
4009 #define EXTI_EMR_EM3 EXTI_EMR_MR3
4010 #define EXTI_EMR_EM4 EXTI_EMR_MR4
4011 #define EXTI_EMR_EM5 EXTI_EMR_MR5
4012 #define EXTI_EMR_EM6 EXTI_EMR_MR6
4013 #define EXTI_EMR_EM7 EXTI_EMR_MR7
4014 #define EXTI_EMR_EM8 EXTI_EMR_MR8
4015 #define EXTI_EMR_EM9 EXTI_EMR_MR9
4016 #define EXTI_EMR_EM10 EXTI_EMR_MR10
4017 #define EXTI_EMR_EM11 EXTI_EMR_MR11
4018 #define EXTI_EMR_EM12 EXTI_EMR_MR12
4019 #define EXTI_EMR_EM13 EXTI_EMR_MR13
4020 #define EXTI_EMR_EM14 EXTI_EMR_MR14
4021 #define EXTI_EMR_EM15 EXTI_EMR_MR15
4022 #define EXTI_EMR_EM16 EXTI_EMR_MR16
4023 #define EXTI_EMR_EM17 EXTI_EMR_MR17
4024 #define EXTI_EMR_EM18 EXTI_EMR_MR18
4025 #define EXTI_EMR_EM19 EXTI_EMR_MR19
4026 #define EXTI_EMR_EM20 EXTI_EMR_MR20
4027 #define EXTI_EMR_EM21 EXTI_EMR_MR21
4028 #define EXTI_EMR_EM22 EXTI_EMR_MR22
4029 #define EXTI_EMR_EM23 EXTI_EMR_MR23
4030 #define EXTI_EMR_EM24 EXTI_EMR_MR24
4031 
4032 
4033 /****************** Bit definition for EXTI_RTSR register *******************/
4034 #define EXTI_RTSR_TR0 0x00000001U
4035 #define EXTI_RTSR_TR1 0x00000002U
4036 #define EXTI_RTSR_TR2 0x00000004U
4037 #define EXTI_RTSR_TR3 0x00000008U
4038 #define EXTI_RTSR_TR4 0x00000010U
4039 #define EXTI_RTSR_TR5 0x00000020U
4040 #define EXTI_RTSR_TR6 0x00000040U
4041 #define EXTI_RTSR_TR7 0x00000080U
4042 #define EXTI_RTSR_TR8 0x00000100U
4043 #define EXTI_RTSR_TR9 0x00000200U
4044 #define EXTI_RTSR_TR10 0x00000400U
4045 #define EXTI_RTSR_TR11 0x00000800U
4046 #define EXTI_RTSR_TR12 0x00001000U
4047 #define EXTI_RTSR_TR13 0x00002000U
4048 #define EXTI_RTSR_TR14 0x00004000U
4049 #define EXTI_RTSR_TR15 0x00008000U
4050 #define EXTI_RTSR_TR16 0x00010000U
4051 #define EXTI_RTSR_TR17 0x00020000U
4052 #define EXTI_RTSR_TR18 0x00040000U
4053 #define EXTI_RTSR_TR19 0x00080000U
4054 #define EXTI_RTSR_TR20 0x00100000U
4055 #define EXTI_RTSR_TR21 0x00200000U
4056 #define EXTI_RTSR_TR22 0x00400000U
4057 #define EXTI_RTSR_TR23 0x00800000U
4058 #define EXTI_RTSR_TR24 0x01000000U
4060 /****************** Bit definition for EXTI_FTSR register *******************/
4061 #define EXTI_FTSR_TR0 0x00000001U
4062 #define EXTI_FTSR_TR1 0x00000002U
4063 #define EXTI_FTSR_TR2 0x00000004U
4064 #define EXTI_FTSR_TR3 0x00000008U
4065 #define EXTI_FTSR_TR4 0x00000010U
4066 #define EXTI_FTSR_TR5 0x00000020U
4067 #define EXTI_FTSR_TR6 0x00000040U
4068 #define EXTI_FTSR_TR7 0x00000080U
4069 #define EXTI_FTSR_TR8 0x00000100U
4070 #define EXTI_FTSR_TR9 0x00000200U
4071 #define EXTI_FTSR_TR10 0x00000400U
4072 #define EXTI_FTSR_TR11 0x00000800U
4073 #define EXTI_FTSR_TR12 0x00001000U
4074 #define EXTI_FTSR_TR13 0x00002000U
4075 #define EXTI_FTSR_TR14 0x00004000U
4076 #define EXTI_FTSR_TR15 0x00008000U
4077 #define EXTI_FTSR_TR16 0x00010000U
4078 #define EXTI_FTSR_TR17 0x00020000U
4079 #define EXTI_FTSR_TR18 0x00040000U
4080 #define EXTI_FTSR_TR19 0x00080000U
4081 #define EXTI_FTSR_TR20 0x00100000U
4082 #define EXTI_FTSR_TR21 0x00200000U
4083 #define EXTI_FTSR_TR22 0x00400000U
4084 #define EXTI_FTSR_TR23 0x00800000U
4085 #define EXTI_FTSR_TR24 0x01000000U
4087 /****************** Bit definition for EXTI_SWIER register ******************/
4088 #define EXTI_SWIER_SWIER0 0x00000001U
4089 #define EXTI_SWIER_SWIER1 0x00000002U
4090 #define EXTI_SWIER_SWIER2 0x00000004U
4091 #define EXTI_SWIER_SWIER3 0x00000008U
4092 #define EXTI_SWIER_SWIER4 0x00000010U
4093 #define EXTI_SWIER_SWIER5 0x00000020U
4094 #define EXTI_SWIER_SWIER6 0x00000040U
4095 #define EXTI_SWIER_SWIER7 0x00000080U
4096 #define EXTI_SWIER_SWIER8 0x00000100U
4097 #define EXTI_SWIER_SWIER9 0x00000200U
4098 #define EXTI_SWIER_SWIER10 0x00000400U
4099 #define EXTI_SWIER_SWIER11 0x00000800U
4100 #define EXTI_SWIER_SWIER12 0x00001000U
4101 #define EXTI_SWIER_SWIER13 0x00002000U
4102 #define EXTI_SWIER_SWIER14 0x00004000U
4103 #define EXTI_SWIER_SWIER15 0x00008000U
4104 #define EXTI_SWIER_SWIER16 0x00010000U
4105 #define EXTI_SWIER_SWIER17 0x00020000U
4106 #define EXTI_SWIER_SWIER18 0x00040000U
4107 #define EXTI_SWIER_SWIER19 0x00080000U
4108 #define EXTI_SWIER_SWIER20 0x00100000U
4109 #define EXTI_SWIER_SWIER21 0x00200000U
4110 #define EXTI_SWIER_SWIER22 0x00400000U
4111 #define EXTI_SWIER_SWIER23 0x00800000U
4112 #define EXTI_SWIER_SWIER24 0x01000000U
4114 /******************* Bit definition for EXTI_PR register ********************/
4115 #define EXTI_PR_PR0 0x00000001U
4116 #define EXTI_PR_PR1 0x00000002U
4117 #define EXTI_PR_PR2 0x00000004U
4118 #define EXTI_PR_PR3 0x00000008U
4119 #define EXTI_PR_PR4 0x00000010U
4120 #define EXTI_PR_PR5 0x00000020U
4121 #define EXTI_PR_PR6 0x00000040U
4122 #define EXTI_PR_PR7 0x00000080U
4123 #define EXTI_PR_PR8 0x00000100U
4124 #define EXTI_PR_PR9 0x00000200U
4125 #define EXTI_PR_PR10 0x00000400U
4126 #define EXTI_PR_PR11 0x00000800U
4127 #define EXTI_PR_PR12 0x00001000U
4128 #define EXTI_PR_PR13 0x00002000U
4129 #define EXTI_PR_PR14 0x00004000U
4130 #define EXTI_PR_PR15 0x00008000U
4131 #define EXTI_PR_PR16 0x00010000U
4132 #define EXTI_PR_PR17 0x00020000U
4133 #define EXTI_PR_PR18 0x00040000U
4134 #define EXTI_PR_PR19 0x00080000U
4135 #define EXTI_PR_PR20 0x00100000U
4136 #define EXTI_PR_PR21 0x00200000U
4137 #define EXTI_PR_PR22 0x00400000U
4138 #define EXTI_PR_PR23 0x00800000U
4139 #define EXTI_PR_PR24 0x01000000U
4141 /******************************************************************************/
4142 /* */
4143 /* FLASH */
4144 /* */
4145 /******************************************************************************/
4146 /*
4147 * @brief FLASH Total Sectors Number
4148 */
4149 #define FLASH_SECTOR_TOTAL 24
4150 
4151 /******************* Bits definition for FLASH_ACR register *****************/
4152 #define FLASH_ACR_LATENCY 0x0000000FU
4153 #define FLASH_ACR_LATENCY_0WS 0x00000000U
4154 #define FLASH_ACR_LATENCY_1WS 0x00000001U
4155 #define FLASH_ACR_LATENCY_2WS 0x00000002U
4156 #define FLASH_ACR_LATENCY_3WS 0x00000003U
4157 #define FLASH_ACR_LATENCY_4WS 0x00000004U
4158 #define FLASH_ACR_LATENCY_5WS 0x00000005U
4159 #define FLASH_ACR_LATENCY_6WS 0x00000006U
4160 #define FLASH_ACR_LATENCY_7WS 0x00000007U
4161 #define FLASH_ACR_LATENCY_8WS 0x00000008U
4162 #define FLASH_ACR_LATENCY_9WS 0x00000009U
4163 #define FLASH_ACR_LATENCY_10WS 0x0000000AU
4164 #define FLASH_ACR_LATENCY_11WS 0x0000000BU
4165 #define FLASH_ACR_LATENCY_12WS 0x0000000CU
4166 #define FLASH_ACR_LATENCY_13WS 0x0000000DU
4167 #define FLASH_ACR_LATENCY_14WS 0x0000000EU
4168 #define FLASH_ACR_LATENCY_15WS 0x0000000FU
4169 #define FLASH_ACR_PRFTEN 0x00000100U
4170 #define FLASH_ACR_ARTEN 0x00000200U
4171 #define FLASH_ACR_ARTRST 0x00000800U
4172 
4173 /******************* Bits definition for FLASH_SR register ******************/
4174 #define FLASH_SR_EOP 0x00000001U
4175 #define FLASH_SR_OPERR 0x00000002U
4176 #define FLASH_SR_WRPERR 0x00000010U
4177 #define FLASH_SR_PGAERR 0x00000020U
4178 #define FLASH_SR_PGPERR 0x00000040U
4179 #define FLASH_SR_ERSERR 0x00000080U
4180 #define FLASH_SR_BSY 0x00010000U
4181 
4182 /******************* Bits definition for FLASH_CR register ******************/
4183 #define FLASH_CR_PG 0x00000001U
4184 #define FLASH_CR_SER 0x00000002U
4185 #define FLASH_CR_MER 0x00000004U
4186 #define FLASH_CR_MER1 FLASH_CR_MER
4187 #define FLASH_CR_SNB 0x000000F8U
4188 #define FLASH_CR_SNB_0 0x00000008U
4189 #define FLASH_CR_SNB_1 0x00000010U
4190 #define FLASH_CR_SNB_2 0x00000020U
4191 #define FLASH_CR_SNB_3 0x00000040U
4192 #define FLASH_CR_SNB_4 0x00000080U
4193 #define FLASH_CR_PSIZE 0x00000300U
4194 #define FLASH_CR_PSIZE_0 0x00000100U
4195 #define FLASH_CR_PSIZE_1 0x00000200U
4196 #define FLASH_CR_MER2 0x00008000U
4197 #define FLASH_CR_STRT 0x00010000U
4198 #define FLASH_CR_EOPIE 0x01000000U
4199 #define FLASH_CR_ERRIE 0x02000000U
4200 #define FLASH_CR_LOCK 0x80000000U
4201 
4202 /******************* Bits definition for FLASH_OPTCR register ***************/
4203 #define FLASH_OPTCR_OPTLOCK 0x00000001U
4204 #define FLASH_OPTCR_OPTSTRT 0x00000002U
4205 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
4206 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
4207 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
4208 #define FLASH_OPTCR_WWDG_SW 0x00000010U
4209 #define FLASH_OPTCR_IWDG_SW 0x00000020U
4210 #define FLASH_OPTCR_nRST_STOP 0x00000040U
4211 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
4212 #define FLASH_OPTCR_RDP 0x0000FF00U
4213 #define FLASH_OPTCR_RDP_0 0x00000100U
4214 #define FLASH_OPTCR_RDP_1 0x00000200U
4215 #define FLASH_OPTCR_RDP_2 0x00000400U
4216 #define FLASH_OPTCR_RDP_3 0x00000800U
4217 #define FLASH_OPTCR_RDP_4 0x00001000U
4218 #define FLASH_OPTCR_RDP_5 0x00002000U
4219 #define FLASH_OPTCR_RDP_6 0x00004000U
4220 #define FLASH_OPTCR_RDP_7 0x00008000U
4221 #define FLASH_OPTCR_nWRP 0x0FFF0000U
4222 #define FLASH_OPTCR_nWRP_0 0x00010000U
4223 #define FLASH_OPTCR_nWRP_1 0x00020000U
4224 #define FLASH_OPTCR_nWRP_2 0x00040000U
4225 #define FLASH_OPTCR_nWRP_3 0x00080000U
4226 #define FLASH_OPTCR_nWRP_4 0x00100000U
4227 #define FLASH_OPTCR_nWRP_5 0x00200000U
4228 #define FLASH_OPTCR_nWRP_6 0x00400000U
4229 #define FLASH_OPTCR_nWRP_7 0x00800000U
4230 #define FLASH_OPTCR_nWRP_8 0x01000000U
4231 #define FLASH_OPTCR_nWRP_9 0x02000000U
4232 #define FLASH_OPTCR_nWRP_10 0x04000000U
4233 #define FLASH_OPTCR_nWRP_11 0x08000000U
4234 #define FLASH_OPTCR_nDBOOT 0x10000000U
4235 #define FLASH_OPTCR_nDBANK 0x20000000U
4236 #define FLASH_OPTCR_IWDG_STDBY 0x40000000U
4237 #define FLASH_OPTCR_IWDG_STOP 0x80000000U
4238 
4239 /******************* Bits definition for FLASH_OPTCR1 register ***************/
4240 #define FLASH_OPTCR1_BOOT_ADD0 0x0000FFFFU
4241 #define FLASH_OPTCR1_BOOT_ADD1 0xFFFF0000U
4242 
4243 /******************************************************************************/
4244 /* */
4245 /* Flexible Memory Controller */
4246 /* */
4247 /******************************************************************************/
4248 /****************** Bit definition for FMC_BCR1 register *******************/
4249 #define FMC_BCR1_MBKEN 0x00000001U
4250 #define FMC_BCR1_MUXEN 0x00000002U
4251 #define FMC_BCR1_MTYP 0x0000000CU
4252 #define FMC_BCR1_MTYP_0 0x00000004U
4253 #define FMC_BCR1_MTYP_1 0x00000008U
4254 #define FMC_BCR1_MWID 0x00000030U
4255 #define FMC_BCR1_MWID_0 0x00000010U
4256 #define FMC_BCR1_MWID_1 0x00000020U
4257 #define FMC_BCR1_FACCEN 0x00000040U
4258 #define FMC_BCR1_BURSTEN 0x00000100U
4259 #define FMC_BCR1_WAITPOL 0x00000200U
4260 #define FMC_BCR1_WRAPMOD 0x00000400U
4261 #define FMC_BCR1_WAITCFG 0x00000800U
4262 #define FMC_BCR1_WREN 0x00001000U
4263 #define FMC_BCR1_WAITEN 0x00002000U
4264 #define FMC_BCR1_EXTMOD 0x00004000U
4265 #define FMC_BCR1_ASYNCWAIT 0x00008000U
4266 #define FMC_BCR1_CPSIZE 0x00070000U
4267 #define FMC_BCR1_CPSIZE_0 0x00010000U
4268 #define FMC_BCR1_CPSIZE_1 0x00020000U
4269 #define FMC_BCR1_CPSIZE_2 0x00040000U
4270 #define FMC_BCR1_CBURSTRW 0x00080000U
4271 #define FMC_BCR1_CCLKEN 0x00100000U
4272 #define FMC_BCR1_WFDIS 0x00200000U
4274 /****************** Bit definition for FMC_BCR2 register *******************/
4275 #define FMC_BCR2_MBKEN 0x00000001U
4276 #define FMC_BCR2_MUXEN 0x00000002U
4277 #define FMC_BCR2_MTYP 0x0000000CU
4278 #define FMC_BCR2_MTYP_0 0x00000004U
4279 #define FMC_BCR2_MTYP_1 0x00000008U
4280 #define FMC_BCR2_MWID 0x00000030U
4281 #define FMC_BCR2_MWID_0 0x00000010U
4282 #define FMC_BCR2_MWID_1 0x00000020U
4283 #define FMC_BCR2_FACCEN 0x00000040U
4284 #define FMC_BCR2_BURSTEN 0x00000100U
4285 #define FMC_BCR2_WAITPOL 0x00000200U
4286 #define FMC_BCR2_WRAPMOD 0x00000400U
4287 #define FMC_BCR2_WAITCFG 0x00000800U
4288 #define FMC_BCR2_WREN 0x00001000U
4289 #define FMC_BCR2_WAITEN 0x00002000U
4290 #define FMC_BCR2_EXTMOD 0x00004000U
4291 #define FMC_BCR2_ASYNCWAIT 0x00008000U
4292 #define FMC_BCR2_CPSIZE 0x00070000U
4293 #define FMC_BCR2_CPSIZE_0 0x00010000U
4294 #define FMC_BCR2_CPSIZE_1 0x00020000U
4295 #define FMC_BCR2_CPSIZE_2 0x00040000U
4296 #define FMC_BCR2_CBURSTRW 0x00080000U
4298 /****************** Bit definition for FMC_BCR3 register *******************/
4299 #define FMC_BCR3_MBKEN 0x00000001U
4300 #define FMC_BCR3_MUXEN 0x00000002U
4301 #define FMC_BCR3_MTYP 0x0000000CU
4302 #define FMC_BCR3_MTYP_0 0x00000004U
4303 #define FMC_BCR3_MTYP_1 0x00000008U
4304 #define FMC_BCR3_MWID 0x00000030U
4305 #define FMC_BCR3_MWID_0 0x00000010U
4306 #define FMC_BCR3_MWID_1 0x00000020U
4307 #define FMC_BCR3_FACCEN 0x00000040U
4308 #define FMC_BCR3_BURSTEN 0x00000100U
4309 #define FMC_BCR3_WAITPOL 0x00000200U
4310 #define FMC_BCR3_WRAPMOD 0x00000400U
4311 #define FMC_BCR3_WAITCFG 0x00000800U
4312 #define FMC_BCR3_WREN 0x00001000U
4313 #define FMC_BCR3_WAITEN 0x00002000U
4314 #define FMC_BCR3_EXTMOD 0x00004000U
4315 #define FMC_BCR3_ASYNCWAIT 0x00008000U
4316 #define FMC_BCR3_CPSIZE 0x00070000U
4317 #define FMC_BCR3_CPSIZE_0 0x00010000U
4318 #define FMC_BCR3_CPSIZE_1 0x00020000U
4319 #define FMC_BCR3_CPSIZE_2 0x00040000U
4320 #define FMC_BCR3_CBURSTRW 0x00080000U
4322 /****************** Bit definition for FMC_BCR4 register *******************/
4323 #define FMC_BCR4_MBKEN 0x00000001U
4324 #define FMC_BCR4_MUXEN 0x00000002U
4325 #define FMC_BCR4_MTYP 0x0000000CU
4326 #define FMC_BCR4_MTYP_0 0x00000004U
4327 #define FMC_BCR4_MTYP_1 0x00000008U
4328 #define FMC_BCR4_MWID 0x00000030U
4329 #define FMC_BCR4_MWID_0 0x00000010U
4330 #define FMC_BCR4_MWID_1 0x00000020U
4331 #define FMC_BCR4_FACCEN 0x00000040U
4332 #define FMC_BCR4_BURSTEN 0x00000100U
4333 #define FMC_BCR4_WAITPOL 0x00000200U
4334 #define FMC_BCR4_WRAPMOD 0x00000400U
4335 #define FMC_BCR4_WAITCFG 0x00000800U
4336 #define FMC_BCR4_WREN 0x00001000U
4337 #define FMC_BCR4_WAITEN 0x00002000U
4338 #define FMC_BCR4_EXTMOD 0x00004000U
4339 #define FMC_BCR4_ASYNCWAIT 0x00008000U
4340 #define FMC_BCR4_CPSIZE 0x00070000U
4341 #define FMC_BCR4_CPSIZE_0 0x00010000U
4342 #define FMC_BCR4_CPSIZE_1 0x00020000U
4343 #define FMC_BCR4_CPSIZE_2 0x00040000U
4344 #define FMC_BCR4_CBURSTRW 0x00080000U
4346 /****************** Bit definition for FMC_BTR1 register ******************/
4347 #define FMC_BTR1_ADDSET 0x0000000FU
4348 #define FMC_BTR1_ADDSET_0 0x00000001U
4349 #define FMC_BTR1_ADDSET_1 0x00000002U
4350 #define FMC_BTR1_ADDSET_2 0x00000004U
4351 #define FMC_BTR1_ADDSET_3 0x00000008U
4352 #define FMC_BTR1_ADDHLD 0x000000F0U
4353 #define FMC_BTR1_ADDHLD_0 0x00000010U
4354 #define FMC_BTR1_ADDHLD_1 0x00000020U
4355 #define FMC_BTR1_ADDHLD_2 0x00000040U
4356 #define FMC_BTR1_ADDHLD_3 0x00000080U
4357 #define FMC_BTR1_DATAST 0x0000FF00U
4358 #define FMC_BTR1_DATAST_0 0x00000100U
4359 #define FMC_BTR1_DATAST_1 0x00000200U
4360 #define FMC_BTR1_DATAST_2 0x00000400U
4361 #define FMC_BTR1_DATAST_3 0x00000800U
4362 #define FMC_BTR1_DATAST_4 0x00001000U
4363 #define FMC_BTR1_DATAST_5 0x00002000U
4364 #define FMC_BTR1_DATAST_6 0x00004000U
4365 #define FMC_BTR1_DATAST_7 0x00008000U
4366 #define FMC_BTR1_BUSTURN 0x000F0000U
4367 #define FMC_BTR1_BUSTURN_0 0x00010000U
4368 #define FMC_BTR1_BUSTURN_1 0x00020000U
4369 #define FMC_BTR1_BUSTURN_2 0x00040000U
4370 #define FMC_BTR1_BUSTURN_3 0x00080000U
4371 #define FMC_BTR1_CLKDIV 0x00F00000U
4372 #define FMC_BTR1_CLKDIV_0 0x00100000U
4373 #define FMC_BTR1_CLKDIV_1 0x00200000U
4374 #define FMC_BTR1_CLKDIV_2 0x00400000U
4375 #define FMC_BTR1_CLKDIV_3 0x00800000U
4376 #define FMC_BTR1_DATLAT 0x0F000000U
4377 #define FMC_BTR1_DATLAT_0 0x01000000U
4378 #define FMC_BTR1_DATLAT_1 0x02000000U
4379 #define FMC_BTR1_DATLAT_2 0x04000000U
4380 #define FMC_BTR1_DATLAT_3 0x08000000U
4381 #define FMC_BTR1_ACCMOD 0x30000000U
4382 #define FMC_BTR1_ACCMOD_0 0x10000000U
4383 #define FMC_BTR1_ACCMOD_1 0x20000000U
4385 /****************** Bit definition for FMC_BTR2 register *******************/
4386 #define FMC_BTR2_ADDSET 0x0000000FU
4387 #define FMC_BTR2_ADDSET_0 0x00000001U
4388 #define FMC_BTR2_ADDSET_1 0x00000002U
4389 #define FMC_BTR2_ADDSET_2 0x00000004U
4390 #define FMC_BTR2_ADDSET_3 0x00000008U
4391 #define FMC_BTR2_ADDHLD 0x000000F0U
4392 #define FMC_BTR2_ADDHLD_0 0x00000010U
4393 #define FMC_BTR2_ADDHLD_1 0x00000020U
4394 #define FMC_BTR2_ADDHLD_2 0x00000040U
4395 #define FMC_BTR2_ADDHLD_3 0x00000080U
4396 #define FMC_BTR2_DATAST 0x0000FF00U
4397 #define FMC_BTR2_DATAST_0 0x00000100U
4398 #define FMC_BTR2_DATAST_1 0x00000200U
4399 #define FMC_BTR2_DATAST_2 0x00000400U
4400 #define FMC_BTR2_DATAST_3 0x00000800U
4401 #define FMC_BTR2_DATAST_4 0x00001000U
4402 #define FMC_BTR2_DATAST_5 0x00002000U
4403 #define FMC_BTR2_DATAST_6 0x00004000U
4404 #define FMC_BTR2_DATAST_7 0x00008000U
4405 #define FMC_BTR2_BUSTURN 0x000F0000U
4406 #define FMC_BTR2_BUSTURN_0 0x00010000U
4407 #define FMC_BTR2_BUSTURN_1 0x00020000U
4408 #define FMC_BTR2_BUSTURN_2 0x00040000U
4409 #define FMC_BTR2_BUSTURN_3 0x00080000U
4410 #define FMC_BTR2_CLKDIV 0x00F00000U
4411 #define FMC_BTR2_CLKDIV_0 0x00100000U
4412 #define FMC_BTR2_CLKDIV_1 0x00200000U
4413 #define FMC_BTR2_CLKDIV_2 0x00400000U
4414 #define FMC_BTR2_CLKDIV_3 0x00800000U
4415 #define FMC_BTR2_DATLAT 0x0F000000U
4416 #define FMC_BTR2_DATLAT_0 0x01000000U
4417 #define FMC_BTR2_DATLAT_1 0x02000000U
4418 #define FMC_BTR2_DATLAT_2 0x04000000U
4419 #define FMC_BTR2_DATLAT_3 0x08000000U
4420 #define FMC_BTR2_ACCMOD 0x30000000U
4421 #define FMC_BTR2_ACCMOD_0 0x10000000U
4422 #define FMC_BTR2_ACCMOD_1 0x20000000U
4424 /******************* Bit definition for FMC_BTR3 register *******************/
4425 #define FMC_BTR3_ADDSET 0x0000000FU
4426 #define FMC_BTR3_ADDSET_0 0x00000001U
4427 #define FMC_BTR3_ADDSET_1 0x00000002U
4428 #define FMC_BTR3_ADDSET_2 0x00000004U
4429 #define FMC_BTR3_ADDSET_3 0x00000008U
4430 #define FMC_BTR3_ADDHLD 0x000000F0U
4431 #define FMC_BTR3_ADDHLD_0 0x00000010U
4432 #define FMC_BTR3_ADDHLD_1 0x00000020U
4433 #define FMC_BTR3_ADDHLD_2 0x00000040U
4434 #define FMC_BTR3_ADDHLD_3 0x00000080U
4435 #define FMC_BTR3_DATAST 0x0000FF00U
4436 #define FMC_BTR3_DATAST_0 0x00000100U
4437 #define FMC_BTR3_DATAST_1 0x00000200U
4438 #define FMC_BTR3_DATAST_2 0x00000400U
4439 #define FMC_BTR3_DATAST_3 0x00000800U
4440 #define FMC_BTR3_DATAST_4 0x00001000U
4441 #define FMC_BTR3_DATAST_5 0x00002000U
4442 #define FMC_BTR3_DATAST_6 0x00004000U
4443 #define FMC_BTR3_DATAST_7 0x00008000U
4444 #define FMC_BTR3_BUSTURN 0x000F0000U
4445 #define FMC_BTR3_BUSTURN_0 0x00010000U
4446 #define FMC_BTR3_BUSTURN_1 0x00020000U
4447 #define FMC_BTR3_BUSTURN_2 0x00040000U
4448 #define FMC_BTR3_BUSTURN_3 0x00080000U
4449 #define FMC_BTR3_CLKDIV 0x00F00000U
4450 #define FMC_BTR3_CLKDIV_0 0x00100000U
4451 #define FMC_BTR3_CLKDIV_1 0x00200000U
4452 #define FMC_BTR3_CLKDIV_2 0x00400000U
4453 #define FMC_BTR3_CLKDIV_3 0x00800000U
4454 #define FMC_BTR3_DATLAT 0x0F000000U
4455 #define FMC_BTR3_DATLAT_0 0x01000000U
4456 #define FMC_BTR3_DATLAT_1 0x02000000U
4457 #define FMC_BTR3_DATLAT_2 0x04000000U
4458 #define FMC_BTR3_DATLAT_3 0x08000000U
4459 #define FMC_BTR3_ACCMOD 0x30000000U
4460 #define FMC_BTR3_ACCMOD_0 0x10000000U
4461 #define FMC_BTR3_ACCMOD_1 0x20000000U
4463 /****************** Bit definition for FMC_BTR4 register *******************/
4464 #define FMC_BTR4_ADDSET 0x0000000FU
4465 #define FMC_BTR4_ADDSET_0 0x00000001U
4466 #define FMC_BTR4_ADDSET_1 0x00000002U
4467 #define FMC_BTR4_ADDSET_2 0x00000004U
4468 #define FMC_BTR4_ADDSET_3 0x00000008U
4469 #define FMC_BTR4_ADDHLD 0x000000F0U
4470 #define FMC_BTR4_ADDHLD_0 0x00000010U
4471 #define FMC_BTR4_ADDHLD_1 0x00000020U
4472 #define FMC_BTR4_ADDHLD_2 0x00000040U
4473 #define FMC_BTR4_ADDHLD_3 0x00000080U
4474 #define FMC_BTR4_DATAST 0x0000FF00U
4475 #define FMC_BTR4_DATAST_0 0x00000100U
4476 #define FMC_BTR4_DATAST_1 0x00000200U
4477 #define FMC_BTR4_DATAST_2 0x00000400U
4478 #define FMC_BTR4_DATAST_3 0x00000800U
4479 #define FMC_BTR4_DATAST_4 0x00001000U
4480 #define FMC_BTR4_DATAST_5 0x00002000U
4481 #define FMC_BTR4_DATAST_6 0x00004000U
4482 #define FMC_BTR4_DATAST_7 0x00008000U
4483 #define FMC_BTR4_BUSTURN 0x000F0000U
4484 #define FMC_BTR4_BUSTURN_0 0x00010000U
4485 #define FMC_BTR4_BUSTURN_1 0x00020000U
4486 #define FMC_BTR4_BUSTURN_2 0x00040000U
4487 #define FMC_BTR4_BUSTURN_3 0x00080000U
4488 #define FMC_BTR4_CLKDIV 0x00F00000U
4489 #define FMC_BTR4_CLKDIV_0 0x00100000U
4490 #define FMC_BTR4_CLKDIV_1 0x00200000U
4491 #define FMC_BTR4_CLKDIV_2 0x00400000U
4492 #define FMC_BTR4_CLKDIV_3 0x00800000U
4493 #define FMC_BTR4_DATLAT 0x0F000000U
4494 #define FMC_BTR4_DATLAT_0 0x01000000U
4495 #define FMC_BTR4_DATLAT_1 0x02000000U
4496 #define FMC_BTR4_DATLAT_2 0x04000000U
4497 #define FMC_BTR4_DATLAT_3 0x08000000U
4498 #define FMC_BTR4_ACCMOD 0x30000000U
4499 #define FMC_BTR4_ACCMOD_0 0x10000000U
4500 #define FMC_BTR4_ACCMOD_1 0x20000000U
4502 /****************** Bit definition for FMC_BWTR1 register ******************/
4503 #define FMC_BWTR1_ADDSET 0x0000000FU
4504 #define FMC_BWTR1_ADDSET_0 0x00000001U
4505 #define FMC_BWTR1_ADDSET_1 0x00000002U
4506 #define FMC_BWTR1_ADDSET_2 0x00000004U
4507 #define FMC_BWTR1_ADDSET_3 0x00000008U
4508 #define FMC_BWTR1_ADDHLD 0x000000F0U
4509 #define FMC_BWTR1_ADDHLD_0 0x00000010U
4510 #define FMC_BWTR1_ADDHLD_1 0x00000020U
4511 #define FMC_BWTR1_ADDHLD_2 0x00000040U
4512 #define FMC_BWTR1_ADDHLD_3 0x00000080U
4513 #define FMC_BWTR1_DATAST 0x0000FF00U
4514 #define FMC_BWTR1_DATAST_0 0x00000100U
4515 #define FMC_BWTR1_DATAST_1 0x00000200U
4516 #define FMC_BWTR1_DATAST_2 0x00000400U
4517 #define FMC_BWTR1_DATAST_3 0x00000800U
4518 #define FMC_BWTR1_DATAST_4 0x00001000U
4519 #define FMC_BWTR1_DATAST_5 0x00002000U
4520 #define FMC_BWTR1_DATAST_6 0x00004000U
4521 #define FMC_BWTR1_DATAST_7 0x00008000U
4522 #define FMC_BWTR1_BUSTURN 0x000F0000U
4523 #define FMC_BWTR1_BUSTURN_0 0x00010000U
4524 #define FMC_BWTR1_BUSTURN_1 0x00020000U
4525 #define FMC_BWTR1_BUSTURN_2 0x00040000U
4526 #define FMC_BWTR1_BUSTURN_3 0x00080000U
4527 #define FMC_BWTR1_ACCMOD 0x30000000U
4528 #define FMC_BWTR1_ACCMOD_0 0x10000000U
4529 #define FMC_BWTR1_ACCMOD_1 0x20000000U
4531 /****************** Bit definition for FMC_BWTR2 register ******************/
4532 #define FMC_BWTR2_ADDSET 0x0000000FU
4533 #define FMC_BWTR2_ADDSET_0 0x00000001U
4534 #define FMC_BWTR2_ADDSET_1 0x00000002U
4535 #define FMC_BWTR2_ADDSET_2 0x00000004U
4536 #define FMC_BWTR2_ADDSET_3 0x00000008U
4537 #define FMC_BWTR2_ADDHLD 0x000000F0U
4538 #define FMC_BWTR2_ADDHLD_0 0x00000010U
4539 #define FMC_BWTR2_ADDHLD_1 0x00000020U
4540 #define FMC_BWTR2_ADDHLD_2 0x00000040U
4541 #define FMC_BWTR2_ADDHLD_3 0x00000080U
4542 #define FMC_BWTR2_DATAST 0x0000FF00U
4543 #define FMC_BWTR2_DATAST_0 0x00000100U
4544 #define FMC_BWTR2_DATAST_1 0x00000200U
4545 #define FMC_BWTR2_DATAST_2 0x00000400U
4546 #define FMC_BWTR2_DATAST_3 0x00000800U
4547 #define FMC_BWTR2_DATAST_4 0x00001000U
4548 #define FMC_BWTR2_DATAST_5 0x00002000U
4549 #define FMC_BWTR2_DATAST_6 0x00004000U
4550 #define FMC_BWTR2_DATAST_7 0x00008000U
4551 #define FMC_BWTR2_BUSTURN 0x000F0000U
4552 #define FMC_BWTR2_BUSTURN_0 0x00010000U
4553 #define FMC_BWTR2_BUSTURN_1 0x00020000U
4554 #define FMC_BWTR2_BUSTURN_2 0x00040000U
4555 #define FMC_BWTR2_BUSTURN_3 0x00080000U
4556 #define FMC_BWTR2_ACCMOD 0x30000000U
4557 #define FMC_BWTR2_ACCMOD_0 0x10000000U
4558 #define FMC_BWTR2_ACCMOD_1 0x20000000U
4560 /****************** Bit definition for FMC_BWTR3 register ******************/
4561 #define FMC_BWTR3_ADDSET 0x0000000FU
4562 #define FMC_BWTR3_ADDSET_0 0x00000001U
4563 #define FMC_BWTR3_ADDSET_1 0x00000002U
4564 #define FMC_BWTR3_ADDSET_2 0x00000004U
4565 #define FMC_BWTR3_ADDSET_3 0x00000008U
4566 #define FMC_BWTR3_ADDHLD 0x000000F0U
4567 #define FMC_BWTR3_ADDHLD_0 0x00000010U
4568 #define FMC_BWTR3_ADDHLD_1 0x00000020U
4569 #define FMC_BWTR3_ADDHLD_2 0x00000040U
4570 #define FMC_BWTR3_ADDHLD_3 0x00000080U
4571 #define FMC_BWTR3_DATAST 0x0000FF00U
4572 #define FMC_BWTR3_DATAST_0 0x00000100U
4573 #define FMC_BWTR3_DATAST_1 0x00000200U
4574 #define FMC_BWTR3_DATAST_2 0x00000400U
4575 #define FMC_BWTR3_DATAST_3 0x00000800U
4576 #define FMC_BWTR3_DATAST_4 0x00001000U
4577 #define FMC_BWTR3_DATAST_5 0x00002000U
4578 #define FMC_BWTR3_DATAST_6 0x00004000U
4579 #define FMC_BWTR3_DATAST_7 0x00008000U
4580 #define FMC_BWTR3_BUSTURN 0x000F0000U
4581 #define FMC_BWTR3_BUSTURN_0 0x00010000U
4582 #define FMC_BWTR3_BUSTURN_1 0x00020000U
4583 #define FMC_BWTR3_BUSTURN_2 0x00040000U
4584 #define FMC_BWTR3_BUSTURN_3 0x00080000U
4585 #define FMC_BWTR3_ACCMOD 0x30000000U
4586 #define FMC_BWTR3_ACCMOD_0 0x10000000U
4587 #define FMC_BWTR3_ACCMOD_1 0x20000000U
4589 /****************** Bit definition for FMC_BWTR4 register ******************/
4590 #define FMC_BWTR4_ADDSET 0x0000000FU
4591 #define FMC_BWTR4_ADDSET_0 0x00000001U
4592 #define FMC_BWTR4_ADDSET_1 0x00000002U
4593 #define FMC_BWTR4_ADDSET_2 0x00000004U
4594 #define FMC_BWTR4_ADDSET_3 0x00000008U
4595 #define FMC_BWTR4_ADDHLD 0x000000F0U
4596 #define FMC_BWTR4_ADDHLD_0 0x00000010U
4597 #define FMC_BWTR4_ADDHLD_1 0x00000020U
4598 #define FMC_BWTR4_ADDHLD_2 0x00000040U
4599 #define FMC_BWTR4_ADDHLD_3 0x00000080U
4600 #define FMC_BWTR4_DATAST 0x0000FF00U
4601 #define FMC_BWTR4_DATAST_0 0x00000100U
4602 #define FMC_BWTR4_DATAST_1 0x00000200U
4603 #define FMC_BWTR4_DATAST_2 0x00000400U
4604 #define FMC_BWTR4_DATAST_3 0x00000800U
4605 #define FMC_BWTR4_DATAST_4 0x00001000U
4606 #define FMC_BWTR4_DATAST_5 0x00002000U
4607 #define FMC_BWTR4_DATAST_6 0x00004000U
4608 #define FMC_BWTR4_DATAST_7 0x00008000U
4609 #define FMC_BWTR4_BUSTURN 0x000F0000U
4610 #define FMC_BWTR4_BUSTURN_0 0x00010000U
4611 #define FMC_BWTR4_BUSTURN_1 0x00020000U
4612 #define FMC_BWTR4_BUSTURN_2 0x00040000U
4613 #define FMC_BWTR4_BUSTURN_3 0x00080000U
4614 #define FMC_BWTR4_ACCMOD 0x30000000U
4615 #define FMC_BWTR4_ACCMOD_0 0x10000000U
4616 #define FMC_BWTR4_ACCMOD_1 0x20000000U
4618 /****************** Bit definition for FMC_PCR register *******************/
4619 #define FMC_PCR_PWAITEN 0x00000002U
4620 #define FMC_PCR_PBKEN 0x00000004U
4621 #define FMC_PCR_PTYP 0x00000008U
4622 #define FMC_PCR_PWID 0x00000030U
4623 #define FMC_PCR_PWID_0 0x00000010U
4624 #define FMC_PCR_PWID_1 0x00000020U
4625 #define FMC_PCR_ECCEN 0x00000040U
4626 #define FMC_PCR_TCLR 0x00001E00U
4627 #define FMC_PCR_TCLR_0 0x00000200U
4628 #define FMC_PCR_TCLR_1 0x00000400U
4629 #define FMC_PCR_TCLR_2 0x00000800U
4630 #define FMC_PCR_TCLR_3 0x00001000U
4631 #define FMC_PCR_TAR 0x0001E000U
4632 #define FMC_PCR_TAR_0 0x00002000U
4633 #define FMC_PCR_TAR_1 0x00004000U
4634 #define FMC_PCR_TAR_2 0x00008000U
4635 #define FMC_PCR_TAR_3 0x00010000U
4636 #define FMC_PCR_ECCPS 0x000E0000U
4637 #define FMC_PCR_ECCPS_0 0x00020000U
4638 #define FMC_PCR_ECCPS_1 0x00040000U
4639 #define FMC_PCR_ECCPS_2 0x00080000U
4641 /******************* Bit definition for FMC_SR register *******************/
4642 #define FMC_SR_IRS 0x01U
4643 #define FMC_SR_ILS 0x02U
4644 #define FMC_SR_IFS 0x04U
4645 #define FMC_SR_IREN 0x08U
4646 #define FMC_SR_ILEN 0x10U
4647 #define FMC_SR_IFEN 0x20U
4648 #define FMC_SR_FEMPT 0x40U
4650 /****************** Bit definition for FMC_PMEM register ******************/
4651 #define FMC_PMEM_MEMSET3 0x000000FFU
4652 #define FMC_PMEM_MEMSET3_0 0x00000001U
4653 #define FMC_PMEM_MEMSET3_1 0x00000002U
4654 #define FMC_PMEM_MEMSET3_2 0x00000004U
4655 #define FMC_PMEM_MEMSET3_3 0x00000008U
4656 #define FMC_PMEM_MEMSET3_4 0x00000010U
4657 #define FMC_PMEM_MEMSET3_5 0x00000020U
4658 #define FMC_PMEM_MEMSET3_6 0x00000040U
4659 #define FMC_PMEM_MEMSET3_7 0x00000080U
4660 #define FMC_PMEM_MEMWAIT3 0x0000FF00U
4661 #define FMC_PMEM_MEMWAIT3_0 0x00000100U
4662 #define FMC_PMEM_MEMWAIT3_1 0x00000200U
4663 #define FMC_PMEM_MEMWAIT3_2 0x00000400U
4664 #define FMC_PMEM_MEMWAIT3_3 0x00000800U
4665 #define FMC_PMEM_MEMWAIT3_4 0x00001000U
4666 #define FMC_PMEM_MEMWAIT3_5 0x00002000U
4667 #define FMC_PMEM_MEMWAIT3_6 0x00004000U
4668 #define FMC_PMEM_MEMWAIT3_7 0x00008000U
4669 #define FMC_PMEM_MEMHOLD3 0x00FF0000U
4670 #define FMC_PMEM_MEMHOLD3_0 0x00010000U
4671 #define FMC_PMEM_MEMHOLD3_1 0x00020000U
4672 #define FMC_PMEM_MEMHOLD3_2 0x00040000U
4673 #define FMC_PMEM_MEMHOLD3_3 0x00080000U
4674 #define FMC_PMEM_MEMHOLD3_4 0x00100000U
4675 #define FMC_PMEM_MEMHOLD3_5 0x00200000U
4676 #define FMC_PMEM_MEMHOLD3_6 0x00400000U
4677 #define FMC_PMEM_MEMHOLD3_7 0x00800000U
4678 #define FMC_PMEM_MEMHIZ3 0xFF000000U
4679 #define FMC_PMEM_MEMHIZ3_0 0x01000000U
4680 #define FMC_PMEM_MEMHIZ3_1 0x02000000U
4681 #define FMC_PMEM_MEMHIZ3_2 0x04000000U
4682 #define FMC_PMEM_MEMHIZ3_3 0x08000000U
4683 #define FMC_PMEM_MEMHIZ3_4 0x10000000U
4684 #define FMC_PMEM_MEMHIZ3_5 0x20000000U
4685 #define FMC_PMEM_MEMHIZ3_6 0x40000000U
4686 #define FMC_PMEM_MEMHIZ3_7 0x80000000U
4688 /****************** Bit definition for FMC_PATT register ******************/
4689 #define FMC_PATT_ATTSET3 0x000000FFU
4690 #define FMC_PATT_ATTSET3_0 0x00000001U
4691 #define FMC_PATT_ATTSET3_1 0x00000002U
4692 #define FMC_PATT_ATTSET3_2 0x00000004U
4693 #define FMC_PATT_ATTSET3_3 0x00000008U
4694 #define FMC_PATT_ATTSET3_4 0x00000010U
4695 #define FMC_PATT_ATTSET3_5 0x00000020U
4696 #define FMC_PATT_ATTSET3_6 0x00000040U
4697 #define FMC_PATT_ATTSET3_7 0x00000080U
4698 #define FMC_PATT_ATTWAIT3 0x0000FF00U
4699 #define FMC_PATT_ATTWAIT3_0 0x00000100U
4700 #define FMC_PATT_ATTWAIT3_1 0x00000200U
4701 #define FMC_PATT_ATTWAIT3_2 0x00000400U
4702 #define FMC_PATT_ATTWAIT3_3 0x00000800U
4703 #define FMC_PATT_ATTWAIT3_4 0x00001000U
4704 #define FMC_PATT_ATTWAIT3_5 0x00002000U
4705 #define FMC_PATT_ATTWAIT3_6 0x00004000U
4706 #define FMC_PATT_ATTWAIT3_7 0x00008000U
4707 #define FMC_PATT_ATTHOLD3 0x00FF0000U
4708 #define FMC_PATT_ATTHOLD3_0 0x00010000U
4709 #define FMC_PATT_ATTHOLD3_1 0x00020000U
4710 #define FMC_PATT_ATTHOLD3_2 0x00040000U
4711 #define FMC_PATT_ATTHOLD3_3 0x00080000U
4712 #define FMC_PATT_ATTHOLD3_4 0x00100000U
4713 #define FMC_PATT_ATTHOLD3_5 0x00200000U
4714 #define FMC_PATT_ATTHOLD3_6 0x00400000U
4715 #define FMC_PATT_ATTHOLD3_7 0x00800000U
4716 #define FMC_PATT_ATTHIZ3 0xFF000000U
4717 #define FMC_PATT_ATTHIZ3_0 0x01000000U
4718 #define FMC_PATT_ATTHIZ3_1 0x02000000U
4719 #define FMC_PATT_ATTHIZ3_2 0x04000000U
4720 #define FMC_PATT_ATTHIZ3_3 0x08000000U
4721 #define FMC_PATT_ATTHIZ3_4 0x10000000U
4722 #define FMC_PATT_ATTHIZ3_5 0x20000000U
4723 #define FMC_PATT_ATTHIZ3_6 0x40000000U
4724 #define FMC_PATT_ATTHIZ3_7 0x80000000U
4726 /****************** Bit definition for FMC_ECCR register ******************/
4727 #define FMC_ECCR_ECC3 0xFFFFFFFFU
4729 /****************** Bit definition for FMC_SDCR1 register ******************/
4730 #define FMC_SDCR1_NC 0x00000003U
4731 #define FMC_SDCR1_NC_0 0x00000001U
4732 #define FMC_SDCR1_NC_1 0x00000002U
4733 #define FMC_SDCR1_NR 0x0000000CU
4734 #define FMC_SDCR1_NR_0 0x00000004U
4735 #define FMC_SDCR1_NR_1 0x00000008U
4736 #define FMC_SDCR1_MWID 0x00000030U
4737 #define FMC_SDCR1_MWID_0 0x00000010U
4738 #define FMC_SDCR1_MWID_1 0x00000020U
4739 #define FMC_SDCR1_NB 0x00000040U
4740 #define FMC_SDCR1_CAS 0x00000180U
4741 #define FMC_SDCR1_CAS_0 0x00000080U
4742 #define FMC_SDCR1_CAS_1 0x00000100U
4743 #define FMC_SDCR1_WP 0x00000200U
4744 #define FMC_SDCR1_SDCLK 0x00000C00U
4745 #define FMC_SDCR1_SDCLK_0 0x00000400U
4746 #define FMC_SDCR1_SDCLK_1 0x00000800U
4747 #define FMC_SDCR1_RBURST 0x00001000U
4748 #define FMC_SDCR1_RPIPE 0x00006000U
4749 #define FMC_SDCR1_RPIPE_0 0x00002000U
4750 #define FMC_SDCR1_RPIPE_1 0x00004000U
4752 /****************** Bit definition for FMC_SDCR2 register ******************/
4753 #define FMC_SDCR2_NC 0x00000003U
4754 #define FMC_SDCR2_NC_0 0x00000001U
4755 #define FMC_SDCR2_NC_1 0x00000002U
4756 #define FMC_SDCR2_NR 0x0000000CU
4757 #define FMC_SDCR2_NR_0 0x00000004U
4758 #define FMC_SDCR2_NR_1 0x00000008U
4759 #define FMC_SDCR2_MWID 0x00000030U
4760 #define FMC_SDCR2_MWID_0 0x00000010U
4761 #define FMC_SDCR2_MWID_1 0x00000020U
4762 #define FMC_SDCR2_NB 0x00000040U
4763 #define FMC_SDCR2_CAS 0x00000180U
4764 #define FMC_SDCR2_CAS_0 0x00000080U
4765 #define FMC_SDCR2_CAS_1 0x00000100U
4766 #define FMC_SDCR2_WP 0x00000200U
4767 #define FMC_SDCR2_SDCLK 0x00000C00U
4768 #define FMC_SDCR2_SDCLK_0 0x00000400U
4769 #define FMC_SDCR2_SDCLK_1 0x00000800U
4770 #define FMC_SDCR2_RBURST 0x00001000U
4771 #define FMC_SDCR2_RPIPE 0x00006000U
4772 #define FMC_SDCR2_RPIPE_0 0x00002000U
4773 #define FMC_SDCR2_RPIPE_1 0x00004000U
4775 /****************** Bit definition for FMC_SDTR1 register ******************/
4776 #define FMC_SDTR1_TMRD 0x0000000FU
4777 #define FMC_SDTR1_TMRD_0 0x00000001U
4778 #define FMC_SDTR1_TMRD_1 0x00000002U
4779 #define FMC_SDTR1_TMRD_2 0x00000004U
4780 #define FMC_SDTR1_TMRD_3 0x00000008U
4781 #define FMC_SDTR1_TXSR 0x000000F0U
4782 #define FMC_SDTR1_TXSR_0 0x00000010U
4783 #define FMC_SDTR1_TXSR_1 0x00000020U
4784 #define FMC_SDTR1_TXSR_2 0x00000040U
4785 #define FMC_SDTR1_TXSR_3 0x00000080U
4786 #define FMC_SDTR1_TRAS 0x00000F00U
4787 #define FMC_SDTR1_TRAS_0 0x00000100U
4788 #define FMC_SDTR1_TRAS_1 0x00000200U
4789 #define FMC_SDTR1_TRAS_2 0x00000400U
4790 #define FMC_SDTR1_TRAS_3 0x00000800U
4791 #define FMC_SDTR1_TRC 0x0000F000U
4792 #define FMC_SDTR1_TRC_0 0x00001000U
4793 #define FMC_SDTR1_TRC_1 0x00002000U
4794 #define FMC_SDTR1_TRC_2 0x00004000U
4795 #define FMC_SDTR1_TWR 0x000F0000U
4796 #define FMC_SDTR1_TWR_0 0x00010000U
4797 #define FMC_SDTR1_TWR_1 0x00020000U
4798 #define FMC_SDTR1_TWR_2 0x00040000U
4799 #define FMC_SDTR1_TRP 0x00F00000U
4800 #define FMC_SDTR1_TRP_0 0x00100000U
4801 #define FMC_SDTR1_TRP_1 0x00200000U
4802 #define FMC_SDTR1_TRP_2 0x00400000U
4803 #define FMC_SDTR1_TRCD 0x0F000000U
4804 #define FMC_SDTR1_TRCD_0 0x01000000U
4805 #define FMC_SDTR1_TRCD_1 0x02000000U
4806 #define FMC_SDTR1_TRCD_2 0x04000000U
4808 /****************** Bit definition for FMC_SDTR2 register ******************/
4809 #define FMC_SDTR2_TMRD 0x0000000FU
4810 #define FMC_SDTR2_TMRD_0 0x00000001U
4811 #define FMC_SDTR2_TMRD_1 0x00000002U
4812 #define FMC_SDTR2_TMRD_2 0x00000004U
4813 #define FMC_SDTR2_TMRD_3 0x00000008U
4814 #define FMC_SDTR2_TXSR 0x000000F0U
4815 #define FMC_SDTR2_TXSR_0 0x00000010U
4816 #define FMC_SDTR2_TXSR_1 0x00000020U
4817 #define FMC_SDTR2_TXSR_2 0x00000040U
4818 #define FMC_SDTR2_TXSR_3 0x00000080U
4819 #define FMC_SDTR2_TRAS 0x00000F00U
4820 #define FMC_SDTR2_TRAS_0 0x00000100U
4821 #define FMC_SDTR2_TRAS_1 0x00000200U
4822 #define FMC_SDTR2_TRAS_2 0x00000400U
4823 #define FMC_SDTR2_TRAS_3 0x00000800U
4824 #define FMC_SDTR2_TRC 0x0000F000U
4825 #define FMC_SDTR2_TRC_0 0x00001000U
4826 #define FMC_SDTR2_TRC_1 0x00002000U
4827 #define FMC_SDTR2_TRC_2 0x00004000U
4828 #define FMC_SDTR2_TWR 0x000F0000U
4829 #define FMC_SDTR2_TWR_0 0x00010000U
4830 #define FMC_SDTR2_TWR_1 0x00020000U
4831 #define FMC_SDTR2_TWR_2 0x00040000U
4832 #define FMC_SDTR2_TRP 0x00F00000U
4833 #define FMC_SDTR2_TRP_0 0x00100000U
4834 #define FMC_SDTR2_TRP_1 0x00200000U
4835 #define FMC_SDTR2_TRP_2 0x00400000U
4836 #define FMC_SDTR2_TRCD 0x0F000000U
4837 #define FMC_SDTR2_TRCD_0 0x01000000U
4838 #define FMC_SDTR2_TRCD_1 0x02000000U
4839 #define FMC_SDTR2_TRCD_2 0x04000000U
4841 /****************** Bit definition for FMC_SDCMR register ******************/
4842 #define FMC_SDCMR_MODE 0x00000007U
4843 #define FMC_SDCMR_MODE_0 0x00000001U
4844 #define FMC_SDCMR_MODE_1 0x00000002U
4845 #define FMC_SDCMR_MODE_2 0x00000003U
4846 #define FMC_SDCMR_CTB2 0x00000008U
4847 #define FMC_SDCMR_CTB1 0x00000010U
4848 #define FMC_SDCMR_NRFS 0x000001E0U
4849 #define FMC_SDCMR_NRFS_0 0x00000020U
4850 #define FMC_SDCMR_NRFS_1 0x00000040U
4851 #define FMC_SDCMR_NRFS_2 0x00000080U
4852 #define FMC_SDCMR_NRFS_3 0x00000100U
4853 #define FMC_SDCMR_MRD 0x003FFE00U
4855 /****************** Bit definition for FMC_SDRTR register ******************/
4856 #define FMC_SDRTR_CRE 0x00000001U
4857 #define FMC_SDRTR_COUNT 0x00003FFEU
4858 #define FMC_SDRTR_REIE 0x00004000U
4860 /****************** Bit definition for FMC_SDSR register ******************/
4861 #define FMC_SDSR_RE 0x00000001U
4862 #define FMC_SDSR_MODES1 0x00000006U
4863 #define FMC_SDSR_MODES1_0 0x00000002U
4864 #define FMC_SDSR_MODES1_1 0x00000004U
4865 #define FMC_SDSR_MODES2 0x00000018U
4866 #define FMC_SDSR_MODES2_0 0x00000008U
4867 #define FMC_SDSR_MODES2_1 0x00000010U
4868 #define FMC_SDSR_BUSY 0x00000020U
4870 /******************************************************************************/
4871 /* */
4872 /* General Purpose I/O */
4873 /* */
4874 /******************************************************************************/
4875 /****************** Bits definition for GPIO_MODER register *****************/
4876 #define GPIO_MODER_MODER0 0x00000003U
4877 #define GPIO_MODER_MODER0_0 0x00000001U
4878 #define GPIO_MODER_MODER0_1 0x00000002U
4879 #define GPIO_MODER_MODER1 0x0000000CU
4880 #define GPIO_MODER_MODER1_0 0x00000004U
4881 #define GPIO_MODER_MODER1_1 0x00000008U
4882 #define GPIO_MODER_MODER2 0x00000030U
4883 #define GPIO_MODER_MODER2_0 0x00000010U
4884 #define GPIO_MODER_MODER2_1 0x00000020U
4885 #define GPIO_MODER_MODER3 0x000000C0U
4886 #define GPIO_MODER_MODER3_0 0x00000040U
4887 #define GPIO_MODER_MODER3_1 0x00000080U
4888 #define GPIO_MODER_MODER4 0x00000300U
4889 #define GPIO_MODER_MODER4_0 0x00000100U
4890 #define GPIO_MODER_MODER4_1 0x00000200U
4891 #define GPIO_MODER_MODER5 0x00000C00U
4892 #define GPIO_MODER_MODER5_0 0x00000400U
4893 #define GPIO_MODER_MODER5_1 0x00000800U
4894 #define GPIO_MODER_MODER6 0x00003000U
4895 #define GPIO_MODER_MODER6_0 0x00001000U
4896 #define GPIO_MODER_MODER6_1 0x00002000U
4897 #define GPIO_MODER_MODER7 0x0000C000U
4898 #define GPIO_MODER_MODER7_0 0x00004000U
4899 #define GPIO_MODER_MODER7_1 0x00008000U
4900 #define GPIO_MODER_MODER8 0x00030000U
4901 #define GPIO_MODER_MODER8_0 0x00010000U
4902 #define GPIO_MODER_MODER8_1 0x00020000U
4903 #define GPIO_MODER_MODER9 0x000C0000U
4904 #define GPIO_MODER_MODER9_0 0x00040000U
4905 #define GPIO_MODER_MODER9_1 0x00080000U
4906 #define GPIO_MODER_MODER10 0x00300000U
4907 #define GPIO_MODER_MODER10_0 0x00100000U
4908 #define GPIO_MODER_MODER10_1 0x00200000U
4909 #define GPIO_MODER_MODER11 0x00C00000U
4910 #define GPIO_MODER_MODER11_0 0x00400000U
4911 #define GPIO_MODER_MODER11_1 0x00800000U
4912 #define GPIO_MODER_MODER12 0x03000000U
4913 #define GPIO_MODER_MODER12_0 0x01000000U
4914 #define GPIO_MODER_MODER12_1 0x02000000U
4915 #define GPIO_MODER_MODER13 0x0C000000U
4916 #define GPIO_MODER_MODER13_0 0x04000000U
4917 #define GPIO_MODER_MODER13_1 0x08000000U
4918 #define GPIO_MODER_MODER14 0x30000000U
4919 #define GPIO_MODER_MODER14_0 0x10000000U
4920 #define GPIO_MODER_MODER14_1 0x20000000U
4921 #define GPIO_MODER_MODER15 0xC0000000U
4922 #define GPIO_MODER_MODER15_0 0x40000000U
4923 #define GPIO_MODER_MODER15_1 0x80000000U
4924 
4925 /****************** Bits definition for GPIO_OTYPER register ****************/
4926 #define GPIO_OTYPER_OT_0 0x00000001U
4927 #define GPIO_OTYPER_OT_1 0x00000002U
4928 #define GPIO_OTYPER_OT_2 0x00000004U
4929 #define GPIO_OTYPER_OT_3 0x00000008U
4930 #define GPIO_OTYPER_OT_4 0x00000010U
4931 #define GPIO_OTYPER_OT_5 0x00000020U
4932 #define GPIO_OTYPER_OT_6 0x00000040U
4933 #define GPIO_OTYPER_OT_7 0x00000080U
4934 #define GPIO_OTYPER_OT_8 0x00000100U
4935 #define GPIO_OTYPER_OT_9 0x00000200U
4936 #define GPIO_OTYPER_OT_10 0x00000400U
4937 #define GPIO_OTYPER_OT_11 0x00000800U
4938 #define GPIO_OTYPER_OT_12 0x00001000U
4939 #define GPIO_OTYPER_OT_13 0x00002000U
4940 #define GPIO_OTYPER_OT_14 0x00004000U
4941 #define GPIO_OTYPER_OT_15 0x00008000U
4942 
4943 /****************** Bits definition for GPIO_OSPEEDR register ***************/
4944 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
4945 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
4946 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
4947 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
4948 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
4949 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
4950 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
4951 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
4952 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
4953 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
4954 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
4955 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
4956 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
4957 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
4958 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
4959 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
4960 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
4961 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
4962 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
4963 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
4964 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
4965 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
4966 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
4967 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
4968 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
4969 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
4970 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
4971 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
4972 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
4973 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
4974 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
4975 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
4976 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
4977 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
4978 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
4979 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
4980 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
4981 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
4982 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
4983 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
4984 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
4985 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
4986 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
4987 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
4988 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
4989 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
4990 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
4991 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
4992 
4993 /****************** Bits definition for GPIO_PUPDR register *****************/
4994 #define GPIO_PUPDR_PUPDR0 0x00000003U
4995 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
4996 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
4997 #define GPIO_PUPDR_PUPDR1 0x0000000CU
4998 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
4999 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
5000 #define GPIO_PUPDR_PUPDR2 0x00000030U
5001 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
5002 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
5003 #define GPIO_PUPDR_PUPDR3 0x000000C0U
5004 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
5005 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
5006 #define GPIO_PUPDR_PUPDR4 0x00000300U
5007 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
5008 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
5009 #define GPIO_PUPDR_PUPDR5 0x00000C00U
5010 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
5011 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
5012 #define GPIO_PUPDR_PUPDR6 0x00003000U
5013 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
5014 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
5015 #define GPIO_PUPDR_PUPDR7 0x0000C000U
5016 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
5017 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
5018 #define GPIO_PUPDR_PUPDR8 0x00030000U
5019 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
5020 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
5021 #define GPIO_PUPDR_PUPDR9 0x000C0000U
5022 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
5023 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
5024 #define GPIO_PUPDR_PUPDR10 0x00300000U
5025 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
5026 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
5027 #define GPIO_PUPDR_PUPDR11 0x00C00000U
5028 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
5029 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
5030 #define GPIO_PUPDR_PUPDR12 0x03000000U
5031 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
5032 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
5033 #define GPIO_PUPDR_PUPDR13 0x0C000000U
5034 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
5035 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
5036 #define GPIO_PUPDR_PUPDR14 0x30000000U
5037 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
5038 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
5039 #define GPIO_PUPDR_PUPDR15 0xC0000000U
5040 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
5041 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
5042 
5043 /****************** Bits definition for GPIO_IDR register *******************/
5044 #define GPIO_IDR_IDR_0 0x00000001U
5045 #define GPIO_IDR_IDR_1 0x00000002U
5046 #define GPIO_IDR_IDR_2 0x00000004U
5047 #define GPIO_IDR_IDR_3 0x00000008U
5048 #define GPIO_IDR_IDR_4 0x00000010U
5049 #define GPIO_IDR_IDR_5 0x00000020U
5050 #define GPIO_IDR_IDR_6 0x00000040U
5051 #define GPIO_IDR_IDR_7 0x00000080U
5052 #define GPIO_IDR_IDR_8 0x00000100U
5053 #define GPIO_IDR_IDR_9 0x00000200U
5054 #define GPIO_IDR_IDR_10 0x00000400U
5055 #define GPIO_IDR_IDR_11 0x00000800U
5056 #define GPIO_IDR_IDR_12 0x00001000U
5057 #define GPIO_IDR_IDR_13 0x00002000U
5058 #define GPIO_IDR_IDR_14 0x00004000U
5059 #define GPIO_IDR_IDR_15 0x00008000U
5060 
5061 /****************** Bits definition for GPIO_ODR register *******************/
5062 #define GPIO_ODR_ODR_0 0x00000001U
5063 #define GPIO_ODR_ODR_1 0x00000002U
5064 #define GPIO_ODR_ODR_2 0x00000004U
5065 #define GPIO_ODR_ODR_3 0x00000008U
5066 #define GPIO_ODR_ODR_4 0x00000010U
5067 #define GPIO_ODR_ODR_5 0x00000020U
5068 #define GPIO_ODR_ODR_6 0x00000040U
5069 #define GPIO_ODR_ODR_7 0x00000080U
5070 #define GPIO_ODR_ODR_8 0x00000100U
5071 #define GPIO_ODR_ODR_9 0x00000200U
5072 #define GPIO_ODR_ODR_10 0x00000400U
5073 #define GPIO_ODR_ODR_11 0x00000800U
5074 #define GPIO_ODR_ODR_12 0x00001000U
5075 #define GPIO_ODR_ODR_13 0x00002000U
5076 #define GPIO_ODR_ODR_14 0x00004000U
5077 #define GPIO_ODR_ODR_15 0x00008000U
5078 
5079 /****************** Bits definition for GPIO_BSRR register ******************/
5080 #define GPIO_BSRR_BS_0 0x00000001U
5081 #define GPIO_BSRR_BS_1 0x00000002U
5082 #define GPIO_BSRR_BS_2 0x00000004U
5083 #define GPIO_BSRR_BS_3 0x00000008U
5084 #define GPIO_BSRR_BS_4 0x00000010U
5085 #define GPIO_BSRR_BS_5 0x00000020U
5086 #define GPIO_BSRR_BS_6 0x00000040U
5087 #define GPIO_BSRR_BS_7 0x00000080U
5088 #define GPIO_BSRR_BS_8 0x00000100U
5089 #define GPIO_BSRR_BS_9 0x00000200U
5090 #define GPIO_BSRR_BS_10 0x00000400U
5091 #define GPIO_BSRR_BS_11 0x00000800U
5092 #define GPIO_BSRR_BS_12 0x00001000U
5093 #define GPIO_BSRR_BS_13 0x00002000U
5094 #define GPIO_BSRR_BS_14 0x00004000U
5095 #define GPIO_BSRR_BS_15 0x00008000U
5096 #define GPIO_BSRR_BR_0 0x00010000U
5097 #define GPIO_BSRR_BR_1 0x00020000U
5098 #define GPIO_BSRR_BR_2 0x00040000U
5099 #define GPIO_BSRR_BR_3 0x00080000U
5100 #define GPIO_BSRR_BR_4 0x00100000U
5101 #define GPIO_BSRR_BR_5 0x00200000U
5102 #define GPIO_BSRR_BR_6 0x00400000U
5103 #define GPIO_BSRR_BR_7 0x00800000U
5104 #define GPIO_BSRR_BR_8 0x01000000U
5105 #define GPIO_BSRR_BR_9 0x02000000U
5106 #define GPIO_BSRR_BR_10 0x04000000U
5107 #define GPIO_BSRR_BR_11 0x08000000U
5108 #define GPIO_BSRR_BR_12 0x10000000U
5109 #define GPIO_BSRR_BR_13 0x20000000U
5110 #define GPIO_BSRR_BR_14 0x40000000U
5111 #define GPIO_BSRR_BR_15 0x80000000U
5112 
5113 /****************** Bit definition for GPIO_LCKR register *********************/
5114 #define GPIO_LCKR_LCK0 0x00000001U
5115 #define GPIO_LCKR_LCK1 0x00000002U
5116 #define GPIO_LCKR_LCK2 0x00000004U
5117 #define GPIO_LCKR_LCK3 0x00000008U
5118 #define GPIO_LCKR_LCK4 0x00000010U
5119 #define GPIO_LCKR_LCK5 0x00000020U
5120 #define GPIO_LCKR_LCK6 0x00000040U
5121 #define GPIO_LCKR_LCK7 0x00000080U
5122 #define GPIO_LCKR_LCK8 0x00000100U
5123 #define GPIO_LCKR_LCK9 0x00000200U
5124 #define GPIO_LCKR_LCK10 0x00000400U
5125 #define GPIO_LCKR_LCK11 0x00000800U
5126 #define GPIO_LCKR_LCK12 0x00001000U
5127 #define GPIO_LCKR_LCK13 0x00002000U
5128 #define GPIO_LCKR_LCK14 0x00004000U
5129 #define GPIO_LCKR_LCK15 0x00008000U
5130 #define GPIO_LCKR_LCKK 0x00010000U
5131 
5132 
5133 /******************************************************************************/
5134 /* */
5135 /* Inter-integrated Circuit Interface (I2C) */
5136 /* */
5137 /******************************************************************************/
5138 /******************* Bit definition for I2C_CR1 register *******************/
5139 #define I2C_CR1_PE 0x00000001U
5140 #define I2C_CR1_TXIE 0x00000002U
5141 #define I2C_CR1_RXIE 0x00000004U
5142 #define I2C_CR1_ADDRIE 0x00000008U
5143 #define I2C_CR1_NACKIE 0x00000010U
5144 #define I2C_CR1_STOPIE 0x00000020U
5145 #define I2C_CR1_TCIE 0x00000040U
5146 #define I2C_CR1_ERRIE 0x00000080U
5147 #define I2C_CR1_DNF 0x00000F00U
5148 #define I2C_CR1_ANFOFF 0x00001000U
5149 #define I2C_CR1_TXDMAEN 0x00004000U
5150 #define I2C_CR1_RXDMAEN 0x00008000U
5151 #define I2C_CR1_SBC 0x00010000U
5152 #define I2C_CR1_NOSTRETCH 0x00020000U
5153 #define I2C_CR1_GCEN 0x00080000U
5154 #define I2C_CR1_SMBHEN 0x00100000U
5155 #define I2C_CR1_SMBDEN 0x00200000U
5156 #define I2C_CR1_ALERTEN 0x00400000U
5157 #define I2C_CR1_PECEN 0x00800000U
5160 /****************** Bit definition for I2C_CR2 register ********************/
5161 #define I2C_CR2_SADD 0x000003FFU
5162 #define I2C_CR2_RD_WRN 0x00000400U
5163 #define I2C_CR2_ADD10 0x00000800U
5164 #define I2C_CR2_HEAD10R 0x00001000U
5165 #define I2C_CR2_START 0x00002000U
5166 #define I2C_CR2_STOP 0x00004000U
5167 #define I2C_CR2_NACK 0x00008000U
5168 #define I2C_CR2_NBYTES 0x00FF0000U
5169 #define I2C_CR2_RELOAD 0x01000000U
5170 #define I2C_CR2_AUTOEND 0x02000000U
5171 #define I2C_CR2_PECBYTE 0x04000000U
5173 /******************* Bit definition for I2C_OAR1 register ******************/
5174 #define I2C_OAR1_OA1 0x000003FFU
5175 #define I2C_OAR1_OA1MODE 0x00000400U
5176 #define I2C_OAR1_OA1EN 0x00008000U
5178 /******************* Bit definition for I2C_OAR2 register ******************/
5179 #define I2C_OAR2_OA2 0x000000FEU
5180 #define I2C_OAR2_OA2MSK 0x00000700U
5181 #define I2C_OAR2_OA2NOMASK 0x00000000U
5182 #define I2C_OAR2_OA2MASK01 0x00000100U
5183 #define I2C_OAR2_OA2MASK02 0x00000200U
5184 #define I2C_OAR2_OA2MASK03 0x00000300U
5185 #define I2C_OAR2_OA2MASK04 0x00000400U
5186 #define I2C_OAR2_OA2MASK05 0x00000500U
5187 #define I2C_OAR2_OA2MASK06 0x00000600U
5188 #define I2C_OAR2_OA2MASK07 0x00000700U
5189 #define I2C_OAR2_OA2EN 0x00008000U
5191 /******************* Bit definition for I2C_TIMINGR register *******************/
5192 #define I2C_TIMINGR_SCLL 0x000000FFU
5193 #define I2C_TIMINGR_SCLH 0x0000FF00U
5194 #define I2C_TIMINGR_SDADEL 0x000F0000U
5195 #define I2C_TIMINGR_SCLDEL 0x00F00000U
5196 #define I2C_TIMINGR_PRESC 0xF0000000U
5198 /******************* Bit definition for I2C_TIMEOUTR register *******************/
5199 #define I2C_TIMEOUTR_TIMEOUTA 0x00000FFFU
5200 #define I2C_TIMEOUTR_TIDLE 0x00001000U
5201 #define I2C_TIMEOUTR_TIMOUTEN 0x00008000U
5202 #define I2C_TIMEOUTR_TIMEOUTB 0x0FFF0000U
5203 #define I2C_TIMEOUTR_TEXTEN 0x80000000U
5205 /****************** Bit definition for I2C_ISR register *********************/
5206 #define I2C_ISR_TXE 0x00000001U
5207 #define I2C_ISR_TXIS 0x00000002U
5208 #define I2C_ISR_RXNE 0x00000004U
5209 #define I2C_ISR_ADDR 0x00000008U
5210 #define I2C_ISR_NACKF 0x00000010U
5211 #define I2C_ISR_STOPF 0x00000020U
5212 #define I2C_ISR_TC 0x00000040U
5213 #define I2C_ISR_TCR 0x00000080U
5214 #define I2C_ISR_BERR 0x00000100U
5215 #define I2C_ISR_ARLO 0x00000200U
5216 #define I2C_ISR_OVR 0x00000400U
5217 #define I2C_ISR_PECERR 0x00000800U
5218 #define I2C_ISR_TIMEOUT 0x00001000U
5219 #define I2C_ISR_ALERT 0x00002000U
5220 #define I2C_ISR_BUSY 0x00008000U
5221 #define I2C_ISR_DIR 0x00010000U
5222 #define I2C_ISR_ADDCODE 0x00FE0000U
5224 /****************** Bit definition for I2C_ICR register *********************/
5225 #define I2C_ICR_ADDRCF 0x00000008U
5226 #define I2C_ICR_NACKCF 0x00000010U
5227 #define I2C_ICR_STOPCF 0x00000020U
5228 #define I2C_ICR_BERRCF 0x00000100U
5229 #define I2C_ICR_ARLOCF 0x00000200U
5230 #define I2C_ICR_OVRCF 0x00000400U
5231 #define I2C_ICR_PECCF 0x00000800U
5232 #define I2C_ICR_TIMOUTCF 0x00001000U
5233 #define I2C_ICR_ALERTCF 0x00002000U
5235 /****************** Bit definition for I2C_PECR register *********************/
5236 #define I2C_PECR_PEC 0x000000FFU
5238 /****************** Bit definition for I2C_RXDR register *********************/
5239 #define I2C_RXDR_RXDATA 0x000000FFU
5241 /****************** Bit definition for I2C_TXDR register *********************/
5242 #define I2C_TXDR_TXDATA 0x000000FFU
5245 /******************************************************************************/
5246 /* */
5247 /* Independent WATCHDOG */
5248 /* */
5249 /******************************************************************************/
5250 /******************* Bit definition for IWDG_KR register ********************/
5251 #define IWDG_KR_KEY 0xFFFFU
5253 /******************* Bit definition for IWDG_PR register ********************/
5254 #define IWDG_PR_PR 0x07U
5255 #define IWDG_PR_PR_0 0x01U
5256 #define IWDG_PR_PR_1 0x02U
5257 #define IWDG_PR_PR_2 0x04U
5259 /******************* Bit definition for IWDG_RLR register *******************/
5260 #define IWDG_RLR_RL 0x0FFFU
5262 /******************* Bit definition for IWDG_SR register ********************/
5263 #define IWDG_SR_PVU 0x01U
5264 #define IWDG_SR_RVU 0x02U
5265 #define IWDG_SR_WVU 0x04U
5267 /******************* Bit definition for IWDG_KR register ********************/
5268 #define IWDG_WINR_WIN 0x0FFFU
5271 /******************************************************************************/
5272 /* */
5273 /* Power Control */
5274 /* */
5275 /******************************************************************************/
5276 /******************** Bit definition for PWR_CR1 register ********************/
5277 #define PWR_CR1_LPDS 0x00000001U
5278 #define PWR_CR1_PDDS 0x00000002U
5279 #define PWR_CR1_CSBF 0x00000008U
5280 #define PWR_CR1_PVDE 0x00000010U
5281 #define PWR_CR1_PLS 0x000000E0U
5282 #define PWR_CR1_PLS_0 0x00000020U
5283 #define PWR_CR1_PLS_1 0x00000040U
5284 #define PWR_CR1_PLS_2 0x00000080U
5287 #define PWR_CR1_PLS_LEV0 0x00000000U
5288 #define PWR_CR1_PLS_LEV1 0x00000020U
5289 #define PWR_CR1_PLS_LEV2 0x00000040U
5290 #define PWR_CR1_PLS_LEV3 0x00000060U
5291 #define PWR_CR1_PLS_LEV4 0x00000080U
5292 #define PWR_CR1_PLS_LEV5 0x000000A0U
5293 #define PWR_CR1_PLS_LEV6 0x000000C0U
5294 #define PWR_CR1_PLS_LEV7 0x000000E0U
5295 #define PWR_CR1_DBP 0x00000100U
5296 #define PWR_CR1_FPDS 0x00000200U
5297 #define PWR_CR1_LPUDS 0x00000400U
5298 #define PWR_CR1_MRUDS 0x00000800U
5299 #define PWR_CR1_ADCDC1 0x00002000U
5300 #define PWR_CR1_VOS 0x0000C000U
5301 #define PWR_CR1_VOS_0 0x00004000U
5302 #define PWR_CR1_VOS_1 0x00008000U
5303 #define PWR_CR1_ODEN 0x00010000U
5304 #define PWR_CR1_ODSWEN 0x00020000U
5305 #define PWR_CR1_UDEN 0x000C0000U
5306 #define PWR_CR1_UDEN_0 0x00040000U
5307 #define PWR_CR1_UDEN_1 0x00080000U
5309 /******************* Bit definition for PWR_CSR1 register ********************/
5310 #define PWR_CSR1_WUIF 0x00000001U
5311 #define PWR_CSR1_SBF 0x00000002U
5312 #define PWR_CSR1_PVDO 0x00000004U
5313 #define PWR_CSR1_BRR 0x00000008U
5314 #define PWR_CSR1_EIWUP 0x00000100U
5315 #define PWR_CSR1_BRE 0x00000200U
5316 #define PWR_CSR1_VOSRDY 0x00004000U
5317 #define PWR_CSR1_ODRDY 0x00010000U
5318 #define PWR_CSR1_ODSWRDY 0x00020000U
5319 #define PWR_CSR1_UDRDY 0x000C0000U
5322 /******************** Bit definition for PWR_CR2 register ********************/
5323 #define PWR_CR2_CWUPF1 0x00000001U
5324 #define PWR_CR2_CWUPF2 0x00000002U
5325 #define PWR_CR2_CWUPF3 0x00000004U
5326 #define PWR_CR2_CWUPF4 0x00000008U
5327 #define PWR_CR2_CWUPF5 0x00000010U
5328 #define PWR_CR2_CWUPF6 0x00000020U
5329 #define PWR_CR2_WUPP1 0x00000100U
5330 #define PWR_CR2_WUPP2 0x00000200U
5331 #define PWR_CR2_WUPP3 0x00000400U
5332 #define PWR_CR2_WUPP4 0x00000800U
5333 #define PWR_CR2_WUPP5 0x00001000U
5334 #define PWR_CR2_WUPP6 0x00002000U
5336 /******************* Bit definition for PWR_CSR2 register ********************/
5337 #define PWR_CSR2_WUPF1 0x00000001U
5338 #define PWR_CSR2_WUPF2 0x00000002U
5339 #define PWR_CSR2_WUPF3 0x00000004U
5340 #define PWR_CSR2_WUPF4 0x00000008U
5341 #define PWR_CSR2_WUPF5 0x00000010U
5342 #define PWR_CSR2_WUPF6 0x00000020U
5343 #define PWR_CSR2_EWUP1 0x00000100U
5344 #define PWR_CSR2_EWUP2 0x00000200U
5345 #define PWR_CSR2_EWUP3 0x00000400U
5346 #define PWR_CSR2_EWUP4 0x00000800U
5347 #define PWR_CSR2_EWUP5 0x00001000U
5348 #define PWR_CSR2_EWUP6 0x00002000U
5350 /******************************************************************************/
5351 /* */
5352 /* QUADSPI */
5353 /* */
5354 /******************************************************************************/
5355 /***************** Bit definition for QUADSPI_CR register *******************/
5356 #define QUADSPI_CR_EN 0x00000001U
5357 #define QUADSPI_CR_ABORT 0x00000002U
5358 #define QUADSPI_CR_DMAEN 0x00000004U
5359 #define QUADSPI_CR_TCEN 0x00000008U
5360 #define QUADSPI_CR_SSHIFT 0x00000010U
5361 #define QUADSPI_CR_DFM 0x00000040U
5362 #define QUADSPI_CR_FSEL 0x00000080U
5363 #define QUADSPI_CR_FTHRES 0x00001F00U
5364 #define QUADSPI_CR_FTHRES_0 0x00000100U
5365 #define QUADSPI_CR_FTHRES_1 0x00000200U
5366 #define QUADSPI_CR_FTHRES_2 0x00000400U
5367 #define QUADSPI_CR_FTHRES_3 0x00000800U
5368 #define QUADSPI_CR_FTHRES_4 0x00001000U
5369 #define QUADSPI_CR_TEIE 0x00010000U
5370 #define QUADSPI_CR_TCIE 0x00020000U
5371 #define QUADSPI_CR_FTIE 0x00040000U
5372 #define QUADSPI_CR_SMIE 0x00080000U
5373 #define QUADSPI_CR_TOIE 0x00100000U
5374 #define QUADSPI_CR_APMS 0x00400000U
5375 #define QUADSPI_CR_PMM 0x00800000U
5376 #define QUADSPI_CR_PRESCALER 0xFF000000U
5377 #define QUADSPI_CR_PRESCALER_0 0x01000000U
5378 #define QUADSPI_CR_PRESCALER_1 0x02000000U
5379 #define QUADSPI_CR_PRESCALER_2 0x04000000U
5380 #define QUADSPI_CR_PRESCALER_3 0x08000000U
5381 #define QUADSPI_CR_PRESCALER_4 0x10000000U
5382 #define QUADSPI_CR_PRESCALER_5 0x20000000U
5383 #define QUADSPI_CR_PRESCALER_6 0x40000000U
5384 #define QUADSPI_CR_PRESCALER_7 0x80000000U
5386 /***************** Bit definition for QUADSPI_DCR register ******************/
5387 #define QUADSPI_DCR_CKMODE 0x00000001U
5388 #define QUADSPI_DCR_CSHT 0x00000700U
5389 #define QUADSPI_DCR_CSHT_0 0x00000100U
5390 #define QUADSPI_DCR_CSHT_1 0x00000200U
5391 #define QUADSPI_DCR_CSHT_2 0x00000400U
5392 #define QUADSPI_DCR_FSIZE 0x001F0000U
5393 #define QUADSPI_DCR_FSIZE_0 0x00010000U
5394 #define QUADSPI_DCR_FSIZE_1 0x00020000U
5395 #define QUADSPI_DCR_FSIZE_2 0x00040000U
5396 #define QUADSPI_DCR_FSIZE_3 0x00080000U
5397 #define QUADSPI_DCR_FSIZE_4 0x00100000U
5399 /****************** Bit definition for QUADSPI_SR register *******************/
5400 #define QUADSPI_SR_TEF 0x00000001U
5401 #define QUADSPI_SR_TCF 0x00000002U
5402 #define QUADSPI_SR_FTF 0x00000004U
5403 #define QUADSPI_SR_SMF 0x00000008U
5404 #define QUADSPI_SR_TOF 0x00000010U
5405 #define QUADSPI_SR_BUSY 0x00000020U
5406 #define QUADSPI_SR_FLEVEL 0x00001F00U
5407 #define QUADSPI_SR_FLEVEL_0 0x00000100U
5408 #define QUADSPI_SR_FLEVEL_1 0x00000200U
5409 #define QUADSPI_SR_FLEVEL_2 0x00000400U
5410 #define QUADSPI_SR_FLEVEL_3 0x00000800U
5411 #define QUADSPI_SR_FLEVEL_4 0x00001000U
5413 /****************** Bit definition for QUADSPI_FCR register ******************/
5414 #define QUADSPI_FCR_CTEF 0x00000001U
5415 #define QUADSPI_FCR_CTCF 0x00000002U
5416 #define QUADSPI_FCR_CSMF 0x00000008U
5417 #define QUADSPI_FCR_CTOF 0x00000010U
5419 /****************** Bit definition for QUADSPI_DLR register ******************/
5420 #define QUADSPI_DLR_DL 0xFFFFFFFFU
5422 /****************** Bit definition for QUADSPI_CCR register ******************/
5423 #define QUADSPI_CCR_INSTRUCTION 0x000000FFU
5424 #define QUADSPI_CCR_INSTRUCTION_0 0x00000001U
5425 #define QUADSPI_CCR_INSTRUCTION_1 0x00000002U
5426 #define QUADSPI_CCR_INSTRUCTION_2 0x00000004U
5427 #define QUADSPI_CCR_INSTRUCTION_3 0x00000008U
5428 #define QUADSPI_CCR_INSTRUCTION_4 0x00000010U
5429 #define QUADSPI_CCR_INSTRUCTION_5 0x00000020U
5430 #define QUADSPI_CCR_INSTRUCTION_6 0x00000040U
5431 #define QUADSPI_CCR_INSTRUCTION_7 0x00000080U
5432 #define QUADSPI_CCR_IMODE 0x00000300U
5433 #define QUADSPI_CCR_IMODE_0 0x00000100U
5434 #define QUADSPI_CCR_IMODE_1 0x00000200U
5435 #define QUADSPI_CCR_ADMODE 0x00000C00U
5436 #define QUADSPI_CCR_ADMODE_0 0x00000400U
5437 #define QUADSPI_CCR_ADMODE_1 0x00000800U
5438 #define QUADSPI_CCR_ADSIZE 0x00003000U
5439 #define QUADSPI_CCR_ADSIZE_0 0x00001000U
5440 #define QUADSPI_CCR_ADSIZE_1 0x00002000U
5441 #define QUADSPI_CCR_ABMODE 0x0000C000U
5442 #define QUADSPI_CCR_ABMODE_0 0x00004000U
5443 #define QUADSPI_CCR_ABMODE_1 0x00008000U
5444 #define QUADSPI_CCR_ABSIZE 0x00030000U
5445 #define QUADSPI_CCR_ABSIZE_0 0x00010000U
5446 #define QUADSPI_CCR_ABSIZE_1 0x00020000U
5447 #define QUADSPI_CCR_DCYC 0x007C0000U
5448 #define QUADSPI_CCR_DCYC_0 0x00040000U
5449 #define QUADSPI_CCR_DCYC_1 0x00080000U
5450 #define QUADSPI_CCR_DCYC_2 0x00100000U
5451 #define QUADSPI_CCR_DCYC_3 0x00200000U
5452 #define QUADSPI_CCR_DCYC_4 0x00400000U
5453 #define QUADSPI_CCR_DMODE 0x03000000U
5454 #define QUADSPI_CCR_DMODE_0 0x01000000U
5455 #define QUADSPI_CCR_DMODE_1 0x02000000U
5456 #define QUADSPI_CCR_FMODE 0x0C000000U
5457 #define QUADSPI_CCR_FMODE_0 0x04000000U
5458 #define QUADSPI_CCR_FMODE_1 0x08000000U
5459 #define QUADSPI_CCR_SIOO 0x10000000U
5460 #define QUADSPI_CCR_DHHC 0x40000000U
5461 #define QUADSPI_CCR_DDRM 0x80000000U
5462 /****************** Bit definition for QUADSPI_AR register *******************/
5463 #define QUADSPI_AR_ADDRESS 0xFFFFFFFFU
5465 /****************** Bit definition for QUADSPI_ABR register ******************/
5466 #define QUADSPI_ABR_ALTERNATE 0xFFFFFFFFU
5468 /****************** Bit definition for QUADSPI_DR register *******************/
5469 #define QUADSPI_DR_DATA 0xFFFFFFFFU
5471 /****************** Bit definition for QUADSPI_PSMKR register ****************/
5472 #define QUADSPI_PSMKR_MASK 0xFFFFFFFFU
5474 /****************** Bit definition for QUADSPI_PSMAR register ****************/
5475 #define QUADSPI_PSMAR_MATCH 0xFFFFFFFFU
5477 /****************** Bit definition for QUADSPI_PIR register *****************/
5478 #define QUADSPI_PIR_INTERVAL 0x0000FFFFU
5480 /****************** Bit definition for QUADSPI_LPTR register *****************/
5481 #define QUADSPI_LPTR_TIMEOUT 0x0000FFFFU
5483 /******************************************************************************/
5484 /* */
5485 /* Reset and Clock Control */
5486 /* */
5487 /******************************************************************************/
5488 /******************** Bit definition for RCC_CR register ********************/
5489 #define RCC_CR_HSION 0x00000001U
5490 #define RCC_CR_HSIRDY 0x00000002U
5491 #define RCC_CR_HSITRIM 0x000000F8U
5492 #define RCC_CR_HSITRIM_0 0x00000008U
5493 #define RCC_CR_HSITRIM_1 0x00000010U
5494 #define RCC_CR_HSITRIM_2 0x00000020U
5495 #define RCC_CR_HSITRIM_3 0x00000040U
5496 #define RCC_CR_HSITRIM_4 0x00000080U
5497 #define RCC_CR_HSICAL 0x0000FF00U
5498 #define RCC_CR_HSICAL_0 0x00000100U
5499 #define RCC_CR_HSICAL_1 0x00000200U
5500 #define RCC_CR_HSICAL_2 0x00000400U
5501 #define RCC_CR_HSICAL_3 0x00000800U
5502 #define RCC_CR_HSICAL_4 0x00001000U
5503 #define RCC_CR_HSICAL_5 0x00002000U
5504 #define RCC_CR_HSICAL_6 0x00004000U
5505 #define RCC_CR_HSICAL_7 0x00008000U
5506 #define RCC_CR_HSEON 0x00010000U
5507 #define RCC_CR_HSERDY 0x00020000U
5508 #define RCC_CR_HSEBYP 0x00040000U
5509 #define RCC_CR_CSSON 0x00080000U
5510 #define RCC_CR_PLLON 0x01000000U
5511 #define RCC_CR_PLLRDY 0x02000000U
5512 #define RCC_CR_PLLI2SON 0x04000000U
5513 #define RCC_CR_PLLI2SRDY 0x08000000U
5514 #define RCC_CR_PLLSAION 0x10000000U
5515 #define RCC_CR_PLLSAIRDY 0x20000000U
5516 
5517 /******************** Bit definition for RCC_PLLCFGR register ***************/
5518 #define RCC_PLLCFGR_PLLM 0x0000003FU
5519 #define RCC_PLLCFGR_PLLM_0 0x00000001U
5520 #define RCC_PLLCFGR_PLLM_1 0x00000002U
5521 #define RCC_PLLCFGR_PLLM_2 0x00000004U
5522 #define RCC_PLLCFGR_PLLM_3 0x00000008U
5523 #define RCC_PLLCFGR_PLLM_4 0x00000010U
5524 #define RCC_PLLCFGR_PLLM_5 0x00000020U
5525 #define RCC_PLLCFGR_PLLN 0x00007FC0U
5526 #define RCC_PLLCFGR_PLLN_0 0x00000040U
5527 #define RCC_PLLCFGR_PLLN_1 0x00000080U
5528 #define RCC_PLLCFGR_PLLN_2 0x00000100U
5529 #define RCC_PLLCFGR_PLLN_3 0x00000200U
5530 #define RCC_PLLCFGR_PLLN_4 0x00000400U
5531 #define RCC_PLLCFGR_PLLN_5 0x00000800U
5532 #define RCC_PLLCFGR_PLLN_6 0x00001000U
5533 #define RCC_PLLCFGR_PLLN_7 0x00002000U
5534 #define RCC_PLLCFGR_PLLN_8 0x00004000U
5535 #define RCC_PLLCFGR_PLLP 0x00030000U
5536 #define RCC_PLLCFGR_PLLP_0 0x00010000U
5537 #define RCC_PLLCFGR_PLLP_1 0x00020000U
5538 #define RCC_PLLCFGR_PLLSRC 0x00400000U
5539 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
5540 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
5541 #define RCC_PLLCFGR_PLLQ 0x0F000000U
5542 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
5543 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
5544 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
5545 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
5546 
5547 #define RCC_PLLCFGR_PLLR 0x70000000U
5548 #define RCC_PLLCFGR_PLLR_0 0x10000000U
5549 #define RCC_PLLCFGR_PLLR_1 0x20000000U
5550 #define RCC_PLLCFGR_PLLR_2 0x40000000U
5551 
5552 /******************** Bit definition for RCC_CFGR register ******************/
5554 #define RCC_CFGR_SW 0x00000003U
5555 #define RCC_CFGR_SW_0 0x00000001U
5556 #define RCC_CFGR_SW_1 0x00000002U
5557 #define RCC_CFGR_SW_HSI 0x00000000U
5558 #define RCC_CFGR_SW_HSE 0x00000001U
5559 #define RCC_CFGR_SW_PLL 0x00000002U
5562 #define RCC_CFGR_SWS 0x0000000CU
5563 #define RCC_CFGR_SWS_0 0x00000004U
5564 #define RCC_CFGR_SWS_1 0x00000008U
5565 #define RCC_CFGR_SWS_HSI 0x00000000U
5566 #define RCC_CFGR_SWS_HSE 0x00000004U
5567 #define RCC_CFGR_SWS_PLL 0x00000008U
5570 #define RCC_CFGR_HPRE 0x000000F0U
5571 #define RCC_CFGR_HPRE_0 0x00000010U
5572 #define RCC_CFGR_HPRE_1 0x00000020U
5573 #define RCC_CFGR_HPRE_2 0x00000040U
5574 #define RCC_CFGR_HPRE_3 0x00000080U
5576 #define RCC_CFGR_HPRE_DIV1 0x00000000U
5577 #define RCC_CFGR_HPRE_DIV2 0x00000080U
5578 #define RCC_CFGR_HPRE_DIV4 0x00000090U
5579 #define RCC_CFGR_HPRE_DIV8 0x000000A0U
5580 #define RCC_CFGR_HPRE_DIV16 0x000000B0U
5581 #define RCC_CFGR_HPRE_DIV64 0x000000C0U
5582 #define RCC_CFGR_HPRE_DIV128 0x000000D0U
5583 #define RCC_CFGR_HPRE_DIV256 0x000000E0U
5584 #define RCC_CFGR_HPRE_DIV512 0x000000F0U
5587 #define RCC_CFGR_PPRE1 0x00001C00U
5588 #define RCC_CFGR_PPRE1_0 0x00000400U
5589 #define RCC_CFGR_PPRE1_1 0x00000800U
5590 #define RCC_CFGR_PPRE1_2 0x00001000U
5592 #define RCC_CFGR_PPRE1_DIV1 0x00000000U
5593 #define RCC_CFGR_PPRE1_DIV2 0x00001000U
5594 #define RCC_CFGR_PPRE1_DIV4 0x00001400U
5595 #define RCC_CFGR_PPRE1_DIV8 0x00001800U
5596 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U
5599 #define RCC_CFGR_PPRE2 0x0000E000U
5600 #define RCC_CFGR_PPRE2_0 0x00002000U
5601 #define RCC_CFGR_PPRE2_1 0x00004000U
5602 #define RCC_CFGR_PPRE2_2 0x00008000U
5604 #define RCC_CFGR_PPRE2_DIV1 0x00000000U
5605 #define RCC_CFGR_PPRE2_DIV2 0x00008000U
5606 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U
5607 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U
5608 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U
5611 #define RCC_CFGR_RTCPRE 0x001F0000U
5612 #define RCC_CFGR_RTCPRE_0 0x00010000U
5613 #define RCC_CFGR_RTCPRE_1 0x00020000U
5614 #define RCC_CFGR_RTCPRE_2 0x00040000U
5615 #define RCC_CFGR_RTCPRE_3 0x00080000U
5616 #define RCC_CFGR_RTCPRE_4 0x00100000U
5617 
5619 #define RCC_CFGR_MCO1 0x00600000U
5620 #define RCC_CFGR_MCO1_0 0x00200000U
5621 #define RCC_CFGR_MCO1_1 0x00400000U
5622 
5623 #define RCC_CFGR_I2SSRC 0x00800000U
5624 
5625 #define RCC_CFGR_MCO1PRE 0x07000000U
5626 #define RCC_CFGR_MCO1PRE_0 0x01000000U
5627 #define RCC_CFGR_MCO1PRE_1 0x02000000U
5628 #define RCC_CFGR_MCO1PRE_2 0x04000000U
5629 
5630 #define RCC_CFGR_MCO2PRE 0x38000000U
5631 #define RCC_CFGR_MCO2PRE_0 0x08000000U
5632 #define RCC_CFGR_MCO2PRE_1 0x10000000U
5633 #define RCC_CFGR_MCO2PRE_2 0x20000000U
5634 
5635 #define RCC_CFGR_MCO2 0xC0000000U
5636 #define RCC_CFGR_MCO2_0 0x40000000U
5637 #define RCC_CFGR_MCO2_1 0x80000000U
5638 
5639 /******************** Bit definition for RCC_CIR register *******************/
5640 #define RCC_CIR_LSIRDYF 0x00000001U
5641 #define RCC_CIR_LSERDYF 0x00000002U
5642 #define RCC_CIR_HSIRDYF 0x00000004U
5643 #define RCC_CIR_HSERDYF 0x00000008U
5644 #define RCC_CIR_PLLRDYF 0x00000010U
5645 #define RCC_CIR_PLLI2SRDYF 0x00000020U
5646 #define RCC_CIR_PLLSAIRDYF 0x00000040U
5647 #define RCC_CIR_CSSF 0x00000080U
5648 #define RCC_CIR_LSIRDYIE 0x00000100U
5649 #define RCC_CIR_LSERDYIE 0x00000200U
5650 #define RCC_CIR_HSIRDYIE 0x00000400U
5651 #define RCC_CIR_HSERDYIE 0x00000800U
5652 #define RCC_CIR_PLLRDYIE 0x00001000U
5653 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
5654 #define RCC_CIR_PLLSAIRDYIE 0x00004000U
5655 #define RCC_CIR_LSIRDYC 0x00010000U
5656 #define RCC_CIR_LSERDYC 0x00020000U
5657 #define RCC_CIR_HSIRDYC 0x00040000U
5658 #define RCC_CIR_HSERDYC 0x00080000U
5659 #define RCC_CIR_PLLRDYC 0x00100000U
5660 #define RCC_CIR_PLLI2SRDYC 0x00200000U
5661 #define RCC_CIR_PLLSAIRDYC 0x00400000U
5662 #define RCC_CIR_CSSC 0x00800000U
5663 
5664 /******************** Bit definition for RCC_AHB1RSTR register **************/
5665 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
5666 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
5667 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
5668 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
5669 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
5670 #define RCC_AHB1RSTR_GPIOFRST 0x00000020U
5671 #define RCC_AHB1RSTR_GPIOGRST 0x00000040U
5672 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
5673 #define RCC_AHB1RSTR_GPIOIRST 0x00000100U
5674 #define RCC_AHB1RSTR_GPIOJRST 0x00000200U
5675 #define RCC_AHB1RSTR_GPIOKRST 0x00000400U
5676 #define RCC_AHB1RSTR_CRCRST 0x00001000U
5677 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
5678 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
5679 #define RCC_AHB1RSTR_DMA2DRST 0x00800000U
5680 #define RCC_AHB1RSTR_ETHMACRST 0x02000000U
5681 #define RCC_AHB1RSTR_OTGHRST 0x20000000U
5682 
5683 /******************** Bit definition for RCC_AHB2RSTR register **************/
5684 #define RCC_AHB2RSTR_DCMIRST 0x00000001U
5685 #define RCC_AHB2RSTR_RNGRST 0x00000040U
5686 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
5687 
5688 /******************** Bit definition for RCC_AHB3RSTR register **************/
5689 
5690 #define RCC_AHB3RSTR_FMCRST 0x00000001U
5691 #define RCC_AHB3RSTR_QSPIRST 0x00000002U
5692 
5693 /******************** Bit definition for RCC_APB1RSTR register **************/
5694 #define RCC_APB1RSTR_TIM2RST 0x00000001U
5695 #define RCC_APB1RSTR_TIM3RST 0x00000002U
5696 #define RCC_APB1RSTR_TIM4RST 0x00000004U
5697 #define RCC_APB1RSTR_TIM5RST 0x00000008U
5698 #define RCC_APB1RSTR_TIM6RST 0x00000010U
5699 #define RCC_APB1RSTR_TIM7RST 0x00000020U
5700 #define RCC_APB1RSTR_TIM12RST 0x00000040U
5701 #define RCC_APB1RSTR_TIM13RST 0x00000080U
5702 #define RCC_APB1RSTR_TIM14RST 0x00000100U
5703 #define RCC_APB1RSTR_LPTIM1RST 0x00000200U
5704 #define RCC_APB1RSTR_WWDGRST 0x00000800U
5705 #define RCC_APB1RSTR_CAN3RST 0x00002000U
5706 #define RCC_APB1RSTR_SPI2RST 0x00004000U
5707 #define RCC_APB1RSTR_SPI3RST 0x00008000U
5708 #define RCC_APB1RSTR_SPDIFRXRST 0x00010000U
5709 #define RCC_APB1RSTR_USART2RST 0x00020000U
5710 #define RCC_APB1RSTR_USART3RST 0x00040000U
5711 #define RCC_APB1RSTR_UART4RST 0x00080000U
5712 #define RCC_APB1RSTR_UART5RST 0x00100000U
5713 #define RCC_APB1RSTR_I2C1RST 0x00200000U
5714 #define RCC_APB1RSTR_I2C2RST 0x00400000U
5715 #define RCC_APB1RSTR_I2C3RST 0x00800000U
5716 #define RCC_APB1RSTR_I2C4RST 0x01000000U
5717 #define RCC_APB1RSTR_CAN1RST 0x02000000U
5718 #define RCC_APB1RSTR_CAN2RST 0x04000000U
5719 #define RCC_APB1RSTR_CECRST 0x08000000U
5720 #define RCC_APB1RSTR_PWRRST 0x10000000U
5721 #define RCC_APB1RSTR_DACRST 0x20000000U
5722 #define RCC_APB1RSTR_UART7RST 0x40000000U
5723 #define RCC_APB1RSTR_UART8RST 0x80000000U
5724 
5725 /******************** Bit definition for RCC_APB2RSTR register **************/
5726 #define RCC_APB2RSTR_TIM1RST 0x00000001U
5727 #define RCC_APB2RSTR_TIM8RST 0x00000002U
5728 #define RCC_APB2RSTR_USART1RST 0x00000010U
5729 #define RCC_APB2RSTR_USART6RST 0x00000020U
5730 #define RCC_APB2RSTR_SDMMC2RST 0x00000080U
5731 #define RCC_APB2RSTR_ADCRST 0x00000100U
5732 #define RCC_APB2RSTR_SDMMC1RST 0x00000800U
5733 #define RCC_APB2RSTR_SPI1RST 0x00001000U
5734 #define RCC_APB2RSTR_SPI4RST 0x00002000U
5735 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
5736 #define RCC_APB2RSTR_TIM9RST 0x00010000U
5737 #define RCC_APB2RSTR_TIM10RST 0x00020000U
5738 #define RCC_APB2RSTR_TIM11RST 0x00040000U
5739 #define RCC_APB2RSTR_SPI5RST 0x00100000U
5740 #define RCC_APB2RSTR_SPI6RST 0x00200000U
5741 #define RCC_APB2RSTR_SAI1RST 0x00400000U
5742 #define RCC_APB2RSTR_SAI2RST 0x00800000U
5743 #define RCC_APB2RSTR_DFSDM1RST 0x20000000U
5744 #define RCC_APB2RSTR_MDIORST 0x40000000U
5745 
5746 /******************** Bit definition for RCC_AHB1ENR register ***************/
5747 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
5748 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
5749 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
5750 #define RCC_AHB1ENR_GPIODEN 0x00000008U
5751 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
5752 #define RCC_AHB1ENR_GPIOFEN 0x00000020U
5753 #define RCC_AHB1ENR_GPIOGEN 0x00000040U
5754 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
5755 #define RCC_AHB1ENR_GPIOIEN 0x00000100U
5756 #define RCC_AHB1ENR_GPIOJEN 0x00000200U
5757 #define RCC_AHB1ENR_GPIOKEN 0x00000400U
5758 #define RCC_AHB1ENR_CRCEN 0x00001000U
5759 #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
5760 #define RCC_AHB1ENR_DTCMRAMEN 0x00100000U
5761 #define RCC_AHB1ENR_DMA1EN 0x00200000U
5762 #define RCC_AHB1ENR_DMA2EN 0x00400000U
5763 #define RCC_AHB1ENR_DMA2DEN 0x00800000U
5764 #define RCC_AHB1ENR_ETHMACEN 0x02000000U
5765 #define RCC_AHB1ENR_ETHMACTXEN 0x04000000U
5766 #define RCC_AHB1ENR_ETHMACRXEN 0x08000000U
5767 #define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U
5768 #define RCC_AHB1ENR_OTGHSEN 0x20000000U
5769 #define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
5770 
5771 /******************** Bit definition for RCC_AHB2ENR register ***************/
5772 #define RCC_AHB2ENR_DCMIEN 0x00000001U
5773 #define RCC_AHB2ENR_RNGEN 0x00000040U
5774 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
5775 
5776 /******************** Bit definition for RCC_AHB3ENR register ***************/
5777 #define RCC_AHB3ENR_FMCEN 0x00000001U
5778 #define RCC_AHB3ENR_QSPIEN 0x00000002U
5779 
5780 /******************** Bit definition for RCC_APB1ENR register ***************/
5781 #define RCC_APB1ENR_TIM2EN 0x00000001U
5782 #define RCC_APB1ENR_TIM3EN 0x00000002U
5783 #define RCC_APB1ENR_TIM4EN 0x00000004U
5784 #define RCC_APB1ENR_TIM5EN 0x00000008U
5785 #define RCC_APB1ENR_TIM6EN 0x00000010U
5786 #define RCC_APB1ENR_TIM7EN 0x00000020U
5787 #define RCC_APB1ENR_TIM12EN 0x00000040U
5788 #define RCC_APB1ENR_TIM13EN 0x00000080U
5789 #define RCC_APB1ENR_TIM14EN 0x00000100U
5790 #define RCC_APB1ENR_LPTIM1EN 0x00000200U
5791 #define RCC_APB1ENR_RTCEN 0x00000400U
5792 #define RCC_APB1ENR_WWDGEN 0x00000800U
5793 #define RCC_APB1ENR_CAN3EN 0x00002000U
5794 #define RCC_APB1ENR_SPI2EN 0x00004000U
5795 #define RCC_APB1ENR_SPI3EN 0x00008000U
5796 #define RCC_APB1ENR_SPDIFRXEN 0x00010000U
5797 #define RCC_APB1ENR_USART2EN 0x00020000U
5798 #define RCC_APB1ENR_USART3EN 0x00040000U
5799 #define RCC_APB1ENR_UART4EN 0x00080000U
5800 #define RCC_APB1ENR_UART5EN 0x00100000U
5801 #define RCC_APB1ENR_I2C1EN 0x00200000U
5802 #define RCC_APB1ENR_I2C2EN 0x00400000U
5803 #define RCC_APB1ENR_I2C3EN 0x00800000U
5804 #define RCC_APB1ENR_I2C4EN 0x01000000U
5805 #define RCC_APB1ENR_CAN1EN 0x02000000U
5806 #define RCC_APB1ENR_CAN2EN 0x04000000U
5807 #define RCC_APB1ENR_CECEN 0x08000000U
5808 #define RCC_APB1ENR_PWREN 0x10000000U
5809 #define RCC_APB1ENR_DACEN 0x20000000U
5810 #define RCC_APB1ENR_UART7EN 0x40000000U
5811 #define RCC_APB1ENR_UART8EN 0x80000000U
5812 
5813 /******************** Bit definition for RCC_APB2ENR register ***************/
5814 #define RCC_APB2ENR_TIM1EN 0x00000001U
5815 #define RCC_APB2ENR_TIM8EN 0x00000002U
5816 #define RCC_APB2ENR_USART1EN 0x00000010U
5817 #define RCC_APB2ENR_USART6EN 0x00000020U
5818 #define RCC_APB2ENR_SDMMC2EN 0x00000080U
5819 #define RCC_APB2ENR_ADC1EN 0x00000100U
5820 #define RCC_APB2ENR_ADC2EN 0x00000200U
5821 #define RCC_APB2ENR_ADC3EN 0x00000400U
5822 #define RCC_APB2ENR_SDMMC1EN 0x00000800U
5823 #define RCC_APB2ENR_SPI1EN 0x00001000U
5824 #define RCC_APB2ENR_SPI4EN 0x00002000U
5825 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
5826 #define RCC_APB2ENR_TIM9EN 0x00010000U
5827 #define RCC_APB2ENR_TIM10EN 0x00020000U
5828 #define RCC_APB2ENR_TIM11EN 0x00040000U
5829 #define RCC_APB2ENR_SPI5EN 0x00100000U
5830 #define RCC_APB2ENR_SPI6EN 0x00200000U
5831 #define RCC_APB2ENR_SAI1EN 0x00400000U
5832 #define RCC_APB2ENR_SAI2EN 0x00800000U
5833 #define RCC_APB2ENR_DFSDM1EN 0x20000000U
5834 #define RCC_APB2ENR_MDIOEN 0x40000000U
5835 
5836 /******************** Bit definition for RCC_AHB1LPENR register *************/
5837 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
5838 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
5839 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
5840 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
5841 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
5842 #define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
5843 #define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
5844 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
5845 #define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
5846 #define RCC_AHB1LPENR_GPIOJLPEN 0x00000200U
5847 #define RCC_AHB1LPENR_GPIOKLPEN 0x00000400U
5848 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
5849 #define RCC_AHB1LPENR_AXILPEN 0x00002000U
5850 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
5851 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
5852 #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
5853 #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
5854 #define RCC_AHB1LPENR_DTCMLPEN 0x00100000U
5855 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
5856 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
5857 #define RCC_AHB1LPENR_DMA2DLPEN 0x00800000U
5858 #define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U
5859 #define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U
5860 #define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U
5861 #define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U
5862 #define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
5863 #define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
5864 
5865 /******************** Bit definition for RCC_AHB2LPENR register *************/
5866 #define RCC_AHB2LPENR_DCMILPEN 0x00000001U
5867 #define RCC_AHB2LPENR_RNGLPEN 0x00000040U
5868 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
5869 
5870 /******************** Bit definition for RCC_AHB3LPENR register *************/
5871 #define RCC_AHB3LPENR_FMCLPEN 0x00000001U
5872 #define RCC_AHB3LPENR_QSPILPEN 0x00000002U
5873 /******************** Bit definition for RCC_APB1LPENR register *************/
5874 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
5875 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
5876 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
5877 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
5878 #define RCC_APB1LPENR_TIM6LPEN 0x00000010U
5879 #define RCC_APB1LPENR_TIM7LPEN 0x00000020U
5880 #define RCC_APB1LPENR_TIM12LPEN 0x00000040U
5881 #define RCC_APB1LPENR_TIM13LPEN 0x00000080U
5882 #define RCC_APB1LPENR_TIM14LPEN 0x00000100U
5883 #define RCC_APB1LPENR_LPTIM1LPEN 0x00000200U
5884 #define RCC_APB1LPENR_RTCLPEN 0x00000400U
5885 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
5886 #define RCC_APB1LPENR_CAN3LPEN 0x00002000U
5887 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
5888 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
5889 #define RCC_APB1LPENR_SPDIFRXLPEN 0x00010000U
5890 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
5891 #define RCC_APB1LPENR_USART3LPEN 0x00040000U
5892 #define RCC_APB1LPENR_UART4LPEN 0x00080000U
5893 #define RCC_APB1LPENR_UART5LPEN 0x00100000U
5894 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
5895 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
5896 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
5897 #define RCC_APB1LPENR_I2C4LPEN 0x01000000U
5898 #define RCC_APB1LPENR_CAN1LPEN 0x02000000U
5899 #define RCC_APB1LPENR_CAN2LPEN 0x04000000U
5900 #define RCC_APB1LPENR_CECLPEN 0x08000000U
5901 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
5902 #define RCC_APB1LPENR_DACLPEN 0x20000000U
5903 #define RCC_APB1LPENR_UART7LPEN 0x40000000U
5904 #define RCC_APB1LPENR_UART8LPEN 0x80000000U
5905 
5906 /******************** Bit definition for RCC_APB2LPENR register *************/
5907 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
5908 #define RCC_APB2LPENR_TIM8LPEN 0x00000002U
5909 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
5910 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
5911 #define RCC_APB2LPENR_SDMMC2LPEN 0x00000080U
5912 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
5913 #define RCC_APB2LPENR_ADC2LPEN 0x00000200U
5914 #define RCC_APB2LPENR_ADC3LPEN 0x00000400U
5915 #define RCC_APB2LPENR_SDMMC1LPEN 0x00000800U
5916 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
5917 #define RCC_APB2LPENR_SPI4LPEN 0x00002000U
5918 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
5919 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
5920 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
5921 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
5922 #define RCC_APB2LPENR_SPI5LPEN 0x00100000U
5923 #define RCC_APB2LPENR_SPI6LPEN 0x00200000U
5924 #define RCC_APB2LPENR_SAI1LPEN 0x00400000U
5925 #define RCC_APB2LPENR_SAI2LPEN 0x00800000U
5926 #define RCC_APB2LPENR_DFSDM1LPEN 0x20000000U
5927 #define RCC_APB2LPENR_MDIOLPEN 0x40000000U
5928 
5929 /******************** Bit definition for RCC_BDCR register ******************/
5930 #define RCC_BDCR_LSEON 0x00000001U
5931 #define RCC_BDCR_LSERDY 0x00000002U
5932 #define RCC_BDCR_LSEBYP 0x00000004U
5933 #define RCC_BDCR_LSEDRV 0x00000018U
5934 #define RCC_BDCR_LSEDRV_0 0x00000008U
5935 #define RCC_BDCR_LSEDRV_1 0x00000010U
5936 #define RCC_BDCR_RTCSEL 0x00000300U
5937 #define RCC_BDCR_RTCSEL_0 0x00000100U
5938 #define RCC_BDCR_RTCSEL_1 0x00000200U
5939 #define RCC_BDCR_RTCEN 0x00008000U
5940 #define RCC_BDCR_BDRST 0x00010000U
5941 
5942 /******************** Bit definition for RCC_CSR register *******************/
5943 #define RCC_CSR_LSION 0x00000001U
5944 #define RCC_CSR_LSIRDY 0x00000002U
5945 #define RCC_CSR_RMVF 0x01000000U
5946 #define RCC_CSR_BORRSTF 0x02000000U
5947 #define RCC_CSR_PINRSTF 0x04000000U
5948 #define RCC_CSR_PORRSTF 0x08000000U
5949 #define RCC_CSR_SFTRSTF 0x10000000U
5950 #define RCC_CSR_IWDGRSTF 0x20000000U
5951 #define RCC_CSR_WWDGRSTF 0x40000000U
5952 #define RCC_CSR_LPWRRSTF 0x80000000U
5953 
5954 /******************** Bit definition for RCC_SSCGR register *****************/
5955 #define RCC_SSCGR_MODPER 0x00001FFFU
5956 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
5957 #define RCC_SSCGR_SPREADSEL 0x40000000U
5958 #define RCC_SSCGR_SSCGEN 0x80000000U
5959 
5960 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
5961 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
5962 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
5963 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
5964 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
5965 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
5966 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
5967 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
5968 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
5969 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
5970 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
5971 #define RCC_PLLI2SCFGR_PLLI2SP 0x00030000U
5972 #define RCC_PLLI2SCFGR_PLLI2SP_0 0x00010000U
5973 #define RCC_PLLI2SCFGR_PLLI2SP_1 0x00020000U
5974 #define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
5975 #define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
5976 #define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
5977 #define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
5978 #define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
5979 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
5980 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
5981 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
5982 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
5983 
5984 /******************** Bit definition for RCC_PLLSAICFGR register ************/
5985 #define RCC_PLLSAICFGR_PLLSAIN 0x00007FC0U
5986 #define RCC_PLLSAICFGR_PLLSAIN_0 0x00000040U
5987 #define RCC_PLLSAICFGR_PLLSAIN_1 0x00000080U
5988 #define RCC_PLLSAICFGR_PLLSAIN_2 0x00000100U
5989 #define RCC_PLLSAICFGR_PLLSAIN_3 0x00000200U
5990 #define RCC_PLLSAICFGR_PLLSAIN_4 0x00000400U
5991 #define RCC_PLLSAICFGR_PLLSAIN_5 0x00000800U
5992 #define RCC_PLLSAICFGR_PLLSAIN_6 0x00001000U
5993 #define RCC_PLLSAICFGR_PLLSAIN_7 0x00002000U
5994 #define RCC_PLLSAICFGR_PLLSAIN_8 0x00004000U
5995 #define RCC_PLLSAICFGR_PLLSAIP 0x00030000U
5996 #define RCC_PLLSAICFGR_PLLSAIP_0 0x00010000U
5997 #define RCC_PLLSAICFGR_PLLSAIP_1 0x00020000U
5998 #define RCC_PLLSAICFGR_PLLSAIQ 0x0F000000U
5999 #define RCC_PLLSAICFGR_PLLSAIQ_0 0x01000000U
6000 #define RCC_PLLSAICFGR_PLLSAIQ_1 0x02000000U
6001 #define RCC_PLLSAICFGR_PLLSAIQ_2 0x04000000U
6002 #define RCC_PLLSAICFGR_PLLSAIQ_3 0x08000000U
6003 #define RCC_PLLSAICFGR_PLLSAIR 0x70000000U
6004 #define RCC_PLLSAICFGR_PLLSAIR_0 0x10000000U
6005 #define RCC_PLLSAICFGR_PLLSAIR_1 0x20000000U
6006 #define RCC_PLLSAICFGR_PLLSAIR_2 0x40000000U
6007 
6008 /******************** Bit definition for RCC_DCKCFGR1 register ***************/
6009 #define RCC_DCKCFGR1_PLLI2SDIVQ 0x0000001FU
6010 #define RCC_DCKCFGR1_PLLI2SDIVQ_0 0x00000001U
6011 #define RCC_DCKCFGR1_PLLI2SDIVQ_1 0x00000002U
6012 #define RCC_DCKCFGR1_PLLI2SDIVQ_2 0x00000004U
6013 #define RCC_DCKCFGR1_PLLI2SDIVQ_3 0x00000008U
6014 #define RCC_DCKCFGR1_PLLI2SDIVQ_4 0x00000010U
6015 
6016 #define RCC_DCKCFGR1_PLLSAIDIVQ 0x00001F00U
6017 #define RCC_DCKCFGR1_PLLSAIDIVQ_0 0x00000100U
6018 #define RCC_DCKCFGR1_PLLSAIDIVQ_1 0x00000200U
6019 #define RCC_DCKCFGR1_PLLSAIDIVQ_2 0x00000400U
6020 #define RCC_DCKCFGR1_PLLSAIDIVQ_3 0x00000800U
6021 #define RCC_DCKCFGR1_PLLSAIDIVQ_4 0x00001000U
6022 
6023 #define RCC_DCKCFGR1_PLLSAIDIVR 0x00030000U
6024 #define RCC_DCKCFGR1_PLLSAIDIVR_0 0x00010000U
6025 #define RCC_DCKCFGR1_PLLSAIDIVR_1 0x00020000U
6026 
6027 #define RCC_DCKCFGR1_SAI1SEL 0x00300000U
6028 #define RCC_DCKCFGR1_SAI1SEL_0 0x00100000U
6029 #define RCC_DCKCFGR1_SAI1SEL_1 0x00200000U
6030 
6031 #define RCC_DCKCFGR1_SAI2SEL 0x00C00000U
6032 #define RCC_DCKCFGR1_SAI2SEL_0 0x00400000U
6033 #define RCC_DCKCFGR1_SAI2SEL_1 0x00800000U
6034 
6035 #define RCC_DCKCFGR1_TIMPRE 0x01000000U
6036 #define RCC_DCKCFGR1_DFSDM1SEL 0x02000000U
6037 #define RCC_DCKCFGR1_ADFSDM1SEL 0x04000000U
6038 
6039 /******************** Bit definition for RCC_DCKCFGR2 register ***************/
6040 #define RCC_DCKCFGR2_USART1SEL 0x00000003U
6041 #define RCC_DCKCFGR2_USART1SEL_0 0x00000001U
6042 #define RCC_DCKCFGR2_USART1SEL_1 0x00000002U
6043 #define RCC_DCKCFGR2_USART2SEL 0x0000000CU
6044 #define RCC_DCKCFGR2_USART2SEL_0 0x00000004U
6045 #define RCC_DCKCFGR2_USART2SEL_1 0x00000008U
6046 #define RCC_DCKCFGR2_USART3SEL 0x00000030U
6047 #define RCC_DCKCFGR2_USART3SEL_0 0x00000010U
6048 #define RCC_DCKCFGR2_USART3SEL_1 0x00000020U
6049 #define RCC_DCKCFGR2_UART4SEL 0x000000C0U
6050 #define RCC_DCKCFGR2_UART4SEL_0 0x00000040U
6051 #define RCC_DCKCFGR2_UART4SEL_1 0x00000080U
6052 #define RCC_DCKCFGR2_UART5SEL 0x00000300U
6053 #define RCC_DCKCFGR2_UART5SEL_0 0x00000100U
6054 #define RCC_DCKCFGR2_UART5SEL_1 0x00000200U
6055 #define RCC_DCKCFGR2_USART6SEL 0x00000C00U
6056 #define RCC_DCKCFGR2_USART6SEL_0 0x00000400U
6057 #define RCC_DCKCFGR2_USART6SEL_1 0x00000800U
6058 #define RCC_DCKCFGR2_UART7SEL 0x00003000U
6059 #define RCC_DCKCFGR2_UART7SEL_0 0x00001000U
6060 #define RCC_DCKCFGR2_UART7SEL_1 0x00002000U
6061 #define RCC_DCKCFGR2_UART8SEL 0x0000C000U
6062 #define RCC_DCKCFGR2_UART8SEL_0 0x00004000U
6063 #define RCC_DCKCFGR2_UART8SEL_1 0x00008000U
6064 #define RCC_DCKCFGR2_I2C1SEL 0x00030000U
6065 #define RCC_DCKCFGR2_I2C1SEL_0 0x00010000U
6066 #define RCC_DCKCFGR2_I2C1SEL_1 0x00020000U
6067 #define RCC_DCKCFGR2_I2C2SEL 0x000C0000U
6068 #define RCC_DCKCFGR2_I2C2SEL_0 0x00040000U
6069 #define RCC_DCKCFGR2_I2C2SEL_1 0x00080000U
6070 #define RCC_DCKCFGR2_I2C3SEL 0x00300000U
6071 #define RCC_DCKCFGR2_I2C3SEL_0 0x00100000U
6072 #define RCC_DCKCFGR2_I2C3SEL_1 0x00200000U
6073 #define RCC_DCKCFGR2_I2C4SEL 0x00C00000U
6074 #define RCC_DCKCFGR2_I2C4SEL_0 0x00400000U
6075 #define RCC_DCKCFGR2_I2C4SEL_1 0x00800000U
6076 #define RCC_DCKCFGR2_LPTIM1SEL 0x03000000U
6077 #define RCC_DCKCFGR2_LPTIM1SEL_0 0x01000000U
6078 #define RCC_DCKCFGR2_LPTIM1SEL_1 0x02000000U
6079 #define RCC_DCKCFGR2_CECSEL 0x04000000U
6080 #define RCC_DCKCFGR2_CK48MSEL 0x08000000U
6081 #define RCC_DCKCFGR2_SDMMC1SEL 0x10000000U
6082 #define RCC_DCKCFGR2_SDMMC2SEL 0x20000000U
6083 
6084 /******************************************************************************/
6085 /* */
6086 /* RNG */
6087 /* */
6088 /******************************************************************************/
6089 /******************** Bits definition for RNG_CR register *******************/
6090 #define RNG_CR_RNGEN 0x00000004U
6091 #define RNG_CR_IE 0x00000008U
6092 
6093 /******************** Bits definition for RNG_SR register *******************/
6094 #define RNG_SR_DRDY 0x00000001U
6095 #define RNG_SR_CECS 0x00000002U
6096 #define RNG_SR_SECS 0x00000004U
6097 #define RNG_SR_CEIS 0x00000020U
6098 #define RNG_SR_SEIS 0x00000040U
6099 
6100 /******************************************************************************/
6101 /* */
6102 /* Real-Time Clock (RTC) */
6103 /* */
6104 /******************************************************************************/
6105 /******************** Bits definition for RTC_TR register *******************/
6106 #define RTC_TR_PM 0x00400000U
6107 #define RTC_TR_HT 0x00300000U
6108 #define RTC_TR_HT_0 0x00100000U
6109 #define RTC_TR_HT_1 0x00200000U
6110 #define RTC_TR_HU 0x000F0000U
6111 #define RTC_TR_HU_0 0x00010000U
6112 #define RTC_TR_HU_1 0x00020000U
6113 #define RTC_TR_HU_2 0x00040000U
6114 #define RTC_TR_HU_3 0x00080000U
6115 #define RTC_TR_MNT 0x00007000U
6116 #define RTC_TR_MNT_0 0x00001000U
6117 #define RTC_TR_MNT_1 0x00002000U
6118 #define RTC_TR_MNT_2 0x00004000U
6119 #define RTC_TR_MNU 0x00000F00U
6120 #define RTC_TR_MNU_0 0x00000100U
6121 #define RTC_TR_MNU_1 0x00000200U
6122 #define RTC_TR_MNU_2 0x00000400U
6123 #define RTC_TR_MNU_3 0x00000800U
6124 #define RTC_TR_ST 0x00000070U
6125 #define RTC_TR_ST_0 0x00000010U
6126 #define RTC_TR_ST_1 0x00000020U
6127 #define RTC_TR_ST_2 0x00000040U
6128 #define RTC_TR_SU 0x0000000FU
6129 #define RTC_TR_SU_0 0x00000001U
6130 #define RTC_TR_SU_1 0x00000002U
6131 #define RTC_TR_SU_2 0x00000004U
6132 #define RTC_TR_SU_3 0x00000008U
6133 
6134 /******************** Bits definition for RTC_DR register *******************/
6135 #define RTC_DR_YT 0x00F00000U
6136 #define RTC_DR_YT_0 0x00100000U
6137 #define RTC_DR_YT_1 0x00200000U
6138 #define RTC_DR_YT_2 0x00400000U
6139 #define RTC_DR_YT_3 0x00800000U
6140 #define RTC_DR_YU 0x000F0000U
6141 #define RTC_DR_YU_0 0x00010000U
6142 #define RTC_DR_YU_1 0x00020000U
6143 #define RTC_DR_YU_2 0x00040000U
6144 #define RTC_DR_YU_3 0x00080000U
6145 #define RTC_DR_WDU 0x0000E000U
6146 #define RTC_DR_WDU_0 0x00002000U
6147 #define RTC_DR_WDU_1 0x00004000U
6148 #define RTC_DR_WDU_2 0x00008000U
6149 #define RTC_DR_MT 0x00001000U
6150 #define RTC_DR_MU 0x00000F00U
6151 #define RTC_DR_MU_0 0x00000100U
6152 #define RTC_DR_MU_1 0x00000200U
6153 #define RTC_DR_MU_2 0x00000400U
6154 #define RTC_DR_MU_3 0x00000800U
6155 #define RTC_DR_DT 0x00000030U
6156 #define RTC_DR_DT_0 0x00000010U
6157 #define RTC_DR_DT_1 0x00000020U
6158 #define RTC_DR_DU 0x0000000FU
6159 #define RTC_DR_DU_0 0x00000001U
6160 #define RTC_DR_DU_1 0x00000002U
6161 #define RTC_DR_DU_2 0x00000004U
6162 #define RTC_DR_DU_3 0x00000008U
6163 
6164 /******************** Bits definition for RTC_CR register *******************/
6165 #define RTC_CR_ITSE 0x01000000U
6166 #define RTC_CR_COE 0x00800000U
6167 #define RTC_CR_OSEL 0x00600000U
6168 #define RTC_CR_OSEL_0 0x00200000U
6169 #define RTC_CR_OSEL_1 0x00400000U
6170 #define RTC_CR_POL 0x00100000U
6171 #define RTC_CR_COSEL 0x00080000U
6172 #define RTC_CR_BCK 0x00040000U
6173 #define RTC_CR_SUB1H 0x00020000U
6174 #define RTC_CR_ADD1H 0x00010000U
6175 #define RTC_CR_TSIE 0x00008000U
6176 #define RTC_CR_WUTIE 0x00004000U
6177 #define RTC_CR_ALRBIE 0x00002000U
6178 #define RTC_CR_ALRAIE 0x00001000U
6179 #define RTC_CR_TSE 0x00000800U
6180 #define RTC_CR_WUTE 0x00000400U
6181 #define RTC_CR_ALRBE 0x00000200U
6182 #define RTC_CR_ALRAE 0x00000100U
6183 #define RTC_CR_FMT 0x00000040U
6184 #define RTC_CR_BYPSHAD 0x00000020U
6185 #define RTC_CR_REFCKON 0x00000010U
6186 #define RTC_CR_TSEDGE 0x00000008U
6187 #define RTC_CR_WUCKSEL 0x00000007U
6188 #define RTC_CR_WUCKSEL_0 0x00000001U
6189 #define RTC_CR_WUCKSEL_1 0x00000002U
6190 #define RTC_CR_WUCKSEL_2 0x00000004U
6191 
6192 /******************** Bits definition for RTC_ISR register ******************/
6193 #define RTC_ISR_ITSF 0x00020000U
6194 #define RTC_ISR_RECALPF 0x00010000U
6195 #define RTC_ISR_TAMP3F 0x00008000U
6196 #define RTC_ISR_TAMP2F 0x00004000U
6197 #define RTC_ISR_TAMP1F 0x00002000U
6198 #define RTC_ISR_TSOVF 0x00001000U
6199 #define RTC_ISR_TSF 0x00000800U
6200 #define RTC_ISR_WUTF 0x00000400U
6201 #define RTC_ISR_ALRBF 0x00000200U
6202 #define RTC_ISR_ALRAF 0x00000100U
6203 #define RTC_ISR_INIT 0x00000080U
6204 #define RTC_ISR_INITF 0x00000040U
6205 #define RTC_ISR_RSF 0x00000020U
6206 #define RTC_ISR_INITS 0x00000010U
6207 #define RTC_ISR_SHPF 0x00000008U
6208 #define RTC_ISR_WUTWF 0x00000004U
6209 #define RTC_ISR_ALRBWF 0x00000002U
6210 #define RTC_ISR_ALRAWF 0x00000001U
6211 
6212 /******************** Bits definition for RTC_PRER register *****************/
6213 #define RTC_PRER_PREDIV_A 0x007F0000U
6214 #define RTC_PRER_PREDIV_S 0x00007FFFU
6215 
6216 /******************** Bits definition for RTC_WUTR register *****************/
6217 #define RTC_WUTR_WUT 0x0000FFFFU
6218 
6219 /******************** Bits definition for RTC_ALRMAR register ***************/
6220 #define RTC_ALRMAR_MSK4 0x80000000U
6221 #define RTC_ALRMAR_WDSEL 0x40000000U
6222 #define RTC_ALRMAR_DT 0x30000000U
6223 #define RTC_ALRMAR_DT_0 0x10000000U
6224 #define RTC_ALRMAR_DT_1 0x20000000U
6225 #define RTC_ALRMAR_DU 0x0F000000U
6226 #define RTC_ALRMAR_DU_0 0x01000000U
6227 #define RTC_ALRMAR_DU_1 0x02000000U
6228 #define RTC_ALRMAR_DU_2 0x04000000U
6229 #define RTC_ALRMAR_DU_3 0x08000000U
6230 #define RTC_ALRMAR_MSK3 0x00800000U
6231 #define RTC_ALRMAR_PM 0x00400000U
6232 #define RTC_ALRMAR_HT 0x00300000U
6233 #define RTC_ALRMAR_HT_0 0x00100000U
6234 #define RTC_ALRMAR_HT_1 0x00200000U
6235 #define RTC_ALRMAR_HU 0x000F0000U
6236 #define RTC_ALRMAR_HU_0 0x00010000U
6237 #define RTC_ALRMAR_HU_1 0x00020000U
6238 #define RTC_ALRMAR_HU_2 0x00040000U
6239 #define RTC_ALRMAR_HU_3 0x00080000U
6240 #define RTC_ALRMAR_MSK2 0x00008000U
6241 #define RTC_ALRMAR_MNT 0x00007000U
6242 #define RTC_ALRMAR_MNT_0 0x00001000U
6243 #define RTC_ALRMAR_MNT_1 0x00002000U
6244 #define RTC_ALRMAR_MNT_2 0x00004000U
6245 #define RTC_ALRMAR_MNU 0x00000F00U
6246 #define RTC_ALRMAR_MNU_0 0x00000100U
6247 #define RTC_ALRMAR_MNU_1 0x00000200U
6248 #define RTC_ALRMAR_MNU_2 0x00000400U
6249 #define RTC_ALRMAR_MNU_3 0x00000800U
6250 #define RTC_ALRMAR_MSK1 0x00000080U
6251 #define RTC_ALRMAR_ST 0x00000070U
6252 #define RTC_ALRMAR_ST_0 0x00000010U
6253 #define RTC_ALRMAR_ST_1 0x00000020U
6254 #define RTC_ALRMAR_ST_2 0x00000040U
6255 #define RTC_ALRMAR_SU 0x0000000FU
6256 #define RTC_ALRMAR_SU_0 0x00000001U
6257 #define RTC_ALRMAR_SU_1 0x00000002U
6258 #define RTC_ALRMAR_SU_2 0x00000004U
6259 #define RTC_ALRMAR_SU_3 0x00000008U
6260 
6261 /******************** Bits definition for RTC_ALRMBR register ***************/
6262 #define RTC_ALRMBR_MSK4 0x80000000U
6263 #define RTC_ALRMBR_WDSEL 0x40000000U
6264 #define RTC_ALRMBR_DT 0x30000000U
6265 #define RTC_ALRMBR_DT_0 0x10000000U
6266 #define RTC_ALRMBR_DT_1 0x20000000U
6267 #define RTC_ALRMBR_DU 0x0F000000U
6268 #define RTC_ALRMBR_DU_0 0x01000000U
6269 #define RTC_ALRMBR_DU_1 0x02000000U
6270 #define RTC_ALRMBR_DU_2 0x04000000U
6271 #define RTC_ALRMBR_DU_3 0x08000000U
6272 #define RTC_ALRMBR_MSK3 0x00800000U
6273 #define RTC_ALRMBR_PM 0x00400000U
6274 #define RTC_ALRMBR_HT 0x00300000U
6275 #define RTC_ALRMBR_HT_0 0x00100000U
6276 #define RTC_ALRMBR_HT_1 0x00200000U
6277 #define RTC_ALRMBR_HU 0x000F0000U
6278 #define RTC_ALRMBR_HU_0 0x00010000U
6279 #define RTC_ALRMBR_HU_1 0x00020000U
6280 #define RTC_ALRMBR_HU_2 0x00040000U
6281 #define RTC_ALRMBR_HU_3 0x00080000U
6282 #define RTC_ALRMBR_MSK2 0x00008000U
6283 #define RTC_ALRMBR_MNT 0x00007000U
6284 #define RTC_ALRMBR_MNT_0 0x00001000U
6285 #define RTC_ALRMBR_MNT_1 0x00002000U
6286 #define RTC_ALRMBR_MNT_2 0x00004000U
6287 #define RTC_ALRMBR_MNU 0x00000F00U
6288 #define RTC_ALRMBR_MNU_0 0x00000100U
6289 #define RTC_ALRMBR_MNU_1 0x00000200U
6290 #define RTC_ALRMBR_MNU_2 0x00000400U
6291 #define RTC_ALRMBR_MNU_3 0x00000800U
6292 #define RTC_ALRMBR_MSK1 0x00000080U
6293 #define RTC_ALRMBR_ST 0x00000070U
6294 #define RTC_ALRMBR_ST_0 0x00000010U
6295 #define RTC_ALRMBR_ST_1 0x00000020U
6296 #define RTC_ALRMBR_ST_2 0x00000040U
6297 #define RTC_ALRMBR_SU 0x0000000FU
6298 #define RTC_ALRMBR_SU_0 0x00000001U
6299 #define RTC_ALRMBR_SU_1 0x00000002U
6300 #define RTC_ALRMBR_SU_2 0x00000004U
6301 #define RTC_ALRMBR_SU_3 0x00000008U
6302 
6303 /******************** Bits definition for RTC_WPR register ******************/
6304 #define RTC_WPR_KEY 0x000000FFU
6305 
6306 /******************** Bits definition for RTC_SSR register ******************/
6307 #define RTC_SSR_SS 0x0000FFFFU
6308 
6309 /******************** Bits definition for RTC_SHIFTR register ***************/
6310 #define RTC_SHIFTR_SUBFS 0x00007FFFU
6311 #define RTC_SHIFTR_ADD1S 0x80000000U
6312 
6313 /******************** Bits definition for RTC_TSTR register *****************/
6314 #define RTC_TSTR_PM 0x00400000U
6315 #define RTC_TSTR_HT 0x00300000U
6316 #define RTC_TSTR_HT_0 0x00100000U
6317 #define RTC_TSTR_HT_1 0x00200000U
6318 #define RTC_TSTR_HU 0x000F0000U
6319 #define RTC_TSTR_HU_0 0x00010000U
6320 #define RTC_TSTR_HU_1 0x00020000U
6321 #define RTC_TSTR_HU_2 0x00040000U
6322 #define RTC_TSTR_HU_3 0x00080000U
6323 #define RTC_TSTR_MNT 0x00007000U
6324 #define RTC_TSTR_MNT_0 0x00001000U
6325 #define RTC_TSTR_MNT_1 0x00002000U
6326 #define RTC_TSTR_MNT_2 0x00004000U
6327 #define RTC_TSTR_MNU 0x00000F00U
6328 #define RTC_TSTR_MNU_0 0x00000100U
6329 #define RTC_TSTR_MNU_1 0x00000200U
6330 #define RTC_TSTR_MNU_2 0x00000400U
6331 #define RTC_TSTR_MNU_3 0x00000800U
6332 #define RTC_TSTR_ST 0x00000070U
6333 #define RTC_TSTR_ST_0 0x00000010U
6334 #define RTC_TSTR_ST_1 0x00000020U
6335 #define RTC_TSTR_ST_2 0x00000040U
6336 #define RTC_TSTR_SU 0x0000000FU
6337 #define RTC_TSTR_SU_0 0x00000001U
6338 #define RTC_TSTR_SU_1 0x00000002U
6339 #define RTC_TSTR_SU_2 0x00000004U
6340 #define RTC_TSTR_SU_3 0x00000008U
6341 
6342 /******************** Bits definition for RTC_TSDR register *****************/
6343 #define RTC_TSDR_WDU 0x0000E000U
6344 #define RTC_TSDR_WDU_0 0x00002000U
6345 #define RTC_TSDR_WDU_1 0x00004000U
6346 #define RTC_TSDR_WDU_2 0x00008000U
6347 #define RTC_TSDR_MT 0x00001000U
6348 #define RTC_TSDR_MU 0x00000F00U
6349 #define RTC_TSDR_MU_0 0x00000100U
6350 #define RTC_TSDR_MU_1 0x00000200U
6351 #define RTC_TSDR_MU_2 0x00000400U
6352 #define RTC_TSDR_MU_3 0x00000800U
6353 #define RTC_TSDR_DT 0x00000030U
6354 #define RTC_TSDR_DT_0 0x00000010U
6355 #define RTC_TSDR_DT_1 0x00000020U
6356 #define RTC_TSDR_DU 0x0000000FU
6357 #define RTC_TSDR_DU_0 0x00000001U
6358 #define RTC_TSDR_DU_1 0x00000002U
6359 #define RTC_TSDR_DU_2 0x00000004U
6360 #define RTC_TSDR_DU_3 0x00000008U
6361 
6362 /******************** Bits definition for RTC_TSSSR register ****************/
6363 #define RTC_TSSSR_SS 0x0000FFFFU
6364 
6365 /******************** Bits definition for RTC_CAL register *****************/
6366 #define RTC_CALR_CALP 0x00008000U
6367 #define RTC_CALR_CALW8 0x00004000U
6368 #define RTC_CALR_CALW16 0x00002000U
6369 #define RTC_CALR_CALM 0x000001FFU
6370 #define RTC_CALR_CALM_0 0x00000001U
6371 #define RTC_CALR_CALM_1 0x00000002U
6372 #define RTC_CALR_CALM_2 0x00000004U
6373 #define RTC_CALR_CALM_3 0x00000008U
6374 #define RTC_CALR_CALM_4 0x00000010U
6375 #define RTC_CALR_CALM_5 0x00000020U
6376 #define RTC_CALR_CALM_6 0x00000040U
6377 #define RTC_CALR_CALM_7 0x00000080U
6378 #define RTC_CALR_CALM_8 0x00000100U
6379 
6380 /******************** Bits definition for RTC_TAMPCR register ****************/
6381 #define RTC_TAMPCR_TAMP3MF 0x01000000U
6382 #define RTC_TAMPCR_TAMP3NOERASE 0x00800000U
6383 #define RTC_TAMPCR_TAMP3IE 0x00400000U
6384 #define RTC_TAMPCR_TAMP2MF 0x00200000U
6385 #define RTC_TAMPCR_TAMP2NOERASE 0x00100000U
6386 #define RTC_TAMPCR_TAMP2IE 0x00080000U
6387 #define RTC_TAMPCR_TAMP1MF 0x00040000U
6388 #define RTC_TAMPCR_TAMP1NOERASE 0x00020000U
6389 #define RTC_TAMPCR_TAMP1IE 0x00010000U
6390 #define RTC_TAMPCR_TAMPPUDIS 0x00008000U
6391 #define RTC_TAMPCR_TAMPPRCH 0x00006000U
6392 #define RTC_TAMPCR_TAMPPRCH_0 0x00002000U
6393 #define RTC_TAMPCR_TAMPPRCH_1 0x00004000U
6394 #define RTC_TAMPCR_TAMPFLT 0x00001800U
6395 #define RTC_TAMPCR_TAMPFLT_0 0x00000800U
6396 #define RTC_TAMPCR_TAMPFLT_1 0x00001000U
6397 #define RTC_TAMPCR_TAMPFREQ 0x00000700U
6398 #define RTC_TAMPCR_TAMPFREQ_0 0x00000100U
6399 #define RTC_TAMPCR_TAMPFREQ_1 0x00000200U
6400 #define RTC_TAMPCR_TAMPFREQ_2 0x00000400U
6401 #define RTC_TAMPCR_TAMPTS 0x00000080U
6402 #define RTC_TAMPCR_TAMP3TRG 0x00000040U
6403 #define RTC_TAMPCR_TAMP3E 0x00000020U
6404 #define RTC_TAMPCR_TAMP2TRG 0x00000010U
6405 #define RTC_TAMPCR_TAMP2E 0x00000008U
6406 #define RTC_TAMPCR_TAMPIE 0x00000004U
6407 #define RTC_TAMPCR_TAMP1TRG 0x00000002U
6408 #define RTC_TAMPCR_TAMP1E 0x00000001U
6409 
6410 
6411 /******************** Bits definition for RTC_ALRMASSR register *************/
6412 #define RTC_ALRMASSR_MASKSS 0x0F000000U
6413 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
6414 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
6415 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
6416 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
6417 #define RTC_ALRMASSR_SS 0x00007FFFU
6418 
6419 /******************** Bits definition for RTC_ALRMBSSR register *************/
6420 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
6421 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
6422 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
6423 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
6424 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
6425 #define RTC_ALRMBSSR_SS 0x00007FFFU
6426 
6427 /******************** Bits definition for RTC_OR register ****************/
6428 #define RTC_OR_TSINSEL 0x00000006U
6429 #define RTC_OR_TSINSEL_0 0x00000002U
6430 #define RTC_OR_TSINSEL_1 0x00000004U
6431 #define RTC_OR_ALARMTYPE 0x00000008U
6432 
6433 /******************** Bits definition for RTC_BKP0R register ****************/
6434 #define RTC_BKP0R 0xFFFFFFFFU
6435 
6436 /******************** Bits definition for RTC_BKP1R register ****************/
6437 #define RTC_BKP1R 0xFFFFFFFFU
6438 
6439 /******************** Bits definition for RTC_BKP2R register ****************/
6440 #define RTC_BKP2R 0xFFFFFFFFU
6441 
6442 /******************** Bits definition for RTC_BKP3R register ****************/
6443 #define RTC_BKP3R 0xFFFFFFFFU
6444 
6445 /******************** Bits definition for RTC_BKP4R register ****************/
6446 #define RTC_BKP4R 0xFFFFFFFFU
6447 
6448 /******************** Bits definition for RTC_BKP5R register ****************/
6449 #define RTC_BKP5R 0xFFFFFFFFU
6450 
6451 /******************** Bits definition for RTC_BKP6R register ****************/
6452 #define RTC_BKP6R 0xFFFFFFFFU
6453 
6454 /******************** Bits definition for RTC_BKP7R register ****************/
6455 #define RTC_BKP7R 0xFFFFFFFFU
6456 
6457 /******************** Bits definition for RTC_BKP8R register ****************/
6458 #define RTC_BKP8R 0xFFFFFFFFU
6459 
6460 /******************** Bits definition for RTC_BKP9R register ****************/
6461 #define RTC_BKP9R 0xFFFFFFFFU
6462 
6463 /******************** Bits definition for RTC_BKP10R register ***************/
6464 #define RTC_BKP10R 0xFFFFFFFFU
6465 
6466 /******************** Bits definition for RTC_BKP11R register ***************/
6467 #define RTC_BKP11R 0xFFFFFFFFU
6468 
6469 /******************** Bits definition for RTC_BKP12R register ***************/
6470 #define RTC_BKP12R 0xFFFFFFFFU
6471 
6472 /******************** Bits definition for RTC_BKP13R register ***************/
6473 #define RTC_BKP13R 0xFFFFFFFFU
6474 
6475 /******************** Bits definition for RTC_BKP14R register ***************/
6476 #define RTC_BKP14R 0xFFFFFFFFU
6477 
6478 /******************** Bits definition for RTC_BKP15R register ***************/
6479 #define RTC_BKP15R 0xFFFFFFFFU
6480 
6481 /******************** Bits definition for RTC_BKP16R register ***************/
6482 #define RTC_BKP16R 0xFFFFFFFFU
6483 
6484 /******************** Bits definition for RTC_BKP17R register ***************/
6485 #define RTC_BKP17R 0xFFFFFFFFU
6486 
6487 /******************** Bits definition for RTC_BKP18R register ***************/
6488 #define RTC_BKP18R 0xFFFFFFFFU
6489 
6490 /******************** Bits definition for RTC_BKP19R register ***************/
6491 #define RTC_BKP19R 0xFFFFFFFFU
6492 
6493 /******************** Bits definition for RTC_BKP20R register ***************/
6494 #define RTC_BKP20R 0xFFFFFFFFU
6495 
6496 /******************** Bits definition for RTC_BKP21R register ***************/
6497 #define RTC_BKP21R 0xFFFFFFFFU
6498 
6499 /******************** Bits definition for RTC_BKP22R register ***************/
6500 #define RTC_BKP22R 0xFFFFFFFFU
6501 
6502 /******************** Bits definition for RTC_BKP23R register ***************/
6503 #define RTC_BKP23R 0xFFFFFFFFU
6504 
6505 /******************** Bits definition for RTC_BKP24R register ***************/
6506 #define RTC_BKP24R 0xFFFFFFFFU
6507 
6508 /******************** Bits definition for RTC_BKP25R register ***************/
6509 #define RTC_BKP25R 0xFFFFFFFFU
6510 
6511 /******************** Bits definition for RTC_BKP26R register ***************/
6512 #define RTC_BKP26R 0xFFFFFFFFU
6513 
6514 /******************** Bits definition for RTC_BKP27R register ***************/
6515 #define RTC_BKP27R 0xFFFFFFFFU
6516 
6517 /******************** Bits definition for RTC_BKP28R register ***************/
6518 #define RTC_BKP28R 0xFFFFFFFFU
6519 
6520 /******************** Bits definition for RTC_BKP29R register ***************/
6521 #define RTC_BKP29R 0xFFFFFFFFU
6522 
6523 /******************** Bits definition for RTC_BKP30R register ***************/
6524 #define RTC_BKP30R 0xFFFFFFFFU
6525 
6526 /******************** Bits definition for RTC_BKP31R register ***************/
6527 #define RTC_BKP31R 0xFFFFFFFFU
6528 
6529 /******************** Number of backup registers ******************************/
6530 #define RTC_BKP_NUMBER 0x00000020U
6531 
6532 
6533 /******************************************************************************/
6534 /* */
6535 /* Serial Audio Interface */
6536 /* */
6537 /******************************************************************************/
6538 /******************** Bit definition for SAI_GCR register *******************/
6539 #define SAI_GCR_SYNCIN 0x00000003U
6540 #define SAI_GCR_SYNCIN_0 0x00000001U
6541 #define SAI_GCR_SYNCIN_1 0x00000002U
6543 #define SAI_GCR_SYNCOUT 0x00000030U
6544 #define SAI_GCR_SYNCOUT_0 0x00000010U
6545 #define SAI_GCR_SYNCOUT_1 0x00000020U
6547 /******************* Bit definition for SAI_xCR1 register *******************/
6548 #define SAI_xCR1_MODE 0x00000003U
6549 #define SAI_xCR1_MODE_0 0x00000001U
6550 #define SAI_xCR1_MODE_1 0x00000002U
6552 #define SAI_xCR1_PRTCFG 0x0000000CU
6553 #define SAI_xCR1_PRTCFG_0 0x00000004U
6554 #define SAI_xCR1_PRTCFG_1 0x00000008U
6556 #define SAI_xCR1_DS 0x000000E0U
6557 #define SAI_xCR1_DS_0 0x00000020U
6558 #define SAI_xCR1_DS_1 0x00000040U
6559 #define SAI_xCR1_DS_2 0x00000080U
6561 #define SAI_xCR1_LSBFIRST 0x00000100U
6562 #define SAI_xCR1_CKSTR 0x00000200U
6564 #define SAI_xCR1_SYNCEN 0x00000C00U
6565 #define SAI_xCR1_SYNCEN_0 0x00000400U
6566 #define SAI_xCR1_SYNCEN_1 0x00000800U
6568 #define SAI_xCR1_MONO 0x00001000U
6569 #define SAI_xCR1_OUTDRIV 0x00002000U
6570 #define SAI_xCR1_SAIEN 0x00010000U
6571 #define SAI_xCR1_DMAEN 0x00020000U
6572 #define SAI_xCR1_NODIV 0x00080000U
6574 #define SAI_xCR1_MCKDIV 0x00F00000U
6575 #define SAI_xCR1_MCKDIV_0 0x00100000U
6576 #define SAI_xCR1_MCKDIV_1 0x00200000U
6577 #define SAI_xCR1_MCKDIV_2 0x00400000U
6578 #define SAI_xCR1_MCKDIV_3 0x00800000U
6580 /******************* Bit definition for SAI_xCR2 register *******************/
6581 #define SAI_xCR2_FTH 0x00000007U
6582 #define SAI_xCR2_FTH_0 0x00000001U
6583 #define SAI_xCR2_FTH_1 0x00000002U
6584 #define SAI_xCR2_FTH_2 0x00000004U
6586 #define SAI_xCR2_FFLUSH 0x00000008U
6587 #define SAI_xCR2_TRIS 0x00000010U
6588 #define SAI_xCR2_MUTE 0x00000020U
6589 #define SAI_xCR2_MUTEVAL 0x00000040U
6591 #define SAI_xCR2_MUTECNT 0x00001F80U
6592 #define SAI_xCR2_MUTECNT_0 0x00000080U
6593 #define SAI_xCR2_MUTECNT_1 0x00000100U
6594 #define SAI_xCR2_MUTECNT_2 0x00000200U
6595 #define SAI_xCR2_MUTECNT_3 0x00000400U
6596 #define SAI_xCR2_MUTECNT_4 0x00000800U
6597 #define SAI_xCR2_MUTECNT_5 0x00001000U
6599 #define SAI_xCR2_CPL 0x00002000U
6601 #define SAI_xCR2_COMP 0x0000C000U
6602 #define SAI_xCR2_COMP_0 0x00004000U
6603 #define SAI_xCR2_COMP_1 0x00008000U
6605 /****************** Bit definition for SAI_xFRCR register *******************/
6606 #define SAI_xFRCR_FRL 0x000000FFU
6607 #define SAI_xFRCR_FRL_0 0x00000001U
6608 #define SAI_xFRCR_FRL_1 0x00000002U
6609 #define SAI_xFRCR_FRL_2 0x00000004U
6610 #define SAI_xFRCR_FRL_3 0x00000008U
6611 #define SAI_xFRCR_FRL_4 0x00000010U
6612 #define SAI_xFRCR_FRL_5 0x00000020U
6613 #define SAI_xFRCR_FRL_6 0x00000040U
6614 #define SAI_xFRCR_FRL_7 0x00000080U
6616 #define SAI_xFRCR_FSALL 0x00007F00U
6617 #define SAI_xFRCR_FSALL_0 0x00000100U
6618 #define SAI_xFRCR_FSALL_1 0x00000200U
6619 #define SAI_xFRCR_FSALL_2 0x00000400U
6620 #define SAI_xFRCR_FSALL_3 0x00000800U
6621 #define SAI_xFRCR_FSALL_4 0x00001000U
6622 #define SAI_xFRCR_FSALL_5 0x00002000U
6623 #define SAI_xFRCR_FSALL_6 0x00004000U
6625 #define SAI_xFRCR_FSDEF 0x00010000U
6626 #define SAI_xFRCR_FSPOL 0x00020000U
6627 #define SAI_xFRCR_FSOFF 0x00040000U
6629 /* Legacy define */
6630 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
6631 
6632 /****************** Bit definition for SAI_xSLOTR register *******************/
6633 #define SAI_xSLOTR_FBOFF 0x0000001FU
6634 #define SAI_xSLOTR_FBOFF_0 0x00000001U
6635 #define SAI_xSLOTR_FBOFF_1 0x00000002U
6636 #define SAI_xSLOTR_FBOFF_2 0x00000004U
6637 #define SAI_xSLOTR_FBOFF_3 0x00000008U
6638 #define SAI_xSLOTR_FBOFF_4 0x00000010U
6640 #define SAI_xSLOTR_SLOTSZ 0x000000C0U
6641 #define SAI_xSLOTR_SLOTSZ_0 0x00000040U
6642 #define SAI_xSLOTR_SLOTSZ_1 0x00000080U
6644 #define SAI_xSLOTR_NBSLOT 0x00000F00U
6645 #define SAI_xSLOTR_NBSLOT_0 0x00000100U
6646 #define SAI_xSLOTR_NBSLOT_1 0x00000200U
6647 #define SAI_xSLOTR_NBSLOT_2 0x00000400U
6648 #define SAI_xSLOTR_NBSLOT_3 0x00000800U
6650 #define SAI_xSLOTR_SLOTEN 0xFFFF0000U
6652 /******************* Bit definition for SAI_xIMR register *******************/
6653 #define SAI_xIMR_OVRUDRIE 0x00000001U
6654 #define SAI_xIMR_MUTEDETIE 0x00000002U
6655 #define SAI_xIMR_WCKCFGIE 0x00000004U
6656 #define SAI_xIMR_FREQIE 0x00000008U
6657 #define SAI_xIMR_CNRDYIE 0x00000010U
6658 #define SAI_xIMR_AFSDETIE 0x00000020U
6659 #define SAI_xIMR_LFSDETIE 0x00000040U
6661 /******************** Bit definition for SAI_xSR register *******************/
6662 #define SAI_xSR_OVRUDR 0x00000001U
6663 #define SAI_xSR_MUTEDET 0x00000002U
6664 #define SAI_xSR_WCKCFG 0x00000004U
6665 #define SAI_xSR_FREQ 0x00000008U
6666 #define SAI_xSR_CNRDY 0x00000010U
6667 #define SAI_xSR_AFSDET 0x00000020U
6668 #define SAI_xSR_LFSDET 0x00000040U
6670 #define SAI_xSR_FLVL 0x00070000U
6671 #define SAI_xSR_FLVL_0 0x00010000U
6672 #define SAI_xSR_FLVL_1 0x00020000U
6673 #define SAI_xSR_FLVL_2 0x00040000U
6675 /****************** Bit definition for SAI_xCLRFR register ******************/
6676 #define SAI_xCLRFR_COVRUDR 0x00000001U
6677 #define SAI_xCLRFR_CMUTEDET 0x00000002U
6678 #define SAI_xCLRFR_CWCKCFG 0x00000004U
6679 #define SAI_xCLRFR_CFREQ 0x00000008U
6680 #define SAI_xCLRFR_CCNRDY 0x00000010U
6681 #define SAI_xCLRFR_CAFSDET 0x00000020U
6682 #define SAI_xCLRFR_CLFSDET 0x00000040U
6684 /****************** Bit definition for SAI_xDR register *********************/
6685 #define SAI_xDR_DATA 0xFFFFFFFFU
6686 
6687 /******************************************************************************/
6688 /* */
6689 /* SPDIF-RX Interface */
6690 /* */
6691 /******************************************************************************/
6692 /******************** Bit definition for SPDIF_CR register *******************/
6693 #define SPDIFRX_CR_SPDIFEN 0x00000003U
6694 #define SPDIFRX_CR_RXDMAEN 0x00000004U
6695 #define SPDIFRX_CR_RXSTEO 0x00000008U
6696 #define SPDIFRX_CR_DRFMT 0x00000030U
6697 #define SPDIFRX_CR_PMSK 0x00000040U
6698 #define SPDIFRX_CR_VMSK 0x00000080U
6699 #define SPDIFRX_CR_CUMSK 0x00000100U
6700 #define SPDIFRX_CR_PTMSK 0x00000200U
6701 #define SPDIFRX_CR_CBDMAEN 0x00000400U
6702 #define SPDIFRX_CR_CHSEL 0x00000800U
6703 #define SPDIFRX_CR_NBTR 0x00003000U
6704 #define SPDIFRX_CR_WFA 0x00004000U
6705 #define SPDIFRX_CR_INSEL 0x00070000U
6707 /******************* Bit definition for SPDIFRX_IMR register *******************/
6708 #define SPDIFRX_IMR_RXNEIE 0x00000001U
6709 #define SPDIFRX_IMR_CSRNEIE 0x00000002U
6710 #define SPDIFRX_IMR_PERRIE 0x00000004U
6711 #define SPDIFRX_IMR_OVRIE 0x00000008U
6712 #define SPDIFRX_IMR_SBLKIE 0x00000010U
6713 #define SPDIFRX_IMR_SYNCDIE 0x00000020U
6714 #define SPDIFRX_IMR_IFEIE 0x00000040U
6716 /******************* Bit definition for SPDIFRX_SR register *******************/
6717 #define SPDIFRX_SR_RXNE 0x00000001U
6718 #define SPDIFRX_SR_CSRNE 0x00000002U
6719 #define SPDIFRX_SR_PERR 0x00000004U
6720 #define SPDIFRX_SR_OVR 0x00000008U
6721 #define SPDIFRX_SR_SBD 0x00000010U
6722 #define SPDIFRX_SR_SYNCD 0x00000020U
6723 #define SPDIFRX_SR_FERR 0x00000040U
6724 #define SPDIFRX_SR_SERR 0x00000080U
6725 #define SPDIFRX_SR_TERR 0x00000100U
6726 #define SPDIFRX_SR_WIDTH5 0x7FFF0000U
6728 /******************* Bit definition for SPDIFRX_IFCR register *******************/
6729 #define SPDIFRX_IFCR_PERRCF 0x00000004U
6730 #define SPDIFRX_IFCR_OVRCF 0x00000008U
6731 #define SPDIFRX_IFCR_SBDCF 0x00000010U
6732 #define SPDIFRX_IFCR_SYNCDCF 0x00000020U
6734 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
6735 #define SPDIFRX_DR0_DR 0x00FFFFFFU
6736 #define SPDIFRX_DR0_PE 0x01000000U
6737 #define SPDIFRX_DR0_V 0x02000000U
6738 #define SPDIFRX_DR0_U 0x04000000U
6739 #define SPDIFRX_DR0_C 0x08000000U
6740 #define SPDIFRX_DR0_PT 0x30000000U
6742 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
6743 #define SPDIFRX_DR1_DR 0xFFFFFF00U
6744 #define SPDIFRX_DR1_PT 0x00000030U
6745 #define SPDIFRX_DR1_C 0x00000008U
6746 #define SPDIFRX_DR1_U 0x00000004U
6747 #define SPDIFRX_DR1_V 0x00000002U
6748 #define SPDIFRX_DR1_PE 0x00000001U
6750 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
6751 #define SPDIFRX_DR1_DRNL1 0xFFFF0000U
6752 #define SPDIFRX_DR1_DRNL2 0x0000FFFFU
6754 /******************* Bit definition for SPDIFRX_CSR register *******************/
6755 #define SPDIFRX_CSR_USR 0x0000FFFFU
6756 #define SPDIFRX_CSR_CS 0x00FF0000U
6757 #define SPDIFRX_CSR_SOB 0x01000000U
6759 /******************* Bit definition for SPDIFRX_DIR register *******************/
6760 #define SPDIFRX_DIR_THI 0x000013FFU
6761 #define SPDIFRX_DIR_TLO 0x1FFF0000U
6764 /******************************************************************************/
6765 /* */
6766 /* SD host Interface */
6767 /* */
6768 /******************************************************************************/
6769 /****************** Bit definition for SDMMC_POWER register ******************/
6770 #define SDMMC_POWER_PWRCTRL 0x03U
6771 #define SDMMC_POWER_PWRCTRL_0 0x01U
6772 #define SDMMC_POWER_PWRCTRL_1 0x02U
6774 /****************** Bit definition for SDMMC_CLKCR register ******************/
6775 #define SDMMC_CLKCR_CLKDIV 0x00FFU
6776 #define SDMMC_CLKCR_CLKEN 0x0100U
6777 #define SDMMC_CLKCR_PWRSAV 0x0200U
6778 #define SDMMC_CLKCR_BYPASS 0x0400U
6780 #define SDMMC_CLKCR_WIDBUS 0x1800U
6781 #define SDMMC_CLKCR_WIDBUS_0 0x0800U
6782 #define SDMMC_CLKCR_WIDBUS_1 0x1000U
6784 #define SDMMC_CLKCR_NEGEDGE 0x2000U
6785 #define SDMMC_CLKCR_HWFC_EN 0x4000U
6787 /******************* Bit definition for SDMMC_ARG register *******************/
6788 #define SDMMC_ARG_CMDARG 0xFFFFFFFFU
6790 /******************* Bit definition for SDMMC_CMD register *******************/
6791 #define SDMMC_CMD_CMDINDEX 0x003FU
6793 #define SDMMC_CMD_WAITRESP 0x00C0U
6794 #define SDMMC_CMD_WAITRESP_0 0x0040U
6795 #define SDMMC_CMD_WAITRESP_1 0x0080U
6797 #define SDMMC_CMD_WAITINT 0x0100U
6798 #define SDMMC_CMD_WAITPEND 0x0200U
6799 #define SDMMC_CMD_CPSMEN 0x0400U
6800 #define SDMMC_CMD_SDIOSUSPEND 0x0800U
6802 /***************** Bit definition for SDMMC_RESPCMD register *****************/
6803 #define SDMMC_RESPCMD_RESPCMD 0x3FU
6805 /****************** Bit definition for SDMMC_RESP0 register ******************/
6806 #define SDMMC_RESP0_CARDSTATUS0 0xFFFFFFFFU
6808 /****************** Bit definition for SDMMC_RESP1 register ******************/
6809 #define SDMMC_RESP1_CARDSTATUS1 0xFFFFFFFFU
6811 /****************** Bit definition for SDMMC_RESP2 register ******************/
6812 #define SDMMC_RESP2_CARDSTATUS2 0xFFFFFFFFU
6814 /****************** Bit definition for SDMMC_RESP3 register ******************/
6815 #define SDMMC_RESP3_CARDSTATUS3 0xFFFFFFFFU
6817 /****************** Bit definition for SDMMC_RESP4 register ******************/
6818 #define SDMMC_RESP4_CARDSTATUS4 0xFFFFFFFFU
6820 /****************** Bit definition for SDMMC_DTIMER register *****************/
6821 #define SDMMC_DTIMER_DATATIME 0xFFFFFFFFU
6823 /****************** Bit definition for SDMMC_DLEN register *******************/
6824 #define SDMMC_DLEN_DATALENGTH 0x01FFFFFFU
6826 /****************** Bit definition for SDMMC_DCTRL register ******************/
6827 #define SDMMC_DCTRL_DTEN 0x0001U
6828 #define SDMMC_DCTRL_DTDIR 0x0002U
6829 #define SDMMC_DCTRL_DTMODE 0x0004U
6830 #define SDMMC_DCTRL_DMAEN 0x0008U
6832 #define SDMMC_DCTRL_DBLOCKSIZE 0x00F0U
6833 #define SDMMC_DCTRL_DBLOCKSIZE_0 0x0010U
6834 #define SDMMC_DCTRL_DBLOCKSIZE_1 0x0020U
6835 #define SDMMC_DCTRL_DBLOCKSIZE_2 0x0040U
6836 #define SDMMC_DCTRL_DBLOCKSIZE_3 0x0080U
6838 #define SDMMC_DCTRL_RWSTART 0x0100U
6839 #define SDMMC_DCTRL_RWSTOP 0x0200U
6840 #define SDMMC_DCTRL_RWMOD 0x0400U
6841 #define SDMMC_DCTRL_SDIOEN 0x0800U
6843 /****************** Bit definition for SDMMC_DCOUNT register *****************/
6844 #define SDMMC_DCOUNT_DATACOUNT 0x01FFFFFFU
6846 /****************** Bit definition for SDMMC_STA registe ********************/
6847 #define SDMMC_STA_CCRCFAIL 0x00000001U
6848 #define SDMMC_STA_DCRCFAIL 0x00000002U
6849 #define SDMMC_STA_CTIMEOUT 0x00000004U
6850 #define SDMMC_STA_DTIMEOUT 0x00000008U
6851 #define SDMMC_STA_TXUNDERR 0x00000010U
6852 #define SDMMC_STA_RXOVERR 0x00000020U
6853 #define SDMMC_STA_CMDREND 0x00000040U
6854 #define SDMMC_STA_CMDSENT 0x00000080U
6855 #define SDMMC_STA_DATAEND 0x00000100U
6856 #define SDMMC_STA_DBCKEND 0x00000400U
6857 #define SDMMC_STA_CMDACT 0x00000800U
6858 #define SDMMC_STA_TXACT 0x00001000U
6859 #define SDMMC_STA_RXACT 0x00002000U
6860 #define SDMMC_STA_TXFIFOHE 0x00004000U
6861 #define SDMMC_STA_RXFIFOHF 0x00008000U
6862 #define SDMMC_STA_TXFIFOF 0x00010000U
6863 #define SDMMC_STA_RXFIFOF 0x00020000U
6864 #define SDMMC_STA_TXFIFOE 0x00040000U
6865 #define SDMMC_STA_RXFIFOE 0x00080000U
6866 #define SDMMC_STA_TXDAVL 0x00100000U
6867 #define SDMMC_STA_RXDAVL 0x00200000U
6868 #define SDMMC_STA_SDIOIT 0x00400000U
6870 /******************* Bit definition for SDMMC_ICR register *******************/
6871 #define SDMMC_ICR_CCRCFAILC 0x00000001U
6872 #define SDMMC_ICR_DCRCFAILC 0x00000002U
6873 #define SDMMC_ICR_CTIMEOUTC 0x00000004U
6874 #define SDMMC_ICR_DTIMEOUTC 0x00000008U
6875 #define SDMMC_ICR_TXUNDERRC 0x00000010U
6876 #define SDMMC_ICR_RXOVERRC 0x00000020U
6877 #define SDMMC_ICR_CMDRENDC 0x00000040U
6878 #define SDMMC_ICR_CMDSENTC 0x00000080U
6879 #define SDMMC_ICR_DATAENDC 0x00000100U
6880 #define SDMMC_ICR_DBCKENDC 0x00000400U
6881 #define SDMMC_ICR_SDIOITC 0x00400000U
6883 /****************** Bit definition for SDMMC_MASK register *******************/
6884 #define SDMMC_MASK_CCRCFAILIE 0x00000001U
6885 #define SDMMC_MASK_DCRCFAILIE 0x00000002U
6886 #define SDMMC_MASK_CTIMEOUTIE 0x00000004U
6887 #define SDMMC_MASK_DTIMEOUTIE 0x00000008U
6888 #define SDMMC_MASK_TXUNDERRIE 0x00000010U
6889 #define SDMMC_MASK_RXOVERRIE 0x00000020U
6890 #define SDMMC_MASK_CMDRENDIE 0x00000040U
6891 #define SDMMC_MASK_CMDSENTIE 0x00000080U
6892 #define SDMMC_MASK_DATAENDIE 0x00000100U
6893 #define SDMMC_MASK_DBCKENDIE 0x00000400U
6894 #define SDMMC_MASK_CMDACTIE 0x00000800U
6895 #define SDMMC_MASK_TXACTIE 0x00001000U
6896 #define SDMMC_MASK_RXACTIE 0x00002000U
6897 #define SDMMC_MASK_TXFIFOHEIE 0x00004000U
6898 #define SDMMC_MASK_RXFIFOHFIE 0x00008000U
6899 #define SDMMC_MASK_TXFIFOFIE 0x00010000U
6900 #define SDMMC_MASK_RXFIFOFIE 0x00020000U
6901 #define SDMMC_MASK_TXFIFOEIE 0x00040000U
6902 #define SDMMC_MASK_RXFIFOEIE 0x00080000U
6903 #define SDMMC_MASK_TXDAVLIE 0x00100000U
6904 #define SDMMC_MASK_RXDAVLIE 0x00200000U
6905 #define SDMMC_MASK_SDIOITIE 0x00400000U
6907 /***************** Bit definition for SDMMC_FIFOCNT register *****************/
6908 #define SDMMC_FIFOCNT_FIFOCOUNT 0x00FFFFFFU
6910 /****************** Bit definition for SDMMC_FIFO register *******************/
6911 #define SDMMC_FIFO_FIFODATA 0xFFFFFFFFU
6913 /******************************************************************************/
6914 /* */
6915 /* Serial Peripheral Interface (SPI) */
6916 /* */
6917 /******************************************************************************/
6918 /******************* Bit definition for SPI_CR1 register ********************/
6919 #define SPI_CR1_CPHA 0x00000001U
6920 #define SPI_CR1_CPOL 0x00000002U
6921 #define SPI_CR1_MSTR 0x00000004U
6922 #define SPI_CR1_BR 0x00000038U
6923 #define SPI_CR1_BR_0 0x00000008U
6924 #define SPI_CR1_BR_1 0x00000010U
6925 #define SPI_CR1_BR_2 0x00000020U
6926 #define SPI_CR1_SPE 0x00000040U
6927 #define SPI_CR1_LSBFIRST 0x00000080U
6928 #define SPI_CR1_SSI 0x00000100U
6929 #define SPI_CR1_SSM 0x00000200U
6930 #define SPI_CR1_RXONLY 0x00000400U
6931 #define SPI_CR1_CRCL 0x00000800U
6932 #define SPI_CR1_CRCNEXT 0x00001000U
6933 #define SPI_CR1_CRCEN 0x00002000U
6934 #define SPI_CR1_BIDIOE 0x00004000U
6935 #define SPI_CR1_BIDIMODE 0x00008000U
6937 /******************* Bit definition for SPI_CR2 register ********************/
6938 #define SPI_CR2_RXDMAEN 0x00000001U
6939 #define SPI_CR2_TXDMAEN 0x00000002U
6940 #define SPI_CR2_SSOE 0x00000004U
6941 #define SPI_CR2_NSSP 0x00000008U
6942 #define SPI_CR2_FRF 0x00000010U
6943 #define SPI_CR2_ERRIE 0x00000020U
6944 #define SPI_CR2_RXNEIE 0x00000040U
6945 #define SPI_CR2_TXEIE 0x00000080U
6946 #define SPI_CR2_DS 0x00000F00U
6947 #define SPI_CR2_DS_0 0x00000100U
6948 #define SPI_CR2_DS_1 0x00000200U
6949 #define SPI_CR2_DS_2 0x00000400U
6950 #define SPI_CR2_DS_3 0x00000800U
6951 #define SPI_CR2_FRXTH 0x00001000U
6952 #define SPI_CR2_LDMARX 0x00002000U
6953 #define SPI_CR2_LDMATX 0x00004000U
6955 /******************** Bit definition for SPI_SR register ********************/
6956 #define SPI_SR_RXNE 0x00000001U
6957 #define SPI_SR_TXE 0x00000002U
6958 #define SPI_SR_CHSIDE 0x00000004U
6959 #define SPI_SR_UDR 0x00000008U
6960 #define SPI_SR_CRCERR 0x00000010U
6961 #define SPI_SR_MODF 0x00000020U
6962 #define SPI_SR_OVR 0x00000040U
6963 #define SPI_SR_BSY 0x00000080U
6964 #define SPI_SR_FRE 0x00000100U
6965 #define SPI_SR_FRLVL 0x00000600U
6966 #define SPI_SR_FRLVL_0 0x00000200U
6967 #define SPI_SR_FRLVL_1 0x00000400U
6968 #define SPI_SR_FTLVL 0x00001800U
6969 #define SPI_SR_FTLVL_0 0x00000800U
6970 #define SPI_SR_FTLVL_1 0x00001000U
6972 /******************** Bit definition for SPI_DR register ********************/
6973 #define SPI_DR_DR 0xFFFFU
6975 /******************* Bit definition for SPI_CRCPR register ******************/
6976 #define SPI_CRCPR_CRCPOLY 0xFFFFU
6978 /****************** Bit definition for SPI_RXCRCR register ******************/
6979 #define SPI_RXCRCR_RXCRC 0xFFFFU
6981 /****************** Bit definition for SPI_TXCRCR register ******************/
6982 #define SPI_TXCRCR_TXCRC 0xFFFFU
6984 /****************** Bit definition for SPI_I2SCFGR register *****************/
6985 #define SPI_I2SCFGR_CHLEN 0x00000001U
6986 #define SPI_I2SCFGR_DATLEN 0x00000006U
6987 #define SPI_I2SCFGR_DATLEN_0 0x00000002U
6988 #define SPI_I2SCFGR_DATLEN_1 0x00000004U
6989 #define SPI_I2SCFGR_CKPOL 0x00000008U
6990 #define SPI_I2SCFGR_I2SSTD 0x00000030U
6991 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U
6992 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U
6993 #define SPI_I2SCFGR_PCMSYNC 0x00000080U
6994 #define SPI_I2SCFGR_I2SCFG 0x00000300U
6995 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U
6996 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U
6997 #define SPI_I2SCFGR_I2SE 0x00000400U
6998 #define SPI_I2SCFGR_I2SMOD 0x00000800U
6999 #define SPI_I2SCFGR_ASTRTEN 0x00001000U
7001 /****************** Bit definition for SPI_I2SPR register *******************/
7002 #define SPI_I2SPR_I2SDIV 0x00FFU
7003 #define SPI_I2SPR_ODD 0x0100U
7004 #define SPI_I2SPR_MCKOE 0x0200U
7007 /******************************************************************************/
7008 /* */
7009 /* SYSCFG */
7010 /* */
7011 /******************************************************************************/
7012 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
7013 #define SYSCFG_MEMRMP_MEM_BOOT 0x00000001U
7015 #define SYSCFG_MEMRMP_SWP_FB 0x00000100U
7017 #define SYSCFG_MEMRMP_SWP_FMC 0x00000C00U
7018 #define SYSCFG_MEMRMP_SWP_FMC_0 0x00000400U
7019 #define SYSCFG_MEMRMP_SWP_FMC_1 0x00000800U
7020 
7021 /****************** Bit definition for SYSCFG_PMC register ******************/
7022 #define SYSCFG_PMC_I2C1_FMP 0x00000001U
7023 #define SYSCFG_PMC_I2C2_FMP 0x00000002U
7024 #define SYSCFG_PMC_I2C3_FMP 0x00000004U
7025 #define SYSCFG_PMC_I2C4_FMP 0x00000008U
7026 #define SYSCFG_PMC_I2C_PB6_FMP 0x00000010U
7027 #define SYSCFG_PMC_I2C_PB7_FMP 0x00000020U
7028 #define SYSCFG_PMC_I2C_PB8_FMP 0x00000040U
7029 #define SYSCFG_PMC_I2C_PB9_FMP 0x00000080U
7031 #define SYSCFG_PMC_ADCxDC2 0x00070000U
7032 #define SYSCFG_PMC_ADC1DC2 0x00010000U
7033 #define SYSCFG_PMC_ADC2DC2 0x00020000U
7034 #define SYSCFG_PMC_ADC3DC2 0x00040000U
7036 #define SYSCFG_PMC_MII_RMII_SEL 0x00800000U
7038 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
7039 #define SYSCFG_EXTICR1_EXTI0 0x000FU
7040 #define SYSCFG_EXTICR1_EXTI1 0x00F0U
7041 #define SYSCFG_EXTICR1_EXTI2 0x0F00U
7042 #define SYSCFG_EXTICR1_EXTI3 0xF000U
7046 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
7047 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
7048 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
7049 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
7050 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
7051 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
7052 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
7053 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
7054 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U
7055 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U
7056 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU
7061 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
7062 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
7063 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
7064 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
7065 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
7066 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
7067 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
7068 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
7069 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U
7070 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U
7071 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U
7076 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
7077 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
7078 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
7079 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
7080 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
7081 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
7082 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
7083 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
7084 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U
7085 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U
7086 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U
7091 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
7092 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
7093 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
7094 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
7095 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
7096 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
7097 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
7098 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
7099 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U
7100 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U
7101 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U
7103 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
7104 #define SYSCFG_EXTICR2_EXTI4 0x000FU
7105 #define SYSCFG_EXTICR2_EXTI5 0x00F0U
7106 #define SYSCFG_EXTICR2_EXTI6 0x0F00U
7107 #define SYSCFG_EXTICR2_EXTI7 0xF000U
7111 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
7112 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
7113 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
7114 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
7115 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
7116 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
7117 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
7118 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
7119 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U
7120 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U
7121 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU
7126 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
7127 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
7128 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
7129 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
7130 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
7131 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
7132 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
7133 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
7134 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U
7135 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U
7136 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U
7141 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
7142 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
7143 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
7144 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
7145 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
7146 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
7147 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
7148 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
7149 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U
7150 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U
7151 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U
7156 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
7157 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
7158 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
7159 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
7160 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
7161 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
7162 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
7163 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
7164 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U
7165 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U
7166 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U
7168 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
7169 #define SYSCFG_EXTICR3_EXTI8 0x000FU
7170 #define SYSCFG_EXTICR3_EXTI9 0x00F0U
7171 #define SYSCFG_EXTICR3_EXTI10 0x0F00U
7172 #define SYSCFG_EXTICR3_EXTI11 0xF000U
7177 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
7178 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
7179 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
7180 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
7181 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
7182 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
7183 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
7184 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
7185 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U
7186 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U
7191 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
7192 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
7193 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
7194 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
7195 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
7196 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
7197 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
7198 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
7199 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U
7200 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U
7205 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
7206 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
7207 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
7208 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
7209 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
7210 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
7211 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
7212 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
7213 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U
7214 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U
7219 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
7220 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
7221 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
7222 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
7223 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
7224 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
7225 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
7226 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
7227 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U
7228 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U
7231 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
7232 #define SYSCFG_EXTICR4_EXTI12 0x000FU
7233 #define SYSCFG_EXTICR4_EXTI13 0x00F0U
7234 #define SYSCFG_EXTICR4_EXTI14 0x0F00U
7235 #define SYSCFG_EXTICR4_EXTI15 0xF000U
7239 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
7240 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
7241 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
7242 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
7243 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
7244 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
7245 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
7246 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
7247 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U
7248 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U
7253 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
7254 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
7255 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
7256 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
7257 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
7258 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
7259 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
7260 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
7261 #define SYSCFG_EXTICR4_EXTI13_PI 0x0080U
7262 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0090U
7267 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
7268 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
7269 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
7270 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
7271 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
7272 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
7273 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
7274 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
7275 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U
7276 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U
7281 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
7282 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
7283 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
7284 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
7285 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
7286 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
7287 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
7288 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
7289 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U
7290 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U
7292 /****************** Bit definition for SYSCFG_CBR register ******************/
7293 #define SYSCFG_CBR_CLL 0x00000001U
7294 #define SYSCFG_CBR_PVDL 0x00000004U
7296 /****************** Bit definition for SYSCFG_CMPCR register ****************/
7297 #define SYSCFG_CMPCR_CMP_PD 0x00000001U
7298 #define SYSCFG_CMPCR_READY 0x00000100U
7300 /******************************************************************************/
7301 /* */
7302 /* TIM */
7303 /* */
7304 /******************************************************************************/
7305 /******************* Bit definition for TIM_CR1 register ********************/
7306 #define TIM_CR1_CEN 0x0001U
7307 #define TIM_CR1_UDIS 0x0002U
7308 #define TIM_CR1_URS 0x0004U
7309 #define TIM_CR1_OPM 0x0008U
7310 #define TIM_CR1_DIR 0x0010U
7312 #define TIM_CR1_CMS 0x0060U
7313 #define TIM_CR1_CMS_0 0x0020U
7314 #define TIM_CR1_CMS_1 0x0040U
7316 #define TIM_CR1_ARPE 0x0080U
7318 #define TIM_CR1_CKD 0x0300U
7319 #define TIM_CR1_CKD_0 0x0100U
7320 #define TIM_CR1_CKD_1 0x0200U
7321 #define TIM_CR1_UIFREMAP 0x0800U
7323 /******************* Bit definition for TIM_CR2 register ********************/
7324 #define TIM_CR2_CCPC 0x00000001U
7325 #define TIM_CR2_CCUS 0x00000004U
7326 #define TIM_CR2_CCDS 0x00000008U
7328 #define TIM_CR2_OIS5 0x00010000U
7329 #define TIM_CR2_OIS6 0x00040000U
7331 #define TIM_CR2_MMS 0x0070U
7332 #define TIM_CR2_MMS_0 0x0010U
7333 #define TIM_CR2_MMS_1 0x0020U
7334 #define TIM_CR2_MMS_2 0x0040U
7336 #define TIM_CR2_MMS2 0x00F00000U
7337 #define TIM_CR2_MMS2_0 0x00100000U
7338 #define TIM_CR2_MMS2_1 0x00200000U
7339 #define TIM_CR2_MMS2_2 0x00400000U
7340 #define TIM_CR2_MMS2_3 0x00800000U
7342 #define TIM_CR2_TI1S 0x0080U
7343 #define TIM_CR2_OIS1 0x0100U
7344 #define TIM_CR2_OIS1N 0x0200U
7345 #define TIM_CR2_OIS2 0x0400U
7346 #define TIM_CR2_OIS2N 0x0800U
7347 #define TIM_CR2_OIS3 0x1000U
7348 #define TIM_CR2_OIS3N 0x2000U
7349 #define TIM_CR2_OIS4 0x4000U
7351 /******************* Bit definition for TIM_SMCR register *******************/
7352 #define TIM_SMCR_SMS 0x00010007U
7353 #define TIM_SMCR_SMS_0 0x00000001U
7354 #define TIM_SMCR_SMS_1 0x00000002U
7355 #define TIM_SMCR_SMS_2 0x00000004U
7356 #define TIM_SMCR_SMS_3 0x00010000U
7357 #define TIM_SMCR_OCCS 0x00000008U
7359 #define TIM_SMCR_TS 0x0070U
7360 #define TIM_SMCR_TS_0 0x0010U
7361 #define TIM_SMCR_TS_1 0x0020U
7362 #define TIM_SMCR_TS_2 0x0040U
7364 #define TIM_SMCR_MSM 0x0080U
7366 #define TIM_SMCR_ETF 0x0F00U
7367 #define TIM_SMCR_ETF_0 0x0100U
7368 #define TIM_SMCR_ETF_1 0x0200U
7369 #define TIM_SMCR_ETF_2 0x0400U
7370 #define TIM_SMCR_ETF_3 0x0800U
7372 #define TIM_SMCR_ETPS 0x3000U
7373 #define TIM_SMCR_ETPS_0 0x1000U
7374 #define TIM_SMCR_ETPS_1 0x2000U
7376 #define TIM_SMCR_ECE 0x4000U
7377 #define TIM_SMCR_ETP 0x8000U
7379 /******************* Bit definition for TIM_DIER register *******************/
7380 #define TIM_DIER_UIE 0x0001U
7381 #define TIM_DIER_CC1IE 0x0002U
7382 #define TIM_DIER_CC2IE 0x0004U
7383 #define TIM_DIER_CC3IE 0x0008U
7384 #define TIM_DIER_CC4IE 0x0010U
7385 #define TIM_DIER_COMIE 0x0020U
7386 #define TIM_DIER_TIE 0x0040U
7387 #define TIM_DIER_BIE 0x0080U
7388 #define TIM_DIER_UDE 0x0100U
7389 #define TIM_DIER_CC1DE 0x0200U
7390 #define TIM_DIER_CC2DE 0x0400U
7391 #define TIM_DIER_CC3DE 0x0800U
7392 #define TIM_DIER_CC4DE 0x1000U
7393 #define TIM_DIER_COMDE 0x2000U
7394 #define TIM_DIER_TDE 0x4000U
7396 /******************** Bit definition for TIM_SR register ********************/
7397 #define TIM_SR_UIF 0x0001U
7398 #define TIM_SR_CC1IF 0x0002U
7399 #define TIM_SR_CC2IF 0x0004U
7400 #define TIM_SR_CC3IF 0x0008U
7401 #define TIM_SR_CC4IF 0x0010U
7402 #define TIM_SR_COMIF 0x0020U
7403 #define TIM_SR_TIF 0x0040U
7404 #define TIM_SR_BIF 0x0080U
7405 #define TIM_SR_B2IF 0x0100U
7406 #define TIM_SR_CC1OF 0x0200U
7407 #define TIM_SR_CC2OF 0x0400U
7408 #define TIM_SR_CC3OF 0x0800U
7409 #define TIM_SR_CC4OF 0x1000U
7411 /******************* Bit definition for TIM_EGR register ********************/
7412 #define TIM_EGR_UG 0x00000001U
7413 #define TIM_EGR_CC1G 0x00000002U
7414 #define TIM_EGR_CC2G 0x00000004U
7415 #define TIM_EGR_CC3G 0x00000008U
7416 #define TIM_EGR_CC4G 0x00000010U
7417 #define TIM_EGR_COMG 0x00000020U
7418 #define TIM_EGR_TG 0x00000040U
7419 #define TIM_EGR_BG 0x00000080U
7420 #define TIM_EGR_B2G 0x00000100U
7422 /****************** Bit definition for TIM_CCMR1 register *******************/
7423 #define TIM_CCMR1_CC1S 0x00000003U
7424 #define TIM_CCMR1_CC1S_0 0x00000001U
7425 #define TIM_CCMR1_CC1S_1 0x00000002U
7427 #define TIM_CCMR1_OC1FE 0x00000004U
7428 #define TIM_CCMR1_OC1PE 0x00000008U
7430 #define TIM_CCMR1_OC1M 0x00010070U
7431 #define TIM_CCMR1_OC1M_0 0x00000010U
7432 #define TIM_CCMR1_OC1M_1 0x00000020U
7433 #define TIM_CCMR1_OC1M_2 0x00000040U
7434 #define TIM_CCMR1_OC1M_3 0x00010000U
7436 #define TIM_CCMR1_OC1CE 0x00000080U
7438 #define TIM_CCMR1_CC2S 0x00000300U
7439 #define TIM_CCMR1_CC2S_0 0x00000100U
7440 #define TIM_CCMR1_CC2S_1 0x00000200U
7442 #define TIM_CCMR1_OC2FE 0x00000400U
7443 #define TIM_CCMR1_OC2PE 0x00000800U
7445 #define TIM_CCMR1_OC2M 0x01007000U
7446 #define TIM_CCMR1_OC2M_0 0x00001000U
7447 #define TIM_CCMR1_OC2M_1 0x00002000U
7448 #define TIM_CCMR1_OC2M_2 0x00004000U
7449 #define TIM_CCMR1_OC2M_3 0x01000000U
7451 #define TIM_CCMR1_OC2CE 0x00008000U
7453 /*----------------------------------------------------------------------------*/
7454 
7455 #define TIM_CCMR1_IC1PSC 0x000CU
7456 #define TIM_CCMR1_IC1PSC_0 0x0004U
7457 #define TIM_CCMR1_IC1PSC_1 0x0008U
7459 #define TIM_CCMR1_IC1F 0x00F0U
7460 #define TIM_CCMR1_IC1F_0 0x0010U
7461 #define TIM_CCMR1_IC1F_1 0x0020U
7462 #define TIM_CCMR1_IC1F_2 0x0040U
7463 #define TIM_CCMR1_IC1F_3 0x0080U
7465 #define TIM_CCMR1_IC2PSC 0x0C00U
7466 #define TIM_CCMR1_IC2PSC_0 0x0400U
7467 #define TIM_CCMR1_IC2PSC_1 0x0800U
7469 #define TIM_CCMR1_IC2F 0xF000U
7470 #define TIM_CCMR1_IC2F_0 0x1000U
7471 #define TIM_CCMR1_IC2F_1 0x2000U
7472 #define TIM_CCMR1_IC2F_2 0x4000U
7473 #define TIM_CCMR1_IC2F_3 0x8000U
7475 /****************** Bit definition for TIM_CCMR2 register *******************/
7476 #define TIM_CCMR2_CC3S 0x00000003U
7477 #define TIM_CCMR2_CC3S_0 0x00000001U
7478 #define TIM_CCMR2_CC3S_1 0x00000002U
7480 #define TIM_CCMR2_OC3FE 0x00000004U
7481 #define TIM_CCMR2_OC3PE 0x00000008U
7483 #define TIM_CCMR2_OC3M 0x00010070U
7484 #define TIM_CCMR2_OC3M_0 0x00000010U
7485 #define TIM_CCMR2_OC3M_1 0x00000020U
7486 #define TIM_CCMR2_OC3M_2 0x00000040U
7487 #define TIM_CCMR2_OC3M_3 0x00010000U
7491 #define TIM_CCMR2_OC3CE 0x00000080U
7493 #define TIM_CCMR2_CC4S 0x00000300U
7494 #define TIM_CCMR2_CC4S_0 0x00000100U
7495 #define TIM_CCMR2_CC4S_1 0x00000200U
7497 #define TIM_CCMR2_OC4FE 0x00000400U
7498 #define TIM_CCMR2_OC4PE 0x00000800U
7500 #define TIM_CCMR2_OC4M 0x01007000U
7501 #define TIM_CCMR2_OC4M_0 0x00001000U
7502 #define TIM_CCMR2_OC4M_1 0x00002000U
7503 #define TIM_CCMR2_OC4M_2 0x00004000U
7504 #define TIM_CCMR2_OC4M_3 0x01000000U
7506 #define TIM_CCMR2_OC4CE 0x8000U
7508 /*----------------------------------------------------------------------------*/
7509 
7510 #define TIM_CCMR2_IC3PSC 0x000CU
7511 #define TIM_CCMR2_IC3PSC_0 0x0004U
7512 #define TIM_CCMR2_IC3PSC_1 0x0008U
7514 #define TIM_CCMR2_IC3F 0x00F0U
7515 #define TIM_CCMR2_IC3F_0 0x0010U
7516 #define TIM_CCMR2_IC3F_1 0x0020U
7517 #define TIM_CCMR2_IC3F_2 0x0040U
7518 #define TIM_CCMR2_IC3F_3 0x0080U
7520 #define TIM_CCMR2_IC4PSC 0x0C00U
7521 #define TIM_CCMR2_IC4PSC_0 0x0400U
7522 #define TIM_CCMR2_IC4PSC_1 0x0800U
7524 #define TIM_CCMR2_IC4F 0xF000U
7525 #define TIM_CCMR2_IC4F_0 0x1000U
7526 #define TIM_CCMR2_IC4F_1 0x2000U
7527 #define TIM_CCMR2_IC4F_2 0x4000U
7528 #define TIM_CCMR2_IC4F_3 0x8000U
7530 /******************* Bit definition for TIM_CCER register *******************/
7531 #define TIM_CCER_CC1E 0x00000001U
7532 #define TIM_CCER_CC1P 0x00000002U
7533 #define TIM_CCER_CC1NE 0x00000004U
7534 #define TIM_CCER_CC1NP 0x00000008U
7535 #define TIM_CCER_CC2E 0x00000010U
7536 #define TIM_CCER_CC2P 0x00000020U
7537 #define TIM_CCER_CC2NE 0x00000040U
7538 #define TIM_CCER_CC2NP 0x00000080U
7539 #define TIM_CCER_CC3E 0x00000100U
7540 #define TIM_CCER_CC3P 0x00000200U
7541 #define TIM_CCER_CC3NE 0x00000400U
7542 #define TIM_CCER_CC3NP 0x00000800U
7543 #define TIM_CCER_CC4E 0x00001000U
7544 #define TIM_CCER_CC4P 0x00002000U
7545 #define TIM_CCER_CC4NP 0x00008000U
7546 #define TIM_CCER_CC5E 0x00010000U
7547 #define TIM_CCER_CC5P 0x00020000U
7548 #define TIM_CCER_CC6E 0x00100000U
7549 #define TIM_CCER_CC6P 0x00200000U
7552 /******************* Bit definition for TIM_CNT register ********************/
7553 #define TIM_CNT_CNT 0xFFFFU
7555 /******************* Bit definition for TIM_PSC register ********************/
7556 #define TIM_PSC_PSC 0xFFFFU
7558 /******************* Bit definition for TIM_ARR register ********************/
7559 #define TIM_ARR_ARR 0xFFFFU
7561 /******************* Bit definition for TIM_RCR register ********************/
7562 #define TIM_RCR_REP ((uint8_t)0xFFU)
7564 /******************* Bit definition for TIM_CCR1 register *******************/
7565 #define TIM_CCR1_CCR1 0xFFFFU
7567 /******************* Bit definition for TIM_CCR2 register *******************/
7568 #define TIM_CCR2_CCR2 0xFFFFU
7570 /******************* Bit definition for TIM_CCR3 register *******************/
7571 #define TIM_CCR3_CCR3 0xFFFFU
7573 /******************* Bit definition for TIM_CCR4 register *******************/
7574 #define TIM_CCR4_CCR4 0xFFFFU
7576 /******************* Bit definition for TIM_BDTR register *******************/
7577 #define TIM_BDTR_DTG 0x000000FFU
7578 #define TIM_BDTR_DTG_0 0x00000001U
7579 #define TIM_BDTR_DTG_1 0x00000002U
7580 #define TIM_BDTR_DTG_2 0x00000004U
7581 #define TIM_BDTR_DTG_3 0x00000008U
7582 #define TIM_BDTR_DTG_4 0x00000010U
7583 #define TIM_BDTR_DTG_5 0x00000020U
7584 #define TIM_BDTR_DTG_6 0x00000040U
7585 #define TIM_BDTR_DTG_7 0x00000080U
7587 #define TIM_BDTR_LOCK 0x00000300U
7588 #define TIM_BDTR_LOCK_0 0x00000100U
7589 #define TIM_BDTR_LOCK_1 0x00000200U
7591 #define TIM_BDTR_OSSI 0x00000400U
7592 #define TIM_BDTR_OSSR 0x00000800U
7593 #define TIM_BDTR_BKE 0x00001000U
7594 #define TIM_BDTR_BKP 0x00002000U
7595 #define TIM_BDTR_AOE 0x00004000U
7596 #define TIM_BDTR_MOE 0x00008000U
7597 #define TIM_BDTR_BKF 0x000F0000U
7598 #define TIM_BDTR_BK2F 0x00F00000U
7599 #define TIM_BDTR_BK2E 0x01000000U
7600 #define TIM_BDTR_BK2P 0x02000000U
7602 /******************* Bit definition for TIM_DCR register ********************/
7603 #define TIM_DCR_DBA 0x001FU
7604 #define TIM_DCR_DBA_0 0x0001U
7605 #define TIM_DCR_DBA_1 0x0002U
7606 #define TIM_DCR_DBA_2 0x0004U
7607 #define TIM_DCR_DBA_3 0x0008U
7608 #define TIM_DCR_DBA_4 0x0010U
7610 #define TIM_DCR_DBL 0x1F00U
7611 #define TIM_DCR_DBL_0 0x0100U
7612 #define TIM_DCR_DBL_1 0x0200U
7613 #define TIM_DCR_DBL_2 0x0400U
7614 #define TIM_DCR_DBL_3 0x0800U
7615 #define TIM_DCR_DBL_4 0x1000U
7617 /******************* Bit definition for TIM_DMAR register *******************/
7618 #define TIM_DMAR_DMAB 0xFFFFU
7620 /******************* Bit definition for TIM_OR regiter *********************/
7621 #define TIM_OR_TI4_RMP 0x00C0U
7622 #define TIM_OR_TI4_RMP_0 0x0040U
7623 #define TIM_OR_TI4_RMP_1 0x0080U
7624 #define TIM_OR_ITR1_RMP 0x0C00U
7625 #define TIM_OR_ITR1_RMP_0 0x0400U
7626 #define TIM_OR_ITR1_RMP_1 0x0800U
7628 /****************** Bit definition for TIM_CCMR3 register *******************/
7629 #define TIM_CCMR3_OC5FE 0x00000004U
7630 #define TIM_CCMR3_OC5PE 0x00000008U
7632 #define TIM_CCMR3_OC5M 0x00010070U
7633 #define TIM_CCMR3_OC5M_0 0x00000010U
7634 #define TIM_CCMR3_OC5M_1 0x00000020U
7635 #define TIM_CCMR3_OC5M_2 0x00000040U
7636 #define TIM_CCMR3_OC5M_3 0x00010000U
7638 #define TIM_CCMR3_OC5CE 0x00000080U
7640 #define TIM_CCMR3_OC6FE 0x00000400U
7641 #define TIM_CCMR3_OC6PE 0x00000800U
7643 #define TIM_CCMR3_OC6M 0x01007000U
7644 #define TIM_CCMR3_OC6M_0 0x00001000U
7645 #define TIM_CCMR3_OC6M_1 0x00002000U
7646 #define TIM_CCMR3_OC6M_2 0x00004000U
7647 #define TIM_CCMR3_OC6M_3 0x01000000U
7649 #define TIM_CCMR3_OC6CE 0x00008000U
7651 /******************* Bit definition for TIM_CCR5 register *******************/
7652 #define TIM_CCR5_CCR5 0xFFFFFFFFU
7653 #define TIM_CCR5_GC5C1 0x20000000U
7654 #define TIM_CCR5_GC5C2 0x40000000U
7655 #define TIM_CCR5_GC5C3 0x80000000U
7657 /******************* Bit definition for TIM_CCR6 register *******************/
7658 #define TIM_CCR6_CCR6 ((uint16_t)0xFFFFU)
7660 /******************* Bit definition for TIM1_AF1 register *******************/
7661 #define TIM1_AF1_BKINE 0x00000001U
7662 #define TIM1_AF1_BKDF1BKE 0x00000100U
7664 /******************* Bit definition for TIM1_AF2 register *******************/
7665 #define TIM1_AF2_BK2INE 0x00000001U
7666 #define TIM1_AF2_BK2DF1BKE 0x00000100U
7668 /******************* Bit definition for TIM8_AF1 register *******************/
7669 #define TIM8_AF1_BKINE 0x00000001U
7670 #define TIM8_AF1_BKDF1BKE 0x00000100U
7672 /******************* Bit definition for TIM8_AF2 register *******************/
7673 #define TIM8_AF2_BK2INE 0x00000001U
7674 #define TIM8_AF2_BK2DF1BKE 0x00000100U
7676 /******************************************************************************/
7677 /* */
7678 /* Low Power Timer (LPTIM) */
7679 /* */
7680 /******************************************************************************/
7681 /****************** Bit definition for LPTIM_ISR register *******************/
7682 #define LPTIM_ISR_CMPM 0x00000001U
7683 #define LPTIM_ISR_ARRM 0x00000002U
7684 #define LPTIM_ISR_EXTTRIG 0x00000004U
7685 #define LPTIM_ISR_CMPOK 0x00000008U
7686 #define LPTIM_ISR_ARROK 0x00000010U
7687 #define LPTIM_ISR_UP 0x00000020U
7688 #define LPTIM_ISR_DOWN 0x00000040U
7690 /****************** Bit definition for LPTIM_ICR register *******************/
7691 #define LPTIM_ICR_CMPMCF 0x00000001U
7692 #define LPTIM_ICR_ARRMCF 0x00000002U
7693 #define LPTIM_ICR_EXTTRIGCF 0x00000004U
7694 #define LPTIM_ICR_CMPOKCF 0x00000008U
7695 #define LPTIM_ICR_ARROKCF 0x00000010U
7696 #define LPTIM_ICR_UPCF 0x00000020U
7697 #define LPTIM_ICR_DOWNCF 0x00000040U
7699 /****************** Bit definition for LPTIM_IER register *******************/
7700 #define LPTIM_IER_CMPMIE 0x00000001U
7701 #define LPTIM_IER_ARRMIE 0x00000002U
7702 #define LPTIM_IER_EXTTRIGIE 0x00000004U
7703 #define LPTIM_IER_CMPOKIE 0x00000008U
7704 #define LPTIM_IER_ARROKIE 0x00000010U
7705 #define LPTIM_IER_UPIE 0x00000020U
7706 #define LPTIM_IER_DOWNIE 0x00000040U
7708 /****************** Bit definition for LPTIM_CFGR register*******************/
7709 #define LPTIM_CFGR_CKSEL 0x00000001U
7711 #define LPTIM_CFGR_CKPOL 0x00000006U
7712 #define LPTIM_CFGR_CKPOL_0 0x00000002U
7713 #define LPTIM_CFGR_CKPOL_1 0x00000004U
7715 #define LPTIM_CFGR_CKFLT 0x00000018U
7716 #define LPTIM_CFGR_CKFLT_0 0x00000008U
7717 #define LPTIM_CFGR_CKFLT_1 0x00000010U
7719 #define LPTIM_CFGR_TRGFLT 0x000000C0U
7720 #define LPTIM_CFGR_TRGFLT_0 0x00000040U
7721 #define LPTIM_CFGR_TRGFLT_1 0x00000080U
7723 #define LPTIM_CFGR_PRESC 0x00000E00U
7724 #define LPTIM_CFGR_PRESC_0 0x00000200U
7725 #define LPTIM_CFGR_PRESC_1 0x00000400U
7726 #define LPTIM_CFGR_PRESC_2 0x00000800U
7728 #define LPTIM_CFGR_TRIGSEL 0x0000E000U
7729 #define LPTIM_CFGR_TRIGSEL_0 0x00002000U
7730 #define LPTIM_CFGR_TRIGSEL_1 0x00004000U
7731 #define LPTIM_CFGR_TRIGSEL_2 0x00008000U
7733 #define LPTIM_CFGR_TRIGEN 0x00060000U
7734 #define LPTIM_CFGR_TRIGEN_0 0x00020000U
7735 #define LPTIM_CFGR_TRIGEN_1 0x00040000U
7737 #define LPTIM_CFGR_TIMOUT 0x00080000U
7738 #define LPTIM_CFGR_WAVE 0x00100000U
7739 #define LPTIM_CFGR_WAVPOL 0x00200000U
7740 #define LPTIM_CFGR_PRELOAD 0x00400000U
7741 #define LPTIM_CFGR_COUNTMODE 0x00800000U
7742 #define LPTIM_CFGR_ENC 0x01000000U
7744 /****************** Bit definition for LPTIM_CR register ********************/
7745 #define LPTIM_CR_ENABLE 0x00000001U
7746 #define LPTIM_CR_SNGSTRT 0x00000002U
7747 #define LPTIM_CR_CNTSTRT 0x00000004U
7749 /****************** Bit definition for LPTIM_CMP register *******************/
7750 #define LPTIM_CMP_CMP 0x0000FFFFU
7752 /****************** Bit definition for LPTIM_ARR register *******************/
7753 #define LPTIM_ARR_ARR 0x0000FFFFU
7755 /****************** Bit definition for LPTIM_CNT register *******************/
7756 #define LPTIM_CNT_CNT 0x0000FFFFU
7757 /******************************************************************************/
7758 /* */
7759 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
7760 /* */
7761 /******************************************************************************/
7762 /****************** Bit definition for USART_CR1 register *******************/
7763 #define USART_CR1_UE 0x00000001U
7764 #define USART_CR1_RE 0x00000004U
7765 #define USART_CR1_TE 0x00000008U
7766 #define USART_CR1_IDLEIE 0x00000010U
7767 #define USART_CR1_RXNEIE 0x00000020U
7768 #define USART_CR1_TCIE 0x00000040U
7769 #define USART_CR1_TXEIE 0x00000080U
7770 #define USART_CR1_PEIE 0x00000100U
7771 #define USART_CR1_PS 0x00000200U
7772 #define USART_CR1_PCE 0x00000400U
7773 #define USART_CR1_WAKE 0x00000800U
7774 #define USART_CR1_M 0x10001000U
7775 #define USART_CR1_M_0 0x00001000U
7776 #define USART_CR1_MME 0x00002000U
7777 #define USART_CR1_CMIE 0x00004000U
7778 #define USART_CR1_OVER8 0x00008000U
7779 #define USART_CR1_DEDT 0x001F0000U
7780 #define USART_CR1_DEDT_0 0x00010000U
7781 #define USART_CR1_DEDT_1 0x00020000U
7782 #define USART_CR1_DEDT_2 0x00040000U
7783 #define USART_CR1_DEDT_3 0x00080000U
7784 #define USART_CR1_DEDT_4 0x00100000U
7785 #define USART_CR1_DEAT 0x03E00000U
7786 #define USART_CR1_DEAT_0 0x00200000U
7787 #define USART_CR1_DEAT_1 0x00400000U
7788 #define USART_CR1_DEAT_2 0x00800000U
7789 #define USART_CR1_DEAT_3 0x01000000U
7790 #define USART_CR1_DEAT_4 0x02000000U
7791 #define USART_CR1_RTOIE 0x04000000U
7792 #define USART_CR1_EOBIE 0x08000000U
7793 #define USART_CR1_M_1 0x10000000U
7795 /****************** Bit definition for USART_CR2 register *******************/
7796 #define USART_CR2_ADDM7 0x00000010U
7797 #define USART_CR2_LBDL 0x00000020U
7798 #define USART_CR2_LBDIE 0x00000040U
7799 #define USART_CR2_LBCL 0x00000100U
7800 #define USART_CR2_CPHA 0x00000200U
7801 #define USART_CR2_CPOL 0x00000400U
7802 #define USART_CR2_CLKEN 0x00000800U
7803 #define USART_CR2_STOP 0x00003000U
7804 #define USART_CR2_STOP_0 0x00001000U
7805 #define USART_CR2_STOP_1 0x00002000U
7806 #define USART_CR2_LINEN 0x00004000U
7807 #define USART_CR2_SWAP 0x00008000U
7808 #define USART_CR2_RXINV 0x00010000U
7809 #define USART_CR2_TXINV 0x00020000U
7810 #define USART_CR2_DATAINV 0x00040000U
7811 #define USART_CR2_MSBFIRST 0x00080000U
7812 #define USART_CR2_ABREN 0x00100000U
7813 #define USART_CR2_ABRMODE 0x00600000U
7814 #define USART_CR2_ABRMODE_0 0x00200000U
7815 #define USART_CR2_ABRMODE_1 0x00400000U
7816 #define USART_CR2_RTOEN 0x00800000U
7817 #define USART_CR2_ADD 0xFF000000U
7819 /****************** Bit definition for USART_CR3 register *******************/
7820 #define USART_CR3_EIE 0x00000001U
7821 #define USART_CR3_IREN 0x00000002U
7822 #define USART_CR3_IRLP 0x00000004U
7823 #define USART_CR3_HDSEL 0x00000008U
7824 #define USART_CR3_NACK 0x00000010U
7825 #define USART_CR3_SCEN 0x00000020U
7826 #define USART_CR3_DMAR 0x00000040U
7827 #define USART_CR3_DMAT 0x00000080U
7828 #define USART_CR3_RTSE 0x00000100U
7829 #define USART_CR3_CTSE 0x00000200U
7830 #define USART_CR3_CTSIE 0x00000400U
7831 #define USART_CR3_ONEBIT 0x00000800U
7832 #define USART_CR3_OVRDIS 0x00001000U
7833 #define USART_CR3_DDRE 0x00002000U
7834 #define USART_CR3_DEM 0x00004000U
7835 #define USART_CR3_DEP 0x00008000U
7836 #define USART_CR3_SCARCNT 0x000E0000U
7837 #define USART_CR3_SCARCNT_0 0x00020000U
7838 #define USART_CR3_SCARCNT_1 0x00040000U
7839 #define USART_CR3_SCARCNT_2 0x00080000U
7842 /****************** Bit definition for USART_BRR register *******************/
7843 #define USART_BRR_DIV_FRACTION 0x000FU
7844 #define USART_BRR_DIV_MANTISSA 0xFFF0U
7846 /****************** Bit definition for USART_GTPR register ******************/
7847 #define USART_GTPR_PSC 0x00FFU
7848 #define USART_GTPR_GT 0xFF00U
7851 /******************* Bit definition for USART_RTOR register *****************/
7852 #define USART_RTOR_RTO 0x00FFFFFFU
7853 #define USART_RTOR_BLEN 0xFF000000U
7855 /******************* Bit definition for USART_RQR register ******************/
7856 #define USART_RQR_ABRRQ 0x0001U
7857 #define USART_RQR_SBKRQ 0x0002U
7858 #define USART_RQR_MMRQ 0x0004U
7859 #define USART_RQR_RXFRQ 0x0008U
7860 #define USART_RQR_TXFRQ 0x0010U
7862 /******************* Bit definition for USART_ISR register ******************/
7863 #define USART_ISR_PE 0x00000001U
7864 #define USART_ISR_FE 0x00000002U
7865 #define USART_ISR_NE 0x00000004U
7866 #define USART_ISR_ORE 0x00000008U
7867 #define USART_ISR_IDLE 0x00000010U
7868 #define USART_ISR_RXNE 0x00000020U
7869 #define USART_ISR_TC 0x00000040U
7870 #define USART_ISR_TXE 0x00000080U
7871 #define USART_ISR_LBDF 0x00000100U
7872 #define USART_ISR_CTSIF 0x00000200U
7873 #define USART_ISR_CTS 0x00000400U
7874 #define USART_ISR_RTOF 0x00000800U
7875 #define USART_ISR_EOBF 0x00001000U
7876 #define USART_ISR_ABRE 0x00004000U
7877 #define USART_ISR_ABRF 0x00008000U
7878 #define USART_ISR_BUSY 0x00010000U
7879 #define USART_ISR_CMF 0x00020000U
7880 #define USART_ISR_SBKF 0x00040000U
7881 #define USART_ISR_RWU 0x00080000U
7882 #define USART_ISR_WUF 0x00100000U
7883 #define USART_ISR_TEACK 0x00200000U
7884 #define USART_ISR_REACK 0x00400000U
7887 /******************* Bit definition for USART_ICR register ******************/
7888 #define USART_ICR_PECF 0x00000001U
7889 #define USART_ICR_FECF 0x00000002U
7890 #define USART_ICR_NCF 0x00000004U
7891 #define USART_ICR_ORECF 0x00000008U
7892 #define USART_ICR_IDLECF 0x00000010U
7893 #define USART_ICR_TCCF 0x00000040U
7894 #define USART_ICR_LBDCF 0x00000100U
7895 #define USART_ICR_CTSCF 0x00000200U
7896 #define USART_ICR_RTOCF 0x00000800U
7897 #define USART_ICR_EOBCF 0x00001000U
7898 #define USART_ICR_CMCF 0x00020000U
7899 #define USART_ICR_WUCF 0x00100000U
7901 /******************* Bit definition for USART_RDR register ******************/
7902 #define USART_RDR_RDR 0x01FFU
7904 /******************* Bit definition for USART_TDR register ******************/
7905 #define USART_TDR_TDR 0x01FFU
7907 /******************************************************************************/
7908 /* */
7909 /* Window WATCHDOG */
7910 /* */
7911 /******************************************************************************/
7912 /******************* Bit definition for WWDG_CR register ********************/
7913 #define WWDG_CR_T 0x7FU
7914 #define WWDG_CR_T_0 0x01U
7915 #define WWDG_CR_T_1 0x02U
7916 #define WWDG_CR_T_2 0x04U
7917 #define WWDG_CR_T_3 0x08U
7918 #define WWDG_CR_T_4 0x10U
7919 #define WWDG_CR_T_5 0x20U
7920 #define WWDG_CR_T_6 0x40U
7923 #define WWDG_CR_WDGA 0x80U
7925 /******************* Bit definition for WWDG_CFR register *******************/
7926 #define WWDG_CFR_W 0x007FU
7927 #define WWDG_CFR_W_0 0x0001U
7928 #define WWDG_CFR_W_1 0x0002U
7929 #define WWDG_CFR_W_2 0x0004U
7930 #define WWDG_CFR_W_3 0x0008U
7931 #define WWDG_CFR_W_4 0x0010U
7932 #define WWDG_CFR_W_5 0x0020U
7933 #define WWDG_CFR_W_6 0x0040U
7936 #define WWDG_CFR_WDGTB 0x0180U
7937 #define WWDG_CFR_WDGTB_0 0x0080U
7938 #define WWDG_CFR_WDGTB_1 0x0100U
7941 #define WWDG_CFR_EWI 0x0200U
7943 /******************* Bit definition for WWDG_SR register ********************/
7944 #define WWDG_SR_EWIF 0x01U
7946 /******************************************************************************/
7947 /* */
7948 /* DBG */
7949 /* */
7950 /******************************************************************************/
7951 /******************** Bit definition for DBGMCU_IDCODE register *************/
7952 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
7953 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
7954 
7955 /******************** Bit definition for DBGMCU_CR register *****************/
7956 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
7957 #define DBGMCU_CR_DBG_STOP 0x00000002U
7958 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
7959 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
7960 
7961 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
7962 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U
7963 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U
7965 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
7966 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
7967 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
7968 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
7969 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
7970 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
7971 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
7972 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
7973 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
7974 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
7975 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
7976 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
7977 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
7978 #define DBGMCU_APB1_FZ_DBG_CAN3_STOP 0x00002000U
7979 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
7980 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
7981 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
7982 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
7983 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
7984 
7985 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
7986 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
7987 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
7988 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
7989 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
7990 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
7991 
7992 /******************************************************************************/
7993 /* */
7994 /* Ethernet MAC Registers bits definitions */
7995 /* */
7996 /******************************************************************************/
7997 /* Bit definition for Ethernet MAC Control Register register */
7998 #define ETH_MACCR_WD 0x00800000U /* Watchdog disable */
7999 #define ETH_MACCR_JD 0x00400000U /* Jabber disable */
8000 #define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */
8001 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
8002 #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
8003 #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
8004 #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
8005 #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
8006 #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
8007 #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
8008 #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
8009 #define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */
8010 #define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */
8011 #define ETH_MACCR_ROD 0x00002000U /* Receive own disable */
8012 #define ETH_MACCR_LM 0x00001000U /* loopback mode */
8013 #define ETH_MACCR_DM 0x00000800U /* Duplex mode */
8014 #define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */
8015 #define ETH_MACCR_RD 0x00000200U /* Retry disable */
8016 #define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */
8017 #define ETH_MACCR_BL 0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling
8018  a transmission attempt during retries after a collision: 0 =< r <2^k */
8019 #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
8020 #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
8021 #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
8022 #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
8023 #define ETH_MACCR_DC 0x00000010U /* Defferal check */
8024 #define ETH_MACCR_TE 0x00000008U /* Transmitter enable */
8025 #define ETH_MACCR_RE 0x00000004U /* Receiver enable */
8026 
8027 /* Bit definition for Ethernet MAC Frame Filter Register */
8028 #define ETH_MACFFR_RA 0x80000000U /* Receive all */
8029 #define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */
8030 #define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */
8031 #define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */
8032 #define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */
8033 #define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */
8034 #define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
8035 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
8036 #define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */
8037 #define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */
8038 #define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */
8039 #define ETH_MACFFR_HM 0x00000004U /* Hash multicast */
8040 #define ETH_MACFFR_HU 0x00000002U /* Hash unicast */
8041 #define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */
8042 
8043 /* Bit definition for Ethernet MAC Hash Table High Register */
8044 #define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */
8045 
8046 /* Bit definition for Ethernet MAC Hash Table Low Register */
8047 #define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */
8048 
8049 /* Bit definition for Ethernet MAC MII Address Register */
8050 #define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */
8051 #define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */
8052 #define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */
8053 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
8054 #define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
8055 #define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
8056 #define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
8057 #define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
8058 #define ETH_MACMIIAR_MW 0x00000002U /* MII write */
8059 #define ETH_MACMIIAR_MB 0x00000001U /* MII busy */
8060 
8061 /* Bit definition for Ethernet MAC MII Data Register */
8062 #define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */
8063 
8064 /* Bit definition for Ethernet MAC Flow Control Register */
8065 #define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */
8066 #define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */
8067 #define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */
8068 #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
8069 #define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */
8070 #define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */
8071 #define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */
8072 #define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */
8073 #define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */
8074 #define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */
8075 #define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */
8076 
8077 /* Bit definition for Ethernet MAC VLAN Tag Register */
8078 #define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */
8079 #define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */
8080 
8081 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
8082 #define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */
8083 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
8084  Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
8085 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
8086  Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
8087  Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
8088  Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
8089  Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
8090  RSVD - Filter1 Command - RSVD - Filter0 Command
8091  Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
8092  Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
8093  Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
8094 
8095 /* Bit definition for Ethernet MAC PMT Control and Status Register */
8096 #define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
8097 #define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */
8098 #define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */
8099 #define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */
8100 #define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */
8101 #define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */
8102 #define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */
8103 
8104 /* Bit definition for Ethernet MAC Status Register */
8105 #define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */
8106 #define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */
8107 #define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */
8108 #define ETH_MACSR_MMCS 0x00000010U /* MMC status */
8109 #define ETH_MACSR_PMTS 0x00000008U /* PMT status */
8110 
8111 /* Bit definition for Ethernet MAC Interrupt Mask Register */
8112 #define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */
8113 #define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */
8114 
8115 /* Bit definition for Ethernet MAC Address0 High Register */
8116 #define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */
8117 
8118 /* Bit definition for Ethernet MAC Address0 Low Register */
8119 #define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */
8120 
8121 /* Bit definition for Ethernet MAC Address1 High Register */
8122 #define ETH_MACA1HR_AE 0x80000000U /* Address enable */
8123 #define ETH_MACA1HR_SA 0x40000000U /* Source address */
8124 #define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
8125  #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
8126  #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
8127  #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
8128  #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
8129  #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
8130  #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
8131 #define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */
8132 
8133 /* Bit definition for Ethernet MAC Address1 Low Register */
8134 #define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */
8135 
8136 /* Bit definition for Ethernet MAC Address2 High Register */
8137 #define ETH_MACA2HR_AE 0x80000000U /* Address enable */
8138 #define ETH_MACA2HR_SA 0x40000000U /* Source address */
8139 #define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */
8140  #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
8141  #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
8142  #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
8143  #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
8144  #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
8145  #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
8146 #define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */
8147 
8148 /* Bit definition for Ethernet MAC Address2 Low Register */
8149 #define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */
8150 
8151 /* Bit definition for Ethernet MAC Address3 High Register */
8152 #define ETH_MACA3HR_AE 0x80000000U /* Address enable */
8153 #define ETH_MACA3HR_SA 0x40000000U /* Source address */
8154 #define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */
8155  #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
8156  #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
8157  #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
8158  #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
8159  #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
8160  #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
8161 #define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */
8162 
8163 /* Bit definition for Ethernet MAC Address3 Low Register */
8164 #define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */
8165 
8166 /******************************************************************************/
8167 /* Ethernet MMC Registers bits definition */
8168 /******************************************************************************/
8169 
8170 /* Bit definition for Ethernet MMC Contol Register */
8171 #define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */
8172 #define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */
8173 #define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */
8174 #define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */
8175 #define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */
8176 #define ETH_MMCCR_CR 0x00000001U /* Counters Reset */
8177 
8178 /* Bit definition for Ethernet MMC Receive Interrupt Register */
8179 #define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
8180 #define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
8181 #define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
8182 
8183 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
8184 #define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
8185 #define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
8186 #define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
8187 
8188 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
8189 #define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
8190 #define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
8191 #define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
8192 
8193 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
8194 #define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
8195 #define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
8196 #define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
8197 
8198 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
8199 #define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
8200 
8201 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
8202 #define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
8203 
8204 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
8205 #define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */
8206 
8207 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
8208 #define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */
8209 
8210 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
8211 #define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
8212 
8213 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
8214 #define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */
8215 
8216 /******************************************************************************/
8217 /* Ethernet PTP Registers bits definition */
8218 /******************************************************************************/
8219 
8220 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
8221 #define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */
8222 #define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */
8223 #define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */
8224 #define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */
8225 #define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */
8226 #define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
8227 #define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
8228 #define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */
8229 #define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */
8230 
8231 #define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */
8232 #define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */
8233 #define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */
8234 #define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */
8235 #define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */
8236 #define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */
8237 
8238 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
8239 #define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */
8240 
8241 /* Bit definition for Ethernet PTP Time Stamp High Register */
8242 #define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */
8243 
8244 /* Bit definition for Ethernet PTP Time Stamp Low Register */
8245 #define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */
8246 #define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */
8247 
8248 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
8249 #define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */
8250 
8251 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
8252 #define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */
8253 #define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */
8254 
8255 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
8256 #define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */
8257 
8258 /* Bit definition for Ethernet PTP Target Time High Register */
8259 #define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */
8260 
8261 /* Bit definition for Ethernet PTP Target Time Low Register */
8262 #define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */
8263 
8264 /* Bit definition for Ethernet PTP Time Stamp Status Register */
8265 #define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */
8266 #define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */
8267 
8268 /******************************************************************************/
8269 /* Ethernet DMA Registers bits definition */
8270 /******************************************************************************/
8271 
8272 /* Bit definition for Ethernet DMA Bus Mode Register */
8273 #define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */
8274 #define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */
8275 #define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */
8276 #define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */
8277  #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
8278  #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
8279  #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
8280  #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
8281  #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
8282  #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
8283  #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
8284  #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
8285  #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
8286  #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
8287  #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
8288  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
8289 #define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */
8290 #define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */
8291  #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
8292  #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
8293  #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
8294  #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
8295 #define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */
8296  #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
8297  #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
8298  #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
8299  #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
8300  #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
8301  #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
8302  #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
8303  #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
8304  #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
8305  #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
8306  #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
8307  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
8308 #define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */
8309 #define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */
8310 #define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */
8311 #define ETH_DMABMR_SR 0x00000001U /* Software reset */
8312 
8313 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
8314 #define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */
8315 
8316 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
8317 #define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */
8318 
8319 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
8320 #define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */
8321 
8322 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
8323 #define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */
8324 
8325 /* Bit definition for Ethernet DMA Status Register */
8326 #define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */
8327 #define ETH_DMASR_PMTS 0x10000000U /* PMT status */
8328 #define ETH_DMASR_MMCS 0x08000000U /* MMC status */
8329 #define ETH_DMASR_EBS 0x03800000U /* Error bits status */
8330  /* combination with EBS[2:0] for GetFlagStatus function */
8331  #define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */
8332  #define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
8333  #define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
8334 #define ETH_DMASR_TPS 0x00700000U /* Transmit process state */
8335  #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
8336  #define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */
8337  #define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */
8338  #define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */
8339  #define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */
8340  #define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */
8341 #define ETH_DMASR_RPS 0x000E0000U /* Receive process state */
8342  #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
8343  #define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */
8344  #define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */
8345  #define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */
8346  #define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */
8347  #define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */
8348 #define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */
8349 #define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */
8350 #define ETH_DMASR_ERS 0x00004000U /* Early receive status */
8351 #define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */
8352 #define ETH_DMASR_ETS 0x00000400U /* Early transmit status */
8353 #define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */
8354 #define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */
8355 #define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */
8356 #define ETH_DMASR_RS 0x00000040U /* Receive status */
8357 #define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */
8358 #define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */
8359 #define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */
8360 #define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */
8361 #define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */
8362 #define ETH_DMASR_TS 0x00000001U /* Transmit status */
8363 
8364 /* Bit definition for Ethernet DMA Operation Mode Register */
8365 #define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
8366 #define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */
8367 #define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */
8368 #define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */
8369 #define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */
8370 #define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */
8371  #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
8372  #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
8373  #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
8374  #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
8375  #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
8376  #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
8377  #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
8378  #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
8379 #define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */
8380 #define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */
8381 #define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */
8382 #define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */
8383  #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
8384  #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
8385  #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
8386  #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
8387 #define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */
8388 #define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */
8389 
8390 /* Bit definition for Ethernet DMA Interrupt Enable Register */
8391 #define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */
8392 #define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */
8393 #define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */
8394 #define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */
8395 #define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */
8396 #define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */
8397 #define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */
8398 #define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */
8399 #define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */
8400 #define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */
8401 #define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */
8402 #define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */
8403 #define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */
8404 #define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */
8405 #define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */
8406 
8407 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
8408 #define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */
8409 #define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */
8410 #define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */
8411 #define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */
8412 
8413 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
8414 #define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */
8415 
8416 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
8417 #define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */
8418 
8419 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
8420 #define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */
8421 
8422 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
8423 #define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */
8424 
8425 /******************************************************************************/
8426 /* */
8427 /* USB_OTG */
8428 /* */
8429 /******************************************************************************/
8430 /******************** Bit definition for USB_OTG_GOTGCTL register ********************/
8431 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U
8432 #define USB_OTG_GOTGCTL_SRQ 0x00000002U
8433 #define USB_OTG_GOTGCTL_VBVALOEN 0x00000004U
8434 #define USB_OTG_GOTGCTL_VBVALOVAL 0x00000008U
8435 #define USB_OTG_GOTGCTL_AVALOEN 0x00000010U
8436 #define USB_OTG_GOTGCTL_AVALOVAL 0x00000020U
8437 #define USB_OTG_GOTGCTL_BVALOEN 0x00000040U
8438 #define USB_OTG_GOTGCTL_BVALOVAL 0x00000080U
8439 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U
8440 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U
8441 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U
8442 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U
8443 #define USB_OTG_GOTGCTL_EHEN 0x00001000U
8444 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U
8445 #define USB_OTG_GOTGCTL_DBCT 0x00020000U
8446 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U
8447 #define USB_OTG_GOTGCTL_BSESVLD 0x00080000U
8448 #define USB_OTG_GOTGCTL_OTGVER 0x00100000U
8450 /******************** Bit definition for USB_OTG_HCFG register ********************/
8451 #define USB_OTG_HCFG_FSLSPCS 0x00000003U
8452 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U
8453 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U
8454 #define USB_OTG_HCFG_FSLSS 0x00000004U
8456 /******************** Bit definition for USB_OTG_DCFG register ********************/
8457 #define USB_OTG_DCFG_DSPD 0x00000003U
8458 #define USB_OTG_DCFG_DSPD_0 0x00000001U
8459 #define USB_OTG_DCFG_DSPD_1 0x00000002U
8460 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U
8462 #define USB_OTG_DCFG_DAD 0x000007F0U
8463 #define USB_OTG_DCFG_DAD_0 0x00000010U
8464 #define USB_OTG_DCFG_DAD_1 0x00000020U
8465 #define USB_OTG_DCFG_DAD_2 0x00000040U
8466 #define USB_OTG_DCFG_DAD_3 0x00000080U
8467 #define USB_OTG_DCFG_DAD_4 0x00000100U
8468 #define USB_OTG_DCFG_DAD_5 0x00000200U
8469 #define USB_OTG_DCFG_DAD_6 0x00000400U
8471 #define USB_OTG_DCFG_PFIVL 0x00001800U
8472 #define USB_OTG_DCFG_PFIVL_0 0x00000800U
8473 #define USB_OTG_DCFG_PFIVL_1 0x00001000U
8475 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U
8476 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U
8477 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U
8479 /******************** Bit definition for USB_OTG_PCGCR register ********************/
8480 #define USB_OTG_PCGCR_STPPCLK 0x00000001U
8481 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U
8482 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U
8484 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
8485 #define USB_OTG_GOTGINT_SEDET 0x00000004U
8486 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U
8487 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U
8488 #define USB_OTG_GOTGINT_HNGDET 0x00020000U
8489 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U
8490 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U
8491 #define USB_OTG_GOTGINT_IDCHNG 0x00100000U
8493 /******************** Bit definition for USB_OTG_DCTL register ********************/
8494 #define USB_OTG_DCTL_RWUSIG 0x00000001U
8495 #define USB_OTG_DCTL_SDIS 0x00000002U
8496 #define USB_OTG_DCTL_GINSTS 0x00000004U
8497 #define USB_OTG_DCTL_GONSTS 0x00000008U
8499 #define USB_OTG_DCTL_TCTL 0x00000070U
8500 #define USB_OTG_DCTL_TCTL_0 0x00000010U
8501 #define USB_OTG_DCTL_TCTL_1 0x00000020U
8502 #define USB_OTG_DCTL_TCTL_2 0x00000040U
8503 #define USB_OTG_DCTL_SGINAK 0x00000080U
8504 #define USB_OTG_DCTL_CGINAK 0x00000100U
8505 #define USB_OTG_DCTL_SGONAK 0x00000200U
8506 #define USB_OTG_DCTL_CGONAK 0x00000400U
8507 #define USB_OTG_DCTL_POPRGDNE 0x00000800U
8509 /******************** Bit definition for USB_OTG_HFIR register ********************/
8510 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU
8512 /******************** Bit definition for USB_OTG_HFNUM register ********************/
8513 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU
8514 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U
8516 /******************** Bit definition for USB_OTG_DSTS register ********************/
8517 #define USB_OTG_DSTS_SUSPSTS 0x00000001U
8519 #define USB_OTG_DSTS_ENUMSPD 0x00000006U
8520 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U
8521 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U
8522 #define USB_OTG_DSTS_EERR 0x00000008U
8523 #define USB_OTG_DSTS_FNSOF 0x003FFF00U
8525 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
8526 #define USB_OTG_GAHBCFG_GINT 0x00000001U
8527 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU
8528 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U
8529 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U
8530 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U
8531 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U
8532 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U
8533 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U
8534 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U
8536 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
8537 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U
8538 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U
8539 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U
8540 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U
8541 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U
8542 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U
8543 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U
8544 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U
8545 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U
8546 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U
8547 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U
8548 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U
8549 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U
8550 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U
8551 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U
8552 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U
8553 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U
8554 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U
8555 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U
8556 #define USB_OTG_GUSBCFG_PCCI 0x00800000U
8557 #define USB_OTG_GUSBCFG_PTCI 0x01000000U
8558 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U
8559 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U
8560 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U
8561 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U
8563 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
8564 #define USB_OTG_GRSTCTL_CSRST 0x00000001U
8565 #define USB_OTG_GRSTCTL_HSRST 0x00000002U
8566 #define USB_OTG_GRSTCTL_FCRST 0x00000004U
8567 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U
8568 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U
8569 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U
8570 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U
8571 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U
8572 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U
8573 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U
8574 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U
8575 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U
8576 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U
8578 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
8579 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U
8580 #define USB_OTG_DIEPMSK_EPDM 0x00000002U
8581 #define USB_OTG_DIEPMSK_TOM 0x00000008U
8582 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U
8583 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U
8584 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U
8585 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U
8586 #define USB_OTG_DIEPMSK_BIM 0x00000200U
8588 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
8589 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU
8590 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U
8591 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U
8592 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U
8593 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U
8594 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U
8595 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U
8596 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U
8597 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U
8598 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U
8600 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U
8601 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U
8602 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U
8603 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U
8604 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U
8605 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U
8606 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U
8607 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U
8608 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U
8610 /******************** Bit definition for USB_OTG_HAINT register ********************/
8611 #define USB_OTG_HAINT_HAINT 0x0000FFFFU
8613 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
8614 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U
8615 #define USB_OTG_DOEPMSK_EPDM 0x00000002U
8616 #define USB_OTG_DOEPMSK_STUPM 0x00000008U
8617 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U
8618 #define USB_OTG_DOEPMSK_OTEPSPRM 0x00000020U
8619 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U
8620 #define USB_OTG_DOEPMSK_OPEM 0x00000100U
8621 #define USB_OTG_DOEPMSK_BOIM 0x00000200U
8623 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
8624 #define USB_OTG_GINTSTS_CMOD 0x00000001U
8625 #define USB_OTG_GINTSTS_MMIS 0x00000002U
8626 #define USB_OTG_GINTSTS_OTGINT 0x00000004U
8627 #define USB_OTG_GINTSTS_SOF 0x00000008U
8628 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U
8629 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U
8630 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U
8631 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U
8632 #define USB_OTG_GINTSTS_ESUSP 0x00000400U
8633 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U
8634 #define USB_OTG_GINTSTS_USBRST 0x00001000U
8635 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U
8636 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U
8637 #define USB_OTG_GINTSTS_EOPF 0x00008000U
8638 #define USB_OTG_GINTSTS_IEPINT 0x00040000U
8639 #define USB_OTG_GINTSTS_OEPINT 0x00080000U
8640 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U
8641 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U
8642 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U
8643 #define USB_OTG_GINTSTS_RSTDET 0x00800000U
8644 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U
8645 #define USB_OTG_GINTSTS_HCINT 0x02000000U
8646 #define USB_OTG_GINTSTS_PTXFE 0x04000000U
8647 #define USB_OTG_GINTSTS_LPMINT 0x08000000U
8648 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U
8649 #define USB_OTG_GINTSTS_DISCINT 0x20000000U
8650 #define USB_OTG_GINTSTS_SRQINT 0x40000000U
8651 #define USB_OTG_GINTSTS_WKUINT 0x80000000U
8653 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
8654 #define USB_OTG_GINTMSK_MMISM 0x00000002U
8655 #define USB_OTG_GINTMSK_OTGINT 0x00000004U
8656 #define USB_OTG_GINTMSK_SOFM 0x00000008U
8657 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U
8658 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U
8659 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U
8660 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U
8661 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U
8662 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U
8663 #define USB_OTG_GINTMSK_USBRST 0x00001000U
8664 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U
8665 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U
8666 #define USB_OTG_GINTMSK_EOPFM 0x00008000U
8667 #define USB_OTG_GINTMSK_EPMISM 0x00020000U
8668 #define USB_OTG_GINTMSK_IEPINT 0x00040000U
8669 #define USB_OTG_GINTMSK_OEPINT 0x00080000U
8670 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U
8671 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U
8672 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U
8673 #define USB_OTG_GINTMSK_RSTDEM 0x00800000U
8674 #define USB_OTG_GINTMSK_PRTIM 0x01000000U
8675 #define USB_OTG_GINTMSK_HCIM 0x02000000U
8676 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U
8677 #define USB_OTG_GINTMSK_LPMINTM 0x08000000U
8678 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U
8679 #define USB_OTG_GINTMSK_DISCINT 0x20000000U
8680 #define USB_OTG_GINTMSK_SRQIM 0x40000000U
8681 #define USB_OTG_GINTMSK_WUIM 0x80000000U
8683 /******************** Bit definition for USB_OTG_DAINT register ********************/
8684 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU
8685 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U
8687 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
8688 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU
8690 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
8691 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU
8692 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U
8693 #define USB_OTG_GRXSTSP_DPID 0x00018000U
8694 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U
8696 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
8697 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU
8698 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U
8700 /******************** Bit definition for OTG register ********************/
8701 
8702 #define USB_OTG_CHNUM 0x0000000FU
8703 #define USB_OTG_CHNUM_0 0x00000001U
8704 #define USB_OTG_CHNUM_1 0x00000002U
8705 #define USB_OTG_CHNUM_2 0x00000004U
8706 #define USB_OTG_CHNUM_3 0x00000008U
8707 #define USB_OTG_BCNT 0x00007FF0U
8709 #define USB_OTG_DPID 0x00018000U
8710 #define USB_OTG_DPID_0 0x00008000U
8711 #define USB_OTG_DPID_1 0x00010000U
8713 #define USB_OTG_PKTSTS 0x001E0000U
8714 #define USB_OTG_PKTSTS_0 0x00020000U
8715 #define USB_OTG_PKTSTS_1 0x00040000U
8716 #define USB_OTG_PKTSTS_2 0x00080000U
8717 #define USB_OTG_PKTSTS_3 0x00100000U
8719 #define USB_OTG_EPNUM 0x0000000FU
8720 #define USB_OTG_EPNUM_0 0x00000001U
8721 #define USB_OTG_EPNUM_1 0x00000002U
8722 #define USB_OTG_EPNUM_2 0x00000004U
8723 #define USB_OTG_EPNUM_3 0x00000008U
8725 #define USB_OTG_FRMNUM 0x01E00000U
8726 #define USB_OTG_FRMNUM_0 0x00200000U
8727 #define USB_OTG_FRMNUM_1 0x00400000U
8728 #define USB_OTG_FRMNUM_2 0x00800000U
8729 #define USB_OTG_FRMNUM_3 0x01000000U
8731 /******************** Bit definition for OTG register ********************/
8732 
8733 #define USB_OTG_CHNUM 0x0000000FU
8734 #define USB_OTG_CHNUM_0 0x00000001U
8735 #define USB_OTG_CHNUM_1 0x00000002U
8736 #define USB_OTG_CHNUM_2 0x00000004U
8737 #define USB_OTG_CHNUM_3 0x00000008U
8738 #define USB_OTG_BCNT 0x00007FF0U
8740 #define USB_OTG_DPID 0x00018000U
8741 #define USB_OTG_DPID_0 0x00008000U
8742 #define USB_OTG_DPID_1 0x00010000U
8744 #define USB_OTG_PKTSTS 0x001E0000U
8745 #define USB_OTG_PKTSTS_0 0x00020000U
8746 #define USB_OTG_PKTSTS_1 0x00040000U
8747 #define USB_OTG_PKTSTS_2 0x00080000U
8748 #define USB_OTG_PKTSTS_3 0x00100000U
8750 #define USB_OTG_EPNUM 0x0000000FU
8751 #define USB_OTG_EPNUM_0 0x00000001U
8752 #define USB_OTG_EPNUM_1 0x00000002U
8753 #define USB_OTG_EPNUM_2 0x00000004U
8754 #define USB_OTG_EPNUM_3 0x00000008U
8756 #define USB_OTG_FRMNUM 0x01E00000U
8757 #define USB_OTG_FRMNUM_0 0x00200000U
8758 #define USB_OTG_FRMNUM_1 0x00400000U
8759 #define USB_OTG_FRMNUM_2 0x00800000U
8760 #define USB_OTG_FRMNUM_3 0x01000000U
8762 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
8763 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU
8765 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
8766 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU
8768 /******************** Bit definition for OTG register ********************/
8769 #define USB_OTG_NPTXFSA 0x0000FFFFU
8770 #define USB_OTG_NPTXFD 0xFFFF0000U
8771 #define USB_OTG_TX0FSA 0x0000FFFFU
8772 #define USB_OTG_TX0FD 0xFFFF0000U
8774 /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
8775 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU
8777 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
8778 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU
8780 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U
8781 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U
8782 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U
8783 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U
8784 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U
8785 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U
8786 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U
8787 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U
8788 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U
8790 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U
8791 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U
8792 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U
8793 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U
8794 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U
8795 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U
8796 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U
8797 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U
8799 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
8800 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U
8801 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U
8803 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU
8804 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U
8805 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U
8806 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U
8807 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U
8808 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U
8809 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U
8810 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U
8811 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U
8812 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U
8813 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U
8815 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U
8816 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U
8817 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U
8818 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U
8819 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U
8820 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U
8821 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U
8822 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U
8823 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U
8824 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U
8825 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U
8827 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
8828 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU
8830 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
8831 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U
8832 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U
8834 /******************** Bit definition for USB_OTG_GCCFG register ********************/
8835 #define USB_OTG_GCCFG_PWRDWN 0x00010000U
8836 #define USB_OTG_GCCFG_VBDEN 0x00200000U
8838 /******************** Bit definition for USB_OTG_GPWRDN) register ********************/
8839 #define USB_OTG_GPWRDN_ADPMEN 0x00000001U
8840 #define USB_OTG_GPWRDN_ADPIF 0x00800000U
8842 /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
8843 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U
8844 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U
8846 /******************** Bit definition for USB_OTG_CID register ********************/
8847 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU
8849 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
8850 #define USB_OTG_GLPMCFG_LPMEN 0x00000001U
8851 #define USB_OTG_GLPMCFG_LPMACK 0x00000002U
8852 #define USB_OTG_GLPMCFG_BESL 0x0000003CU
8853 #define USB_OTG_GLPMCFG_REMWAKE 0x00000040U
8854 #define USB_OTG_GLPMCFG_L1SSEN 0x00000080U
8855 #define USB_OTG_GLPMCFG_BESLTHRS 0x00000F00U
8856 #define USB_OTG_GLPMCFG_L1DSEN 0x00001000U
8857 #define USB_OTG_GLPMCFG_LPMRSP 0x00006000U
8858 #define USB_OTG_GLPMCFG_SLPSTS 0x00008000U
8859 #define USB_OTG_GLPMCFG_L1RSMOK 0x00010000U
8860 #define USB_OTG_GLPMCFG_LPMCHIDX 0x001E0000U
8861 #define USB_OTG_GLPMCFG_LPMRCNT 0x00E00000U
8862 #define USB_OTG_GLPMCFG_SNDLPM 0x01000000U
8863 #define USB_OTG_GLPMCFG_LPMRCNTSTS 0x0E000000U
8864 #define USB_OTG_GLPMCFG_ENBESL 0x10000000U
8866 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
8867 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U
8868 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U
8869 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U
8870 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U
8871 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U
8872 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U
8873 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U
8874 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U
8875 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U
8877 /******************** Bit definition for USB_OTG_HPRT register ********************/
8878 #define USB_OTG_HPRT_PCSTS 0x00000001U
8879 #define USB_OTG_HPRT_PCDET 0x00000002U
8880 #define USB_OTG_HPRT_PENA 0x00000004U
8881 #define USB_OTG_HPRT_PENCHNG 0x00000008U
8882 #define USB_OTG_HPRT_POCA 0x00000010U
8883 #define USB_OTG_HPRT_POCCHNG 0x00000020U
8884 #define USB_OTG_HPRT_PRES 0x00000040U
8885 #define USB_OTG_HPRT_PSUSP 0x00000080U
8886 #define USB_OTG_HPRT_PRST 0x00000100U
8888 #define USB_OTG_HPRT_PLSTS 0x00000C00U
8889 #define USB_OTG_HPRT_PLSTS_0 0x00000400U
8890 #define USB_OTG_HPRT_PLSTS_1 0x00000800U
8891 #define USB_OTG_HPRT_PPWR 0x00001000U
8893 #define USB_OTG_HPRT_PTCTL 0x0001E000U
8894 #define USB_OTG_HPRT_PTCTL_0 0x00002000U
8895 #define USB_OTG_HPRT_PTCTL_1 0x00004000U
8896 #define USB_OTG_HPRT_PTCTL_2 0x00008000U
8897 #define USB_OTG_HPRT_PTCTL_3 0x00010000U
8899 #define USB_OTG_HPRT_PSPD 0x00060000U
8900 #define USB_OTG_HPRT_PSPD_0 0x00020000U
8901 #define USB_OTG_HPRT_PSPD_1 0x00040000U
8903 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
8904 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U
8905 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U
8906 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U
8907 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U
8908 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U
8909 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U
8910 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U
8911 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U
8912 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U
8913 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U
8914 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U
8916 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
8917 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU
8918 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U
8920 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
8921 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU
8922 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U
8923 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U
8924 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U
8926 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U
8927 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U
8928 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U
8929 #define USB_OTG_DIEPCTL_STALL 0x00200000U
8931 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U
8932 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U
8933 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U
8934 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U
8935 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U
8936 #define USB_OTG_DIEPCTL_CNAK 0x04000000U
8937 #define USB_OTG_DIEPCTL_SNAK 0x08000000U
8938 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U
8939 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U
8940 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U
8941 #define USB_OTG_DIEPCTL_EPENA 0x80000000U
8943 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
8944 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU
8946 #define USB_OTG_HCCHAR_EPNUM 0x00007800U
8947 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U
8948 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U
8949 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U
8950 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U
8951 #define USB_OTG_HCCHAR_EPDIR 0x00008000U
8952 #define USB_OTG_HCCHAR_LSDEV 0x00020000U
8954 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U
8955 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U
8956 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U
8958 #define USB_OTG_HCCHAR_MC 0x00300000U
8959 #define USB_OTG_HCCHAR_MC_0 0x00100000U
8960 #define USB_OTG_HCCHAR_MC_1 0x00200000U
8962 #define USB_OTG_HCCHAR_DAD 0x1FC00000U
8963 #define USB_OTG_HCCHAR_DAD_0 0x00400000U
8964 #define USB_OTG_HCCHAR_DAD_1 0x00800000U
8965 #define USB_OTG_HCCHAR_DAD_2 0x01000000U
8966 #define USB_OTG_HCCHAR_DAD_3 0x02000000U
8967 #define USB_OTG_HCCHAR_DAD_4 0x04000000U
8968 #define USB_OTG_HCCHAR_DAD_5 0x08000000U
8969 #define USB_OTG_HCCHAR_DAD_6 0x10000000U
8970 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U
8971 #define USB_OTG_HCCHAR_CHDIS 0x40000000U
8972 #define USB_OTG_HCCHAR_CHENA 0x80000000U
8974 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
8975 
8976 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU
8977 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U
8978 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U
8979 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U
8980 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U
8981 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U
8982 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U
8983 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U
8985 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U
8986 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U
8987 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U
8988 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U
8989 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U
8990 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U
8991 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U
8992 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U
8994 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U
8995 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U
8996 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U
8997 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U
8998 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U
9000 /******************** Bit definition for USB_OTG_HCINT register ********************/
9001 #define USB_OTG_HCINT_XFRC 0x00000001U
9002 #define USB_OTG_HCINT_CHH 0x00000002U
9003 #define USB_OTG_HCINT_AHBERR 0x00000004U
9004 #define USB_OTG_HCINT_STALL 0x00000008U
9005 #define USB_OTG_HCINT_NAK 0x00000010U
9006 #define USB_OTG_HCINT_ACK 0x00000020U
9007 #define USB_OTG_HCINT_NYET 0x00000040U
9008 #define USB_OTG_HCINT_TXERR 0x00000080U
9009 #define USB_OTG_HCINT_BBERR 0x00000100U
9010 #define USB_OTG_HCINT_FRMOR 0x00000200U
9011 #define USB_OTG_HCINT_DTERR 0x00000400U
9013 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
9014 #define USB_OTG_DIEPINT_XFRC 0x00000001U
9015 #define USB_OTG_DIEPINT_EPDISD 0x00000002U
9016 #define USB_OTG_DIEPINT_TOC 0x00000008U
9017 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U
9018 #define USB_OTG_DIEPINT_INEPNE 0x00000040U
9019 #define USB_OTG_DIEPINT_TXFE 0x00000080U
9020 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U
9021 #define USB_OTG_DIEPINT_BNA 0x00000200U
9022 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U
9023 #define USB_OTG_DIEPINT_BERR 0x00001000U
9024 #define USB_OTG_DIEPINT_NAK 0x00002000U
9026 /******************** Bit definition for USB_OTG_HCINTMSK register ********************/
9027 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U
9028 #define USB_OTG_HCINTMSK_CHHM 0x00000002U
9029 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U
9030 #define USB_OTG_HCINTMSK_STALLM 0x00000008U
9031 #define USB_OTG_HCINTMSK_NAKM 0x00000010U
9032 #define USB_OTG_HCINTMSK_ACKM 0x00000020U
9033 #define USB_OTG_HCINTMSK_NYET 0x00000040U
9034 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U
9035 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U
9036 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U
9037 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U
9039 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
9040 
9041 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU
9042 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U
9043 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U
9044 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
9045 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU
9046 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U
9047 #define USB_OTG_HCTSIZ_DOPING 0x80000000U
9048 #define USB_OTG_HCTSIZ_DPID 0x60000000U
9049 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U
9050 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U
9052 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
9053 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU
9055 /******************** Bit definition for USB_OTG_HCDMA register ********************/
9056 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU
9058 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
9059 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU
9061 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
9062 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU
9063 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U
9065 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
9066 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU
9067 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U
9068 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U
9069 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U
9070 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U
9071 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U
9072 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U
9073 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U
9074 #define USB_OTG_DOEPCTL_SNPM 0x00100000U
9075 #define USB_OTG_DOEPCTL_STALL 0x00200000U
9076 #define USB_OTG_DOEPCTL_CNAK 0x04000000U
9077 #define USB_OTG_DOEPCTL_SNAK 0x08000000U
9078 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U
9079 #define USB_OTG_DOEPCTL_EPENA 0x80000000U
9081 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
9082 #define USB_OTG_DOEPINT_XFRC 0x00000001U
9083 #define USB_OTG_DOEPINT_EPDISD 0x00000002U
9084 #define USB_OTG_DOEPINT_STUP 0x00000008U
9085 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U
9086 #define USB_OTG_DOEPINT_OTEPSPR 0x00000020U
9087 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U
9088 #define USB_OTG_DOEPINT_NYET 0x00004000U
9090 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
9091 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU
9092 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U
9094 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U
9095 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U
9096 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U
9098 /******************** Bit definition for PCGCCTL register ********************/
9099 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U
9100 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U
9101 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U
9104 /******************************************************************************/
9105 /* */
9106 /* MDIOS */
9107 /* */
9108 /******************************************************************************/
9109 /******************** Bit definition for MDIOS_CR register *******************/
9110 #define MDIOS_CR_EN 0x00000001U
9111 #define MDIOS_CR_WRIE 0x00000002U
9112 #define MDIOS_CR_RDIE 0x00000004U
9113 #define MDIOS_CR_EIE 0x00000008U
9114 #define MDIOS_CR_DPC 0x00000080U
9115 #define MDIOS_CR_PORT_ADDRESS 0x00001F00U
9116 #define MDIOS_CR_PORT_ADDRESS_0 0x00000100U
9117 #define MDIOS_CR_PORT_ADDRESS_1 0x00000200U
9118 #define MDIOS_CR_PORT_ADDRESS_2 0x00000400U
9119 #define MDIOS_CR_PORT_ADDRESS_3 0x00000800U
9120 #define MDIOS_CR_PORT_ADDRESS_4 0x00001000U
9122 /******************** Bit definition for MDIOS_WRFR register *******************/
9123 #define MDIOS_WRFR_WRF 0xFFFFFFFFU
9125 /******************** Bit definition for MDIOS_CWRFR register *******************/
9126 #define MDIOS_CWRFR_CWRF 0xFFFFFFFFU
9128 /******************** Bit definition for MDIOS_RDFR register *******************/
9129 #define MDIOS_RDFR_RDF 0xFFFFFFFFU
9131 /******************** Bit definition for MDIOS_CRDFR register *******************/
9132 #define MDIOS_CRDFR_CRDF 0xFFFFFFFFU
9134 /******************** Bit definition for MDIOS_SR register *******************/
9135 #define MDIOS_SR_PERF 0x00000001U
9136 #define MDIOS_SR_SERF 0x00000002U
9137 #define MDIOS_SR_TERF 0x00000004U
9139 /******************** Bit definition for MDIOS_CLRFR register *******************/
9140 #define MDIOS_CLRFR_CPERF 0x00000001U
9141 #define MDIOS_CLRFR_CSERF 0x00000002U
9142 #define MDIOS_CLRFR_CTERF 0x00000004U
9156 /******************************* ADC Instances ********************************/
9157 #define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
9158  ((__INSTANCE__) == ADC2) || \
9159  ((__INSTANCE__) == ADC3))
9160 
9161 /******************************* CAN Instances ********************************/
9162 #define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
9163  ((__INSTANCE__) == CAN2) || \
9164  ((__INSTANCE__) == CAN3))
9165 /******************************* CRC Instances ********************************/
9166 #define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
9167 
9168 /******************************* DAC Instances ********************************/
9169 #define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)
9170 
9171 /******************************* DCMI Instances *******************************/
9172 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
9173 
9174 /****************************** DFSDM Instances *******************************/
9175 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
9176  ((INSTANCE) == DFSDM1_Filter1) || \
9177  ((INSTANCE) == DFSDM1_Filter2) || \
9178  ((INSTANCE) == DFSDM1_Filter3))
9179 
9180 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
9181  ((INSTANCE) == DFSDM1_Channel1) || \
9182  ((INSTANCE) == DFSDM1_Channel2) || \
9183  ((INSTANCE) == DFSDM1_Channel3) || \
9184  ((INSTANCE) == DFSDM1_Channel4) || \
9185  ((INSTANCE) == DFSDM1_Channel5) || \
9186  ((INSTANCE) == DFSDM1_Channel6) || \
9187  ((INSTANCE) == DFSDM1_Channel7))
9188 
9189 /******************************* DMA2D Instances *******************************/
9190 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
9191 
9192 /******************************** DMA Instances *******************************/
9193 #define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
9194  ((__INSTANCE__) == DMA1_Stream1) || \
9195  ((__INSTANCE__) == DMA1_Stream2) || \
9196  ((__INSTANCE__) == DMA1_Stream3) || \
9197  ((__INSTANCE__) == DMA1_Stream4) || \
9198  ((__INSTANCE__) == DMA1_Stream5) || \
9199  ((__INSTANCE__) == DMA1_Stream6) || \
9200  ((__INSTANCE__) == DMA1_Stream7) || \
9201  ((__INSTANCE__) == DMA2_Stream0) || \
9202  ((__INSTANCE__) == DMA2_Stream1) || \
9203  ((__INSTANCE__) == DMA2_Stream2) || \
9204  ((__INSTANCE__) == DMA2_Stream3) || \
9205  ((__INSTANCE__) == DMA2_Stream4) || \
9206  ((__INSTANCE__) == DMA2_Stream5) || \
9207  ((__INSTANCE__) == DMA2_Stream6) || \
9208  ((__INSTANCE__) == DMA2_Stream7))
9209 
9210 /******************************* GPIO Instances *******************************/
9211 #define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
9212  ((__INSTANCE__) == GPIOB) || \
9213  ((__INSTANCE__) == GPIOC) || \
9214  ((__INSTANCE__) == GPIOD) || \
9215  ((__INSTANCE__) == GPIOE) || \
9216  ((__INSTANCE__) == GPIOF) || \
9217  ((__INSTANCE__) == GPIOG) || \
9218  ((__INSTANCE__) == GPIOH) || \
9219  ((__INSTANCE__) == GPIOI) || \
9220  ((__INSTANCE__) == GPIOJ) || \
9221  ((__INSTANCE__) == GPIOK))
9222 
9223 #define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
9224  ((__INSTANCE__) == GPIOB) || \
9225  ((__INSTANCE__) == GPIOC) || \
9226  ((__INSTANCE__) == GPIOD) || \
9227  ((__INSTANCE__) == GPIOE) || \
9228  ((__INSTANCE__) == GPIOF) || \
9229  ((__INSTANCE__) == GPIOG) || \
9230  ((__INSTANCE__) == GPIOH) || \
9231  ((__INSTANCE__) == GPIOI) || \
9232  ((__INSTANCE__) == GPIOJ) || \
9233  ((__INSTANCE__) == GPIOK))
9234 
9235 /****************************** CEC Instances *********************************/
9236 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
9237 
9238 /****************************** QSPI Instances *********************************/
9239 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
9240 
9241 
9242 /******************************** I2C Instances *******************************/
9243 #define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
9244  ((__INSTANCE__) == I2C2) || \
9245  ((__INSTANCE__) == I2C3) || \
9246  ((__INSTANCE__) == I2C4))
9247 
9248 /******************************** I2S Instances *******************************/
9249 #define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
9250  ((__INSTANCE__) == SPI2) || \
9251  ((__INSTANCE__) == SPI3))
9252 
9253 /******************************* LPTIM Instances ********************************/
9254 #define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
9255 
9256 
9257 /****************************** MDIOS Instances ********************************/
9258 #define IS_MDIOS_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == MDIOS)
9259 
9260 
9261 /******************************* RNG Instances ********************************/
9262 #define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
9263 
9264 /****************************** RTC Instances *********************************/
9265 #define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)
9266 
9267 /******************************* SAI Instances ********************************/
9268 #define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
9269  ((__PERIPH__) == SAI1_Block_B) || \
9270  ((__PERIPH__) == SAI2_Block_A) || \
9271  ((__PERIPH__) == SAI2_Block_B))
9272 /* Legacy define */
9273 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
9274 
9275 /******************************** SDMMC Instances *******************************/
9276 #define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SDMMC1) || \
9277  ((__INSTANCE__) == SDMMC2))
9278 
9279 /****************************** SPDIFRX Instances *********************************/
9280 #define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
9281 
9282 /******************************** SPI Instances *******************************/
9283 #define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
9284  ((__INSTANCE__) == SPI2) || \
9285  ((__INSTANCE__) == SPI3) || \
9286  ((__INSTANCE__) == SPI4) || \
9287  ((__INSTANCE__) == SPI5) || \
9288  ((__INSTANCE__) == SPI6))
9289 
9290 /****************** TIM Instances : All supported instances *******************/
9291 #define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9292  ((__INSTANCE__) == TIM2) || \
9293  ((__INSTANCE__) == TIM3) || \
9294  ((__INSTANCE__) == TIM4) || \
9295  ((__INSTANCE__) == TIM5) || \
9296  ((__INSTANCE__) == TIM6) || \
9297  ((__INSTANCE__) == TIM7) || \
9298  ((__INSTANCE__) == TIM8) || \
9299  ((__INSTANCE__) == TIM9) || \
9300  ((__INSTANCE__) == TIM10) || \
9301  ((__INSTANCE__) == TIM11) || \
9302  ((__INSTANCE__) == TIM12) || \
9303  ((__INSTANCE__) == TIM13) || \
9304  ((__INSTANCE__) == TIM14))
9305 
9306 /************* TIM Instances : at least 1 capture/compare channel *************/
9307 #define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9308  ((__INSTANCE__) == TIM2) || \
9309  ((__INSTANCE__) == TIM3) || \
9310  ((__INSTANCE__) == TIM4) || \
9311  ((__INSTANCE__) == TIM5) || \
9312  ((__INSTANCE__) == TIM8) || \
9313  ((__INSTANCE__) == TIM9) || \
9314  ((__INSTANCE__) == TIM10) || \
9315  ((__INSTANCE__) == TIM11) || \
9316  ((__INSTANCE__) == TIM12) || \
9317  ((__INSTANCE__) == TIM13) || \
9318  ((__INSTANCE__) == TIM14))
9319 
9320 /************ TIM Instances : at least 2 capture/compare channels *************/
9321 #define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9322  ((__INSTANCE__) == TIM2) || \
9323  ((__INSTANCE__) == TIM3) || \
9324  ((__INSTANCE__) == TIM4) || \
9325  ((__INSTANCE__) == TIM5) || \
9326  ((__INSTANCE__) == TIM8) || \
9327  ((__INSTANCE__) == TIM9) || \
9328  ((__INSTANCE__) == TIM12))
9329 
9330 /************ TIM Instances : at least 3 capture/compare channels *************/
9331 #define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9332  ((__INSTANCE__) == TIM2) || \
9333  ((__INSTANCE__) == TIM3) || \
9334  ((__INSTANCE__) == TIM4) || \
9335  ((__INSTANCE__) == TIM5) || \
9336  ((__INSTANCE__) == TIM8))
9337 
9338 /************ TIM Instances : at least 4 capture/compare channels *************/
9339 #define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9340  ((__INSTANCE__) == TIM2) || \
9341  ((__INSTANCE__) == TIM3) || \
9342  ((__INSTANCE__) == TIM4) || \
9343  ((__INSTANCE__) == TIM5) || \
9344  ((__INSTANCE__) == TIM8))
9345 
9346 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
9347 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
9348  (((__INSTANCE__) == TIM1) || \
9349  ((__INSTANCE__) == TIM8))
9350 
9351 /****************** TIM Instances : supporting OCxREF clear *******************/
9352 #define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
9353  (((__INSTANCE__) == TIM1) || \
9354  ((__INSTANCE__) == TIM2) || \
9355  ((__INSTANCE__) == TIM3) || \
9356  ((__INSTANCE__) == TIM4) || \
9357  ((__INSTANCE__) == TIM8))
9358 
9359 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
9360 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
9361  (((__INSTANCE__) == TIM1) || \
9362  ((__INSTANCE__) == TIM2) || \
9363  ((__INSTANCE__) == TIM3) || \
9364  ((__INSTANCE__) == TIM4) || \
9365  ((__INSTANCE__) == TIM5) || \
9366  ((__INSTANCE__) == TIM8))
9367 
9368 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
9369 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
9370  (((__INSTANCE__) == TIM1) || \
9371  ((__INSTANCE__) == TIM2) || \
9372  ((__INSTANCE__) == TIM3) || \
9373  ((__INSTANCE__) == TIM4) || \
9374  ((__INSTANCE__) == TIM5) || \
9375  ((__INSTANCE__) == TIM8))
9376 /****************** TIM Instances : at least 5 capture/compare channels *******/
9377 #define IS_TIM_CC5_INSTANCE(__INSTANCE__)\
9378  (((__INSTANCE__) == TIM1) || \
9379  ((__INSTANCE__) == TIM8) )
9380 
9381 /****************** TIM Instances : at least 6 capture/compare channels *******/
9382 #define IS_TIM_CC6_INSTANCE(__INSTANCE__)\
9383  (((__INSTANCE__) == TIM1) || \
9384  ((__INSTANCE__) == TIM8))
9385 
9386 
9387 /******************** TIM Instances : Advanced-control timers *****************/
9388 #define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9389  ((__INSTANCE__) == TIM8))
9390 
9391 /****************** TIM Instances : supporting 2 break inputs *****************/
9392 #define IS_TIM_BREAK_INSTANCE(__INSTANCE__)\
9393  (((__INSTANCE__) == TIM1) || \
9394  ((__INSTANCE__) == TIM8))
9395 
9396 /******************* TIM Instances : Timer input XOR function *****************/
9397 #define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9398  ((__INSTANCE__) == TIM2) || \
9399  ((__INSTANCE__) == TIM3) || \
9400  ((__INSTANCE__) == TIM4) || \
9401  ((__INSTANCE__) == TIM5) || \
9402  ((__INSTANCE__) == TIM8))
9403 
9404 /****************** TIM Instances : DMA requests generation (UDE) *************/
9405 #define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9406  ((__INSTANCE__) == TIM2) || \
9407  ((__INSTANCE__) == TIM3) || \
9408  ((__INSTANCE__) == TIM4) || \
9409  ((__INSTANCE__) == TIM5) || \
9410  ((__INSTANCE__) == TIM6) || \
9411  ((__INSTANCE__) == TIM7) || \
9412  ((__INSTANCE__) == TIM8))
9413 
9414 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
9415 #define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9416  ((__INSTANCE__) == TIM2) || \
9417  ((__INSTANCE__) == TIM3) || \
9418  ((__INSTANCE__) == TIM4) || \
9419  ((__INSTANCE__) == TIM5) || \
9420  ((__INSTANCE__) == TIM8))
9421 
9422 /************ TIM Instances : DMA requests generation (COMDE) *****************/
9423 #define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9424  ((__INSTANCE__) == TIM2) || \
9425  ((__INSTANCE__) == TIM3) || \
9426  ((__INSTANCE__) == TIM4) || \
9427  ((__INSTANCE__) == TIM5) || \
9428  ((__INSTANCE__) == TIM8))
9429 
9430 /******************** TIM Instances : DMA burst feature ***********************/
9431 #define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9432  ((__INSTANCE__) == TIM2) || \
9433  ((__INSTANCE__) == TIM3) || \
9434  ((__INSTANCE__) == TIM4) || \
9435  ((__INSTANCE__) == TIM5) || \
9436  ((__INSTANCE__) == TIM8))
9437 
9438 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
9439 #define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9440  ((__INSTANCE__) == TIM2) || \
9441  ((__INSTANCE__) == TIM3) || \
9442  ((__INSTANCE__) == TIM4) || \
9443  ((__INSTANCE__) == TIM5) || \
9444  ((__INSTANCE__) == TIM6) || \
9445  ((__INSTANCE__) == TIM7) || \
9446  ((__INSTANCE__) == TIM8) || \
9447  ((__INSTANCE__) == TIM13) || \
9448  ((__INSTANCE__) == TIM14))
9449 
9450 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
9451 #define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9452  ((__INSTANCE__) == TIM2) || \
9453  ((__INSTANCE__) == TIM3) || \
9454  ((__INSTANCE__) == TIM4) || \
9455  ((__INSTANCE__) == TIM5) || \
9456  ((__INSTANCE__) == TIM8) || \
9457  ((__INSTANCE__) == TIM9) || \
9458  ((__INSTANCE__) == TIM12))
9459 
9460 /********************** TIM Instances : 32 bit Counter ************************/
9461 #define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)(((__INSTANCE__) == TIM2) || \
9462  ((__INSTANCE__) == TIM5))
9463 
9464 /***************** TIM Instances : external trigger input available ************/
9465 #define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9466  ((__INSTANCE__) == TIM2) || \
9467  ((__INSTANCE__) == TIM3) || \
9468  ((__INSTANCE__) == TIM4) || \
9469  ((__INSTANCE__) == TIM5) || \
9470  ((__INSTANCE__) == TIM8))
9471 
9472 /****************** TIM Instances : remapping capability **********************/
9473 #define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
9474  ((__INSTANCE__) == TIM5) || \
9475  ((__INSTANCE__) == TIM11))
9476 
9477 /******************* TIM Instances : output(s) available **********************/
9478 #define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
9479  ((((__INSTANCE__) == TIM1) && \
9480  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9481  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9482  ((__CHANNEL__) == TIM_CHANNEL_3) || \
9483  ((__CHANNEL__) == TIM_CHANNEL_4))) \
9484  || \
9485  (((__INSTANCE__) == TIM2) && \
9486  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9487  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9488  ((__CHANNEL__) == TIM_CHANNEL_3) || \
9489  ((__CHANNEL__) == TIM_CHANNEL_4))) \
9490  || \
9491  (((__INSTANCE__) == TIM3) && \
9492  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9493  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9494  ((__CHANNEL__) == TIM_CHANNEL_3) || \
9495  ((__CHANNEL__) == TIM_CHANNEL_4))) \
9496  || \
9497  (((__INSTANCE__) == TIM4) && \
9498  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9499  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9500  ((__CHANNEL__) == TIM_CHANNEL_3) || \
9501  ((__CHANNEL__) == TIM_CHANNEL_4))) \
9502  || \
9503  (((__INSTANCE__) == TIM5) && \
9504  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9505  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9506  ((__CHANNEL__) == TIM_CHANNEL_3) || \
9507  ((__CHANNEL__) == TIM_CHANNEL_4))) \
9508  || \
9509  (((__INSTANCE__) == TIM8) && \
9510  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9511  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9512  ((__CHANNEL__) == TIM_CHANNEL_3) || \
9513  ((__CHANNEL__) == TIM_CHANNEL_4))) \
9514  || \
9515  (((__INSTANCE__) == TIM9) && \
9516  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9517  ((__CHANNEL__) == TIM_CHANNEL_2))) \
9518  || \
9519  (((__INSTANCE__) == TIM10) && \
9520  (((__CHANNEL__) == TIM_CHANNEL_1))) \
9521  || \
9522  (((__INSTANCE__) == TIM11) && \
9523  (((__CHANNEL__) == TIM_CHANNEL_1))) \
9524  || \
9525  (((__INSTANCE__) == TIM12) && \
9526  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9527  ((__CHANNEL__) == TIM_CHANNEL_2))) \
9528  || \
9529  (((__INSTANCE__) == TIM13) && \
9530  (((__CHANNEL__) == TIM_CHANNEL_1))) \
9531  || \
9532  (((__INSTANCE__) == TIM14) && \
9533  (((__CHANNEL__) == TIM_CHANNEL_1))))
9534 
9535 /************ TIM Instances : complementary output(s) available ***************/
9536 #define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
9537  ((((__INSTANCE__) == TIM1) && \
9538  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9539  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9540  ((__CHANNEL__) == TIM_CHANNEL_3))) \
9541  || \
9542  (((__INSTANCE__) == TIM8) && \
9543  (((__CHANNEL__) == TIM_CHANNEL_1) || \
9544  ((__CHANNEL__) == TIM_CHANNEL_2) || \
9545  ((__CHANNEL__) == TIM_CHANNEL_3))))
9546 
9547 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
9548 #define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
9549  (((__INSTANCE__) == TIM1) || \
9550  ((__INSTANCE__) == TIM8) )
9551 
9552 /****************** TIM Instances : supporting synchronization ****************/
9553 #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
9554  (((__INSTANCE__) == TIM1) || \
9555  ((__INSTANCE__) == TIM2) || \
9556  ((__INSTANCE__) == TIM3) || \
9557  ((__INSTANCE__) == TIM4) || \
9558  ((__INSTANCE__) == TIM5) || \
9559  ((__INSTANCE__) == TIM6) || \
9560  ((__INSTANCE__) == TIM7) || \
9561  ((__INSTANCE__) == TIM8))
9562 
9563 /******************** USART Instances : Synchronous mode **********************/
9564 #define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9565  ((__INSTANCE__) == USART2) || \
9566  ((__INSTANCE__) == USART3) || \
9567  ((__INSTANCE__) == USART6))
9568 
9569 /******************** UART Instances : Asynchronous mode **********************/
9570 #define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9571  ((__INSTANCE__) == USART2) || \
9572  ((__INSTANCE__) == USART3) || \
9573  ((__INSTANCE__) == UART4) || \
9574  ((__INSTANCE__) == UART5) || \
9575  ((__INSTANCE__) == USART6) || \
9576  ((__INSTANCE__) == UART7) || \
9577  ((__INSTANCE__) == UART8))
9578 
9579 /****************** UART Instances : Driver Enable *****************/
9580 #define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9581  ((__INSTANCE__) == USART2) || \
9582  ((__INSTANCE__) == USART3) || \
9583  ((__INSTANCE__) == UART4) || \
9584  ((__INSTANCE__) == UART5) || \
9585  ((__INSTANCE__) == USART6) || \
9586  ((__INSTANCE__) == UART7) || \
9587  ((__INSTANCE__) == UART8))
9588 
9589 /****************** UART Instances : Hardware Flow control ********************/
9590 #define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9591  ((__INSTANCE__) == USART2) || \
9592  ((__INSTANCE__) == USART3) || \
9593  ((__INSTANCE__) == UART4) || \
9594  ((__INSTANCE__) == UART5) || \
9595  ((__INSTANCE__) == USART6) || \
9596  ((__INSTANCE__) == UART7) || \
9597  ((__INSTANCE__) == UART8))
9598 
9599 /********************* UART Instances : Smart card mode ***********************/
9600 #define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9601  ((__INSTANCE__) == USART2) || \
9602  ((__INSTANCE__) == USART3) || \
9603  ((__INSTANCE__) == USART6))
9604 
9605 /*********************** UART Instances : IRDA mode ***************************/
9606 #define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9607  ((__INSTANCE__) == USART2) || \
9608  ((__INSTANCE__) == USART3) || \
9609  ((__INSTANCE__) == UART4) || \
9610  ((__INSTANCE__) == UART5) || \
9611  ((__INSTANCE__) == USART6) || \
9612  ((__INSTANCE__) == UART7) || \
9613  ((__INSTANCE__) == UART8))
9614 
9615 /****************************** IWDG Instances ********************************/
9616 #define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)
9617 
9618 /****************************** WWDG Instances ********************************/
9619 #define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)
9620 
9621 
9622 /******************************************************************************/
9623 /* For a painless codes migration between the STM32F7xx device product */
9624 /* lines, the aliases defined below are put in place to overcome the */
9625 /* differences in the interrupt handlers and IRQn definitions. */
9626 /* No need to update developed interrupt code when moving across */
9627 /* product lines within the same STM32F7 Family */
9628 /******************************************************************************/
9629 
9630 /* Aliases for __IRQn */
9631 #define HASH_RNG_IRQn RNG_IRQn
9632 
9633 /* Aliases for __IRQHandler */
9634 #define HASH_RNG_IRQHandler RNG_IRQHandler
9635 
9648 #ifdef __cplusplus
9649 }
9650 #endif /* __cplusplus */
9651 
9652 #endif /* __STM32F765xx_H */
9653 
9654 
9655 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
MDIOS_TypeDef::DINR19
__IO uint32_t DINR19
Definition: stm32f765xx.h:1175
DFSDM_Filter_TypeDef::FLTJDATAR
__IO uint32_t FLTJDATAR
Definition: stm32f765xx.h:375
RESERVED
#define RESERVED
Definition: usbh_cdc.h:68
MDIOS_TypeDef::DINR12
__IO uint32_t DINR12
Definition: stm32f765xx.h:1168
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition: stm32f745xx.h:253
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f745xx.h:613
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f745xx.h:841
SPI5_IRQn
Definition: stm32f765xx.h:163
DMA1_Stream2_IRQn
Definition: stm32f765xx.h:92
MDIOS_TypeDef::DOUTR4
__IO uint32_t DOUTR4
Definition: stm32f765xx.h:1192
CAN2_SCE_IRQn
Definition: stm32f765xx.h:145
OTG_FS_WKUP_IRQn
Definition: stm32f765xx.h:121
MDIOS_TypeDef::SR
__IO uint32_t SR
Definition: stm32f765xx.h:1153
MDIOS_TypeDef::CLRFR
__IO uint32_t CLRFR
Definition: stm32f765xx.h:1154
SVCall_IRQn
Definition: stm32f765xx.h:74
DMA2_Stream6_IRQn
Definition: stm32f765xx.h:148
OTG_HS_EP1_IN_IRQn
Definition: stm32f765xx.h:154
DMA2_Stream7_IRQn
Definition: stm32f765xx.h:149
EXTI4_IRQn
Definition: stm32f765xx.h:89
TIM4_IRQn
Definition: stm32f765xx.h:109
DFSDM_Channel_TypeDef::CHAWSCDR
__IO uint32_t CHAWSCDR
Definition: stm32f765xx.h:393
MDIOS_TypeDef::DINR7
__IO uint32_t DINR7
Definition: stm32f765xx.h:1163
MDIOS_TypeDef::DINR30
__IO uint32_t DINR30
Definition: stm32f765xx.h:1186
DFSDM1_FLT1_IRQn
Definition: stm32f765xx.h:175
MDIOS_TypeDef::DINR13
__IO uint32_t DINR13
Definition: stm32f765xx.h:1169
LPTIM1_IRQn
Definition: stm32f765xx.h:169
MDIOS_TypeDef::DINR29
__IO uint32_t DINR29
Definition: stm32f765xx.h:1185
SAI2_IRQn
Definition: stm32f765xx.h:167
ADC_IRQn
Definition: stm32f765xx.h:97
MDIOS_TypeDef::DOUTR5
__IO uint32_t DOUTR5
Definition: stm32f765xx.h:1193
CAN1_SCE_IRQn
Definition: stm32f765xx.h:101
EXTI1_IRQn
Definition: stm32f765xx.h:86
MDIOS_TypeDef::DOUTR11
__IO uint32_t DOUTR11
Definition: stm32f765xx.h:1199
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f745xx.h:519
MDIOS_TypeDef::DINR2
__IO uint32_t DINR2
Definition: stm32f765xx.h:1158
SDMMC2_IRQn
Definition: stm32f765xx.h:178
DFSDM_Filter_TypeDef::FLTRDATAR
__IO uint32_t FLTRDATAR
Definition: stm32f765xx.h:376
DMA2_Stream1_IRQn
Definition: stm32f765xx.h:136
I2C4_EV_IRQn
Definition: stm32f765xx.h:171
EXTI15_10_IRQn
Definition: stm32f765xx.h:119
CAN3_RX0_IRQn
Definition: stm32f765xx.h:180
MDIOS_TypeDef::DINR10
__IO uint32_t DINR10
Definition: stm32f765xx.h:1166
MDIOS_TypeDef::DOUTR21
__IO uint32_t DOUTR21
Definition: stm32f765xx.h:1209
SPDIFRX_TypeDef
SPDIF-RX Interface.
Definition: stm32f745xx.h:797
CEC_TypeDef
HDMI-CEC.
Definition: stm32f745xx.h:305
SPI4_IRQn
Definition: stm32f765xx.h:162
UART5_IRQn
Definition: stm32f765xx.h:132
SAI1_IRQn
Definition: stm32f765xx.h:165
TIM1_TRG_COM_TIM11_IRQn
Definition: stm32f765xx.h:105
MDIOS_TypeDef::DINR11
__IO uint32_t DINR11
Definition: stm32f765xx.h:1167
FMC_Bank3_TypeDef
Flexible Memory Controller Bank3.
Definition: stm32f745xx.h:568
MDIOS_TypeDef::DOUTR29
__IO uint32_t DOUTR29
Definition: stm32f765xx.h:1217
MDIOS_TypeDef::DINR31
__IO uint32_t DINR31
Definition: stm32f765xx.h:1187
DFSDM_Channel_TypeDef::CHDATINR
__IO uint32_t CHDATINR
Definition: stm32f765xx.h:396
TIM_TypeDef::AF1
__IO uint32_t AF1
Definition: stm32f765xx.h:950
CRC_TypeDef
CRC calculation unit.
Definition: stm32f745xx.h:320
DFSDM_Filter_TypeDef::FLTAWCFR
__IO uint32_t FLTAWCFR
Definition: stm32f765xx.h:380
EXTI9_5_IRQn
Definition: stm32f765xx.h:102
MDIOS_TypeDef::DINR4
__IO uint32_t DINR4
Definition: stm32f765xx.h:1160
DIR
Definition: ff.h:151
DFSDM1_FLT0_IRQn
Definition: stm32f765xx.h:174
MDIOS_TypeDef::DINR18
__IO uint32_t DINR18
Definition: stm32f765xx.h:1174
DFSDM_Filter_TypeDef::FLTICR
__IO uint32_t FLTICR
Definition: stm32f765xx.h:372
CAN1_RX1_IRQn
Definition: stm32f765xx.h:100
DFSDM_Filter_TypeDef::FLTAWHTR
__IO uint32_t FLTAWHTR
Definition: stm32f765xx.h:377
DMA2_Stream0_IRQn
Definition: stm32f765xx.h:135
MDIOS_TypeDef::DINR1
__IO uint32_t DINR1
Definition: stm32f765xx.h:1157
CEC_IRQn
Definition: stm32f765xx.h:170
USB_OTG_INEndpointTypeDef
USB_OTG_IN_Endpoint-Specific_Register.
Definition: stm32f745xx.h:1035
SDMMC1_IRQn
Definition: stm32f765xx.h:128
MDIOS_TypeDef::DOUTR7
__IO uint32_t DOUTR7
Definition: stm32f765xx.h:1195
I2C2_ER_IRQn
Definition: stm32f765xx.h:113
DMA2_Stream4_IRQn
Definition: stm32f765xx.h:139
EXTI3_IRQn
Definition: stm32f765xx.h:88
CAN2_RX1_IRQn
Definition: stm32f765xx.h:144
FMC_Bank1E_TypeDef
Flexible Memory Controller Bank1E.
Definition: stm32f745xx.h:559
DMA_TypeDef
Definition: stm32f745xx.h:400
TAMP_STAMP_IRQn
Definition: stm32f765xx.h:81
MDIOS_TypeDef::DINR24
__IO uint32_t DINR24
Definition: stm32f765xx.h:1180
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f745xx.h:948
MDIOS_TypeDef::RDFR
__IO uint32_t RDFR
Definition: stm32f765xx.h:1151
DFSDM1_FLT2_IRQn
Definition: stm32f765xx.h:176
MDIOS_TypeDef::CWRFR
__IO uint32_t CWRFR
Definition: stm32f765xx.h:1150
DFSDM_Channel_TypeDef::CHCFGR2
__IO uint32_t CHCFGR2
Definition: stm32f765xx.h:392
UART4_IRQn
Definition: stm32f765xx.h:131
DMA1_Stream6_IRQn
Definition: stm32f765xx.h:96
RTC_Alarm_IRQn
Definition: stm32f765xx.h:120
MDIOS_TypeDef::DOUTR24
__IO uint32_t DOUTR24
Definition: stm32f765xx.h:1212
__I
#define __I
Definition: core_cm0.h:210
DFSDM_Filter_TypeDef::FLTCNVTIMR
__IO uint32_t FLTCNVTIMR
Definition: stm32f765xx.h:383
DMA1_Stream5_IRQn
Definition: stm32f765xx.h:95
SPI2_IRQn
Definition: stm32f765xx.h:115
CAN3_RX1_IRQn
Definition: stm32f765xx.h:181
DFSDM_Channel_TypeDef::CHWDATAR
__IO uint32_t CHWDATAR
Definition: stm32f765xx.h:395
USB_OTG_GlobalTypeDef
USB_OTG_Core_Registers.
Definition: stm32f745xx.h:974
DMA1_Stream1_IRQn
Definition: stm32f765xx.h:91
DFSDM_Filter_TypeDef::FLTFCR
__IO uint32_t FLTFCR
Definition: stm32f765xx.h:374
DFSDM_Filter_TypeDef::FLTAWLTR
__IO uint32_t FLTAWLTR
Definition: stm32f765xx.h:378
PendSV_IRQn
Definition: stm32f765xx.h:76
UART7_IRQn
Definition: stm32f765xx.h:160
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f745xx.h:596
BusFault_IRQn
Definition: stm32f765xx.h:72
I2C2_EV_IRQn
Definition: stm32f765xx.h:112
MDIOS_IRQn
Definition: stm32f765xx.h:183
MDIOS_TypeDef::DINR8
__IO uint32_t DINR8
Definition: stm32f765xx.h:1164
TIM8_TRG_COM_TIM14_IRQn
Definition: stm32f765xx.h:124
TIM_TypeDef::AF2
__IO uint32_t AF2
Definition: stm32f765xx.h:951
QUADSPI_TypeDef
QUAD Serial Peripheral Interface.
Definition: stm32f745xx.h:858
MDIOS_TypeDef::DINR25
__IO uint32_t DINR25
Definition: stm32f765xx.h:1181
MDIOS_TypeDef::CR
__IO uint32_t CR
Definition: stm32f765xx.h:1148
MDIOS_TypeDef::DOUTR10
__IO uint32_t DOUTR10
Definition: stm32f765xx.h:1198
CAN2_TX_IRQn
Definition: stm32f765xx.h:142
I2C1_EV_IRQn
Definition: stm32f765xx.h:110
CAN_TypeDef
Controller Area Network.
Definition: stm32f745xx.h:275
LPTIM_TypeDef
LPTIMIMER.
Definition: stm32f745xx.h:911
FMC_IRQn
Definition: stm32f765xx.h:127
DCMI_IRQn
Definition: stm32f765xx.h:157
TIM7_IRQn
Definition: stm32f765xx.h:134
MDIOS_TypeDef::DINR3
__IO uint32_t DINR3
Definition: stm32f765xx.h:1159
DMA2D_TypeDef
DMA2D Controller.
Definition: stm32f745xx.h:413
RCC_IRQn
Definition: stm32f765xx.h:84
I2C3_EV_IRQn
Definition: stm32f765xx.h:151
__IO
#define __IO
Definition: core_cm0.h:213
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32f745xx.h:204
SysTick_IRQn
Definition: stm32f765xx.h:77
MDIOS_TypeDef::DINR17
__IO uint32_t DINR17
Definition: stm32f765xx.h:1173
SAI_TypeDef
Serial Audio Interface.
Definition: stm32f745xx.h:776
MDIOS_TypeDef::DOUTR27
__IO uint32_t DOUTR27
Definition: stm32f765xx.h:1215
DMA1_Stream0_IRQn
Definition: stm32f765xx.h:90
MDIOS_TypeDef::DOUTR20
__IO uint32_t DOUTR20
Definition: stm32f765xx.h:1208
DFSDM_Filter_TypeDef::FLTISR
__IO uint32_t FLTISR
Definition: stm32f765xx.h:371
USB_OTG_HostTypeDef
USB_OTG_Host_Mode_Register_Structures.
Definition: stm32f745xx.h:1066
IRQn_Type
IRQn_Type
STM32F7xx Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f765xx.h:67
MDIOS_TypeDef::DINR22
__IO uint32_t DINR22
Definition: stm32f765xx.h:1178
QUADSPI_IRQn
Definition: stm32f765xx.h:168
MDIOS_TypeDef::DOUTR22
__IO uint32_t DOUTR22
Definition: stm32f765xx.h:1210
MDIOS_TypeDef::DOUTR19
__IO uint32_t DOUTR19
Definition: stm32f765xx.h:1207
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition: stm32f745xx.h:241
DFSDM_Filter_TypeDef::FLTJCHGR
__IO uint32_t FLTJCHGR
Definition: stm32f765xx.h:373
ETH_TypeDef
Ethernet MAC.
Definition: stm32f745xx.h:445
TIM2_IRQn
Definition: stm32f765xx.h:107
SPI3_IRQn
Definition: stm32f765xx.h:130
MDIOS_TypeDef::DOUTR13
__IO uint32_t DOUTR13
Definition: stm32f765xx.h:1201
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f745xx.h:928
MDIOS_TypeDef::DOUTR17
__IO uint32_t DOUTR17
Definition: stm32f765xx.h:1205
TIM_TypeDef
TIM.
Definition: stm32f745xx.h:879
DMA1_Stream7_IRQn
Definition: stm32f765xx.h:126
DMA2_Stream5_IRQn
Definition: stm32f765xx.h:147
DFSDM_Filter_TypeDef
DFSDM module registers.
Definition: stm32f765xx.h:367
USART1_IRQn
Definition: stm32f765xx.h:116
MDIOS_TypeDef::DOUTR18
__IO uint32_t DOUTR18
Definition: stm32f765xx.h:1206
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f745xx.h:390
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32f745xx.h:336
USB_OTG_HostChannelTypeDef
USB_OTG_Host_Channel_Specific_Registers.
Definition: stm32f745xx.h:1080
OTG_HS_WKUP_IRQn
Definition: stm32f765xx.h:155
MDIOS_TypeDef::CRDFR
__IO uint32_t CRDFR
Definition: stm32f765xx.h:1152
I2C4_ER_IRQn
Definition: stm32f765xx.h:172
FLASH_TypeDef
FLASH Registers.
Definition: stm32f745xx.h:533
MDIOS_TypeDef::WRFR
__IO uint32_t WRFR
Definition: stm32f765xx.h:1149
DMA2_Stream2_IRQn
Definition: stm32f765xx.h:137
MDIOS_TypeDef::DOUTR12
__IO uint32_t DOUTR12
Definition: stm32f765xx.h:1200
MDIOS_TypeDef::DINR15
__IO uint32_t DINR15
Definition: stm32f765xx.h:1171
PWR_TypeDef
Power Control.
Definition: stm32f745xx.h:660
PVD_IRQn
Definition: stm32f765xx.h:80
ETH_IRQn
Definition: stm32f765xx.h:140
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f745xx.h:645
FPU_IRQn
Definition: stm32f765xx.h:159
DFSDM_Channel_TypeDef
DFSDM channel configuration registers.
Definition: stm32f765xx.h:389
OTG_HS_EP1_OUT_IRQn
Definition: stm32f765xx.h:153
MDIOS_TypeDef::DINR16
__IO uint32_t DINR16
Definition: stm32f765xx.h:1172
MDIOS_TypeDef::DINR20
__IO uint32_t DINR20
Definition: stm32f765xx.h:1176
ADC_Common_TypeDef
Definition: stm32f745xx.h:228
DMA1_Stream3_IRQn
Definition: stm32f765xx.h:93
RTC_WKUP_IRQn
Definition: stm32f765xx.h:82
DFSDM_Filter_TypeDef::FLTCR1
__IO uint32_t FLTCR1
Definition: stm32f765xx.h:369
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f745xx.h:673
MDIOS_TypeDef::DOUTR28
__IO uint32_t DOUTR28
Definition: stm32f765xx.h:1216
WWDG_IRQn
Definition: stm32f765xx.h:79
CAN2_RX0_IRQn
Definition: stm32f765xx.h:143
TIM8_BRK_TIM12_IRQn
Definition: stm32f765xx.h:122
MDIOS_TypeDef::DINR28
__IO uint32_t DINR28
Definition: stm32f765xx.h:1184
DMA2D_IRQn
Definition: stm32f765xx.h:166
MDIOS_TypeDef::DOUTR16
__IO uint32_t DOUTR16
Definition: stm32f765xx.h:1204
I2C3_ER_IRQn
Definition: stm32f765xx.h:152
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition: stm32f745xx.h:265
CAN1_TX_IRQn
Definition: stm32f765xx.h:98
DebugMonitor_IRQn
Definition: stm32f765xx.h:75
FMC_Bank1_TypeDef
Flexible Memory Controller.
Definition: stm32f745xx.h:550
MDIOS_TypeDef::DINR23
__IO uint32_t DINR23
Definition: stm32f765xx.h:1179
DFSDM_Channel_TypeDef::CHCFGR1
__IO uint32_t CHCFGR1
Definition: stm32f765xx.h:391
DMA1_Stream4_IRQn
Definition: stm32f765xx.h:94
TIM6_DAC_IRQn
Definition: stm32f765xx.h:133
MDIOS_TypeDef::DOUTR9
__IO uint32_t DOUTR9
Definition: stm32f765xx.h:1197
DFSDM_Filter_TypeDef::FLTCR2
__IO uint32_t FLTCR2
Definition: stm32f765xx.h:370
SPDIF_RX_IRQn
Definition: stm32f765xx.h:173
DFSDM_Filter_TypeDef::FLTEXMIN
__IO uint32_t FLTEXMIN
Definition: stm32f765xx.h:382
RTC_TypeDef
Real-Time Clock.
Definition: stm32f745xx.h:715
ETH_WKUP_IRQn
Definition: stm32f765xx.h:141
DCMI_TypeDef
DCMI.
Definition: stm32f745xx.h:371
I2C1_ER_IRQn
Definition: stm32f765xx.h:111
MDIOS_TypeDef::DINR0
__IO uint32_t DINR0
Definition: stm32f765xx.h:1156
FMC_Bank5_6_TypeDef
Flexible Memory Controller Bank5_6.
Definition: stm32f745xx.h:582
MDIOS_TypeDef::DINR27
__IO uint32_t DINR27
Definition: stm32f765xx.h:1183
OTG_HS_IRQn
Definition: stm32f765xx.h:156
TIM1_CC_IRQn
Definition: stm32f765xx.h:106
RNG_IRQn
Definition: stm32f765xx.h:158
MDIOS_TypeDef::DOUTR30
__IO uint32_t DOUTR30
Definition: stm32f765xx.h:1218
FLASH_IRQn
Definition: stm32f765xx.h:83
DMA2_Stream3_IRQn
Definition: stm32f765xx.h:138
MDIOS_TypeDef::DOUTR3
__IO uint32_t DOUTR3
Definition: stm32f765xx.h:1191
MDIOS_TypeDef::DINR5
__IO uint32_t DINR5
Definition: stm32f765xx.h:1161
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f745xx.h:626
TIM8_UP_TIM13_IRQn
Definition: stm32f765xx.h:123
DFSDM_Filter_TypeDef::FLTEXMAX
__IO uint32_t FLTEXMAX
Definition: stm32f765xx.h:381
SYSCFG_TypeDef::CBR
__IO uint32_t CBR
Definition: stm32f765xx.h:663
MDIOS_TypeDef::DINR14
__IO uint32_t DINR14
Definition: stm32f765xx.h:1170
MDIOS_TypeDef::DOUTR14
__IO uint32_t DOUTR14
Definition: stm32f765xx.h:1202
MDIOS_TypeDef::DOUTR26
__IO uint32_t DOUTR26
Definition: stm32f765xx.h:1214
MDIOS_TypeDef::DOUTR31
__IO uint32_t DOUTR31
Definition: stm32f765xx.h:1219
RNG_TypeDef
RNG.
Definition: stm32f745xx.h:960
SPI6_IRQn
Definition: stm32f765xx.h:164
TIM1_BRK_TIM9_IRQn
Definition: stm32f765xx.h:103
TIM1_UP_TIM10_IRQn
Definition: stm32f765xx.h:104
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f745xx.h:359
SPI1_IRQn
Definition: stm32f765xx.h:114
TIM3_IRQn
Definition: stm32f765xx.h:108
MDIOS_TypeDef::DINR6
__IO uint32_t DINR6
Definition: stm32f765xx.h:1162
MDIOS_TypeDef::DINR26
__IO uint32_t DINR26
Definition: stm32f765xx.h:1182
NonMaskableInt_IRQn
Definition: stm32f765xx.h:70
SDMMC_TypeDef
SD host Interface.
Definition: stm32f745xx.h:813
MDIOS_TypeDef::DOUTR0
__IO uint32_t DOUTR0
Definition: stm32f765xx.h:1188
DFSDM_Filter_TypeDef::FLTAWSR
__IO uint32_t FLTAWSR
Definition: stm32f765xx.h:379
TIM8_CC_IRQn
Definition: stm32f765xx.h:125
SAI_Block_TypeDef
Definition: stm32f745xx.h:781
EXTI0_IRQn
Definition: stm32f765xx.h:85
MDIOS_TypeDef::DINR21
__IO uint32_t DINR21
Definition: stm32f765xx.h:1177
EXTI2_IRQn
Definition: stm32f765xx.h:87
USB_OTG_OUTEndpointTypeDef
USB_OTG_OUT_Endpoint-Specific_Registers.
Definition: stm32f745xx.h:1051
USART3_IRQn
Definition: stm32f765xx.h:118
DFSDM1_FLT3_IRQn
Definition: stm32f765xx.h:177
MDIOS_TypeDef::DOUTR23
__IO uint32_t DOUTR23
Definition: stm32f765xx.h:1211
MDIOS_TypeDef
MDIOS.
Definition: stm32f765xx.h:1146
USART2_IRQn
Definition: stm32f765xx.h:117
MDIOS_TypeDef::DOUTR15
__IO uint32_t DOUTR15
Definition: stm32f765xx.h:1203
MDIOS_TypeDef::DINR9
__IO uint32_t DINR9
Definition: stm32f765xx.h:1165
MDIOS_TypeDef::DOUTR1
__IO uint32_t DOUTR1
Definition: stm32f765xx.h:1189
UART8_IRQn
Definition: stm32f765xx.h:161
MDIOS_TypeDef::DOUTR8
__IO uint32_t DOUTR8
Definition: stm32f765xx.h:1196
CAN3_SCE_IRQn
Definition: stm32f765xx.h:182
MDIOS_TypeDef::DOUTR6
__IO uint32_t DOUTR6
Definition: stm32f765xx.h:1194
OTG_FS_IRQn
Definition: stm32f765xx.h:146
UsageFault_IRQn
Definition: stm32f765xx.h:73
MemoryManagement_IRQn
Definition: stm32f765xx.h:71
USB_OTG_DeviceTypeDef
USB_OTG_device_Registers.
Definition: stm32f745xx.h:1007
TIM5_IRQn
Definition: stm32f765xx.h:129
CAN3_TX_IRQn
Definition: stm32f765xx.h:179
USART6_IRQn
Definition: stm32f765xx.h:150
MDIOS_TypeDef::DOUTR2
__IO uint32_t DOUTR2
Definition: stm32f765xx.h:1190
CAN1_RX0_IRQn
Definition: stm32f765xx.h:99
MDIOS_TypeDef::DOUTR25
__IO uint32_t DOUTR25
Definition: stm32f765xx.h:1213
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