STM32F769IDiscovery  1.00
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stm32f7xx_hal_rcc.h
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1 
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F7xx_HAL_RCC_H
40 #define __STM32F7xx_HAL_RCC_H
41 
42 #ifdef __cplusplus
43  extern "C" {
44 #endif
45 
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f7xx_hal_def.h"
48 
49 /* Include RCC HAL Extended module */
50 /* (include on top of file since RCC structures are defined in extended file) */
51 #include "stm32f7xx_hal_rcc_ex.h"
52 
61 /* Exported types ------------------------------------------------------------*/
62 
70 typedef struct
71 {
72  uint32_t OscillatorType;
75  uint32_t HSEState;
78  uint32_t LSEState;
81  uint32_t HSIState;
84  uint32_t HSICalibrationValue;
87  uint32_t LSIState;
90  RCC_PLLInitTypeDef PLL;
92 }RCC_OscInitTypeDef;
93 
97 typedef struct
98 {
99  uint32_t ClockType;
102  uint32_t SYSCLKSource;
105  uint32_t AHBCLKDivider;
108  uint32_t APB1CLKDivider;
111  uint32_t APB2CLKDivider;
114 }RCC_ClkInitTypeDef;
115 
120 /* Exported constants --------------------------------------------------------*/
128 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U)
129 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U)
130 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U)
131 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U)
132 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U)
133 
140 #define RCC_HSE_OFF ((uint32_t)0x00000000U)
141 #define RCC_HSE_ON RCC_CR_HSEON
142 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
143 
150 #define RCC_LSE_OFF ((uint32_t)0x00000000U)
151 #define RCC_LSE_ON RCC_BDCR_LSEON
152 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
153 
160 #define RCC_HSI_OFF ((uint32_t)0x00000000U)
161 #define RCC_HSI_ON RCC_CR_HSION
162 
163 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */
164 
171 #define RCC_LSI_OFF ((uint32_t)0x00000000U)
172 #define RCC_LSI_ON RCC_CSR_LSION
173 
180 #define RCC_PLL_NONE ((uint32_t)0x00000000U)
181 #define RCC_PLL_OFF ((uint32_t)0x00000001U)
182 #define RCC_PLL_ON ((uint32_t)0x00000002U)
183 
190 #define RCC_PLLP_DIV2 ((uint32_t)0x00000002U)
191 #define RCC_PLLP_DIV4 ((uint32_t)0x00000004U)
192 #define RCC_PLLP_DIV6 ((uint32_t)0x00000006U)
193 #define RCC_PLLP_DIV8 ((uint32_t)0x00000008U)
194 
201 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
202 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
203 
210 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U)
211 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U)
212 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U)
213 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U)
214 
221 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
222 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
223 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
224 
232 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
233 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
234 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
242 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
243 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
244 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
245 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
246 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
247 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
248 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
249 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
250 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
251 
258 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
259 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
260 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
261 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
262 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
263 
270 #define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U)
271 #define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U)
272 #define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U)
273 #define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U)
274 #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U)
275 #define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U)
276 #define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U)
277 #define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U)
278 #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U)
279 #define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U)
280 #define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U)
281 #define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U)
282 #define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U)
283 #define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U)
284 #define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U)
285 #define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U)
286 #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U)
287 #define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U)
288 #define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U)
289 #define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U)
290 #define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U)
291 #define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U)
292 #define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U)
293 #define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U)
294 #define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U)
295 #define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U)
296 #define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U)
297 #define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U)
298 #define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U)
299 #define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U)
300 #define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U)
301 #define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U)
302 
311 #define RCC_MCO1 ((uint32_t)0x00000000U)
312 #define RCC_MCO2 ((uint32_t)0x00000001U)
313 
320 #define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U)
321 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
322 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
323 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
324 
331 #define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U)
332 #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
333 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
334 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
335 
342 #define RCC_MCODIV_1 ((uint32_t)0x00000000U)
343 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
344 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
345 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
346 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
347 
354 #define RCC_IT_LSIRDY ((uint8_t)0x01U)
355 #define RCC_IT_LSERDY ((uint8_t)0x02U)
356 #define RCC_IT_HSIRDY ((uint8_t)0x04U)
357 #define RCC_IT_HSERDY ((uint8_t)0x08U)
358 #define RCC_IT_PLLRDY ((uint8_t)0x10U)
359 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20U)
360 #define RCC_IT_PLLSAIRDY ((uint8_t)0x40U)
361 #define RCC_IT_CSS ((uint8_t)0x80U)
362 
375 /* Flags in the CR register */
376 #define RCC_FLAG_HSIRDY ((uint8_t)0x21U)
377 #define RCC_FLAG_HSERDY ((uint8_t)0x31U)
378 #define RCC_FLAG_PLLRDY ((uint8_t)0x39U)
379 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU)
380 #define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3CU)
381 
382 /* Flags in the BDCR register */
383 #define RCC_FLAG_LSERDY ((uint8_t)0x41U)
384 
385 /* Flags in the CSR register */
386 #define RCC_FLAG_LSIRDY ((uint8_t)0x61U)
387 #define RCC_FLAG_BORRST ((uint8_t)0x79U)
388 #define RCC_FLAG_PINRST ((uint8_t)0x7AU)
389 #define RCC_FLAG_PORRST ((uint8_t)0x7BU)
390 #define RCC_FLAG_SFTRST ((uint8_t)0x7CU)
391 #define RCC_FLAG_IWDGRST ((uint8_t)0x7DU)
392 #define RCC_FLAG_WWDGRST ((uint8_t)0x7EU)
393 #define RCC_FLAG_LPWRRST ((uint8_t)0x7FU)
394 
401 #define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U)
402 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1
403 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0
404 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
405 
413 /* Exported macro ------------------------------------------------------------*/
425 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
426  __IO uint32_t tmpreg; \
427  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
428  /* Delay after an RCC peripheral clock enabling */ \
429  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
430  UNUSED(tmpreg); \
431  } while(0)
432 
433 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
434  __IO uint32_t tmpreg; \
435  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
436  /* Delay after an RCC peripheral clock enabling */ \
437  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
438  UNUSED(tmpreg); \
439  } while(0)
440 
441 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
442 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
443 
455 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
456  __IO uint32_t tmpreg; \
457  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
458  /* Delay after an RCC peripheral clock enabling */ \
459  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
460  UNUSED(tmpreg); \
461  } while(0)
462 
463 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
464  __IO uint32_t tmpreg; \
465  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
466  /* Delay after an RCC peripheral clock enabling */ \
467  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
468  UNUSED(tmpreg); \
469  } while(0)
470 
471 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
472 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
473 
484 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
485  __IO uint32_t tmpreg; \
486  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
487  /* Delay after an RCC peripheral clock enabling */ \
488  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
489  UNUSED(tmpreg); \
490  } while(0)
491 
492 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
493 
505 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
506 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET)
507 
508 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
509 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET)
510 
521 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
522 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
523 
524 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
525 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
526 
537 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
538 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
539 
547 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
548 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
549 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
550 
551 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
552 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
553 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
554 
562 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
563 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
564 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
565 
566 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
567 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
568 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
569 
577 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
578 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
579 
580 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
581 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
582 
594 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
595 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
596 
597 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
598 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
599 
606 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
607 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
608 
609 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
610 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
611 
618 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
619 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
620 
633 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET)
634 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET)
635 
636 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET)
637 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET)
638 
650 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET)
651 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET)
652 
653 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET)
654 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET)
655 
667 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET)
668 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET)
669 
691 #define __HAL_RCC_HSI_ENABLE() (RCC->CR |= (RCC_CR_HSION))
692 #define __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION))
693 
700 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\
701  RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_CR_HSITRIM)))
702 
718 #define __HAL_RCC_LSI_ENABLE() (RCC->CSR |= (RCC_CSR_LSION))
719 #define __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION))
720 
749 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
750  do { \
751  if ((__STATE__) == RCC_HSE_ON) \
752  { \
753  SET_BIT(RCC->CR, RCC_CR_HSEON); \
754  } \
755  else if ((__STATE__) == RCC_HSE_OFF) \
756  { \
757  CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
758  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
759  } \
760  else if ((__STATE__) == RCC_HSE_BYPASS) \
761  { \
762  SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
763  SET_BIT(RCC->CR, RCC_CR_HSEON); \
764  } \
765  else \
766  { \
767  CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
768  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
769  } \
770  } while(0)
771 
797 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
798  do { \
799  if((__STATE__) == RCC_LSE_ON) \
800  { \
801  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
802  } \
803  else if((__STATE__) == RCC_LSE_OFF) \
804  { \
805  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
806  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
807  } \
808  else if((__STATE__) == RCC_LSE_BYPASS) \
809  { \
810  SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
811  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
812  } \
813  else \
814  { \
815  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
816  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
817  } \
818  } while(0)
819 
830 #define __HAL_RCC_RTC_ENABLE() (RCC->BDCR |= (RCC_BDCR_RTCEN))
831 #define __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN))
832 
854 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
855  MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
856 
857 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
858  RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \
859  } while (0)
860 
866 #define __HAL_RCC_BACKUPRESET_FORCE() (RCC->BDCR |= (RCC_BDCR_BDRST))
867 #define __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST))
868 
883 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
884 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
885 
894 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
895 
905 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
906 
922 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \
923  RCC->CFGR |= (__SOURCE__); \
924  }while(0)
925 
929 #define __HAL_RCC_PLLI2S_ENABLE() (RCC->CR |= (RCC_CR_PLLI2SON))
930 #define __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON))
931 
946 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
947 
955 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
956 
971 #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) \
972  (MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
973 
980 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
981 
1005 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
1006  MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
1007 
1024 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
1025  MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3)));
1026 
1046 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
1047 
1059 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
1060 
1073 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
1074 
1087 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
1088 
1092 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
1093 
1112 #define RCC_FLAG_MASK ((uint8_t)0x1F)
1113 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
1114 
1123 /* Include RCC HAL Extension module */
1124 #include "stm32f7xx_hal_rcc_ex.h"
1125 
1126 /* Exported functions --------------------------------------------------------*/
1134 /* Initialization and de-initialization functions ******************************/
1135 void HAL_RCC_DeInit(void);
1136 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1137 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
1145 /* Peripheral Control functions ************************************************/
1146 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
1147 void HAL_RCC_EnableCSS(void);
1148 void HAL_RCC_DisableCSS(void);
1149 uint32_t HAL_RCC_GetSysClockFreq(void);
1150 uint32_t HAL_RCC_GetHCLKFreq(void);
1151 uint32_t HAL_RCC_GetPCLK1Freq(void);
1152 uint32_t HAL_RCC_GetPCLK2Freq(void);
1153 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1154 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
1155 
1156 /* CSS NMI IRQ handler */
1157 void HAL_RCC_NMI_IRQHandler(void);
1158 
1159 /* User Callbacks in non blocking mode (IT mode) */
1160 void HAL_RCC_CSSCallback(void);
1169 /* Private types -------------------------------------------------------------*/
1170 /* Private variables ---------------------------------------------------------*/
1171 /* Private constants ---------------------------------------------------------*/
1175 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
1176 #define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
1177 #define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
1178 #define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
1179 #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
1180 
1185 /* CIR register byte 2 (Bits[15:8]) base address */
1186 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
1187 
1188 /* CIR register byte 3 (Bits[23:16]) base address */
1189 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
1190 
1191 #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
1192 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
1193 
1200 /* Private macros ------------------------------------------------------------*/
1208 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
1209 
1210 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
1211  ((HSE) == RCC_HSE_BYPASS))
1212 
1213 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
1214  ((LSE) == RCC_LSE_BYPASS))
1215 
1216 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
1217 
1218 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
1219 
1220 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
1221 
1222 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
1223  ((SOURCE) == RCC_PLLSOURCE_HSE))
1224 
1225 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
1226  ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
1227  ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
1228 #define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))
1229 
1230 #define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
1231 
1232 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || \
1233  ((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8))
1234 #define IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
1235 
1236 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
1237  ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
1238  ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
1239  ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
1240  ((HCLK) == RCC_SYSCLK_DIV512))
1241 
1242 #define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
1243 
1244 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
1245  ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
1246  ((PCLK) == RCC_HCLK_DIV16))
1247 
1248 #define IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) || ((MCOX) == RCC_MCO2))
1249 
1250 
1251 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
1252  ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
1253 
1254 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
1255  ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
1256 
1257 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
1258  ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
1259  ((DIV) == RCC_MCODIV_5))
1260 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
1261 
1262 #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \
1263  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
1264  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
1265  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
1266  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
1267  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
1268  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
1269  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
1270  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
1271  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
1272  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
1273  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
1274  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
1275  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
1276  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
1277  ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31))
1278 
1279 
1280 #define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW) || \
1281  ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW) || \
1282  ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \
1283  ((DRIVE) == RCC_LSEDRIVE_HIGH))
1284 
1300 #ifdef __cplusplus
1301 }
1302 #endif
1303 
1304 #endif /* __STM32F7xx_HAL_RCC_H */
1305 
1306 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RCC_ClkInitTypeDef::APB2CLKDivider
uint32_t APB2CLKDivider
Definition: stm32f7xx_hal_rcc.h:111
stm32f7xx_hal_rcc_ex.h
Header file of RCC HAL Extension module.
RCC_OscInitTypeDef::HSICalibrationValue
uint32_t HSICalibrationValue
Definition: stm32f7xx_hal_rcc.h:84
RCC_ClkInitTypeDef::ClockType
uint32_t ClockType
Definition: stm32f7xx_hal_rcc.h:99
RCC_ClkInitTypeDef
RCC System, AHB and APB busses clock configuration structure definition.
Definition: stm32f7xx_hal_rcc.h:97
HAL_RCC_MCOConfig
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
HAL_RCC_EnableCSS
void HAL_RCC_EnableCSS(void)
RCC_OscInitTypeDef::HSIState
uint32_t HSIState
Definition: stm32f7xx_hal_rcc.h:81
RCC_ClkInitTypeDef::SYSCLKSource
uint32_t SYSCLKSource
Definition: stm32f7xx_hal_rcc.h:102
RCC_PLLInitTypeDef
RCC PLL configuration structure definition.
Definition: stm32f7xx_hal_rcc_ex.h:65
HAL_RCC_DeInit
void HAL_RCC_DeInit(void)
HAL_RCC_GetClockConfig
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
RCC_OscInitTypeDef::PLL
RCC_PLLInitTypeDef PLL
Definition: stm32f7xx_hal_rcc.h:90
RCC_OscInitTypeDef::HSEState
uint32_t HSEState
Definition: stm32f7xx_hal_rcc.h:75
RCC_OscInitTypeDef::LSEState
uint32_t LSEState
Definition: stm32f7xx_hal_rcc.h:78
HAL_RCC_GetPCLK1Freq
uint32_t HAL_RCC_GetPCLK1Freq(void)
HAL_RCC_GetSysClockFreq
uint32_t HAL_RCC_GetSysClockFreq(void)
RCC_OscInitTypeDef::OscillatorType
uint32_t OscillatorType
Definition: stm32f7xx_hal_rcc.h:72
HAL_RCC_OscConfig
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
HAL_RCC_GetOscConfig
void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition.
Definition: stm32f7xx_hal_rcc.h:70
RCC_OscInitTypeDef::LSIState
uint32_t LSIState
Definition: stm32f7xx_hal_rcc.h:87
HAL_RCC_DisableCSS
void HAL_RCC_DisableCSS(void)
HAL_RCC_GetHCLKFreq
uint32_t HAL_RCC_GetHCLKFreq(void)
RCC_ClkInitTypeDef::AHBCLKDivider
uint32_t AHBCLKDivider
Definition: stm32f7xx_hal_rcc.h:105
stm32f7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
RCC_ClkInitTypeDef::APB1CLKDivider
uint32_t APB1CLKDivider
Definition: stm32f7xx_hal_rcc.h:108
HAL_RCC_ClockConfig
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
HAL_RCC_CSSCallback
void HAL_RCC_CSSCallback(void)
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32f7xx_hal_def.h:56
HAL_RCC_GetPCLK2Freq
uint32_t HAL_RCC_GetPCLK2Freq(void)
HAL_RCC_NMI_IRQHandler
void HAL_RCC_NMI_IRQHandler(void)
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