APB2 Peripheral Clock Enable Disable

Enable or disable the High Speed APB (APB2) peripheral clock. More...

Macros
#define	__HAL_RCC_SYSCFG_CLK_ENABLE()
#define	__HAL_RCC_SYSCFG_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))

Detailed Description

Enable or disable the High Speed APB (APB2) peripheral clock.

Note

After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Macro Definition Documentation

#define __HAL_RCC_SYSCFG_CLK_DISABLE

(

)

(RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))

Definition at line 492 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_CLK_ENABLE

(

)

Value:

do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 484 of file stm32f7xx_hal_rcc.h.