STM32F769IDiscovery  1.00
uDANTE Audio Networking with STM32F7 DISCO board
stm32f7xx_hal_rcc_ex.h
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1 
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F7xx_HAL_RCC_EX_H
40 #define __STM32F7xx_HAL_RCC_EX_H
41 
42 #ifdef __cplusplus
43  extern "C" {
44 #endif
45 
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f7xx_hal_def.h"
48 
57 /* Exported types ------------------------------------------------------------*/
65 typedef struct
66 {
67  uint32_t PLLState;
70  uint32_t PLLSource;
73  uint32_t PLLM;
76  uint32_t PLLN;
79  uint32_t PLLP;
82  uint32_t PLLQ;
84 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
85  uint32_t PLLR;
87 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
88 
89 }RCC_PLLInitTypeDef;
90 
94 typedef struct
95 {
96  uint32_t PLLI2SN;
100  uint32_t PLLI2SR;
104  uint32_t PLLI2SQ;
108  uint32_t PLLI2SP;
111 }RCC_PLLI2SInitTypeDef;
112 
116 typedef struct
117 {
118  uint32_t PLLSAIN;
122  uint32_t PLLSAIQ;
126  uint32_t PLLSAIR;
130  uint32_t PLLSAIP;
133 }RCC_PLLSAIInitTypeDef;
134 
138 typedef struct
139 {
140  uint32_t PeriphClockSelection;
143  RCC_PLLI2SInitTypeDef PLLI2S;
146  RCC_PLLSAIInitTypeDef PLLSAI;
149  uint32_t PLLI2SDivQ;
153  uint32_t PLLSAIDivQ;
157  uint32_t PLLSAIDivR;
160  uint32_t RTCClockSelection;
163  uint32_t I2sClockSelection;
166  uint32_t TIMPresSelection;
169  uint32_t Sai1ClockSelection;
172  uint32_t Sai2ClockSelection;
175  uint32_t Usart1ClockSelection;
178  uint32_t Usart2ClockSelection;
181  uint32_t Usart3ClockSelection;
184  uint32_t Uart4ClockSelection;
187  uint32_t Uart5ClockSelection;
190  uint32_t Usart6ClockSelection;
193  uint32_t Uart7ClockSelection;
196  uint32_t Uart8ClockSelection;
199  uint32_t I2c1ClockSelection;
202  uint32_t I2c2ClockSelection;
205  uint32_t I2c3ClockSelection;
208  uint32_t I2c4ClockSelection;
211  uint32_t Lptim1ClockSelection;
214  uint32_t CecClockSelection;
217  uint32_t Clk48ClockSelection;
220  uint32_t Sdmmc1ClockSelection;
223 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
224  uint32_t Sdmmc2ClockSelection;
227  uint32_t Dfsdm1ClockSelection;
230  uint32_t Dfsdm1AudioClockSelection;
232 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
233 }RCC_PeriphCLKInitTypeDef;
238 /* Exported constants --------------------------------------------------------*/
246 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U)
247 #if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
248 #define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U)
249 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
250 #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U)
251 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U)
252 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040U)
253 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080U)
254 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100U)
255 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200U)
256 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400U)
257 #define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800U)
258 #define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000U)
259 #define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000U)
260 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000U)
261 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000U)
262 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000U)
263 #define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000U)
264 #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000U)
265 #define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000U)
266 #define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000U)
267 #define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000U)
268 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000U)
269 #define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000U)
270 #define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000U)
271 #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000U)
272 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
273 #define RCC_PERIPHCLK_SDMMC2 ((uint32_t)0x04000000U)
274 #define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x08000000U)
275 #define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x10000000U)
276 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
277 
285 #define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000000U)
286 #define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000001U)
287 #define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000002U)
288 #define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000003U)
289 
296 #define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000U)
297 #define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001U)
298 #define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002U)
299 #define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003U)
300 
307 #define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000U)
308 #define RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0
309 #define RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1
310 #define RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR
311 
318 #define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000U)
319 #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC
320 
329 #define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000U)
330 #define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0
331 #define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1
332 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
333 #define RCC_SAI1CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI1SEL
334 #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
335 
342 #define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000U)
343 #define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0
344 #define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1
345 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
346 #define RCC_SAI2CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI2SEL
347 #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
348 
355 #define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000U)
356 #define RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/
357 
364 #define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)
365 #define RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0
366 #define RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1
367 #define RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL
368 
375 #define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
376 #define RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0
377 #define RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1
378 #define RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL
379 
386 #define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
387 #define RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0
388 #define RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1
389 #define RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL
390 
397 #define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
398 #define RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0
399 #define RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1
400 #define RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL
401 
408 #define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
409 #define RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0
410 #define RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1
411 #define RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL
412 
419 #define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)
420 #define RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0
421 #define RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1
422 #define RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL
423 
430 #define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
431 #define RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0
432 #define RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1
433 #define RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL
434 
441 #define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
442 #define RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0
443 #define RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1
444 #define RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL
445 
452 #define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
453 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0
454 #define RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1
455 
462 #define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
463 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0
464 #define RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1
465 
473 #define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
474 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0
475 #define RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1
476 
483 #define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
484 #define RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0
485 #define RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1
486 
493 #define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
494 #define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0
495 #define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1
496 #define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL
497 
505 #define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000U)
506 #define RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL
507 
514 #define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000U)
515 #define RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE
516 
523 #define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000U)
524 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL
525 
529 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
530 
533 #define RCC_SDMMC2CLKSOURCE_CLK48 ((uint32_t)0x00000000U)
534 #define RCC_SDMMC2CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC2SEL
535 
542 #define RCC_DFSDM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
543 #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL
544 
551 #define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 ((uint32_t)0x00000000U)
552 #define RCC_DFSDM1AUDIOCLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL
553 
556 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
557 
558 #if defined (STM32F769xx) || defined (STM32F779xx)
559 
562 #define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000U)
563 #define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR2_DSISEL)
564 
567 #endif /* STM32F769xx || STM32F779xx */
568 
573 /* Exported macro ------------------------------------------------------------*/
590 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
591  __IO uint32_t tmpreg; \
592  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
593  /* Delay after an RCC peripheral clock enabling */ \
594  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
595  UNUSED(tmpreg); \
596  } while(0)
597 
598 #define __HAL_RCC_DTCMRAMEN_CLK_ENABLE() do { \
599  __IO uint32_t tmpreg; \
600  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
601  /* Delay after an RCC peripheral clock enabling */ \
602  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
603  UNUSED(tmpreg); \
604  } while(0)
605 
606 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
607  __IO uint32_t tmpreg; \
608  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
609  /* Delay after an RCC peripheral clock enabling */ \
610  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
611  UNUSED(tmpreg); \
612  } while(0)
613 
614 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
615  __IO uint32_t tmpreg; \
616  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
617  /* Delay after an RCC peripheral clock enabling */ \
618  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
619  UNUSED(tmpreg); \
620  } while(0)
621 
622 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
623  __IO uint32_t tmpreg; \
624  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
625  /* Delay after an RCC peripheral clock enabling */ \
626  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
627  UNUSED(tmpreg); \
628  } while(0)
629 
630 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
631  __IO uint32_t tmpreg; \
632  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
633  /* Delay after an RCC peripheral clock enabling */ \
634  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
635  UNUSED(tmpreg); \
636  } while(0)
637 
638 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
639  __IO uint32_t tmpreg; \
640  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
641  /* Delay after an RCC peripheral clock enabling */ \
642  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
643  UNUSED(tmpreg); \
644  } while(0)
645 
646 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
647  __IO uint32_t tmpreg; \
648  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
649  /* Delay after an RCC peripheral clock enabling */ \
650  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
651  UNUSED(tmpreg); \
652  } while(0)
653 
654 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
655  __IO uint32_t tmpreg; \
656  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
657  /* Delay after an RCC peripheral clock enabling */ \
658  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
659  UNUSED(tmpreg); \
660  } while(0)
661 
662 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
663  __IO uint32_t tmpreg; \
664  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
665  /* Delay after an RCC peripheral clock enabling */ \
666  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
667  UNUSED(tmpreg); \
668  } while(0)
669 
670 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
671  __IO uint32_t tmpreg; \
672  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
673  /* Delay after an RCC peripheral clock enabling */ \
674  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
675  UNUSED(tmpreg); \
676  } while(0)
677 
678 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
679  __IO uint32_t tmpreg; \
680  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
681  /* Delay after an RCC peripheral clock enabling */ \
682  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
683  UNUSED(tmpreg); \
684  } while(0)
685 
686 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
687  __IO uint32_t tmpreg; \
688  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
689  /* Delay after an RCC peripheral clock enabling */ \
690  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
691  UNUSED(tmpreg); \
692  } while(0)
693 
694 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
695  __IO uint32_t tmpreg; \
696  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
697  /* Delay after an RCC peripheral clock enabling */ \
698  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
699  UNUSED(tmpreg); \
700  } while(0)
701 
702 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
703  __IO uint32_t tmpreg; \
704  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
705  /* Delay after an RCC peripheral clock enabling */ \
706  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
707  UNUSED(tmpreg); \
708  } while(0)
709 
710 #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
711  __IO uint32_t tmpreg; \
712  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
713  /* Delay after an RCC peripheral clock enabling */ \
714  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
715  UNUSED(tmpreg); \
716  } while(0)
717 
718 #define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
719  __IO uint32_t tmpreg; \
720  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
721  /* Delay after an RCC peripheral clock enabling */ \
722  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
723  UNUSED(tmpreg); \
724  } while(0)
725 
726 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
727 #define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN))
728 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
729 #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
730 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
731 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
732 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
733 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
734 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
735 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
736 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
737 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
738 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
739 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
740 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
741 #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
742 #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
743 
746 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
747  __IO uint32_t tmpreg; \
748  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
749  /* Delay after an RCC peripheral clock enabling */ \
750  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
751  UNUSED(tmpreg); \
752  } while(0)
753 
754 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
755  __IO uint32_t tmpreg; \
756  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
757  /* Delay after an RCC peripheral clock enabling */ \
758  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
759  UNUSED(tmpreg); \
760  } while(0)
761 
762 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
763  __IO uint32_t tmpreg; \
764  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
765  /* Delay after an RCC peripheral clock enabling */ \
766  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
767  UNUSED(tmpreg); \
768  } while(0)
769 
770 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
771  __IO uint32_t tmpreg; \
772  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
773  /* Delay after an RCC peripheral clock enabling */ \
774  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
775  UNUSED(tmpreg); \
776  } while(0)
777 
778 #define __HAL_RCC_ETH_CLK_ENABLE() do { \
779  __HAL_RCC_ETHMAC_CLK_ENABLE(); \
780  __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
781  __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
782  } while(0)
783 
786 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
787 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
788 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
789 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
790 #define __HAL_RCC_ETH_CLK_DISABLE() do { \
791  __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
792  __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
793  __HAL_RCC_ETHMAC_CLK_DISABLE(); \
794  } while(0)
795 
801 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
802  __IO uint32_t tmpreg; \
803  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
804  /* Delay after an RCC peripheral clock enabling */ \
805  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
806  UNUSED(tmpreg); \
807  } while(0)
808 
809 #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
810 #define __HAL_RCC_JPEG_CLK_ENABLE() do { \
811  __IO uint32_t tmpreg; \
812  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\
813  /* Delay after an RCC peripheral clock enabling */ \
814  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\
815  UNUSED(tmpreg); \
816  } while(0)
817 #define __HAL_RCC_JPEG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN))
818 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
819 
820 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
821  __IO uint32_t tmpreg; \
822  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
823  /* Delay after an RCC peripheral clock enabling */ \
824  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
825  UNUSED(tmpreg); \
826  } while(0)
827 
828 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
829  __IO uint32_t tmpreg; \
830  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
831  /* Delay after an RCC peripheral clock enabling */ \
832  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
833  UNUSED(tmpreg); \
834  __HAL_RCC_SYSCFG_CLK_ENABLE();\
835  } while(0)
836 
837 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
838 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
839 
840 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
841 #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
842 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \
843  __IO uint32_t tmpreg; \
844  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
845  /* Delay after an RCC peripheral clock enabling */ \
846  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
847  UNUSED(tmpreg); \
848  } while(0)
849 
850 #define __HAL_RCC_HASH_CLK_ENABLE() do { \
851  __IO uint32_t tmpreg; \
852  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
853  /* Delay after an RCC peripheral clock enabling */ \
854  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
855  UNUSED(tmpreg); \
856  } while(0)
857 
858 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
859 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
860 #endif /* STM32F756x || STM32F777xx || STM32F779xx */
861 
867 #define __HAL_RCC_FMC_CLK_ENABLE() do { \
868  __IO uint32_t tmpreg; \
869  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
870  /* Delay after an RCC peripheral clock enabling */ \
871  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
872  UNUSED(tmpreg); \
873  } while(0)
874 
875 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \
876  __IO uint32_t tmpreg; \
877  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
878  /* Delay after an RCC peripheral clock enabling */ \
879  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
880  UNUSED(tmpreg); \
881  } while(0)
882 
883 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
884 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
885 
891 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
892  __IO uint32_t tmpreg; \
893  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
894  /* Delay after an RCC peripheral clock enabling */ \
895  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
896  UNUSED(tmpreg); \
897  } while(0)
898 
899 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
900  __IO uint32_t tmpreg; \
901  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
902  /* Delay after an RCC peripheral clock enabling */ \
903  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
904  UNUSED(tmpreg); \
905  } while(0)
906 
907 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
908  __IO uint32_t tmpreg; \
909  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
910  /* Delay after an RCC peripheral clock enabling */ \
911  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
912  UNUSED(tmpreg); \
913  } while(0)
914 
915 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
916  __IO uint32_t tmpreg; \
917  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
918  /* Delay after an RCC peripheral clock enabling */ \
919  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
920  UNUSED(tmpreg); \
921  } while(0)
922 
923 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
924  __IO uint32_t tmpreg; \
925  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
926  /* Delay after an RCC peripheral clock enabling */ \
927  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
928  UNUSED(tmpreg); \
929  } while(0)
930 
931 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
932  __IO uint32_t tmpreg; \
933  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
934  /* Delay after an RCC peripheral clock enabling */ \
935  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
936  UNUSED(tmpreg); \
937  } while(0)
938 
939 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
940  __IO uint32_t tmpreg; \
941  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
942  /* Delay after an RCC peripheral clock enabling */ \
943  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
944  UNUSED(tmpreg); \
945  } while(0)
946 
947 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
948  __IO uint32_t tmpreg; \
949  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
950  /* Delay after an RCC peripheral clock enabling */ \
951  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
952  UNUSED(tmpreg); \
953  } while(0)
954 
955 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
956  __IO uint32_t tmpreg; \
957  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
958  /* Delay after an RCC peripheral clock enabling */ \
959  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
960  UNUSED(tmpreg); \
961  } while(0)
962 
963 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
964  __IO uint32_t tmpreg; \
965  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
966  /* Delay after an RCC peripheral clock enabling */ \
967  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
968  UNUSED(tmpreg); \
969  } while(0)
970 
971 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
972 #define __HAL_RCC_RTC_CLK_ENABLE() do { \
973  __IO uint32_t tmpreg; \
974  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\
975  /* Delay after an RCC peripheral clock enabling */ \
976  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\
977  UNUSED(tmpreg); \
978  } while(0)
979 
980 #define __HAL_RCC_CAN3_CLK_ENABLE() do { \
981  __IO uint32_t tmpreg; \
982  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
983  /* Delay after an RCC peripheral clock enabling */ \
984  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
985  UNUSED(tmpreg); \
986  } while(0)
987 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
988 
989 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
990  __IO uint32_t tmpreg; \
991  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
992  /* Delay after an RCC peripheral clock enabling */ \
993  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
994  UNUSED(tmpreg); \
995  } while(0)
996 
997 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
998  __IO uint32_t tmpreg; \
999  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
1000  /* Delay after an RCC peripheral clock enabling */ \
1001  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
1002  UNUSED(tmpreg); \
1003  } while(0)
1004 
1005 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
1006  __IO uint32_t tmpreg; \
1007  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
1008  /* Delay after an RCC peripheral clock enabling */ \
1009  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
1010  UNUSED(tmpreg); \
1011  } while(0)
1012 
1013 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
1014  __IO uint32_t tmpreg; \
1015  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
1016  /* Delay after an RCC peripheral clock enabling */ \
1017  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
1018  UNUSED(tmpreg); \
1019  } while(0)
1020 
1021 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
1022  __IO uint32_t tmpreg; \
1023  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
1024  /* Delay after an RCC peripheral clock enabling */ \
1025  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
1026  UNUSED(tmpreg); \
1027  } while(0)
1028 
1029 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
1030  __IO uint32_t tmpreg; \
1031  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
1032  /* Delay after an RCC peripheral clock enabling */ \
1033  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
1034  UNUSED(tmpreg); \
1035  } while(0)
1036 
1037 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
1038  __IO uint32_t tmpreg; \
1039  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
1040  /* Delay after an RCC peripheral clock enabling */ \
1041  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
1042  UNUSED(tmpreg); \
1043  } while(0)
1044 
1045 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
1046  __IO uint32_t tmpreg; \
1047  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
1048  /* Delay after an RCC peripheral clock enabling */ \
1049  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
1050  UNUSED(tmpreg); \
1051  } while(0)
1052 
1053 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
1054  __IO uint32_t tmpreg; \
1055  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
1056  /* Delay after an RCC peripheral clock enabling */ \
1057  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
1058  UNUSED(tmpreg); \
1059  } while(0)
1060 
1061 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
1062  __IO uint32_t tmpreg; \
1063  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
1064  /* Delay after an RCC peripheral clock enabling */ \
1065  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
1066  UNUSED(tmpreg); \
1067  } while(0)
1068 
1069 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \
1070  __IO uint32_t tmpreg; \
1071  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
1072  /* Delay after an RCC peripheral clock enabling */ \
1073  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
1074  UNUSED(tmpreg); \
1075  } while(0)
1076 
1077 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
1078  __IO uint32_t tmpreg; \
1079  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
1080  /* Delay after an RCC peripheral clock enabling */ \
1081  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
1082  UNUSED(tmpreg); \
1083  } while(0)
1084 
1085 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
1086  __IO uint32_t tmpreg; \
1087  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
1088  /* Delay after an RCC peripheral clock enabling */ \
1089  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
1090  UNUSED(tmpreg); \
1091  } while(0)
1092 
1093 #define __HAL_RCC_CEC_CLK_ENABLE() do { \
1094  __IO uint32_t tmpreg; \
1095  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
1096  /* Delay after an RCC peripheral clock enabling */ \
1097  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
1098  UNUSED(tmpreg); \
1099  } while(0)
1100 
1101 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
1102  __IO uint32_t tmpreg; \
1103  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
1104  /* Delay after an RCC peripheral clock enabling */ \
1105  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
1106  UNUSED(tmpreg); \
1107  } while(0)
1108 
1109 #define __HAL_RCC_UART7_CLK_ENABLE() do { \
1110  __IO uint32_t tmpreg; \
1111  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
1112  /* Delay after an RCC peripheral clock enabling */ \
1113  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
1114  UNUSED(tmpreg); \
1115  } while(0)
1116 
1117 #define __HAL_RCC_UART8_CLK_ENABLE() do { \
1118  __IO uint32_t tmpreg; \
1119  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
1120  /* Delay after an RCC peripheral clock enabling */ \
1121  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
1122  UNUSED(tmpreg); \
1123  } while(0)
1124 
1125 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
1126 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
1127 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
1128 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
1129 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
1130 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
1131 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
1132 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
1133 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
1134 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
1135 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1136 #define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN))
1137 #define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN))
1138 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1139 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
1140 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
1141 #define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
1142 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
1143 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
1144 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
1145 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
1146 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
1147 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
1148 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
1149 #define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN))
1150 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
1151 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
1152 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
1153 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
1154 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
1155 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
1156 
1162 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
1163  __IO uint32_t tmpreg; \
1164  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
1165  /* Delay after an RCC peripheral clock enabling */ \
1166  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
1167  UNUSED(tmpreg); \
1168  } while(0)
1169 
1170 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
1171  __IO uint32_t tmpreg; \
1172  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
1173  /* Delay after an RCC peripheral clock enabling */ \
1174  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
1175  UNUSED(tmpreg); \
1176  } while(0)
1177 
1178 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
1179  __IO uint32_t tmpreg; \
1180  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
1181  /* Delay after an RCC peripheral clock enabling */ \
1182  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
1183  UNUSED(tmpreg); \
1184  } while(0)
1185 
1186 #define __HAL_RCC_USART6_CLK_ENABLE() do { \
1187  __IO uint32_t tmpreg; \
1188  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
1189  /* Delay after an RCC peripheral clock enabling */ \
1190  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
1191  UNUSED(tmpreg); \
1192  } while(0)
1193 
1194 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1195 #define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \
1196  __IO uint32_t tmpreg; \
1197  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\
1198  /* Delay after an RCC peripheral clock enabling */ \
1199  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\
1200  UNUSED(tmpreg); \
1201  } while(0)
1202 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1203 
1204 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
1205  __IO uint32_t tmpreg; \
1206  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
1207  /* Delay after an RCC peripheral clock enabling */ \
1208  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
1209  UNUSED(tmpreg); \
1210  } while(0)
1211 
1212 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \
1213  __IO uint32_t tmpreg; \
1214  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
1215  /* Delay after an RCC peripheral clock enabling */ \
1216  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
1217  UNUSED(tmpreg); \
1218  } while(0)
1219 
1220 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \
1221  __IO uint32_t tmpreg; \
1222  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
1223  /* Delay after an RCC peripheral clock enabling */ \
1224  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
1225  UNUSED(tmpreg); \
1226  } while(0)
1227 
1228 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
1229  __IO uint32_t tmpreg; \
1230  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
1231  /* Delay after an RCC peripheral clock enabling */ \
1232  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
1233  UNUSED(tmpreg); \
1234  } while(0)
1235 
1236 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
1237  __IO uint32_t tmpreg; \
1238  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
1239  /* Delay after an RCC peripheral clock enabling */ \
1240  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
1241  UNUSED(tmpreg); \
1242  } while(0)
1243 
1244 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
1245  __IO uint32_t tmpreg; \
1246  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
1247  /* Delay after an RCC peripheral clock enabling */ \
1248  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
1249  UNUSED(tmpreg); \
1250  } while(0)
1251 
1252 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
1253  __IO uint32_t tmpreg; \
1254  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
1255  /* Delay after an RCC peripheral clock enabling */ \
1256  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
1257  UNUSED(tmpreg); \
1258  } while(0)
1259 
1260 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
1261  __IO uint32_t tmpreg; \
1262  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
1263  /* Delay after an RCC peripheral clock enabling */ \
1264  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
1265  UNUSED(tmpreg); \
1266  } while(0)
1267 
1268 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
1269  __IO uint32_t tmpreg; \
1270  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
1271  /* Delay after an RCC peripheral clock enabling */ \
1272  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
1273  UNUSED(tmpreg); \
1274  } while(0)
1275 
1276 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \
1277  __IO uint32_t tmpreg; \
1278  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
1279  /* Delay after an RCC peripheral clock enabling */ \
1280  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
1281  UNUSED(tmpreg); \
1282  } while(0)
1283 
1284 #define __HAL_RCC_SPI6_CLK_ENABLE() do { \
1285  __IO uint32_t tmpreg; \
1286  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
1287  /* Delay after an RCC peripheral clock enabling */ \
1288  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
1289  UNUSED(tmpreg); \
1290  } while(0)
1291 
1292 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \
1293  __IO uint32_t tmpreg; \
1294  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
1295  /* Delay after an RCC peripheral clock enabling */ \
1296  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
1297  UNUSED(tmpreg); \
1298  } while(0)
1299 
1300 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \
1301  __IO uint32_t tmpreg; \
1302  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
1303  /* Delay after an RCC peripheral clock enabling */ \
1304  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
1305  UNUSED(tmpreg); \
1306  } while(0)
1307 
1308 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1309 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \
1310  __IO uint32_t tmpreg; \
1311  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
1312  /* Delay after an RCC peripheral clock enabling */ \
1313  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
1314  UNUSED(tmpreg); \
1315  } while(0)
1316 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1317 
1318 #if defined (STM32F769xx) || defined (STM32F779xx)
1319 #define __HAL_RCC_DSI_CLK_ENABLE() do { \
1320  __IO uint32_t tmpreg; \
1321  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
1322  /* Delay after an RCC peripheral clock enabling */ \
1323  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
1324  UNUSED(tmpreg); \
1325  } while(0)
1326 #endif /* STM32F769xx || STM32F779xx */
1327 
1328 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1329 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
1330  __IO uint32_t tmpreg; \
1331  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
1332  /* Delay after an RCC peripheral clock enabling */ \
1333  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
1334  UNUSED(tmpreg); \
1335  } while(0)
1336 
1337 #define __HAL_RCC_MDIO_CLK_ENABLE() do { \
1338  __IO uint32_t tmpreg; \
1339  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\
1340  /* Delay after an RCC peripheral clock enabling */ \
1341  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\
1342  UNUSED(tmpreg); \
1343  } while(0)
1344 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1345 
1346 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
1347 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
1348 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
1349 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
1350 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1351 #define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN))
1352 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1353 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
1354 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
1355 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
1356 #define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))
1357 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
1358 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
1359 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
1360 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
1361 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
1362 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
1363 #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
1364 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
1365 #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
1366 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1367 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
1368 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1369 #if defined (STM32F769xx) || defined (STM32F779xx)
1370 #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))
1371 #endif /* STM32F769xx || STM32F779xx */
1372 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1373 #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))
1374 #define __HAL_RCC_MDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN))
1375 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1376 
1395 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
1396 #define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET)
1397 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET)
1398 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
1399 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
1400 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
1401 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET)
1402 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET)
1403 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET)
1404 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
1405 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
1406 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
1407 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
1408 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET)
1409 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
1410 #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
1411 #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
1412 
1413 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
1414 #define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET)
1415 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET)
1416 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
1417 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
1418 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
1419 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET)
1420 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET)
1421 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET)
1422 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
1423 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
1424 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
1425 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
1426 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET)
1427 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
1428 #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
1429 #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
1430 
1433 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
1434 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
1435 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
1436 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
1437 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
1438  __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
1439  __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
1440 
1444 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
1445 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
1446 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
1447 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
1448 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
1449  __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
1450  __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
1451 
1457 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
1458 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
1459 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
1460 
1461 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
1462 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
1463 #define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
1464 
1465 #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
1466 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
1467 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
1468 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
1469 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
1470 #endif /* STM32F756xx || STM32F777xx || STM32F779xx */
1471 
1472 #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1473 #define __HAL_RCC_JPEG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET)
1474 #define __HAL_RCC_JPEG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) == RESET)
1475 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1476 
1482 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
1483 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
1484 
1485 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
1486 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
1487 
1493 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
1494 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
1495 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
1496 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
1497 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
1498 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
1499 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
1500 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
1501 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
1502 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
1503 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1504 #define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET)
1505 #define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET)
1506 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1507 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
1508 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
1509 #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
1510 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
1511 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
1512 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
1513 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
1514 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
1515 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
1516 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
1517 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET)
1518 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
1519 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
1520 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
1521 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
1522 #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
1523 #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
1524 
1525 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
1526 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
1527 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
1528 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
1529 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
1530 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
1531 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
1532 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
1533 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
1534 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
1535 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1536 #define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET)
1537 #define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET)
1538 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1539 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
1540 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
1541 #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
1542 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
1543 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
1544 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
1545 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
1546 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
1547 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
1548 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
1549 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET)
1550 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
1551 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
1552 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
1553 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
1554 #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
1555 #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
1556 
1562 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
1563 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
1564 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
1565 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
1566 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
1567 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
1568 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
1569 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET)
1570 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
1571 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
1572 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
1573 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
1574 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
1575 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
1576 #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
1577 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
1578 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
1579 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1580 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
1581 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1582 #if defined (STM32F769xx) || defined (STM32F779xx)
1583 #define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)
1584 #endif /* STM32F769xx || STM32F779xx */
1585 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1586 #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET)
1587 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)
1588 #define __HAL_RCC_MDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET)
1589 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1590 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
1591 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
1592 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
1593 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
1594 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
1595 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
1596 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
1597 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET)
1598 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
1599 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
1600 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
1601 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
1602 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
1603 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
1604 #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
1605 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
1606 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
1607 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1608 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
1609 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1610 #if defined (STM32F769xx) || defined (STM32F779xx)
1611 #define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)
1612 #endif /* STM32F769xx || STM32F779xx */
1613 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1614 #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET)
1615 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)
1616 #define __HAL_RCC_MDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET)
1617 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1618 
1629 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
1630 #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
1631 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
1632 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
1633 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
1634 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
1635 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
1636 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
1637 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
1638 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
1639 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
1640 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
1641 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
1642 #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
1643 #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
1644 
1645 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
1646 #define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
1647 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
1648 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
1649 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
1650 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
1651 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
1652 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
1653 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
1654 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
1655 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
1656 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
1657 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
1658 #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
1659 #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
1660 
1663 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
1664 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
1665 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
1666 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
1667 
1668 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
1669 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
1670 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
1671 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
1672 
1673 #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1674 #define __HAL_RCC_JPEG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_JPEGRST))
1675 #define __HAL_RCC_JPEG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_JPEGRST))
1676 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1677 
1678 #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
1679 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
1680 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
1681 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
1682 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
1683 #endif /* STM32F756xx || STM32F777xx || STM32F779xx */
1684 
1687 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
1688 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
1689 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
1690 
1691 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
1692 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
1693 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
1694 
1697 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
1698 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
1699 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
1700 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
1701 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
1702 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
1703 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
1704 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
1705 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
1706 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
1707 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1708 #define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST))
1709 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1710 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
1711 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
1712 #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))
1713 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
1714 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
1715 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
1716 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
1717 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
1718 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
1719 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
1720 #define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST))
1721 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
1722 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
1723 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
1724 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
1725 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
1726 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
1727 
1728 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
1729 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
1730 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
1731 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
1732 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
1733 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
1734 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
1735 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
1736 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
1737 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
1738 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1739 #define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST))
1740 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1741 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
1742 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
1743 #define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
1744 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
1745 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
1746 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
1747 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
1748 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
1749 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
1750 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
1751 #define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST))
1752 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
1753 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
1754 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
1755 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
1756 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
1757 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
1758 
1761 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
1762 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
1763 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
1764 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
1765 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
1766 #define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST))
1767 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
1768 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
1769 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
1770 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
1771 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
1772 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
1773 #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
1774 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
1775 #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))
1776 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1777 #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
1778 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1779 
1780 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
1781 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
1782 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
1783 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
1784 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
1785 #define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST))
1786 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
1787 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
1788 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
1789 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
1790 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
1791 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
1792 #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
1793 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
1794 #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
1795 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1796 #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
1797 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1798 
1799 #if defined (STM32F769xx) || defined (STM32F779xx)
1800 #define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST))
1801 #define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))
1802 #endif /* STM32F769xx || STM32F779xx */
1803 
1804 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1805 #define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC2RST))
1806 #define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST))
1807 #define __HAL_RCC_MDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_MDIORST))
1808 
1809 #define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST))
1810 #define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))
1811 #define __HAL_RCC_MDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_MDIORST))
1812 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1813 
1828 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
1829 #define __HAL_RCC_AXI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN))
1830 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
1831 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
1832 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
1833 #define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN))
1834 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
1835 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
1836 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
1837 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
1838 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
1839 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
1840 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
1841 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
1842 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
1843 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
1844 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
1845 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
1846 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
1847 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
1848 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
1849 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
1850 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
1851 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
1852 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
1853 
1854 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
1855 #define __HAL_RCC_AXI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN))
1856 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
1857 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
1858 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
1859 #define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN))
1860 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
1861 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
1862 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
1863 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
1864 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
1865 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
1866 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
1867 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
1868 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
1869 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
1870 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
1871 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
1872 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
1873 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
1874 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
1875 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
1876 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
1877 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
1878 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
1879 
1886 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
1887 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
1888 
1889 #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1890 #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_JPEGLPEN))
1891 #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_JPEGLPEN))
1892 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1893 
1894 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
1895 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
1896 
1897 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
1898 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
1899 
1900 #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
1901 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
1902 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
1903 
1904 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
1905 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
1906 #endif /* STM32F756xx || STM32F777xx || STM32F779xx */
1907 
1914 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
1915 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
1916 
1917 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
1918 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
1919 
1926 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
1927 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
1928 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
1929 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
1930 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
1931 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
1932 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
1933 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
1934 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
1935 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
1936 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1937 #define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCLPEN))
1938 #define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN))
1939 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1940 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
1941 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
1942 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))
1943 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
1944 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
1945 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
1946 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
1947 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
1948 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
1949 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
1950 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN))
1951 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
1952 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
1953 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))
1954 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
1955 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
1956 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
1957 
1958 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
1959 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
1960 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
1961 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
1962 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
1963 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
1964 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
1965 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
1966 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
1967 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
1968 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
1969 #define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN))
1970 #define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN))
1971 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
1972 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
1973 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
1974 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
1975 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
1976 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
1977 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
1978 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
1979 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
1980 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
1981 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
1982 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN))
1983 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
1984 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
1985 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
1986 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
1987 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
1988 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
1989 
1996 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
1997 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
1998 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
1999 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
2000 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
2001 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
2002 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
2003 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC1LPEN))
2004 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
2005 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
2006 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
2007 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
2008 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
2009 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
2010 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
2011 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
2012 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))
2013 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
2014 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
2015 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
2016 
2017 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
2018 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
2019 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
2020 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
2021 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
2022 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
2023 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
2024 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN))
2025 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
2026 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
2027 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
2028 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
2029 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
2030 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
2031 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
2032 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
2033 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
2034 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
2035 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
2036 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
2037 #if defined (STM32F769xx) || defined (STM32F779xx)
2038 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN))
2039 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))
2040 #endif /* STM32F769xx || STM32F779xx */
2041 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
2042 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC2LPEN))
2043 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN))
2044 #define __HAL_RCC_MDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_MDIOLPEN))
2045 
2046 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN))
2047 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))
2048 #define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN))
2049 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
2050 
2069 #define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET)
2070 #define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET)
2071 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET)
2072 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET)
2073 #define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET)
2074 #define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET)
2075 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET)
2076 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET)
2077 #define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET)
2078 #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET)
2079 #define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET)
2080 #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET)
2081 #define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET)
2082 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET)
2083 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET)
2084 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET)
2085 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET)
2086 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET)
2087 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET)
2088 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET)
2089 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET)
2090 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET)
2091 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET)
2092 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET)
2093 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET)
2094 
2095 #define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET)
2096 #define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET)
2097 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET)
2098 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET)
2099 #define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET)
2100 #define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET)
2101 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET)
2102 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET)
2103 #define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET)
2104 #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET)
2105 #define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET)
2106 #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET)
2107 #define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET)
2108 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET)
2109 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET)
2110 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET)
2111 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET)
2112 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET)
2113 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET)
2114 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET)
2115 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET)
2116 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET)
2117 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET)
2118 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET)
2119 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET)
2120 
2127 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET)
2128 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET)
2129 
2130 #if defined(STM32F767xx) || defined(STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
2131 #define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET)
2132 #define __HAL_RCC_JPEG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) == RESET)
2133 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
2134 
2135 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET)
2136 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET)
2137 
2138 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET)
2139 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET)
2140 
2141 #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
2142 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET)
2143 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET)
2144 
2145 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET)
2146 #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET)
2147 #endif /* STM32F756xx || STM32F777xx || STM32F779xx */
2148 
2155 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET)
2156 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET)
2157 
2158 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET)
2159 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET)
2160 
2167 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET)
2168 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET)
2169 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET)
2170 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET)
2171 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET)
2172 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET)
2173 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET)
2174 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET)
2175 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET)
2176 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET)
2177 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
2178 #define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET)
2179 #define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET)
2180 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
2181 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET)
2182 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET)
2183 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET)
2184 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET)
2185 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET)
2186 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET)
2187 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET)
2188 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET)
2189 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET)
2190 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET)
2191 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET)
2192 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET)
2193 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET)
2194 #define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET)
2195 #define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET)
2196 #define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET)
2197 #define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET)
2198 
2199 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET)
2200 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET)
2201 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET)
2202 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET)
2203 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET)
2204 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET)
2205 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET)
2206 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET)
2207 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET)
2208 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET)
2209 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
2210 #define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET)
2211 #define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET)
2212 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
2213 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET)
2214 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET)
2215 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET)
2216 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET)
2217 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET)
2218 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET)
2219 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET)
2220 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET)
2221 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET)
2222 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET)
2223 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET)
2224 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET)
2225 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET)
2226 #define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET)
2227 #define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET)
2228 #define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET)
2229 #define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET)
2230 
2237 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET)
2238 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET)
2239 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET)
2240 #define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET)
2241 #define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET)
2242 #define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET)
2243 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET)
2244 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET)
2245 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET)
2246 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET)
2247 #define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET)
2248 #define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET)
2249 #define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET)
2250 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET)
2251 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET)
2252 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET)
2253 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET)
2254 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
2255 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET)
2256 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
2257 #if defined (STM32F769xx) || defined (STM32F779xx)
2258 #define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) != RESET)
2259 #endif /* STM32F769xx || STM32F779xx */
2260 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
2261 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET)
2262 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET)
2263 #define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET)
2264 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
2265 
2266 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET)
2267 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET)
2268 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET)
2269 #define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET)
2270 #define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET)
2271 #define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET)
2272 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET)
2273 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET)
2274 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET)
2275 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET)
2276 #define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET)
2277 #define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET)
2278 #define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET)
2279 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET)
2280 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET)
2281 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET)
2282 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET)
2283 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
2284 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET)
2285 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
2286 #if defined (STM32F769xx) || defined (STM32F779xx)
2287 #define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) == RESET)
2288 #endif /* STM32F769xx || STM32F779xx */
2289 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
2290 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET)
2291 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET)
2292 #define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET)
2293 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
2294 
2298 /*------------------------------- PLL Configuration --------------------------*/
2299 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
2300 
2329 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \
2330  (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \
2331  ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
2332  ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
2333  ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) | \
2334  ((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR))))
2335 #else
2336 
2363 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
2364  (RCC->PLLCFGR = (0x20000000 | (__RCC_PLLSource__) | (__PLLM__)| \
2365  ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
2366  ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
2367  ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
2368 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
2369 /*---------------------------------------------------------------------------------------------*/
2370 
2383 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\
2384  RCC->DCKCFGR1 |= (__PRESC__); \
2385  }while(0)
2386 
2390 #define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION))
2391 #define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION))
2392 
2408 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
2409  (RCC->PLLSAICFGR = ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) |\
2410  ((__PLLSAIP__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) |\
2411  ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) |\
2412  ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)))
2413 
2431 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
2432  (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
2433  ((__PLLI2SP__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) |\
2434  ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) |\
2435  ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
2436 
2443 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
2444 
2451 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
2452 
2460 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\
2461  MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__))
2462 
2478 #define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\
2479  MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__))
2480 
2493 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL)))
2494 
2495 
2511 #define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\
2512  MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__))
2513 
2514 
2527 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL)))
2528 
2529 
2532 #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
2533 
2536 #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
2537 
2540 #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
2541 
2545 #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
2546 
2550 #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
2551 
2557 #define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))
2558 
2567 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
2568  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
2569 
2576 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL)))
2577 
2586 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
2587  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
2588 
2595 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL)))
2596 
2605 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
2606  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
2607 
2614 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL)))
2615 
2624 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
2625  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))
2626 
2633 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL)))
2634 
2644 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
2645  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
2646 
2654 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL)))
2655 
2665 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
2666  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
2667 
2675 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL)))
2676 
2686 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
2687  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
2688 
2696 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL)))
2697 
2707 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
2708  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
2709 
2717 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL)))
2718 
2728 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
2729  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
2730 
2738 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL)))
2739 
2749 #define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \
2750  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__))
2751 
2759 #define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL)))
2760 
2770 #define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \
2771  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__))
2772 
2780 #define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL)))
2781 
2791 #define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \
2792  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__))
2793 
2801 #define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL)))
2802 
2812 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
2813  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
2814 
2822 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)))
2823 
2831 #define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \
2832  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))
2833 
2839 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)))
2840 
2848 #define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \
2849  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__))
2850 
2856 #define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)))
2857 
2865 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
2866  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
2867 
2873 #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL)))
2874 
2875 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
2876 
2882 #define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \
2883  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL, (uint32_t)(__SDMMC2_CLKSOURCE__))
2884 
2890 #define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL)))
2891 
2898 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \
2899  MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__))
2900 
2906 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL)))
2907 
2914 #define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \
2915  MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__))
2916 
2922 #define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL)))
2923 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
2924 
2925 #if defined (STM32F769xx) || defined (STM32F779xx)
2926 
2932 #define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, (uint32_t)(__DSI_CLKSOURCE__)))
2933 
2939 #define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL))
2940 #endif /* STM32F769xx || STM32F779xx */
2941 
2945 /* Exported functions --------------------------------------------------------*/
2949 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
2950 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
2951 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
2952 
2956 /* Private macros ------------------------------------------------------------*/
2963 #if defined(STM32F756xx) || defined(STM32F746xx)
2964 #define IS_RCC_PERIPHCLOCK(SELECTION) \
2965  ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
2966  (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \
2967  (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \
2968  (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
2969  (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
2970  (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
2971  (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
2972  (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
2973  (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \
2974  (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \
2975  (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \
2976  (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
2977  (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
2978  (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
2979  (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
2980  (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
2981  (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
2982  (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
2983  (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \
2984  (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
2985  (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
2986  (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \
2987  (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
2988 #elif defined(STM32F745xx)
2989 #define IS_RCC_PERIPHCLOCK(SELECTION) \
2990  ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
2991  (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \
2992  (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
2993  (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
2994  (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
2995  (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
2996  (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
2997  (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \
2998  (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \
2999  (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \
3000  (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
3001  (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
3002  (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
3003  (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
3004  (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
3005  (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
3006  (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
3007  (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \
3008  (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
3009  (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
3010  (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \
3011  (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
3012 #elif defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
3013 #define IS_RCC_PERIPHCLOCK(SELECTION) \
3014  ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
3015  (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \
3016  (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \
3017  (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
3018  (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
3019  (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
3020  (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
3021  (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
3022  (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \
3023  (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \
3024  (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \
3025  (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
3026  (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
3027  (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
3028  (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
3029  (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
3030  (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
3031  (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
3032  (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \
3033  (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
3034  (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
3035  (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \
3036  (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
3037  (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \
3038  (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \
3039  (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
3040 #elif defined (STM32F765xx)
3041 #define IS_RCC_PERIPHCLOCK(SELECTION) \
3042  ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
3043  (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \
3044  (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
3045  (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
3046  (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
3047  (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
3048  (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
3049  (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \
3050  (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \
3051  (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \
3052  (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
3053  (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
3054  (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
3055  (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
3056  (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
3057  (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
3058  (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
3059  (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \
3060  (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
3061  (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
3062  (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \
3063  (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
3064  (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \
3065  (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \
3066  (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
3067 #endif /* STM32F746xx || STM32F756xx */
3068 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
3069 #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\
3070  ((VALUE) == RCC_PLLI2SP_DIV4) ||\
3071  ((VALUE) == RCC_PLLI2SP_DIV6) ||\
3072  ((VALUE) == RCC_PLLI2SP_DIV8))
3073 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
3074 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
3075 
3076 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
3077 #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\
3078  ((VALUE) == RCC_PLLSAIP_DIV4) ||\
3079  ((VALUE) == RCC_PLLSAIP_DIV6) ||\
3080  ((VALUE) == RCC_PLLSAIP_DIV8))
3081 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
3082 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
3083 
3084 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
3085 
3086 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
3087 
3088 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
3089  ((VALUE) == RCC_PLLSAIDIVR_4) ||\
3090  ((VALUE) == RCC_PLLSAIDIVR_8) ||\
3091  ((VALUE) == RCC_PLLSAIDIVR_16))
3092 #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || \
3093  ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
3094 
3095 #define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \
3096  ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48))
3097 
3098 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
3099  ((SOURCE) == RCC_CECCLKSOURCE_LSE))
3100 #define IS_RCC_USART1CLKSOURCE(SOURCE) \
3101  (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
3102  ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
3103  ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
3104  ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
3105 
3106 #define IS_RCC_USART2CLKSOURCE(SOURCE) \
3107  (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \
3108  ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \
3109  ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
3110  ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
3111 #define IS_RCC_USART3CLKSOURCE(SOURCE) \
3112  (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \
3113  ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \
3114  ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
3115  ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
3116 
3117 #define IS_RCC_UART4CLKSOURCE(SOURCE) \
3118  (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \
3119  ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
3120  ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
3121  ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
3122 
3123 #define IS_RCC_UART5CLKSOURCE(SOURCE) \
3124  (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \
3125  ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
3126  ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
3127  ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
3128 
3129 #define IS_RCC_USART6CLKSOURCE(SOURCE) \
3130  (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) || \
3131  ((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) || \
3132  ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \
3133  ((SOURCE) == RCC_USART6CLKSOURCE_HSI))
3134 
3135 #define IS_RCC_UART7CLKSOURCE(SOURCE) \
3136  (((SOURCE) == RCC_UART7CLKSOURCE_PCLK1) || \
3137  ((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) || \
3138  ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \
3139  ((SOURCE) == RCC_UART7CLKSOURCE_HSI))
3140 
3141 #define IS_RCC_UART8CLKSOURCE(SOURCE) \
3142  (((SOURCE) == RCC_UART8CLKSOURCE_PCLK1) || \
3143  ((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) || \
3144  ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \
3145  ((SOURCE) == RCC_UART8CLKSOURCE_HSI))
3146 #define IS_RCC_I2C1CLKSOURCE(SOURCE) \
3147  (((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || \
3148  ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
3149  ((SOURCE) == RCC_I2C1CLKSOURCE_HSI))
3150 #define IS_RCC_I2C2CLKSOURCE(SOURCE) \
3151  (((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) || \
3152  ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
3153  ((SOURCE) == RCC_I2C2CLKSOURCE_HSI))
3154 
3155 #define IS_RCC_I2C3CLKSOURCE(SOURCE) \
3156  (((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) || \
3157  ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
3158  ((SOURCE) == RCC_I2C3CLKSOURCE_HSI))
3159 #define IS_RCC_I2C4CLKSOURCE(SOURCE) \
3160  (((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) || \
3161  ((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)|| \
3162  ((SOURCE) == RCC_I2C4CLKSOURCE_HSI))
3163 #define IS_RCC_LPTIM1CLK(SOURCE) \
3164  (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || \
3165  ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \
3166  ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \
3167  ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
3168 #define IS_RCC_CLK48SOURCE(SOURCE) \
3169  (((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) || \
3170  ((SOURCE) == RCC_CLK48SOURCE_PLL))
3171 #define IS_RCC_TIMPRES(VALUE) \
3172  (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \
3173  ((VALUE) == RCC_TIMPRES_ACTIVATED))
3174 
3175 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx)
3176 #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \
3177  ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \
3178  ((SOURCE) == RCC_SAI1CLKSOURCE_PIN))
3179 #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \
3180  ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \
3181  ((SOURCE) == RCC_SAI2CLKSOURCE_PIN))
3182 #endif /* STM32F745xx || STM32F746xx || STM32F756xx */
3183 
3184 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
3185 #define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
3186 
3187 #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \
3188  ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \
3189  ((SOURCE) == RCC_SAI1CLKSOURCE_PIN) || \
3190  ((SOURCE) == RCC_SAI1CLKSOURCE_PLLSRC))
3191 
3192 #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \
3193  ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \
3194  ((SOURCE) == RCC_SAI2CLKSOURCE_PIN) || \
3195  ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
3196 
3197 #define IS_RCC_SDMMC2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) || \
3198  ((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48))
3199 
3200 #define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_PCLK) || \
3201  ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYSCLK))
3202 
3203 #define IS_RCC_DFSDM1AUDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \
3204  ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI2))
3205 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
3206 
3207 #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
3208 #define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\
3209  ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))
3210 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
3211 
3227 #ifdef __cplusplus
3228 }
3229 #endif
3230 
3231 #endif /* __STM32F7xx_HAL_RCC_EX_H */
3232 
3233 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RCC_PLLSAIInitTypeDef::PLLSAIP
uint32_t PLLSAIP
Definition: stm32f7xx_hal_rcc_ex.h:130
RCC_PeriphCLKInitTypeDef::PeriphClockSelection
uint32_t PeriphClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:140
RCC_PeriphCLKInitTypeDef::Uart4ClockSelection
uint32_t Uart4ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:184
RCC_PeriphCLKInitTypeDef::I2sClockSelection
uint32_t I2sClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:163
RCC_PeriphCLKInitTypeDef::PLLI2S
RCC_PLLI2SInitTypeDef PLLI2S
Definition: stm32f7xx_hal_rcc_ex.h:143
RCC_PeriphCLKInitTypeDef::PLLSAIDivR
uint32_t PLLSAIDivR
Definition: stm32f7xx_hal_rcc_ex.h:157
HAL_RCCEx_PeriphCLKConfig
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
RCC_PLLInitTypeDef::PLLQ
uint32_t PLLQ
Definition: stm32f7xx_hal_rcc_ex.h:82
RCC_PLLSAIInitTypeDef::PLLSAIQ
uint32_t PLLSAIQ
Definition: stm32f7xx_hal_rcc_ex.h:122
RCC_PLLInitTypeDef
RCC PLL configuration structure definition.
Definition: stm32f7xx_hal_rcc_ex.h:65
RCC_PeriphCLKInitTypeDef::I2c2ClockSelection
uint32_t I2c2ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:202
RCC_PeriphCLKInitTypeDef::I2c1ClockSelection
uint32_t I2c1ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:199
RCC_PeriphCLKInitTypeDef::TIMPresSelection
uint32_t TIMPresSelection
Definition: stm32f7xx_hal_rcc_ex.h:166
RCC_PeriphCLKInitTypeDef::Usart1ClockSelection
uint32_t Usart1ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:175
RCC_PeriphCLKInitTypeDef::CecClockSelection
uint32_t CecClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:214
RCC_PLLI2SInitTypeDef::PLLI2SR
uint32_t PLLI2SR
Definition: stm32f7xx_hal_rcc_ex.h:100
RCC_PeriphCLKInitTypeDef::Uart5ClockSelection
uint32_t Uart5ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:187
RCC_PeriphCLKInitTypeDef::Uart7ClockSelection
uint32_t Uart7ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:193
RCC_PLLI2SInitTypeDef::PLLI2SQ
uint32_t PLLI2SQ
Definition: stm32f7xx_hal_rcc_ex.h:104
RCC_PLLSAIInitTypeDef::PLLSAIR
uint32_t PLLSAIR
Definition: stm32f7xx_hal_rcc_ex.h:126
RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition.
Definition: stm32f7xx_hal_rcc_ex.h:138
RCC_PLLInitTypeDef::PLLN
uint32_t PLLN
Definition: stm32f7xx_hal_rcc_ex.h:76
RCC_PeriphCLKInitTypeDef::Sdmmc1ClockSelection
uint32_t Sdmmc1ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:220
RCC_PeriphCLKInitTypeDef::Usart3ClockSelection
uint32_t Usart3ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:181
RCC_PLLI2SInitTypeDef
PLLI2S Clock structure definition.
Definition: stm32f7xx_hal_rcc_ex.h:94
RCC_PeriphCLKInitTypeDef::Clk48ClockSelection
uint32_t Clk48ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:217
HAL_RCCEx_GetPeriphCLKConfig
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
RCC_PeriphCLKInitTypeDef::I2c4ClockSelection
uint32_t I2c4ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:208
RCC_PeriphCLKInitTypeDef::Sai1ClockSelection
uint32_t Sai1ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:169
RCC_PLLInitTypeDef::PLLP
uint32_t PLLP
Definition: stm32f7xx_hal_rcc_ex.h:79
RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection
uint32_t Lptim1ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:211
RCC_PeriphCLKInitTypeDef::PLLSAIDivQ
uint32_t PLLSAIDivQ
Definition: stm32f7xx_hal_rcc_ex.h:153
RCC_PLLI2SInitTypeDef::PLLI2SP
uint32_t PLLI2SP
Definition: stm32f7xx_hal_rcc_ex.h:108
RCC_PLLI2SInitTypeDef::PLLI2SN
uint32_t PLLI2SN
Definition: stm32f7xx_hal_rcc_ex.h:96
HAL_RCCEx_GetPeriphCLKFreq
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
stm32f7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
RCC_PeriphCLKInitTypeDef::Sai2ClockSelection
uint32_t Sai2ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:172
RCC_PLLSAIInitTypeDef
PLLSAI Clock structure definition.
Definition: stm32f7xx_hal_rcc_ex.h:116
RCC_PeriphCLKInitTypeDef::PLLI2SDivQ
uint32_t PLLI2SDivQ
Definition: stm32f7xx_hal_rcc_ex.h:149
RCC_PeriphCLKInitTypeDef::I2c3ClockSelection
uint32_t I2c3ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:205
RCC_PLLInitTypeDef::PLLM
uint32_t PLLM
Definition: stm32f7xx_hal_rcc_ex.h:73
RCC_PeriphCLKInitTypeDef::RTCClockSelection
uint32_t RTCClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:160
RCC_PLLSAIInitTypeDef::PLLSAIN
uint32_t PLLSAIN
Definition: stm32f7xx_hal_rcc_ex.h:118
RCC_PeriphCLKInitTypeDef::Uart8ClockSelection
uint32_t Uart8ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:196
RCC_PLLInitTypeDef::PLLSource
uint32_t PLLSource
Definition: stm32f7xx_hal_rcc_ex.h:70
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32f7xx_hal_def.h:56
RCC_PeriphCLKInitTypeDef::Usart2ClockSelection
uint32_t Usart2ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:178
RCC_PLLInitTypeDef::PLLState
uint32_t PLLState
Definition: stm32f7xx_hal_rcc_ex.h:67
RCC_PeriphCLKInitTypeDef::Usart6ClockSelection
uint32_t Usart6ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:190
RCC_PeriphCLKInitTypeDef::PLLSAI
RCC_PLLSAIInitTypeDef PLLSAI
Definition: stm32f7xx_hal_rcc_ex.h:146
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