STM32F769IDiscovery  1.00
uDANTE Audio Networking with STM32F7 DISCO board
Modules | Macros
RCCEx Exported Macros
STM32F7xx_HAL_Driver » RCCEx

Modules

 RCCEx_Peripheral_Clock_Enable_Disable
 Enables or disables the AHB/APB peripheral clock.
 
 Peripheral Clock Enable Disable Status
 Get the enable or disable status of the AHB/APB peripheral clock.
 
 RCCEx Force Release Peripheral Reset
 Forces or releases AHB/APB peripheral reset.
 
 RCCEx Peripheral Clock Sleep Enable Disable
 Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode.
 
 AHB/APB Peripheral Clock Sleep Enable Disable Status
 Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode.
 

Macros

#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)
 Macro to configure the main PLL clock source, multiplication and division factors. More...
 
#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__)
 Macro to configure the Timers clocks prescalers. More...
 
#define __HAL_RCC_PLLSAI_ENABLE()   (RCC->CR |= (RCC_CR_PLLSAION))
 Macros to Enable or Disable the PLLISAI. More...
 
#define __HAL_RCC_PLLSAI_DISABLE()   (RCC->CR &= ~(RCC_CR_PLLSAION))
 
#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__)
 Macro to configure the PLLSAI clock multiplication and division factors. More...
 
#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__)
 Macro to configure the PLLI2S clock multiplication and division factors. More...
 
#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__)   (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
 Macro to configure the SAI clock Divider coming from PLLI2S. More...
 
#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__)   (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
 Macro to configure the SAI clock Divider coming from PLLSAI. More...
 
#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)   MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__))
 Macro to configure the LTDC clock Divider coming from PLLSAI. More...
 
#define __HAL_RCC_SAI1_CONFIG(__SOURCE__)   MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__))
 Macro to configure SAI1 clock source selection. More...
 
#define __HAL_RCC_GET_SAI1_SOURCE()   ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL)))
 Macro to get the SAI1 clock source. More...
 
#define __HAL_RCC_SAI2_CONFIG(__SOURCE__)   MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__))
 Macro to configure SAI2 clock source selection. More...
 
#define __HAL_RCC_GET_SAI2_SOURCE()   ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL)))
 Macro to get the SAI2 clock source. More...
 
#define __HAL_RCC_PLLSAI_ENABLE_IT()   (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
 Enable PLLSAI_RDY interrupt. More...
 
#define __HAL_RCC_PLLSAI_DISABLE_IT()   (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
 Disable PLLSAI_RDY interrupt. More...
 
#define __HAL_RCC_PLLSAI_CLEAR_IT()   (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
 Clear the PLLSAI RDY interrupt pending bits. More...
 
#define __HAL_RCC_PLLSAI_GET_IT()   ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
 Check the PLLSAI RDY interrupt has occurred or not. More...
 
#define __HAL_RCC_PLLSAI_GET_FLAG()   ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
 Check PLLSAI RDY flag is set or not. More...
 
#define __HAL_RCC_GET_I2SCLKSOURCE()   (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))
 Macro to Get I2S clock source selection. More...
 
#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__)   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
 Macro to configure the I2C1 clock (I2C1CLK). More...
 
#define __HAL_RCC_GET_I2C1_SOURCE()   ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL)))
 Macro to get the I2C1 clock source. More...
 
#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__)   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
 Macro to configure the I2C2 clock (I2C2CLK). More...
 
#define __HAL_RCC_GET_I2C2_SOURCE()   ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL)))
 Macro to get the I2C2 clock source. More...
 
#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__)   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
 Macro to configure the I2C3 clock (I2C3CLK). More...
 
#define __HAL_RCC_GET_I2C3_SOURCE()   ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL)))
 macro to get the I2C3 clock source. More...
 
#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__)   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))
 Macro to configure the I2C4 clock (I2C4CLK). More...
 
#define __HAL_RCC_GET_I2C4_SOURCE()   ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL)))
 macro to get the I2C4 clock source. More...
 
#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__)   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
 Macro to configure the USART1 clock (USART1CLK). More...
 
#define __HAL_RCC_GET_USART1_SOURCE()   ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL)))
 macro to get the USART1 clock source. More...
 
#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__)   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
 Macro to configure the USART2 clock (USART2CLK). More...
 
#define __HAL_RCC_GET_USART2_SOURCE()   ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL)))
 macro to get the USART2 clock source. More...
 
#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__)   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
 Macro to configure the USART3 clock (USART3CLK). More...
 
#define __HAL_RCC_GET_USART3_SOURCE()   ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL)))
 macro to get the USART3 clock source. More...
 
#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__)   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
 Macro to configure the UART4 clock (UART4CLK). More...
 
#define __HAL_RCC_GET_UART4_SOURCE()   ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL)))
 macro to get the UART4 clock source. More...
 
#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__)   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
 Macro to configure the UART5 clock (UART5CLK). More...
 
#define __HAL_RCC_GET_UART5_SOURCE()   ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL)))
 macro to get the UART5 clock source. More...
 
#define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__)   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__))
 Macro to configure the USART6 clock (USART6CLK). More...
 
#define __HAL_RCC_GET_USART6_SOURCE()   ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL)))
 macro to get the USART6 clock source. More...
 
#define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__)   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__))
 Macro to configure the UART7 clock (UART7CLK). More...
 
#define __HAL_RCC_GET_UART7_SOURCE()   ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL)))
 macro to get the UART7 clock source. More...
 
#define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__)   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__))
 Macro to configure the UART8 clock (UART8CLK). More...
 
#define __HAL_RCC_GET_UART8_SOURCE()   ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL)))
 macro to get the UART8 clock source. More...
 
#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__)   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
 Macro to configure the LPTIM1 clock (LPTIM1CLK). More...
 
#define __HAL_RCC_GET_LPTIM1_SOURCE()   ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)))
 macro to get the LPTIM1 clock source. More...
 
#define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__)   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))
 Macro to configure the CEC clock (CECCLK). More...
 
#define __HAL_RCC_GET_CEC_SOURCE()   ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)))
 macro to get the CEC clock source. More...
 
#define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__)   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__))
 Macro to configure the CLK48 source (CLK48CLK). More...
 
#define __HAL_RCC_GET_CLK48_SOURCE()   ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)))
 macro to get the CLK48 source. More...
 
#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__)   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
 Macro to configure the SDMMC1 clock (SDMMC1CLK). More...
 
#define __HAL_RCC_GET_SDMMC1_SOURCE()   ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL)))
 macro to get the SDMMC1 clock source. More...
 

Detailed Description

Macro Definition Documentation

#define __HAL_RCC_CEC_CONFIG (   __CEC_CLKSOURCE__)    MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))

Macro to configure the CEC clock (CECCLK).

Parameters
<strong>CEC_CLKSOURCE</strong>specifies the CEC clock source. This parameter can be one of the following values:
  • RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
  • RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock

Definition at line 2831 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CLK48_CONFIG (   __CLK48_SOURCE__)    MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__))

Macro to configure the CLK48 source (CLK48CLK).

Parameters
<strong>CLK48_SOURCE</strong>specifies the CLK48 clock source. This parameter can be one of the following values:
  • RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source
  • RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source

Definition at line 2848 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_CEC_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)))

macro to get the CEC clock source.

Return values
Theclock source can be one of the following values:
  • RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
  • RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock

Definition at line 2839 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_CLK48_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)))

macro to get the CLK48 source.

Return values
Theclock source can be one of the following values:
  • RCC_CLK48SOURCE_PLL: PLL used as CLK48 source
  • RCC_CLK48SOURCE_PLLSAIP: PLLSAIP used as CLK48 source

Definition at line 2856 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_I2C1_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL)))

Macro to get the I2C1 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock

Definition at line 2576 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_I2C2_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL)))

Macro to get the I2C2 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock

Definition at line 2595 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_I2C3_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL)))

macro to get the I2C3 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock

Definition at line 2614 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_I2C4_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL)))

macro to get the I2C4 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
  • RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
  • RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock

Definition at line 2633 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_I2SCLKSOURCE ( )    (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))

Macro to Get I2S clock source selection.

Return values
Theclock source can be one of the following values:
  • RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
  • RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source

Definition at line 2557 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_LPTIM1_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)))

macro to get the LPTIM1 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock

Definition at line 2822 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_SAI1_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL)))

Macro to get the SAI1 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
  • RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
  • RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
  • RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI1 clock.
Note
The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices

Definition at line 2493 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_SAI2_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL)))

Macro to get the SAI2 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
  • RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
  • RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin used as SAI2 clock.
  • RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
Note
The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices

Definition at line 2527 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_SDMMC1_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL)))

macro to get the SDMMC1 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock
  • RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock

Definition at line 2873 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_UART4_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL)))

macro to get the UART4 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
  • RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
  • RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock

Definition at line 2717 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_UART5_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL)))

macro to get the UART5 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
  • RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
  • RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
  • RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock

Definition at line 2738 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_UART7_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL)))

macro to get the UART7 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
  • RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
  • RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
  • RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock

Definition at line 2780 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_UART8_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL)))

macro to get the UART8 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
  • RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
  • RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
  • RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock

Definition at line 2801 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_USART1_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL)))

macro to get the USART1 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
  • RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
  • RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock

Definition at line 2654 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_USART2_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL)))

macro to get the USART2 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
  • RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
  • RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock

Definition at line 2675 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_USART3_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL)))

macro to get the USART3 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
  • RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
  • RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock

Definition at line 2696 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GET_USART6_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL)))

macro to get the USART6 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
  • RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
  • RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
  • RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock

Definition at line 2759 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C1_CONFIG (   __I2C1_CLKSOURCE__)    MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))

Macro to configure the I2C1 clock (I2C1CLK).

Parameters
<strong>I2C1_CLKSOURCE</strong>specifies the I2C1 clock source. This parameter can be one of the following values:
  • RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock

Definition at line 2567 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_CONFIG (   __I2C2_CLKSOURCE__)    MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))

Macro to configure the I2C2 clock (I2C2CLK).

Parameters
<strong>I2C2_CLKSOURCE</strong>specifies the I2C2 clock source. This parameter can be one of the following values:
  • RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock

Definition at line 2586 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C3_CONFIG (   __I2C3_CLKSOURCE__)    MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))

Macro to configure the I2C3 clock (I2C3CLK).

Parameters
<strong>I2C3_CLKSOURCE</strong>specifies the I2C3 clock source. This parameter can be one of the following values:
  • RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock

Definition at line 2605 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C4_CONFIG (   __I2C4_CLKSOURCE__)    MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))

Macro to configure the I2C4 clock (I2C4CLK).

Parameters
<strong>I2C4_CLKSOURCE</strong>specifies the I2C4 clock source. This parameter can be one of the following values:
  • RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
  • RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
  • RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock

Definition at line 2624 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_LPTIM1_CONFIG (   __LPTIM1_CLKSOURCE__)    MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))

Macro to configure the LPTIM1 clock (LPTIM1CLK).

Parameters
<strong>LPTIM1_CLKSOURCE</strong>specifies the LPTIM1 clock source. This parameter can be one of the following values:
  • RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock

Definition at line 2812 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_PLL_CONFIG (   __RCC_PLLSource__,
  __PLLM__,
  __PLLN__,
  __PLLP__,
  __PLLQ__ 
)
Value:
(RCC->PLLCFGR = (0x20000000 | (__RCC_PLLSource__) | (__PLLM__)| \
((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
RCC_PLLCFGR_PLLN
#define RCC_PLLCFGR_PLLN
Definition: stm32f745xx.h:5213
RCC
#define RCC
Definition: stm32f745xx.h:1325
POSITION_VAL
#define POSITION_VAL(VAL)
Definition: stm32f7xx.h:192
RCC_PLLCFGR_PLLP
#define RCC_PLLCFGR_PLLP
Definition: stm32f745xx.h:5223
RCC_PLLCFGR_PLLQ
#define RCC_PLLCFGR_PLLQ
Definition: stm32f745xx.h:5229

Macro to configure the main PLL clock source, multiplication and division factors.

Note
This function must be used only when the main PLL is disabled.
Parameters
<strong>RCC_PLLSource</strong>specifies the PLL entry clock source. This parameter can be one of the following values:
  • RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Note
This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
Parameters
<strong>PLLM</strong>specifies the division factor for PLL VCO input clock This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Note
You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter.
Parameters
<strong>PLLN</strong>specifies the multiplication factor for PLL VCO output clock This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Note
You have to set the PLLN parameter correctly to ensure that the VCO output frequency is between 100 and 432 MHz.
Parameters
<strong>PLLP</strong>specifies the division factor for main system clock (SYSCLK) This parameter must be a number in the range {2, 4, 6, or 8}.
Note
You have to set the PLLP parameter correctly to not exceed 216 MHz on the System clock frequency.
Parameters
<strong>PLLQ</strong>specifies the division factor for OTG FS, SDMMC and RNG clocks This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Note
If the USB OTG FS is used in your application, you have to set the PLLQ parameter correctly to have 48 MHz clock for the USB. However, the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work correctly.

Definition at line 2363 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLI2S_CONFIG (   __PLLI2SN__,
  __PLLI2SP__,
  __PLLI2SQ__,
  __PLLI2SR__ 
)
Value:
(RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
((__PLLI2SP__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) |\
((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) |\
((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
RCC
#define RCC
Definition: stm32f745xx.h:1325
POSITION_VAL
#define POSITION_VAL(VAL)
Definition: stm32f7xx.h:192
RCC_PLLI2SCFGR_PLLI2SN
#define RCC_PLLI2SCFGR_PLLI2SN
Definition: stm32f745xx.h:5631
RCC_PLLI2SCFGR_PLLI2SQ
#define RCC_PLLI2SCFGR_PLLI2SQ
Definition: stm32f745xx.h:5644
RCC_PLLI2SCFGR_PLLI2SP
#define RCC_PLLI2SCFGR_PLLI2SP
Definition: stm32f745xx.h:5641
RCC_PLLI2SCFGR_PLLI2SR
#define RCC_PLLI2SCFGR_PLLI2SR
Definition: stm32f745xx.h:5649

Macro to configure the PLLI2S clock multiplication and division factors.

Note
This macro must be used only when the PLLI2S is disabled.
PLLI2S clock source is common with the main PLL (configured in HAL_RCC_ClockConfig() API)
Parameters
<strong>PLLI2SN</strong>specifies the multiplication factor for PLLI2S VCO output clock. This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Note
You have to set the PLLI2SN parameter correctly to ensure that the VCO output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
Parameters
<strong>PLLI2SP</strong>specifies the division factor for SPDDIF-RX clock. This parameter can be a value of RCCEx PLLI2SP Clock Divider.
<strong>PLLI2SQ</strong>specifies the division factor for SAI clock. This parameter must be a number between Min_Data = 2 and Max_Data = 15.
<strong>PLLI2SR</strong>specifies the division factor for I2S clock This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Note
You have to set the PLLI2SR parameter correctly to not exceed 192 MHz on the I2S clock frequency.

Definition at line 2431 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG (   __PLLI2SDivQ__)    (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))

Macro to configure the SAI clock Divider coming from PLLI2S.

Note
This function must be called before enabling the PLLI2S.
Parameters
<strong>PLLI2SDivQ</strong>specifies the PLLI2S division factor for SAI1 clock . This parameter must be a number between 1 and 32. SAI1 clock frequency = f(PLLI2SQ) / PLLI2SDivQ

Definition at line 2443 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI_CLEAR_IT ( )    (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))

Clear the PLLSAI RDY interrupt pending bits.

Definition at line 2540 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI_CONFIG (   __PLLSAIN__,
  __PLLSAIP__,
  __PLLSAIQ__,
  __PLLSAIR__ 
)
Value:
(RCC->PLLSAICFGR = ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) |\
((__PLLSAIP__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) |\
((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) |\
((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)))
RCC_PLLSAICFGR_PLLSAIN
#define RCC_PLLSAICFGR_PLLSAIN
Definition: stm32f745xx.h:5655
RCC_PLLSAICFGR_PLLSAIP
#define RCC_PLLSAICFGR_PLLSAIP
Definition: stm32f745xx.h:5665
RCC
#define RCC
Definition: stm32f745xx.h:1325
POSITION_VAL
#define POSITION_VAL(VAL)
Definition: stm32f7xx.h:192
RCC_PLLSAICFGR_PLLSAIR
#define RCC_PLLSAICFGR_PLLSAIR
Definition: stm32f745xx.h:5673
RCC_PLLSAICFGR_PLLSAIQ
#define RCC_PLLSAICFGR_PLLSAIQ
Definition: stm32f745xx.h:5668

Macro to configure the PLLSAI clock multiplication and division factors.

Note
This function must be used only when the PLLSAI is disabled.
PLLSAI clock source is common with the main PLL (configured in RCC_PLLConfig function )
Parameters
<strong>PLLSAIN</strong>specifies the multiplication factor for PLLSAI VCO output clock. This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Note
You have to set the PLLSAIN parameter correctly to ensure that the VCO output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
Parameters
<strong>PLLSAIP</strong>specifies the division factor for USB, RNG, SDMMC clocks This parameter can be a value of RCCEx PLLSAIP Clock Divider.
<strong>PLLSAIQ</strong>specifies the division factor for SAI clock This parameter must be a number between Min_Data = 2 and Max_Data = 15.
<strong>PLLSAIR</strong>specifies the division factor for LTDC clock This parameter must be a number between Min_Data = 2 and Max_Data = 7.

Definition at line 2408 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI_DISABLE ( )    (RCC->CR &= ~(RCC_CR_PLLSAION))

Definition at line 2391 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI_DISABLE_IT ( )    (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))

Disable PLLSAI_RDY interrupt.

Definition at line 2536 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI_ENABLE ( )    (RCC->CR |= (RCC_CR_PLLSAION))

Macros to Enable or Disable the PLLISAI.

Note
The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.

Definition at line 2390 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI_ENABLE_IT ( )    (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))

Enable PLLSAI_RDY interrupt.

Definition at line 2532 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI_GET_FLAG ( )    ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))

Check PLLSAI RDY flag is set or not.

Return values
Thenew state (TRUE or FALSE).

Definition at line 2550 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI_GET_IT ( )    ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))

Check the PLLSAI RDY interrupt has occurred or not.

Return values
Thenew state (TRUE or FALSE).

Definition at line 2545 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG (   __PLLSAIDivQ__)    (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))

Macro to configure the SAI clock Divider coming from PLLSAI.

Note
This function must be called before enabling the PLLSAI.
Parameters
<strong>PLLSAIDivQ</strong>specifies the PLLSAI division factor for SAI1 clock . This parameter must be a number between Min_Data = 1 and Max_Data = 32. SAI1 clock frequency = f(PLLSAIQ) / PLLSAIDivQ

Definition at line 2451 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG (   __PLLSAIDivR__)    MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__))

Macro to configure the LTDC clock Divider coming from PLLSAI.

Note
This function must be called before enabling the PLLSAI.
Parameters
<strong>PLLSAIDivR</strong>specifies the PLLSAI division factor for LTDC clock . This parameter can be a value of RCCEx PLLSAI DIVR. LTDC clock frequency = f(PLLSAIR) / PLLSAIDivR

Definition at line 2460 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI1_CONFIG (   __SOURCE__)    MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__))

Macro to configure SAI1 clock source selection.

Note
This function must be called before enabling PLLSAI, PLLI2S and the SAI clock.
Parameters
<strong>SOURCE</strong>specifies the SAI1 clock source. This parameter can be one of the following values:
  • RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
  • RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
  • RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
  • RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI1 clock.
Note
The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices

Definition at line 2478 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI2_CONFIG (   __SOURCE__)    MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__))

Macro to configure SAI2 clock source selection.

Note
This function must be called before enabling PLLSAI, PLLI2S and the SAI clock.
Parameters
<strong>SOURCE</strong>specifies the SAI2 clock source. This parameter can be one of the following values:
  • RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
  • RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
  • RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin used as SAI2 clock.
  • RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
Note
The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices

Definition at line 2511 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SDMMC1_CONFIG (   __SDMMC1_CLKSOURCE__)    MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))

Macro to configure the SDMMC1 clock (SDMMC1CLK).

Parameters
<strong>SDMMC1_CLKSOURCE</strong>specifies the SDMMC1 clock source. This parameter can be one of the following values:
  • RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock
  • RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock

Definition at line 2865 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIMCLKPRESCALER (   __PRESC__)
Value:
do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\
RCC->DCKCFGR1 |= (__PRESC__); \
}while(0)
RCC_DCKCFGR1_TIMPRE
#define RCC_DCKCFGR1_TIMPRE
Definition: stm32f745xx.h:5705
RCC
#define RCC
Definition: stm32f745xx.h:1325

Macro to configure the Timers clocks prescalers.

Parameters
<strong>PRESC</strong>: specifies the Timers clocks prescalers selection This parameter can be one of the following values:
  • RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is equal to HPRE if PPREx is corresponding to division by 1 or 2, else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to division by 4 or more.
  • RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding to division by 8 or more.

Definition at line 2383 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART4_CONFIG (   __UART4_CLKSOURCE__)    MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))

Macro to configure the UART4 clock (UART4CLK).

Parameters
<strong>UART4_CLKSOURCE</strong>specifies the UART4 clock source. This parameter can be one of the following values:
  • RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
  • RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
  • RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock

Definition at line 2707 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART5_CONFIG (   __UART5_CLKSOURCE__)    MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))

Macro to configure the UART5 clock (UART5CLK).

Parameters
<strong>UART5_CLKSOURCE</strong>specifies the UART5 clock source. This parameter can be one of the following values:
  • RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
  • RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
  • RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
  • RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock

Definition at line 2728 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART7_CONFIG (   __UART7_CLKSOURCE__)    MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__))

Macro to configure the UART7 clock (UART7CLK).

Parameters
<strong>UART7_CLKSOURCE</strong>specifies the UART7 clock source. This parameter can be one of the following values:
  • RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
  • RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
  • RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
  • RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock

Definition at line 2770 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART8_CONFIG (   __UART8_CLKSOURCE__)    MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__))

Macro to configure the UART8 clock (UART8CLK).

Parameters
<strong>UART8_CLKSOURCE</strong>specifies the UART8 clock source. This parameter can be one of the following values:
  • RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
  • RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
  • RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
  • RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock

Definition at line 2791 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART1_CONFIG (   __USART1_CLKSOURCE__)    MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))

Macro to configure the USART1 clock (USART1CLK).

Parameters
<strong>USART1_CLKSOURCE</strong>specifies the USART1 clock source. This parameter can be one of the following values:
  • RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
  • RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
  • RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock

Definition at line 2644 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART2_CONFIG (   __USART2_CLKSOURCE__)    MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))

Macro to configure the USART2 clock (USART2CLK).

Parameters
<strong>USART2_CLKSOURCE</strong>specifies the USART2 clock source. This parameter can be one of the following values:
  • RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
  • RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
  • RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock

Definition at line 2665 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART3_CONFIG (   __USART3_CLKSOURCE__)    MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))

Macro to configure the USART3 clock (USART3CLK).

Parameters
<strong>USART3_CLKSOURCE</strong>specifies the USART3 clock source. This parameter can be one of the following values:
  • RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
  • RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
  • RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock

Definition at line 2686 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART6_CONFIG (   __USART6_CLKSOURCE__)    MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__))

Macro to configure the USART6 clock (USART6CLK).

Parameters
<strong>USART6_CLKSOURCE</strong>specifies the USART6 clock source. This parameter can be one of the following values:
  • RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
  • RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
  • RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
  • RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock

Definition at line 2749 of file stm32f7xx_hal_rcc_ex.h.

Generated by   doxygen 1.8.11