Peripheral Clock Enable Disable Status

Get the enable or disable status of the AHB/APB peripheral clock. More...

Macros
#define	__HAL_RCC_BKPSRAM_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
	Get the enable or disable status of the AHB1 peripheral clock. More...
#define	__HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET)
#define	__HAL_RCC_DMA2_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET)
#define	__HAL_RCC_DMA2D_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
#define	__HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
#define	__HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
#define	__HAL_RCC_GPIOA_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET)
#define	__HAL_RCC_GPIOB_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET)
#define	__HAL_RCC_GPIOC_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET)
#define	__HAL_RCC_GPIOD_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
#define	__HAL_RCC_GPIOE_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
#define	__HAL_RCC_GPIOF_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
#define	__HAL_RCC_GPIOG_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
#define	__HAL_RCC_GPIOH_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET)
#define	__HAL_RCC_GPIOI_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
#define	__HAL_RCC_GPIOJ_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
#define	__HAL_RCC_GPIOK_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
#define	__HAL_RCC_BKPSRAM_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
#define	__HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET)
#define	__HAL_RCC_DMA2_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET)
#define	__HAL_RCC_DMA2D_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
#define	__HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
#define	__HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
#define	__HAL_RCC_GPIOA_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET)
#define	__HAL_RCC_GPIOB_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET)
#define	__HAL_RCC_GPIOC_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET)
#define	__HAL_RCC_GPIOD_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
#define	__HAL_RCC_GPIOE_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
#define	__HAL_RCC_GPIOF_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
#define	__HAL_RCC_GPIOG_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
#define	__HAL_RCC_GPIOH_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET)
#define	__HAL_RCC_GPIOI_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
#define	__HAL_RCC_GPIOJ_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
#define	__HAL_RCC_GPIOK_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
#define	__HAL_RCC_ETHMAC_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
	Enable ETHERNET clock. More...
#define	__HAL_RCC_ETHMACTX_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
#define	__HAL_RCC_ETHMACRX_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
#define	__HAL_RCC_ETHMACPTP_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
#define	__HAL_RCC_ETH_IS_CLK_ENABLED()
#define	__HAL_RCC_ETHMAC_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
	Disable ETHERNET clock. More...
#define	__HAL_RCC_ETHMACTX_IS_CLK_DISABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
#define	__HAL_RCC_ETHMACRX_IS_CLK_DISABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
#define	__HAL_RCC_ETHMACPTP_IS_CLK_DISABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
#define	__HAL_RCC_ETH_IS_CLK_DISABLED()
#define	__HAL_RCC_DCMI_IS_CLK_ENABLED()    ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
	Get the enable or disable status of the AHB2 peripheral clock. More...
#define	__HAL_RCC_RNG_IS_CLK_ENABLED()    ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
#define	__HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
#define	__HAL_RCC_DCMI_IS_CLK_DISABLED()    ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
#define	__HAL_RCC_RNG_IS_CLK_DISABLED()    ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
#define	__HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
#define	__HAL_RCC_FMC_IS_CLK_ENABLED()    ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
	Get the enable or disable status of the AHB3 peripheral clock. More...
#define	__HAL_RCC_QSPI_IS_CLK_ENABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
#define	__HAL_RCC_FMC_IS_CLK_DISABLED()    ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
#define	__HAL_RCC_QSPI_IS_CLK_DISABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
#define	__HAL_RCC_TIM2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
	Get the enable or disable status of the APB1 peripheral clock. More...
#define	__HAL_RCC_TIM3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
#define	__HAL_RCC_TIM4_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
#define	__HAL_RCC_TIM5_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
#define	__HAL_RCC_TIM6_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
#define	__HAL_RCC_TIM7_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
#define	__HAL_RCC_TIM12_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
#define	__HAL_RCC_TIM13_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
#define	__HAL_RCC_TIM14_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
#define	__HAL_RCC_LPTIM1_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
#define	__HAL_RCC_SPI2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
#define	__HAL_RCC_SPI3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
#define	__HAL_RCC_SPDIFRX_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
#define	__HAL_RCC_USART2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
#define	__HAL_RCC_USART3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
#define	__HAL_RCC_UART4_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
#define	__HAL_RCC_UART5_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
#define	__HAL_RCC_I2C1_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
#define	__HAL_RCC_I2C2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
#define	__HAL_RCC_I2C3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
#define	__HAL_RCC_I2C4_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET)
#define	__HAL_RCC_CAN1_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
#define	__HAL_RCC_CAN2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
#define	__HAL_RCC_CEC_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
#define	__HAL_RCC_DAC_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
#define	__HAL_RCC_UART7_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
#define	__HAL_RCC_UART8_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
#define	__HAL_RCC_TIM2_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
#define	__HAL_RCC_TIM3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
#define	__HAL_RCC_TIM4_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
#define	__HAL_RCC_TIM5_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
#define	__HAL_RCC_TIM6_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
#define	__HAL_RCC_TIM7_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
#define	__HAL_RCC_TIM12_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
#define	__HAL_RCC_TIM13_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
#define	__HAL_RCC_TIM14_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
#define	__HAL_RCC_LPTIM1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
#define	__HAL_RCC_SPI2_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
#define	__HAL_RCC_SPI3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
#define	__HAL_RCC_SPDIFRX_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
#define	__HAL_RCC_USART2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
#define	__HAL_RCC_USART3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
#define	__HAL_RCC_UART4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
#define	__HAL_RCC_UART5_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
#define	__HAL_RCC_I2C1_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
#define	__HAL_RCC_I2C2_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
#define	__HAL_RCC_I2C3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
#define	__HAL_RCC_I2C4_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET)
#define	__HAL_RCC_CAN1_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
#define	__HAL_RCC_CAN2_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
#define	__HAL_RCC_CEC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
#define	__HAL_RCC_DAC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
#define	__HAL_RCC_UART7_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
#define	__HAL_RCC_UART8_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
#define	__HAL_RCC_TIM1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
	Get the enable or disable status of the APB2 peripheral clock. More...
#define	__HAL_RCC_TIM8_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
#define	__HAL_RCC_USART1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
#define	__HAL_RCC_USART6_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
#define	__HAL_RCC_ADC1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
#define	__HAL_RCC_ADC2_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
#define	__HAL_RCC_ADC3_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
#define	__HAL_RCC_SDMMC1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET)
#define	__HAL_RCC_SPI1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
#define	__HAL_RCC_SPI4_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
#define	__HAL_RCC_TIM9_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
#define	__HAL_RCC_TIM10_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
#define	__HAL_RCC_TIM11_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
#define	__HAL_RCC_SPI5_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
#define	__HAL_RCC_SPI6_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
#define	__HAL_RCC_SAI1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
#define	__HAL_RCC_SAI2_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
#define	__HAL_RCC_TIM1_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
#define	__HAL_RCC_TIM8_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
#define	__HAL_RCC_USART1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
#define	__HAL_RCC_USART6_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
#define	__HAL_RCC_ADC1_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
#define	__HAL_RCC_ADC2_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
#define	__HAL_RCC_ADC3_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
#define	__HAL_RCC_SDMMC1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET)
#define	__HAL_RCC_SPI1_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
#define	__HAL_RCC_SPI4_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
#define	__HAL_RCC_TIM9_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
#define	__HAL_RCC_TIM10_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
#define	__HAL_RCC_TIM11_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
#define	__HAL_RCC_SPI5_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
#define	__HAL_RCC_SPI6_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
#define	__HAL_RCC_SAI1_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
#define	__HAL_RCC_SAI2_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)

Detailed Description

Get the enable or disable status of the AHB/APB peripheral clock.

Note

After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Macro Definition Documentation

#define __HAL_RCC_ADC1_IS_CLK_DISABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)

Definition at line 1594 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC1_IS_CLK_ENABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)

Definition at line 1566 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC2_IS_CLK_DISABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)

Definition at line 1595 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC2_IS_CLK_ENABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)

Definition at line 1567 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC3_IS_CLK_DISABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)

Definition at line 1596 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC3_IS_CLK_ENABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)

Definition at line 1568 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)

Definition at line 1413 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)

Get the enable or disable status of the AHB1 peripheral clock.

Note

After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 1395 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN1_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)

Definition at line 1550 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN1_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)

Definition at line 1518 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN2_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)

Definition at line 1551 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN2_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)

Definition at line 1519 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CEC_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)

Definition at line 1552 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CEC_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)

Definition at line 1520 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DAC_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)

Definition at line 1553 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DAC_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)

Definition at line 1521 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DCMI_IS_CLK_DISABLED

(

)

((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)

Definition at line 1461 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DCMI_IS_CLK_ENABLED

(

)

((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)

Get the enable or disable status of the AHB2 peripheral clock.

Note

After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 1457 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2_IS_CLK_DISABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET)

Definition at line 1415 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2_IS_CLK_ENABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET)

Definition at line 1397 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2D_IS_CLK_DISABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)

Definition at line 1416 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2D_IS_CLK_ENABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)

Definition at line 1398 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET)

Definition at line 1414 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET)

Definition at line 1396 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETH_IS_CLK_DISABLED

(

)

Value:

(__HAL_RCC_ETHMAC_IS_CLK_DISABLED()   && \
                                                __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
                                                __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())

Definition at line 1448 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETH_IS_CLK_ENABLED

(

)

Value:

(__HAL_RCC_ETHMAC_IS_CLK_ENABLED()   && \
                                               __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
                                               __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())

Definition at line 1437 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)

Disable ETHERNET clock.

Definition at line 1444 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)

Enable ETHERNET clock.

Definition at line 1433 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)

Definition at line 1447 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)

Definition at line 1436 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)

Definition at line 1446 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)

Definition at line 1435 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)

Definition at line 1445 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)

Definition at line 1434 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_FMC_IS_CLK_DISABLED

(

)

((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)

Definition at line 1485 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_FMC_IS_CLK_ENABLED

(

)

((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)

Get the enable or disable status of the AHB3 peripheral clock.

Note

After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 1482 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOA_IS_CLK_DISABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET)

Definition at line 1419 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOA_IS_CLK_ENABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET)

Definition at line 1401 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOB_IS_CLK_DISABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET)

Definition at line 1420 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOB_IS_CLK_ENABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET)

Definition at line 1402 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOC_IS_CLK_DISABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET)

Definition at line 1421 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOC_IS_CLK_ENABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET)

Definition at line 1403 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOD_IS_CLK_DISABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)

Definition at line 1422 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOD_IS_CLK_ENABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)

Definition at line 1404 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOE_IS_CLK_DISABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)

Definition at line 1423 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOE_IS_CLK_ENABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)

Definition at line 1405 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOF_IS_CLK_DISABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)

Definition at line 1424 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOF_IS_CLK_ENABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)

Definition at line 1406 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOG_IS_CLK_DISABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)

Definition at line 1425 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOG_IS_CLK_ENABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)

Definition at line 1407 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOH_IS_CLK_DISABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET)

Definition at line 1426 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOH_IS_CLK_ENABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET)

Definition at line 1408 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOI_IS_CLK_DISABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)

Definition at line 1427 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOI_IS_CLK_ENABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)

Definition at line 1409 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)

Definition at line 1428 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)

Definition at line 1410 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOK_IS_CLK_DISABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)

Definition at line 1429 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOK_IS_CLK_ENABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)

Definition at line 1411 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C1_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)

Definition at line 1546 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C1_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)

Definition at line 1514 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)

Definition at line 1547 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)

Definition at line 1515 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C3_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)

Definition at line 1548 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C3_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)

Definition at line 1516 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C4_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET)

Definition at line 1549 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C4_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET)

Definition at line 1517 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)

Definition at line 1534 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)

Definition at line 1502 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_QSPI_IS_CLK_DISABLED

(

)

((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)

Definition at line 1486 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_QSPI_IS_CLK_ENABLED

(

)

((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)

Definition at line 1483 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_RNG_IS_CLK_DISABLED

(

)

((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)

Definition at line 1462 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_RNG_IS_CLK_ENABLED

(

)

((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)

Definition at line 1458 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI1_IS_CLK_DISABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)

Definition at line 1605 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI1_IS_CLK_ENABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)

Definition at line 1577 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI2_IS_CLK_DISABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)

Definition at line 1606 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI2_IS_CLK_ENABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)

Definition at line 1578 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET)

Definition at line 1597 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET)

Definition at line 1569 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)

Definition at line 1541 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)

Definition at line 1509 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI1_IS_CLK_DISABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)

Definition at line 1598 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI1_IS_CLK_ENABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)

Definition at line 1570 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI2_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)

Definition at line 1539 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI2_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)

Definition at line 1507 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI3_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)

Definition at line 1540 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI3_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)

Definition at line 1508 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI4_IS_CLK_DISABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)

Definition at line 1599 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI4_IS_CLK_ENABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)

Definition at line 1571 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI5_IS_CLK_DISABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)

Definition at line 1603 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI5_IS_CLK_ENABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)

Definition at line 1575 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI6_IS_CLK_DISABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)

Definition at line 1604 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI6_IS_CLK_ENABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)

Definition at line 1576 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM10_IS_CLK_DISABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)

Definition at line 1601 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM10_IS_CLK_ENABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)

Definition at line 1573 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM11_IS_CLK_DISABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)

Definition at line 1602 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM11_IS_CLK_ENABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)

Definition at line 1574 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM12_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)

Definition at line 1531 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM12_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)

Definition at line 1499 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM13_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)

Definition at line 1532 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM13_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)

Definition at line 1500 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM14_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)

Definition at line 1533 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM14_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)

Definition at line 1501 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM1_IS_CLK_DISABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)

Definition at line 1590 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM1_IS_CLK_ENABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)

Get the enable or disable status of the APB2 peripheral clock.

Note

After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 1562 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM2_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)

Definition at line 1525 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM2_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)

Get the enable or disable status of the APB1 peripheral clock.

Note

After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 1493 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM3_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)

Definition at line 1526 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM3_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)

Definition at line 1494 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM4_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)

Definition at line 1527 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM4_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)

Definition at line 1495 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM5_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)

Definition at line 1528 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM5_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)

Definition at line 1496 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM6_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)

Definition at line 1529 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM6_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)

Definition at line 1497 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM7_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)

Definition at line 1530 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM7_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)

Definition at line 1498 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM8_IS_CLK_DISABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)

Definition at line 1591 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM8_IS_CLK_ENABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)

Definition at line 1563 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM9_IS_CLK_DISABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)

Definition at line 1600 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM9_IS_CLK_ENABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)

Definition at line 1572 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART4_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)

Definition at line 1544 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART4_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)

Definition at line 1512 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART5_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)

Definition at line 1545 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART5_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)

Definition at line 1513 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART7_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)

Definition at line 1554 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART7_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)

Definition at line 1522 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART8_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)

Definition at line 1555 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART8_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)

Definition at line 1523 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART1_IS_CLK_DISABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)

Definition at line 1592 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART1_IS_CLK_ENABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)

Definition at line 1564 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART2_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)

Definition at line 1542 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART2_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)

Definition at line 1510 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART3_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)

Definition at line 1543 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART3_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)

Definition at line 1511 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART6_IS_CLK_DISABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)

Definition at line 1593 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART6_IS_CLK_ENABLED

(

)

((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)

Definition at line 1565 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED

(

)

((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)

Definition at line 1463 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED

(

)

((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)

Definition at line 1459 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)

Definition at line 1417 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)

Definition at line 1399 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)

Definition at line 1418 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED

(

)

((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)

Definition at line 1400 of file stm32f7xx_hal_rcc_ex.h.