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Macros
RCCEx_Peripheral_Clock_Enable_Disable
STM32F7xx_HAL_Driver » RCCEx » RCCEx Exported Macros

Enables or disables the AHB/APB peripheral clock. More...

Macros

#define __HAL_RCC_BKPSRAM_CLK_ENABLE()
 Enables or disables the AHB1 peripheral clock. More...
 
#define __HAL_RCC_DTCMRAMEN_CLK_ENABLE()
 
#define __HAL_RCC_DMA2_CLK_ENABLE()
 
#define __HAL_RCC_DMA2D_CLK_ENABLE()
 
#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()
 
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()
 
#define __HAL_RCC_GPIOA_CLK_ENABLE()
 
#define __HAL_RCC_GPIOB_CLK_ENABLE()
 
#define __HAL_RCC_GPIOC_CLK_ENABLE()
 
#define __HAL_RCC_GPIOD_CLK_ENABLE()
 
#define __HAL_RCC_GPIOE_CLK_ENABLE()
 
#define __HAL_RCC_GPIOF_CLK_ENABLE()
 
#define __HAL_RCC_GPIOG_CLK_ENABLE()
 
#define __HAL_RCC_GPIOH_CLK_ENABLE()
 
#define __HAL_RCC_GPIOI_CLK_ENABLE()
 
#define __HAL_RCC_GPIOJ_CLK_ENABLE()
 
#define __HAL_RCC_GPIOK_CLK_ENABLE()
 
#define __HAL_RCC_BKPSRAM_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
 
#define __HAL_RCC_DTCMRAMEN_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN))
 
#define __HAL_RCC_DMA2_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
 
#define __HAL_RCC_DMA2D_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
 
#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
 
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
 
#define __HAL_RCC_GPIOA_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
 
#define __HAL_RCC_GPIOB_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
 
#define __HAL_RCC_GPIOC_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
 
#define __HAL_RCC_GPIOD_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
 
#define __HAL_RCC_GPIOE_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
 
#define __HAL_RCC_GPIOF_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
 
#define __HAL_RCC_GPIOG_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
 
#define __HAL_RCC_GPIOH_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
 
#define __HAL_RCC_GPIOI_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
 
#define __HAL_RCC_GPIOJ_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
 
#define __HAL_RCC_GPIOK_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
 
#define __HAL_RCC_ETHMAC_CLK_ENABLE()
 Enable ETHERNET clock. More...
 
#define __HAL_RCC_ETHMACTX_CLK_ENABLE()
 
#define __HAL_RCC_ETHMACRX_CLK_ENABLE()
 
#define __HAL_RCC_ETHMACPTP_CLK_ENABLE()
 
#define __HAL_RCC_ETH_CLK_ENABLE()
 
#define __HAL_RCC_ETHMAC_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
 Disable ETHERNET clock. More...
 
#define __HAL_RCC_ETHMACTX_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
 
#define __HAL_RCC_ETHMACRX_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
 
#define __HAL_RCC_ETHMACPTP_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
 
#define __HAL_RCC_ETH_CLK_DISABLE()
 
#define __HAL_RCC_DCMI_CLK_ENABLE()
 Enable or disable the AHB2 peripheral clock. More...
 
#define __HAL_RCC_RNG_CLK_ENABLE()
 
#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()
 
#define __HAL_RCC_DCMI_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
 
#define __HAL_RCC_RNG_CLK_DISABLE()    (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
 
#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
 
#define __HAL_RCC_FMC_CLK_ENABLE()
 Enables or disables the AHB3 peripheral clock. More...
 
#define __HAL_RCC_QSPI_CLK_ENABLE()
 
#define __HAL_RCC_FMC_CLK_DISABLE()    (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
 
#define __HAL_RCC_QSPI_CLK_DISABLE()   (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
 
#define __HAL_RCC_TIM2_CLK_ENABLE()
 Enable or disable the Low Speed APB (APB1) peripheral clock. More...
 
#define __HAL_RCC_TIM3_CLK_ENABLE()
 
#define __HAL_RCC_TIM4_CLK_ENABLE()
 
#define __HAL_RCC_TIM5_CLK_ENABLE()
 
#define __HAL_RCC_TIM6_CLK_ENABLE()
 
#define __HAL_RCC_TIM7_CLK_ENABLE()
 
#define __HAL_RCC_TIM12_CLK_ENABLE()
 
#define __HAL_RCC_TIM13_CLK_ENABLE()
 
#define __HAL_RCC_TIM14_CLK_ENABLE()
 
#define __HAL_RCC_LPTIM1_CLK_ENABLE()
 
#define __HAL_RCC_SPI2_CLK_ENABLE()
 
#define __HAL_RCC_SPI3_CLK_ENABLE()
 
#define __HAL_RCC_SPDIFRX_CLK_ENABLE()
 
#define __HAL_RCC_USART2_CLK_ENABLE()
 
#define __HAL_RCC_USART3_CLK_ENABLE()
 
#define __HAL_RCC_UART4_CLK_ENABLE()
 
#define __HAL_RCC_UART5_CLK_ENABLE()
 
#define __HAL_RCC_I2C1_CLK_ENABLE()
 
#define __HAL_RCC_I2C2_CLK_ENABLE()
 
#define __HAL_RCC_I2C3_CLK_ENABLE()
 
#define __HAL_RCC_I2C4_CLK_ENABLE()
 
#define __HAL_RCC_CAN1_CLK_ENABLE()
 
#define __HAL_RCC_CAN2_CLK_ENABLE()
 
#define __HAL_RCC_CEC_CLK_ENABLE()
 
#define __HAL_RCC_DAC_CLK_ENABLE()
 
#define __HAL_RCC_UART7_CLK_ENABLE()
 
#define __HAL_RCC_UART8_CLK_ENABLE()
 
#define __HAL_RCC_TIM2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
 
#define __HAL_RCC_TIM3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
 
#define __HAL_RCC_TIM4_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
 
#define __HAL_RCC_TIM5_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
 
#define __HAL_RCC_TIM6_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
 
#define __HAL_RCC_TIM7_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
 
#define __HAL_RCC_TIM12_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
 
#define __HAL_RCC_TIM13_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
 
#define __HAL_RCC_TIM14_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
 
#define __HAL_RCC_LPTIM1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
 
#define __HAL_RCC_SPI2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
 
#define __HAL_RCC_SPI3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
 
#define __HAL_RCC_SPDIFRX_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
 
#define __HAL_RCC_USART2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
 
#define __HAL_RCC_USART3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
 
#define __HAL_RCC_UART4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
 
#define __HAL_RCC_UART5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
 
#define __HAL_RCC_I2C1_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
 
#define __HAL_RCC_I2C2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
 
#define __HAL_RCC_I2C3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
 
#define __HAL_RCC_I2C4_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN))
 
#define __HAL_RCC_CAN1_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
 
#define __HAL_RCC_CAN2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
 
#define __HAL_RCC_CEC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
 
#define __HAL_RCC_DAC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
 
#define __HAL_RCC_UART7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
 
#define __HAL_RCC_UART8_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
 
#define __HAL_RCC_TIM1_CLK_ENABLE()
 Enable or disable the High Speed APB (APB2) peripheral clock. More...
 
#define __HAL_RCC_TIM8_CLK_ENABLE()
 
#define __HAL_RCC_USART1_CLK_ENABLE()
 
#define __HAL_RCC_USART6_CLK_ENABLE()
 
#define __HAL_RCC_ADC1_CLK_ENABLE()
 
#define __HAL_RCC_ADC2_CLK_ENABLE()
 
#define __HAL_RCC_ADC3_CLK_ENABLE()
 
#define __HAL_RCC_SDMMC1_CLK_ENABLE()
 
#define __HAL_RCC_SPI1_CLK_ENABLE()
 
#define __HAL_RCC_SPI4_CLK_ENABLE()
 
#define __HAL_RCC_TIM9_CLK_ENABLE()
 
#define __HAL_RCC_TIM10_CLK_ENABLE()
 
#define __HAL_RCC_TIM11_CLK_ENABLE()
 
#define __HAL_RCC_SPI5_CLK_ENABLE()
 
#define __HAL_RCC_SPI6_CLK_ENABLE()
 
#define __HAL_RCC_SAI1_CLK_ENABLE()
 
#define __HAL_RCC_SAI2_CLK_ENABLE()
 
#define __HAL_RCC_TIM1_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
 
#define __HAL_RCC_TIM8_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
 
#define __HAL_RCC_USART1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
 
#define __HAL_RCC_USART6_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
 
#define __HAL_RCC_ADC1_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
 
#define __HAL_RCC_ADC2_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
 
#define __HAL_RCC_ADC3_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
 
#define __HAL_RCC_SDMMC1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))
 
#define __HAL_RCC_SPI1_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
 
#define __HAL_RCC_SPI4_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
 
#define __HAL_RCC_TIM9_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
 
#define __HAL_RCC_TIM10_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
 
#define __HAL_RCC_TIM11_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
 
#define __HAL_RCC_SPI5_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
 
#define __HAL_RCC_SPI6_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
 
#define __HAL_RCC_SAI1_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
 
#define __HAL_RCC_SAI2_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
 

Detailed Description

Enables or disables the AHB/APB peripheral clock.

Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Macro Definition Documentation

#define __HAL_RCC_ADC1_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))

Definition at line 1353 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB2ENR_ADC1EN
#define RCC_APB2ENR_ADC1EN
Definition: stm32f745xx.h:5496
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 1204 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC2_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))

Definition at line 1354 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
RCC_APB2ENR_ADC2EN
#define RCC_APB2ENR_ADC2EN
Definition: stm32f745xx.h:5497
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 1212 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC3_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))

Definition at line 1355 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC3_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_APB2ENR_ADC3EN
#define RCC_APB2ENR_ADC3EN
Definition: stm32f745xx.h:5498

Definition at line 1220 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_BKPSRAM_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))

Definition at line 726 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_BKPSRAM_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
UNUSED(tmpreg); \
} while(0)
RCC_AHB1ENR_BKPSRAMEN
#define RCC_AHB1ENR_BKPSRAMEN
Definition: stm32f745xx.h:5439
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Enables or disables the AHB1 peripheral clock.

Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 590 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN1_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))

Definition at line 1150 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_APB1ENR_CAN1EN
#define RCC_APB1ENR_CAN1EN
Definition: stm32f745xx.h:5483

Definition at line 1077 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN2_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))

Definition at line 1151 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
RCC_APB1ENR_CAN2EN
#define RCC_APB1ENR_CAN2EN
Definition: stm32f745xx.h:5484
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 1085 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CEC_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))

Definition at line 1152 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CEC_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_APB1ENR_CECEN
#define RCC_APB1ENR_CECEN
Definition: stm32f745xx.h:5485

Definition at line 1093 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DAC_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))

Definition at line 1153 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DAC_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
RCC_APB1ENR_DACEN
#define RCC_APB1ENR_DACEN
Definition: stm32f745xx.h:5487
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 1101 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DCMI_CLK_DISABLE ( )    (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))

Definition at line 837 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DCMI_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_AHB2ENR_DCMIEN
#define RCC_AHB2ENR_DCMIEN
Definition: stm32f745xx.h:5452

Enable or disable the AHB2 peripheral clock.

Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 801 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))

Definition at line 728 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
RCC_AHB1ENR_DMA2EN
#define RCC_AHB1ENR_DMA2EN
Definition: stm32f745xx.h:5442
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 606 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2D_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))

Definition at line 729 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2D_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
UNUSED(tmpreg); \
} while(0)
RCC_AHB1ENR_DMA2DEN
#define RCC_AHB1ENR_DMA2DEN
Definition: stm32f745xx.h:5443
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 614 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DTCMRAMEN_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN))

Definition at line 727 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DTCMRAMEN_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_AHB1ENR_DTCMRAMEN
#define RCC_AHB1ENR_DTCMRAMEN
Definition: stm32f745xx.h:5440

Definition at line 598 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETH_CLK_DISABLE ( )
Value:
do { \
__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
__HAL_RCC_ETHMAC_CLK_DISABLE(); \
} while(0)

Definition at line 790 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETH_CLK_ENABLE ( )
Value:
do { \
__HAL_RCC_ETHMAC_CLK_ENABLE(); \
__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
} while(0)

Definition at line 778 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMAC_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))

Disable ETHERNET clock.

Definition at line 786 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMAC_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
UNUSED(tmpreg); \
} while(0)
RCC_AHB1ENR_ETHMACEN
#define RCC_AHB1ENR_ETHMACEN
Definition: stm32f745xx.h:5444
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Enable ETHERNET clock.

Definition at line 746 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACPTP_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))

Definition at line 789 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACPTP_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
RCC_AHB1ENR_ETHMACPTPEN
#define RCC_AHB1ENR_ETHMACPTPEN
Definition: stm32f745xx.h:5447
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 770 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACRX_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))

Definition at line 788 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACRX_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_AHB1ENR_ETHMACRXEN
#define RCC_AHB1ENR_ETHMACRXEN
Definition: stm32f745xx.h:5446

Definition at line 762 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACTX_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))

Definition at line 787 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACTX_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_AHB1ENR_ETHMACTXEN
#define RCC_AHB1ENR_ETHMACTXEN
Definition: stm32f745xx.h:5445

Definition at line 754 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_FMC_CLK_DISABLE ( )    (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))

Definition at line 883 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_FMC_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_AHB3ENR_FMCEN
#define RCC_AHB3ENR_FMCEN
Definition: stm32f745xx.h:5457

Enables or disables the AHB3 peripheral clock.

Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 867 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOA_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))

Definition at line 732 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOA_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_AHB1ENR_GPIOAEN
#define RCC_AHB1ENR_GPIOAEN
Definition: stm32f745xx.h:5427

Definition at line 638 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOB_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))

Definition at line 733 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOB_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_AHB1ENR_GPIOBEN
#define RCC_AHB1ENR_GPIOBEN
Definition: stm32f745xx.h:5428

Definition at line 646 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOC_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))

Definition at line 734 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOC_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_AHB1ENR_GPIOCEN
#define RCC_AHB1ENR_GPIOCEN
Definition: stm32f745xx.h:5429

Definition at line 654 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOD_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))

Definition at line 735 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOD_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_AHB1ENR_GPIODEN
#define RCC_AHB1ENR_GPIODEN
Definition: stm32f745xx.h:5430

Definition at line 662 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOE_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))

Definition at line 736 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOE_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_AHB1ENR_GPIOEEN
#define RCC_AHB1ENR_GPIOEEN
Definition: stm32f745xx.h:5431

Definition at line 670 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOF_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))

Definition at line 737 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOF_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
RCC_AHB1ENR_GPIOFEN
#define RCC_AHB1ENR_GPIOFEN
Definition: stm32f745xx.h:5432
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 678 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOG_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))

Definition at line 738 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOG_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_AHB1ENR_GPIOGEN
#define RCC_AHB1ENR_GPIOGEN
Definition: stm32f745xx.h:5433

Definition at line 686 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOH_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))

Definition at line 739 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOH_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
UNUSED(tmpreg); \
} while(0)
RCC_AHB1ENR_GPIOHEN
#define RCC_AHB1ENR_GPIOHEN
Definition: stm32f745xx.h:5434
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 694 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOI_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))

Definition at line 740 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOI_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_AHB1ENR_GPIOIEN
#define RCC_AHB1ENR_GPIOIEN
Definition: stm32f745xx.h:5435

Definition at line 702 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOJ_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))

Definition at line 741 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOJ_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
UNUSED(tmpreg); \
} while(0)
RCC_AHB1ENR_GPIOJEN
#define RCC_AHB1ENR_GPIOJEN
Definition: stm32f745xx.h:5436
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 710 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOK_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))

Definition at line 742 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOK_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_AHB1ENR_GPIOKEN
#define RCC_AHB1ENR_GPIOKEN
Definition: stm32f745xx.h:5437

Definition at line 718 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C1_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))

Definition at line 1146 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_APB1ENR_I2C1EN
#define RCC_APB1ENR_I2C1EN
Definition: stm32f745xx.h:5479

Definition at line 1045 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))

Definition at line 1147 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_APB1ENR_I2C2EN
#define RCC_APB1ENR_I2C2EN
Definition: stm32f745xx.h:5480

Definition at line 1053 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C3_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))

Definition at line 1148 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C3_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
RCC_APB1ENR_I2C3EN
#define RCC_APB1ENR_I2C3EN
Definition: stm32f745xx.h:5481
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 1061 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C4_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN))

Definition at line 1149 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C4_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_APB1ENR_I2C4EN
#define RCC_APB1ENR_I2C4EN
Definition: stm32f745xx.h:5482

Definition at line 1069 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_LPTIM1_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))

Definition at line 1134 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_LPTIM1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
RCC_APB1ENR_LPTIM1EN
#define RCC_APB1ENR_LPTIM1EN
Definition: stm32f745xx.h:5470
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 963 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_QSPI_CLK_DISABLE ( )    (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))

Definition at line 884 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_QSPI_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
UNUSED(tmpreg); \
} while(0)
RCC_AHB3ENR_QSPIEN
#define RCC_AHB3ENR_QSPIEN
Definition: stm32f745xx.h:5458
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 875 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_RNG_CLK_DISABLE ( )    (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))

Definition at line 838 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_RNG_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
UNUSED(tmpreg); \
} while(0)
RCC_AHB2ENR_RNGEN
#define RCC_AHB2ENR_RNGEN
Definition: stm32f745xx.h:5453
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 820 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI1_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))

Definition at line 1364 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_APB2ENR_SAI1EN
#define RCC_APB2ENR_SAI1EN
Definition: stm32f745xx.h:5508

Definition at line 1292 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI2_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))

Definition at line 1365 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_APB2ENR_SAI2EN
#define RCC_APB2ENR_SAI2EN
Definition: stm32f745xx.h:5509

Definition at line 1300 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SDMMC1_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))

Definition at line 1356 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SDMMC1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB2ENR_SDMMC1EN
#define RCC_APB2ENR_SDMMC1EN
Definition: stm32f745xx.h:5499
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 1228 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPDIFRX_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))

Definition at line 1141 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPDIFRX_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
RCC_APB1ENR_SPDIFRXEN
#define RCC_APB1ENR_SPDIFRXEN
Definition: stm32f745xx.h:5474
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 1005 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI1_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))

Definition at line 1357 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB2ENR_SPI1EN
#define RCC_APB2ENR_SPI1EN
Definition: stm32f745xx.h:5500
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 1236 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI2_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))

Definition at line 1139 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_APB1ENR_SPI2EN
#define RCC_APB1ENR_SPI2EN
Definition: stm32f745xx.h:5472

Definition at line 989 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI3_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))

Definition at line 1140 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI3_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
RCC_APB1ENR_SPI3EN
#define RCC_APB1ENR_SPI3EN
Definition: stm32f745xx.h:5473
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 997 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI4_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))

Definition at line 1358 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI4_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_APB2ENR_SPI4EN
#define RCC_APB2ENR_SPI4EN
Definition: stm32f745xx.h:5501

Definition at line 1244 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI5_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))

Definition at line 1362 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI5_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB2ENR_SPI5EN
#define RCC_APB2ENR_SPI5EN
Definition: stm32f745xx.h:5506
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 1276 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI6_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))

Definition at line 1363 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI6_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_APB2ENR_SPI6EN
#define RCC_APB2ENR_SPI6EN
Definition: stm32f745xx.h:5507

Definition at line 1284 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM10_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))

Definition at line 1360 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM10_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB2ENR_TIM10EN
#define RCC_APB2ENR_TIM10EN
Definition: stm32f745xx.h:5504
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 1260 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM11_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))

Definition at line 1361 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM11_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB2ENR_TIM11EN
#define RCC_APB2ENR_TIM11EN
Definition: stm32f745xx.h:5505
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 1268 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM12_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))

Definition at line 1131 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM12_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_APB1ENR_TIM12EN
#define RCC_APB1ENR_TIM12EN
Definition: stm32f745xx.h:5467

Definition at line 939 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM13_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))

Definition at line 1132 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM13_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_APB1ENR_TIM13EN
#define RCC_APB1ENR_TIM13EN
Definition: stm32f745xx.h:5468

Definition at line 947 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM14_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))

Definition at line 1133 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM14_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_APB1ENR_TIM14EN
#define RCC_APB1ENR_TIM14EN
Definition: stm32f745xx.h:5469

Definition at line 955 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM1_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))

Definition at line 1346 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB2ENR_TIM1EN
#define RCC_APB2ENR_TIM1EN
Definition: stm32f745xx.h:5492
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Enable or disable the High Speed APB (APB2) peripheral clock.

Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 1162 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM2_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))

Definition at line 1125 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_APB1ENR_TIM2EN
#define RCC_APB1ENR_TIM2EN
Definition: stm32f745xx.h:5461

Enable or disable the Low Speed APB (APB1) peripheral clock.

Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Definition at line 891 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM3_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))

Definition at line 1126 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM3_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
RCC_APB1ENR_TIM3EN
#define RCC_APB1ENR_TIM3EN
Definition: stm32f745xx.h:5462
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 899 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM4_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))

Definition at line 1127 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM4_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_APB1ENR_TIM4EN
#define RCC_APB1ENR_TIM4EN
Definition: stm32f745xx.h:5463

Definition at line 907 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM5_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))

Definition at line 1128 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM5_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_APB1ENR_TIM5EN
#define RCC_APB1ENR_TIM5EN
Definition: stm32f745xx.h:5464

Definition at line 915 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM6_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))

Definition at line 1129 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM6_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
RCC_APB1ENR_TIM6EN
#define RCC_APB1ENR_TIM6EN
Definition: stm32f745xx.h:5465
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 923 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM7_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))

Definition at line 1130 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM7_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
RCC_APB1ENR_TIM7EN
#define RCC_APB1ENR_TIM7EN
Definition: stm32f745xx.h:5466
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 931 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM8_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))

Definition at line 1347 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM8_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
RCC_APB2ENR_TIM8EN
#define RCC_APB2ENR_TIM8EN
Definition: stm32f745xx.h:5493
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 1170 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM9_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))

Definition at line 1359 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM9_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
RCC_APB2ENR_TIM9EN
#define RCC_APB2ENR_TIM9EN
Definition: stm32f745xx.h:5503
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 1252 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART4_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))

Definition at line 1144 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART4_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_UART4EN
#define RCC_APB1ENR_UART4EN
Definition: stm32f745xx.h:5477
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 1029 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART5_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))

Definition at line 1145 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART5_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_APB1ENR_UART5EN
#define RCC_APB1ENR_UART5EN
Definition: stm32f745xx.h:5478

Definition at line 1037 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART7_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))

Definition at line 1154 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART7_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_UART7EN
#define RCC_APB1ENR_UART7EN
Definition: stm32f745xx.h:5488
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 1109 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART8_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))

Definition at line 1155 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART8_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
RCC_APB1ENR_UART8EN
#define RCC_APB1ENR_UART8EN
Definition: stm32f745xx.h:5489
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 1117 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART1_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))

Definition at line 1348 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_APB2ENR_USART1EN
#define RCC_APB2ENR_USART1EN
Definition: stm32f745xx.h:5494

Definition at line 1178 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART2_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))

Definition at line 1142 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_APB1ENR_USART2EN
#define RCC_APB1ENR_USART2EN
Definition: stm32f745xx.h:5475

Definition at line 1013 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART3_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))

Definition at line 1143 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART3_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_USART3EN
#define RCC_APB1ENR_USART3EN
Definition: stm32f745xx.h:5476
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 1021 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART6_CLK_DISABLE ( )    (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))

Definition at line 1349 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART6_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
RCC_APB2ENR_USART6EN
#define RCC_APB2ENR_USART6EN
Definition: stm32f745xx.h:5495
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 1186 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE ( )    (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))

Definition at line 840 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
UNUSED(tmpreg); \
__HAL_RCC_SYSCFG_CLK_ENABLE();\
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
RCC_AHB2ENR_OTGFSEN
#define RCC_AHB2ENR_OTGFSEN
Definition: stm32f745xx.h:5454
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 828 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))

Definition at line 730 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
UNUSED(tmpreg); \
} while(0)
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182
RCC_AHB1ENR_OTGHSEN
#define RCC_AHB1ENR_OTGHSEN
Definition: stm32f745xx.h:5448

Definition at line 622 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE ( )    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))

Definition at line 731 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
UNUSED(tmpreg); \
} while(0)
RCC_AHB1ENR_OTGHSULPIEN
#define RCC_AHB1ENR_OTGHSULPIEN
Definition: stm32f745xx.h:5449
RCC
#define RCC
Definition: stm32f745xx.h:1325
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f7xx.h:182

Definition at line 630 of file stm32f7xx_hal_rcc_ex.h.

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