STM32F769IDiscovery  1.00
uDANTE Audio Networking with STM32F7 DISCO board
Macros
AHB/APB Peripheral Clock Sleep Enable Disable Status
STM32F7xx_HAL_Driver » RCCEx » RCCEx Exported Macros

Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode. More...

Macros

#define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET)
 Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode. More...
 
#define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET)
 
#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET)
 
#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET)
 
#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET)
 
#define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET)
 
#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET)
 
#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET)
 
#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET)
 
#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET)
 
#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET)
 
#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED()   ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET)
 
#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED()   ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET)
 
#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED()   ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET)
 
#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET)
 
#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET)
 
#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET)
 
#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET)
 
#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET)
 
#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET)
 
#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET)
 
#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET)
 
#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET)
 
#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET)
 
#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET)
 
#define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET)
 
#define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET)
 
#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET)
 
#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET)
 
#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET)
 
#define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET)
 
#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET)
 
#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET)
 
#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET)
 
#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED()   ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET)
 
#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED()   ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET)
 
#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED()   ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET)
 
#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED()   ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET)
 
#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED()   ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET)
 
#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET)
 
#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET)
 
#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET)
 
#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET)
 
#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET)
 
#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET)
 
#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET)
 
#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET)
 
#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET)
 
#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET)
 
#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET)
 
#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET)
 Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode. More...
 
#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET)
 
#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET)
 
#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET)
 
#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED()   ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET)
 
#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED()   ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET)
 
#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED()   ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET)
 Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode. More...
 
#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED()   ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET)
 
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED()   ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET)
 
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED()   ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET)
 
#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET)
 Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode. More...
 
#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET)
 
#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET)
 
#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET)
 
#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET)
 
#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET)
 
#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET)
 
#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET)
 
#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET)
 
#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET)
 
#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET)
 
#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET)
 
#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET)
 
#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET)
 
#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET)
 
#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET)
 
#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET)
 
#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET)
 
#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET)
 
#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET)
 
#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET)
 
#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET)
 
#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET)
 
#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET)
 
#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET)
 
#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET)
 
#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET)
 
#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET)
 
#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET)
 
#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET)
 
#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET)
 
#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET)
 
#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET)
 
#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET)
 
#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET)
 
#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET)
 
#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET)
 
#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET)
 
#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET)
 
#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET)
 
#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET)
 
#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET)
 
#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET)
 
#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET)
 
#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET)
 
#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET)
 
#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET)
 
#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET)
 
#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET)
 
#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET)
 
#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET)
 
#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET)
 
#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET)
 
#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET)
 
#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET)
 Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode. More...
 
#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET)
 
#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET)
 
#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET)
 
#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET)
 
#define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET)
 
#define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET)
 
#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET)
 
#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET)
 
#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET)
 
#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET)
 
#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET)
 
#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET)
 
#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET)
 
#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET)
 
#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET)
 
#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET)
 
#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET)
 
#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET)
 
#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET)
 
#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET)
 
#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET)
 
#define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET)
 
#define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET)
 
#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET)
 
#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET)
 
#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET)
 
#define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET)
 
#define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET)
 
#define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET)
 
#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET)
 
#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET)
 
#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET)
 
#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET)
 

Detailed Description

Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode.

Note
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Macro Definition Documentation

#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET)

Definition at line 2270 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET)

Definition at line 2241 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET)

Definition at line 2271 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET)

Definition at line 2242 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET)

Definition at line 2272 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET)

Definition at line 2243 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET)

Definition at line 2096 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET)

Definition at line 2070 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET)

Definition at line 2099 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET)

Definition at line 2073 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET)

Definition at line 2224 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET)

Definition at line 2192 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET)

Definition at line 2225 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET)

Definition at line 2193 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET)

Definition at line 2226 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET)

Definition at line 2194 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET)

Definition at line 2227 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET)

Definition at line 2195 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED ( )    ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET)

Definition at line 2128 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED ( )    ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET)

Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode.

Note
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Definition at line 2127 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET)

Definition at line 2101 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET)

Definition at line 2075 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET)

Definition at line 2102 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET)

Definition at line 2076 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET)

Definition at line 2100 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET)

Definition at line 2074 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET)

Definition at line 2103 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET)

Definition at line 2077 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET)

Definition at line 2106 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET)

Definition at line 2080 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET)

Definition at line 2105 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET)

Definition at line 2079 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET)

Definition at line 2104 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET)

Definition at line 2078 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET)

Definition at line 2095 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET)

Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.

Note
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Definition at line 2069 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED ( )    ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET)

Definition at line 2156 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED ( )    ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET)

Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode.

Note
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Definition at line 2155 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET)

Definition at line 2109 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET)

Definition at line 2083 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET)

Definition at line 2110 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET)

Definition at line 2084 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET)

Definition at line 2111 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET)

Definition at line 2085 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET)

Definition at line 2112 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET)

Definition at line 2086 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET)

Definition at line 2113 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET)

Definition at line 2087 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET)

Definition at line 2114 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET)

Definition at line 2088 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET)

Definition at line 2115 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET)

Definition at line 2089 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET)

Definition at line 2116 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET)

Definition at line 2090 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET)

Definition at line 2117 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET)

Definition at line 2091 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET)

Definition at line 2118 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET)

Definition at line 2092 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET)

Definition at line 2119 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET)

Definition at line 2093 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET)

Definition at line 2220 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET)

Definition at line 2188 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET)

Definition at line 2221 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET)

Definition at line 2189 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET)

Definition at line 2222 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET)

Definition at line 2190 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET)

Definition at line 2223 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET)

Definition at line 2191 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET)

Definition at line 2208 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET)

Definition at line 2176 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED ( )    ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET)

Definition at line 2159 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED ( )    ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET)

Definition at line 2158 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED ( )    ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET)

Definition at line 2136 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED ( )    ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET)

Definition at line 2135 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET)

Definition at line 2281 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET)

Definition at line 2252 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET)

Definition at line 2282 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET)

Definition at line 2253 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET)

Definition at line 2273 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET)

Definition at line 2244 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET)

Definition at line 2215 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET)

Definition at line 2183 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET)

Definition at line 2274 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET)

Definition at line 2245 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET)

Definition at line 2213 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET)

Definition at line 2181 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET)

Definition at line 2214 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET)

Definition at line 2182 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET)

Definition at line 2275 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET)

Definition at line 2246 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET)

Definition at line 2279 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET)

Definition at line 2250 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET)

Definition at line 2280 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET)

Definition at line 2251 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET)

Definition at line 2097 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET)

Definition at line 2071 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET)

Definition at line 2098 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET)

Definition at line 2072 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET)

Definition at line 2277 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET)

Definition at line 2248 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET)

Definition at line 2278 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET)

Definition at line 2249 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET)

Definition at line 2205 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET)

Definition at line 2173 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET)

Definition at line 2206 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET)

Definition at line 2174 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET)

Definition at line 2207 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET)

Definition at line 2175 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET)

Definition at line 2266 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET)

Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.

Note
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Definition at line 2237 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET)

Definition at line 2199 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET)

Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.

Note
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Definition at line 2167 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET)

Definition at line 2200 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET)

Definition at line 2168 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET)

Definition at line 2201 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET)

Definition at line 2169 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET)

Definition at line 2202 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET)

Definition at line 2170 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET)

Definition at line 2203 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET)

Definition at line 2171 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET)

Definition at line 2204 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET)

Definition at line 2172 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET)

Definition at line 2267 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET)

Definition at line 2238 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET)

Definition at line 2276 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET)

Definition at line 2247 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET)

Definition at line 2218 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET)

Definition at line 2186 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET)

Definition at line 2219 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET)

Definition at line 2187 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET)

Definition at line 2228 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET)

Definition at line 2196 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET)

Definition at line 2229 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET)

Definition at line 2197 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET)

Definition at line 2268 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET)

Definition at line 2239 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET)

Definition at line 2216 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET)

Definition at line 2184 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET)

Definition at line 2217 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET)

Definition at line 2185 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET)

Definition at line 2269 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED ( )    ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET)

Definition at line 2240 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED ( )    ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET)

Definition at line 2139 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED ( )    ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET)

Definition at line 2138 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET)

Definition at line 2107 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET)

Definition at line 2081 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET)

Definition at line 2108 of file stm32f7xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED ( )    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET)

Definition at line 2082 of file stm32f7xx_hal_rcc_ex.h.

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