STM32F769IDiscovery  1.00
uDANTE Audio Networking with STM32F7 DISCO board
stm32f7xx_hal_eth.h
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1 
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F7xx_HAL_ETH_H
40 #define __STM32F7xx_HAL_ETH_H
41 
42 #ifdef __cplusplus
43  extern "C" {
44 #endif
45 
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f7xx_hal_def.h"
48 
60 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
61 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
62  ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
63 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
64  ((SPEED) == ETH_SPEED_100M))
65 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
66  ((MODE) == ETH_MODE_HALFDUPLEX))
67 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
68  ((MODE) == ETH_RXINTERRUPT_MODE))
69 #define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
70  ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
71 #define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
72  ((MODE) == ETH_MEDIA_INTERFACE_RMII))
73 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
74  ((CMD) == ETH_WATCHDOG_DISABLE))
75 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
76  ((CMD) == ETH_JABBER_DISABLE))
77 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
78  ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
79  ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
80  ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
81  ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
82  ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
83  ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
84  ((GAP) == ETH_INTERFRAMEGAP_40BIT))
85 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
86  ((CMD) == ETH_CARRIERSENCE_DISABLE))
87 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
88  ((CMD) == ETH_RECEIVEOWN_DISABLE))
89 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
90  ((CMD) == ETH_LOOPBACKMODE_DISABLE))
91 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
92  ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
93 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
94  ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
95 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
96  ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
97 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
98  ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
99  ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
100  ((LIMIT) == ETH_BACKOFFLIMIT_1))
101 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
102  ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
103 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
104  ((CMD) == ETH_RECEIVEAll_DISABLE))
105 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
106  ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
107  ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
108 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
109  ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
110  ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
111 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
112  ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
113 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
114  ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
115 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
116  ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
117 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
118  ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
119  ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
120  ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
121 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
122  ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
123  ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
124 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
125 #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
126  ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
127 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
128  ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
129  ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
130  ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
131 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
132  ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
133 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
134  ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
135 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
136  ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
137 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
138  ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
139 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
140 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
141  ((ADDRESS) == ETH_MAC_ADDRESS1) || \
142  ((ADDRESS) == ETH_MAC_ADDRESS2) || \
143  ((ADDRESS) == ETH_MAC_ADDRESS3))
144 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
145  ((ADDRESS) == ETH_MAC_ADDRESS2) || \
146  ((ADDRESS) == ETH_MAC_ADDRESS3))
147 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
148  ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
149 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
150  ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
151  ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
152  ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
153  ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
154  ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
155 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
156  ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
157 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
158  ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
159 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
160  ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
161 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
162  ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
163 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
164  ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
165  ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
166  ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
167  ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
168  ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
169  ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
170  ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
171 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
172  ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
173 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
174  ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
175 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
176  ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
177  ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
178  ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
179 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
180  ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
181 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
182  ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
183 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
184  ((CMD) == ETH_FIXEDBURST_DISABLE))
185 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
186  ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
187  ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
188  ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
189  ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
190  ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
191  ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
192  ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
193  ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
194  ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
195  ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
196  ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
197 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
198  ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
199  ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
200  ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
201  ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
202  ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
203  ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
204  ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
205  ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
206  ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
207  ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
208  ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
209 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
210 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
211  ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
212  ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
213  ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
214  ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
215 #define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
216  ((FLAG) == ETH_DMATXDESC_IC) || \
217  ((FLAG) == ETH_DMATXDESC_LS) || \
218  ((FLAG) == ETH_DMATXDESC_FS) || \
219  ((FLAG) == ETH_DMATXDESC_DC) || \
220  ((FLAG) == ETH_DMATXDESC_DP) || \
221  ((FLAG) == ETH_DMATXDESC_TTSE) || \
222  ((FLAG) == ETH_DMATXDESC_TER) || \
223  ((FLAG) == ETH_DMATXDESC_TCH) || \
224  ((FLAG) == ETH_DMATXDESC_TTSS) || \
225  ((FLAG) == ETH_DMATXDESC_IHE) || \
226  ((FLAG) == ETH_DMATXDESC_ES) || \
227  ((FLAG) == ETH_DMATXDESC_JT) || \
228  ((FLAG) == ETH_DMATXDESC_FF) || \
229  ((FLAG) == ETH_DMATXDESC_PCE) || \
230  ((FLAG) == ETH_DMATXDESC_LCA) || \
231  ((FLAG) == ETH_DMATXDESC_NC) || \
232  ((FLAG) == ETH_DMATXDESC_LCO) || \
233  ((FLAG) == ETH_DMATXDESC_EC) || \
234  ((FLAG) == ETH_DMATXDESC_VF) || \
235  ((FLAG) == ETH_DMATXDESC_CC) || \
236  ((FLAG) == ETH_DMATXDESC_ED) || \
237  ((FLAG) == ETH_DMATXDESC_UF) || \
238  ((FLAG) == ETH_DMATXDESC_DB))
239 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
240  ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
241 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
242  ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
243  ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
244  ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
245 #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
246 #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
247  ((FLAG) == ETH_DMARXDESC_AFM) || \
248  ((FLAG) == ETH_DMARXDESC_ES) || \
249  ((FLAG) == ETH_DMARXDESC_DE) || \
250  ((FLAG) == ETH_DMARXDESC_SAF) || \
251  ((FLAG) == ETH_DMARXDESC_LE) || \
252  ((FLAG) == ETH_DMARXDESC_OE) || \
253  ((FLAG) == ETH_DMARXDESC_VLAN) || \
254  ((FLAG) == ETH_DMARXDESC_FS) || \
255  ((FLAG) == ETH_DMARXDESC_LS) || \
256  ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
257  ((FLAG) == ETH_DMARXDESC_LC) || \
258  ((FLAG) == ETH_DMARXDESC_FT) || \
259  ((FLAG) == ETH_DMARXDESC_RWT) || \
260  ((FLAG) == ETH_DMARXDESC_RE) || \
261  ((FLAG) == ETH_DMARXDESC_DBE) || \
262  ((FLAG) == ETH_DMARXDESC_CE) || \
263  ((FLAG) == ETH_DMARXDESC_MAMPCE))
264 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
265  ((BUFFER) == ETH_DMARXDESC_BUFFER2))
266 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
267  ((FLAG) == ETH_PMT_FLAG_MPR))
268 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))
269 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
270  ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
271  ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
272  ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
273  ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
274  ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
275  ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
276  ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
277  ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
278  ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
279  ((FLAG) == ETH_DMA_FLAG_T))
280 #define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00))
281 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
282  ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
283  ((IT) == ETH_MAC_IT_PMT))
284 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
285  ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
286  ((FLAG) == ETH_MAC_FLAG_PMT))
287 #define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
288 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
289  ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
290  ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
291  ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
292  ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
293  ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
294  ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
295  ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
296  ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
297 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
298  ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
299 #define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
300  ((IT) != 0x00))
301 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
302  ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
303  ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
304 #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
305  ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
306 
307 
315 /* Delay to wait when writing to some Ethernet registers */
316 #define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001U)
317 
318 /* Ethernet Errors */
319 #define ETH_SUCCESS ((uint32_t)0U)
320 #define ETH_ERROR ((uint32_t)1U)
321 
322 /* Ethernet DMA Tx descriptors Collision Count Shift */
323 #define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3U)
324 
325 /* Ethernet DMA Tx descriptors Buffer2 Size Shift */
326 #define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16U)
327 
328 /* Ethernet DMA Rx descriptors Frame Length Shift */
329 #define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16U)
330 
331 /* Ethernet DMA Rx descriptors Buffer2 Size Shift */
332 #define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16U)
333 
334 /* Ethernet DMA Rx descriptors Frame length Shift */
335 #define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
336 
337 /* Ethernet MAC address offsets */
338 #define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40U) /* Ethernet MAC address high offset */
339 #define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44U) /* Ethernet MAC address low offset */
340 
341 /* Ethernet MACMIIAR register Mask */
342 #define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3U)
343 
344 /* Ethernet MACCR register Mask */
345 #define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810FU)
346 
347 /* Ethernet MACFCR register Mask */
348 #define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41U)
349 
350 /* Ethernet DMAOMR register Mask */
351 #define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23U)
352 
353 /* Ethernet Remote Wake-up frame register length */
354 #define ETH_WAKEUP_REGISTER_LENGTH 8U
355 
356 /* Ethernet Missed frames counter Shift */
357 #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U
358 
362 /* Exported types ------------------------------------------------------------*/
370 typedef enum
371 {
372  HAL_ETH_STATE_RESET = 0x00U,
373  HAL_ETH_STATE_READY = 0x01U,
374  HAL_ETH_STATE_BUSY = 0x02U,
375  HAL_ETH_STATE_BUSY_TX = 0x12U,
376  HAL_ETH_STATE_BUSY_RX = 0x22U,
377  HAL_ETH_STATE_BUSY_TX_RX = 0x32U,
378  HAL_ETH_STATE_BUSY_WR = 0x42U,
379  HAL_ETH_STATE_BUSY_RD = 0x82U,
380  HAL_ETH_STATE_TIMEOUT = 0x03U,
381  HAL_ETH_STATE_ERROR = 0x04U
382 }HAL_ETH_StateTypeDef;
383 
388 typedef struct
389 {
390  uint32_t AutoNegotiation;
395  uint32_t Speed;
398  uint32_t DuplexMode;
401  uint16_t PhyAddress;
404  uint8_t *MACAddr;
406  uint32_t RxMode;
409  uint32_t ChecksumMode;
412  uint32_t MediaInterface ;
415 } ETH_InitTypeDef;
416 
417 
422 typedef struct
423 {
424  uint32_t Watchdog;
429  uint32_t Jabber;
434  uint32_t InterFrameGap;
437  uint32_t CarrierSense;
440  uint32_t ReceiveOwn;
445  uint32_t LoopbackMode;
448  uint32_t ChecksumOffload;
451  uint32_t RetryTransmission;
455  uint32_t AutomaticPadCRCStrip;
458  uint32_t BackOffLimit;
461  uint32_t DeferralCheck;
464  uint32_t ReceiveAll;
467  uint32_t SourceAddrFilter;
470  uint32_t PassControlFrames;
473  uint32_t BroadcastFramesReception;
476  uint32_t DestinationAddrFilter;
479  uint32_t PromiscuousMode;
482  uint32_t MulticastFramesFilter;
485  uint32_t UnicastFramesFilter;
488  uint32_t HashTableHigh;
491  uint32_t HashTableLow;
494  uint32_t PauseTime;
497  uint32_t ZeroQuantaPause;
500  uint32_t PauseLowThreshold;
504  uint32_t UnicastPauseFrameDetect;
508  uint32_t ReceiveFlowControl;
512  uint32_t TransmitFlowControl;
516  uint32_t VLANTagComparison;
520  uint32_t VLANTagIdentifier;
522 } ETH_MACInitTypeDef;
523 
524 
529 typedef struct
530 {
531  uint32_t DropTCPIPChecksumErrorFrame;
534  uint32_t ReceiveStoreForward;
537  uint32_t FlushReceivedFrame;
540  uint32_t TransmitStoreForward;
543  uint32_t TransmitThresholdControl;
546  uint32_t ForwardErrorFrames;
549  uint32_t ForwardUndersizedGoodFrames;
553  uint32_t ReceiveThresholdControl;
556  uint32_t SecondFrameOperate;
560  uint32_t AddressAlignedBeats;
563  uint32_t FixedBurst;
566  uint32_t RxDMABurstLength;
569  uint32_t TxDMABurstLength;
572  uint32_t EnhancedDescriptorFormat;
575  uint32_t DescriptorSkipLength;
578  uint32_t DMAArbitration;
580 } ETH_DMAInitTypeDef;
581 
582 
587 typedef struct
588 {
589  __IO uint32_t Status;
591  uint32_t ControlBufferSize;
593  uint32_t Buffer1Addr;
595  uint32_t Buffer2NextDescAddr;
598  uint32_t ExtendedStatus;
600  uint32_t Reserved1;
602  uint32_t TimeStampLow;
604  uint32_t TimeStampHigh;
606 } ETH_DMADescTypeDef;
607 
608 
612 typedef struct
613 {
614  ETH_DMADescTypeDef *FSRxDesc;
616  ETH_DMADescTypeDef *LSRxDesc;
618  uint32_t SegCount;
620  uint32_t length;
622  uint32_t buffer;
624 } ETH_DMARxFrameInfos;
625 
626 
631 typedef struct
632 {
633  ETH_TypeDef *Instance;
635  ETH_InitTypeDef Init;
637  uint32_t LinkStatus;
639  ETH_DMADescTypeDef *RxDesc;
641  ETH_DMADescTypeDef *TxDesc;
643  ETH_DMARxFrameInfos RxFrameInfos;
645  __IO HAL_ETH_StateTypeDef State;
647  HAL_LockTypeDef Lock;
649 } ETH_HandleTypeDef;
650 
655 /* Exported constants --------------------------------------------------------*/
663 #define ETH_MAX_PACKET_SIZE ((uint32_t)1524U)
664 #define ETH_HEADER ((uint32_t)14U)
665 #define ETH_CRC ((uint32_t)4U)
666 #define ETH_EXTRA ((uint32_t)2U)
667 #define ETH_VLAN_TAG ((uint32_t)4U)
668 #define ETH_MIN_ETH_PAYLOAD ((uint32_t)46U)
669 #define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500U)
670 #define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000U)
672  /* Ethernet driver receive buffers are organized in a chained linked-list, when
673  an Ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
674  to the driver receive buffers memory.
675 
676  Depending on the size of the received Ethernet packet and the size of
677  each Ethernet driver receive buffer, the received packet can take one or more
678  Ethernet driver receive buffer.
679 
680  In below are defined the size of one Ethernet driver receive buffer ETH_RX_BUF_SIZE
681  and the total count of the driver receive buffers ETH_RXBUFNB.
682 
683  The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
684  example, they can be reconfigured in the application layer to fit the application
685  needs */
686 
687 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
688  packet */
689 #ifndef ETH_RX_BUF_SIZE
690  #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
691 #endif
692 
693 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
694 #ifndef ETH_RXBUFNB
695  #define ETH_RXBUFNB ((uint32_t)5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
696 #endif
697 
698 
699  /* Ethernet driver transmit buffers are organized in a chained linked-list, when
700  an Ethernet packet is transmitted, Tx-DMA will transfer the packet from the
701  driver transmit buffers memory to the TxFIFO.
702 
703  Depending on the size of the Ethernet packet to be transmitted and the size of
704  each Ethernet driver transmit buffer, the packet to be transmitted can take
705  one or more Ethernet driver transmit buffer.
706 
707  In below are defined the size of one Ethernet driver transmit buffer ETH_TX_BUF_SIZE
708  and the total count of the driver transmit buffers ETH_TXBUFNB.
709 
710  The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
711  example, they can be reconfigured in the application layer to fit the application
712  needs */
713 
714 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
715  packet */
716 #ifndef ETH_TX_BUF_SIZE
717  #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
718 #endif
719 
720 /* 5 Ethernet driver transmit buffers are used (in a chained linked list)*/
721 #ifndef ETH_TXBUFNB
722  #define ETH_TXBUFNB ((uint32_t)5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
723 #endif
724 
733 /*
734  DMA Tx Descriptor
735  -----------------------------------------------------------------------------------------------
736  TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
737  -----------------------------------------------------------------------------------------------
738  TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
739  -----------------------------------------------------------------------------------------------
740  TDES2 | Buffer1 Address [31:0] |
741  -----------------------------------------------------------------------------------------------
742  TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
743  -----------------------------------------------------------------------------------------------
744 */
745 
749 #define ETH_DMATXDESC_OWN ((uint32_t)0x80000000U)
750 #define ETH_DMATXDESC_IC ((uint32_t)0x40000000U)
751 #define ETH_DMATXDESC_LS ((uint32_t)0x20000000U)
752 #define ETH_DMATXDESC_FS ((uint32_t)0x10000000U)
753 #define ETH_DMATXDESC_DC ((uint32_t)0x08000000U)
754 #define ETH_DMATXDESC_DP ((uint32_t)0x04000000U)
755 #define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000U)
756 #define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000U)
757 #define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000U)
758 #define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000U)
759 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000U)
760 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000U)
761 #define ETH_DMATXDESC_TER ((uint32_t)0x00200000U)
762 #define ETH_DMATXDESC_TCH ((uint32_t)0x00100000U)
763 #define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000U)
764 #define ETH_DMATXDESC_IHE ((uint32_t)0x00010000U)
765 #define ETH_DMATXDESC_ES ((uint32_t)0x00008000U)
766 #define ETH_DMATXDESC_JT ((uint32_t)0x00004000U)
767 #define ETH_DMATXDESC_FF ((uint32_t)0x00002000U)
768 #define ETH_DMATXDESC_PCE ((uint32_t)0x00001000U)
769 #define ETH_DMATXDESC_LCA ((uint32_t)0x00000800U)
770 #define ETH_DMATXDESC_NC ((uint32_t)0x00000400U)
771 #define ETH_DMATXDESC_LCO ((uint32_t)0x00000200U)
772 #define ETH_DMATXDESC_EC ((uint32_t)0x00000100U)
773 #define ETH_DMATXDESC_VF ((uint32_t)0x00000080U)
774 #define ETH_DMATXDESC_CC ((uint32_t)0x00000078U)
775 #define ETH_DMATXDESC_ED ((uint32_t)0x00000004U)
776 #define ETH_DMATXDESC_UF ((uint32_t)0x00000002U)
777 #define ETH_DMATXDESC_DB ((uint32_t)0x00000001U)
782 #define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000U)
783 #define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFFU)
788 #define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFFU)
793 #define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFFU)
795  /*---------------------------------------------------------------------------------------------
796  TDES6 | Transmit Time Stamp Low [31:0] |
797  -----------------------------------------------------------------------------------------------
798  TDES7 | Transmit Time Stamp High [31:0] |
799  ----------------------------------------------------------------------------------------------*/
800 
801 /* Bit definition of TDES6 register */
802  #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp Low */
803 
804 /* Bit definition of TDES7 register */
805  #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp High */
806 
814 /*
815  DMA Rx Descriptor
816  --------------------------------------------------------------------------------------------------------------------
817  RDES0 | OWN(31) | Status [30:0] |
818  ---------------------------------------------------------------------------------------------------------------------
819  RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
820  ---------------------------------------------------------------------------------------------------------------------
821  RDES2 | Buffer1 Address [31:0] |
822  ---------------------------------------------------------------------------------------------------------------------
823  RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
824  ---------------------------------------------------------------------------------------------------------------------
825 */
826 
830 #define ETH_DMARXDESC_OWN ((uint32_t)0x80000000U)
831 #define ETH_DMARXDESC_AFM ((uint32_t)0x40000000U)
832 #define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000U)
833 #define ETH_DMARXDESC_ES ((uint32_t)0x00008000U)
834 #define ETH_DMARXDESC_DE ((uint32_t)0x00004000U)
835 #define ETH_DMARXDESC_SAF ((uint32_t)0x00002000U)
836 #define ETH_DMARXDESC_LE ((uint32_t)0x00001000U)
837 #define ETH_DMARXDESC_OE ((uint32_t)0x00000800U)
838 #define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400U)
839 #define ETH_DMARXDESC_FS ((uint32_t)0x00000200U)
840 #define ETH_DMARXDESC_LS ((uint32_t)0x00000100U)
841 #define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080U)
842 #define ETH_DMARXDESC_LC ((uint32_t)0x00000040U)
843 #define ETH_DMARXDESC_FT ((uint32_t)0x00000020U)
844 #define ETH_DMARXDESC_RWT ((uint32_t)0x00000010U)
845 #define ETH_DMARXDESC_RE ((uint32_t)0x00000008U)
846 #define ETH_DMARXDESC_DBE ((uint32_t)0x00000004U)
847 #define ETH_DMARXDESC_CE ((uint32_t)0x00000002U)
848 #define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001U)
853 #define ETH_DMARXDESC_DIC ((uint32_t)0x80000000U)
854 #define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000U)
855 #define ETH_DMARXDESC_RER ((uint32_t)0x00008000U)
856 #define ETH_DMARXDESC_RCH ((uint32_t)0x00004000U)
857 #define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFFU)
862 #define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFFU)
867 #define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFFU)
869 /*---------------------------------------------------------------------------------------------------------------------
870  RDES4 | Reserved[31:15] | Extended Status [14:0] |
871  ---------------------------------------------------------------------------------------------------------------------
872  RDES5 | Reserved[31:0] |
873  ---------------------------------------------------------------------------------------------------------------------
874  RDES6 | Receive Time Stamp Low [31:0] |
875  ---------------------------------------------------------------------------------------------------------------------
876  RDES7 | Receive Time Stamp High [31:0] |
877  --------------------------------------------------------------------------------------------------------------------*/
878 
879 /* Bit definition of RDES4 register */
880 #define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000U) /* PTP Version */
881 #define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000U) /* PTP Frame Type */
882 #define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00U) /* PTP Message Type */
883 #define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100U) /* SYNC message (all clock types) */
884 #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200U) /* FollowUp message (all clock types) */
885 #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300U) /* DelayReq message (all clock types) */
886 #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400U) /* DelayResp message (all clock types) */
887 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500U) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
888 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600U) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
889 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700U) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
890 #define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080U) /* IPv6 Packet Received */
891 #define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040U) /* IPv4 Packet Received */
892 #define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020U) /* IP Checksum Bypassed */
893 #define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010U) /* IP Payload Error */
894 #define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008U) /* IP Header Error */
895 #define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007U) /* IP Payload Type */
896 #define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001U) /* UDP payload encapsulated in the IP datagram */
897 #define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002U) /* TCP payload encapsulated in the IP datagram */
898 #define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003U) /* ICMP payload encapsulated in the IP datagram */
899 
900 /* Bit definition of RDES6 register */
901 #define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp Low */
902 
903 /* Bit definition of RDES7 register */
904 #define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp High */
905 
911 #define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001U)
912 #define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000U)
913 
920 #define ETH_SPEED_10M ((uint32_t)0x00000000U)
921 #define ETH_SPEED_100M ((uint32_t)0x00004000U)
922 
929 #define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800U)
930 #define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000U)
931 
937 #define ETH_RXPOLLING_MODE ((uint32_t)0x00000000U)
938 #define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001U)
939 
946 #define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000U)
947 #define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001U)
948 
955 #define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000U)
956 #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
957 
964 #define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000U)
965 #define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000U)
966 
973 #define ETH_JABBER_ENABLE ((uint32_t)0x00000000U)
974 #define ETH_JABBER_DISABLE ((uint32_t)0x00400000U)
975 
982 #define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000U)
983 #define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000U)
984 #define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000U)
985 #define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000U)
986 #define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000U)
987 #define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000U)
988 #define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000U)
989 #define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000U)
997 #define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000U)
998 #define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000U)
999 
1006 #define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000U)
1007 #define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000U)
1008 
1015 #define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000U)
1016 #define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000U)
1017 
1024 #define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400U)
1025 #define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000U)
1026 
1033 #define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000U)
1034 #define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200U)
1035 
1042 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080U)
1043 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000U)
1044 
1051 #define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000U)
1052 #define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020U)
1053 #define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040U)
1054 #define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060U)
1055 
1062 #define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010U)
1063 #define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000U)
1064 
1071 #define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000U)
1072 #define ETH_RECEIVEALL_DISABLE ((uint32_t)0x00000000U)
1073 
1080 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200U)
1081 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300U)
1082 #define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000U)
1083 
1090 #define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040U)
1091 #define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080U)
1092 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0U)
1100 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000U)
1101 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020U)
1102 
1109 #define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000U)
1110 #define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008U)
1111 
1118 #define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001U)
1119 #define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000U)
1120 
1127 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404U)
1128 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004U)
1129 #define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000U)
1130 #define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010U)
1131 
1138 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402U)
1139 #define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002U)
1140 #define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000U)
1141 
1148 #define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000U)
1149 #define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080U)
1150 
1157 #define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000U)
1158 #define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010U)
1159 #define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020U)
1160 #define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030U)
1168 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008U)
1169 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000U)
1170 
1177 #define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004U)
1178 #define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000U)
1179 
1186 #define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002U)
1187 #define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000U)
1188 
1195 #define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000U)
1196 #define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U)
1197 
1204 #define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000U)
1205 #define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008U)
1206 #define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010U)
1207 #define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018U)
1208 
1215 #define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000U)
1216 #define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008U)
1217 
1224 #define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000U)
1225 #define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000U)
1226 #define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000U)
1227 #define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000U)
1228 #define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000U)
1229 #define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000U)
1237 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000U)
1238 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000U)
1239 
1246 #define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000U)
1247 #define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000U)
1248 
1255 #define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000U)
1256 #define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000U)
1257 
1264 #define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000U)
1265 #define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000U)
1266 
1273 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000U)
1274 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000U)
1275 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000U)
1276 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000U)
1277 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000U)
1278 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000U)
1279 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000U)
1280 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000U)
1288 #define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080U)
1289 #define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000U)
1290 
1297 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040U)
1298 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000U)
1299 
1306 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000U)
1307 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008U)
1308 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010U)
1309 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018U)
1317 #define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004U)
1318 #define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000U)
1319 
1326 #define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000U)
1327 #define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000U)
1328 
1335 #define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000U)
1336 #define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000U)
1337 
1344 #define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000U)
1345 #define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000U)
1346 #define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000U)
1347 #define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000U)
1348 #define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000U)
1349 #define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000U)
1350 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000U)
1351 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000U)
1352 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000U)
1353 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000U)
1354 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000U)
1355 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000U)
1363 #define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100U)
1364 #define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200U)
1365 #define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400U)
1366 #define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800U)
1367 #define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000U)
1368 #define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000U)
1369 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100U)
1370 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200U)
1371 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400U)
1372 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800U)
1373 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000U)
1374 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000U)
1382 #define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080U)
1383 #define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000U)
1384 
1391 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000U)
1392 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000U)
1393 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000U)
1394 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000U)
1395 #define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002U)
1396 
1403 #define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000U)
1404 #define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000U)
1412 #define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000U)
1413 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000U)
1414 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000U)
1415 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000U)
1423 #define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000U)
1424 #define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001U)
1432 #define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000U)
1433 #define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040U)
1434 #define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020U)
1442 #define ETH_MMC_IT_TGF ((uint32_t)0x00200000U)
1443 #define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000U)
1444 #define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000U)
1452 #define ETH_MMC_IT_RGUF ((uint32_t)0x10020000U)
1453 #define ETH_MMC_IT_RFAE ((uint32_t)0x10000040U)
1454 #define ETH_MMC_IT_RFCE ((uint32_t)0x10000020U)
1462 #define ETH_MAC_FLAG_TST ((uint32_t)0x00000200U)
1463 #define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040U)
1464 #define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020U)
1465 #define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010U)
1466 #define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008U)
1474 #define ETH_DMA_FLAG_TST ((uint32_t)0x20000000U)
1475 #define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000U)
1476 #define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000U)
1477 #define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000U)
1478 #define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000U)
1479 #define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000U)
1480 #define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000U)
1481 #define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000U)
1482 #define ETH_DMA_FLAG_ER ((uint32_t)0x00004000U)
1483 #define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000U)
1484 #define ETH_DMA_FLAG_ET ((uint32_t)0x00000400U)
1485 #define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200U)
1486 #define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100U)
1487 #define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080U)
1488 #define ETH_DMA_FLAG_R ((uint32_t)0x00000040U)
1489 #define ETH_DMA_FLAG_TU ((uint32_t)0x00000020U)
1490 #define ETH_DMA_FLAG_RO ((uint32_t)0x00000010U)
1491 #define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008U)
1492 #define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004U)
1493 #define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002U)
1494 #define ETH_DMA_FLAG_T ((uint32_t)0x00000001U)
1502 #define ETH_MAC_IT_TST ((uint32_t)0x00000200U)
1503 #define ETH_MAC_IT_MMCT ((uint32_t)0x00000040U)
1504 #define ETH_MAC_IT_MMCR ((uint32_t)0x00000020U)
1505 #define ETH_MAC_IT_MMC ((uint32_t)0x00000010U)
1506 #define ETH_MAC_IT_PMT ((uint32_t)0x00000008U)
1514 #define ETH_DMA_IT_TST ((uint32_t)0x20000000U)
1515 #define ETH_DMA_IT_PMT ((uint32_t)0x10000000U)
1516 #define ETH_DMA_IT_MMC ((uint32_t)0x08000000U)
1517 #define ETH_DMA_IT_NIS ((uint32_t)0x00010000U)
1518 #define ETH_DMA_IT_AIS ((uint32_t)0x00008000U)
1519 #define ETH_DMA_IT_ER ((uint32_t)0x00004000U)
1520 #define ETH_DMA_IT_FBE ((uint32_t)0x00002000U)
1521 #define ETH_DMA_IT_ET ((uint32_t)0x00000400U)
1522 #define ETH_DMA_IT_RWT ((uint32_t)0x00000200U)
1523 #define ETH_DMA_IT_RPS ((uint32_t)0x00000100U)
1524 #define ETH_DMA_IT_RBU ((uint32_t)0x00000080U)
1525 #define ETH_DMA_IT_R ((uint32_t)0x00000040U)
1526 #define ETH_DMA_IT_TU ((uint32_t)0x00000020U)
1527 #define ETH_DMA_IT_RO ((uint32_t)0x00000010U)
1528 #define ETH_DMA_IT_TJT ((uint32_t)0x00000008U)
1529 #define ETH_DMA_IT_TBU ((uint32_t)0x00000004U)
1530 #define ETH_DMA_IT_TPS ((uint32_t)0x00000002U)
1531 #define ETH_DMA_IT_T ((uint32_t)0x00000001U)
1539 #define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000U)
1540 #define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000U)
1541 #define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000U)
1542 #define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000U)
1543 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000U)
1544 #define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000U)
1554 #define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000U)
1555 #define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000U)
1556 #define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000U)
1557 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000U)
1558 #define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000U)
1559 #define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000U)
1568 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000U)
1569 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000U)
1577 #define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000U)
1587 /* Exported macro ------------------------------------------------------------*/
1588 
1597 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
1598 
1605 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
1606 
1613 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
1614 
1620 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
1621 
1627 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
1628 
1634 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
1635 
1641 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
1642 
1648 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
1649 
1655 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
1656 
1662 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
1663 
1675 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
1676 
1682 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
1683 
1689 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
1690 
1696 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
1697 
1703 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
1704 
1715 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
1716 
1727 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
1728 
1734 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
1735 
1741 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
1742 
1748 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
1749 
1755 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
1756 
1769 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
1770 
1778 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
1779 
1787 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
1788 
1795 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
1796 
1803 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
1804 
1811 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
1812 
1822 #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
1823 
1830 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
1831 
1838 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
1839 
1846 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
1847 
1853 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
1854 
1860 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
1861 
1867 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
1868 
1874 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
1875 
1881 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
1882 
1888 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
1889 
1900 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
1901 
1907 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
1908 
1914 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
1915  (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
1916 
1922 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
1923 
1929 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
1930 
1936 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
1937 
1943 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
1944 
1950 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
1951 
1957 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
1958 
1964 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
1965 
1976 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
1977 
1987 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)
1988 
1998 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
1999 
2010 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
2011 
2016 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
2017 
2022 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
2023 
2028 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
2029 
2034 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
2035 
2040 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
2041 
2046 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
2047 
2052 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
2053 
2058 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
2059 
2064 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
2065 
2070 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
2071 
2076 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
2077  EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP
2078 
2083 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
2084  EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
2085 
2090 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
2091 
2095 /* Exported functions --------------------------------------------------------*/
2096 
2101 /* Initialization and de-initialization functions ****************************/
2102 
2106 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
2107 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
2108 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
2109 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
2110 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
2111 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
2112 
2116 /* IO operation functions ****************************************************/
2117 
2121 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
2122 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
2123 /* Communication with PHY functions*/
2124 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
2125 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
2126 /* Non-Blocking mode: Interrupt */
2127 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
2128 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
2129 /* Callback in non blocking modes (Interrupt) */
2130 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
2131 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
2132 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
2137 /* Peripheral Control functions **********************************************/
2138 
2143 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
2144 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
2145 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
2146 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
2151 /* Peripheral State functions ************************************************/
2152 
2156 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
2172 #ifdef __cplusplus
2173 }
2174 #endif
2175 
2176 #endif /* __STM32F7xx_HAL_ETH_H */
2177 
2178 
2179 
2180 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
HAL_ETH_GetReceivedFrame
HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
ETH_DMAInitTypeDef::RxDMABurstLength
uint32_t RxDMABurstLength
Definition: stm32f7xx_hal_eth.h:566
ETH_HandleTypeDef::RxDesc
ETH_DMADescTypeDef * RxDesc
Definition: stm32f7xx_hal_eth.h:639
ETH_MACInitTypeDef::UnicastPauseFrameDetect
uint32_t UnicastPauseFrameDetect
Definition: stm32f7xx_hal_eth.h:504
HAL_ETH_StateTypeDef
HAL_ETH_StateTypeDef
HAL State structures definition.
Definition: stm32f7xx_hal_eth.h:370
ETH_DMADescTypeDef::TimeStampHigh
uint32_t TimeStampHigh
Definition: stm32f7xx_hal_eth.h:604
ETH_DMAInitTypeDef::AddressAlignedBeats
uint32_t AddressAlignedBeats
Definition: stm32f7xx_hal_eth.h:560
ETH_MACInitTypeDef::InterFrameGap
uint32_t InterFrameGap
Definition: stm32f7xx_hal_eth.h:434
ETH_DMARxFrameInfos::SegCount
uint32_t SegCount
Definition: stm32f7xx_hal_eth.h:618
HAL_ETH_ErrorCallback
void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
ETH_DMADescTypeDef::TimeStampLow
uint32_t TimeStampLow
Definition: stm32f7xx_hal_eth.h:602
ETH_InitTypeDef::RxMode
uint32_t RxMode
Definition: stm32f7xx_hal_eth.h:406
ETH_MACInitTypeDef::PromiscuousMode
uint32_t PromiscuousMode
Definition: stm32f7xx_hal_eth.h:479
ETH_InitTypeDef::DuplexMode
uint32_t DuplexMode
Definition: stm32f7xx_hal_eth.h:398
HAL_ETH_Stop
HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
HAL_ETH_STATE_BUSY
Definition: stm32f7xx_hal_eth.h:374
HAL_ETH_Start
HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
HAL_ETH_STATE_READY
Definition: stm32f7xx_hal_eth.h:373
ETH_DMAInitTypeDef
ETH DMA Configuration Structure definition.
Definition: stm32f7xx_hal_eth.h:529
ETH_MACInitTypeDef::DeferralCheck
uint32_t DeferralCheck
Definition: stm32f7xx_hal_eth.h:461
ETH_HandleTypeDef::TxDesc
ETH_DMADescTypeDef * TxDesc
Definition: stm32f7xx_hal_eth.h:641
ETH_MACInitTypeDef::ReceiveOwn
uint32_t ReceiveOwn
Definition: stm32f7xx_hal_eth.h:440
ETH_DMADescTypeDef
ETH DMA Descriptors data structure definition.
Definition: stm32f7xx_hal_eth.h:587
ETH_MACInitTypeDef::AutomaticPadCRCStrip
uint32_t AutomaticPadCRCStrip
Definition: stm32f7xx_hal_eth.h:455
HAL_ETH_MspDeInit
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
ETH_HandleTypeDef::Init
ETH_InitTypeDef Init
Definition: stm32f7xx_hal_eth.h:635
ETH_MACInitTypeDef::PassControlFrames
uint32_t PassControlFrames
Definition: stm32f7xx_hal_eth.h:470
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition.
Definition: stm32f7xx_hal_def.h:67
ETH_DMADescTypeDef::Reserved1
uint32_t Reserved1
Definition: stm32f7xx_hal_eth.h:600
ETH_MACInitTypeDef::ChecksumOffload
uint32_t ChecksumOffload
Definition: stm32f7xx_hal_eth.h:448
ETH_MACInitTypeDef::DestinationAddrFilter
uint32_t DestinationAddrFilter
Definition: stm32f7xx_hal_eth.h:476
HAL_ETH_STATE_BUSY_RD
Definition: stm32f7xx_hal_eth.h:379
ETH_DMAInitTypeDef::TransmitStoreForward
uint32_t TransmitStoreForward
Definition: stm32f7xx_hal_eth.h:540
HAL_ETH_ConfigDMA
HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
ETH_DMARxFrameInfos::buffer
uint32_t buffer
Definition: stm32f7xx_hal_eth.h:622
ETH_HandleTypeDef::LinkStatus
uint32_t LinkStatus
Definition: stm32f7xx_hal_eth.h:637
ETH_DMADescTypeDef::Buffer1Addr
uint32_t Buffer1Addr
Definition: stm32f7xx_hal_eth.h:593
ETH_MACInitTypeDef::LoopbackMode
uint32_t LoopbackMode
Definition: stm32f7xx_hal_eth.h:445
ETH_InitTypeDef::AutoNegotiation
uint32_t AutoNegotiation
Definition: stm32f7xx_hal_eth.h:390
ETH_MACInitTypeDef::SourceAddrFilter
uint32_t SourceAddrFilter
Definition: stm32f7xx_hal_eth.h:467
ETH_MACInitTypeDef::ReceiveAll
uint32_t ReceiveAll
Definition: stm32f7xx_hal_eth.h:464
HAL_ETH_DeInit
HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
HAL_ETH_STATE_ERROR
Definition: stm32f7xx_hal_eth.h:381
ETH_HandleTypeDef::Lock
HAL_LockTypeDef Lock
Definition: stm32f7xx_hal_eth.h:647
ETH_DMAInitTypeDef::DescriptorSkipLength
uint32_t DescriptorSkipLength
Definition: stm32f7xx_hal_eth.h:575
HAL_ETH_DMATxDescListInit
HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
ETH_DMAInitTypeDef::FixedBurst
uint32_t FixedBurst
Definition: stm32f7xx_hal_eth.h:563
ETH_MACInitTypeDef::CarrierSense
uint32_t CarrierSense
Definition: stm32f7xx_hal_eth.h:437
ETH_InitTypeDef::ChecksumMode
uint32_t ChecksumMode
Definition: stm32f7xx_hal_eth.h:409
ETH_MACInitTypeDef::Jabber
uint32_t Jabber
Definition: stm32f7xx_hal_eth.h:429
ETH_DMAInitTypeDef::SecondFrameOperate
uint32_t SecondFrameOperate
Definition: stm32f7xx_hal_eth.h:556
ETH_InitTypeDef::Speed
uint32_t Speed
Definition: stm32f7xx_hal_eth.h:395
ETH_InitTypeDef::MediaInterface
uint32_t MediaInterface
Definition: stm32f7xx_hal_eth.h:412
ETH_MACInitTypeDef::BroadcastFramesReception
uint32_t BroadcastFramesReception
Definition: stm32f7xx_hal_eth.h:473
ETH_DMADescTypeDef::Buffer2NextDescAddr
uint32_t Buffer2NextDescAddr
Definition: stm32f7xx_hal_eth.h:595
ETH_DMARxFrameInfos::FSRxDesc
ETH_DMADescTypeDef * FSRxDesc
Definition: stm32f7xx_hal_eth.h:614
HAL_ETH_IRQHandler
void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
HAL_ETH_TransmitFrame
HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
HAL_ETH_STATE_BUSY_TX
Definition: stm32f7xx_hal_eth.h:375
__IO
#define __IO
Definition: core_cm0.h:213
ETH_DMAInitTypeDef::ForwardUndersizedGoodFrames
uint32_t ForwardUndersizedGoodFrames
Definition: stm32f7xx_hal_eth.h:549
HAL_ETH_ReadPHYRegister
HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
ETH_TypeDef
Ethernet MAC.
Definition: stm32f745xx.h:445
ETH_DMARxFrameInfos::LSRxDesc
ETH_DMADescTypeDef * LSRxDesc
Definition: stm32f7xx_hal_eth.h:616
ETH_DMARxFrameInfos
Received Frame Informations structure definition.
Definition: stm32f7xx_hal_eth.h:612
ETH_MACInitTypeDef
ETH MAC Configuration Structure definition.
Definition: stm32f7xx_hal_eth.h:422
ETH_MACInitTypeDef::PauseLowThreshold
uint32_t PauseLowThreshold
Definition: stm32f7xx_hal_eth.h:500
ETH_MACInitTypeDef::ReceiveFlowControl
uint32_t ReceiveFlowControl
Definition: stm32f7xx_hal_eth.h:508
ETH_DMAInitTypeDef::EnhancedDescriptorFormat
uint32_t EnhancedDescriptorFormat
Definition: stm32f7xx_hal_eth.h:572
ETH_InitTypeDef::MACAddr
uint8_t * MACAddr
Definition: stm32f7xx_hal_eth.h:404
ETH_DMAInitTypeDef::ForwardErrorFrames
uint32_t ForwardErrorFrames
Definition: stm32f7xx_hal_eth.h:546
ETH_MACInitTypeDef::TransmitFlowControl
uint32_t TransmitFlowControl
Definition: stm32f7xx_hal_eth.h:512
HAL_ETH_GetState
HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
ETH_MACInitTypeDef::PauseTime
uint32_t PauseTime
Definition: stm32f7xx_hal_eth.h:494
HAL_ETH_ConfigMAC
HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
ETH_MACInitTypeDef::HashTableLow
uint32_t HashTableLow
Definition: stm32f7xx_hal_eth.h:491
HAL_ETH_MspInit
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
Initializes the ETH MSP.
Definition: ethernetif.c:113
ETH_HandleTypeDef::RxFrameInfos
ETH_DMARxFrameInfos RxFrameInfos
Definition: stm32f7xx_hal_eth.h:643
ETH_DMAInitTypeDef::FlushReceivedFrame
uint32_t FlushReceivedFrame
Definition: stm32f7xx_hal_eth.h:537
ETH_MACInitTypeDef::MulticastFramesFilter
uint32_t MulticastFramesFilter
Definition: stm32f7xx_hal_eth.h:482
HAL_ETH_DMARxDescListInit
HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
ETH_MACInitTypeDef::ZeroQuantaPause
uint32_t ZeroQuantaPause
Definition: stm32f7xx_hal_eth.h:497
HAL_ETH_GetReceivedFrame_IT
HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
HAL_ETH_TxCpltCallback
void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
stm32f7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
ETH_InitTypeDef::PhyAddress
uint16_t PhyAddress
Definition: stm32f7xx_hal_eth.h:401
HAL_ETH_STATE_BUSY_TX_RX
Definition: stm32f7xx_hal_eth.h:377
HAL_ETH_RxCpltCallback
void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
Ethernet Rx Transfer completed callback.
Definition: ethernetif.c:165
ETH_MACInitTypeDef::UnicastFramesFilter
uint32_t UnicastFramesFilter
Definition: stm32f7xx_hal_eth.h:485
HAL_ETH_STATE_RESET
Definition: stm32f7xx_hal_eth.h:372
ETH_MACInitTypeDef::VLANTagIdentifier
uint32_t VLANTagIdentifier
Definition: stm32f7xx_hal_eth.h:520
ETH_MACInitTypeDef::Watchdog
uint32_t Watchdog
Definition: stm32f7xx_hal_eth.h:424
ETH_DMAInitTypeDef::DropTCPIPChecksumErrorFrame
uint32_t DropTCPIPChecksumErrorFrame
Definition: stm32f7xx_hal_eth.h:531
HAL_ETH_STATE_BUSY_WR
Definition: stm32f7xx_hal_eth.h:378
ETH_DMADescTypeDef::Status
__IO uint32_t Status
Definition: stm32f7xx_hal_eth.h:589
ETH_DMAInitTypeDef::ReceiveStoreForward
uint32_t ReceiveStoreForward
Definition: stm32f7xx_hal_eth.h:534
HAL_ETH_STATE_BUSY_RX
Definition: stm32f7xx_hal_eth.h:376
ETH_MACInitTypeDef::RetryTransmission
uint32_t RetryTransmission
Definition: stm32f7xx_hal_eth.h:451
ETH_HandleTypeDef::State
__IO HAL_ETH_StateTypeDef State
Definition: stm32f7xx_hal_eth.h:645
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32f7xx_hal_def.h:56
HAL_ETH_WritePHYRegister
HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
ETH_DMAInitTypeDef::ReceiveThresholdControl
uint32_t ReceiveThresholdControl
Definition: stm32f7xx_hal_eth.h:553
ETH_DMARxFrameInfos::length
uint32_t length
Definition: stm32f7xx_hal_eth.h:620
HAL_ETH_STATE_TIMEOUT
Definition: stm32f7xx_hal_eth.h:380
HAL_ETH_Init
HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
ETH_DMADescTypeDef::ExtendedStatus
uint32_t ExtendedStatus
Definition: stm32f7xx_hal_eth.h:598
ETH_HandleTypeDef::Instance
ETH_TypeDef * Instance
Definition: stm32f7xx_hal_eth.h:633
ETH_MACInitTypeDef::HashTableHigh
uint32_t HashTableHigh
Definition: stm32f7xx_hal_eth.h:488
ETH_DMAInitTypeDef::TxDMABurstLength
uint32_t TxDMABurstLength
Definition: stm32f7xx_hal_eth.h:569
ETH_HandleTypeDef
ETH Handle Structure definition.
Definition: stm32f7xx_hal_eth.h:631
ETH_MACInitTypeDef::BackOffLimit
uint32_t BackOffLimit
Definition: stm32f7xx_hal_eth.h:458
ETH_InitTypeDef
ETH Init Structure definition.
Definition: stm32f7xx_hal_eth.h:388
ETH_DMAInitTypeDef::TransmitThresholdControl
uint32_t TransmitThresholdControl
Definition: stm32f7xx_hal_eth.h:543
ETH_DMADescTypeDef::ControlBufferSize
uint32_t ControlBufferSize
Definition: stm32f7xx_hal_eth.h:591
ETH_DMAInitTypeDef::DMAArbitration
uint32_t DMAArbitration
Definition: stm32f7xx_hal_eth.h:578
ETH_MACInitTypeDef::VLANTagComparison
uint32_t VLANTagComparison
Definition: stm32f7xx_hal_eth.h:516
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