STM32F769IDiscovery  1.00
uDANTE Audio Networking with STM32F7 DISCO board
Data Structures | Macros | Enumerations | Functions
stm32f7xx_hal_eth.h File Reference

Header file of ETH HAL module. More...

#include "stm32f7xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct  ETH_InitTypeDef
 ETH Init Structure definition. More...
 
struct  ETH_MACInitTypeDef
 ETH MAC Configuration Structure definition. More...
 
struct  ETH_DMAInitTypeDef
 ETH DMA Configuration Structure definition. More...
 
struct  ETH_DMADescTypeDef
 ETH DMA Descriptors data structure definition. More...
 
struct  ETH_DMARxFrameInfos
 Received Frame Informations structure definition. More...
 
struct  ETH_HandleTypeDef
 ETH Handle Structure definition. More...
 

Macros

#define IS_ETH_PHY_ADDRESS(ADDRESS)   ((ADDRESS) <= 0x20)
 
#define IS_ETH_AUTONEGOTIATION(CMD)
 
#define IS_ETH_SPEED(SPEED)
 
#define IS_ETH_DUPLEX_MODE(MODE)
 
#define IS_ETH_RX_MODE(MODE)
 
#define IS_ETH_CHECKSUM_MODE(MODE)
 
#define IS_ETH_MEDIA_INTERFACE(MODE)
 
#define IS_ETH_WATCHDOG(CMD)
 
#define IS_ETH_JABBER(CMD)
 
#define IS_ETH_INTER_FRAME_GAP(GAP)
 
#define IS_ETH_CARRIER_SENSE(CMD)
 
#define IS_ETH_RECEIVE_OWN(CMD)
 
#define IS_ETH_LOOPBACK_MODE(CMD)
 
#define IS_ETH_CHECKSUM_OFFLOAD(CMD)
 
#define IS_ETH_RETRY_TRANSMISSION(CMD)
 
#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD)
 
#define IS_ETH_BACKOFF_LIMIT(LIMIT)
 
#define IS_ETH_DEFERRAL_CHECK(CMD)
 
#define IS_ETH_RECEIVE_ALL(CMD)
 
#define IS_ETH_SOURCE_ADDR_FILTER(CMD)
 
#define IS_ETH_CONTROL_FRAMES(PASS)
 
#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD)
 
#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER)
 
#define IS_ETH_PROMISCUOUS_MODE(CMD)
 
#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER)
 
#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER)
 
#define IS_ETH_PAUSE_TIME(TIME)   ((TIME) <= 0xFFFF)
 
#define IS_ETH_ZEROQUANTA_PAUSE(CMD)
 
#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD)
 
#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD)
 
#define IS_ETH_RECEIVE_FLOWCONTROL(CMD)
 
#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD)
 
#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON)
 
#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER)   ((IDENTIFIER) <= 0xFFFF)
 
#define IS_ETH_MAC_ADDRESS0123(ADDRESS)
 
#define IS_ETH_MAC_ADDRESS123(ADDRESS)
 
#define IS_ETH_MAC_ADDRESS_FILTER(FILTER)
 
#define IS_ETH_MAC_ADDRESS_MASK(MASK)
 
#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD)
 
#define IS_ETH_RECEIVE_STORE_FORWARD(CMD)
 
#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD)
 
#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD)
 
#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD)
 
#define IS_ETH_FORWARD_ERROR_FRAMES(CMD)
 
#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD)
 
#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD)
 
#define IS_ETH_SECOND_FRAME_OPERATE(CMD)
 
#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD)
 
#define IS_ETH_FIXED_BURST(CMD)
 
#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH)
 
#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH)
 
#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH)   ((LENGTH) <= 0x1F)
 
#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO)
 
#define IS_ETH_DMATXDESC_GET_FLAG(FLAG)
 
#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT)
 
#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM)
 
#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE)   ((SIZE) <= 0x1FFF)
 
#define IS_ETH_DMARXDESC_GET_FLAG(FLAG)
 
#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER)
 
#define IS_ETH_PMT_GET_FLAG(FLAG)
 
#define IS_ETH_DMA_FLAG(FLAG)   ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))
 
#define IS_ETH_DMA_GET_FLAG(FLAG)
 
#define IS_ETH_MAC_IT(IT)   ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00))
 
#define IS_ETH_MAC_GET_IT(IT)
 
#define IS_ETH_MAC_GET_FLAG(FLAG)
 
#define IS_ETH_DMA_IT(IT)   ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
 
#define IS_ETH_DMA_GET_IT(IT)
 
#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW)
 
#define IS_ETH_MMC_IT(IT)
 
#define IS_ETH_MMC_GET_IT(IT)
 
#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD)
 
#define ETH_REG_WRITE_DELAY   ((uint32_t)0x00000001U)
 
#define ETH_SUCCESS   ((uint32_t)0U)
 
#define ETH_ERROR   ((uint32_t)1U)
 
#define ETH_DMATXDESC_COLLISION_COUNTSHIFT   ((uint32_t)3U)
 
#define ETH_DMATXDESC_BUFFER2_SIZESHIFT   ((uint32_t)16U)
 
#define ETH_DMARXDESC_FRAME_LENGTHSHIFT   ((uint32_t)16U)
 
#define ETH_DMARXDESC_BUFFER2_SIZESHIFT   ((uint32_t)16U)
 
#define ETH_DMARXDESC_FRAMELENGTHSHIFT   ((uint32_t)16)
 
#define ETH_MAC_ADDR_HBASE   (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40U) /* Ethernet MAC address high offset */
 
#define ETH_MAC_ADDR_LBASE   (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44U) /* Ethernet MAC address low offset */
 
#define ETH_MACMIIAR_CR_MASK   ((uint32_t)0xFFFFFFE3U)
 
#define ETH_MACCR_CLEAR_MASK   ((uint32_t)0xFF20810FU)
 
#define ETH_MACFCR_CLEAR_MASK   ((uint32_t)0x0000FF41U)
 
#define ETH_DMAOMR_CLEAR_MASK   ((uint32_t)0xF8DE3F23U)
 
#define ETH_WAKEUP_REGISTER_LENGTH   8U
 
#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT   17U
 
#define ETH_MAX_PACKET_SIZE   ((uint32_t)1524U)
 
#define ETH_HEADER   ((uint32_t)14U)
 
#define ETH_CRC   ((uint32_t)4U)
 
#define ETH_EXTRA   ((uint32_t)2U)
 
#define ETH_VLAN_TAG   ((uint32_t)4U)
 
#define ETH_MIN_ETH_PAYLOAD   ((uint32_t)46U)
 
#define ETH_MAX_ETH_PAYLOAD   ((uint32_t)1500U)
 
#define ETH_JUMBO_FRAME_PAYLOAD   ((uint32_t)9000U)
 
#define ETH_RX_BUF_SIZE   ETH_MAX_PACKET_SIZE
 
#define ETH_RXBUFNB   ((uint32_t)5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
 
#define ETH_TX_BUF_SIZE   ETH_MAX_PACKET_SIZE
 
#define ETH_TXBUFNB   ((uint32_t)5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
 
#define ETH_DMATXDESC_OWN   ((uint32_t)0x80000000U)
 Bit definition of TDES0 register: DMA Tx descriptor status register. More...
 
#define ETH_DMATXDESC_IC   ((uint32_t)0x40000000U)
 
#define ETH_DMATXDESC_LS   ((uint32_t)0x20000000U)
 
#define ETH_DMATXDESC_FS   ((uint32_t)0x10000000U)
 
#define ETH_DMATXDESC_DC   ((uint32_t)0x08000000U)
 
#define ETH_DMATXDESC_DP   ((uint32_t)0x04000000U)
 
#define ETH_DMATXDESC_TTSE   ((uint32_t)0x02000000U)
 
#define ETH_DMATXDESC_CIC   ((uint32_t)0x00C00000U)
 
#define ETH_DMATXDESC_CIC_BYPASS   ((uint32_t)0x00000000U)
 
#define ETH_DMATXDESC_CIC_IPV4HEADER   ((uint32_t)0x00400000U)
 
#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT   ((uint32_t)0x00800000U)
 
#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL   ((uint32_t)0x00C00000U)
 
#define ETH_DMATXDESC_TER   ((uint32_t)0x00200000U)
 
#define ETH_DMATXDESC_TCH   ((uint32_t)0x00100000U)
 
#define ETH_DMATXDESC_TTSS   ((uint32_t)0x00020000U)
 
#define ETH_DMATXDESC_IHE   ((uint32_t)0x00010000U)
 
#define ETH_DMATXDESC_ES   ((uint32_t)0x00008000U)
 
#define ETH_DMATXDESC_JT   ((uint32_t)0x00004000U)
 
#define ETH_DMATXDESC_FF   ((uint32_t)0x00002000U)
 
#define ETH_DMATXDESC_PCE   ((uint32_t)0x00001000U)
 
#define ETH_DMATXDESC_LCA   ((uint32_t)0x00000800U)
 
#define ETH_DMATXDESC_NC   ((uint32_t)0x00000400U)
 
#define ETH_DMATXDESC_LCO   ((uint32_t)0x00000200U)
 
#define ETH_DMATXDESC_EC   ((uint32_t)0x00000100U)
 
#define ETH_DMATXDESC_VF   ((uint32_t)0x00000080U)
 
#define ETH_DMATXDESC_CC   ((uint32_t)0x00000078U)
 
#define ETH_DMATXDESC_ED   ((uint32_t)0x00000004U)
 
#define ETH_DMATXDESC_UF   ((uint32_t)0x00000002U)
 
#define ETH_DMATXDESC_DB   ((uint32_t)0x00000001U)
 
#define ETH_DMATXDESC_TBS2   ((uint32_t)0x1FFF0000U)
 Bit definition of TDES1 register. More...
 
#define ETH_DMATXDESC_TBS1   ((uint32_t)0x00001FFFU)
 
#define ETH_DMATXDESC_B1AP   ((uint32_t)0xFFFFFFFFU)
 Bit definition of TDES2 register. More...
 
#define ETH_DMATXDESC_B2AP   ((uint32_t)0xFFFFFFFFU)
 Bit definition of TDES3 register. More...
 
#define ETH_DMAPTPTXDESC_TTSL   ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp Low */
 
#define ETH_DMAPTPTXDESC_TTSH   ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp High */
 
#define ETH_DMARXDESC_OWN   ((uint32_t)0x80000000U)
 Bit definition of RDES0 register: DMA Rx descriptor status register. More...
 
#define ETH_DMARXDESC_AFM   ((uint32_t)0x40000000U)
 
#define ETH_DMARXDESC_FL   ((uint32_t)0x3FFF0000U)
 
#define ETH_DMARXDESC_ES   ((uint32_t)0x00008000U)
 
#define ETH_DMARXDESC_DE   ((uint32_t)0x00004000U)
 
#define ETH_DMARXDESC_SAF   ((uint32_t)0x00002000U)
 
#define ETH_DMARXDESC_LE   ((uint32_t)0x00001000U)
 
#define ETH_DMARXDESC_OE   ((uint32_t)0x00000800U)
 
#define ETH_DMARXDESC_VLAN   ((uint32_t)0x00000400U)
 
#define ETH_DMARXDESC_FS   ((uint32_t)0x00000200U)
 
#define ETH_DMARXDESC_LS   ((uint32_t)0x00000100U)
 
#define ETH_DMARXDESC_IPV4HCE   ((uint32_t)0x00000080U)
 
#define ETH_DMARXDESC_LC   ((uint32_t)0x00000040U)
 
#define ETH_DMARXDESC_FT   ((uint32_t)0x00000020U)
 
#define ETH_DMARXDESC_RWT   ((uint32_t)0x00000010U)
 
#define ETH_DMARXDESC_RE   ((uint32_t)0x00000008U)
 
#define ETH_DMARXDESC_DBE   ((uint32_t)0x00000004U)
 
#define ETH_DMARXDESC_CE   ((uint32_t)0x00000002U)
 
#define ETH_DMARXDESC_MAMPCE   ((uint32_t)0x00000001U)
 
#define ETH_DMARXDESC_DIC   ((uint32_t)0x80000000U)
 Bit definition of RDES1 register. More...
 
#define ETH_DMARXDESC_RBS2   ((uint32_t)0x1FFF0000U)
 
#define ETH_DMARXDESC_RER   ((uint32_t)0x00008000U)
 
#define ETH_DMARXDESC_RCH   ((uint32_t)0x00004000U)
 
#define ETH_DMARXDESC_RBS1   ((uint32_t)0x00001FFFU)
 
#define ETH_DMARXDESC_B1AP   ((uint32_t)0xFFFFFFFFU)
 Bit definition of RDES2 register. More...
 
#define ETH_DMARXDESC_B2AP   ((uint32_t)0xFFFFFFFFU)
 Bit definition of RDES3 register. More...
 
#define ETH_DMAPTPRXDESC_PTPV   ((uint32_t)0x00002000U) /* PTP Version */
 
#define ETH_DMAPTPRXDESC_PTPFT   ((uint32_t)0x00001000U) /* PTP Frame Type */
 
#define ETH_DMAPTPRXDESC_PTPMT   ((uint32_t)0x00000F00U) /* PTP Message Type */
 
#define ETH_DMAPTPRXDESC_PTPMT_SYNC   ((uint32_t)0x00000100U) /* SYNC message (all clock types) */
 
#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP   ((uint32_t)0x00000200U) /* FollowUp message (all clock types) */
 
#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ   ((uint32_t)0x00000300U) /* DelayReq message (all clock types) */
 
#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP   ((uint32_t)0x00000400U) /* DelayResp message (all clock types) */
 
#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE   ((uint32_t)0x00000500U) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
 
#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG   ((uint32_t)0x00000600U) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
 
#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL   ((uint32_t)0x00000700U) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
 
#define ETH_DMAPTPRXDESC_IPV6PR   ((uint32_t)0x00000080U) /* IPv6 Packet Received */
 
#define ETH_DMAPTPRXDESC_IPV4PR   ((uint32_t)0x00000040U) /* IPv4 Packet Received */
 
#define ETH_DMAPTPRXDESC_IPCB   ((uint32_t)0x00000020U) /* IP Checksum Bypassed */
 
#define ETH_DMAPTPRXDESC_IPPE   ((uint32_t)0x00000010U) /* IP Payload Error */
 
#define ETH_DMAPTPRXDESC_IPHE   ((uint32_t)0x00000008U) /* IP Header Error */
 
#define ETH_DMAPTPRXDESC_IPPT   ((uint32_t)0x00000007U) /* IP Payload Type */
 
#define ETH_DMAPTPRXDESC_IPPT_UDP   ((uint32_t)0x00000001U) /* UDP payload encapsulated in the IP datagram */
 
#define ETH_DMAPTPRXDESC_IPPT_TCP   ((uint32_t)0x00000002U) /* TCP payload encapsulated in the IP datagram */
 
#define ETH_DMAPTPRXDESC_IPPT_ICMP   ((uint32_t)0x00000003U) /* ICMP payload encapsulated in the IP datagram */
 
#define ETH_DMAPTPRXDESC_RTSL   ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp Low */
 
#define ETH_DMAPTPRXDESC_RTSH   ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp High */
 
#define ETH_AUTONEGOTIATION_ENABLE   ((uint32_t)0x00000001U)
 
#define ETH_AUTONEGOTIATION_DISABLE   ((uint32_t)0x00000000U)
 
#define ETH_SPEED_10M   ((uint32_t)0x00000000U)
 
#define ETH_SPEED_100M   ((uint32_t)0x00004000U)
 
#define ETH_MODE_FULLDUPLEX   ((uint32_t)0x00000800U)
 
#define ETH_MODE_HALFDUPLEX   ((uint32_t)0x00000000U)
 
#define ETH_RXPOLLING_MODE   ((uint32_t)0x00000000U)
 
#define ETH_RXINTERRUPT_MODE   ((uint32_t)0x00000001U)
 
#define ETH_CHECKSUM_BY_HARDWARE   ((uint32_t)0x00000000U)
 
#define ETH_CHECKSUM_BY_SOFTWARE   ((uint32_t)0x00000001U)
 
#define ETH_MEDIA_INTERFACE_MII   ((uint32_t)0x00000000U)
 
#define ETH_MEDIA_INTERFACE_RMII   ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
 
#define ETH_WATCHDOG_ENABLE   ((uint32_t)0x00000000U)
 
#define ETH_WATCHDOG_DISABLE   ((uint32_t)0x00800000U)
 
#define ETH_JABBER_ENABLE   ((uint32_t)0x00000000U)
 
#define ETH_JABBER_DISABLE   ((uint32_t)0x00400000U)
 
#define ETH_INTERFRAMEGAP_96BIT   ((uint32_t)0x00000000U)
 
#define ETH_INTERFRAMEGAP_88BIT   ((uint32_t)0x00020000U)
 
#define ETH_INTERFRAMEGAP_80BIT   ((uint32_t)0x00040000U)
 
#define ETH_INTERFRAMEGAP_72BIT   ((uint32_t)0x00060000U)
 
#define ETH_INTERFRAMEGAP_64BIT   ((uint32_t)0x00080000U)
 
#define ETH_INTERFRAMEGAP_56BIT   ((uint32_t)0x000A0000U)
 
#define ETH_INTERFRAMEGAP_48BIT   ((uint32_t)0x000C0000U)
 
#define ETH_INTERFRAMEGAP_40BIT   ((uint32_t)0x000E0000U)
 
#define ETH_CARRIERSENCE_ENABLE   ((uint32_t)0x00000000U)
 
#define ETH_CARRIERSENCE_DISABLE   ((uint32_t)0x00010000U)
 
#define ETH_RECEIVEOWN_ENABLE   ((uint32_t)0x00000000U)
 
#define ETH_RECEIVEOWN_DISABLE   ((uint32_t)0x00002000U)
 
#define ETH_LOOPBACKMODE_ENABLE   ((uint32_t)0x00001000U)
 
#define ETH_LOOPBACKMODE_DISABLE   ((uint32_t)0x00000000U)
 
#define ETH_CHECKSUMOFFLAOD_ENABLE   ((uint32_t)0x00000400U)
 
#define ETH_CHECKSUMOFFLAOD_DISABLE   ((uint32_t)0x00000000U)
 
#define ETH_RETRYTRANSMISSION_ENABLE   ((uint32_t)0x00000000U)
 
#define ETH_RETRYTRANSMISSION_DISABLE   ((uint32_t)0x00000200U)
 
#define ETH_AUTOMATICPADCRCSTRIP_ENABLE   ((uint32_t)0x00000080U)
 
#define ETH_AUTOMATICPADCRCSTRIP_DISABLE   ((uint32_t)0x00000000U)
 
#define ETH_BACKOFFLIMIT_10   ((uint32_t)0x00000000U)
 
#define ETH_BACKOFFLIMIT_8   ((uint32_t)0x00000020U)
 
#define ETH_BACKOFFLIMIT_4   ((uint32_t)0x00000040U)
 
#define ETH_BACKOFFLIMIT_1   ((uint32_t)0x00000060U)
 
#define ETH_DEFFERRALCHECK_ENABLE   ((uint32_t)0x00000010U)
 
#define ETH_DEFFERRALCHECK_DISABLE   ((uint32_t)0x00000000U)
 
#define ETH_RECEIVEALL_ENABLE   ((uint32_t)0x80000000U)
 
#define ETH_RECEIVEALL_DISABLE   ((uint32_t)0x00000000U)
 
#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE   ((uint32_t)0x00000200U)
 
#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE   ((uint32_t)0x00000300U)
 
#define ETH_SOURCEADDRFILTER_DISABLE   ((uint32_t)0x00000000U)
 
#define ETH_PASSCONTROLFRAMES_BLOCKALL   ((uint32_t)0x00000040U)
 
#define ETH_PASSCONTROLFRAMES_FORWARDALL   ((uint32_t)0x00000080U)
 
#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER   ((uint32_t)0x000000C0U)
 
#define ETH_BROADCASTFRAMESRECEPTION_ENABLE   ((uint32_t)0x00000000U)
 
#define ETH_BROADCASTFRAMESRECEPTION_DISABLE   ((uint32_t)0x00000020U)
 
#define ETH_DESTINATIONADDRFILTER_NORMAL   ((uint32_t)0x00000000U)
 
#define ETH_DESTINATIONADDRFILTER_INVERSE   ((uint32_t)0x00000008U)
 
#define ETH_PROMISCUOUS_MODE_ENABLE   ((uint32_t)0x00000001U)
 
#define ETH_PROMISCUOUS_MODE_DISABLE   ((uint32_t)0x00000000U)
 
#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE   ((uint32_t)0x00000404U)
 
#define ETH_MULTICASTFRAMESFILTER_HASHTABLE   ((uint32_t)0x00000004U)
 
#define ETH_MULTICASTFRAMESFILTER_PERFECT   ((uint32_t)0x00000000U)
 
#define ETH_MULTICASTFRAMESFILTER_NONE   ((uint32_t)0x00000010U)
 
#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE   ((uint32_t)0x00000402U)
 
#define ETH_UNICASTFRAMESFILTER_HASHTABLE   ((uint32_t)0x00000002U)
 
#define ETH_UNICASTFRAMESFILTER_PERFECT   ((uint32_t)0x00000000U)
 
#define ETH_ZEROQUANTAPAUSE_ENABLE   ((uint32_t)0x00000000U)
 
#define ETH_ZEROQUANTAPAUSE_DISABLE   ((uint32_t)0x00000080U)
 
#define ETH_PAUSELOWTHRESHOLD_MINUS4   ((uint32_t)0x00000000U)
 
#define ETH_PAUSELOWTHRESHOLD_MINUS28   ((uint32_t)0x00000010U)
 
#define ETH_PAUSELOWTHRESHOLD_MINUS144   ((uint32_t)0x00000020U)
 
#define ETH_PAUSELOWTHRESHOLD_MINUS256   ((uint32_t)0x00000030U)
 
#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE   ((uint32_t)0x00000008U)
 
#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE   ((uint32_t)0x00000000U)
 
#define ETH_RECEIVEFLOWCONTROL_ENABLE   ((uint32_t)0x00000004U)
 
#define ETH_RECEIVEFLOWCONTROL_DISABLE   ((uint32_t)0x00000000U)
 
#define ETH_TRANSMITFLOWCONTROL_ENABLE   ((uint32_t)0x00000002U)
 
#define ETH_TRANSMITFLOWCONTROL_DISABLE   ((uint32_t)0x00000000U)
 
#define ETH_VLANTAGCOMPARISON_12BIT   ((uint32_t)0x00010000U)
 
#define ETH_VLANTAGCOMPARISON_16BIT   ((uint32_t)0x00000000U)
 
#define ETH_MAC_ADDRESS0   ((uint32_t)0x00000000U)
 
#define ETH_MAC_ADDRESS1   ((uint32_t)0x00000008U)
 
#define ETH_MAC_ADDRESS2   ((uint32_t)0x00000010U)
 
#define ETH_MAC_ADDRESS3   ((uint32_t)0x00000018U)
 
#define ETH_MAC_ADDRESSFILTER_SA   ((uint32_t)0x00000000U)
 
#define ETH_MAC_ADDRESSFILTER_DA   ((uint32_t)0x00000008U)
 
#define ETH_MAC_ADDRESSMASK_BYTE6   ((uint32_t)0x20000000U)
 
#define ETH_MAC_ADDRESSMASK_BYTE5   ((uint32_t)0x10000000U)
 
#define ETH_MAC_ADDRESSMASK_BYTE4   ((uint32_t)0x08000000U)
 
#define ETH_MAC_ADDRESSMASK_BYTE3   ((uint32_t)0x04000000U)
 
#define ETH_MAC_ADDRESSMASK_BYTE2   ((uint32_t)0x02000000U)
 
#define ETH_MAC_ADDRESSMASK_BYTE1   ((uint32_t)0x01000000U)
 
#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE   ((uint32_t)0x00000000U)
 
#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE   ((uint32_t)0x04000000U)
 
#define ETH_RECEIVESTOREFORWARD_ENABLE   ((uint32_t)0x02000000U)
 
#define ETH_RECEIVESTOREFORWARD_DISABLE   ((uint32_t)0x00000000U)
 
#define ETH_FLUSHRECEIVEDFRAME_ENABLE   ((uint32_t)0x00000000U)
 
#define ETH_FLUSHRECEIVEDFRAME_DISABLE   ((uint32_t)0x01000000U)
 
#define ETH_TRANSMITSTOREFORWARD_ENABLE   ((uint32_t)0x00200000U)
 
#define ETH_TRANSMITSTOREFORWARD_DISABLE   ((uint32_t)0x00000000U)
 
#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES   ((uint32_t)0x00000000U)
 
#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES   ((uint32_t)0x00004000U)
 
#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES   ((uint32_t)0x00008000U)
 
#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES   ((uint32_t)0x0000C000U)
 
#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES   ((uint32_t)0x00010000U)
 
#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES   ((uint32_t)0x00014000U)
 
#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES   ((uint32_t)0x00018000U)
 
#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES   ((uint32_t)0x0001C000U)
 
#define ETH_FORWARDERRORFRAMES_ENABLE   ((uint32_t)0x00000080U)
 
#define ETH_FORWARDERRORFRAMES_DISABLE   ((uint32_t)0x00000000U)
 
#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE   ((uint32_t)0x00000040U)
 
#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE   ((uint32_t)0x00000000U)
 
#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES   ((uint32_t)0x00000000U)
 
#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES   ((uint32_t)0x00000008U)
 
#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES   ((uint32_t)0x00000010U)
 
#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES   ((uint32_t)0x00000018U)
 
#define ETH_SECONDFRAMEOPERARTE_ENABLE   ((uint32_t)0x00000004U)
 
#define ETH_SECONDFRAMEOPERARTE_DISABLE   ((uint32_t)0x00000000U)
 
#define ETH_ADDRESSALIGNEDBEATS_ENABLE   ((uint32_t)0x02000000U)
 
#define ETH_ADDRESSALIGNEDBEATS_DISABLE   ((uint32_t)0x00000000U)
 
#define ETH_FIXEDBURST_ENABLE   ((uint32_t)0x00010000U)
 
#define ETH_FIXEDBURST_DISABLE   ((uint32_t)0x00000000U)
 
#define ETH_RXDMABURSTLENGTH_1BEAT   ((uint32_t)0x00020000U)
 
#define ETH_RXDMABURSTLENGTH_2BEAT   ((uint32_t)0x00040000U)
 
#define ETH_RXDMABURSTLENGTH_4BEAT   ((uint32_t)0x00080000U)
 
#define ETH_RXDMABURSTLENGTH_8BEAT   ((uint32_t)0x00100000U)
 
#define ETH_RXDMABURSTLENGTH_16BEAT   ((uint32_t)0x00200000U)
 
#define ETH_RXDMABURSTLENGTH_32BEAT   ((uint32_t)0x00400000U)
 
#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT   ((uint32_t)0x01020000U)
 
#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT   ((uint32_t)0x01040000U)
 
#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT   ((uint32_t)0x01080000U)
 
#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT   ((uint32_t)0x01100000U)
 
#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT   ((uint32_t)0x01200000U)
 
#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT   ((uint32_t)0x01400000U)
 
#define ETH_TXDMABURSTLENGTH_1BEAT   ((uint32_t)0x00000100U)
 
#define ETH_TXDMABURSTLENGTH_2BEAT   ((uint32_t)0x00000200U)
 
#define ETH_TXDMABURSTLENGTH_4BEAT   ((uint32_t)0x00000400U)
 
#define ETH_TXDMABURSTLENGTH_8BEAT   ((uint32_t)0x00000800U)
 
#define ETH_TXDMABURSTLENGTH_16BEAT   ((uint32_t)0x00001000U)
 
#define ETH_TXDMABURSTLENGTH_32BEAT   ((uint32_t)0x00002000U)
 
#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT   ((uint32_t)0x01000100U)
 
#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT   ((uint32_t)0x01000200U)
 
#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT   ((uint32_t)0x01000400U)
 
#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT   ((uint32_t)0x01000800U)
 
#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT   ((uint32_t)0x01001000U)
 
#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT   ((uint32_t)0x01002000U)
 
#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE   ((uint32_t)0x00000080U)
 
#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE   ((uint32_t)0x00000000U)
 
#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1   ((uint32_t)0x00000000U)
 
#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1   ((uint32_t)0x00004000U)
 
#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1   ((uint32_t)0x00008000U)
 
#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1   ((uint32_t)0x0000C000U)
 
#define ETH_DMAARBITRATION_RXPRIORTX   ((uint32_t)0x00000002U)
 
#define ETH_DMATXDESC_LASTSEGMENTS   ((uint32_t)0x40000000U)
 
#define ETH_DMATXDESC_FIRSTSEGMENT   ((uint32_t)0x20000000U)
 
#define ETH_DMATXDESC_CHECKSUMBYPASS   ((uint32_t)0x00000000U)
 
#define ETH_DMATXDESC_CHECKSUMIPV4HEADER   ((uint32_t)0x00400000U)
 
#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT   ((uint32_t)0x00800000U)
 
#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL   ((uint32_t)0x00C00000U)
 
#define ETH_DMARXDESC_BUFFER1   ((uint32_t)0x00000000U)
 
#define ETH_DMARXDESC_BUFFER2   ((uint32_t)0x00000001U)
 
#define ETH_PMT_FLAG_WUFFRPR   ((uint32_t)0x80000000U)
 
#define ETH_PMT_FLAG_WUFR   ((uint32_t)0x00000040U)
 
#define ETH_PMT_FLAG_MPR   ((uint32_t)0x00000020U)
 
#define ETH_MMC_IT_TGF   ((uint32_t)0x00200000U)
 
#define ETH_MMC_IT_TGFMSC   ((uint32_t)0x00008000U)
 
#define ETH_MMC_IT_TGFSC   ((uint32_t)0x00004000U)
 
#define ETH_MMC_IT_RGUF   ((uint32_t)0x10020000U)
 
#define ETH_MMC_IT_RFAE   ((uint32_t)0x10000040U)
 
#define ETH_MMC_IT_RFCE   ((uint32_t)0x10000020U)
 
#define ETH_MAC_FLAG_TST   ((uint32_t)0x00000200U)
 
#define ETH_MAC_FLAG_MMCT   ((uint32_t)0x00000040U)
 
#define ETH_MAC_FLAG_MMCR   ((uint32_t)0x00000020U)
 
#define ETH_MAC_FLAG_MMC   ((uint32_t)0x00000010U)
 
#define ETH_MAC_FLAG_PMT   ((uint32_t)0x00000008U)
 
#define ETH_DMA_FLAG_TST   ((uint32_t)0x20000000U)
 
#define ETH_DMA_FLAG_PMT   ((uint32_t)0x10000000U)
 
#define ETH_DMA_FLAG_MMC   ((uint32_t)0x08000000U)
 
#define ETH_DMA_FLAG_DATATRANSFERERROR   ((uint32_t)0x00800000U)
 
#define ETH_DMA_FLAG_READWRITEERROR   ((uint32_t)0x01000000U)
 
#define ETH_DMA_FLAG_ACCESSERROR   ((uint32_t)0x02000000U)
 
#define ETH_DMA_FLAG_NIS   ((uint32_t)0x00010000U)
 
#define ETH_DMA_FLAG_AIS   ((uint32_t)0x00008000U)
 
#define ETH_DMA_FLAG_ER   ((uint32_t)0x00004000U)
 
#define ETH_DMA_FLAG_FBE   ((uint32_t)0x00002000U)
 
#define ETH_DMA_FLAG_ET   ((uint32_t)0x00000400U)
 
#define ETH_DMA_FLAG_RWT   ((uint32_t)0x00000200U)
 
#define ETH_DMA_FLAG_RPS   ((uint32_t)0x00000100U)
 
#define ETH_DMA_FLAG_RBU   ((uint32_t)0x00000080U)
 
#define ETH_DMA_FLAG_R   ((uint32_t)0x00000040U)
 
#define ETH_DMA_FLAG_TU   ((uint32_t)0x00000020U)
 
#define ETH_DMA_FLAG_RO   ((uint32_t)0x00000010U)
 
#define ETH_DMA_FLAG_TJT   ((uint32_t)0x00000008U)
 
#define ETH_DMA_FLAG_TBU   ((uint32_t)0x00000004U)
 
#define ETH_DMA_FLAG_TPS   ((uint32_t)0x00000002U)
 
#define ETH_DMA_FLAG_T   ((uint32_t)0x00000001U)
 
#define ETH_MAC_IT_TST   ((uint32_t)0x00000200U)
 
#define ETH_MAC_IT_MMCT   ((uint32_t)0x00000040U)
 
#define ETH_MAC_IT_MMCR   ((uint32_t)0x00000020U)
 
#define ETH_MAC_IT_MMC   ((uint32_t)0x00000010U)
 
#define ETH_MAC_IT_PMT   ((uint32_t)0x00000008U)
 
#define ETH_DMA_IT_TST   ((uint32_t)0x20000000U)
 
#define ETH_DMA_IT_PMT   ((uint32_t)0x10000000U)
 
#define ETH_DMA_IT_MMC   ((uint32_t)0x08000000U)
 
#define ETH_DMA_IT_NIS   ((uint32_t)0x00010000U)
 
#define ETH_DMA_IT_AIS   ((uint32_t)0x00008000U)
 
#define ETH_DMA_IT_ER   ((uint32_t)0x00004000U)
 
#define ETH_DMA_IT_FBE   ((uint32_t)0x00002000U)
 
#define ETH_DMA_IT_ET   ((uint32_t)0x00000400U)
 
#define ETH_DMA_IT_RWT   ((uint32_t)0x00000200U)
 
#define ETH_DMA_IT_RPS   ((uint32_t)0x00000100U)
 
#define ETH_DMA_IT_RBU   ((uint32_t)0x00000080U)
 
#define ETH_DMA_IT_R   ((uint32_t)0x00000040U)
 
#define ETH_DMA_IT_TU   ((uint32_t)0x00000020U)
 
#define ETH_DMA_IT_RO   ((uint32_t)0x00000010U)
 
#define ETH_DMA_IT_TJT   ((uint32_t)0x00000008U)
 
#define ETH_DMA_IT_TBU   ((uint32_t)0x00000004U)
 
#define ETH_DMA_IT_TPS   ((uint32_t)0x00000002U)
 
#define ETH_DMA_IT_T   ((uint32_t)0x00000001U)
 
#define ETH_DMA_TRANSMITPROCESS_STOPPED   ((uint32_t)0x00000000U)
 
#define ETH_DMA_TRANSMITPROCESS_FETCHING   ((uint32_t)0x00100000U)
 
#define ETH_DMA_TRANSMITPROCESS_WAITING   ((uint32_t)0x00200000U)
 
#define ETH_DMA_TRANSMITPROCESS_READING   ((uint32_t)0x00300000U)
 
#define ETH_DMA_TRANSMITPROCESS_SUSPENDED   ((uint32_t)0x00600000U)
 
#define ETH_DMA_TRANSMITPROCESS_CLOSING   ((uint32_t)0x00700000U)
 
#define ETH_DMA_RECEIVEPROCESS_STOPPED   ((uint32_t)0x00000000U)
 
#define ETH_DMA_RECEIVEPROCESS_FETCHING   ((uint32_t)0x00020000U)
 
#define ETH_DMA_RECEIVEPROCESS_WAITING   ((uint32_t)0x00060000U)
 
#define ETH_DMA_RECEIVEPROCESS_SUSPENDED   ((uint32_t)0x00080000U)
 
#define ETH_DMA_RECEIVEPROCESS_CLOSING   ((uint32_t)0x000A0000U)
 
#define ETH_DMA_RECEIVEPROCESS_QUEUING   ((uint32_t)0x000E0000U)
 
#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER   ((uint32_t)0x10000000U)
 
#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER   ((uint32_t)0x00010000U)
 
#define ETH_EXTI_LINE_WAKEUP   ((uint32_t)0x00080000U)
 
#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__)   ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
 Reset ETH handle state. More...
 
#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__)    ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
 Checks whether the specified Ethernet DMA Tx Desc flag is set or not. More...
 
#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__)    ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
 Checks whether the specified Ethernet DMA Rx Desc flag is set or not. More...
 
#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__)    ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
 Enables the specified DMA Rx Desc receive interrupt. More...
 
#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__)    ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
 Disables the specified DMA Rx Desc receive interrupt. More...
 
#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__)    ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
 Set the specified DMA Rx Desc Own bit. More...
 
#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__)    (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
 Returns the specified Ethernet DMA Tx Desc collision count. More...
 
#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__)    ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
 Set the specified DMA Tx Desc Own bit. More...
 
#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__)    ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
 Enables the specified DMA Tx Desc Transmit interrupt. More...
 
#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__)    ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
 Disables the specified DMA Tx Desc Transmit interrupt. More...
 
#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__)    ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
 Selects the specified Ethernet DMA Tx Desc Checksum Insertion. More...
 
#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__)    ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
 Enables the DMA Tx Desc CRC. More...
 
#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__)    ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
 Disables the DMA Tx Desc CRC. More...
 
#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__)    ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
 Enables the DMA Tx Desc padding for frame shorter than 64 bytes. More...
 
#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__)    ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
 Disables the DMA Tx Desc padding for frame shorter than 64 bytes. More...
 
#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
 Enables the specified Ethernet MAC interrupts. More...
 
#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
 Disables the specified Ethernet MAC interrupts. More...
 
#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__)    ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
 Initiate a Pause Control Frame (Full-duplex only). More...
 
#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__)    (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
 Checks whether the Ethernet flow control busy bit is set or not. More...
 
#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
 Enables the MAC Back Pressure operation activation (Half-duplex only). More...
 
#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__)    ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
 Disables the MAC BackPressure operation activation (Half-duplex only). More...
 
#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__)    (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
 Checks whether the specified Ethernet MAC flag is set or not. More...
 
#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
 Enables the specified Ethernet DMA interrupts. More...
 
#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
 Disables the specified Ethernet DMA interrupts. More...
 
#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
 Clears the Ethernet DMA IT pending bit. More...
 
#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__)    (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
 Checks whether the specified Ethernet DMA flag is set or not. More...
 
#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)    ((__HANDLE__)->Instance->DMASR = (__FLAG__))
 Checks whether the specified Ethernet DMA flag is set or not. More...
 
#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__)    (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
 Checks whether the specified Ethernet DMA overflow flag is set or not. More...
 
#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__)    ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
 Set the DMA Receive status watchdog timer register value. More...
 
#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
 Enables any unicast packet filtered by the MAC address recognition to be a wake-up frame. More...
 
#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__)    ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
 Disables any unicast packet filtered by the MAC address recognition to be a wake-up frame. More...
 
#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
 Enables the MAC Wake-Up Frame Detection. More...
 
#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__)    ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
 Disables the MAC Wake-Up Frame Detection. More...
 
#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
 Enables the MAC Magic Packet Detection. More...
 
#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__)    ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
 Disables the MAC Magic Packet Detection. More...
 
#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
 Enables the MAC Power Down. More...
 
#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__)    ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
 Disables the MAC Power Down. More...
 
#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__)    (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
 Checks whether the specified Ethernet PMT flag is set or not. More...
 
#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__)    ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
 Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16) More...
 
#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__)
 Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16) More...
 
#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
 Enables the MMC Counter Freeze. More...
 
#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__)    ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
 Disables the MMC Counter Freeze. More...
 
#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
 Enables the MMC Reset On Read. More...
 
#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__)    ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
 Disables the MMC Reset On Read. More...
 
#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
 Enables the MMC Counter Stop Rollover. More...
 
#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__)    ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
 Disables the MMC Counter Stop Rollover. More...
 
#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__)    ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
 Resets the MMC Counters. More...
 
#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__)    (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
 Enables the specified Ethernet MMC Rx interrupts. More...
 
#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__)    (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)
 Disables the specified Ethernet MMC Rx interrupts. More...
 
#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
 Enables the specified Ethernet MMC Tx interrupts. More...
 
#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
 Disables the specified Ethernet MMC Tx interrupts. More...
 
#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
 Enables the ETH External interrupt line. More...
 
#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT()    EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
 Disables the ETH External interrupt line. More...
 
#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT()   EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
 Enable event on ETH External event line. More...
 
#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT()   EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
 Disable event on ETH External event line. More...
 
#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG()    EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
 Get flag of the ETH External interrupt line. More...
 
#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG()    EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
 Clear flag of the ETH External interrupt line. More...
 
#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER()   EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
 Enables rising edge trigger to the ETH External interrupt line. More...
 
#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER()   EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
 Disables the rising edge trigger to the ETH External interrupt line. More...
 
#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER()   EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
 Enables falling edge trigger to the ETH External interrupt line. More...
 
#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER()   EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
 Disables falling edge trigger to the ETH External interrupt line. More...
 
#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER()
 Enables rising/falling edge trigger to the ETH External interrupt line. More...
 
#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER()
 Disables rising/falling edge trigger to the ETH External interrupt line. More...
 
#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT()    EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
 Generate a Software interrupt on selected EXTI line. More...
 

Enumerations

enum  HAL_ETH_StateTypeDef {
  HAL_ETH_STATE_RESET = 0x00U, HAL_ETH_STATE_READY = 0x01U, HAL_ETH_STATE_BUSY = 0x02U, HAL_ETH_STATE_BUSY_TX = 0x12U,
  HAL_ETH_STATE_BUSY_RX = 0x22U, HAL_ETH_STATE_BUSY_TX_RX = 0x32U, HAL_ETH_STATE_BUSY_WR = 0x42U, HAL_ETH_STATE_BUSY_RD = 0x82U,
  HAL_ETH_STATE_TIMEOUT = 0x03U, HAL_ETH_STATE_ERROR = 0x04U
}
 HAL State structures definition. More...
 

Functions

HAL_StatusTypeDef HAL_ETH_Init (ETH_HandleTypeDef *heth)
 
HAL_StatusTypeDef HAL_ETH_DeInit (ETH_HandleTypeDef *heth)
 
void HAL_ETH_MspInit (ETH_HandleTypeDef *heth)
 Initializes the ETH MSP. More...
 
void HAL_ETH_MspDeInit (ETH_HandleTypeDef *heth)
 
HAL_StatusTypeDef HAL_ETH_DMATxDescListInit (ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
 
HAL_StatusTypeDef HAL_ETH_DMARxDescListInit (ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
 
HAL_StatusTypeDef HAL_ETH_TransmitFrame (ETH_HandleTypeDef *heth, uint32_t FrameLength)
 
HAL_StatusTypeDef HAL_ETH_GetReceivedFrame (ETH_HandleTypeDef *heth)
 
HAL_StatusTypeDef HAL_ETH_ReadPHYRegister (ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
 
HAL_StatusTypeDef HAL_ETH_WritePHYRegister (ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
 
HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT (ETH_HandleTypeDef *heth)
 
void HAL_ETH_IRQHandler (ETH_HandleTypeDef *heth)
 
void HAL_ETH_TxCpltCallback (ETH_HandleTypeDef *heth)
 
void HAL_ETH_RxCpltCallback (ETH_HandleTypeDef *heth)
 Ethernet Rx Transfer completed callback. More...
 
void HAL_ETH_ErrorCallback (ETH_HandleTypeDef *heth)
 
HAL_StatusTypeDef HAL_ETH_Start (ETH_HandleTypeDef *heth)
 
HAL_StatusTypeDef HAL_ETH_Stop (ETH_HandleTypeDef *heth)
 
HAL_StatusTypeDef HAL_ETH_ConfigMAC (ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
 
HAL_StatusTypeDef HAL_ETH_ConfigDMA (ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
 
HAL_ETH_StateTypeDef HAL_ETH_GetState (ETH_HandleTypeDef *heth)
 

Detailed Description

Header file of ETH HAL module.

Author
MCD Application Team
Version
V1.1.0
Date
22-April-2016
Attention

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

  1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
  2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f7xx_hal_eth.h.

Generated by   doxygen 1.8.11