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STM32F769IDiscovery
1.00
uDANTE Audio Networking with STM32F7 DISCO board
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STM32F769IDiscovery
1.00
uDANTE Audio Networking with STM32F7 DISCO board
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Macros | |
| #define | ETH_DMATXDESC_OWN ((uint32_t)0x80000000U) |
| Bit definition of TDES0 register: DMA Tx descriptor status register. More... | |
| #define | ETH_DMATXDESC_IC ((uint32_t)0x40000000U) |
| #define | ETH_DMATXDESC_LS ((uint32_t)0x20000000U) |
| #define | ETH_DMATXDESC_FS ((uint32_t)0x10000000U) |
| #define | ETH_DMATXDESC_DC ((uint32_t)0x08000000U) |
| #define | ETH_DMATXDESC_DP ((uint32_t)0x04000000U) |
| #define | ETH_DMATXDESC_TTSE ((uint32_t)0x02000000U) |
| #define | ETH_DMATXDESC_CIC ((uint32_t)0x00C00000U) |
| #define | ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000U) |
| #define | ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000U) |
| #define | ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000U) |
| #define | ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000U) |
| #define | ETH_DMATXDESC_TER ((uint32_t)0x00200000U) |
| #define | ETH_DMATXDESC_TCH ((uint32_t)0x00100000U) |
| #define | ETH_DMATXDESC_TTSS ((uint32_t)0x00020000U) |
| #define | ETH_DMATXDESC_IHE ((uint32_t)0x00010000U) |
| #define | ETH_DMATXDESC_ES ((uint32_t)0x00008000U) |
| #define | ETH_DMATXDESC_JT ((uint32_t)0x00004000U) |
| #define | ETH_DMATXDESC_FF ((uint32_t)0x00002000U) |
| #define | ETH_DMATXDESC_PCE ((uint32_t)0x00001000U) |
| #define | ETH_DMATXDESC_LCA ((uint32_t)0x00000800U) |
| #define | ETH_DMATXDESC_NC ((uint32_t)0x00000400U) |
| #define | ETH_DMATXDESC_LCO ((uint32_t)0x00000200U) |
| #define | ETH_DMATXDESC_EC ((uint32_t)0x00000100U) |
| #define | ETH_DMATXDESC_VF ((uint32_t)0x00000080U) |
| #define | ETH_DMATXDESC_CC ((uint32_t)0x00000078U) |
| #define | ETH_DMATXDESC_ED ((uint32_t)0x00000004U) |
| #define | ETH_DMATXDESC_UF ((uint32_t)0x00000002U) |
| #define | ETH_DMATXDESC_DB ((uint32_t)0x00000001U) |
| #define | ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000U) |
| Bit definition of TDES1 register. More... | |
| #define | ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFFU) |
| #define | ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFFU) |
| Bit definition of TDES2 register. More... | |
| #define | ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFFU) |
| Bit definition of TDES3 register. More... | |
| #define | ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp Low */ |
| #define | ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp High */ |
| #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp High */ |
Definition at line 805 of file stm32f7xx_hal_eth.h.
| #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp Low */ |
Definition at line 802 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFFU) |
Bit definition of TDES2 register.
Buffer1 Address Pointer
Definition at line 788 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFFU) |
Bit definition of TDES3 register.
Buffer2 Address Pointer
Definition at line 793 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_CC ((uint32_t)0x00000078U) |
Collision Count
Definition at line 774 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000U) |
Checksum Insertion Control: 4 cases
Definition at line 756 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000U) |
Do Nothing: Checksum Engine is bypassed
Definition at line 757 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000U) |
IPV4 header Checksum Insertion
Definition at line 758 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000U) |
TCP/UDP/ICMP Checksum Insertion fully calculated
Definition at line 760 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000U) |
TCP/UDP/ICMP Checksum Insertion calculated over segment only
Definition at line 759 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_DB ((uint32_t)0x00000001U) |
Deferred Bit
Definition at line 777 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_DC ((uint32_t)0x08000000U) |
Disable CRC
Definition at line 753 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_DP ((uint32_t)0x04000000U) |
Disable Padding
Definition at line 754 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_EC ((uint32_t)0x00000100U) |
Excessive Collision: transmission aborted after 16 collisions
Definition at line 772 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_ED ((uint32_t)0x00000004U) |
Excessive Deferral
Definition at line 775 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_ES ((uint32_t)0x00008000U) |
Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT
Definition at line 765 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_FF ((uint32_t)0x00002000U) |
Frame Flushed: DMA/MTL flushed the frame due to SW flush
Definition at line 767 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_FS ((uint32_t)0x10000000U) |
First Segment
Definition at line 752 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_IC ((uint32_t)0x40000000U) |
Interrupt on Completion
Definition at line 750 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_IHE ((uint32_t)0x00010000U) |
IP Header Error
Definition at line 764 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_JT ((uint32_t)0x00004000U) |
Jabber Timeout
Definition at line 766 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_LCA ((uint32_t)0x00000800U) |
Loss of Carrier: carrier lost during transmission
Definition at line 769 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_LCO ((uint32_t)0x00000200U) |
Late Collision: transmission aborted due to collision
Definition at line 771 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_LS ((uint32_t)0x20000000U) |
Last Segment
Definition at line 751 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_NC ((uint32_t)0x00000400U) |
No Carrier: no carrier signal from the transceiver
Definition at line 770 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_OWN ((uint32_t)0x80000000U) |
Bit definition of TDES0 register: DMA Tx descriptor status register.
OWN bit: descriptor is owned by DMA engine
Definition at line 749 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_PCE ((uint32_t)0x00001000U) |
Payload Checksum Error
Definition at line 768 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFFU) |
Transmit Buffer1 Size
Definition at line 783 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000U) |
Bit definition of TDES1 register.
Transmit Buffer2 Size
Definition at line 782 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_TCH ((uint32_t)0x00100000U) |
Second Address Chained
Definition at line 762 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_TER ((uint32_t)0x00200000U) |
Transmit End of Ring
Definition at line 761 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000U) |
Transmit Time Stamp Enable
Definition at line 755 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000U) |
Tx Time Stamp Status
Definition at line 763 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_UF ((uint32_t)0x00000002U) |
Underflow Error: late data arrival from the memory
Definition at line 776 of file stm32f7xx_hal_eth.h.
| #define ETH_DMATXDESC_VF ((uint32_t)0x00000080U) |
VLAN Frame
Definition at line 773 of file stm32f7xx_hal_eth.h.
1.8.11
