STM32F769IDiscovery  1.00
uDANTE Audio Networking with STM32F7 DISCO board
stm32f7xx_hal_cec.c
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1 
79 /* Includes ------------------------------------------------------------------*/
80 #include "stm32f7xx_hal.h"
81 
90 #ifdef HAL_CEC_MODULE_ENABLED
91 
92 /* Private typedef -----------------------------------------------------------*/
93 /* Private define ------------------------------------------------------------*/
101 /* Private macro -------------------------------------------------------------*/
102 /* Private variables ---------------------------------------------------------*/
103 /* Private function prototypes -----------------------------------------------*/
111 /* Exported functions ---------------------------------------------------------*/
112 
148 {
149  /* Check the CEC handle allocation */
150  if((hcec == NULL) ||(hcec->Init.RxBuffer == NULL))
151  {
152  return HAL_ERROR;
153  }
154 
155  /* Check the parameters */
166 
167  if(hcec->gState == HAL_CEC_STATE_RESET)
168  {
169  /* Allocate lock resource and initialize it */
170  hcec->Lock = HAL_UNLOCKED;
171  /* Init the low level hardware : GPIO, CLOCK */
172  HAL_CEC_MspInit(hcec);
173  }
174  hcec->gState = HAL_CEC_STATE_BUSY;
175 
176  /* Disable the Peripheral */
177  __HAL_CEC_DISABLE(hcec);
178 
179  /* Write to CEC Control Register */
180  hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop|\
181  hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen |\
182  hcec->Init.SignalFreeTimeOption |((uint32_t)(hcec->Init.OwnAddress)<<16U) |\
183  hcec->Init.ListenMode;
184 
185  /* Enable the following CEC Transmission/Reception interrupts as
186  * well as the following CEC Transmission/Reception Errors interrupts
187  * Rx Byte Received IT
188  * End of Reception IT
189  * Rx overrun
190  * Rx bit rising error
191  * Rx short bit period error
192  * Rx long bit period error
193  * Rx missing acknowledge
194  * Tx Byte Request IT
195  * End of Transmission IT
196  * Tx Missing Acknowledge IT
197  * Tx-Error IT
198  * Tx-Buffer Underrun IT
199  * Tx arbitration lost */
201 
202  /* Enable the CEC Peripheral */
203  __HAL_CEC_ENABLE(hcec);
204 
206  hcec->gState = HAL_CEC_STATE_READY;
208 
209  return HAL_OK;
210 }
211 
218 {
219  /* Check the CEC handle allocation */
220  if(hcec == NULL)
221  {
222  return HAL_ERROR;
223  }
224 
225  /* Check the parameters */
227 
228  hcec->gState = HAL_CEC_STATE_BUSY;
229 
230  /* DeInit the low level hardware */
231  HAL_CEC_MspDeInit(hcec);
232 
233  /* Disable the Peripheral */
234  __HAL_CEC_DISABLE(hcec);
235 
236  /* Clear Flags */
238 
239  /* Disable the following CEC Transmission/Reception interrupts as
240  * well as the following CEC Transmission/Reception Errors interrupts
241  * Rx Byte Received IT
242  * End of Reception IT
243  * Rx overrun
244  * Rx bit rising error
245  * Rx short bit period error
246  * Rx long bit period error
247  * Rx missing acknowledge
248  * Tx Byte Request IT
249  * End of Transmission IT
250  * Tx Missing Acknowledge IT
251  * Tx-Error IT
252  * Tx-Buffer Underrun IT
253  * Tx arbitration lost */
255 
257  hcec->gState = HAL_CEC_STATE_RESET;
259 
260  /* Process Unlock */
261  __HAL_UNLOCK(hcec);
262 
263  return HAL_OK;
264 }
265 
272 HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
273 {
274  /* Check the parameters */
275  assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress));
276 
277  if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY))
278  {
279  /* Process Locked */
280  __HAL_LOCK(hcec);
281 
282  hcec->gState = HAL_CEC_STATE_BUSY;
283 
284  /* Disable the Peripheral */
285  __HAL_CEC_DISABLE(hcec);
286 
287  if(CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)
288  {
289  hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress<<16);
290  }
291  else
292  {
293  hcec->Instance->CFGR &= ~(CEC_CFGR_OAR);
294  }
295 
296  hcec->gState = HAL_CEC_STATE_READY;
298 
299  /* Process Unlocked */
300  __HAL_UNLOCK(hcec);
301 
302  /* Enable the Peripheral */
303  __HAL_CEC_ENABLE(hcec);
304 
305  return HAL_OK;
306  }
307  else
308  {
309  return HAL_BUSY;
310  }
311 }
312 
318  __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
319 {
320  /* Prevent unused argument(s) compilation warning */
321  UNUSED(hcec);
322  /* NOTE : This function should not be modified, when the callback is needed,
323  the HAL_CEC_MspInit can be implemented in the user file
324  */
325 }
326 
332  __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
333 {
334  /* Prevent unused argument(s) compilation warning */
335  UNUSED(hcec);
336  /* NOTE : This function should not be modified, when the callback is needed,
337  the HAL_CEC_MspDeInit can be implemented in the user file
338  */
339 }
340 
390 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
391 {
392  /* if the IP isn't already busy and if there is no previous transmission
393  already pending due to arbitration lost */
394  if (hcec->gState == HAL_CEC_STATE_READY)
395  {
396  if((pData == NULL ) && (Size > 0))
397  {
398  return HAL_ERROR;
399  }
400 
401  assert_param(IS_CEC_ADDRESS(DestinationAddress));
402  assert_param(IS_CEC_ADDRESS(InitiatorAddress));
404 
405  /* Process Locked */
406  __HAL_LOCK(hcec);
407  hcec->pTxBuffPtr = pData;
410 
411  /* initialize the number of bytes to send,
412  * 0 means only one header is sent (ping operation) */
413  hcec->TxXferCount = Size;
414 
415  /* in case of no payload (Size = 0), sender is only pinging the system;
416  Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
417  if (Size == 0)
418  {
420  }
421  /* send header block */
422  hcec->Instance->TXDR = ((uint8_t)(InitiatorAddress << CEC_INITIATOR_LSB_POS) |(uint8_t) DestinationAddress);
423  /* Set TX Start of Message (TXSOM) bit */
425 
426  /* Process Unlocked */
427  __HAL_UNLOCK(hcec);
428 
429  return HAL_OK;
430 
431  }
432  else
433  {
434  return HAL_BUSY;
435  }
436 }
437 
444 {
445  return hcec->RxXferSize;
446 }
447 
455 void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer)
456 {
457  hcec->Init.RxBuffer = Rxbuffer;
458 }
459 
466 {
467 
468  /* save interrupts register for further error or interrupts handling purposes */
469  uint32_t reg = 0;
470  reg = hcec->Instance->ISR;
471 
472 
473  /* ----------------------------Arbitration Lost Management----------------------------------*/
474  /* CEC TX arbitration error interrupt occurred --------------------------------------*/
475  if((reg & CEC_FLAG_ARBLST) != RESET)
476  {
478  __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);
479  }
480 
481  /* ----------------------------Rx Management----------------------------------*/
482  /* CEC RX byte received interrupt ---------------------------------------------------*/
483  if((reg & CEC_FLAG_RXBR) != RESET)
484  {
485  /* reception is starting */
487  hcec->RxXferSize++;
488  /* read received byte */
489  *hcec->Init.RxBuffer++ = hcec->Instance->RXDR;
490  __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR);
491  }
492 
493  /* CEC RX end received interrupt ---------------------------------------------------*/
494  if((reg & CEC_FLAG_RXEND) != RESET)
495  {
496  /* clear IT */
497  __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);
498 
499  /* Rx process is completed, restore hcec->RxState to Ready */
500  hcec->RxState = HAL_CEC_STATE_READY;
502  hcec->Init.RxBuffer-=hcec->RxXferSize;
503  HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize);
504  hcec->RxXferSize = 0;
505  }
506 
507  /* ----------------------------Tx Management----------------------------------*/
508  /* CEC TX byte request interrupt ------------------------------------------------*/
509  if((reg & CEC_FLAG_TXBR) != RESET)
510  {
511  if (hcec->TxXferCount == 0)
512  {
513  /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
515  hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
516  }
517  else
518  {
519  hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
520  hcec->TxXferCount--;
521  }
522  /* clear Tx-Byte request flag */
523  __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR);
524  }
525 
526  /* CEC TX end interrupt ------------------------------------------------*/
527  if((reg & CEC_FLAG_TXEND) != RESET)
528  {
529  __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND);
530 
531  /* Tx process is ended, restore hcec->gState to Ready */
532  hcec->gState = HAL_CEC_STATE_READY;
533  /* Call the Process Unlocked before calling the Tx call back API to give the possibility to
534  start again the Transmission under the Tx call back API */
535  __HAL_UNLOCK(hcec);
538  }
539 
540  /* ----------------------------Rx/Tx Error Management----------------------------------*/
542  {
543  hcec->ErrorCode = reg;
545 
546 
548  {
549  hcec->Init.RxBuffer-=hcec->RxXferSize;
550  hcec->RxXferSize = 0;
552  }
553  else if (((reg & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != RESET) && ((reg & CEC_ISR_ARBLST) == RESET))
554  {
555  /* Set the CEC state ready to be able to start again the process */
556  hcec->gState = HAL_CEC_STATE_READY;
557  }
558 
559  /* Error Call Back */
560  HAL_CEC_ErrorCallback(hcec);
561  }
562 
563 }
564 
570  __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
571 {
572  /* Prevent unused argument(s) compilation warning */
573  UNUSED(hcec);
574  /* NOTE : This function should not be modified, when the callback is needed,
575  the HAL_CEC_TxCpltCallback can be implemented in the user file
576  */
577 }
578 
585 __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
586 {
587  /* Prevent unused argument(s) compilation warning */
588  UNUSED(hcec);
589  UNUSED(RxFrameSize);
590  /* NOTE : This function should not be modified, when the callback is needed,
591  the HAL_CEC_RxCpltCallback can be implemented in the user file
592  */
593 }
594 
600  __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
601 {
602  /* Prevent unused argument(s) compilation warning */
603  UNUSED(hcec);
604  /* NOTE : This function should not be modified, when the callback is needed,
605  the HAL_CEC_ErrorCallback can be implemented in the user file
606  */
607 }
633 {
634  uint32_t temp1= 0x00U, temp2 = 0x00U;
635  temp1 = hcec->gState;
636  temp2 = hcec->RxState;
637 
638  return (HAL_CEC_StateTypeDef)(temp1 | temp2);
639 }
640 
647 uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
648 {
649  return hcec->ErrorCode;
650 }
651 
659 #endif /* HAL_CEC_MODULE_ENABLED */
660 
668 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
#define IS_CEC_LISTENING_MODE(__MODE__)
#define CEC_FLAG_TXEND
#define HAL_CEC_ERROR_BRE
#define CEC_ISR_TXERR
Definition: stm32f745xx.h:3039
#define __HAL_CEC_ENABLE(__HANDLE__)
Enables the CEC device.
#define CEC_IT_TXBR
#define CEC_IT_TXEND
#define IS_CEC_SFTOP(__SFTOP__)
#define assert_param(expr)
Include module&#39;s header file.
void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
#define IS_CEC_ALL_INSTANCE(__INSTANCE__)
Definition: stm32f745xx.h:8846
HAL_CEC_StateTypeDef
HAL CEC State structures definition.
HAL_LockTypeDef Lock
#define __HAL_CEC_DISABLE(__HANDLE__)
Disables the CEC device.
#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__)
#define HAL_CEC_ERROR_TXUDR
void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
#define CEC_ISR_RXOVR
Definition: stm32f745xx.h:3030
#define __HAL_UNLOCK(__HANDLE__)
#define HAL_CEC_ERROR_RXOVR
#define CEC_ISR_TXUDR
Definition: stm32f745xx.h:3038
CEC handle Structure definition.
#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__)
Set Transmission End flag.
#define CEC_ISR_ARBLST
Definition: stm32f745xx.h:3035
CEC_InitTypeDef Init
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
HAL_CEC_StateTypeDef RxState
void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer)
#define CEC_FLAG_RXEND
#define CEC_IT_RXBR
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
#define IS_CEC_BRERXSTOP(__BRERXSTOP__)
#define __HAL_LOCK(__HANDLE__)
#define CEC_IER_TX_ALL_ERR
#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disables the specified CEC interrupt.
#define CEC_FLAG_SBPE
#define NULL
Definition: usbd_def.h:53
#define CEC_FLAG_ARBLST
#define HAL_CEC_ERROR_TXERR
#define IS_CEC_ADDRESS(__ADDRESS__)
Check CEC initiator or destination logical address setting. Initiator and destination addresses are c...
#define IS_CEC_TOLERANCE(__RXTOL__)
uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)
#define CEC_IT_RXEND
__IO uint32_t RXDR
Definition: stm32f745xx.h:310
This file contains all the functions prototypes for the HAL module driver.
uint32_t LBPEErrorBitGen
#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__)
Set Transmission Start flag.
#define CEC_FLAG_TXBR
uint32_t BroadcastMsgNoErrorBitGen
void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
#define CEC_CFGR_OAR
Definition: stm32f745xx.h:3018
#define IS_CEC_MSGSIZE(__SIZE__)
Check CEC message size. The message size is the payload size: without counting the header...
#define CEC_ISR_ALL_ERROR
#define CEC_ISR_LBPE
Definition: stm32f745xx.h:3033
#define IS_CEC_OWN_ADDRESS(__ADDRESS__)
Check CEC device Own Address Register (OAR) setting. OAR address is written in a 15-bit field within ...
uint32_t SignalFreeTimeOption
#define UNUSED(x)
__IO uint32_t ISR
Definition: stm32f745xx.h:311
#define HAL_CEC_ERROR_NONE
#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enables the specified CEC interrupt.
#define CEC_FLAG_RXBR
__IO uint32_t TXDR
Definition: stm32f745xx.h:309
#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clears the interrupt or status flag when raised (write at 1)
#define CEC_INITIATOR_LSB_POS
HAL_CEC_StateTypeDef gState
#define CEC_ISR_RXACKE
Definition: stm32f745xx.h:3034
#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__)
#define IS_CEC_SIGNALFREETIME(__SFT__)
#define CEC_ISR_TXACKE
Definition: stm32f745xx.h:3040
#define CEC_IER_RX_ALL_ERR
#define HAL_CEC_ERROR_RXACKE
CEC_TypeDef * Instance
HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
#define HAL_CEC_ERROR_ARBLST
#define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__)
void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
#define HAL_CEC_ERROR_TXACKE
__IO uint32_t CFGR
Definition: stm32f745xx.h:308
HAL_StatusTypeDef
HAL Status structures definition.
#define CEC_OWN_ADDRESS_NONE
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
#define CEC_ISR_SBPE
Definition: stm32f745xx.h:3032
#define CEC_ISR_BRE
Definition: stm32f745xx.h:3031
#define CEC_FLAG_LBPE