STM32F769IDiscovery  1.00
uDANTE Audio Networking with STM32F7 DISCO board
core_sc000.h
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1 /**************************************************************************/
7 /* Copyright (c) 2009 - 2015 ARM LIMITED
8 
9  All rights reserved.
10  Redistribution and use in source and binary forms, with or without
11  modification, are permitted provided that the following conditions are met:
12  - Redistributions of source code must retain the above copyright
13  notice, this list of conditions and the following disclaimer.
14  - Redistributions in binary form must reproduce the above copyright
15  notice, this list of conditions and the following disclaimer in the
16  documentation and/or other materials provided with the distribution.
17  - Neither the name of ARM nor the names of its contributors may be used
18  to endorse or promote products derived from this software without
19  specific prior written permission.
20  *
21  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
25  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  POSSIBILITY OF SUCH DAMAGE.
32  ---------------------------------------------------------------------------*/
33 
34 
35 #if defined ( __ICCARM__ )
36  #pragma system_include /* treat file as system include file for MISRA check */
37 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
38  #pragma clang system_header /* treat file as system include file */
39 #endif
40 
41 #ifndef __CORE_SC000_H_GENERIC
42 #define __CORE_SC000_H_GENERIC
43 
44 #include <stdint.h>
45 
46 #ifdef __cplusplus
47  extern "C" {
48 #endif
49 
65 /*******************************************************************************
66  * CMSIS definitions
67  ******************************************************************************/
73 /* CMSIS SC000 definitions */
74 #define __SC000_CMSIS_VERSION_MAIN (0x04U)
75 #define __SC000_CMSIS_VERSION_SUB (0x1EU)
76 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
77  __SC000_CMSIS_VERSION_SUB )
79 #define __CORTEX_SC (000U)
82 #if defined ( __CC_ARM )
83  #define __ASM __asm
84  #define __INLINE __inline
85  #define __STATIC_INLINE static __inline
86 
87 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
88  #define __ASM __asm
89  #define __INLINE __inline
90  #define __STATIC_INLINE static __inline
91 
92 #elif defined ( __GNUC__ )
93  #define __ASM __asm
94  #define __INLINE inline
95  #define __STATIC_INLINE static inline
96 
97 #elif defined ( __ICCARM__ )
98  #define __ASM __asm
99  #define __INLINE inline
100  #define __STATIC_INLINE static inline
101 
102 #elif defined ( __TMS470__ )
103  #define __ASM __asm
104  #define __STATIC_INLINE static inline
105 
106 #elif defined ( __TASKING__ )
107  #define __ASM __asm
108  #define __INLINE inline
109  #define __STATIC_INLINE static inline
110 
111 #elif defined ( __CSMC__ )
112  #define __packed
113  #define __ASM _asm
114  #define __INLINE inline
115  #define __STATIC_INLINE static inline
116 
117 #else
118  #error Unknown compiler
119 #endif
120 
124 #define __FPU_USED 0U
125 
126 #if defined ( __CC_ARM )
127  #if defined __TARGET_FPU_VFP
128  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
129  #endif
130 
131 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
132  #if defined __ARM_PCS_VFP
133  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
134  #endif
135 
136 #elif defined ( __GNUC__ )
137  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
138  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
139  #endif
140 
141 #elif defined ( __ICCARM__ )
142  #if defined __ARMVFP__
143  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
144  #endif
145 
146 #elif defined ( __TMS470__ )
147  #if defined __TI_VFP_SUPPORT__
148  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
149  #endif
150 
151 #elif defined ( __TASKING__ )
152  #if defined __FPU_VFP__
153  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
154  #endif
155 
156 #elif defined ( __CSMC__ )
157  #if ( __CSMC__ & 0x400U)
158  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
159  #endif
160 
161 #endif
162 
163 #include "core_cmInstr.h" /* Core Instruction Access */
164 #include "core_cmFunc.h" /* Core Function Access */
165 
166 #ifdef __cplusplus
167 }
168 #endif
169 
170 #endif /* __CORE_SC000_H_GENERIC */
171 
172 #ifndef __CMSIS_GENERIC
173 
174 #ifndef __CORE_SC000_H_DEPENDANT
175 #define __CORE_SC000_H_DEPENDANT
176 
177 #ifdef __cplusplus
178  extern "C" {
179 #endif
180 
181 /* check device defines and use defaults */
182 #if defined __CHECK_DEVICE_DEFINES
183  #ifndef __SC000_REV
184  #define __SC000_REV 0x0000U
185  #warning "__SC000_REV not defined in device header file; using default!"
186  #endif
187 
188  #ifndef __MPU_PRESENT
189  #define __MPU_PRESENT 0U
190  #warning "__MPU_PRESENT not defined in device header file; using default!"
191  #endif
192 
193  #ifndef __NVIC_PRIO_BITS
194  #define __NVIC_PRIO_BITS 2U
195  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
196  #endif
197 
198  #ifndef __Vendor_SysTickConfig
199  #define __Vendor_SysTickConfig 0U
200  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
201  #endif
202 #endif
203 
204 /* IO definitions (access restrictions to peripheral registers) */
212 #ifdef __cplusplus
213  #define __I volatile
214 #else
215  #define __I volatile const
216 #endif
217 #define __O volatile
218 #define __IO volatile
220 /* following defines should be used for structure members */
221 #define __IM volatile const
222 #define __OM volatile
223 #define __IOM volatile
225 
229 /*******************************************************************************
230  * Register Abstraction
231  Core Register contain:
232  - Core Register
233  - Core NVIC Register
234  - Core SCB Register
235  - Core SysTick Register
236  - Core MPU Register
237  ******************************************************************************/
238 
253 typedef union
254 {
255  struct
256  {
257  uint32_t _reserved0:28;
258  uint32_t V:1;
259  uint32_t C:1;
260  uint32_t Z:1;
261  uint32_t N:1;
262  } b;
263  uint32_t w;
264 } APSR_Type;
265 
266 /* APSR Register Definitions */
267 #define APSR_N_Pos 31U
268 #define APSR_N_Msk (1UL << APSR_N_Pos)
270 #define APSR_Z_Pos 30U
271 #define APSR_Z_Msk (1UL << APSR_Z_Pos)
273 #define APSR_C_Pos 29U
274 #define APSR_C_Msk (1UL << APSR_C_Pos)
276 #define APSR_V_Pos 28U
277 #define APSR_V_Msk (1UL << APSR_V_Pos)
283 typedef union
284 {
285  struct
286  {
287  uint32_t ISR:9;
288  uint32_t _reserved0:23;
289  } b;
290  uint32_t w;
291 } IPSR_Type;
292 
293 /* IPSR Register Definitions */
294 #define IPSR_ISR_Pos 0U
295 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
301 typedef union
302 {
303  struct
304  {
305  uint32_t ISR:9;
306  uint32_t _reserved0:15;
307  uint32_t T:1;
308  uint32_t _reserved1:3;
309  uint32_t V:1;
310  uint32_t C:1;
311  uint32_t Z:1;
312  uint32_t N:1;
313  } b;
314  uint32_t w;
315 } xPSR_Type;
316 
317 /* xPSR Register Definitions */
318 #define xPSR_N_Pos 31U
319 #define xPSR_N_Msk (1UL << xPSR_N_Pos)
321 #define xPSR_Z_Pos 30U
322 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
324 #define xPSR_C_Pos 29U
325 #define xPSR_C_Msk (1UL << xPSR_C_Pos)
327 #define xPSR_V_Pos 28U
328 #define xPSR_V_Msk (1UL << xPSR_V_Pos)
330 #define xPSR_T_Pos 24U
331 #define xPSR_T_Msk (1UL << xPSR_T_Pos)
333 #define xPSR_ISR_Pos 0U
334 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
340 typedef union
341 {
342  struct
343  {
344  uint32_t _reserved0:1;
345  uint32_t SPSEL:1;
346  uint32_t _reserved1:30;
347  } b;
348  uint32_t w;
349 } CONTROL_Type;
350 
351 /* CONTROL Register Definitions */
352 #define CONTROL_SPSEL_Pos 1U
353 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
355 
368 typedef struct
369 {
370  __IOM uint32_t ISER[1U];
371  uint32_t RESERVED0[31U];
372  __IOM uint32_t ICER[1U];
373  uint32_t RSERVED1[31U];
374  __IOM uint32_t ISPR[1U];
375  uint32_t RESERVED2[31U];
376  __IOM uint32_t ICPR[1U];
377  uint32_t RESERVED3[31U];
378  uint32_t RESERVED4[64U];
379  __IOM uint32_t IP[8U];
380 } NVIC_Type;
381 
395 typedef struct
396 {
397  __IM uint32_t CPUID;
398  __IOM uint32_t ICSR;
399  __IOM uint32_t VTOR;
400  __IOM uint32_t AIRCR;
401  __IOM uint32_t SCR;
402  __IOM uint32_t CCR;
403  uint32_t RESERVED0[1U];
404  __IOM uint32_t SHP[2U];
405  __IOM uint32_t SHCSR;
406  uint32_t RESERVED1[154U];
407  __IOM uint32_t SFCR;
408 } SCB_Type;
409 
410 /* SCB CPUID Register Definitions */
411 #define SCB_CPUID_IMPLEMENTER_Pos 24U
412 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
414 #define SCB_CPUID_VARIANT_Pos 20U
415 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
417 #define SCB_CPUID_ARCHITECTURE_Pos 16U
418 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
420 #define SCB_CPUID_PARTNO_Pos 4U
421 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
423 #define SCB_CPUID_REVISION_Pos 0U
424 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
426 /* SCB Interrupt Control State Register Definitions */
427 #define SCB_ICSR_NMIPENDSET_Pos 31U
428 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
430 #define SCB_ICSR_PENDSVSET_Pos 28U
431 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
433 #define SCB_ICSR_PENDSVCLR_Pos 27U
434 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
436 #define SCB_ICSR_PENDSTSET_Pos 26U
437 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
439 #define SCB_ICSR_PENDSTCLR_Pos 25U
440 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
442 #define SCB_ICSR_ISRPREEMPT_Pos 23U
443 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
445 #define SCB_ICSR_ISRPENDING_Pos 22U
446 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
448 #define SCB_ICSR_VECTPENDING_Pos 12U
449 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
451 #define SCB_ICSR_VECTACTIVE_Pos 0U
452 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
454 /* SCB Interrupt Control State Register Definitions */
455 #define SCB_VTOR_TBLOFF_Pos 7U
456 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
458 /* SCB Application Interrupt and Reset Control Register Definitions */
459 #define SCB_AIRCR_VECTKEY_Pos 16U
460 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
462 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U
463 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
465 #define SCB_AIRCR_ENDIANESS_Pos 15U
466 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
468 #define SCB_AIRCR_SYSRESETREQ_Pos 2U
469 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
471 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
472 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
474 /* SCB System Control Register Definitions */
475 #define SCB_SCR_SEVONPEND_Pos 4U
476 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
478 #define SCB_SCR_SLEEPDEEP_Pos 2U
479 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
481 #define SCB_SCR_SLEEPONEXIT_Pos 1U
482 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
484 /* SCB Configuration Control Register Definitions */
485 #define SCB_CCR_STKALIGN_Pos 9U
486 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
488 #define SCB_CCR_UNALIGN_TRP_Pos 3U
489 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
491 /* SCB System Handler Control and State Register Definitions */
492 #define SCB_SHCSR_SVCALLPENDED_Pos 15U
493 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
495 
508 typedef struct
509 {
510  uint32_t RESERVED0[2U];
511  __IOM uint32_t ACTLR;
512 } SCnSCB_Type;
513 
514 /* Auxiliary Control Register Definitions */
515 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U
516 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)
518 
531 typedef struct
532 {
533  __IOM uint32_t CTRL;
534  __IOM uint32_t LOAD;
535  __IOM uint32_t VAL;
536  __IM uint32_t CALIB;
537 } SysTick_Type;
538 
539 /* SysTick Control / Status Register Definitions */
540 #define SysTick_CTRL_COUNTFLAG_Pos 16U
541 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
543 #define SysTick_CTRL_CLKSOURCE_Pos 2U
544 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
546 #define SysTick_CTRL_TICKINT_Pos 1U
547 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
549 #define SysTick_CTRL_ENABLE_Pos 0U
550 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
552 /* SysTick Reload Register Definitions */
553 #define SysTick_LOAD_RELOAD_Pos 0U
554 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
556 /* SysTick Current Register Definitions */
557 #define SysTick_VAL_CURRENT_Pos 0U
558 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
560 /* SysTick Calibration Register Definitions */
561 #define SysTick_CALIB_NOREF_Pos 31U
562 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
564 #define SysTick_CALIB_SKEW_Pos 30U
565 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
567 #define SysTick_CALIB_TENMS_Pos 0U
568 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
570 
572 #if (__MPU_PRESENT == 1U)
573 
583 typedef struct
584 {
585  __IM uint32_t TYPE;
586  __IOM uint32_t CTRL;
587  __IOM uint32_t RNR;
588  __IOM uint32_t RBAR;
589  __IOM uint32_t RASR;
590 } MPU_Type;
591 
592 /* MPU Type Register Definitions */
593 #define MPU_TYPE_IREGION_Pos 16U
594 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
596 #define MPU_TYPE_DREGION_Pos 8U
597 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
599 #define MPU_TYPE_SEPARATE_Pos 0U
600 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
602 /* MPU Control Register Definitions */
603 #define MPU_CTRL_PRIVDEFENA_Pos 2U
604 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
606 #define MPU_CTRL_HFNMIENA_Pos 1U
607 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
609 #define MPU_CTRL_ENABLE_Pos 0U
610 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
612 /* MPU Region Number Register Definitions */
613 #define MPU_RNR_REGION_Pos 0U
614 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
616 /* MPU Region Base Address Register Definitions */
617 #define MPU_RBAR_ADDR_Pos 8U
618 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)
620 #define MPU_RBAR_VALID_Pos 4U
621 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
623 #define MPU_RBAR_REGION_Pos 0U
624 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
626 /* MPU Region Attribute and Size Register Definitions */
627 #define MPU_RASR_ATTRS_Pos 16U
628 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
630 #define MPU_RASR_XN_Pos 28U
631 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
633 #define MPU_RASR_AP_Pos 24U
634 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
636 #define MPU_RASR_TEX_Pos 19U
637 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
639 #define MPU_RASR_S_Pos 18U
640 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
642 #define MPU_RASR_C_Pos 17U
643 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
645 #define MPU_RASR_B_Pos 16U
646 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
648 #define MPU_RASR_SRD_Pos 8U
649 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
651 #define MPU_RASR_SIZE_Pos 1U
652 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
654 #define MPU_RASR_ENABLE_Pos 0U
655 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/)
657 
658 #endif
659 
660 
668 
684 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
685 
692 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
693 
704 /* Memory mapping of SC000 Hardware */
705 #define SCS_BASE (0xE000E000UL)
706 #define SysTick_BASE (SCS_BASE + 0x0010UL)
707 #define NVIC_BASE (SCS_BASE + 0x0100UL)
708 #define SCB_BASE (SCS_BASE + 0x0D00UL)
710 #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
711 #define SCB ((SCB_Type *) SCB_BASE )
712 #define SysTick ((SysTick_Type *) SysTick_BASE )
713 #define NVIC ((NVIC_Type *) NVIC_BASE )
715 #if (__MPU_PRESENT == 1U)
716  #define MPU_BASE (SCS_BASE + 0x0D90UL)
717  #define MPU ((MPU_Type *) MPU_BASE )
718 #endif
719 
724 /*******************************************************************************
725  * Hardware Abstraction Layer
726  Core Function Interface contains:
727  - Core NVIC Functions
728  - Core SysTick Functions
729  - Core Register Access Functions
730  ******************************************************************************/
737 /* ########################## NVIC functions #################################### */
745 /* Interrupt Priorities are WORD accessible only under ARMv6M */
746 /* The following MACROS handle generation of the register offset and byte masks */
747 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
748 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
749 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
750 
751 
757 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
758 {
759  NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
760 }
761 
762 
768 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
769 {
770  NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
771 }
772 
773 
781 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
782 {
783  return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
784 }
785 
786 
792 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
793 {
794  NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
795 }
796 
797 
803 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
804 {
805  NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
806 }
807 
808 
816 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
817 {
818  if ((int32_t)(IRQn) < 0)
819  {
820  SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
821  (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
822  }
823  else
824  {
825  NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
826  (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
827  }
828 }
829 
830 
840 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
841 {
842 
843  if ((int32_t)(IRQn) < 0)
844  {
845  return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
846  }
847  else
848  {
849  return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
850  }
851 }
852 
853 
858 __STATIC_INLINE void NVIC_SystemReset(void)
859 {
860  __DSB(); /* Ensure all outstanding memory accesses included
861  buffered write are completed before reset */
862  SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
863  SCB_AIRCR_SYSRESETREQ_Msk);
864  __DSB(); /* Ensure completion of memory access */
865 
866  for(;;) /* wait until reset */
867  {
868  __NOP();
869  }
870 }
871 
876 /* ################################## SysTick function ############################################ */
884 #if (__Vendor_SysTickConfig == 0U)
885 
897 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
898 {
899  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
900  {
901  return (1UL); /* Reload value impossible */
902  }
903 
904  SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
905  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
906  SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
907  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
908  SysTick_CTRL_TICKINT_Msk |
909  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
910  return (0UL); /* Function successful */
911 }
912 
913 #endif
914 
920 #ifdef __cplusplus
921 }
922 #endif
923 
924 #endif /* __CORE_SC000_H_DEPENDANT */
925 
926 #endif /* __CMSIS_GENERIC */
core_cmFunc.h
CMSIS Cortex-M Core Function Access Header File.
__NOP
#define __NOP
No Operation.
Definition: cmsis_armcc.h:313
NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_cm0.h:653
NVIC_SetPendingIRQ
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_cm0.h:664
_IP_IDX
#define _IP_IDX(IRQn)
Definition: core_sc000.h:749
SCB_Type::SFCR
__IOM uint32_t SFCR
Definition: core_sc000.h:407
SysTick
#define SysTick
Definition: core_sc000.h:712
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_cm0.h:277
__DSB
#define __DSB()
Data Synchronization Barrier.
Definition: cmsis_armcc.h:355
NVIC
#define NVIC
Definition: core_sc000.h:713
__IOM
#define __IOM
Definition: core_sc000.h:223
NVIC_EnableIRQ
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable External Interrupt.
Definition: core_cm0.h:629
SysTick_IRQn
Definition: stm32f745xx.h:77
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: core_cm0.h:389
SCB
#define SCB
Definition: core_sc000.h:711
IRQn_Type
IRQn_Type
STM32F7xx Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f745xx.h:67
SysTick_Config
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
System Tick Configuration.
Definition: core_cm0.h:769
NVIC_GetPriority
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_cm0.h:712
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: stm32f745xx.h:185
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition: core_cm3.h:644
NVIC_SetPriority
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_cm0.h:688
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_cm0.h:362
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: core_cm0.h:496
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_sc000.h:459
NVIC_SystemReset
__STATIC_INLINE void NVIC_SystemReset(void)
System Reset.
Definition: core_cm0.h:730
__IM
#define __IM
Definition: core_sc000.h:221
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_sc000.h:469
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: core_cm0.h:247
NVIC_DisableIRQ
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Disable External Interrupt.
Definition: core_cm0.h:640
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_sc000.h:554
_BIT_SHIFT
#define _BIT_SHIFT(IRQn)
Definition: core_sc000.h:747
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: core_cm0.h:334
_SHP_IDX
#define _SHP_IDX(IRQn)
Definition: core_sc000.h:748
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_sc000.h:544
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_sc000.h:550
NVIC_ClearPendingIRQ
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_cm0.h:675
core_cmInstr.h
CMSIS Cortex-M Core Instruction Access Header File.
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_cm0.h:295
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_sc000.h:547
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