STM32F769IDiscovery  1.00
uDANTE Audio Networking with STM32F7 DISCO board
stm32f7xx_hal_dsi.h
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1 
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F7xx_HAL_DSI_H
40 #define __STM32F7xx_HAL_DSI_H
41 
42 #ifdef __cplusplus
43  extern "C" {
44 #endif
45 
46 #if defined (STM32F769xx) || defined (STM32F779xx)
47 /* Includes ------------------------------------------------------------------*/
48 #include "stm32f7xx_hal_def.h"
49 
59 /* Exported types ------------------------------------------------------------*/
63 typedef struct
64 {
65  uint32_t AutomaticClockLaneControl;
68  uint32_t TXEscapeCkdiv;
71  uint32_t NumberOfLanes;
74 }DSI_InitTypeDef;
75 
79 typedef struct
80 {
81  uint32_t PLLNDIV;
84  uint32_t PLLIDF;
87  uint32_t PLLODF;
90 }DSI_PLLInitTypeDef;
91 
95 typedef struct
96 {
97  uint32_t VirtualChannelID;
99  uint32_t ColorCoding;
102  uint32_t LooselyPacked;
106  uint32_t Mode;
109  uint32_t PacketSize;
111  uint32_t NumberOfChunks;
113  uint32_t NullPacketSize;
115  uint32_t HSPolarity;
118  uint32_t VSPolarity;
121  uint32_t DEPolarity;
124  uint32_t HorizontalSyncActive;
126  uint32_t HorizontalBackPorch;
128  uint32_t HorizontalLine;
130  uint32_t VerticalSyncActive;
132  uint32_t VerticalBackPorch;
134  uint32_t VerticalFrontPorch;
136  uint32_t VerticalActive;
138  uint32_t LPCommandEnable;
141  uint32_t LPLargestPacketSize;
144  uint32_t LPVACTLargestPacketSize;
147  uint32_t LPHorizontalFrontPorchEnable;
150  uint32_t LPHorizontalBackPorchEnable;
153  uint32_t LPVerticalActiveEnable;
156  uint32_t LPVerticalFrontPorchEnable;
159  uint32_t LPVerticalBackPorchEnable;
162  uint32_t LPVerticalSyncActiveEnable;
165  uint32_t FrameBTAAcknowledgeEnable;
168 }DSI_VidCfgTypeDef;
169 
173 typedef struct
174 {
175  uint32_t VirtualChannelID;
177  uint32_t ColorCoding;
180  uint32_t CommandSize;
183  uint32_t TearingEffectSource;
186  uint32_t TearingEffectPolarity;
189  uint32_t HSPolarity;
192  uint32_t VSPolarity;
195  uint32_t DEPolarity;
198  uint32_t VSyncPol;
201  uint32_t AutomaticRefresh;
204  uint32_t TEAcknowledgeRequest;
207 }DSI_CmdCfgTypeDef;
208 
212 typedef struct
213 {
214  uint32_t LPGenShortWriteNoP;
217  uint32_t LPGenShortWriteOneP;
220  uint32_t LPGenShortWriteTwoP;
223  uint32_t LPGenShortReadNoP;
226  uint32_t LPGenShortReadOneP;
229  uint32_t LPGenShortReadTwoP;
232  uint32_t LPGenLongWrite;
235  uint32_t LPDcsShortWriteNoP;
238  uint32_t LPDcsShortWriteOneP;
241  uint32_t LPDcsShortReadNoP;
244  uint32_t LPDcsLongWrite;
247  uint32_t LPMaxReadPacket;
250  uint32_t AcknowledgeRequest;
253 }DSI_LPCmdTypeDef;
254 
258 typedef struct
259 {
260  uint32_t ClockLaneHS2LPTime;
263  uint32_t ClockLaneLP2HSTime;
266  uint32_t DataLaneHS2LPTime;
269  uint32_t DataLaneLP2HSTime;
272  uint32_t DataLaneMaxReadTime;
274  uint32_t StopWaitTime;
277 }DSI_PHY_TimerTypeDef;
278 
282 typedef struct
283 {
284  uint32_t TimeoutCkdiv;
286  uint32_t HighSpeedTransmissionTimeout;
288  uint32_t LowPowerReceptionTimeout;
290  uint32_t HighSpeedReadTimeout;
292  uint32_t LowPowerReadTimeout;
294  uint32_t HighSpeedWriteTimeout;
296  uint32_t HighSpeedWritePrespMode;
299  uint32_t LowPowerWriteTimeout;
301  uint32_t BTATimeout;
303 }DSI_HOST_TimeoutTypeDef;
304 
308 typedef enum
309 {
310  HAL_DSI_STATE_RESET = 0x00U,
311  HAL_DSI_STATE_READY = 0x01U,
312  HAL_DSI_STATE_ERROR = 0x02U,
313  HAL_DSI_STATE_BUSY = 0x03U,
314  HAL_DSI_STATE_TIMEOUT = 0x04U
315 }HAL_DSI_StateTypeDef;
316 
320 typedef struct
321 {
322  DSI_TypeDef *Instance;
323  DSI_InitTypeDef Init;
324  HAL_LockTypeDef Lock;
325  __IO HAL_DSI_StateTypeDef State;
326  __IO uint32_t ErrorCode;
327  uint32_t ErrorMsk;
328 }DSI_HandleTypeDef;
329 
330 /* Exported constants --------------------------------------------------------*/
334 #define DSI_ENTER_IDLE_MODE 0x39U
335 #define DSI_ENTER_INVERT_MODE 0x21U
336 #define DSI_ENTER_NORMAL_MODE 0x13U
337 #define DSI_ENTER_PARTIAL_MODE 0x12U
338 #define DSI_ENTER_SLEEP_MODE 0x10U
339 #define DSI_EXIT_IDLE_MODE 0x38U
340 #define DSI_EXIT_INVERT_MODE 0x20U
341 #define DSI_EXIT_SLEEP_MODE 0x11U
342 #define DSI_GET_3D_CONTROL 0x3FU
343 #define DSI_GET_ADDRESS_MODE 0x0BU
344 #define DSI_GET_BLUE_CHANNEL 0x08U
345 #define DSI_GET_DIAGNOSTIC_RESULT 0x0FU
346 #define DSI_GET_DISPLAY_MODE 0x0DU
347 #define DSI_GET_GREEN_CHANNEL 0x07U
348 #define DSI_GET_PIXEL_FORMAT 0x0CU
349 #define DSI_GET_POWER_MODE 0x0AU
350 #define DSI_GET_RED_CHANNEL 0x06U
351 #define DSI_GET_SCANLINE 0x45U
352 #define DSI_GET_SIGNAL_MODE 0x0EU
353 #define DSI_NOP 0x00U
354 #define DSI_READ_DDB_CONTINUE 0xA8U
355 #define DSI_READ_DDB_START 0xA1U
356 #define DSI_READ_MEMORY_CONTINUE 0x3EU
357 #define DSI_READ_MEMORY_START 0x2EU
358 #define DSI_SET_3D_CONTROL 0x3DU
359 #define DSI_SET_ADDRESS_MODE 0x36U
360 #define DSI_SET_COLUMN_ADDRESS 0x2AU
361 #define DSI_SET_DISPLAY_OFF 0x28U
362 #define DSI_SET_DISPLAY_ON 0x29U
363 #define DSI_SET_GAMMA_CURVE 0x26U
364 #define DSI_SET_PAGE_ADDRESS 0x2BU
365 #define DSI_SET_PARTIAL_COLUMNS 0x31U
366 #define DSI_SET_PARTIAL_ROWS 0x30U
367 #define DSI_SET_PIXEL_FORMAT 0x3AU
368 #define DSI_SET_SCROLL_AREA 0x33U
369 #define DSI_SET_SCROLL_START 0x37U
370 #define DSI_SET_TEAR_OFF 0x34U
371 #define DSI_SET_TEAR_ON 0x35U
372 #define DSI_SET_TEAR_SCANLINE 0x44U
373 #define DSI_SET_VSYNC_TIMING 0x40U
374 #define DSI_SOFT_RESET 0x01U
375 #define DSI_WRITE_LUT 0x2DU
376 #define DSI_WRITE_MEMORY_CONTINUE 0x3CU
377 #define DSI_WRITE_MEMORY_START 0x2CU
378 
385 #define DSI_VID_MODE_NB_PULSES 0U
386 #define DSI_VID_MODE_NB_EVENTS 1U
387 #define DSI_VID_MODE_BURST 2U
388 
395 #define DSI_COLOR_MODE_FULL 0U
396 #define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM
397 
404 #define DSI_DISPLAY_ON 0U
405 #define DSI_DISPLAY_OFF DSI_WCR_SHTDN
406 
413 #define DSI_LP_COMMAND_DISABLE 0U
414 #define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE
415 
422 #define DSI_LP_HFP_DISABLE 0U
423 #define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE
424 
431 #define DSI_LP_HBP_DISABLE 0U
432 #define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE
433 
440 #define DSI_LP_VACT_DISABLE 0U
441 #define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE
442 
449 #define DSI_LP_VFP_DISABLE 0
450 #define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE
451 
458 #define DSI_LP_VBP_DISABLE 0U
459 #define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE
460 
467 #define DSI_LP_VSYNC_DISABLE 0U
468 #define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE
469 
476 #define DSI_FBTAA_DISABLE 0U
477 #define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE
478 
485 #define DSI_TE_DSILINK 0U
486 #define DSI_TE_EXTERNAL DSI_WCFGR_TESRC
487 
494 #define DSI_TE_RISING_EDGE 0U
495 #define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL
496 
503 #define DSI_VSYNC_FALLING 0U
504 #define DSI_VSYNC_RISING DSI_WCFGR_VSPOL
505 
512 #define DSI_AR_DISABLE 0U
513 #define DSI_AR_ENABLE DSI_WCFGR_AR
514 
521 #define DSI_TE_ACKNOWLEDGE_DISABLE 0U
522 #define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE
523 
530 #define DSI_ACKNOWLEDGE_DISABLE 0U
531 #define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE
532 
539 #define DSI_LP_GSW0P_DISABLE 0U
540 #define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX
541 
548 #define DSI_LP_GSW1P_DISABLE 0U
549 #define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX
550 
557 #define DSI_LP_GSW2P_DISABLE 0U
558 #define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX
559 
566 #define DSI_LP_GSR0P_DISABLE 0U
567 #define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX
568 
575 #define DSI_LP_GSR1P_DISABLE 0U
576 #define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX
577 
584 #define DSI_LP_GSR2P_DISABLE 0U
585 #define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX
586 
593 #define DSI_LP_GLW_DISABLE 0U
594 #define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX
595 
602 #define DSI_LP_DSW0P_DISABLE 0U
603 #define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX
604 
611 #define DSI_LP_DSW1P_DISABLE 0U
612 #define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX
613 
620 #define DSI_LP_DSR0P_DISABLE 0U
621 #define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX
622 
629 #define DSI_LP_DLW_DISABLE 0U
630 #define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX
631 
638 #define DSI_LP_MRDP_DISABLE 0U
639 #define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS
640 
647 #define DSI_HS_PM_DISABLE 0U
648 #define DSI_HS_PM_ENABLE DSI_TCCR3_PM
649 
657 #define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0U
658 #define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR
659 
666 #define DSI_ONE_DATA_LANE 0U
667 #define DSI_TWO_DATA_LANES 1U
668 
675 #define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE
676 #define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE
677 #define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE
678 #define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE
679 #define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE
680 #define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \
681  DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \
682  DSI_FLOW_CONTROL_EOTP_TX)
683 
690 #define DSI_RGB565 ((uint32_t)0x00000000U)
691 #define DSI_RGB666 ((uint32_t)0x00000003U)
692 #define DSI_RGB888 ((uint32_t)0x00000005U)
693 
700 #define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE
701 #define DSI_LOOSELY_PACKED_DISABLE 0U
702 
709 #define DSI_HSYNC_ACTIVE_HIGH 0U
710 #define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP
711 
718 #define DSI_VSYNC_ACTIVE_HIGH 0U
719 #define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP
720 
727 #define DSI_DATA_ENABLE_ACTIVE_HIGH 0U
728 #define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP
729 
736 #define DSI_PLL_IN_DIV1 ((uint32_t)0x00000001U)
737 #define DSI_PLL_IN_DIV2 ((uint32_t)0x00000002U)
738 #define DSI_PLL_IN_DIV3 ((uint32_t)0x00000003U)
739 #define DSI_PLL_IN_DIV4 ((uint32_t)0x00000004U)
740 #define DSI_PLL_IN_DIV5 ((uint32_t)0x00000005U)
741 #define DSI_PLL_IN_DIV6 ((uint32_t)0x00000006U)
742 #define DSI_PLL_IN_DIV7 ((uint32_t)0x00000007U)
743 
750 #define DSI_PLL_OUT_DIV1 ((uint32_t)0x00000000U)
751 #define DSI_PLL_OUT_DIV2 ((uint32_t)0x00000001U)
752 #define DSI_PLL_OUT_DIV4 ((uint32_t)0x00000002U)
753 #define DSI_PLL_OUT_DIV8 ((uint32_t)0x00000003U)
754 
761 #define DSI_FLAG_TE DSI_WISR_TEIF
762 #define DSI_FLAG_ER DSI_WISR_ERIF
763 #define DSI_FLAG_BUSY DSI_WISR_BUSY
764 #define DSI_FLAG_PLLLS DSI_WISR_PLLLS
765 #define DSI_FLAG_PLLL DSI_WISR_PLLLIF
766 #define DSI_FLAG_PLLU DSI_WISR_PLLUIF
767 #define DSI_FLAG_RRS DSI_WISR_RRS
768 #define DSI_FLAG_RR DSI_WISR_RRIF
769 
776 #define DSI_IT_TE DSI_WIER_TEIE
777 #define DSI_IT_ER DSI_WIER_ERIE
778 #define DSI_IT_PLLL DSI_WIER_PLLLIE
779 #define DSI_IT_PLLU DSI_WIER_PLLUIE
780 #define DSI_IT_RR DSI_WIER_RRIE
781 
788 #define DSI_DCS_SHORT_PKT_WRITE_P0 ((uint32_t)0x00000005U)
789 #define DSI_DCS_SHORT_PKT_WRITE_P1 ((uint32_t)0x00000015U)
790 #define DSI_GEN_SHORT_PKT_WRITE_P0 ((uint32_t)0x00000003U)
791 #define DSI_GEN_SHORT_PKT_WRITE_P1 ((uint32_t)0x00000013U)
792 #define DSI_GEN_SHORT_PKT_WRITE_P2 ((uint32_t)0x00000023U)
800 #define DSI_DCS_LONG_PKT_WRITE ((uint32_t)0x00000039U)
801 #define DSI_GEN_LONG_PKT_WRITE ((uint32_t)0x00000029U)
809 #define DSI_DCS_SHORT_PKT_READ ((uint32_t)0x00000006U)
810 #define DSI_GEN_SHORT_PKT_READ_P0 ((uint32_t)0x00000004U)
811 #define DSI_GEN_SHORT_PKT_READ_P1 ((uint32_t)0x00000014U)
812 #define DSI_GEN_SHORT_PKT_READ_P2 ((uint32_t)0x00000024U)
820 #define HAL_DSI_ERROR_NONE 0
821 #define HAL_DSI_ERROR_ACK ((uint32_t)0x00000001U)
822 #define HAL_DSI_ERROR_PHY ((uint32_t)0x00000002U)
823 #define HAL_DSI_ERROR_TX ((uint32_t)0x00000004U)
824 #define HAL_DSI_ERROR_RX ((uint32_t)0x00000008U)
825 #define HAL_DSI_ERROR_ECC ((uint32_t)0x00000010U)
826 #define HAL_DSI_ERROR_CRC ((uint32_t)0x00000020U)
827 #define HAL_DSI_ERROR_PSE ((uint32_t)0x00000040U)
828 #define HAL_DSI_ERROR_EOT ((uint32_t)0x00000080U)
829 #define HAL_DSI_ERROR_OVF ((uint32_t)0x00000100U)
830 #define HAL_DSI_ERROR_GEN ((uint32_t)0x00000200U)
838 #define DSI_CLOCK_LANE ((uint32_t)0x00000000U)
839 #define DSI_DATA_LANES ((uint32_t)0x00000001U)
840 
847 #define DSI_SLEW_RATE_HSTX ((uint32_t)0x00000000U)
848 #define DSI_SLEW_RATE_LPTX ((uint32_t)0x00000001U)
849 #define DSI_HS_DELAY ((uint32_t)0x00000002U)
850 
857 #define DSI_SWAP_LANE_PINS ((uint32_t)0x00000000U)
858 #define DSI_INVERT_HS_SIGNAL ((uint32_t)0x00000001U)
859 
866 #define DSI_CLOCK_LANE ((uint32_t)0x00000000U)
867 #define DSI_DATA_LANE0 ((uint32_t)0x00000001U)
868 #define DSI_DATA_LANE1 ((uint32_t)0x00000002U)
869 
876 #define DSI_TCLK_POST ((uint32_t)0x00000000U)
877 #define DSI_TLPX_CLK ((uint32_t)0x00000001U)
878 #define DSI_THS_EXIT ((uint32_t)0x00000002U)
879 #define DSI_TLPX_DATA ((uint32_t)0x00000003U)
880 #define DSI_THS_ZERO ((uint32_t)0x00000004U)
881 #define DSI_THS_TRAIL ((uint32_t)0x00000005U)
882 #define DSI_THS_PREPARE ((uint32_t)0x00000006U)
883 #define DSI_TCLK_ZERO ((uint32_t)0x00000007U)
884 #define DSI_TCLK_PREPARE ((uint32_t)0x00000008U)
885 
889 /* Exported macros -----------------------------------------------------------*/
895 #define __HAL_DSI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DSI_CR_EN)
896 
902 #define __HAL_DSI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DSI_CR_EN)
903 
909 #define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WCR |= DSI_WCR_DSIEN)
910 
916 #define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WCR &= ~DSI_WCR_DSIEN)
917 
923 #define __HAL_DSI_PLL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR |= DSI_WRPCR_PLLEN)
924 
930 #define __HAL_DSI_PLL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR &= ~DSI_WRPCR_PLLEN)
931 
937 #define __HAL_DSI_REG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR |= DSI_WRPCR_REGEN)
938 
944 #define __HAL_DSI_REG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR &= ~DSI_WRPCR_REGEN)
945 
961 #define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__))
962 
975 #define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__))
976 
989 #define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__))
990 
1003 #define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__))
1004 
1017 #define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WISR & (__INTERRUPT__))
1018 
1019 /* Exported functions --------------------------------------------------------*/
1023 HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit);
1024 HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi);
1025 void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi);
1026 void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi);
1027 
1028 void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);
1029 void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
1030 void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
1031 void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
1032 
1033 HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID);
1034 HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg);
1035 HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg);
1036 HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd);
1037 HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl);
1038 HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers);
1039 HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts);
1040 HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi);
1041 HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi);
1042 HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi);
1043 HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode);
1044 HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown);
1045 HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
1046  uint32_t ChannelID,
1047  uint32_t Mode,
1048  uint32_t Param1,
1049  uint32_t Param2);
1050 HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
1051  uint32_t ChannelID,
1052  uint32_t Mode,
1053  uint32_t NbParams,
1054  uint32_t Param1,
1055  uint8_t* ParametersTable);
1056 HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
1057  uint32_t ChannelNbr,
1058  uint8_t* Array,
1059  uint32_t Size,
1060  uint32_t Mode,
1061  uint32_t DCSCmd,
1062  uint8_t* ParametersTable);
1063 HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi);
1064 HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi);
1065 HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi);
1066 HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi);
1067 
1068 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation);
1069 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi);
1070 
1071 HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value);
1072 HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency);
1073 HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State);
1074 HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State);
1075 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value);
1076 HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State);
1077 HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State);
1078 HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State);
1079 HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State);
1080 HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State);
1081 
1082 uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi);
1083 HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);
1084 HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
1089 /* Private types -------------------------------------------------------------*/
1098 /* Private defines -----------------------------------------------------------*/
1107 /* Private variables ---------------------------------------------------------*/
1116 /* Private constants ---------------------------------------------------------*/
1120 #define DSI_MAX_RETURN_PKT_SIZE ((uint32_t)0x00000037)
1125 /* Private macros ------------------------------------------------------------*/
1126 
1129 #define IS_DSI_PLL_NDIV(NDIV) ((10U <= (NDIV)) && ((NDIV) <= 125U))
1130 #define IS_DSI_PLL_IDF(IDF) (((IDF) == DSI_PLL_IN_DIV1) || \
1131  ((IDF) == DSI_PLL_IN_DIV2) || \
1132  ((IDF) == DSI_PLL_IN_DIV3) || \
1133  ((IDF) == DSI_PLL_IN_DIV4) || \
1134  ((IDF) == DSI_PLL_IN_DIV5) || \
1135  ((IDF) == DSI_PLL_IN_DIV6) || \
1136  ((IDF) == DSI_PLL_IN_DIV7))
1137 #define IS_DSI_PLL_ODF(ODF) (((ODF) == DSI_PLL_OUT_DIV1) || \
1138  ((ODF) == DSI_PLL_OUT_DIV2) || \
1139  ((ODF) == DSI_PLL_OUT_DIV4) || \
1140  ((ODF) == DSI_PLL_OUT_DIV8))
1141 #define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
1142 #define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES))
1143 #define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)
1144 #define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5)
1145 #define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
1146 #define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
1147 #define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
1148 #define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
1149 #define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \
1150  ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \
1151  ((VideoModeType) == DSI_VID_MODE_BURST))
1152 #define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT))
1153 #define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF))
1154 #define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE))
1155 #define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE))
1156 #define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE))
1157 #define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE))
1158 #define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE))
1159 #define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE))
1160 #define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
1161 #define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
1162 #define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL))
1163 #define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE))
1164 #define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE))
1165 #define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING))
1166 #define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
1167 #define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
1168 #define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
1169 #define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
1170 #define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
1171 #define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
1172 #define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
1173 #define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
1174 #define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE))
1175 #define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
1176 #define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
1177 #define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
1178 #define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE))
1179 #define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
1180 #define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \
1181  ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \
1182  ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \
1183  ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \
1184  ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2))
1185 #define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \
1186  ((MODE) == DSI_GEN_LONG_PKT_WRITE))
1187 #define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) || \
1188  ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \
1189  ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \
1190  ((MODE) == DSI_GEN_SHORT_PKT_READ_P2))
1191 #define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY))
1192 #define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES))
1193 #define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL))
1194 #define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1))
1195 #define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \
1196  ((Timing) == DSI_TLPX_CLK ) || \
1197  ((Timing) == DSI_THS_EXIT ) || \
1198  ((Timing) == DSI_TLPX_DATA ) || \
1199  ((Timing) == DSI_THS_ZERO ) || \
1200  ((Timing) == DSI_THS_TRAIL ) || \
1201  ((Timing) == DSI_THS_PREPARE ) || \
1202  ((Timing) == DSI_TCLK_ZERO ) || \
1203  ((Timing) == DSI_TCLK_PREPARE))
1204 
1209 /* Private functions prototypes ----------------------------------------------*/
1218 /* Private functions ---------------------------------------------------------*/
1234 #endif /*STM32F769xx | STM32F779xx */
1235 
1236 #ifdef __cplusplus
1237 }
1238 #endif
1239 
1240 #endif /* __STM32F7xx_HAL_DSI_H */
1241 
1242 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
__DMA2D_HandleTypeDef::Instance
DMA2D_TypeDef * Instance
Definition: stm32f7xx_hal_dma2d.h:179
LPCmd
DSI_LPCmdTypeDef LPCmd
Definition: main.c:69
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition.
Definition: stm32f7xx_hal_def.h:67
CmdCfg
DSI_CmdCfgTypeDef CmdCfg
Definition: main.c:68
HAL_DSI_EndOfRefreshCallback
void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi)
End of Refresh DSI callback.
Definition: main.c:591
FunctionalState
FunctionalState
Definition: stm32f7xx.h:158
__IO
#define __IO
Definition: core_cm0.h:213
__DMA2D_HandleTypeDef::State
__IO HAL_DMA2D_StateTypeDef State
Definition: stm32f7xx_hal_dma2d.h:191
__DMA2D_HandleTypeDef::Init
DMA2D_InitTypeDef Init
Definition: stm32f7xx_hal_dma2d.h:181
stm32f7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
__DMA2D_HandleTypeDef::ErrorCode
__IO uint32_t ErrorCode
Definition: stm32f7xx_hal_dma2d.h:193
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32f7xx_hal_def.h:56
__DMA2D_HandleTypeDef::Lock
HAL_LockTypeDef Lock
Definition: stm32f7xx_hal_dma2d.h:189
DSI_TypeDef
DSI Controller.
Definition: stm32f769xx.h:1313
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