STM32F769IDiscovery  1.00
uDANTE Audio Networking with STM32F7 DISCO board
core_cm0plus.h
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1 /**************************************************************************/
7 /* Copyright (c) 2009 - 2015 ARM LIMITED
8 
9  All rights reserved.
10  Redistribution and use in source and binary forms, with or without
11  modification, are permitted provided that the following conditions are met:
12  - Redistributions of source code must retain the above copyright
13  notice, this list of conditions and the following disclaimer.
14  - Redistributions in binary form must reproduce the above copyright
15  notice, this list of conditions and the following disclaimer in the
16  documentation and/or other materials provided with the distribution.
17  - Neither the name of ARM nor the names of its contributors may be used
18  to endorse or promote products derived from this software without
19  specific prior written permission.
20  *
21  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
25  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  POSSIBILITY OF SUCH DAMAGE.
32  ---------------------------------------------------------------------------*/
33 
34 
35 #if defined ( __ICCARM__ )
36  #pragma system_include /* treat file as system include file for MISRA check */
37 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
38  #pragma clang system_header /* treat file as system include file */
39 #endif
40 
41 #ifndef __CORE_CM0PLUS_H_GENERIC
42 #define __CORE_CM0PLUS_H_GENERIC
43 
44 #include <stdint.h>
45 
46 #ifdef __cplusplus
47  extern "C" {
48 #endif
49 
65 /*******************************************************************************
66  * CMSIS definitions
67  ******************************************************************************/
73 /* CMSIS CM0+ definitions */
74 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U)
75 #define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU)
76 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
77  __CM0PLUS_CMSIS_VERSION_SUB )
79 #define __CORTEX_M (0x00U)
82 #if defined ( __CC_ARM )
83  #define __ASM __asm
84  #define __INLINE __inline
85  #define __STATIC_INLINE static __inline
86 
87 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
88  #define __ASM __asm
89  #define __INLINE __inline
90  #define __STATIC_INLINE static __inline
91 
92 #elif defined ( __GNUC__ )
93  #define __ASM __asm
94  #define __INLINE inline
95  #define __STATIC_INLINE static inline
96 
97 #elif defined ( __ICCARM__ )
98  #define __ASM __asm
99  #define __INLINE inline
100  #define __STATIC_INLINE static inline
101 
102 #elif defined ( __TMS470__ )
103  #define __ASM __asm
104  #define __STATIC_INLINE static inline
105 
106 #elif defined ( __TASKING__ )
107  #define __ASM __asm
108  #define __INLINE inline
109  #define __STATIC_INLINE static inline
110 
111 #elif defined ( __CSMC__ )
112  #define __packed
113  #define __ASM _asm
114  #define __INLINE inline
115  #define __STATIC_INLINE static inline
116 
117 #else
118  #error Unknown compiler
119 #endif
120 
124 #define __FPU_USED 0U
125 
126 #if defined ( __CC_ARM )
127  #if defined __TARGET_FPU_VFP
128  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
129  #endif
130 
131 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
132  #if defined __ARM_PCS_VFP
133  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
134  #endif
135 
136 #elif defined ( __GNUC__ )
137  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
138  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
139  #endif
140 
141 #elif defined ( __ICCARM__ )
142  #if defined __ARMVFP__
143  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
144  #endif
145 
146 #elif defined ( __TMS470__ )
147  #if defined __TI_VFP_SUPPORT__
148  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
149  #endif
150 
151 #elif defined ( __TASKING__ )
152  #if defined __FPU_VFP__
153  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
154  #endif
155 
156 #elif defined ( __CSMC__ )
157  #if ( __CSMC__ & 0x400U)
158  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
159  #endif
160 
161 #endif
162 
163 #include "core_cmInstr.h" /* Core Instruction Access */
164 #include "core_cmFunc.h" /* Core Function Access */
165 
166 #ifdef __cplusplus
167 }
168 #endif
169 
170 #endif /* __CORE_CM0PLUS_H_GENERIC */
171 
172 #ifndef __CMSIS_GENERIC
173 
174 #ifndef __CORE_CM0PLUS_H_DEPENDANT
175 #define __CORE_CM0PLUS_H_DEPENDANT
176 
177 #ifdef __cplusplus
178  extern "C" {
179 #endif
180 
181 /* check device defines and use defaults */
182 #if defined __CHECK_DEVICE_DEFINES
183  #ifndef __CM0PLUS_REV
184  #define __CM0PLUS_REV 0x0000U
185  #warning "__CM0PLUS_REV not defined in device header file; using default!"
186  #endif
187 
188  #ifndef __MPU_PRESENT
189  #define __MPU_PRESENT 0U
190  #warning "__MPU_PRESENT not defined in device header file; using default!"
191  #endif
192 
193  #ifndef __VTOR_PRESENT
194  #define __VTOR_PRESENT 0U
195  #warning "__VTOR_PRESENT not defined in device header file; using default!"
196  #endif
197 
198  #ifndef __NVIC_PRIO_BITS
199  #define __NVIC_PRIO_BITS 2U
200  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
201  #endif
202 
203  #ifndef __Vendor_SysTickConfig
204  #define __Vendor_SysTickConfig 0U
205  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
206  #endif
207 #endif
208 
209 /* IO definitions (access restrictions to peripheral registers) */
217 #ifdef __cplusplus
218  #define __I volatile
219 #else
220  #define __I volatile const
221 #endif
222 #define __O volatile
223 #define __IO volatile
225 /* following defines should be used for structure members */
226 #define __IM volatile const
227 #define __OM volatile
228 #define __IOM volatile
230 
234 /*******************************************************************************
235  * Register Abstraction
236  Core Register contain:
237  - Core Register
238  - Core NVIC Register
239  - Core SCB Register
240  - Core SysTick Register
241  - Core MPU Register
242  ******************************************************************************/
243 
258 typedef union
259 {
260  struct
261  {
262  uint32_t _reserved0:28;
263  uint32_t V:1;
264  uint32_t C:1;
265  uint32_t Z:1;
266  uint32_t N:1;
267  } b;
268  uint32_t w;
269 } APSR_Type;
270 
271 /* APSR Register Definitions */
272 #define APSR_N_Pos 31U
273 #define APSR_N_Msk (1UL << APSR_N_Pos)
275 #define APSR_Z_Pos 30U
276 #define APSR_Z_Msk (1UL << APSR_Z_Pos)
278 #define APSR_C_Pos 29U
279 #define APSR_C_Msk (1UL << APSR_C_Pos)
281 #define APSR_V_Pos 28U
282 #define APSR_V_Msk (1UL << APSR_V_Pos)
288 typedef union
289 {
290  struct
291  {
292  uint32_t ISR:9;
293  uint32_t _reserved0:23;
294  } b;
295  uint32_t w;
296 } IPSR_Type;
297 
298 /* IPSR Register Definitions */
299 #define IPSR_ISR_Pos 0U
300 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
306 typedef union
307 {
308  struct
309  {
310  uint32_t ISR:9;
311  uint32_t _reserved0:15;
312  uint32_t T:1;
313  uint32_t _reserved1:3;
314  uint32_t V:1;
315  uint32_t C:1;
316  uint32_t Z:1;
317  uint32_t N:1;
318  } b;
319  uint32_t w;
320 } xPSR_Type;
321 
322 /* xPSR Register Definitions */
323 #define xPSR_N_Pos 31U
324 #define xPSR_N_Msk (1UL << xPSR_N_Pos)
326 #define xPSR_Z_Pos 30U
327 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
329 #define xPSR_C_Pos 29U
330 #define xPSR_C_Msk (1UL << xPSR_C_Pos)
332 #define xPSR_V_Pos 28U
333 #define xPSR_V_Msk (1UL << xPSR_V_Pos)
335 #define xPSR_T_Pos 24U
336 #define xPSR_T_Msk (1UL << xPSR_T_Pos)
338 #define xPSR_ISR_Pos 0U
339 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
345 typedef union
346 {
347  struct
348  {
349  uint32_t nPRIV:1;
350  uint32_t SPSEL:1;
351  uint32_t _reserved1:30;
352  } b;
353  uint32_t w;
354 } CONTROL_Type;
355 
356 /* CONTROL Register Definitions */
357 #define CONTROL_SPSEL_Pos 1U
358 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
360 #define CONTROL_nPRIV_Pos 0U
361 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)
363 
376 typedef struct
377 {
378  __IOM uint32_t ISER[1U];
379  uint32_t RESERVED0[31U];
380  __IOM uint32_t ICER[1U];
381  uint32_t RSERVED1[31U];
382  __IOM uint32_t ISPR[1U];
383  uint32_t RESERVED2[31U];
384  __IOM uint32_t ICPR[1U];
385  uint32_t RESERVED3[31U];
386  uint32_t RESERVED4[64U];
387  __IOM uint32_t IP[8U];
388 } NVIC_Type;
389 
403 typedef struct
404 {
405  __IM uint32_t CPUID;
406  __IOM uint32_t ICSR;
407 #if (__VTOR_PRESENT == 1U)
408  __IOM uint32_t VTOR;
409 #else
410  uint32_t RESERVED0;
411 #endif
412  __IOM uint32_t AIRCR;
413  __IOM uint32_t SCR;
414  __IOM uint32_t CCR;
415  uint32_t RESERVED1;
416  __IOM uint32_t SHP[2U];
417  __IOM uint32_t SHCSR;
418 } SCB_Type;
419 
420 /* SCB CPUID Register Definitions */
421 #define SCB_CPUID_IMPLEMENTER_Pos 24U
422 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
424 #define SCB_CPUID_VARIANT_Pos 20U
425 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
427 #define SCB_CPUID_ARCHITECTURE_Pos 16U
428 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
430 #define SCB_CPUID_PARTNO_Pos 4U
431 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
433 #define SCB_CPUID_REVISION_Pos 0U
434 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
436 /* SCB Interrupt Control State Register Definitions */
437 #define SCB_ICSR_NMIPENDSET_Pos 31U
438 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
440 #define SCB_ICSR_PENDSVSET_Pos 28U
441 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
443 #define SCB_ICSR_PENDSVCLR_Pos 27U
444 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
446 #define SCB_ICSR_PENDSTSET_Pos 26U
447 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
449 #define SCB_ICSR_PENDSTCLR_Pos 25U
450 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
452 #define SCB_ICSR_ISRPREEMPT_Pos 23U
453 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
455 #define SCB_ICSR_ISRPENDING_Pos 22U
456 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
458 #define SCB_ICSR_VECTPENDING_Pos 12U
459 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
461 #define SCB_ICSR_VECTACTIVE_Pos 0U
462 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
464 #if (__VTOR_PRESENT == 1U)
465 /* SCB Interrupt Control State Register Definitions */
466 #define SCB_VTOR_TBLOFF_Pos 8U
467 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)
468 #endif
469 
470 /* SCB Application Interrupt and Reset Control Register Definitions */
471 #define SCB_AIRCR_VECTKEY_Pos 16U
472 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
474 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U
475 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
477 #define SCB_AIRCR_ENDIANESS_Pos 15U
478 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
480 #define SCB_AIRCR_SYSRESETREQ_Pos 2U
481 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
483 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
484 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
486 /* SCB System Control Register Definitions */
487 #define SCB_SCR_SEVONPEND_Pos 4U
488 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
490 #define SCB_SCR_SLEEPDEEP_Pos 2U
491 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
493 #define SCB_SCR_SLEEPONEXIT_Pos 1U
494 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
496 /* SCB Configuration Control Register Definitions */
497 #define SCB_CCR_STKALIGN_Pos 9U
498 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
500 #define SCB_CCR_UNALIGN_TRP_Pos 3U
501 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
503 /* SCB System Handler Control and State Register Definitions */
504 #define SCB_SHCSR_SVCALLPENDED_Pos 15U
505 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
507 
520 typedef struct
521 {
522  __IOM uint32_t CTRL;
523  __IOM uint32_t LOAD;
524  __IOM uint32_t VAL;
525  __IM uint32_t CALIB;
526 } SysTick_Type;
527 
528 /* SysTick Control / Status Register Definitions */
529 #define SysTick_CTRL_COUNTFLAG_Pos 16U
530 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
532 #define SysTick_CTRL_CLKSOURCE_Pos 2U
533 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
535 #define SysTick_CTRL_TICKINT_Pos 1U
536 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
538 #define SysTick_CTRL_ENABLE_Pos 0U
539 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
541 /* SysTick Reload Register Definitions */
542 #define SysTick_LOAD_RELOAD_Pos 0U
543 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
545 /* SysTick Current Register Definitions */
546 #define SysTick_VAL_CURRENT_Pos 0U
547 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
549 /* SysTick Calibration Register Definitions */
550 #define SysTick_CALIB_NOREF_Pos 31U
551 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
553 #define SysTick_CALIB_SKEW_Pos 30U
554 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
556 #define SysTick_CALIB_TENMS_Pos 0U
557 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
559 
561 #if (__MPU_PRESENT == 1U)
562 
572 typedef struct
573 {
574  __IM uint32_t TYPE;
575  __IOM uint32_t CTRL;
576  __IOM uint32_t RNR;
577  __IOM uint32_t RBAR;
578  __IOM uint32_t RASR;
579 } MPU_Type;
580 
581 /* MPU Type Register Definitions */
582 #define MPU_TYPE_IREGION_Pos 16U
583 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
585 #define MPU_TYPE_DREGION_Pos 8U
586 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
588 #define MPU_TYPE_SEPARATE_Pos 0U
589 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
591 /* MPU Control Register Definitions */
592 #define MPU_CTRL_PRIVDEFENA_Pos 2U
593 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
595 #define MPU_CTRL_HFNMIENA_Pos 1U
596 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
598 #define MPU_CTRL_ENABLE_Pos 0U
599 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
601 /* MPU Region Number Register Definitions */
602 #define MPU_RNR_REGION_Pos 0U
603 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
605 /* MPU Region Base Address Register Definitions */
606 #define MPU_RBAR_ADDR_Pos 8U
607 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)
609 #define MPU_RBAR_VALID_Pos 4U
610 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
612 #define MPU_RBAR_REGION_Pos 0U
613 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
615 /* MPU Region Attribute and Size Register Definitions */
616 #define MPU_RASR_ATTRS_Pos 16U
617 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
619 #define MPU_RASR_XN_Pos 28U
620 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
622 #define MPU_RASR_AP_Pos 24U
623 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
625 #define MPU_RASR_TEX_Pos 19U
626 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
628 #define MPU_RASR_S_Pos 18U
629 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
631 #define MPU_RASR_C_Pos 17U
632 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
634 #define MPU_RASR_B_Pos 16U
635 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
637 #define MPU_RASR_SRD_Pos 8U
638 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
640 #define MPU_RASR_SIZE_Pos 1U
641 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
643 #define MPU_RASR_ENABLE_Pos 0U
644 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/)
646 
647 #endif
648 
649 
657 
673 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
674 
681 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
682 
693 /* Memory mapping of Cortex-M0+ Hardware */
694 #define SCS_BASE (0xE000E000UL)
695 #define SysTick_BASE (SCS_BASE + 0x0010UL)
696 #define NVIC_BASE (SCS_BASE + 0x0100UL)
697 #define SCB_BASE (SCS_BASE + 0x0D00UL)
699 #define SCB ((SCB_Type *) SCB_BASE )
700 #define SysTick ((SysTick_Type *) SysTick_BASE )
701 #define NVIC ((NVIC_Type *) NVIC_BASE )
703 #if (__MPU_PRESENT == 1U)
704  #define MPU_BASE (SCS_BASE + 0x0D90UL)
705  #define MPU ((MPU_Type *) MPU_BASE )
706 #endif
707 
712 /*******************************************************************************
713  * Hardware Abstraction Layer
714  Core Function Interface contains:
715  - Core NVIC Functions
716  - Core SysTick Functions
717  - Core Register Access Functions
718  ******************************************************************************/
725 /* ########################## NVIC functions #################################### */
733 /* Interrupt Priorities are WORD accessible only under ARMv6M */
734 /* The following MACROS handle generation of the register offset and byte masks */
735 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
736 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
737 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
738 
739 
745 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
746 {
747  NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
748 }
749 
750 
756 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
757 {
758  NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
759 }
760 
761 
769 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
770 {
771  return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
772 }
773 
774 
780 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
781 {
782  NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
783 }
784 
785 
791 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
792 {
793  NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
794 }
795 
796 
804 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
805 {
806  if ((int32_t)(IRQn) < 0)
807  {
808  SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
809  (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
810  }
811  else
812  {
813  NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
814  (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
815  }
816 }
817 
818 
828 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
829 {
830 
831  if ((int32_t)(IRQn) < 0)
832  {
833  return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
834  }
835  else
836  {
837  return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
838  }
839 }
840 
841 
846 __STATIC_INLINE void NVIC_SystemReset(void)
847 {
848  __DSB(); /* Ensure all outstanding memory accesses included
849  buffered write are completed before reset */
850  SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
851  SCB_AIRCR_SYSRESETREQ_Msk);
852  __DSB(); /* Ensure completion of memory access */
853 
854  for(;;) /* wait until reset */
855  {
856  __NOP();
857  }
858 }
859 
864 /* ################################## SysTick function ############################################ */
872 #if (__Vendor_SysTickConfig == 0U)
873 
885 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
886 {
887  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
888  {
889  return (1UL); /* Reload value impossible */
890  }
891 
892  SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
893  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
894  SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
895  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
896  SysTick_CTRL_TICKINT_Msk |
897  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
898  return (0UL); /* Function successful */
899 }
900 
901 #endif
902 
908 #ifdef __cplusplus
909 }
910 #endif
911 
912 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
913 
914 #endif /* __CMSIS_GENERIC */
core_cmFunc.h
CMSIS Cortex-M Core Function Access Header File.
__NOP
#define __NOP
No Operation.
Definition: cmsis_armcc.h:313
NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_cm0.h:653
NVIC_SetPendingIRQ
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_cm0.h:664
_IP_IDX
#define _IP_IDX(IRQn)
Definition: core_cm0plus.h:737
SysTick
#define SysTick
Definition: core_cm0plus.h:700
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_cm0.h:277
__DSB
#define __DSB()
Data Synchronization Barrier.
Definition: cmsis_armcc.h:355
NVIC
#define NVIC
Definition: core_cm0plus.h:701
NVIC_EnableIRQ
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable External Interrupt.
Definition: core_cm0.h:629
SysTick_IRQn
Definition: stm32f745xx.h:77
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: core_cm0.h:389
SCB
#define SCB
Definition: core_cm0plus.h:699
IRQn_Type
IRQn_Type
STM32F7xx Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f745xx.h:67
__IM
#define __IM
Definition: core_cm0plus.h:226
SysTick_Config
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
System Tick Configuration.
Definition: core_cm0.h:769
NVIC_GetPriority
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_cm0.h:712
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: stm32f745xx.h:185
NVIC_SetPriority
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_cm0.h:688
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_cm0.h:362
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: core_cm0.h:496
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_cm0plus.h:471
NVIC_SystemReset
__STATIC_INLINE void NVIC_SystemReset(void)
System Reset.
Definition: core_cm0.h:730
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_cm0plus.h:481
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: core_cm0.h:247
NVIC_DisableIRQ
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Disable External Interrupt.
Definition: core_cm0.h:640
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_cm0plus.h:543
__IOM
#define __IOM
Definition: core_cm0plus.h:228
_BIT_SHIFT
#define _BIT_SHIFT(IRQn)
Definition: core_cm0plus.h:735
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: core_cm0.h:334
_SHP_IDX
#define _SHP_IDX(IRQn)
Definition: core_cm0plus.h:736
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_cm0plus.h:533
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_cm0plus.h:539
NVIC_ClearPendingIRQ
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_cm0.h:675
core_cmInstr.h
CMSIS Cortex-M Core Instruction Access Header File.
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_cm0.h:295
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_cm0plus.h:536
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