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stm32f7xx_hal_cortex.h
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1 
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F7xx_HAL_CORTEX_H
40 #define __STM32F7xx_HAL_CORTEX_H
41 
42 #ifdef __cplusplus
43  extern "C" {
44 #endif
45 
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f7xx_hal_def.h"
48 
56 /* Exported types ------------------------------------------------------------*/
61 #if (__MPU_PRESENT == 1)
62 
66 typedef struct
67 {
68  uint8_t Enable;
70  uint8_t Number;
72  uint32_t BaseAddress;
73  uint8_t Size;
75  uint8_t SubRegionDisable;
77  uint8_t TypeExtField;
79  uint8_t AccessPermission;
81  uint8_t DisableExec;
83  uint8_t IsShareable;
85  uint8_t IsCacheable;
87  uint8_t IsBufferable;
89 }MPU_Region_InitTypeDef;
93 #endif /* __MPU_PRESENT */
94 
99 /* Exported constants --------------------------------------------------------*/
100 
108 #define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007U)
110 #define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006U)
112 #define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005U)
114 #define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004U)
116 #define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003U)
125 #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U)
126 #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U)
127 
132 #if (__MPU_PRESENT == 1)
133 
136 #define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U)
137 #define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U)
138 #define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U)
139 #define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U)
140 
147 #define MPU_REGION_ENABLE ((uint8_t)0x01U)
148 #define MPU_REGION_DISABLE ((uint8_t)0x00U)
149 
156 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)
157 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)
158 
165 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)
166 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)
167 
174 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)
175 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)
176 
183 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)
184 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)
185 
192 #define MPU_TEX_LEVEL0 ((uint8_t)0x00U)
193 #define MPU_TEX_LEVEL1 ((uint8_t)0x01U)
194 #define MPU_TEX_LEVEL2 ((uint8_t)0x02U)
195 
202 #define MPU_REGION_SIZE_32B ((uint8_t)0x04U)
203 #define MPU_REGION_SIZE_64B ((uint8_t)0x05U)
204 #define MPU_REGION_SIZE_128B ((uint8_t)0x06U)
205 #define MPU_REGION_SIZE_256B ((uint8_t)0x07U)
206 #define MPU_REGION_SIZE_512B ((uint8_t)0x08U)
207 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
208 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
209 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
210 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
211 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
212 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
213 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
214 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
215 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
216 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
217 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
218 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
219 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
220 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
221 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
222 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
223 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
224 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
225 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
226 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
227 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
228 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
229 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
230 
237 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00U)
238 #define MPU_REGION_PRIV_RW ((uint8_t)0x01U)
239 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)
240 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)
241 #define MPU_REGION_PRIV_RO ((uint8_t)0x05U)
242 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)
243 
250 #define MPU_REGION_NUMBER0 ((uint8_t)0x00U)
251 #define MPU_REGION_NUMBER1 ((uint8_t)0x01U)
252 #define MPU_REGION_NUMBER2 ((uint8_t)0x02U)
253 #define MPU_REGION_NUMBER3 ((uint8_t)0x03U)
254 #define MPU_REGION_NUMBER4 ((uint8_t)0x04U)
255 #define MPU_REGION_NUMBER5 ((uint8_t)0x05U)
256 #define MPU_REGION_NUMBER6 ((uint8_t)0x06U)
257 #define MPU_REGION_NUMBER7 ((uint8_t)0x07U)
258 
261 #endif /* __MPU_PRESENT */
262 
268 /* Exported Macros -----------------------------------------------------------*/
269 
270 /* Exported functions --------------------------------------------------------*/
278 /* Initialization and de-initialization functions *****************************/
279 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
280 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
281 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
282 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
283 void HAL_NVIC_SystemReset(void);
284 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
292 /* Peripheral Control functions ***********************************************/
293 #if (__MPU_PRESENT == 1)
294 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
295 #endif /* __MPU_PRESENT */
296 uint32_t HAL_NVIC_GetPriorityGrouping(void);
297 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
298 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
299 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
300 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
301 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
302 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
303 void HAL_SYSTICK_IRQHandler(void);
304 void HAL_SYSTICK_Callback(void);
313 /* Private types -------------------------------------------------------------*/
314 /* Private variables ---------------------------------------------------------*/
315 /* Private constants ---------------------------------------------------------*/
316 /* Private macros ------------------------------------------------------------*/
320 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
321  ((GROUP) == NVIC_PRIORITYGROUP_1) || \
322  ((GROUP) == NVIC_PRIORITYGROUP_2) || \
323  ((GROUP) == NVIC_PRIORITYGROUP_3) || \
324  ((GROUP) == NVIC_PRIORITYGROUP_4))
325 
326 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
327 
328 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
329 
330 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
331 
332 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
333  ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
334 
335 #if (__MPU_PRESENT == 1)
336 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
337  ((STATE) == MPU_REGION_DISABLE))
338 
339 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
340  ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
341 
342 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
343  ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
344 
345 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
346  ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
347 
348 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
349  ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
350 
351 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
352  ((TYPE) == MPU_TEX_LEVEL1) || \
353  ((TYPE) == MPU_TEX_LEVEL2))
354 
355 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
356  ((TYPE) == MPU_REGION_PRIV_RW) || \
357  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
358  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
359  ((TYPE) == MPU_REGION_PRIV_RO) || \
360  ((TYPE) == MPU_REGION_PRIV_RO_URO))
361 
362 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
363  ((NUMBER) == MPU_REGION_NUMBER1) || \
364  ((NUMBER) == MPU_REGION_NUMBER2) || \
365  ((NUMBER) == MPU_REGION_NUMBER3) || \
366  ((NUMBER) == MPU_REGION_NUMBER4) || \
367  ((NUMBER) == MPU_REGION_NUMBER5) || \
368  ((NUMBER) == MPU_REGION_NUMBER6) || \
369  ((NUMBER) == MPU_REGION_NUMBER7))
370 
371 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
372  ((SIZE) == MPU_REGION_SIZE_64B) || \
373  ((SIZE) == MPU_REGION_SIZE_128B) || \
374  ((SIZE) == MPU_REGION_SIZE_256B) || \
375  ((SIZE) == MPU_REGION_SIZE_512B) || \
376  ((SIZE) == MPU_REGION_SIZE_1KB) || \
377  ((SIZE) == MPU_REGION_SIZE_2KB) || \
378  ((SIZE) == MPU_REGION_SIZE_4KB) || \
379  ((SIZE) == MPU_REGION_SIZE_8KB) || \
380  ((SIZE) == MPU_REGION_SIZE_16KB) || \
381  ((SIZE) == MPU_REGION_SIZE_32KB) || \
382  ((SIZE) == MPU_REGION_SIZE_64KB) || \
383  ((SIZE) == MPU_REGION_SIZE_128KB) || \
384  ((SIZE) == MPU_REGION_SIZE_256KB) || \
385  ((SIZE) == MPU_REGION_SIZE_512KB) || \
386  ((SIZE) == MPU_REGION_SIZE_1MB) || \
387  ((SIZE) == MPU_REGION_SIZE_2MB) || \
388  ((SIZE) == MPU_REGION_SIZE_4MB) || \
389  ((SIZE) == MPU_REGION_SIZE_8MB) || \
390  ((SIZE) == MPU_REGION_SIZE_16MB) || \
391  ((SIZE) == MPU_REGION_SIZE_32MB) || \
392  ((SIZE) == MPU_REGION_SIZE_64MB) || \
393  ((SIZE) == MPU_REGION_SIZE_128MB) || \
394  ((SIZE) == MPU_REGION_SIZE_256MB) || \
395  ((SIZE) == MPU_REGION_SIZE_512MB) || \
396  ((SIZE) == MPU_REGION_SIZE_1GB) || \
397  ((SIZE) == MPU_REGION_SIZE_2GB) || \
398  ((SIZE) == MPU_REGION_SIZE_4GB))
399 
400 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)
401 #endif /* __MPU_PRESENT */
402 
407 /* Private functions ---------------------------------------------------------*/
413 #if (__MPU_PRESENT == 1)
414 
418 __STATIC_INLINE void HAL_MPU_Disable(void)
419 {
420  /* Disable fault exceptions */
421  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
422 
423  /* Disable the MPU */
424  MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
425 }
426 
438 __STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
439 {
440  /* Enable the MPU */
441  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
442 
443  /* Enable fault exceptions */
444  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
445 }
446 #endif /* __MPU_PRESENT */
447 
460 #ifdef __cplusplus
461 }
462 #endif
463 
464 #endif /* __STM32F7xx_HAL_CORTEX_H */
465 
466 
467 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
HAL_NVIC_SetPriorityGrouping
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
HAL_NVIC_SetPendingIRQ
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
HAL_NVIC_ClearPendingIRQ
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
HAL_NVIC_GetPriorityGrouping
uint32_t HAL_NVIC_GetPriorityGrouping(void)
HAL_NVIC_GetPendingIRQ
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
SCB_SHCSR_MEMFAULTENA_Msk
#define SCB_SHCSR_MEMFAULTENA_Msk
Definition: core_cm3.h:560
HAL_SYSTICK_Config
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
HAL_NVIC_GetPriority
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
HAL_NVIC_SetPriority
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
SCB
#define SCB
Definition: core_cm0.h:587
IRQn_Type
IRQn_Type
STM32F7xx Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f745xx.h:67
HAL_SYSTICK_Callback
void HAL_SYSTICK_Callback(void)
HAL_NVIC_EnableIRQ
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
HAL_SYSTICK_IRQHandler
void HAL_SYSTICK_IRQHandler(void)
stm32f7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_NVIC_SystemReset
void HAL_NVIC_SystemReset(void)
HAL_SYSTICK_CLKSourceConfig
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
HAL_NVIC_GetActive
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
HAL_NVIC_DisableIRQ
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
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