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STM32F769IDiscovery
1.00
uDANTE Audio Networking with STM32F7 DISCO board
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Header file of SPI HAL module. More...
#include "stm32f7xx_hal_def.h"
Go to the source code of this file.
Data Structures | |
struct | SPI_InitTypeDef |
SPI Configuration Structure definition. More... | |
struct | __SPI_HandleTypeDef |
SPI handle Structure definition. More... | |
Macros | |
#define | HAL_SPI_ERROR_NONE ((uint32_t)0x00000000U) |
#define | HAL_SPI_ERROR_MODF ((uint32_t)0x00000001U) |
#define | HAL_SPI_ERROR_CRC ((uint32_t)0x00000002U) |
#define | HAL_SPI_ERROR_OVR ((uint32_t)0x00000004U) |
#define | HAL_SPI_ERROR_FRE ((uint32_t)0x00000008U) |
#define | HAL_SPI_ERROR_DMA ((uint32_t)0x00000010U) |
#define | HAL_SPI_ERROR_FLAG ((uint32_t)0x00000020U) |
#define | HAL_SPI_ERROR_UNKNOW ((uint32_t)0x00000040U) |
#define | SPI_MODE_SLAVE ((uint32_t)0x00000000U) |
#define | SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) |
#define | SPI_DIRECTION_2LINES ((uint32_t)0x00000000U) |
#define | SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY |
#define | SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE |
#define | SPI_DATASIZE_4BIT ((uint32_t)0x0300U) |
#define | SPI_DATASIZE_5BIT ((uint32_t)0x0400U) |
#define | SPI_DATASIZE_6BIT ((uint32_t)0x0500U) |
#define | SPI_DATASIZE_7BIT ((uint32_t)0x0600U) |
#define | SPI_DATASIZE_8BIT ((uint32_t)0x0700U) |
#define | SPI_DATASIZE_9BIT ((uint32_t)0x0800U) |
#define | SPI_DATASIZE_10BIT ((uint32_t)0x0900U) |
#define | SPI_DATASIZE_11BIT ((uint32_t)0x0A00U) |
#define | SPI_DATASIZE_12BIT ((uint32_t)0x0B00U) |
#define | SPI_DATASIZE_13BIT ((uint32_t)0x0C00U) |
#define | SPI_DATASIZE_14BIT ((uint32_t)0x0D00U) |
#define | SPI_DATASIZE_15BIT ((uint32_t)0x0E00U) |
#define | SPI_DATASIZE_16BIT ((uint32_t)0x0F00U) |
#define | SPI_POLARITY_LOW ((uint32_t)0x00000000U) |
#define | SPI_POLARITY_HIGH SPI_CR1_CPOL |
#define | SPI_PHASE_1EDGE ((uint32_t)0x00000000U) |
#define | SPI_PHASE_2EDGE SPI_CR1_CPHA |
#define | SPI_NSS_SOFT SPI_CR1_SSM |
#define | SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U) |
#define | SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000U) |
#define | SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP |
#define | SPI_NSS_PULSE_DISABLE ((uint32_t)0x00000000U) |
#define | SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000U) |
#define | SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008U) |
#define | SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010U) |
#define | SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018U) |
#define | SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020U) |
#define | SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028U) |
#define | SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030U) |
#define | SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038U) |
#define | SPI_FIRSTBIT_MSB ((uint32_t)0x00000000U) |
#define | SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST |
#define | SPI_TIMODE_DISABLE ((uint32_t)0x00000000U) |
#define | SPI_TIMODE_ENABLE SPI_CR2_FRF |
#define | SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U) |
#define | SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN |
#define | SPI_CRC_LENGTH_DATASIZE ((uint32_t)0x00000000U) |
#define | SPI_CRC_LENGTH_8BIT ((uint32_t)0x00000001U) |
#define | SPI_CRC_LENGTH_16BIT ((uint32_t)0x00000002U) |
#define | SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH |
#define | SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH |
#define | SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x00000000U) |
#define | SPI_IT_TXE SPI_CR2_TXEIE |
#define | SPI_IT_RXNE SPI_CR2_RXNEIE |
#define | SPI_IT_ERR SPI_CR2_ERRIE |
#define | SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */ |
#define | SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */ |
#define | SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */ |
#define | SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */ |
#define | SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */ |
#define | SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */ |
#define | SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */ |
#define | SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */ |
#define | SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */ |
#define | SPI_FTLVL_EMPTY ((uint32_t)0x0000U) |
#define | SPI_FTLVL_QUARTER_FULL ((uint32_t)0x0800U) |
#define | SPI_FTLVL_HALF_FULL ((uint32_t)0x1000U) |
#define | SPI_FTLVL_FULL ((uint32_t)0x1800U) |
#define | SPI_FRLVL_EMPTY ((uint32_t)0x0000U) |
#define | SPI_FRLVL_QUARTER_FULL ((uint32_t)0x0200U) |
#define | SPI_FRLVL_HALF_FULL ((uint32_t)0x0400U) |
#define | SPI_FRLVL_FULL ((uint32_t)0x0600U) |
#define | __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) |
Reset SPI handle state. More... | |
#define | __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__)) |
Enables or disables the specified SPI interrupts. More... | |
#define | __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__))) |
#define | __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
Checks if the specified SPI interrupt source is enabled or disabled. More... | |
#define | __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
Checks whether the specified SPI flag is set or not. More... | |
#define | __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) |
Clears the SPI CRCERR pending flag. More... | |
#define | __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) |
Clears the SPI MODF pending flag. More... | |
#define | __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) |
Clears the SPI OVR pending flag. More... | |
#define | __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) |
Clears the SPI FRE pending flag. More... | |
#define | __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE) |
Enables the SPI. More... | |
#define | __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE)) |
Disables the SPI. More... | |
#define | SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE) |
Sets the SPI transmit-only mode. More... | |
#define | SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE)) |
Sets the SPI receive-only mode. More... | |
#define | SPI_RESET_CRC(__HANDLE__) |
Resets the CRC calculation of the SPI. More... | |
#define | IS_SPI_MODE(MODE) |
#define | IS_SPI_DIRECTION(MODE) |
#define | IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) |
#define | IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) |
#define | IS_SPI_DATASIZE(DATASIZE) |
#define | IS_SPI_CPOL(CPOL) |
#define | IS_SPI_CPHA(CPHA) |
#define | IS_SPI_NSS(NSS) |
#define | IS_SPI_NSSP(NSSP) |
#define | IS_SPI_BAUDRATE_PRESCALER(PRESCALER) |
#define | IS_SPI_FIRST_BIT(BIT) |
#define | IS_SPI_TIMODE(MODE) |
#define | IS_SPI_CRC_CALCULATION(CALCULATION) |
#define | IS_SPI_CRC_LENGTH(LENGTH) |
#define | IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF) && (((POLYNOMIAL)&0x1) != 0)) |
Typedefs | |
typedef struct __SPI_HandleTypeDef | SPI_HandleTypeDef |
SPI handle Structure definition. More... | |
Enumerations | |
enum | HAL_SPI_StateTypeDef { HAL_SPI_STATE_RESET = 0x00U, HAL_SPI_STATE_READY = 0x01U, HAL_SPI_STATE_BUSY = 0x02U, HAL_SPI_STATE_BUSY_TX = 0x03U, HAL_SPI_STATE_BUSY_RX = 0x04U, HAL_SPI_STATE_BUSY_TX_RX = 0x05U, HAL_SPI_STATE_ERROR = 0x06U } |
HAL State structures definition. More... | |
Header file of SPI HAL module.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Definition in file stm32f7xx_hal_spi.h.