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stm32f7xx_hal_dfsdm.h
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1 
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F7xx_HAL_DFSDM_H
40 #define __STM32F7xx_HAL_DFSDM_H
41 
42 #ifdef __cplusplus
43  extern "C" {
44 #endif
45 
46 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
47 /* Includes ------------------------------------------------------------------*/
48 #include "stm32f7xx_hal_def.h"
49 
58 /* Exported types ------------------------------------------------------------*/
66 typedef enum
67 {
68  HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U,
69  HAL_DFSDM_CHANNEL_STATE_READY = 0x01U,
70  HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU
71 }HAL_DFSDM_Channel_StateTypeDef;
72 
76 typedef struct
77 {
78  FunctionalState Activation;
79  uint32_t Selection;
81  uint32_t Divider;
83 }DFSDM_Channel_OutputClockTypeDef;
84 
88 typedef struct
89 {
90  uint32_t Multiplexer;
92  uint32_t DataPacking;
94  uint32_t Pins;
96 }DFSDM_Channel_InputTypeDef;
97 
101 typedef struct
102 {
103  uint32_t Type;
105  uint32_t SpiClock;
107 }DFSDM_Channel_SerialInterfaceTypeDef;
108 
112 typedef struct
113 {
114  uint32_t FilterOrder;
116  uint32_t Oversampling;
118 }DFSDM_Channel_AwdTypeDef;
119 
123 typedef struct
124 {
125  DFSDM_Channel_OutputClockTypeDef OutputClock;
126  DFSDM_Channel_InputTypeDef Input;
127  DFSDM_Channel_SerialInterfaceTypeDef SerialInterface;
128  DFSDM_Channel_AwdTypeDef Awd;
129  int32_t Offset;
131  uint32_t RightBitShift;
133 }DFSDM_Channel_InitTypeDef;
134 
138 typedef struct
139 {
140  DFSDM_Channel_TypeDef *Instance;
141  DFSDM_Channel_InitTypeDef Init;
142  HAL_DFSDM_Channel_StateTypeDef State;
143 }DFSDM_Channel_HandleTypeDef;
144 
148 typedef enum
149 {
150  HAL_DFSDM_FILTER_STATE_RESET = 0x00U,
151  HAL_DFSDM_FILTER_STATE_READY = 0x01U,
152  HAL_DFSDM_FILTER_STATE_REG = 0x02U,
153  HAL_DFSDM_FILTER_STATE_INJ = 0x03U,
154  HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U,
155  HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU
156 }HAL_DFSDM_Filter_StateTypeDef;
157 
161 typedef struct
162 {
163  uint32_t Trigger;
165  FunctionalState FastMode;
166  FunctionalState DmaMode;
167 }DFSDM_Filter_RegularParamTypeDef;
168 
172 typedef struct
173 {
174  uint32_t Trigger;
176  FunctionalState ScanMode;
177  FunctionalState DmaMode;
178  uint32_t ExtTrigger;
180  uint32_t ExtTriggerEdge;
182 }DFSDM_Filter_InjectedParamTypeDef;
183 
187 typedef struct
188 {
189  uint32_t SincOrder;
191  uint32_t Oversampling;
193  uint32_t IntOversampling;
195 }DFSDM_Filter_FilterParamTypeDef;
196 
200 typedef struct
201 {
202  DFSDM_Filter_RegularParamTypeDef RegularParam;
203  DFSDM_Filter_InjectedParamTypeDef InjectedParam;
204  DFSDM_Filter_FilterParamTypeDef FilterParam;
205 }DFSDM_Filter_InitTypeDef;
206 
210 typedef struct
211 {
212  DFSDM_Filter_TypeDef *Instance;
213  DFSDM_Filter_InitTypeDef Init;
214  DMA_HandleTypeDef *hdmaReg;
215  DMA_HandleTypeDef *hdmaInj;
216  uint32_t RegularContMode;
217  uint32_t RegularTrigger;
218  uint32_t InjectedTrigger;
219  uint32_t ExtTriggerEdge;
220  FunctionalState InjectedScanMode;
221  uint32_t InjectedChannelsNbr;
222  uint32_t InjConvRemaining;
223  HAL_DFSDM_Filter_StateTypeDef State;
224  uint32_t ErrorCode;
225 }DFSDM_Filter_HandleTypeDef;
226 
230 typedef struct
231 {
232  uint32_t DataSource;
234  uint32_t Channel;
236  int32_t HighThreshold;
238  int32_t LowThreshold;
240  uint32_t HighBreakSignal;
242  uint32_t LowBreakSignal;
244 }DFSDM_Filter_AwdParamTypeDef;
245 
249 /* End of exported types -----------------------------------------------------*/
250 
251 /* Exported constants --------------------------------------------------------*/
259 #define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000U)
260 #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC
268 #define DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000U)
269 #define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1
277 #define DFSDM_CHANNEL_STANDARD_MODE ((uint32_t)0x00000000U)
278 #define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0
279 #define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1
287 #define DFSDM_CHANNEL_SAME_CHANNEL_PINS ((uint32_t)0x00000000U)
288 #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL
296 #define DFSDM_CHANNEL_SPI_RISING ((uint32_t)0x00000000U)
297 #define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0
298 #define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1
299 #define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP
307 #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL ((uint32_t)0x00000000U)
308 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0
309 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1
310 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL
318 #define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000U)
319 #define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0
320 #define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1
321 #define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD
329 #define DFSDM_FILTER_SW_TRIGGER ((uint32_t)0x00000000U)
330 #define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001U)
331 #define DFSDM_FILTER_EXT_TRIGGER ((uint32_t)0x00000002U)
339 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U)
340 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0
341 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1
342 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1)
343 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2
344 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2)
345 #define DFSDM_FILTER_EXT_TRIG_TIM10_OC1 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2)
346 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1 | \
347  DFSDM_FLTCR1_JEXTSEL_2)
348 #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3
349 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4)
350 #define DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_3 | \
351  DFSDM_FLTCR1_JEXTSEL_4)
352 #define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | \
353  DFSDM_FLTCR1_JEXTSEL_4)
361 #define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0
362 #define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1
363 #define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN
371 #define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000U)
372 #define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0
373 #define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1
374 #define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1)
375 #define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2
376 #define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2)
384 #define DFSDM_FILTER_AWD_FILTER_DATA ((uint32_t)0x00000000U)
385 #define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL
393 #define DFSDM_FILTER_ERROR_NONE ((uint32_t)0x00000000U)
394 #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001U)
395 #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002U)
396 #define DFSDM_FILTER_ERROR_DMA ((uint32_t)0x00000003U)
404 #define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000U)
405 #define DFSDM_BREAK_SIGNAL_0 ((uint32_t)0x00000001U)
406 #define DFSDM_BREAK_SIGNAL_1 ((uint32_t)0x00000002U)
407 #define DFSDM_BREAK_SIGNAL_2 ((uint32_t)0x00000004U)
408 #define DFSDM_BREAK_SIGNAL_3 ((uint32_t)0x00000008U)
416 /* DFSDM Channels ------------------------------------------------------------*/
417 /* The DFSDM channels are defined as follows:
418  - in 16-bit LSB the channel mask is set
419  - in 16-bit MSB the channel number is set
420  e.g. for channel 5 definition:
421  - the channel mask is 0x00000020 (bit 5 is set)
422  - the channel number 5 is 0x00050000
423  --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */
424 #define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U)
425 #define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U)
426 #define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U)
427 #define DFSDM_CHANNEL_3 ((uint32_t)0x00030008U)
428 #define DFSDM_CHANNEL_4 ((uint32_t)0x00040010U)
429 #define DFSDM_CHANNEL_5 ((uint32_t)0x00050020U)
430 #define DFSDM_CHANNEL_6 ((uint32_t)0x00060040U)
431 #define DFSDM_CHANNEL_7 ((uint32_t)0x00070080U)
432 
439 #define DFSDM_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000U)
440 #define DFSDM_CONTINUOUS_CONV_ON ((uint32_t)0x00000001U)
448 #define DFSDM_AWD_HIGH_THRESHOLD ((uint32_t)0x00000000U)
449 #define DFSDM_AWD_LOW_THRESHOLD ((uint32_t)0x00000001U)
457 /* End of exported constants -------------------------------------------------*/
458 
459 /* Exported macros -----------------------------------------------------------*/
468 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
469 
474 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
475 
479 /* End of exported macros ----------------------------------------------------*/
480 
481 /* Exported functions --------------------------------------------------------*/
489 /* Channel initialization and de-initialization functions *********************/
490 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
491 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
492 void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
493 void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
501 /* Channel operation functions ************************************************/
502 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
503 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
504 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
505 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
506 
507 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
508 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
509 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
510 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
511 
512 int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
513 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);
514 
515 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
516 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
517 
518 void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
519 void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
527 /* Channel state function *****************************************************/
528 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
536 /* Filter initialization and de-initialization functions *********************/
537 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
538 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
539 void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
540 void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
548 /* Filter control functions *********************/
549 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
550  uint32_t Channel,
551  uint32_t ContinuousMode);
552 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
553  uint32_t Channel);
561 /* Filter operation functions *********************/
562 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
563 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
564 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
565 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
566 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
567 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
568 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
569 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
570 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
571 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
572 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
573 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
574 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
575 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
576 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
577  DFSDM_Filter_AwdParamTypeDef* awdParam);
578 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
579 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);
580 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
581 
582 int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
583 int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
584 int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
585 int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
586 uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
587 
588 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
589 
590 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
591 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
592 
593 void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
594 void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
595 void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
596 void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
597 void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
598 void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
606 /* Filter state functions *****************************************************/
607 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
608 uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
616 /* End of exported functions -------------------------------------------------*/
617 
618 /* Private macros ------------------------------------------------------------*/
622 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \
623  ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))
624 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256))
625 #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
626  ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
627 #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \
628  ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \
629  ((MODE) == DFSDM_CHANNEL_DUAL_MODE))
630 #define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \
631  ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))
632 #define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \
633  ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \
634  ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \
635  ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))
636 #define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \
637  ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \
638  ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \
639  ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))
640 #define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \
641  ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \
642  ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \
643  ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))
644 #define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 32))
645 #define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
646 #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1F)
647 #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFF)
648 #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
649  ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))
650 #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
651  ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
652  ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))
653 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
654  ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2)|| \
655  ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
656  ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2)|| \
657  ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
658  ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
659  ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \
660  ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
661  ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \
662  ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
663  ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) ||\
664  ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT))
665 #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \
666  ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \
667  ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))
668 #define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \
669  ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \
670  ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \
671  ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \
672  ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \
673  ((ORDER) == DFSDM_FILTER_SINC5_ORDER))
674 #define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 1024))
675 #define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 256))
676 #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \
677  ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))
678 #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
679 #define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xFU)
680 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \
681  ((CHANNEL) == DFSDM_CHANNEL_1) || \
682  ((CHANNEL) == DFSDM_CHANNEL_2) || \
683  ((CHANNEL) == DFSDM_CHANNEL_3) || \
684  ((CHANNEL) == DFSDM_CHANNEL_4) || \
685  ((CHANNEL) == DFSDM_CHANNEL_5) || \
686  ((CHANNEL) == DFSDM_CHANNEL_6) || \
687  ((CHANNEL) == DFSDM_CHANNEL_7))
688 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FFU))
689 #define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \
690  ((MODE) == DFSDM_CONTINUOUS_CONV_ON))
691 
694 /* End of private macros -----------------------------------------------------*/
695 
703 #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
704 #ifdef __cplusplus
705 }
706 #endif
707 
708 #endif /* __STM32F7xx_HAL_DFSDM_H */
709 
710 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
FunctionalState
FunctionalState
Definition: stm32f7xx.h:158
DFSDM_Filter_TypeDef
DFSDM module registers.
Definition: stm32f765xx.h:367
DFSDM_Channel_TypeDef
DFSDM channel configuration registers.
Definition: stm32f765xx.h:389
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition: stm32f7xx_hal_dma.h:156
stm32f7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_DFSDM_FilterRegConvHalfCpltCallback
void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Half regular conversion complete callback.
Definition: stm32f769i_discovery_audio.c:1517
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32f7xx_hal_def.h:56
HAL_DFSDM_FilterRegConvCpltCallback
void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Regular conversion complete callback.
Definition: stm32f769i_discovery_audio.c:1441
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