STM32F769IDiscovery  1.00
uDANTE Audio Networking with STM32F7 DISCO board
stm32f7xx_hal_cryp.c
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1 
100 /* Includes ------------------------------------------------------------------*/
101 #include "stm32f7xx_hal.h"
102 
106 #if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
107 
113 #ifdef HAL_CRYP_MODULE_ENABLED
114 
115 /* Private typedef -----------------------------------------------------------*/
116 /* Private define ------------------------------------------------------------*/
120 #define CRYP_TIMEOUT_VALUE 1
121 
125 /* Private macro -------------------------------------------------------------*/
126 /* Private variables ---------------------------------------------------------*/
127 /* Private function prototypes -----------------------------------------------*/
131 static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize);
132 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize);
133 static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
134 static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
135 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
136 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
137 static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
138 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
139 static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
140 static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
141 static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
142 static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
146 /* Private functions ---------------------------------------------------------*/
147 
157 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
158 {
159  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
160 
161  /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
162  in the DMACR register */
163  hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
164 
165  /* Call input data transfer complete callback */
166  HAL_CRYP_InCpltCallback(hcryp);
167 }
168 
174 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
175 {
176  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
177 
178  /* Disable the DMA transfer for output FIFO request by resetting the DOEN bit
179  in the DMACR register */
180  hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
181 
182  /* Disable CRYP */
183  __HAL_CRYP_DISABLE(hcryp);
184 
185  /* Change the CRYP state to ready */
186  hcryp->State = HAL_CRYP_STATE_READY;
187 
188  /* Call output data transfer complete callback */
189  HAL_CRYP_OutCpltCallback(hcryp);
190 }
191 
197 static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
198 {
199  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
200  hcryp->State= HAL_CRYP_STATE_READY;
201  HAL_CRYP_ErrorCallback(hcryp);
202 }
203 
212 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize)
213 {
214  uint32_t keyaddr = (uint32_t)Key;
215 
216  switch(KeySize)
217  {
218  case CRYP_KEYSIZE_256B:
219  /* Key Initialisation */
220  hcryp->Instance->K0LR = __REV(*(uint32_t*)(keyaddr));
221  keyaddr+=4;
222  hcryp->Instance->K0RR = __REV(*(uint32_t*)(keyaddr));
223  keyaddr+=4;
224  hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
225  keyaddr+=4;
226  hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
227  keyaddr+=4;
228  hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
229  keyaddr+=4;
230  hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
231  keyaddr+=4;
232  hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
233  keyaddr+=4;
234  hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
235  break;
236  case CRYP_KEYSIZE_192B:
237  hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
238  keyaddr+=4;
239  hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
240  keyaddr+=4;
241  hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
242  keyaddr+=4;
243  hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
244  keyaddr+=4;
245  hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
246  keyaddr+=4;
247  hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
248  break;
249  case CRYP_KEYSIZE_128B:
250  hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
251  keyaddr+=4;
252  hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
253  keyaddr+=4;
254  hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
255  keyaddr+=4;
256  hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
257  break;
258  default:
259  break;
260  }
261 }
262 
271 static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize)
272 {
273  uint32_t ivaddr = (uint32_t)InitVector;
274 
275  switch(IVSize)
276  {
277  case CRYP_KEYSIZE_128B:
278  hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
279  ivaddr+=4;
280  hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
281  ivaddr+=4;
282  hcryp->Instance->IV1LR = __REV(*(uint32_t*)(ivaddr));
283  ivaddr+=4;
284  hcryp->Instance->IV1RR = __REV(*(uint32_t*)(ivaddr));
285  break;
286  /* Whatever key size 192 or 256, Init vector is written in IV0LR and IV0RR */
287  case CRYP_KEYSIZE_192B:
288  hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
289  ivaddr+=4;
290  hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
291  break;
292  case CRYP_KEYSIZE_256B:
293  hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
294  ivaddr+=4;
295  hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
296  break;
297  default:
298  break;
299  }
300 }
301 
312 static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
313 {
314  uint32_t tickstart = 0;
315 
316  uint32_t i = 0;
317  uint32_t inputaddr = (uint32_t)Input;
318  uint32_t outputaddr = (uint32_t)Output;
319 
320  for(i=0; (i < Ilength); i+=16)
321  {
322  /* Write the Input block in the IN FIFO */
323  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
324  inputaddr+=4;
325  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
326  inputaddr+=4;
327  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
328  inputaddr+=4;
329  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
330  inputaddr+=4;
331 
332  /* Get tick */
333  tickstart = HAL_GetTick();
334 
335  while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
336  {
337  /* Check for the Timeout */
338  if(Timeout != HAL_MAX_DELAY)
339  {
340  if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
341  {
342  /* Change state */
343  hcryp->State = HAL_CRYP_STATE_TIMEOUT;
344 
345  /* Process Unlocked */
346  __HAL_UNLOCK(hcryp);
347 
348  return HAL_TIMEOUT;
349  }
350  }
351  }
352  /* Read the Output block from the Output FIFO */
353  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
354  outputaddr+=4;
355  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
356  outputaddr+=4;
357  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
358  outputaddr+=4;
359  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
360  outputaddr+=4;
361  }
362  /* Return function status */
363  return HAL_OK;
364 }
365 
376 static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
377 {
378  uint32_t tickstart = 0;
379 
380  uint32_t i = 0;
381  uint32_t inputaddr = (uint32_t)Input;
382  uint32_t outputaddr = (uint32_t)Output;
383 
384  for(i=0; (i < Ilength); i+=8)
385  {
386  /* Write the Input block in the IN FIFO */
387  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
388  inputaddr+=4;
389  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
390  inputaddr+=4;
391 
392  /* Get tick */
393  tickstart = HAL_GetTick();
394 
395  while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
396  {
397  /* Check for the Timeout */
398  if(Timeout != HAL_MAX_DELAY)
399  {
400  if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
401  {
402  /* Change state */
403  hcryp->State = HAL_CRYP_STATE_TIMEOUT;
404 
405  /* Process Unlocked */
406  __HAL_UNLOCK(hcryp);
407 
408  return HAL_TIMEOUT;
409  }
410  }
411  }
412  /* Read the Output block from the Output FIFO */
413  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
414  outputaddr+=4;
415  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
416  outputaddr+=4;
417  }
418  /* Return function status */
419  return HAL_OK;
420 }
421 
431 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
432 {
433  /* Set the CRYP DMA transfer complete callback */
434  hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
435  /* Set the DMA error callback */
436  hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
437 
438  /* Set the CRYP DMA transfer complete callback */
439  hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
440  /* Set the DMA error callback */
441  hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
442 
443  /* Enable CRYP */
444  __HAL_CRYP_ENABLE(hcryp);
445 
446  /* Enable the DMA In DMA Stream */
447  HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DR, Size/4);
448 
449  /* Enable In DMA request */
450  hcryp->Instance->DMACR = (CRYP_DMACR_DIEN);
451 
452  /* Enable the DMA Out DMA Stream */
453  HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size/4);
454 
455  /* Enable Out DMA request */
456  hcryp->Instance->DMACR |= CRYP_DMACR_DOEN;
457 
458 }
459 
467 static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
468 {
469  /* Check if initialization phase has already been performed */
470  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
471  {
472  /* Set the CRYP peripheral in AES ECB mode */
473  __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_DES_ECB | Direction);
474 
475  /* Set the key */
476  hcryp->Instance->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
477  hcryp->Instance->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));
478 
479  /* Flush FIFO */
480  __HAL_CRYP_FIFO_FLUSH(hcryp);
481 
482  /* Set the phase */
483  hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
484  }
485 }
486 
494 static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
495 {
496  /* Check if initialization phase has already been performed */
497  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
498  {
499  /* Set the CRYP peripheral in AES ECB mode */
500  __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_DES_CBC | Direction);
501 
502  /* Set the key */
503  hcryp->Instance->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
504  hcryp->Instance->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));
505 
506  /* Set the Initialization Vector */
507  CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);
508 
509  /* Flush FIFO */
510  __HAL_CRYP_FIFO_FLUSH(hcryp);
511 
512  /* Set the phase */
513  hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
514  }
515 }
516 
524 static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
525 {
526  /* Check if initialization phase has already been performed */
527  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
528  {
529  /* Set the CRYP peripheral in AES ECB mode */
530  __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_TDES_ECB | Direction);
531 
532  /* Set the key */
533  CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);
534 
535  /* Flush FIFO */
536  __HAL_CRYP_FIFO_FLUSH(hcryp);
537 
538  /* Set the phase */
539  hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
540  }
541 }
542 
550 static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
551 {
552  /* Check if initialization phase has already been performed */
553  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
554  {
555  /* Set the CRYP peripheral in AES CBC mode */
556  __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_TDES_CBC | Direction);
557 
558  /* Set the key */
559  CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);
560 
561  /* Set the Initialization Vector */
562  CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);
563 
564  /* Flush FIFO */
565  __HAL_CRYP_FIFO_FLUSH(hcryp);
566 
567  /* Set the phase */
568  hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
569  }
570 }
571 
576  /* Exported functions --------------------------------------------------------*/
606 HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
607 {
608  /* Check the CRYP handle allocation */
609  if(hcryp == NULL)
610  {
611  return HAL_ERROR;
612  }
613 
614  /* Check the parameters */
615  assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
616  assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
617 
618  if(hcryp->State == HAL_CRYP_STATE_RESET)
619  {
620  /* Allocate lock resource and initialize it */
621  hcryp->Lock = HAL_UNLOCKED;
622  /* Init the low level hardware */
623  HAL_CRYP_MspInit(hcryp);
624  }
625 
626  /* Change the CRYP state */
627  hcryp->State = HAL_CRYP_STATE_BUSY;
628 
629  /* Set the key size and data type*/
630  CRYP->CR = (uint32_t) (hcryp->Init.KeySize | hcryp->Init.DataType);
631 
632  /* Reset CrypInCount and CrypOutCount */
633  hcryp->CrypInCount = 0;
634  hcryp->CrypOutCount = 0;
635 
636  /* Change the CRYP state */
637  hcryp->State = HAL_CRYP_STATE_READY;
638 
639  /* Set the default CRYP phase */
640  hcryp->Phase = HAL_CRYP_PHASE_READY;
641 
642  /* Return function status */
643  return HAL_OK;
644 }
645 
652 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
653 {
654  /* Check the CRYP handle allocation */
655  if(hcryp == NULL)
656  {
657  return HAL_ERROR;
658  }
659 
660  /* Change the CRYP state */
661  hcryp->State = HAL_CRYP_STATE_BUSY;
662 
663  /* Set the default CRYP phase */
664  hcryp->Phase = HAL_CRYP_PHASE_READY;
665 
666  /* Reset CrypInCount and CrypOutCount */
667  hcryp->CrypInCount = 0;
668  hcryp->CrypOutCount = 0;
669 
670  /* Disable the CRYP Peripheral Clock */
671  __HAL_CRYP_DISABLE(hcryp);
672 
673  /* DeInit the low level hardware: CLOCK, NVIC.*/
674  HAL_CRYP_MspDeInit(hcryp);
675 
676  /* Change the CRYP state */
677  hcryp->State = HAL_CRYP_STATE_RESET;
678 
679  /* Release Lock */
680  __HAL_UNLOCK(hcryp);
681 
682  /* Return function status */
683  return HAL_OK;
684 }
685 
692 __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
693 {
694  /* Prevent unused argument(s) compilation warning */
695  UNUSED(hcryp);
696 
697  /* NOTE : This function Should not be modified, when the callback is needed,
698  the HAL_CRYP_MspInit could be implemented in the user file
699  */
700 }
701 
708 __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
709 {
710  /* Prevent unused argument(s) compilation warning */
711  UNUSED(hcryp);
712 
713  /* NOTE : This function Should not be modified, when the callback is needed,
714  the HAL_CRYP_MspDeInit could be implemented in the user file
715  */
716 }
717 
752 HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
753 {
754  /* Process Locked */
755  __HAL_LOCK(hcryp);
756 
757  /* Change the CRYP state */
758  hcryp->State = HAL_CRYP_STATE_BUSY;
759 
760  /* Check if initialization phase has already been performed */
761  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
762  {
763  /* Set the key */
764  CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
765 
766  /* Set the CRYP peripheral in AES ECB mode */
767  __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
768 
769  /* Flush FIFO */
770  __HAL_CRYP_FIFO_FLUSH(hcryp);
771 
772  /* Enable CRYP */
773  __HAL_CRYP_ENABLE(hcryp);
774 
775  /* Set the phase */
776  hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
777  }
778 
779  /* Write Plain Data and Get Cypher Data */
780  if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
781  {
782  return HAL_TIMEOUT;
783  }
784 
785  /* Change the CRYP state */
786  hcryp->State = HAL_CRYP_STATE_READY;
787 
788  /* Process Unlocked */
789  __HAL_UNLOCK(hcryp);
790 
791  /* Return function status */
792  return HAL_OK;
793 }
794 
806 HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
807 {
808  /* Process Locked */
809  __HAL_LOCK(hcryp);
810 
811  /* Change the CRYP state */
812  hcryp->State = HAL_CRYP_STATE_BUSY;
813 
814  /* Check if initialization phase has already been performed */
815  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
816  {
817  /* Set the key */
818  CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
819 
820  /* Set the CRYP peripheral in AES ECB mode */
821  __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
822 
823  /* Set the Initialization Vector */
824  CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
825 
826  /* Flush FIFO */
827  __HAL_CRYP_FIFO_FLUSH(hcryp);
828 
829  /* Enable CRYP */
830  __HAL_CRYP_ENABLE(hcryp);
831 
832  /* Set the phase */
833  hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
834  }
835 
836  /* Write Plain Data and Get Cypher Data */
837  if(CRYP_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)
838  {
839  return HAL_TIMEOUT;
840  }
841 
842  /* Change the CRYP state */
843  hcryp->State = HAL_CRYP_STATE_READY;
844 
845  /* Process Unlocked */
846  __HAL_UNLOCK(hcryp);
847 
848  /* Return function status */
849  return HAL_OK;
850 }
851 
863 HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
864 {
865  /* Process Locked */
866  __HAL_LOCK(hcryp);
867 
868  /* Change the CRYP state */
869  hcryp->State = HAL_CRYP_STATE_BUSY;
870 
871  /* Check if initialization phase has already been performed */
872  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
873  {
874  /* Set the key */
875  CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
876 
877  /* Set the CRYP peripheral in AES ECB mode */
878  __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
879 
880  /* Set the Initialization Vector */
881  CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
882 
883  /* Flush FIFO */
884  __HAL_CRYP_FIFO_FLUSH(hcryp);
885 
886  /* Enable CRYP */
887  __HAL_CRYP_ENABLE(hcryp);
888 
889  /* Set the phase */
890  hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
891  }
892 
893  /* Write Plain Data and Get Cypher Data */
894  if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
895  {
896  return HAL_TIMEOUT;
897  }
898 
899  /* Change the CRYP state */
900  hcryp->State = HAL_CRYP_STATE_READY;
901 
902  /* Process Unlocked */
903  __HAL_UNLOCK(hcryp);
904 
905  /* Return function status */
906  return HAL_OK;
907 }
908 
909 
910 
922 HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
923 {
924  uint32_t tickstart = 0;
925 
926  /* Process Locked */
927  __HAL_LOCK(hcryp);
928 
929  /* Change the CRYP state */
930  hcryp->State = HAL_CRYP_STATE_BUSY;
931 
932  /* Check if initialization phase has already been performed */
933  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
934  {
935  /* Set the key */
936  CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
937 
938  /* Set the CRYP peripheral in AES Key mode */
939  __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
940 
941  /* Enable CRYP */
942  __HAL_CRYP_ENABLE(hcryp);
943 
944  /* Get tick */
945  tickstart = HAL_GetTick();
946 
947  while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
948  {
949  /* Check for the Timeout */
950  if(Timeout != HAL_MAX_DELAY)
951  {
952  if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
953  {
954  /* Change state */
955  hcryp->State = HAL_CRYP_STATE_TIMEOUT;
956 
957  /* Process Unlocked */
958  __HAL_UNLOCK(hcryp);
959 
960  return HAL_TIMEOUT;
961  }
962  }
963  }
964 
965  /* Disable CRYP */
966  __HAL_CRYP_DISABLE(hcryp);
967 
968  /* Reset the ALGOMODE bits*/
969  CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
970 
971  /* Set the CRYP peripheral in AES ECB decryption mode */
972  __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
973  /* Flush FIFO */
974  __HAL_CRYP_FIFO_FLUSH(hcryp);
975 
976  /* Enable CRYP */
977  __HAL_CRYP_ENABLE(hcryp);
978 
979  /* Set the phase */
980  hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
981  }
982 
983  /* Write Plain Data and Get Cypher Data */
984  if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
985  {
986  return HAL_TIMEOUT;
987  }
988 
989  /* Change the CRYP state */
990  hcryp->State = HAL_CRYP_STATE_READY;
991 
992  /* Process Unlocked */
993  __HAL_UNLOCK(hcryp);
994 
995  /* Return function status */
996  return HAL_OK;
997 }
998 
1010 HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
1011 {
1012  uint32_t tickstart = 0;
1013 
1014  /* Process Locked */
1015  __HAL_LOCK(hcryp);
1016 
1017  /* Change the CRYP state */
1018  hcryp->State = HAL_CRYP_STATE_BUSY;
1019 
1020  /* Check if initialization phase has already been performed */
1021  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1022  {
1023  /* Set the key */
1024  CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
1025 
1026  /* Set the CRYP peripheral in AES Key mode */
1027  __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
1028 
1029  /* Enable CRYP */
1030  __HAL_CRYP_ENABLE(hcryp);
1031 
1032  /* Get tick */
1033  tickstart = HAL_GetTick();
1034 
1035  while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
1036  {
1037  /* Check for the Timeout */
1038  if(Timeout != HAL_MAX_DELAY)
1039  {
1040  if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
1041  {
1042  /* Change state */
1043  hcryp->State = HAL_CRYP_STATE_TIMEOUT;
1044 
1045  /* Process Unlocked */
1046  __HAL_UNLOCK(hcryp);
1047 
1048  return HAL_TIMEOUT;
1049  }
1050  }
1051  }
1052 
1053  /* Reset the ALGOMODE bits*/
1054  CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
1055 
1056  /* Set the CRYP peripheral in AES CBC decryption mode */
1057  __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
1058 
1059  /* Set the Initialization Vector */
1060  CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
1061 
1062  /* Flush FIFO */
1063  __HAL_CRYP_FIFO_FLUSH(hcryp);
1064 
1065  /* Enable CRYP */
1066  __HAL_CRYP_ENABLE(hcryp);
1067 
1068  /* Set the phase */
1069  hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1070  }
1071 
1072  /* Write Plain Data and Get Cypher Data */
1073  if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
1074  {
1075  return HAL_TIMEOUT;
1076  }
1077 
1078  /* Change the CRYP state */
1079  hcryp->State = HAL_CRYP_STATE_READY;
1080 
1081  /* Process Unlocked */
1082  __HAL_UNLOCK(hcryp);
1083 
1084  /* Return function status */
1085  return HAL_OK;
1086 }
1087 
1099 HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
1100 {
1101  /* Process Locked */
1102  __HAL_LOCK(hcryp);
1103 
1104  /* Check if initialization phase has already been performed */
1105  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1106  {
1107  /* Change the CRYP state */
1108  hcryp->State = HAL_CRYP_STATE_BUSY;
1109 
1110  /* Set the key */
1111  CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
1112 
1113  /* Set the CRYP peripheral in AES CTR mode */
1114  __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
1115 
1116  /* Set the Initialization Vector */
1117  CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
1118 
1119  /* Flush FIFO */
1120  __HAL_CRYP_FIFO_FLUSH(hcryp);
1121 
1122  /* Enable CRYP */
1123  __HAL_CRYP_ENABLE(hcryp);
1124 
1125  /* Set the phase */
1126  hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1127  }
1128 
1129  /* Write Plain Data and Get Cypher Data */
1130  if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
1131  {
1132  return HAL_TIMEOUT;
1133  }
1134 
1135  /* Change the CRYP state */
1136  hcryp->State = HAL_CRYP_STATE_READY;
1137 
1138  /* Process Unlocked */
1139  __HAL_UNLOCK(hcryp);
1140 
1141  /* Return function status */
1142  return HAL_OK;
1143 }
1144 
1154 HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
1155 {
1156  uint32_t inputaddr;
1157  uint32_t outputaddr;
1158 
1159  if(hcryp->State == HAL_CRYP_STATE_READY)
1160  {
1161  /* Process Locked */
1162  __HAL_LOCK(hcryp);
1163 
1164  hcryp->CrypInCount = Size;
1165  hcryp->pCrypInBuffPtr = pPlainData;
1166  hcryp->pCrypOutBuffPtr = pCypherData;
1167  hcryp->CrypOutCount = Size;
1168 
1169  /* Change the CRYP state */
1170  hcryp->State = HAL_CRYP_STATE_BUSY;
1171 
1172  /* Check if initialization phase has already been performed */
1173  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1174  {
1175  /* Set the key */
1176  CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
1177 
1178  /* Set the CRYP peripheral in AES ECB mode */
1179  __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
1180 
1181  /* Flush FIFO */
1182  __HAL_CRYP_FIFO_FLUSH(hcryp);
1183 
1184  /* Set the phase */
1185  hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1186  }
1187 
1188  /* Enable Interrupts */
1189  __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
1190 
1191  /* Enable CRYP */
1192  __HAL_CRYP_ENABLE(hcryp);
1193 
1194  /* Return function status */
1195  return HAL_OK;
1196  }
1197  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
1198  {
1199  inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
1200  /* Write the Input block in the IN FIFO */
1201  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
1202  inputaddr+=4;
1203  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
1204  inputaddr+=4;
1205  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
1206  inputaddr+=4;
1207  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
1208  hcryp->pCrypInBuffPtr += 16;
1209  hcryp->CrypInCount -= 16;
1210  if(hcryp->CrypInCount == 0)
1211  {
1212  __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
1213  /* Call the Input data transfer complete callback */
1214  HAL_CRYP_InCpltCallback(hcryp);
1215  }
1216  }
1217  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
1218  {
1219  outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
1220  /* Read the Output block from the Output FIFO */
1221  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
1222  outputaddr+=4;
1223  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
1224  outputaddr+=4;
1225  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
1226  outputaddr+=4;
1227  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
1228  hcryp->pCrypOutBuffPtr += 16;
1229  hcryp->CrypOutCount -= 16;
1230  if(hcryp->CrypOutCount == 0)
1231  {
1232  __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
1233  /* Process Locked */
1234  __HAL_UNLOCK(hcryp);
1235  /* Change the CRYP state */
1236  hcryp->State = HAL_CRYP_STATE_READY;
1237  /* Call Input transfer complete callback */
1238  HAL_CRYP_OutCpltCallback(hcryp);
1239  }
1240  }
1241 
1242  /* Return function status */
1243  return HAL_OK;
1244 }
1245 
1255 HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
1256 {
1257  uint32_t inputaddr;
1258  uint32_t outputaddr;
1259 
1260  if(hcryp->State == HAL_CRYP_STATE_READY)
1261  {
1262  /* Process Locked */
1263  __HAL_LOCK(hcryp);
1264 
1265  hcryp->CrypInCount = Size;
1266  hcryp->pCrypInBuffPtr = pPlainData;
1267  hcryp->pCrypOutBuffPtr = pCypherData;
1268  hcryp->CrypOutCount = Size;
1269 
1270  /* Change the CRYP state */
1271  hcryp->State = HAL_CRYP_STATE_BUSY;
1272 
1273  /* Check if initialization phase has already been performed */
1274  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1275  {
1276  /* Set the key */
1277  CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
1278 
1279  /* Set the CRYP peripheral in AES CBC mode */
1280  __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
1281 
1282  /* Set the Initialization Vector */
1283  CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
1284 
1285  /* Flush FIFO */
1286  __HAL_CRYP_FIFO_FLUSH(hcryp);
1287 
1288  /* Set the phase */
1289  hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1290  }
1291  /* Enable Interrupts */
1292  __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
1293 
1294  /* Enable CRYP */
1295  __HAL_CRYP_ENABLE(hcryp);
1296 
1297  /* Return function status */
1298  return HAL_OK;
1299  }
1300  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
1301  {
1302  inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
1303  /* Write the Input block in the IN FIFO */
1304  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
1305  inputaddr+=4;
1306  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
1307  inputaddr+=4;
1308  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
1309  inputaddr+=4;
1310  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
1311  hcryp->pCrypInBuffPtr += 16;
1312  hcryp->CrypInCount -= 16;
1313  if(hcryp->CrypInCount == 0)
1314  {
1315  __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
1316  /* Call the Input data transfer complete callback */
1317  HAL_CRYP_InCpltCallback(hcryp);
1318  }
1319  }
1320  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
1321  {
1322  outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
1323  /* Read the Output block from the Output FIFO */
1324  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
1325  outputaddr+=4;
1326  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
1327  outputaddr+=4;
1328  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
1329  outputaddr+=4;
1330  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
1331  hcryp->pCrypOutBuffPtr += 16;
1332  hcryp->CrypOutCount -= 16;
1333  if(hcryp->CrypOutCount == 0)
1334  {
1335  __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
1336  /* Process Locked */
1337  __HAL_UNLOCK(hcryp);
1338  /* Change the CRYP state */
1339  hcryp->State = HAL_CRYP_STATE_READY;
1340  /* Call Input transfer complete callback */
1341  HAL_CRYP_OutCpltCallback(hcryp);
1342  }
1343  }
1344 
1345  /* Return function status */
1346  return HAL_OK;
1347 }
1348 
1358 HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
1359 {
1360  uint32_t inputaddr;
1361  uint32_t outputaddr;
1362 
1363  if(hcryp->State == HAL_CRYP_STATE_READY)
1364  {
1365  /* Process Locked */
1366  __HAL_LOCK(hcryp);
1367 
1368  hcryp->CrypInCount = Size;
1369  hcryp->pCrypInBuffPtr = pPlainData;
1370  hcryp->pCrypOutBuffPtr = pCypherData;
1371  hcryp->CrypOutCount = Size;
1372 
1373  /* Change the CRYP state */
1374  hcryp->State = HAL_CRYP_STATE_BUSY;
1375 
1376  /* Check if initialization phase has already been performed */
1377  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1378  {
1379  /* Set the key */
1380  CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
1381 
1382  /* Set the CRYP peripheral in AES CTR mode */
1383  __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
1384 
1385  /* Set the Initialization Vector */
1386  CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
1387 
1388  /* Flush FIFO */
1389  __HAL_CRYP_FIFO_FLUSH(hcryp);
1390 
1391  /* Set the phase */
1392  hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1393  }
1394  /* Enable Interrupts */
1395  __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
1396 
1397  /* Enable CRYP */
1398  __HAL_CRYP_ENABLE(hcryp);
1399 
1400  /* Return function status */
1401  return HAL_OK;
1402  }
1403  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
1404  {
1405  inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
1406  /* Write the Input block in the IN FIFO */
1407  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
1408  inputaddr+=4;
1409  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
1410  inputaddr+=4;
1411  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
1412  inputaddr+=4;
1413  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
1414  hcryp->pCrypInBuffPtr += 16;
1415  hcryp->CrypInCount -= 16;
1416  if(hcryp->CrypInCount == 0)
1417  {
1418  __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
1419  /* Call the Input data transfer complete callback */
1420  HAL_CRYP_InCpltCallback(hcryp);
1421  }
1422  }
1423  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
1424  {
1425  outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
1426  /* Read the Output block from the Output FIFO */
1427  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
1428  outputaddr+=4;
1429  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
1430  outputaddr+=4;
1431  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
1432  outputaddr+=4;
1433  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
1434  hcryp->pCrypOutBuffPtr += 16;
1435  hcryp->CrypOutCount -= 16;
1436  if(hcryp->CrypOutCount == 0)
1437  {
1438  __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
1439  /* Process Unlocked */
1440  __HAL_UNLOCK(hcryp);
1441  /* Change the CRYP state */
1442  hcryp->State = HAL_CRYP_STATE_READY;
1443  /* Call Input transfer complete callback */
1444  HAL_CRYP_OutCpltCallback(hcryp);
1445  }
1446  }
1447 
1448  /* Return function status */
1449  return HAL_OK;
1450 }
1451 
1452 
1462 HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
1463 {
1464  uint32_t tickstart = 0;
1465 
1466  uint32_t inputaddr;
1467  uint32_t outputaddr;
1468 
1469  if(hcryp->State == HAL_CRYP_STATE_READY)
1470  {
1471  /* Process Locked */
1472  __HAL_LOCK(hcryp);
1473 
1474  hcryp->CrypInCount = Size;
1475  hcryp->pCrypInBuffPtr = pCypherData;
1476  hcryp->pCrypOutBuffPtr = pPlainData;
1477  hcryp->CrypOutCount = Size;
1478 
1479  /* Change the CRYP state */
1480  hcryp->State = HAL_CRYP_STATE_BUSY;
1481 
1482  /* Check if initialization phase has already been performed */
1483  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1484  {
1485  /* Set the key */
1486  CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
1487 
1488  /* Set the CRYP peripheral in AES Key mode */
1489  __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
1490  /* Enable CRYP */
1491  __HAL_CRYP_ENABLE(hcryp);
1492 
1493  /* Get tick */
1494  tickstart = HAL_GetTick();
1495 
1496  while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
1497  {
1498  /* Check for the Timeout */
1499  if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
1500  {
1501  /* Change state */
1502  hcryp->State = HAL_CRYP_STATE_TIMEOUT;
1503 
1504  /* Process Unlocked */
1505  __HAL_UNLOCK(hcryp);
1506 
1507  return HAL_TIMEOUT;
1508  }
1509  }
1510 
1511  /* Reset the ALGOMODE bits*/
1512  CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
1513 
1514  /* Set the CRYP peripheral in AES ECB decryption mode */
1515  __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
1516 
1517  /* Flush FIFO */
1518  __HAL_CRYP_FIFO_FLUSH(hcryp);
1519 
1520  /* Set the phase */
1521  hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1522  }
1523 
1524  /* Enable Interrupts */
1525  __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
1526 
1527  /* Enable CRYP */
1528  __HAL_CRYP_ENABLE(hcryp);
1529 
1530  /* Return function status */
1531  return HAL_OK;
1532  }
1533  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
1534  {
1535  inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
1536  /* Write the Input block in the IN FIFO */
1537  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
1538  inputaddr+=4;
1539  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
1540  inputaddr+=4;
1541  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
1542  inputaddr+=4;
1543  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
1544  hcryp->pCrypInBuffPtr += 16;
1545  hcryp->CrypInCount -= 16;
1546  if(hcryp->CrypInCount == 0)
1547  {
1548  __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
1549  /* Call the Input data transfer complete callback */
1550  HAL_CRYP_InCpltCallback(hcryp);
1551  }
1552  }
1553  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
1554  {
1555  outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
1556  /* Read the Output block from the Output FIFO */
1557  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
1558  outputaddr+=4;
1559  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
1560  outputaddr+=4;
1561  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
1562  outputaddr+=4;
1563  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
1564  hcryp->pCrypOutBuffPtr += 16;
1565  hcryp->CrypOutCount -= 16;
1566  if(hcryp->CrypOutCount == 0)
1567  {
1568  __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
1569  /* Process Unlocked */
1570  __HAL_UNLOCK(hcryp);
1571  /* Change the CRYP state */
1572  hcryp->State = HAL_CRYP_STATE_READY;
1573  /* Call Input transfer complete callback */
1574  HAL_CRYP_OutCpltCallback(hcryp);
1575  }
1576  }
1577 
1578  /* Return function status */
1579  return HAL_OK;
1580 }
1581 
1591 HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
1592 {
1593 
1594  uint32_t tickstart = 0;
1595  uint32_t inputaddr;
1596  uint32_t outputaddr;
1597 
1598  if(hcryp->State == HAL_CRYP_STATE_READY)
1599  {
1600  /* Process Locked */
1601  __HAL_LOCK(hcryp);
1602 
1603  /* Get the buffer addresses and sizes */
1604  hcryp->CrypInCount = Size;
1605  hcryp->pCrypInBuffPtr = pCypherData;
1606  hcryp->pCrypOutBuffPtr = pPlainData;
1607  hcryp->CrypOutCount = Size;
1608 
1609  /* Change the CRYP state */
1610  hcryp->State = HAL_CRYP_STATE_BUSY;
1611 
1612  /* Check if initialization phase has already been performed */
1613  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1614  {
1615  /* Set the key */
1616  CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
1617 
1618  /* Set the CRYP peripheral in AES Key mode */
1619  __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
1620 
1621  /* Enable CRYP */
1622  __HAL_CRYP_ENABLE(hcryp);
1623 
1624  /* Get tick */
1625  tickstart = HAL_GetTick();
1626 
1627  while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
1628  {
1629  /* Check for the Timeout */
1630  if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
1631  {
1632  /* Change state */
1633  hcryp->State = HAL_CRYP_STATE_TIMEOUT;
1634 
1635  /* Process Unlocked */
1636  __HAL_UNLOCK(hcryp);
1637 
1638  return HAL_TIMEOUT;
1639  }
1640  }
1641 
1642  /* Reset the ALGOMODE bits*/
1643  CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
1644 
1645  /* Set the CRYP peripheral in AES CBC decryption mode */
1646  __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
1647 
1648  /* Set the Initialization Vector */
1649  CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
1650 
1651  /* Flush FIFO */
1652  __HAL_CRYP_FIFO_FLUSH(hcryp);
1653 
1654  /* Enable CRYP */
1655  __HAL_CRYP_ENABLE(hcryp);
1656 
1657  /* Set the phase */
1658  hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1659  }
1660 
1661  /* Enable Interrupts */
1662  __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
1663 
1664  /* Enable CRYP */
1665  __HAL_CRYP_ENABLE(hcryp);
1666 
1667  /* Return function status */
1668  return HAL_OK;
1669  }
1670  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
1671  {
1672  inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
1673  /* Write the Input block in the IN FIFO */
1674  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
1675  inputaddr+=4;
1676  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
1677  inputaddr+=4;
1678  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
1679  inputaddr+=4;
1680  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
1681  hcryp->pCrypInBuffPtr += 16;
1682  hcryp->CrypInCount -= 16;
1683  if(hcryp->CrypInCount == 0)
1684  {
1685  __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
1686  /* Call the Input data transfer complete callback */
1687  HAL_CRYP_InCpltCallback(hcryp);
1688  }
1689  }
1690  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
1691  {
1692  outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
1693  /* Read the Output block from the Output FIFO */
1694  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
1695  outputaddr+=4;
1696  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
1697  outputaddr+=4;
1698  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
1699  outputaddr+=4;
1700  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
1701  hcryp->pCrypOutBuffPtr += 16;
1702  hcryp->CrypOutCount -= 16;
1703  if(hcryp->CrypOutCount == 0)
1704  {
1705  __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
1706  /* Process Unlocked */
1707  __HAL_UNLOCK(hcryp);
1708  /* Change the CRYP state */
1709  hcryp->State = HAL_CRYP_STATE_READY;
1710  /* Call Input transfer complete callback */
1711  HAL_CRYP_OutCpltCallback(hcryp);
1712  }
1713  }
1714 
1715  /* Return function status */
1716  return HAL_OK;
1717 }
1718 
1728 HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
1729 {
1730  uint32_t inputaddr;
1731  uint32_t outputaddr;
1732 
1733  if(hcryp->State == HAL_CRYP_STATE_READY)
1734  {
1735  /* Process Locked */
1736  __HAL_LOCK(hcryp);
1737 
1738  /* Get the buffer addresses and sizes */
1739  hcryp->CrypInCount = Size;
1740  hcryp->pCrypInBuffPtr = pCypherData;
1741  hcryp->pCrypOutBuffPtr = pPlainData;
1742  hcryp->CrypOutCount = Size;
1743 
1744  /* Change the CRYP state */
1745  hcryp->State = HAL_CRYP_STATE_BUSY;
1746 
1747  /* Check if initialization phase has already been performed */
1748  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1749  {
1750  /* Set the key */
1751  CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
1752 
1753  /* Set the CRYP peripheral in AES CTR mode */
1754  __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
1755 
1756  /* Set the Initialization Vector */
1757  CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
1758 
1759  /* Flush FIFO */
1760  __HAL_CRYP_FIFO_FLUSH(hcryp);
1761 
1762  /* Set the phase */
1763  hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1764  }
1765 
1766  /* Enable Interrupts */
1767  __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
1768 
1769  /* Enable CRYP */
1770  __HAL_CRYP_ENABLE(hcryp);
1771 
1772  /* Return function status */
1773  return HAL_OK;
1774  }
1775  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
1776  {
1777  inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
1778  /* Write the Input block in the IN FIFO */
1779  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
1780  inputaddr+=4;
1781  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
1782  inputaddr+=4;
1783  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
1784  inputaddr+=4;
1785  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
1786  hcryp->pCrypInBuffPtr += 16;
1787  hcryp->CrypInCount -= 16;
1788  if(hcryp->CrypInCount == 0)
1789  {
1790  __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
1791  /* Call the Input data transfer complete callback */
1792  HAL_CRYP_InCpltCallback(hcryp);
1793  }
1794  }
1795  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
1796  {
1797  outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
1798  /* Read the Output block from the Output FIFO */
1799  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
1800  outputaddr+=4;
1801  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
1802  outputaddr+=4;
1803  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
1804  outputaddr+=4;
1805  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
1806  hcryp->pCrypOutBuffPtr += 16;
1807  hcryp->CrypOutCount -= 16;
1808  if(hcryp->CrypOutCount == 0)
1809  {
1810  __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
1811  /* Process Unlocked */
1812  __HAL_UNLOCK(hcryp);
1813  /* Change the CRYP state */
1814  hcryp->State = HAL_CRYP_STATE_READY;
1815  /* Call Input transfer complete callback */
1816  HAL_CRYP_OutCpltCallback(hcryp);
1817  }
1818  }
1819 
1820  /* Return function status */
1821  return HAL_OK;
1822 }
1823 
1833 HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
1834 {
1835  uint32_t inputaddr;
1836  uint32_t outputaddr;
1837 
1838  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
1839  {
1840  /* Process Locked */
1841  __HAL_LOCK(hcryp);
1842 
1843  inputaddr = (uint32_t)pPlainData;
1844  outputaddr = (uint32_t)pCypherData;
1845 
1846  /* Change the CRYP state */
1847  hcryp->State = HAL_CRYP_STATE_BUSY;
1848 
1849  /* Check if initialization phase has already been performed */
1850  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1851  {
1852  /* Set the key */
1853  CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
1854 
1855  /* Set the CRYP peripheral in AES ECB mode */
1856  __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
1857 
1858  /* Flush FIFO */
1859  __HAL_CRYP_FIFO_FLUSH(hcryp);
1860 
1861  /* Set the phase */
1862  hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1863  }
1864  /* Set the input and output addresses and start DMA transfer */
1865  CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
1866 
1867  /* Process Unlocked */
1868  __HAL_UNLOCK(hcryp);
1869 
1870  /* Return function status */
1871  return HAL_OK;
1872  }
1873  else
1874  {
1875  return HAL_ERROR;
1876  }
1877 }
1878 
1888 HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
1889 {
1890  uint32_t inputaddr;
1891  uint32_t outputaddr;
1892 
1893  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
1894  {
1895  /* Process Locked */
1896  __HAL_LOCK(hcryp);
1897 
1898  inputaddr = (uint32_t)pPlainData;
1899  outputaddr = (uint32_t)pCypherData;
1900 
1901  /* Change the CRYP state */
1902  hcryp->State = HAL_CRYP_STATE_BUSY;
1903 
1904  /* Check if initialization phase has already been performed */
1905  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1906  {
1907  /* Set the key */
1908  CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
1909 
1910  /* Set the CRYP peripheral in AES ECB mode */
1911  __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
1912 
1913  /* Set the Initialization Vector */
1914  CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
1915 
1916  /* Flush FIFO */
1917  __HAL_CRYP_FIFO_FLUSH(hcryp);
1918 
1919  /* Set the phase */
1920  hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1921  }
1922  /* Set the input and output addresses and start DMA transfer */
1923  CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
1924 
1925  /* Process Unlocked */
1926  __HAL_UNLOCK(hcryp);
1927 
1928  /* Return function status */
1929  return HAL_OK;
1930  }
1931  else
1932  {
1933  return HAL_ERROR;
1934  }
1935 }
1936 
1946 HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
1947 {
1948  uint32_t inputaddr;
1949  uint32_t outputaddr;
1950 
1951  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
1952  {
1953  /* Process Locked */
1954  __HAL_LOCK(hcryp);
1955 
1956  inputaddr = (uint32_t)pPlainData;
1957  outputaddr = (uint32_t)pCypherData;
1958 
1959  /* Change the CRYP state */
1960  hcryp->State = HAL_CRYP_STATE_BUSY;
1961 
1962  /* Check if initialization phase has already been performed */
1963  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1964  {
1965  /* Set the key */
1966  CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
1967 
1968  /* Set the CRYP peripheral in AES ECB mode */
1969  __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
1970 
1971  /* Set the Initialization Vector */
1972  CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
1973 
1974  /* Flush FIFO */
1975  __HAL_CRYP_FIFO_FLUSH(hcryp);
1976 
1977  /* Set the phase */
1978  hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1979  }
1980 
1981  /* Set the input and output addresses and start DMA transfer */
1982  CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
1983 
1984  /* Process Unlocked */
1985  __HAL_UNLOCK(hcryp);
1986 
1987  /* Return function status */
1988  return HAL_OK;
1989  }
1990  else
1991  {
1992  return HAL_ERROR;
1993  }
1994 }
1995 
2005 HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
2006 {
2007  uint32_t tickstart = 0;
2008  uint32_t inputaddr;
2009  uint32_t outputaddr;
2010 
2011  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
2012  {
2013  /* Process Locked */
2014  __HAL_LOCK(hcryp);
2015 
2016  inputaddr = (uint32_t)pCypherData;
2017  outputaddr = (uint32_t)pPlainData;
2018 
2019  /* Change the CRYP state */
2020  hcryp->State = HAL_CRYP_STATE_BUSY;
2021 
2022  /* Check if initialization phase has already been performed */
2023  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
2024  {
2025  /* Set the key */
2026  CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
2027 
2028  /* Set the CRYP peripheral in AES Key mode */
2029  __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
2030 
2031  /* Enable CRYP */
2032  __HAL_CRYP_ENABLE(hcryp);
2033 
2034  /* Get tick */
2035  tickstart = HAL_GetTick();
2036 
2037  while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
2038  {
2039  /* Check for the Timeout */
2040  if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
2041  {
2042  /* Change state */
2043  hcryp->State = HAL_CRYP_STATE_TIMEOUT;
2044 
2045  /* Process Unlocked */
2046  __HAL_UNLOCK(hcryp);
2047 
2048  return HAL_TIMEOUT;
2049  }
2050  }
2051 
2052  /* Reset the ALGOMODE bits*/
2053  CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
2054 
2055  /* Set the CRYP peripheral in AES ECB decryption mode */
2056  __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
2057 
2058  /* Flush FIFO */
2059  __HAL_CRYP_FIFO_FLUSH(hcryp);
2060 
2061  /* Set the phase */
2062  hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
2063  }
2064 
2065  /* Set the input and output addresses and start DMA transfer */
2066  CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
2067 
2068  /* Process Unlocked */
2069  __HAL_UNLOCK(hcryp);
2070 
2071  /* Return function status */
2072  return HAL_OK;
2073  }
2074  else
2075  {
2076  return HAL_ERROR;
2077  }
2078 }
2079 
2089 HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
2090 {
2091  uint32_t tickstart = 0;
2092  uint32_t inputaddr;
2093  uint32_t outputaddr;
2094 
2095  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
2096  {
2097  /* Process Locked */
2098  __HAL_LOCK(hcryp);
2099 
2100  inputaddr = (uint32_t)pCypherData;
2101  outputaddr = (uint32_t)pPlainData;
2102 
2103  /* Change the CRYP state */
2104  hcryp->State = HAL_CRYP_STATE_BUSY;
2105 
2106  /* Check if initialization phase has already been performed */
2107  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
2108  {
2109  /* Set the key */
2110  CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
2111 
2112  /* Set the CRYP peripheral in AES Key mode */
2113  __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
2114 
2115  /* Enable CRYP */
2116  __HAL_CRYP_ENABLE(hcryp);
2117 
2118  /* Get tick */
2119  tickstart = HAL_GetTick();
2120 
2121  while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
2122  {
2123  /* Check for the Timeout */
2124  if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
2125  {
2126  /* Change state */
2127  hcryp->State = HAL_CRYP_STATE_TIMEOUT;
2128 
2129  /* Process Unlocked */
2130  __HAL_UNLOCK(hcryp);
2131 
2132  return HAL_TIMEOUT;
2133  }
2134  }
2135 
2136  /* Reset the ALGOMODE bits*/
2137  CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
2138 
2139  /* Set the CRYP peripheral in AES CBC decryption mode */
2140  __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
2141 
2142  /* Set the Initialization Vector */
2143  CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
2144 
2145  /* Flush FIFO */
2146  __HAL_CRYP_FIFO_FLUSH(hcryp);
2147 
2148  /* Set the phase */
2149  hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
2150  }
2151 
2152  /* Set the input and output addresses and start DMA transfer */
2153  CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
2154 
2155  /* Process Unlocked */
2156  __HAL_UNLOCK(hcryp);
2157 
2158  /* Return function status */
2159  return HAL_OK;
2160  }
2161  else
2162  {
2163  return HAL_ERROR;
2164  }
2165 }
2166 
2176 HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
2177 {
2178  uint32_t inputaddr;
2179  uint32_t outputaddr;
2180 
2181  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
2182  {
2183  /* Process Locked */
2184  __HAL_LOCK(hcryp);
2185 
2186  inputaddr = (uint32_t)pCypherData;
2187  outputaddr = (uint32_t)pPlainData;
2188 
2189  /* Change the CRYP state */
2190  hcryp->State = HAL_CRYP_STATE_BUSY;
2191 
2192  /* Check if initialization phase has already been performed */
2193  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
2194  {
2195  /* Set the key */
2196  CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
2197 
2198  /* Set the CRYP peripheral in AES CTR mode */
2199  __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
2200 
2201  /* Set the Initialization Vector */
2202  CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
2203 
2204  /* Flush FIFO */
2205  __HAL_CRYP_FIFO_FLUSH(hcryp);
2206 
2207  /* Set the phase */
2208  hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
2209  }
2210 
2211  /* Set the input and output addresses and start DMA transfer */
2212  CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
2213 
2214  /* Process Unlocked */
2215  __HAL_UNLOCK(hcryp);
2216 
2217  /* Return function status */
2218  return HAL_OK;
2219  }
2220  else
2221  {
2222  return HAL_ERROR;
2223  }
2224 }
2225 
2226 
2260 HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
2261 {
2262  /* Process Locked */
2263  __HAL_LOCK(hcryp);
2264 
2265  /* Change the CRYP state */
2266  hcryp->State = HAL_CRYP_STATE_BUSY;
2267 
2268  /* Set CRYP peripheral in DES ECB encryption mode */
2269  CRYP_SetDESECBMode(hcryp, 0);
2270 
2271  /* Enable CRYP */
2272  __HAL_CRYP_ENABLE(hcryp);
2273 
2274  /* Write Plain Data and Get Cypher Data */
2275  if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
2276  {
2277  return HAL_TIMEOUT;
2278  }
2279 
2280  /* Change the CRYP state */
2281  hcryp->State = HAL_CRYP_STATE_READY;
2282 
2283  /* Process Unlocked */
2284  __HAL_UNLOCK(hcryp);
2285 
2286  /* Return function status */
2287  return HAL_OK;
2288 }
2289 
2300 HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
2301 {
2302  /* Process Locked */
2303  __HAL_LOCK(hcryp);
2304 
2305  /* Change the CRYP state */
2306  hcryp->State = HAL_CRYP_STATE_BUSY;
2307 
2308  /* Set CRYP peripheral in DES ECB decryption mode */
2309  CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
2310 
2311  /* Enable CRYP */
2312  __HAL_CRYP_ENABLE(hcryp);
2313 
2314  /* Write Plain Data and Get Cypher Data */
2315  if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
2316  {
2317  return HAL_TIMEOUT;
2318  }
2319 
2320  /* Change the CRYP state */
2321  hcryp->State = HAL_CRYP_STATE_READY;
2322 
2323  /* Process Unlocked */
2324  __HAL_UNLOCK(hcryp);
2325 
2326  /* Return function status */
2327  return HAL_OK;
2328 }
2329 
2340 HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
2341 {
2342  /* Process Locked */
2343  __HAL_LOCK(hcryp);
2344 
2345  /* Change the CRYP state */
2346  hcryp->State = HAL_CRYP_STATE_BUSY;
2347 
2348  /* Set CRYP peripheral in DES CBC encryption mode */
2349  CRYP_SetDESCBCMode(hcryp, 0);
2350 
2351  /* Enable CRYP */
2352  __HAL_CRYP_ENABLE(hcryp);
2353 
2354  /* Write Plain Data and Get Cypher Data */
2355  if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
2356  {
2357  return HAL_TIMEOUT;
2358  }
2359 
2360  /* Change the CRYP state */
2361  hcryp->State = HAL_CRYP_STATE_READY;
2362 
2363  /* Process Unlocked */
2364  __HAL_UNLOCK(hcryp);
2365 
2366  /* Return function status */
2367  return HAL_OK;
2368 }
2369 
2380 HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
2381 {
2382  /* Process Locked */
2383  __HAL_LOCK(hcryp);
2384 
2385  /* Change the CRYP state */
2386  hcryp->State = HAL_CRYP_STATE_BUSY;
2387 
2388  /* Set CRYP peripheral in DES CBC decryption mode */
2389  CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
2390 
2391  /* Enable CRYP */
2392  __HAL_CRYP_ENABLE(hcryp);
2393 
2394  /* Write Plain Data and Get Cypher Data */
2395  if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
2396  {
2397  return HAL_TIMEOUT;
2398  }
2399 
2400  /* Change the CRYP state */
2401  hcryp->State = HAL_CRYP_STATE_READY;
2402 
2403  /* Process Unlocked */
2404  __HAL_UNLOCK(hcryp);
2405 
2406  /* Return function status */
2407  return HAL_OK;
2408 }
2409 
2419 HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
2420 {
2421  uint32_t inputaddr;
2422  uint32_t outputaddr;
2423 
2424  if(hcryp->State == HAL_CRYP_STATE_READY)
2425  {
2426  /* Process Locked */
2427  __HAL_LOCK(hcryp);
2428 
2429  hcryp->CrypInCount = Size;
2430  hcryp->pCrypInBuffPtr = pPlainData;
2431  hcryp->pCrypOutBuffPtr = pCypherData;
2432  hcryp->CrypOutCount = Size;
2433 
2434  /* Change the CRYP state */
2435  hcryp->State = HAL_CRYP_STATE_BUSY;
2436 
2437  /* Set CRYP peripheral in DES ECB encryption mode */
2438  CRYP_SetDESECBMode(hcryp, 0);
2439 
2440  /* Enable Interrupts */
2441  __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
2442 
2443  /* Enable CRYP */
2444  __HAL_CRYP_ENABLE(hcryp);
2445 
2446  /* Return function status */
2447  return HAL_OK;
2448  }
2449  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
2450  {
2451  inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
2452  /* Write the Input block in the IN FIFO */
2453  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
2454  inputaddr+=4;
2455  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
2456 
2457  hcryp->pCrypInBuffPtr += 8;
2458  hcryp->CrypInCount -= 8;
2459  if(hcryp->CrypInCount == 0)
2460  {
2461  __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
2462  /* Call the Input data transfer complete callback */
2463  HAL_CRYP_InCpltCallback(hcryp);
2464  }
2465  }
2466  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
2467  {
2468  outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
2469  /* Read the Output block from the Output FIFO */
2470  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
2471  outputaddr+=4;
2472  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
2473 
2474  hcryp->pCrypOutBuffPtr += 8;
2475  hcryp->CrypOutCount -= 8;
2476  if(hcryp->CrypOutCount == 0)
2477  {
2478  /* Disable IT */
2479  __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
2480  /* Disable CRYP */
2481  __HAL_CRYP_DISABLE(hcryp);
2482  /* Process Unlocked */
2483  __HAL_UNLOCK(hcryp);
2484  /* Change the CRYP state */
2485  hcryp->State = HAL_CRYP_STATE_READY;
2486  /* Call Input transfer complete callback */
2487  HAL_CRYP_OutCpltCallback(hcryp);
2488  }
2489  }
2490 
2491  /* Return function status */
2492  return HAL_OK;
2493 }
2494 
2504 HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
2505 {
2506  uint32_t inputaddr;
2507  uint32_t outputaddr;
2508 
2509  if(hcryp->State == HAL_CRYP_STATE_READY)
2510  {
2511  /* Process Locked */
2512  __HAL_LOCK(hcryp);
2513 
2514  hcryp->CrypInCount = Size;
2515  hcryp->pCrypInBuffPtr = pPlainData;
2516  hcryp->pCrypOutBuffPtr = pCypherData;
2517  hcryp->CrypOutCount = Size;
2518 
2519  /* Change the CRYP state */
2520  hcryp->State = HAL_CRYP_STATE_BUSY;
2521 
2522  /* Set CRYP peripheral in DES CBC encryption mode */
2523  CRYP_SetDESCBCMode(hcryp, 0);
2524 
2525  /* Enable Interrupts */
2526  __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
2527 
2528  /* Enable CRYP */
2529  __HAL_CRYP_ENABLE(hcryp);
2530 
2531  /* Return function status */
2532  return HAL_OK;
2533  }
2534 
2535  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
2536  {
2537  inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
2538  /* Write the Input block in the IN FIFO */
2539  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
2540  inputaddr+=4;
2541  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
2542 
2543  hcryp->pCrypInBuffPtr += 8;
2544  hcryp->CrypInCount -= 8;
2545  if(hcryp->CrypInCount == 0)
2546  {
2547  __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
2548  /* Call the Input data transfer complete callback */
2549  HAL_CRYP_InCpltCallback(hcryp);
2550  }
2551  }
2552  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
2553  {
2554  outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
2555  /* Read the Output block from the Output FIFO */
2556  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
2557  outputaddr+=4;
2558  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
2559 
2560  hcryp->pCrypOutBuffPtr += 8;
2561  hcryp->CrypOutCount -= 8;
2562  if(hcryp->CrypOutCount == 0)
2563  {
2564  /* Disable IT */
2565  __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
2566  /* Disable CRYP */
2567  __HAL_CRYP_DISABLE(hcryp);
2568  /* Process Unlocked */
2569  __HAL_UNLOCK(hcryp);
2570  /* Change the CRYP state */
2571  hcryp->State = HAL_CRYP_STATE_READY;
2572  /* Call Input transfer complete callback */
2573  HAL_CRYP_OutCpltCallback(hcryp);
2574  }
2575  }
2576 
2577  /* Return function status */
2578  return HAL_OK;
2579 }
2580 
2590 HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
2591 {
2592  uint32_t inputaddr;
2593  uint32_t outputaddr;
2594 
2595  if(hcryp->State == HAL_CRYP_STATE_READY)
2596  {
2597  /* Process Locked */
2598  __HAL_LOCK(hcryp);
2599 
2600  hcryp->CrypInCount = Size;
2601  hcryp->pCrypInBuffPtr = pCypherData;
2602  hcryp->pCrypOutBuffPtr = pPlainData;
2603  hcryp->CrypOutCount = Size;
2604 
2605  /* Change the CRYP state */
2606  hcryp->State = HAL_CRYP_STATE_BUSY;
2607 
2608  /* Set CRYP peripheral in DES ECB decryption mode */
2609  CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
2610 
2611  /* Enable Interrupts */
2612  __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
2613 
2614  /* Enable CRYP */
2615  __HAL_CRYP_ENABLE(hcryp);
2616 
2617  /* Return function status */
2618  return HAL_OK;
2619  }
2620  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
2621  {
2622  inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
2623  /* Write the Input block in the IN FIFO */
2624  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
2625  inputaddr+=4;
2626  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
2627 
2628  hcryp->pCrypInBuffPtr += 8;
2629  hcryp->CrypInCount -= 8;
2630  if(hcryp->CrypInCount == 0)
2631  {
2632  __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
2633  /* Call the Input data transfer complete callback */
2634  HAL_CRYP_InCpltCallback(hcryp);
2635  }
2636  }
2637  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
2638  {
2639  outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
2640  /* Read the Output block from the Output FIFO */
2641  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
2642  outputaddr+=4;
2643  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
2644 
2645  hcryp->pCrypOutBuffPtr += 8;
2646  hcryp->CrypOutCount -= 8;
2647  if(hcryp->CrypOutCount == 0)
2648  {
2649  /* Disable IT */
2650  __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
2651  /* Disable CRYP */
2652  __HAL_CRYP_DISABLE(hcryp);
2653  /* Process Unlocked */
2654  __HAL_UNLOCK(hcryp);
2655  /* Change the CRYP state */
2656  hcryp->State = HAL_CRYP_STATE_READY;
2657  /* Call Input transfer complete callback */
2658  HAL_CRYP_OutCpltCallback(hcryp);
2659  }
2660  }
2661 
2662  /* Return function status */
2663  return HAL_OK;
2664 }
2665 
2675 HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
2676 {
2677  uint32_t inputaddr;
2678  uint32_t outputaddr;
2679 
2680  if(hcryp->State == HAL_CRYP_STATE_READY)
2681  {
2682  /* Process Locked */
2683  __HAL_LOCK(hcryp);
2684 
2685  hcryp->CrypInCount = Size;
2686  hcryp->pCrypInBuffPtr = pCypherData;
2687  hcryp->pCrypOutBuffPtr = pPlainData;
2688  hcryp->CrypOutCount = Size;
2689 
2690  /* Change the CRYP state */
2691  hcryp->State = HAL_CRYP_STATE_BUSY;
2692 
2693  /* Set CRYP peripheral in DES CBC decryption mode */
2694  CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
2695 
2696  /* Enable Interrupts */
2697  __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
2698 
2699  /* Enable CRYP */
2700  __HAL_CRYP_ENABLE(hcryp);
2701 
2702  /* Return function status */
2703  return HAL_OK;
2704  }
2705  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
2706  {
2707  inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
2708  /* Write the Input block in the IN FIFO */
2709  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
2710  inputaddr+=4;
2711  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
2712 
2713  hcryp->pCrypInBuffPtr += 8;
2714  hcryp->CrypInCount -= 8;
2715  if(hcryp->CrypInCount == 0)
2716  {
2717  __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
2718  /* Call the Input data transfer complete callback */
2719  HAL_CRYP_InCpltCallback(hcryp);
2720  }
2721  }
2722  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
2723  {
2724  outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
2725  /* Read the Output block from the Output FIFO */
2726  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
2727  outputaddr+=4;
2728  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
2729 
2730  hcryp->pCrypOutBuffPtr += 8;
2731  hcryp->CrypOutCount -= 8;
2732  if(hcryp->CrypOutCount == 0)
2733  {
2734  /* Disable IT */
2735  __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
2736  /* Disable CRYP */
2737  __HAL_CRYP_DISABLE(hcryp);
2738  /* Process Unlocked */
2739  __HAL_UNLOCK(hcryp);
2740  /* Change the CRYP state */
2741  hcryp->State = HAL_CRYP_STATE_READY;
2742  /* Call Input transfer complete callback */
2743  HAL_CRYP_OutCpltCallback(hcryp);
2744  }
2745  }
2746 
2747  /* Return function status */
2748  return HAL_OK;
2749 }
2750 
2760 HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
2761 {
2762  uint32_t inputaddr;
2763  uint32_t outputaddr;
2764 
2765  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
2766  {
2767  /* Process Locked */
2768  __HAL_LOCK(hcryp);
2769 
2770  inputaddr = (uint32_t)pPlainData;
2771  outputaddr = (uint32_t)pCypherData;
2772 
2773  /* Change the CRYP state */
2774  hcryp->State = HAL_CRYP_STATE_BUSY;
2775 
2776  /* Set CRYP peripheral in DES ECB encryption mode */
2777  CRYP_SetDESECBMode(hcryp, 0);
2778 
2779  /* Set the input and output addresses and start DMA transfer */
2780  CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
2781 
2782  /* Process Unlocked */
2783  __HAL_UNLOCK(hcryp);
2784 
2785  /* Return function status */
2786  return HAL_OK;
2787  }
2788  else
2789  {
2790  return HAL_ERROR;
2791  }
2792 }
2793 
2803 HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
2804 {
2805  uint32_t inputaddr;
2806  uint32_t outputaddr;
2807 
2808  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
2809  {
2810  /* Process Locked */
2811  __HAL_LOCK(hcryp);
2812 
2813  inputaddr = (uint32_t)pPlainData;
2814  outputaddr = (uint32_t)pCypherData;
2815 
2816  /* Change the CRYP state */
2817  hcryp->State = HAL_CRYP_STATE_BUSY;
2818 
2819  /* Set CRYP peripheral in DES CBC encryption mode */
2820  CRYP_SetDESCBCMode(hcryp, 0);
2821 
2822  /* Set the input and output addresses and start DMA transfer */
2823  CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
2824 
2825  /* Process Unlocked */
2826  __HAL_UNLOCK(hcryp);
2827 
2828  /* Return function status */
2829  return HAL_OK;
2830  }
2831  else
2832  {
2833  return HAL_ERROR;
2834  }
2835 }
2836 
2846 HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
2847 {
2848  uint32_t inputaddr;
2849  uint32_t outputaddr;
2850 
2851  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
2852  {
2853  /* Process Locked */
2854  __HAL_LOCK(hcryp);
2855 
2856  inputaddr = (uint32_t)pCypherData;
2857  outputaddr = (uint32_t)pPlainData;
2858 
2859  /* Change the CRYP state */
2860  hcryp->State = HAL_CRYP_STATE_BUSY;
2861 
2862  /* Set CRYP peripheral in DES ECB decryption mode */
2863  CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
2864 
2865  /* Set the input and output addresses and start DMA transfer */
2866  CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
2867 
2868  /* Process Unlocked */
2869  __HAL_UNLOCK(hcryp);
2870 
2871  /* Return function status */
2872  return HAL_OK;
2873  }
2874  else
2875  {
2876  return HAL_ERROR;
2877  }
2878 }
2879 
2889 HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
2890 {
2891  uint32_t inputaddr;
2892  uint32_t outputaddr;
2893 
2894  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
2895  {
2896  /* Process Locked */
2897  __HAL_LOCK(hcryp);
2898 
2899  inputaddr = (uint32_t)pCypherData;
2900  outputaddr = (uint32_t)pPlainData;
2901 
2902  /* Change the CRYP state */
2903  hcryp->State = HAL_CRYP_STATE_BUSY;
2904 
2905  /* Set CRYP peripheral in DES CBC decryption mode */
2906  CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
2907 
2908  /* Set the input and output addresses and start DMA transfer */
2909  CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
2910 
2911  /* Process Unlocked */
2912  __HAL_UNLOCK(hcryp);
2913 
2914  /* Return function status */
2915  return HAL_OK;
2916  }
2917  else
2918  {
2919  return HAL_ERROR;
2920  }
2921 }
2922 
2957 HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
2958 {
2959  /* Process Locked */
2960  __HAL_LOCK(hcryp);
2961 
2962  /* Change the CRYP state */
2963  hcryp->State = HAL_CRYP_STATE_BUSY;
2964 
2965  /* Set CRYP peripheral in TDES ECB encryption mode */
2966  CRYP_SetTDESECBMode(hcryp, 0);
2967 
2968  /* Enable CRYP */
2969  __HAL_CRYP_ENABLE(hcryp);
2970 
2971  /* Write Plain Data and Get Cypher Data */
2972  if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
2973  {
2974  return HAL_TIMEOUT;
2975  }
2976 
2977  /* Change the CRYP state */
2978  hcryp->State = HAL_CRYP_STATE_READY;
2979 
2980  /* Process Unlocked */
2981  __HAL_UNLOCK(hcryp);
2982 
2983  /* Return function status */
2984  return HAL_OK;
2985 }
2986 
2998 HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
2999 {
3000  /* Process Locked */
3001  __HAL_LOCK(hcryp);
3002 
3003  /* Change the CRYP state */
3004  hcryp->State = HAL_CRYP_STATE_BUSY;
3005 
3006  /* Set CRYP peripheral in TDES ECB decryption mode */
3007  CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
3008 
3009  /* Enable CRYP */
3010  __HAL_CRYP_ENABLE(hcryp);
3011 
3012  /* Write Cypher Data and Get Plain Data */
3013  if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
3014  {
3015  return HAL_TIMEOUT;
3016  }
3017 
3018  /* Change the CRYP state */
3019  hcryp->State = HAL_CRYP_STATE_READY;
3020 
3021  /* Process Unlocked */
3022  __HAL_UNLOCK(hcryp);
3023 
3024  /* Return function status */
3025  return HAL_OK;
3026 }
3027 
3039 HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
3040 {
3041  /* Process Locked */
3042  __HAL_LOCK(hcryp);
3043 
3044  /* Change the CRYP state */
3045  hcryp->State = HAL_CRYP_STATE_BUSY;
3046 
3047  /* Set CRYP peripheral in TDES CBC encryption mode */
3048  CRYP_SetTDESCBCMode(hcryp, 0);
3049 
3050  /* Enable CRYP */
3051  __HAL_CRYP_ENABLE(hcryp);
3052 
3053  /* Write Plain Data and Get Cypher Data */
3054  if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
3055  {
3056  return HAL_TIMEOUT;
3057  }
3058 
3059  /* Change the CRYP state */
3060  hcryp->State = HAL_CRYP_STATE_READY;
3061 
3062  /* Process Unlocked */
3063  __HAL_UNLOCK(hcryp);
3064 
3065  /* Return function status */
3066  return HAL_OK;
3067 }
3068 
3080 HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
3081 {
3082  /* Process Locked */
3083  __HAL_LOCK(hcryp);
3084 
3085  /* Change the CRYP state */
3086  hcryp->State = HAL_CRYP_STATE_BUSY;
3087 
3088  /* Set CRYP peripheral in TDES CBC decryption mode */
3089  CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
3090 
3091  /* Enable CRYP */
3092  __HAL_CRYP_ENABLE(hcryp);
3093 
3094  /* Write Cypher Data and Get Plain Data */
3095  if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
3096  {
3097  return HAL_TIMEOUT;
3098  }
3099 
3100  /* Change the CRYP state */
3101  hcryp->State = HAL_CRYP_STATE_READY;
3102 
3103  /* Process Unlocked */
3104  __HAL_UNLOCK(hcryp);
3105 
3106  /* Return function status */
3107  return HAL_OK;
3108 }
3109 
3119 HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
3120 {
3121  uint32_t inputaddr;
3122  uint32_t outputaddr;
3123 
3124  if(hcryp->State == HAL_CRYP_STATE_READY)
3125  {
3126  /* Process Locked */
3127  __HAL_LOCK(hcryp);
3128 
3129  hcryp->CrypInCount = Size;
3130  hcryp->pCrypInBuffPtr = pPlainData;
3131  hcryp->pCrypOutBuffPtr = pCypherData;
3132  hcryp->CrypOutCount = Size;
3133 
3134  /* Change the CRYP state */
3135  hcryp->State = HAL_CRYP_STATE_BUSY;
3136 
3137  /* Set CRYP peripheral in TDES ECB encryption mode */
3138  CRYP_SetTDESECBMode(hcryp, 0);
3139 
3140  /* Enable Interrupts */
3141  __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
3142 
3143  /* Enable CRYP */
3144  __HAL_CRYP_ENABLE(hcryp);
3145 
3146  /* Return function status */
3147  return HAL_OK;
3148  }
3149  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
3150  {
3151  inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
3152  /* Write the Input block in the IN FIFO */
3153  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
3154  inputaddr+=4;
3155  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
3156 
3157  hcryp->pCrypInBuffPtr += 8;
3158  hcryp->CrypInCount -= 8;
3159  if(hcryp->CrypInCount == 0)
3160  {
3161  __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
3162  /* Call the Input data transfer complete callback */
3163  HAL_CRYP_InCpltCallback(hcryp);
3164  }
3165  }
3166  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
3167  {
3168  outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
3169  /* Read the Output block from the Output FIFO */
3170  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
3171  outputaddr+=4;
3172  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
3173 
3174  hcryp->pCrypOutBuffPtr += 8;
3175  hcryp->CrypOutCount -= 8;
3176  if(hcryp->CrypOutCount == 0)
3177  {
3178  /* Disable IT */
3179  __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
3180  /* Disable CRYP */
3181  __HAL_CRYP_DISABLE(hcryp);
3182  /* Process Unlocked */
3183  __HAL_UNLOCK(hcryp);
3184  /* Change the CRYP state */
3185  hcryp->State = HAL_CRYP_STATE_READY;
3186  /* Call the Output data transfer complete callback */
3187  HAL_CRYP_OutCpltCallback(hcryp);
3188  }
3189  }
3190 
3191  /* Return function status */
3192  return HAL_OK;
3193 }
3194 
3204 HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
3205 {
3206  uint32_t inputaddr;
3207  uint32_t outputaddr;
3208 
3209  if(hcryp->State == HAL_CRYP_STATE_READY)
3210  {
3211  /* Process Locked */
3212  __HAL_LOCK(hcryp);
3213 
3214  hcryp->CrypInCount = Size;
3215  hcryp->pCrypInBuffPtr = pPlainData;
3216  hcryp->pCrypOutBuffPtr = pCypherData;
3217  hcryp->CrypOutCount = Size;
3218 
3219  /* Change the CRYP state */
3220  hcryp->State = HAL_CRYP_STATE_BUSY;
3221 
3222  /* Set CRYP peripheral in TDES CBC encryption mode */
3223  CRYP_SetTDESCBCMode(hcryp, 0);
3224 
3225  /* Enable Interrupts */
3226  __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
3227 
3228  /* Enable CRYP */
3229  __HAL_CRYP_ENABLE(hcryp);
3230 
3231  /* Return function status */
3232  return HAL_OK;
3233  }
3234  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
3235  {
3236  inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
3237  /* Write the Input block in the IN FIFO */
3238  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
3239  inputaddr+=4;
3240  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
3241 
3242  hcryp->pCrypInBuffPtr += 8;
3243  hcryp->CrypInCount -= 8;
3244  if(hcryp->CrypInCount == 0)
3245  {
3246  __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
3247  /* Call the Input data transfer complete callback */
3248  HAL_CRYP_InCpltCallback(hcryp);
3249  }
3250  }
3251  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
3252  {
3253  outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
3254  /* Read the Output block from the Output FIFO */
3255  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
3256  outputaddr+=4;
3257  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
3258 
3259  hcryp->pCrypOutBuffPtr += 8;
3260  hcryp->CrypOutCount -= 8;
3261  if(hcryp->CrypOutCount == 0)
3262  {
3263  __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
3264  /* Disable CRYP */
3265  __HAL_CRYP_DISABLE(hcryp);
3266  /* Process Unlocked */
3267  __HAL_UNLOCK(hcryp);
3268  /* Change the CRYP state */
3269  hcryp->State = HAL_CRYP_STATE_READY;
3270  /* Call Input transfer complete callback */
3271  HAL_CRYP_OutCpltCallback(hcryp);
3272  }
3273  }
3274 
3275  /* Return function status */
3276  return HAL_OK;
3277 }
3278 
3288 HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
3289 {
3290  uint32_t inputaddr;
3291  uint32_t outputaddr;
3292 
3293  if(hcryp->State == HAL_CRYP_STATE_READY)
3294  {
3295  /* Process Locked */
3296  __HAL_LOCK(hcryp);
3297 
3298  hcryp->CrypInCount = Size;
3299  hcryp->pCrypInBuffPtr = pCypherData;
3300  hcryp->pCrypOutBuffPtr = pPlainData;
3301  hcryp->CrypOutCount = Size;
3302 
3303  /* Change the CRYP state */
3304  hcryp->State = HAL_CRYP_STATE_BUSY;
3305 
3306  /* Set CRYP peripheral in TDES ECB decryption mode */
3307  CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
3308 
3309  /* Enable Interrupts */
3310  __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
3311 
3312  /* Enable CRYP */
3313  __HAL_CRYP_ENABLE(hcryp);
3314 
3315  /* Return function status */
3316  return HAL_OK;
3317  }
3318  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
3319  {
3320  inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
3321  /* Write the Input block in the IN FIFO */
3322  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
3323  inputaddr+=4;
3324  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
3325 
3326  hcryp->pCrypInBuffPtr += 8;
3327  hcryp->CrypInCount -= 8;
3328  if(hcryp->CrypInCount == 0)
3329  {
3330  __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
3331  /* Call the Input data transfer complete callback */
3332  HAL_CRYP_InCpltCallback(hcryp);
3333  }
3334  }
3335  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
3336  {
3337  outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
3338  /* Read the Output block from the Output FIFO */
3339  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
3340  outputaddr+=4;
3341  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
3342 
3343  hcryp->pCrypOutBuffPtr += 8;
3344  hcryp->CrypOutCount -= 8;
3345  if(hcryp->CrypOutCount == 0)
3346  {
3347  __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
3348  /* Disable CRYP */
3349  __HAL_CRYP_DISABLE(hcryp);
3350  /* Process Unlocked */
3351  __HAL_UNLOCK(hcryp);
3352  /* Change the CRYP state */
3353  hcryp->State = HAL_CRYP_STATE_READY;
3354  /* Call Input transfer complete callback */
3355  HAL_CRYP_OutCpltCallback(hcryp);
3356  }
3357  }
3358 
3359  /* Return function status */
3360  return HAL_OK;
3361 }
3362 
3372 HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
3373 {
3374  uint32_t inputaddr;
3375  uint32_t outputaddr;
3376 
3377  if(hcryp->State == HAL_CRYP_STATE_READY)
3378  {
3379  /* Process Locked */
3380  __HAL_LOCK(hcryp);
3381 
3382  hcryp->CrypInCount = Size;
3383  hcryp->pCrypInBuffPtr = pCypherData;
3384  hcryp->pCrypOutBuffPtr = pPlainData;
3385  hcryp->CrypOutCount = Size;
3386 
3387  /* Change the CRYP state */
3388  hcryp->State = HAL_CRYP_STATE_BUSY;
3389 
3390  /* Set CRYP peripheral in TDES CBC decryption mode */
3391  CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
3392 
3393  /* Enable Interrupts */
3394  __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
3395 
3396  /* Enable CRYP */
3397  __HAL_CRYP_ENABLE(hcryp);
3398 
3399  /* Return function status */
3400  return HAL_OK;
3401  }
3402  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
3403  {
3404  inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
3405  /* Write the Input block in the IN FIFO */
3406  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
3407  inputaddr+=4;
3408  hcryp->Instance->DR = *(uint32_t*)(inputaddr);
3409 
3410  hcryp->pCrypInBuffPtr += 8;
3411  hcryp->CrypInCount -= 8;
3412  if(hcryp->CrypInCount == 0)
3413  {
3414  __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
3415  /* Call the Input data transfer complete callback */
3416  HAL_CRYP_InCpltCallback(hcryp);
3417  }
3418  }
3419  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
3420  {
3421  outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
3422  /* Read the Output block from the Output FIFO */
3423  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
3424  outputaddr+=4;
3425  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
3426 
3427  hcryp->pCrypOutBuffPtr += 8;
3428  hcryp->CrypOutCount -= 8;
3429  if(hcryp->CrypOutCount == 0)
3430  {
3431  __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
3432  /* Disable CRYP */
3433  __HAL_CRYP_DISABLE(hcryp);
3434  /* Process Unlocked */
3435  __HAL_UNLOCK(hcryp);
3436  /* Change the CRYP state */
3437  hcryp->State = HAL_CRYP_STATE_READY;
3438  /* Call Input transfer complete callback */
3439  HAL_CRYP_OutCpltCallback(hcryp);
3440  }
3441  }
3442 
3443  /* Return function status */
3444  return HAL_OK;
3445 }
3446 
3456 HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
3457 {
3458  uint32_t inputaddr;
3459  uint32_t outputaddr;
3460 
3461  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
3462  {
3463  /* Process Locked */
3464  __HAL_LOCK(hcryp);
3465 
3466  inputaddr = (uint32_t)pPlainData;
3467  outputaddr = (uint32_t)pCypherData;
3468 
3469  /* Change the CRYP state */
3470  hcryp->State = HAL_CRYP_STATE_BUSY;
3471 
3472  /* Set CRYP peripheral in TDES ECB encryption mode */
3473  CRYP_SetTDESECBMode(hcryp, 0);
3474 
3475  /* Set the input and output addresses and start DMA transfer */
3476  CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
3477 
3478  /* Process Unlocked */
3479  __HAL_UNLOCK(hcryp);
3480 
3481  /* Return function status */
3482  return HAL_OK;
3483  }
3484  else
3485  {
3486  return HAL_ERROR;
3487  }
3488 }
3489 
3499 HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
3500 {
3501  uint32_t inputaddr;
3502  uint32_t outputaddr;
3503 
3504  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
3505  {
3506  /* Process Locked */
3507  __HAL_LOCK(hcryp);
3508 
3509  inputaddr = (uint32_t)pPlainData;
3510  outputaddr = (uint32_t)pCypherData;
3511 
3512  /* Change the CRYP state */
3513  hcryp->State = HAL_CRYP_STATE_BUSY;
3514 
3515  /* Set CRYP peripheral in TDES CBC encryption mode */
3516  CRYP_SetTDESCBCMode(hcryp, 0);
3517 
3518  /* Set the input and output addresses and start DMA transfer */
3519  CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
3520 
3521  /* Process Unlocked */
3522  __HAL_UNLOCK(hcryp);
3523 
3524  /* Return function status */
3525  return HAL_OK;
3526  }
3527  else
3528  {
3529  return HAL_ERROR;
3530  }
3531 }
3532 
3542 HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
3543 {
3544  uint32_t inputaddr;
3545  uint32_t outputaddr;
3546 
3547  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
3548  {
3549  /* Process Locked */
3550  __HAL_LOCK(hcryp);
3551 
3552  inputaddr = (uint32_t)pCypherData;
3553  outputaddr = (uint32_t)pPlainData;
3554 
3555  /* Change the CRYP state */
3556  hcryp->State = HAL_CRYP_STATE_BUSY;
3557 
3558  /* Set CRYP peripheral in TDES ECB decryption mode */
3559  CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
3560 
3561  /* Set the input and output addresses and start DMA transfer */
3562  CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
3563 
3564  /* Process Unlocked */
3565  __HAL_UNLOCK(hcryp);
3566 
3567  /* Return function status */
3568  return HAL_OK;
3569  }
3570  else
3571  {
3572  return HAL_ERROR;
3573  }
3574 }
3575 
3585 HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
3586 {
3587  uint32_t inputaddr;
3588  uint32_t outputaddr;
3589 
3590  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
3591  {
3592  /* Process Locked */
3593  __HAL_LOCK(hcryp);
3594 
3595  inputaddr = (uint32_t)pCypherData;
3596  outputaddr = (uint32_t)pPlainData;
3597 
3598  /* Change the CRYP state */
3599  hcryp->State = HAL_CRYP_STATE_BUSY;
3600 
3601  /* Set CRYP peripheral in TDES CBC decryption mode */
3602  CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
3603 
3604  /* Set the input and output addresses and start DMA transfer */
3605  CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
3606 
3607  /* Process Unlocked */
3608  __HAL_UNLOCK(hcryp);
3609 
3610  /* Return function status */
3611  return HAL_OK;
3612  }
3613  else
3614  {
3615  return HAL_ERROR;
3616  }
3617 }
3618 
3645 __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
3646 {
3647  /* Prevent unused argument(s) compilation warning */
3648  UNUSED(hcryp);
3649 
3650  /* NOTE : This function Should not be modified, when the callback is needed,
3651  the HAL_CRYP_InCpltCallback could be implemented in the user file
3652  */
3653 }
3654 
3661 __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
3662 {
3663  /* Prevent unused argument(s) compilation warning */
3664  UNUSED(hcryp);
3665 
3666  /* NOTE : This function Should not be modified, when the callback is needed,
3667  the HAL_CRYP_OutCpltCallback could be implemented in the user file
3668  */
3669 }
3670 
3677  __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
3678 {
3679  /* Prevent unused argument(s) compilation warning */
3680  UNUSED(hcryp);
3681 
3682  /* NOTE : This function Should not be modified, when the callback is needed,
3683  the HAL_CRYP_ErrorCallback could be implemented in the user file
3684  */
3685 }
3686 
3710 void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
3711 {
3712  switch(CRYP->CR & CRYP_CR_ALGOMODE_DIRECTION)
3713  {
3714  case CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT:
3715  HAL_CRYP_TDESECB_Encrypt_IT(hcryp, NULL, 0, NULL);
3716  break;
3717 
3718  case CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT:
3719  HAL_CRYP_TDESECB_Decrypt_IT(hcryp, NULL, 0, NULL);
3720  break;
3721 
3722  case CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT:
3723  HAL_CRYP_TDESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);
3724  break;
3725 
3726  case CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT:
3727  HAL_CRYP_TDESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);
3728  break;
3729 
3730  case CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT:
3731  HAL_CRYP_DESECB_Encrypt_IT(hcryp, NULL, 0, NULL);
3732  break;
3733 
3734  case CRYP_CR_ALGOMODE_DES_ECB_DECRYPT:
3735  HAL_CRYP_DESECB_Decrypt_IT(hcryp, NULL, 0, NULL);
3736  break;
3737 
3738  case CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT:
3739  HAL_CRYP_DESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);
3740  break;
3741 
3742  case CRYP_CR_ALGOMODE_DES_CBC_DECRYPT:
3743  HAL_CRYP_DESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);
3744  break;
3745 
3746  case CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT:
3747  HAL_CRYP_AESECB_Encrypt_IT(hcryp, NULL, 0, NULL);
3748  break;
3749 
3750  case CRYP_CR_ALGOMODE_AES_ECB_DECRYPT:
3751  HAL_CRYP_AESECB_Decrypt_IT(hcryp, NULL, 0, NULL);
3752  break;
3753 
3754  case CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT:
3755  HAL_CRYP_AESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);
3756  break;
3757 
3758  case CRYP_CR_ALGOMODE_AES_CBC_DECRYPT:
3759  HAL_CRYP_AESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);
3760  break;
3761 
3762  case CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT:
3763  HAL_CRYP_AESCTR_Encrypt_IT(hcryp, NULL, 0, NULL);
3764  break;
3765 
3766  case CRYP_CR_ALGOMODE_AES_CTR_DECRYPT:
3767  HAL_CRYP_AESCTR_Decrypt_IT(hcryp, NULL, 0, NULL);
3768  break;
3769 
3770  default:
3771  break;
3772  }
3773 }
3774 
3799 HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
3800 {
3801  return hcryp->State;
3802 }
3803 
3812 #endif /* HAL_CRYP_MODULE_ENABLED */
3813 
3814 
3818 #endif /* STM32F756xx || STM32F777xx || STM32F779xx */
3819 
3823 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
HAL_UNLOCKED
Definition: stm32f7xx_hal_def.h:69
CRYP_CR_ALGOMODE_AES_KEY
#define CRYP_CR_ALGOMODE_AES_KEY
Definition: stm32f756xx.h:3233
CRYP_CR_ALGOMODE_DES_ECB
#define CRYP_CR_ALGOMODE_DES_ECB
Definition: stm32f756xx.h:3228
assert_param
#define assert_param(expr)
Include module&#39;s header file.
Definition: stm32f7xx_hal_conf.h:443
CRYP_CR_ALGOMODE_TDES_ECB
#define CRYP_CR_ALGOMODE_TDES_ECB
Definition: stm32f756xx.h:3226
__HAL_UNLOCK
#define __HAL_UNLOCK(__HANDLE__)
Definition: stm32f7xx_hal_def.h:120
HAL_DMA_Start_IT
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
CRYP_CR_ALGODIR
#define CRYP_CR_ALGODIR
Definition: stm32f756xx.h:3220
CRYP_CR_ALGOMODE_TDES_CBC
#define CRYP_CR_ALGOMODE_TDES_CBC
Definition: stm32f756xx.h:3227
__HAL_LOCK
#define __HAL_LOCK(__HANDLE__)
Definition: stm32f7xx_hal_def.h:108
HAL_OK
Definition: stm32f7xx_hal_def.h:58
NULL
#define NULL
Definition: usbd_def.h:53
HAL_MAX_DELAY
#define HAL_MAX_DELAY
Definition: stm32f7xx_hal_def.h:74
CRYP_CR_ALGOMODE
#define CRYP_CR_ALGOMODE
Definition: stm32f756xx.h:3222
stm32f7xx_hal.h
This file contains all the functions prototypes for the HAL module driver.
CRYP
#define CRYP
Definition: stm32f756xx.h:1475
HAL_IS_BIT_CLR
#define HAL_IS_BIT_CLR(REG, BIT)
Definition: stm32f7xx_hal_def.h:77
CRYP_CR_ALGOMODE_AES_ECB
#define CRYP_CR_ALGOMODE_AES_ECB
Definition: stm32f756xx.h:3230
UNUSED
#define UNUSED(x)
Definition: stm32f7xx_hal_def.h:85
CRYP_CR_ALGOMODE_DES_CBC
#define CRYP_CR_ALGOMODE_DES_CBC
Definition: stm32f756xx.h:3229
CRYP_DMACR_DOEN
#define CRYP_DMACR_DOEN
Definition: stm32f756xx.h:3257
CRYP_DMACR_DIEN
#define CRYP_DMACR_DIEN
Definition: stm32f756xx.h:3256
HAL_IS_BIT_SET
#define HAL_IS_BIT_SET(REG, BIT)
Definition: stm32f7xx_hal_def.h:76
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition: stm32f7xx_hal_dma.h:156
HAL_ERROR
Definition: stm32f7xx_hal_def.h:59
__REV
#define __REV
Reverse byte order (32 bit)
Definition: cmsis_armcc.h:378
HAL_TIMEOUT
Definition: stm32f7xx_hal_def.h:61
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32f7xx_hal_def.h:56
HAL_GetTick
uint32_t HAL_GetTick(void)
Provides a tick value in millisecond.
Definition: stm32f7xx_hal.c:301
CRYP_CR_ALGOMODE_AES_CBC
#define CRYP_CR_ALGOMODE_AES_CBC
Definition: stm32f756xx.h:3231
CRYP_CR_ALGOMODE_AES_CTR
#define CRYP_CR_ALGOMODE_AES_CTR
Definition: stm32f756xx.h:3232
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