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STM32F769IDiscovery
1.00
uDANTE Audio Networking with STM32F7 DISCO board
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STM32F769IDiscovery
1.00
uDANTE Audio Networking with STM32F7 DISCO board
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| #define BULK_ERASE_CMD 0xC7 |
Definition at line 170 of file n25q512a.h.
| #define CLEAR_FLAG_STATUS_REG_CMD 0x50 |
Definition at line 138 of file n25q512a.h.
| #define DUAL_IN_FAST_PROG_CMD 0xA2 |
Definition at line 156 of file n25q512a.h.
| #define DUAL_INOUT_FAST_READ_4_BYTE_ADDR_CMD 0xBC |
Definition at line 116 of file n25q512a.h.
| #define DUAL_INOUT_FAST_READ_CMD 0xBB |
Definition at line 114 of file n25q512a.h.
| #define DUAL_INOUT_FAST_READ_DTR_CMD 0xBD |
Definition at line 115 of file n25q512a.h.
| #define DUAL_OUT_FAST_READ_4_BYTE_ADDR_CMD 0x3C |
Definition at line 112 of file n25q512a.h.
| #define DUAL_OUT_FAST_READ_CMD 0x3B |
Definition at line 110 of file n25q512a.h.
| #define DUAL_OUT_FAST_READ_DTR_CMD 0x3D |
Definition at line 111 of file n25q512a.h.
| #define ENTER_4_BYTE_ADDR_MODE_CMD 0xB7 |
Definition at line 180 of file n25q512a.h.
| #define ENTER_QUAD_CMD 0x35 |
Definition at line 184 of file n25q512a.h.
| #define EXIT_4_BYTE_ADDR_MODE_CMD 0xE9 |
Definition at line 181 of file n25q512a.h.
| #define EXIT_QUAD_CMD 0xF5 |
Definition at line 185 of file n25q512a.h.
| #define EXT_DUAL_IN_FAST_PROG_CMD 0xD2 |
Definition at line 157 of file n25q512a.h.
| #define EXT_QUAD_IN_FAST_PROG_CMD 0x12 /*0x38*/ |
Definition at line 160 of file n25q512a.h.
| #define FAST_READ_4_BYTE_ADDR_CMD 0x0C |
Definition at line 108 of file n25q512a.h.
| #define FAST_READ_CMD 0x0B |
Definition at line 106 of file n25q512a.h.
| #define FAST_READ_DTR_CMD 0x0D |
Definition at line 107 of file n25q512a.h.
| #define MULTIPLE_IO_READ_ID_CMD 0xAF |
Definition at line 99 of file n25q512a.h.
| #define N25Q512A_BULK_ERASE_MAX_TIME 480000 |
Definition at line 85 of file n25q512a.h.
| #define N25Q512A_DUMMY_CYCLES_READ 8 |
Definition at line 80 of file n25q512a.h.
| #define N25Q512A_DUMMY_CYCLES_READ_DTR 6 |
Definition at line 82 of file n25q512a.h.
| #define N25Q512A_DUMMY_CYCLES_READ_QUAD 10 |
Definition at line 81 of file n25q512a.h.
| #define N25Q512A_DUMMY_CYCLES_READ_QUAD_DTR 8 |
Definition at line 83 of file n25q512a.h.
| #define N25Q512A_EAR_A24 ((uint8_t)0x01) |
Select the lower or upper 128Mb segment
Definition at line 213 of file n25q512a.h.
| #define N25Q512A_EVCR_DUAL ((uint8_t)0x40) |
Dual I/O protocol
Definition at line 219 of file n25q512a.h.
| #define N25Q512A_EVCR_ODS ((uint8_t)0x07) |
Output driver strength
Definition at line 216 of file n25q512a.h.
| #define N25Q512A_EVCR_QUAD ((uint8_t)0x80) |
Quad I/O protocol
Definition at line 220 of file n25q512a.h.
| #define N25Q512A_EVCR_RH ((uint8_t)0x10) |
Reset/hold
Definition at line 218 of file n25q512a.h.
| #define N25Q512A_EVCR_VPPA ((uint8_t)0x08) |
Vpp accelerator
Definition at line 217 of file n25q512a.h.
| #define N25Q512A_FLASH_SIZE 0x4000000 /* 512 MBits => 64MBytes */ |
N25Q512A Configuration.
Definition at line 75 of file n25q512a.h.
| #define N25Q512A_FSR_ERERR ((uint8_t)0x20) |
Erase error
Definition at line 228 of file n25q512a.h.
| #define N25Q512A_FSR_ERSUS ((uint8_t)0x40) |
Erase operation suspended
Definition at line 229 of file n25q512a.h.
| #define N25Q512A_FSR_NBADDR ((uint8_t)0x01) |
3-bytes or 4-bytes addressing
Definition at line 223 of file n25q512a.h.
| #define N25Q512A_FSR_PGERR ((uint8_t)0x10) |
Program error
Definition at line 227 of file n25q512a.h.
| #define N25Q512A_FSR_PGSUS ((uint8_t)0x04) |
Program operation suspended
Definition at line 225 of file n25q512a.h.
| #define N25Q512A_FSR_PRERR ((uint8_t)0x02) |
Protection error
Definition at line 224 of file n25q512a.h.
| #define N25Q512A_FSR_READY ((uint8_t)0x80) |
Ready or command in progress
Definition at line 230 of file n25q512a.h.
| #define N25Q512A_FSR_VPPERR ((uint8_t)0x08) |
Invalid voltage during program or erase
Definition at line 226 of file n25q512a.h.
| #define N25Q512A_NVCR_DUAL ((uint16_t)0x0004) |
Dual I/O protocol
Definition at line 200 of file n25q512a.h.
| #define N25Q512A_NVCR_NB_DUMMY ((uint16_t)0xF000) |
Number of dummy clock cycles
Definition at line 205 of file n25q512a.h.
| #define N25Q512A_NVCR_NBADDR ((uint16_t)0x0001) |
3-bytes or 4-bytes addressing
Definition at line 198 of file n25q512a.h.
| #define N25Q512A_NVCR_ODS ((uint16_t)0x01C0) |
Output driver strength
Definition at line 203 of file n25q512a.h.
| #define N25Q512A_NVCR_QUAB ((uint16_t)0x0008) |
Quad I/O protocol
Definition at line 201 of file n25q512a.h.
| #define N25Q512A_NVCR_RH ((uint16_t)0x0010) |
Reset/hold
Definition at line 202 of file n25q512a.h.
| #define N25Q512A_NVCR_SEGMENT ((uint16_t)0x0002) |
Upper or lower 128Mb segment selected by default
Definition at line 199 of file n25q512a.h.
| #define N25Q512A_NVCR_XIP ((uint16_t)0x0E00) |
XIP mode at power-on reset
Definition at line 204 of file n25q512a.h.
| #define N25Q512A_PAGE_SIZE 0x100 /* 262144 pages of 256 bytes */ |
Definition at line 78 of file n25q512a.h.
| #define N25Q512A_SECTOR_ERASE_MAX_TIME 3000 |
Definition at line 86 of file n25q512a.h.
| #define N25Q512A_SECTOR_SIZE 0x10000 /* 1024 sectors of 64KBytes */ |
Definition at line 76 of file n25q512a.h.
| #define N25Q512A_SR_BLOCKPR ((uint8_t)0x5C) |
Block protected against program and erase operations
Definition at line 193 of file n25q512a.h.
| #define N25Q512A_SR_PRBOTTOM ((uint8_t)0x20) |
Protected memory area defined by BLOCKPR starts from top or bottom
Definition at line 194 of file n25q512a.h.
| #define N25Q512A_SR_SRWREN ((uint8_t)0x80) |
Status register write enable/disable
Definition at line 195 of file n25q512a.h.
| #define N25Q512A_SR_WIP ((uint8_t)0x01) |
| #define N25Q512A_SR_WREN ((uint8_t)0x02) |
Write enable latch
Definition at line 192 of file n25q512a.h.
| #define N25Q512A_SUBSECTOR_ERASE_MAX_TIME 800 |
Definition at line 87 of file n25q512a.h.
| #define N25Q512A_SUBSECTOR_SIZE 0x1000 /* 16384 subsectors of 4kBytes */ |
Definition at line 77 of file n25q512a.h.
| #define N25Q512A_VCR_NB_DUMMY ((uint8_t)0xF0) |
Number of dummy clock cycles
Definition at line 210 of file n25q512a.h.
| #define N25Q512A_VCR_WRAP ((uint8_t)0x03) |
Wrap
Definition at line 208 of file n25q512a.h.
| #define N25Q512A_VCR_XIP ((uint8_t)0x08) |
XIP
Definition at line 209 of file n25q512a.h.
| #define PAGE_PROG_4_BYTE_ADDR_CMD 0x12 |
Definition at line 154 of file n25q512a.h.
| #define PAGE_PROG_CMD 0x02 |
Definition at line 153 of file n25q512a.h.
| #define PROG_ERASE_RESUME_CMD 0x7A |
Definition at line 172 of file n25q512a.h.
| #define PROG_ERASE_SUSPEND_CMD 0x75 |
Definition at line 173 of file n25q512a.h.
| #define PROG_OTP_ARRAY_CMD 0x42 |
Definition at line 177 of file n25q512a.h.
| #define QUAD_IN_FAST_PROG_4_BYTE_ADDR_CMD 0x34 |
Definition at line 161 of file n25q512a.h.
| #define QUAD_IN_FAST_PROG_CMD 0x32 |
Definition at line 159 of file n25q512a.h.
| #define QUAD_INOUT_FAST_READ_4_BYTE_ADDR_CMD 0xEC |
Definition at line 124 of file n25q512a.h.
| #define QUAD_INOUT_FAST_READ_CMD 0xEB |
Definition at line 122 of file n25q512a.h.
| #define QUAD_INOUT_FAST_READ_DTR_CMD 0xED |
Definition at line 123 of file n25q512a.h.
| #define QUAD_OUT_FAST_READ_4_BYTE_ADDR_CMD 0x6C |
Definition at line 120 of file n25q512a.h.
| #define QUAD_OUT_FAST_READ_CMD 0x6B |
Definition at line 118 of file n25q512a.h.
| #define QUAD_OUT_FAST_READ_DTR_CMD 0x6D |
Definition at line 119 of file n25q512a.h.
| #define READ_4_BYTE_ADDR_CMD 0x13 |
Definition at line 104 of file n25q512a.h.
| #define READ_CMD 0x03 |
Definition at line 103 of file n25q512a.h.
| #define READ_ENHANCED_VOL_CFG_REG_CMD 0x65 |
Definition at line 146 of file n25q512a.h.
| #define READ_EXT_ADDR_REG_CMD 0xC8 |
Definition at line 149 of file n25q512a.h.
| #define READ_FLAG_STATUS_REG_CMD 0x70 |
Definition at line 137 of file n25q512a.h.
| #define READ_ID_CMD 0x9E |
Definition at line 97 of file n25q512a.h.
| #define READ_ID_CMD2 0x9F |
Definition at line 98 of file n25q512a.h.
| #define READ_LOCK_REG_CMD 0xE8 |
Definition at line 134 of file n25q512a.h.
| #define READ_NONVOL_CFG_REG_CMD 0xB5 |
Definition at line 140 of file n25q512a.h.
| #define READ_OTP_ARRAY_CMD 0x4B |
Definition at line 176 of file n25q512a.h.
| #define READ_SERIAL_FLASH_DISCO_PARAM_CMD 0x5A |
Definition at line 100 of file n25q512a.h.
| #define READ_STATUS_REG_CMD 0x05 |
Definition at line 131 of file n25q512a.h.
| #define READ_VOL_CFG_REG_CMD 0x85 |
Definition at line 143 of file n25q512a.h.
| #define RESET_ENABLE_CMD 0x66 |
N25Q512A Commands.
Definition at line 93 of file n25q512a.h.
| #define RESET_MEMORY_CMD 0x99 |
Definition at line 94 of file n25q512a.h.
| #define SECTOR_ERASE_4_BYTE_ADDR_CMD 0xDC |
Definition at line 168 of file n25q512a.h.
| #define SECTOR_ERASE_CMD 0xD8 |
Definition at line 167 of file n25q512a.h.
| #define SUBSECTOR_ERASE_4_BYTE_ADDR_CMD 0x21 |
Definition at line 165 of file n25q512a.h.
| #define SUBSECTOR_ERASE_CMD 0x20 |
Definition at line 164 of file n25q512a.h.
| #define WRITE_DISABLE_CMD 0x04 |
Definition at line 128 of file n25q512a.h.
| #define WRITE_ENABLE_CMD 0x06 |
Definition at line 127 of file n25q512a.h.
| #define WRITE_ENHANCED_VOL_CFG_REG_CMD 0x61 |
Definition at line 147 of file n25q512a.h.
| #define WRITE_EXT_ADDR_REG_CMD 0xC5 |
Definition at line 150 of file n25q512a.h.
| #define WRITE_LOCK_REG_CMD 0xE5 |
Definition at line 135 of file n25q512a.h.
| #define WRITE_NONVOL_CFG_REG_CMD 0xB1 |
Definition at line 141 of file n25q512a.h.
| #define WRITE_STATUS_REG_CMD 0x01 |
Definition at line 132 of file n25q512a.h.
| #define WRITE_VOL_CFG_REG_CMD 0x81 |
Definition at line 144 of file n25q512a.h.
1.8.11
