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STM32F769IDiscovery
1.00
uDANTE Audio Networking with STM32F7 DISCO board
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STM32F769IDiscovery
1.00
uDANTE Audio Networking with STM32F7 DISCO board
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Modules | |
| IDD Control Register Defines | |
| IDD PreDelay Defines | |
| IDD Delta DElay Defines | |
Macros | |
| #define | MFXSTM32L152_REG_ADR_ID ((uint8_t)0x00) |
| MFX COMMON defines. More... | |
| #define | MFXSTM32L152_REG_ADR_FW_VERSION_MSB ((uint8_t)0x01) |
| Register address: chip FW_VERSION (R) More... | |
| #define | MFXSTM32L152_REG_ADR_FW_VERSION_LSB ((uint8_t)0x00) |
| #define | MFXSTM32L152_REG_ADR_SYS_CTRL ((uint8_t)0x40) |
| Register address: System Control Register (R/W) More... | |
| #define | MFXSTM32L152_REG_ADR_VDD_REF_MSB ((uint8_t)0x06) |
| Register address: Vdd monitoring (R) More... | |
| #define | MFXSTM32L152_REG_ADR_VDD_REF_LSB ((uint8_t)0x07) |
| #define | MFXSTM32L152_REG_ADR_ERROR_SRC ((uint8_t)0x03) |
| Register address: Error source. More... | |
| #define | MFXSTM32L152_REG_ADR_ERROR_MSG ((uint8_t)0x04) |
| Register address: Error Message. More... | |
| #define | MFXSTM32L152_REG_ADR_MFX_IRQ_OUT ((uint8_t)0x41) |
| Reg Addr IRQs: to config the pin that informs Main MCU that MFX events appear. More... | |
| #define | MFXSTM32L152_REG_ADR_IRQ_SRC_EN ((uint8_t)0x42) |
| Reg Addr IRQs: to select the events which activate the MFXSTM32L152_IRQ_OUT signal. More... | |
| #define | MFXSTM32L152_REG_ADR_IRQ_PENDING ((uint8_t)0x08) |
| Reg Addr IRQs: the Main MCU must read the IRQ_PENDING register to know the interrupt reason. More... | |
| #define | MFXSTM32L152_REG_ADR_IRQ_ACK ((uint8_t)0x44) |
| Reg Addr IRQs: the Main MCU must acknowledge it thanks to a writing access to the IRQ_ACK register. More... | |
| #define | MFXSTM32L152_ID_1 ((uint8_t)0x7B) |
| MFXSTM32L152_REG_ADR_ID choices. More... | |
| #define | MFXSTM32L152_ID_2 ((uint8_t)0x79) |
| #define | MFXSTM32L152_SWRST ((uint8_t)0x80) |
| MFXSTM32L152_REG_ADR_SYS_CTRL choices. More... | |
| #define | MFXSTM32L152_STANDBY ((uint8_t)0x40) |
| #define | MFXSTM32L152_ALTERNATE_GPIO_EN ((uint8_t)0x08) /* by the way if IDD and TS are enabled they take automatically the AF pins*/ |
| #define | MFXSTM32L152_IDD_EN ((uint8_t)0x04) |
| #define | MFXSTM32L152_TS_EN ((uint8_t)0x02) |
| #define | MFXSTM32L152_GPIO_EN ((uint8_t)0x01) |
| #define | MFXSTM32L152_IDD_ERROR_SRC ((uint8_t)0x04) /* Error raised by Idd */ |
| MFXSTM32L152_REG_ADR_ERROR_SRC choices. More... | |
| #define | MFXSTM32L152_TS_ERROR_SRC ((uint8_t)0x02) /* Error raised by Touch Screen */ |
| #define | MFXSTM32L152_GPIO_ERROR_SRC ((uint8_t)0x01) /* Error raised by Gpio */ |
| #define | MFXSTM32L152_OUT_PIN_TYPE_OPENDRAIN ((uint8_t)0x00) |
| MFXSTM32L152_REG_ADR_MFX_IRQ_OUT choices. More... | |
| #define | MFXSTM32L152_OUT_PIN_TYPE_PUSHPULL ((uint8_t)0x01) |
| #define | MFXSTM32L152_OUT_PIN_POLARITY_LOW ((uint8_t)0x00) |
| #define | MFXSTM32L152_OUT_PIN_POLARITY_HIGH ((uint8_t)0x02) |
| #define | MFXSTM32L152_IRQ_TS_OVF ((uint8_t)0x80) /* TouchScreen FIFO Overflow irq*/ |
| REG_ADR_IRQ_SRC_EN, REG_ADR_IRQ_PENDING & REG_ADR_IRQ_ACK choices. More... | |
| #define | MFXSTM32L152_IRQ_TS_FULL ((uint8_t)0x40) /* TouchScreen FIFO Full irq*/ |
| #define | MFXSTM32L152_IRQ_TS_TH ((uint8_t)0x20) /* TouchScreen FIFO threshold triggered irq*/ |
| #define | MFXSTM32L152_IRQ_TS_NE ((uint8_t)0x10) /* TouchScreen FIFO Not Empty irq*/ |
| #define | MFXSTM32L152_IRQ_TS_DET ((uint8_t)0x08) /* TouchScreen Detect irq*/ |
| #define | MFXSTM32L152_IRQ_ERROR ((uint8_t)0x04) /* Error message from MFXSTM32L152 firmware irq */ |
| #define | MFXSTM32L152_IRQ_IDD ((uint8_t)0x02) /* IDD function irq */ |
| #define | MFXSTM32L152_IRQ_GPIO ((uint8_t)0x01) /* General GPIO irq (only for SRC_EN and PENDING) */ |
| #define | MFXSTM32L152_IRQ_ALL ((uint8_t)0xFF) /* All global interrupts */ |
| #define | MFXSTM32L152_IRQ_TS (MFXSTM32L152_IRQ_TS_DET | MFXSTM32L152_IRQ_TS_NE | MFXSTM32L152_IRQ_TS_TH | MFXSTM32L152_IRQ_TS_FULL | MFXSTM32L152_IRQ_TS_OVF ) |
| #define | MFXSTM32L152_REG_ADR_GPIO_DIR1 ((uint8_t)0x60) /* gpio [0:7] */ |
| GPIO: 24 programmable input/output called MFXSTM32L152_GPIO[23:0] are provided. More... | |
| #define | MFXSTM32L152_REG_ADR_GPIO_DIR2 ((uint8_t)0x61) /* gpio [8:15] */ |
| #define | MFXSTM32L152_REG_ADR_GPIO_DIR3 ((uint8_t)0x62) /* agpio [0:7] */ |
| #define | MFXSTM32L152_REG_ADR_GPIO_TYPE1 ((uint8_t)0x64) /* gpio [0:7] */ |
| Reg addr: GPIO TYPE (R/W): If GPIO in output: (0) output push pull, (1) output open drain. If GPIO in input: (0) input without pull resistor, (1) input with pull resistor. More... | |
| #define | MFXSTM32L152_REG_ADR_GPIO_TYPE2 ((uint8_t)0x65) /* gpio [8:15] */ |
| #define | MFXSTM32L152_REG_ADR_GPIO_TYPE3 ((uint8_t)0x66) /* agpio [0:7] */ |
| #define | MFXSTM32L152_REG_ADR_GPIO_PUPD1 ((uint8_t)0x68) /* gpio [0:7] */ |
| Reg addr: GPIO PULL_UP_PULL_DOWN (R/W): discussion open with Jean Claude. More... | |
| #define | MFXSTM32L152_REG_ADR_GPIO_PUPD2 ((uint8_t)0x69) /* gpio [8:15] */ |
| #define | MFXSTM32L152_REG_ADR_GPIO_PUPD3 ((uint8_t)0x6A) /* agpio [0:7] */ |
| #define | MFXSTM32L152_REG_ADR_GPO_SET1 ((uint8_t)0x6C) /* gpio [0:7] */ |
| Reg addr: GPIO SET (W): When GPIO is in output mode, write (1) puts the corresponding GPO in High level. More... | |
| #define | MFXSTM32L152_REG_ADR_GPO_SET2 ((uint8_t)0x6D) /* gpio [8:15] */ |
| #define | MFXSTM32L152_REG_ADR_GPO_SET3 ((uint8_t)0x6E) /* agpio [0:7] */ |
| #define | MFXSTM32L152_REG_ADR_GPO_CLR1 ((uint8_t)0x70) /* gpio [0:7] */ |
| Reg addr: GPIO CLEAR (W): When GPIO is in output mode, write (1) puts the corresponding GPO in Low level. More... | |
| #define | MFXSTM32L152_REG_ADR_GPO_CLR2 ((uint8_t)0x71) /* gpio [8:15] */ |
| #define | MFXSTM32L152_REG_ADR_GPO_CLR3 ((uint8_t)0x72) /* agpio [0:7] */ |
| #define | MFXSTM32L152_REG_ADR_GPIO_STATE1 ((uint8_t)0x10) /* gpio [0:7] */ |
| Reg addr: GPIO STATE (R): Give state of the GPIO pin. More... | |
| #define | MFXSTM32L152_REG_ADR_GPIO_STATE2 ((uint8_t)0x11) /* gpio [8:15] */ |
| #define | MFXSTM32L152_REG_ADR_GPIO_STATE3 ((uint8_t)0x12) /* agpio [0:7] */ |
| #define | MFXSTM32L152_REG_ADR_IRQ_GPI_SRC1 ((uint8_t)0x48) /* gpio [0:7] */ |
| GPIO IRQ_GPIs. More... | |
| #define | MFXSTM32L152_REG_ADR_IRQ_GPI_SRC2 ((uint8_t)0x49) /* gpio [8:15] */ |
| #define | MFXSTM32L152_REG_ADR_IRQ_GPI_SRC3 ((uint8_t)0x4A) /* agpio [0:7] */ |
| #define | MFXSTM32L152_REG_ADR_IRQ_GPI_EVT1 ((uint8_t)0x4C) /* gpio [0:7] */ |
| GPIO IRQ_GPI_EVT1/2/3 (R/W): Irq generated on level (0) or edge (1). More... | |
| #define | MFXSTM32L152_REG_ADR_IRQ_GPI_EVT2 ((uint8_t)0x4D) /* gpio [8:15] */ |
| #define | MFXSTM32L152_REG_ADR_IRQ_GPI_EVT3 ((uint8_t)0x4E) /* agpio [0:7] */ |
| #define | MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE1 ((uint8_t)0x50) /* gpio [0:7] */ |
| GPIO IRQ_GPI_TYPE1/2/3 (R/W): Irq generated on (0) : Low level or Falling edge. (1) : High level or Rising edge. More... | |
| #define | MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE2 ((uint8_t)0x51) /* gpio [8:15] */ |
| #define | MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE3 ((uint8_t)0x52) /* agpio [0:7] */ |
| #define | MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING1 ((uint8_t)0x0C) /* gpio [0:7] */ |
| GPIO IRQ_GPI_PENDING1/2/3 (R): irq occurs. More... | |
| #define | MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING2 ((uint8_t)0x0D) /* gpio [8:15] */ |
| #define | MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING3 ((uint8_t)0x0E) /* agpio [0:7] */ |
| #define | MFXSTM32L152_REG_ADR_IRQ_GPI_ACK1 ((uint8_t)0x54) /* gpio [0:7] */ |
| GPIO IRQ_GPI_ACK1/2/3 (W): Write (1) to acknowledge IRQ event. More... | |
| #define | MFXSTM32L152_REG_ADR_IRQ_GPI_ACK2 ((uint8_t)0x55) /* gpio [8:15] */ |
| #define | MFXSTM32L152_REG_ADR_IRQ_GPI_ACK3 ((uint8_t)0x56) /* agpio [0:7] */ |
| #define | MFXSTM32L152_GPIO_PIN_0 ((uint32_t)0x0001) |
| GPIO: IO Pins definition. More... | |
| #define | MFXSTM32L152_GPIO_PIN_1 ((uint32_t)0x0002) |
| #define | MFXSTM32L152_GPIO_PIN_2 ((uint32_t)0x0004) |
| #define | MFXSTM32L152_GPIO_PIN_3 ((uint32_t)0x0008) |
| #define | MFXSTM32L152_GPIO_PIN_4 ((uint32_t)0x0010) |
| #define | MFXSTM32L152_GPIO_PIN_5 ((uint32_t)0x0020) |
| #define | MFXSTM32L152_GPIO_PIN_6 ((uint32_t)0x0040) |
| #define | MFXSTM32L152_GPIO_PIN_7 ((uint32_t)0x0080) |
| #define | MFXSTM32L152_GPIO_PIN_8 ((uint32_t)0x0100) |
| #define | MFXSTM32L152_GPIO_PIN_9 ((uint32_t)0x0200) |
| #define | MFXSTM32L152_GPIO_PIN_10 ((uint32_t)0x0400) |
| #define | MFXSTM32L152_GPIO_PIN_11 ((uint32_t)0x0800) |
| #define | MFXSTM32L152_GPIO_PIN_12 ((uint32_t)0x1000) |
| #define | MFXSTM32L152_GPIO_PIN_13 ((uint32_t)0x2000) |
| #define | MFXSTM32L152_GPIO_PIN_14 ((uint32_t)0x4000) |
| #define | MFXSTM32L152_GPIO_PIN_15 ((uint32_t)0x8000) |
| #define | MFXSTM32L152_GPIO_PIN_16 ((uint32_t)0x010000) |
| #define | MFXSTM32L152_GPIO_PIN_17 ((uint32_t)0x020000) |
| #define | MFXSTM32L152_GPIO_PIN_18 ((uint32_t)0x040000) |
| #define | MFXSTM32L152_GPIO_PIN_19 ((uint32_t)0x080000) |
| #define | MFXSTM32L152_GPIO_PIN_20 ((uint32_t)0x100000) |
| #define | MFXSTM32L152_GPIO_PIN_21 ((uint32_t)0x200000) |
| #define | MFXSTM32L152_GPIO_PIN_22 ((uint32_t)0x400000) |
| #define | MFXSTM32L152_GPIO_PIN_23 ((uint32_t)0x800000) |
| #define | MFXSTM32L152_AGPIO_PIN_0 MFXSTM32L152_GPIO_PIN_16 |
| #define | MFXSTM32L152_AGPIO_PIN_1 MFXSTM32L152_GPIO_PIN_17 |
| #define | MFXSTM32L152_AGPIO_PIN_2 MFXSTM32L152_GPIO_PIN_18 |
| #define | MFXSTM32L152_AGPIO_PIN_3 MFXSTM32L152_GPIO_PIN_19 |
| #define | MFXSTM32L152_AGPIO_PIN_4 MFXSTM32L152_GPIO_PIN_20 |
| #define | MFXSTM32L152_AGPIO_PIN_5 MFXSTM32L152_GPIO_PIN_21 |
| #define | MFXSTM32L152_AGPIO_PIN_6 MFXSTM32L152_GPIO_PIN_22 |
| #define | MFXSTM32L152_AGPIO_PIN_7 MFXSTM32L152_GPIO_PIN_23 |
| #define | MFXSTM32L152_GPIO_PINS_ALL ((uint32_t)0xFFFFFF) |
| #define | MFXSTM32L152_GPIO_DIR_IN ((uint8_t)0x0) |
| GPIO: constant. More... | |
| #define | MFXSTM32L152_GPIO_DIR_OUT ((uint8_t)0x1) |
| #define | MFXSTM32L152_IRQ_GPI_EVT_LEVEL ((uint8_t)0x0) |
| #define | MFXSTM32L152_IRQ_GPI_EVT_EDGE ((uint8_t)0x1) |
| #define | MFXSTM32L152_IRQ_GPI_TYPE_LLFE ((uint8_t)0x0) /* Low Level Falling Edge */ |
| #define | MFXSTM32L152_IRQ_GPI_TYPE_HLRE ((uint8_t)0x1) /*High Level Raising Edge */ |
| #define | MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR ((uint8_t)0x0) |
| #define | MFXSTM32L152_GPI_WITH_PULL_RESISTOR ((uint8_t)0x1) |
| #define | MFXSTM32L152_GPO_PUSH_PULL ((uint8_t)0x0) |
| #define | MFXSTM32L152_GPO_OPEN_DRAIN ((uint8_t)0x1) |
| #define | MFXSTM32L152_GPIO_PULL_DOWN ((uint8_t)0x0) |
| #define | MFXSTM32L152_GPIO_PULL_UP ((uint8_t)0x1) |
| #define | MFXSTM32L152_TS_SETTLING ((uint8_t)0xA0) |
| TOUCH SCREEN Registers. More... | |
| #define | MFXSTM32L152_TS_TOUCH_DET_DELAY ((uint8_t)0xA1) |
| #define | MFXSTM32L152_TS_AVE ((uint8_t)0xA2) |
| #define | MFXSTM32L152_TS_TRACK ((uint8_t)0xA3) |
| #define | MFXSTM32L152_TS_FIFO_TH ((uint8_t)0xA4) |
| #define | MFXSTM32L152_TS_FIFO_STA ((uint8_t)0x20) |
| #define | MFXSTM32L152_TS_FIFO_LEVEL ((uint8_t)0x21) |
| #define | MFXSTM32L152_TS_XY_DATA ((uint8_t)0x24) |
| #define | MFXSTM32L152_TS_CTRL_STATUS ((uint8_t)0x08) |
| TS registers masks. More... | |
| #define | MFXSTM32L152_TS_CLEAR_FIFO ((uint8_t)0x80) |
| #define | MFXSTM32L152_REG_ADR_IDD_CTRL ((uint8_t)0x80) |
| Register address: Idd control register (R/W) More... | |
| #define | MFXSTM32L152_REG_ADR_IDD_PRE_DELAY ((uint8_t)0x81) |
| Register address: Idd pre delay register (R/W) More... | |
| #define | MFXSTM32L152_REG_ADR_IDD_SHUNT0_MSB ((uint8_t)0x82) |
| Register address: Idd Shunt registers (R/W) More... | |
| #define | MFXSTM32L152_REG_ADR_IDD_SHUNT0_LSB ((uint8_t)0x83) |
| #define | MFXSTM32L152_REG_ADR_IDD_SHUNT1_MSB ((uint8_t)0x84) |
| #define | MFXSTM32L152_REG_ADR_IDD_SHUNT1_LSB ((uint8_t)0x85) |
| #define | MFXSTM32L152_REG_ADR_IDD_SHUNT2_MSB ((uint8_t)0x86) |
| #define | MFXSTM32L152_REG_ADR_IDD_SHUNT2_LSB ((uint8_t)0x87) |
| #define | MFXSTM32L152_REG_ADR_IDD_SHUNT3_MSB ((uint8_t)0x88) |
| #define | MFXSTM32L152_REG_ADR_IDD_SHUNT3_LSB ((uint8_t)0x89) |
| #define | MFXSTM32L152_REG_ADR_IDD_SHUNT4_MSB ((uint8_t)0x8A) |
| #define | MFXSTM32L152_REG_ADR_IDD_SHUNT4_LSB ((uint8_t)0x8B) |
| #define | MFXSTM32L152_REG_ADR_IDD_GAIN_MSB ((uint8_t)0x8C) |
| Register address: Idd ampli gain register (R/W) More... | |
| #define | MFXSTM32L152_REG_ADR_IDD_GAIN_LSB ((uint8_t)0x8D) |
| #define | MFXSTM32L152_REG_ADR_IDD_VDD_MIN_MSB ((uint8_t)0x8E) |
| Register address: Idd VDD min register (R/W) More... | |
| #define | MFXSTM32L152_REG_ADR_IDD_VDD_MIN_LSB ((uint8_t)0x8F) |
| #define | MFXSTM32L152_REG_ADR_IDD_VALUE_MSB ((uint8_t)0x14) |
| Register address: Idd value register (R) More... | |
| #define | MFXSTM32L152_REG_ADR_IDD_VALUE_MID ((uint8_t)0x15) |
| #define | MFXSTM32L152_REG_ADR_IDD_VALUE_LSB ((uint8_t)0x16) |
| #define | MFXSTM32L152_REG_ADR_IDD_CAL_OFFSET_MSB ((uint8_t)0x18) |
| Register address: Idd calibration offset register (R) More... | |
| #define | MFXSTM32L152_REG_ADR_IDD_CAL_OFFSET_LSB ((uint8_t)0x19) |
| #define | MFXSTM32L152_REG_ADR_IDD_SHUNT_USED ((uint8_t)0x1A) |
| Register address: Idd shunt used offset register (R) More... | |
| #define | MFXSTM32L152_REG_ADR_IDD_SH0_STABILIZATION ((uint8_t)0x90) |
| Register address: shunt stabilisation delay registers (R/W) More... | |
| #define | MFXSTM32L152_REG_ADR_IDD_SH1_STABILIZATION ((uint8_t)0x91) |
| #define | MFXSTM32L152_REG_ADR_IDD_SH2_STABILIZATION ((uint8_t)0x92) |
| #define | MFXSTM32L152_REG_ADR_IDD_SH3_STABILIZATION ((uint8_t)0x93) |
| #define | MFXSTM32L152_REG_ADR_IDD_SH4_STABILIZATION ((uint8_t)0x94) |
| #define | MFXSTM32L152_REG_ADR_IDD_NBR_OF_MEAS ((uint8_t)0x96) |
| Register address: Idd number of measurements register (R/W) More... | |
| #define | MFXSTM32L152_REG_ADR_IDD_MEAS_DELTA_DELAY ((uint8_t)0x97) |
| Register address: Idd delta delay between 2 measurements register (R/W) More... | |
| #define | MFXSTM32L152_REG_ADR_IDD_SHUNTS_ON_BOARD ((uint8_t)0x98) |
| Register address: Idd number of shunt on board register (R/W) More... | |
| #define MFXSTM32L152_AGPIO_PIN_0 MFXSTM32L152_GPIO_PIN_16 |
Definition at line 314 of file mfxstm32l152.h.
| #define MFXSTM32L152_AGPIO_PIN_1 MFXSTM32L152_GPIO_PIN_17 |
Definition at line 315 of file mfxstm32l152.h.
| #define MFXSTM32L152_AGPIO_PIN_2 MFXSTM32L152_GPIO_PIN_18 |
Definition at line 316 of file mfxstm32l152.h.
| #define MFXSTM32L152_AGPIO_PIN_3 MFXSTM32L152_GPIO_PIN_19 |
Definition at line 317 of file mfxstm32l152.h.
| #define MFXSTM32L152_AGPIO_PIN_4 MFXSTM32L152_GPIO_PIN_20 |
Definition at line 318 of file mfxstm32l152.h.
| #define MFXSTM32L152_AGPIO_PIN_5 MFXSTM32L152_GPIO_PIN_21 |
Definition at line 319 of file mfxstm32l152.h.
| #define MFXSTM32L152_AGPIO_PIN_6 MFXSTM32L152_GPIO_PIN_22 |
Definition at line 320 of file mfxstm32l152.h.
| #define MFXSTM32L152_AGPIO_PIN_7 MFXSTM32L152_GPIO_PIN_23 |
Definition at line 321 of file mfxstm32l152.h.
| #define MFXSTM32L152_ALTERNATE_GPIO_EN ((uint8_t)0x08) /* by the way if IDD and TS are enabled they take automatically the AF pins*/ |
Definition at line 170 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPI_WITH_PULL_RESISTOR ((uint8_t)0x1) |
Definition at line 335 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR ((uint8_t)0x0) |
Definition at line 334 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_DIR_IN ((uint8_t)0x0) |
GPIO: constant.
Definition at line 328 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_DIR_OUT ((uint8_t)0x1) |
Definition at line 329 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_EN ((uint8_t)0x01) |
Definition at line 173 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_ERROR_SRC ((uint8_t)0x01) /* Error raised by Gpio */ |
Definition at line 180 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_PIN_0 ((uint32_t)0x0001) |
GPIO: IO Pins definition.
Definition at line 287 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_PIN_1 ((uint32_t)0x0002) |
Definition at line 288 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_PIN_10 ((uint32_t)0x0400) |
Definition at line 298 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_PIN_11 ((uint32_t)0x0800) |
Definition at line 299 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_PIN_12 ((uint32_t)0x1000) |
Definition at line 300 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_PIN_13 ((uint32_t)0x2000) |
Definition at line 301 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_PIN_14 ((uint32_t)0x4000) |
Definition at line 302 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_PIN_15 ((uint32_t)0x8000) |
Definition at line 303 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_PIN_16 ((uint32_t)0x010000) |
Definition at line 305 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_PIN_17 ((uint32_t)0x020000) |
Definition at line 306 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_PIN_18 ((uint32_t)0x040000) |
Definition at line 307 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_PIN_19 ((uint32_t)0x080000) |
Definition at line 308 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_PIN_2 ((uint32_t)0x0004) |
Definition at line 289 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_PIN_20 ((uint32_t)0x100000) |
Definition at line 309 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_PIN_21 ((uint32_t)0x200000) |
Definition at line 310 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_PIN_22 ((uint32_t)0x400000) |
Definition at line 311 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_PIN_23 ((uint32_t)0x800000) |
Definition at line 312 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_PIN_3 ((uint32_t)0x0008) |
Definition at line 290 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_PIN_4 ((uint32_t)0x0010) |
Definition at line 291 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_PIN_5 ((uint32_t)0x0020) |
Definition at line 292 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_PIN_6 ((uint32_t)0x0040) |
Definition at line 293 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_PIN_7 ((uint32_t)0x0080) |
Definition at line 294 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_PIN_8 ((uint32_t)0x0100) |
Definition at line 296 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_PIN_9 ((uint32_t)0x0200) |
Definition at line 297 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_PINS_ALL ((uint32_t)0xFFFFFF) |
Definition at line 323 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_PULL_DOWN ((uint8_t)0x0) |
Definition at line 338 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPIO_PULL_UP ((uint8_t)0x1) |
Definition at line 339 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPO_OPEN_DRAIN ((uint8_t)0x1) |
Definition at line 337 of file mfxstm32l152.h.
| #define MFXSTM32L152_GPO_PUSH_PULL ((uint8_t)0x0) |
Definition at line 336 of file mfxstm32l152.h.
| #define MFXSTM32L152_ID_1 ((uint8_t)0x7B) |
MFXSTM32L152_REG_ADR_ID choices.
Definition at line 162 of file mfxstm32l152.h.
| #define MFXSTM32L152_ID_2 ((uint8_t)0x79) |
Definition at line 163 of file mfxstm32l152.h.
| #define MFXSTM32L152_IDD_EN ((uint8_t)0x04) |
Definition at line 171 of file mfxstm32l152.h.
| #define MFXSTM32L152_IDD_ERROR_SRC ((uint8_t)0x04) /* Error raised by Idd */ |
MFXSTM32L152_REG_ADR_ERROR_SRC choices.
Definition at line 178 of file mfxstm32l152.h.
| #define MFXSTM32L152_IRQ_ALL ((uint8_t)0xFF) /* All global interrupts */ |
Definition at line 201 of file mfxstm32l152.h.
| #define MFXSTM32L152_IRQ_ERROR ((uint8_t)0x04) /* Error message from MFXSTM32L152 firmware irq */ |
Definition at line 198 of file mfxstm32l152.h.
| #define MFXSTM32L152_IRQ_GPI_EVT_EDGE ((uint8_t)0x1) |
Definition at line 331 of file mfxstm32l152.h.
| #define MFXSTM32L152_IRQ_GPI_EVT_LEVEL ((uint8_t)0x0) |
Definition at line 330 of file mfxstm32l152.h.
| #define MFXSTM32L152_IRQ_GPI_TYPE_HLRE ((uint8_t)0x1) /*High Level Raising Edge */ |
Definition at line 333 of file mfxstm32l152.h.
| #define MFXSTM32L152_IRQ_GPI_TYPE_LLFE ((uint8_t)0x0) /* Low Level Falling Edge */ |
Definition at line 332 of file mfxstm32l152.h.
| #define MFXSTM32L152_IRQ_GPIO ((uint8_t)0x01) /* General GPIO irq (only for SRC_EN and PENDING) */ |
Definition at line 200 of file mfxstm32l152.h.
| #define MFXSTM32L152_IRQ_IDD ((uint8_t)0x02) /* IDD function irq */ |
Definition at line 199 of file mfxstm32l152.h.
| #define MFXSTM32L152_IRQ_TS (MFXSTM32L152_IRQ_TS_DET | MFXSTM32L152_IRQ_TS_NE | MFXSTM32L152_IRQ_TS_TH | MFXSTM32L152_IRQ_TS_FULL | MFXSTM32L152_IRQ_TS_OVF ) |
Definition at line 202 of file mfxstm32l152.h.
| #define MFXSTM32L152_IRQ_TS_DET ((uint8_t)0x08) /* TouchScreen Detect irq*/ |
Definition at line 197 of file mfxstm32l152.h.
| #define MFXSTM32L152_IRQ_TS_FULL ((uint8_t)0x40) /* TouchScreen FIFO Full irq*/ |
Definition at line 194 of file mfxstm32l152.h.
| #define MFXSTM32L152_IRQ_TS_NE ((uint8_t)0x10) /* TouchScreen FIFO Not Empty irq*/ |
Definition at line 196 of file mfxstm32l152.h.
| #define MFXSTM32L152_IRQ_TS_OVF ((uint8_t)0x80) /* TouchScreen FIFO Overflow irq*/ |
REG_ADR_IRQ_SRC_EN, REG_ADR_IRQ_PENDING & REG_ADR_IRQ_ACK choices.
Definition at line 193 of file mfxstm32l152.h.
| #define MFXSTM32L152_IRQ_TS_TH ((uint8_t)0x20) /* TouchScreen FIFO threshold triggered irq*/ |
Definition at line 195 of file mfxstm32l152.h.
| #define MFXSTM32L152_OUT_PIN_POLARITY_HIGH ((uint8_t)0x02) |
Definition at line 188 of file mfxstm32l152.h.
| #define MFXSTM32L152_OUT_PIN_POLARITY_LOW ((uint8_t)0x00) |
Definition at line 187 of file mfxstm32l152.h.
| #define MFXSTM32L152_OUT_PIN_TYPE_OPENDRAIN ((uint8_t)0x00) |
MFXSTM32L152_REG_ADR_MFX_IRQ_OUT choices.
Definition at line 185 of file mfxstm32l152.h.
| #define MFXSTM32L152_OUT_PIN_TYPE_PUSHPULL ((uint8_t)0x01) |
Definition at line 186 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_ERROR_MSG ((uint8_t)0x04) |
Register address: Error Message.
Definition at line 140 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_ERROR_SRC ((uint8_t)0x03) |
Register address: Error source.
Definition at line 136 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_FW_VERSION_LSB ((uint8_t)0x00) |
Definition at line 123 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_FW_VERSION_MSB ((uint8_t)0x01) |
Register address: chip FW_VERSION (R)
Definition at line 122 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_GPIO_DIR1 ((uint8_t)0x60) /* gpio [0:7] */ |
GPIO: 24 programmable input/output called MFXSTM32L152_GPIO[23:0] are provided.
Reg addr: GPIO DIRECTION (R/W): GPIO pins direction: (0) input, (1) output.
Definition at line 212 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_GPIO_DIR2 ((uint8_t)0x61) /* gpio [8:15] */ |
Definition at line 213 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_GPIO_DIR3 ((uint8_t)0x62) /* agpio [0:7] */ |
Definition at line 214 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_GPIO_PUPD1 ((uint8_t)0x68) /* gpio [0:7] */ |
Reg addr: GPIO PULL_UP_PULL_DOWN (R/W): discussion open with Jean Claude.
Definition at line 225 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_GPIO_PUPD2 ((uint8_t)0x69) /* gpio [8:15] */ |
Definition at line 226 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_GPIO_PUPD3 ((uint8_t)0x6A) /* agpio [0:7] */ |
Definition at line 227 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_GPIO_STATE1 ((uint8_t)0x10) /* gpio [0:7] */ |
Reg addr: GPIO STATE (R): Give state of the GPIO pin.
Definition at line 243 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_GPIO_STATE2 ((uint8_t)0x11) /* gpio [8:15] */ |
Definition at line 244 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_GPIO_STATE3 ((uint8_t)0x12) /* agpio [0:7] */ |
Definition at line 245 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_GPIO_TYPE1 ((uint8_t)0x64) /* gpio [0:7] */ |
Reg addr: GPIO TYPE (R/W): If GPIO in output: (0) output push pull, (1) output open drain. If GPIO in input: (0) input without pull resistor, (1) input with pull resistor.
Definition at line 219 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_GPIO_TYPE2 ((uint8_t)0x65) /* gpio [8:15] */ |
Definition at line 220 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_GPIO_TYPE3 ((uint8_t)0x66) /* agpio [0:7] */ |
Definition at line 221 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_GPO_CLR1 ((uint8_t)0x70) /* gpio [0:7] */ |
Reg addr: GPIO CLEAR (W): When GPIO is in output mode, write (1) puts the corresponding GPO in Low level.
Definition at line 237 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_GPO_CLR2 ((uint8_t)0x71) /* gpio [8:15] */ |
Definition at line 238 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_GPO_CLR3 ((uint8_t)0x72) /* agpio [0:7] */ |
Definition at line 239 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_GPO_SET1 ((uint8_t)0x6C) /* gpio [0:7] */ |
Reg addr: GPIO SET (W): When GPIO is in output mode, write (1) puts the corresponding GPO in High level.
Definition at line 231 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_GPO_SET2 ((uint8_t)0x6D) /* gpio [8:15] */ |
Definition at line 232 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_GPO_SET3 ((uint8_t)0x6E) /* agpio [0:7] */ |
Definition at line 233 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_ID ((uint8_t)0x00) |
| #define MFXSTM32L152_REG_ADR_IDD_CAL_OFFSET_LSB ((uint8_t)0x19) |
Definition at line 412 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IDD_CAL_OFFSET_MSB ((uint8_t)0x18) |
Register address: Idd calibration offset register (R)
Definition at line 411 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IDD_CTRL ((uint8_t)0x80) |
Register address: Idd control register (R/W)
Definition at line 368 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IDD_GAIN_LSB ((uint8_t)0x8D) |
Definition at line 393 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IDD_GAIN_MSB ((uint8_t)0x8C) |
Register address: Idd ampli gain register (R/W)
Definition at line 392 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IDD_MEAS_DELTA_DELAY ((uint8_t)0x97) |
Register address: Idd delta delay between 2 measurements register (R/W)
Definition at line 436 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IDD_NBR_OF_MEAS ((uint8_t)0x96) |
Register address: Idd number of measurements register (R/W)
Definition at line 431 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IDD_PRE_DELAY ((uint8_t)0x81) |
Register address: Idd pre delay register (R/W)
Definition at line 373 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IDD_SH0_STABILIZATION ((uint8_t)0x90) |
Register address: shunt stabilisation delay registers (R/W)
Definition at line 422 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IDD_SH1_STABILIZATION ((uint8_t)0x91) |
Definition at line 423 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IDD_SH2_STABILIZATION ((uint8_t)0x92) |
Definition at line 424 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IDD_SH3_STABILIZATION ((uint8_t)0x93) |
Definition at line 425 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IDD_SH4_STABILIZATION ((uint8_t)0x94) |
Definition at line 426 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IDD_SHUNT0_LSB ((uint8_t)0x83) |
Definition at line 379 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IDD_SHUNT0_MSB ((uint8_t)0x82) |
Register address: Idd Shunt registers (R/W)
Definition at line 378 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IDD_SHUNT1_LSB ((uint8_t)0x85) |
Definition at line 381 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IDD_SHUNT1_MSB ((uint8_t)0x84) |
Definition at line 380 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IDD_SHUNT2_LSB ((uint8_t)0x87) |
Definition at line 383 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IDD_SHUNT2_MSB ((uint8_t)0x86) |
Definition at line 382 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IDD_SHUNT3_LSB ((uint8_t)0x89) |
Definition at line 385 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IDD_SHUNT3_MSB ((uint8_t)0x88) |
Definition at line 384 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IDD_SHUNT4_LSB ((uint8_t)0x8B) |
Definition at line 387 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IDD_SHUNT4_MSB ((uint8_t)0x8A) |
Definition at line 386 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IDD_SHUNT_USED ((uint8_t)0x1A) |
Register address: Idd shunt used offset register (R)
Definition at line 417 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IDD_SHUNTS_ON_BOARD ((uint8_t)0x98) |
Register address: Idd number of shunt on board register (R/W)
Definition at line 441 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IDD_VALUE_LSB ((uint8_t)0x16) |
Definition at line 406 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IDD_VALUE_MID ((uint8_t)0x15) |
Definition at line 405 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IDD_VALUE_MSB ((uint8_t)0x14) |
Register address: Idd value register (R)
Definition at line 404 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IDD_VDD_MIN_LSB ((uint8_t)0x8F) |
Definition at line 399 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IDD_VDD_MIN_MSB ((uint8_t)0x8E) |
Register address: Idd VDD min register (R/W)
Definition at line 398 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IRQ_ACK ((uint8_t)0x44) |
Reg Addr IRQs: the Main MCU must acknowledge it thanks to a writing access to the IRQ_ACK register.
Definition at line 157 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IRQ_GPI_ACK1 ((uint8_t)0x54) /* gpio [0:7] */ |
GPIO IRQ_GPI_ACK1/2/3 (W): Write (1) to acknowledge IRQ event.
Definition at line 279 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IRQ_GPI_ACK2 ((uint8_t)0x55) /* gpio [8:15] */ |
Definition at line 280 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IRQ_GPI_ACK3 ((uint8_t)0x56) /* agpio [0:7] */ |
Definition at line 281 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IRQ_GPI_EVT1 ((uint8_t)0x4C) /* gpio [0:7] */ |
GPIO IRQ_GPI_EVT1/2/3 (R/W): Irq generated on level (0) or edge (1).
Definition at line 261 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IRQ_GPI_EVT2 ((uint8_t)0x4D) /* gpio [8:15] */ |
Definition at line 262 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IRQ_GPI_EVT3 ((uint8_t)0x4E) /* agpio [0:7] */ |
Definition at line 263 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING1 ((uint8_t)0x0C) /* gpio [0:7] */ |
GPIO IRQ_GPI_PENDING1/2/3 (R): irq occurs.
Definition at line 273 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING2 ((uint8_t)0x0D) /* gpio [8:15] */ |
Definition at line 274 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING3 ((uint8_t)0x0E) /* agpio [0:7] */ |
Definition at line 275 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IRQ_GPI_SRC1 ((uint8_t)0x48) /* gpio [0:7] */ |
GPIO IRQ_GPIs.
GPIO IRQ_GPI_SRC1/2/3 (R/W): registers enable or not the feature to generate irq
Definition at line 255 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IRQ_GPI_SRC2 ((uint8_t)0x49) /* gpio [8:15] */ |
Definition at line 256 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IRQ_GPI_SRC3 ((uint8_t)0x4A) /* agpio [0:7] */ |
Definition at line 257 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE1 ((uint8_t)0x50) /* gpio [0:7] */ |
GPIO IRQ_GPI_TYPE1/2/3 (R/W): Irq generated on (0) : Low level or Falling edge. (1) : High level or Rising edge.
Definition at line 267 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE2 ((uint8_t)0x51) /* gpio [8:15] */ |
Definition at line 268 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE3 ((uint8_t)0x52) /* agpio [0:7] */ |
Definition at line 269 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IRQ_PENDING ((uint8_t)0x08) |
Reg Addr IRQs: the Main MCU must read the IRQ_PENDING register to know the interrupt reason.
Definition at line 153 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_IRQ_SRC_EN ((uint8_t)0x42) |
Reg Addr IRQs: to select the events which activate the MFXSTM32L152_IRQ_OUT signal.
Definition at line 149 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_MFX_IRQ_OUT ((uint8_t)0x41) |
Reg Addr IRQs: to config the pin that informs Main MCU that MFX events appear.
Definition at line 145 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_SYS_CTRL ((uint8_t)0x40) |
Register address: System Control Register (R/W)
Definition at line 127 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_VDD_REF_LSB ((uint8_t)0x07) |
Definition at line 132 of file mfxstm32l152.h.
| #define MFXSTM32L152_REG_ADR_VDD_REF_MSB ((uint8_t)0x06) |
Register address: Vdd monitoring (R)
Definition at line 131 of file mfxstm32l152.h.
| #define MFXSTM32L152_STANDBY ((uint8_t)0x40) |
Definition at line 169 of file mfxstm32l152.h.
| #define MFXSTM32L152_SWRST ((uint8_t)0x80) |
MFXSTM32L152_REG_ADR_SYS_CTRL choices.
Definition at line 168 of file mfxstm32l152.h.
| #define MFXSTM32L152_TS_AVE ((uint8_t)0xA2) |
Definition at line 351 of file mfxstm32l152.h.
| #define MFXSTM32L152_TS_CLEAR_FIFO ((uint8_t)0x80) |
Definition at line 362 of file mfxstm32l152.h.
| #define MFXSTM32L152_TS_CTRL_STATUS ((uint8_t)0x08) |
TS registers masks.
Definition at line 361 of file mfxstm32l152.h.
| #define MFXSTM32L152_TS_EN ((uint8_t)0x02) |
Definition at line 172 of file mfxstm32l152.h.
| #define MFXSTM32L152_TS_ERROR_SRC ((uint8_t)0x02) /* Error raised by Touch Screen */ |
Definition at line 179 of file mfxstm32l152.h.
| #define MFXSTM32L152_TS_FIFO_LEVEL ((uint8_t)0x21) |
Definition at line 355 of file mfxstm32l152.h.
| #define MFXSTM32L152_TS_FIFO_STA ((uint8_t)0x20) |
Definition at line 354 of file mfxstm32l152.h.
| #define MFXSTM32L152_TS_FIFO_TH ((uint8_t)0xA4) |
Definition at line 353 of file mfxstm32l152.h.
| #define MFXSTM32L152_TS_SETTLING ((uint8_t)0xA0) |
| #define MFXSTM32L152_TS_TOUCH_DET_DELAY ((uint8_t)0xA1) |
Definition at line 350 of file mfxstm32l152.h.
| #define MFXSTM32L152_TS_TRACK ((uint8_t)0xA3) |
Definition at line 352 of file mfxstm32l152.h.
| #define MFXSTM32L152_TS_XY_DATA ((uint8_t)0x24) |
Definition at line 356 of file mfxstm32l152.h.
1.8.11
