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STM32F769IDiscovery
1.00
uDANTE Audio Networking with STM32F7 DISCO board
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STM32F769IDiscovery
1.00
uDANTE Audio Networking with STM32F7 DISCO board
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Macros | |
| #define | VLAN_TAG ETH_VLAN_TAG |
| #define | MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD |
| #define | MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD |
| #define | JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD |
| #define | MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK |
| #define | MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK |
| #define | MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK |
| #define | DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK |
| #define | ETH_MMCCR ((uint32_t)0x00000100U) |
| #define | ETH_MMCRIR ((uint32_t)0x00000104U) |
| #define | ETH_MMCTIR ((uint32_t)0x00000108U) |
| #define | ETH_MMCRIMR ((uint32_t)0x0000010CU) |
| #define | ETH_MMCTIMR ((uint32_t)0x00000110U) |
| #define | ETH_MMCTGFSCCR ((uint32_t)0x0000014CU) |
| #define | ETH_MMCTGFMSCCR ((uint32_t)0x00000150U) |
| #define | ETH_MMCTGFCR ((uint32_t)0x00000168U) |
| #define | ETH_MMCRFCECR ((uint32_t)0x00000194U) |
| #define | ETH_MMCRFAECR ((uint32_t)0x00000198U) |
| #define | ETH_MMCRGUFCR ((uint32_t)0x000001C4U) |
| #define | ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */ |
| #define | ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */ |
| #define | ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */ |
| #define | ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */ |
| #define | ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ |
| #define | ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ |
| #define | ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ |
| #define | ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */ |
| #define | ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */ |
| #define | ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ |
| #define | ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ |
| #define | ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */ |
| #define | ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */ |
| #define | ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */ |
| #define | ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ |
| #define | ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */ |
| #define | ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */ |
| #define | ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */ |
| #define | ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */ |
| #define | ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */ |
| #define | ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */ |
| #define | ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */ |
| #define | ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */ |
| #define | ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */ |
| #define | ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */ |
| #define | ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */ |
| #define | ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */ |
| #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK |
Definition at line 903 of file stm32_hal_legacy.h.
| #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */ |
Definition at line 946 of file stm32_hal_legacy.h.
| #define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */ |
Definition at line 929 of file stm32_hal_legacy.h.
| #define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */ |
Definition at line 940 of file stm32_hal_legacy.h.
| #define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */ |
Definition at line 936 of file stm32_hal_legacy.h.
| #define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */ |
Definition at line 937 of file stm32_hal_legacy.h.
| #define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */ |
Definition at line 938 of file stm32_hal_legacy.h.
| #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */ |
Definition at line 932 of file stm32_hal_legacy.h.
| #define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ |
Definition at line 931 of file stm32_hal_legacy.h.
| #define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */ |
Definition at line 930 of file stm32_hal_legacy.h.
| #define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */ |
Definition at line 933 of file stm32_hal_legacy.h.
| #define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */ |
Definition at line 941 of file stm32_hal_legacy.h.
| #define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */ |
Definition at line 942 of file stm32_hal_legacy.h.
| #define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */ |
Definition at line 943 of file stm32_hal_legacy.h.
| #define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */ |
Definition at line 945 of file stm32_hal_legacy.h.
| #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */ |
Definition at line 944 of file stm32_hal_legacy.h.
| #define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */ |
Definition at line 924 of file stm32_hal_legacy.h.
| #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ |
Definition at line 927 of file stm32_hal_legacy.h.
| #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */ |
Definition at line 925 of file stm32_hal_legacy.h.
| #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */ |
Definition at line 928 of file stm32_hal_legacy.h.
| #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ |
Definition at line 926 of file stm32_hal_legacy.h.
| #define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */ |
Definition at line 917 of file stm32_hal_legacy.h.
| #define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */ |
Definition at line 920 of file stm32_hal_legacy.h.
| #define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ |
Definition at line 921 of file stm32_hal_legacy.h.
| #define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ |
Definition at line 922 of file stm32_hal_legacy.h.
| #define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */ |
Definition at line 919 of file stm32_hal_legacy.h.
| #define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ |
Definition at line 923 of file stm32_hal_legacy.h.
| #define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */ |
Definition at line 918 of file stm32_hal_legacy.h.
| #define ETH_MMCCR ((uint32_t)0x00000100U) |
Definition at line 905 of file stm32_hal_legacy.h.
| #define ETH_MMCRFAECR ((uint32_t)0x00000198U) |
Definition at line 914 of file stm32_hal_legacy.h.
| #define ETH_MMCRFCECR ((uint32_t)0x00000194U) |
Definition at line 913 of file stm32_hal_legacy.h.
| #define ETH_MMCRGUFCR ((uint32_t)0x000001C4U) |
Definition at line 915 of file stm32_hal_legacy.h.
| #define ETH_MMCRIMR ((uint32_t)0x0000010CU) |
Definition at line 908 of file stm32_hal_legacy.h.
| #define ETH_MMCRIR ((uint32_t)0x00000104U) |
Definition at line 906 of file stm32_hal_legacy.h.
| #define ETH_MMCTGFCR ((uint32_t)0x00000168U) |
Definition at line 912 of file stm32_hal_legacy.h.
| #define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U) |
Definition at line 911 of file stm32_hal_legacy.h.
| #define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU) |
Definition at line 910 of file stm32_hal_legacy.h.
| #define ETH_MMCTIMR ((uint32_t)0x00000110U) |
Definition at line 909 of file stm32_hal_legacy.h.
| #define ETH_MMCTIR ((uint32_t)0x00000108U) |
Definition at line 907 of file stm32_hal_legacy.h.
| #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD |
Definition at line 899 of file stm32_hal_legacy.h.
| #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK |
Definition at line 901 of file stm32_hal_legacy.h.
| #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK |
Definition at line 902 of file stm32_hal_legacy.h.
| #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK |
Definition at line 900 of file stm32_hal_legacy.h.
| #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD |
Definition at line 898 of file stm32_hal_legacy.h.
| #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD |
Definition at line 897 of file stm32_hal_legacy.h.
| #define VLAN_TAG ETH_VLAN_TAG |
Definition at line 896 of file stm32_hal_legacy.h.
1.8.11
